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b305a080 WYG |
1 | /****************************************************************************** |
2 | * | |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
5 | * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/sched.h> | |
34 | ||
35 | #include "iwl-dev.h" | |
36 | #include "iwl-core.h" | |
37 | #include "iwl-sta.h" | |
38 | #include "iwl-io.h" | |
74bcdb33 | 39 | #include "iwl-helpers.h" |
19e6cda0 | 40 | #include "iwl-agn-hw.h" |
8d801080 | 41 | #include "iwl-agn.h" |
b305a080 | 42 | |
74bcdb33 WYG |
43 | /* |
44 | * mac80211 queues, ACs, hardware queues, FIFOs. | |
45 | * | |
46 | * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues | |
47 | * | |
48 | * Mac80211 uses the following numbers, which we get as from it | |
49 | * by way of skb_get_queue_mapping(skb): | |
50 | * | |
51 | * VO 0 | |
52 | * VI 1 | |
53 | * BE 2 | |
54 | * BK 3 | |
55 | * | |
56 | * | |
57 | * Regular (not A-MPDU) frames are put into hardware queues corresponding | |
58 | * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their | |
59 | * own queue per aggregation session (RA/TID combination), such queues are | |
60 | * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In | |
61 | * order to map frames to the right queue, we also need an AC->hw queue | |
62 | * mapping. This is implemented here. | |
63 | * | |
64 | * Due to the way hw queues are set up (by the hw specific modules like | |
65 | * iwl-4965.c, iwl-5000.c etc.), the AC->hw queue mapping is the identity | |
66 | * mapping. | |
67 | */ | |
68 | ||
69 | static const u8 tid_to_ac[] = { | |
70 | /* this matches the mac80211 numbers */ | |
71 | 2, 3, 3, 2, 1, 1, 0, 0 | |
72 | }; | |
73 | ||
c2845d01 SZ |
74 | static inline int get_ac_from_tid(u16 tid) |
75 | { | |
76 | if (likely(tid < ARRAY_SIZE(tid_to_ac))) | |
77 | return tid_to_ac[tid]; | |
78 | ||
79 | /* no support for TIDs 8-15 yet */ | |
80 | return -EINVAL; | |
81 | } | |
82 | ||
e72f368b | 83 | static inline int get_fifo_from_tid(struct iwl_rxon_context *ctx, u16 tid) |
74bcdb33 WYG |
84 | { |
85 | if (likely(tid < ARRAY_SIZE(tid_to_ac))) | |
e72f368b | 86 | return ctx->ac_to_fifo[tid_to_ac[tid]]; |
74bcdb33 WYG |
87 | |
88 | /* no support for TIDs 8-15 yet */ | |
89 | return -EINVAL; | |
90 | } | |
91 | ||
b305a080 WYG |
92 | /** |
93 | * iwlagn_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
94 | */ | |
95 | void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv, | |
96 | struct iwl_tx_queue *txq, | |
97 | u16 byte_cnt) | |
98 | { | |
19e6cda0 | 99 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
b305a080 WYG |
100 | int write_ptr = txq->q.write_ptr; |
101 | int txq_id = txq->q.id; | |
102 | u8 sec_ctl = 0; | |
103 | u8 sta_id = 0; | |
104 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
105 | __le16 bc_ent; | |
106 | ||
107 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); | |
108 | ||
13bb9483 | 109 | if (txq_id != priv->cmd_queue) { |
b305a080 WYG |
110 | sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; |
111 | sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; | |
112 | ||
113 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
114 | case TX_CMD_SEC_CCM: | |
115 | len += CCMP_MIC_LEN; | |
116 | break; | |
117 | case TX_CMD_SEC_TKIP: | |
118 | len += TKIP_ICV_LEN; | |
119 | break; | |
120 | case TX_CMD_SEC_WEP: | |
121 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
122 | break; | |
123 | } | |
124 | } | |
125 | ||
126 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); | |
127 | ||
128 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
129 | ||
130 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
131 | scd_bc_tbl[txq_id]. | |
132 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
133 | } | |
134 | ||
135 | void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, | |
136 | struct iwl_tx_queue *txq) | |
137 | { | |
19e6cda0 | 138 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
b305a080 WYG |
139 | int txq_id = txq->q.id; |
140 | int read_ptr = txq->q.read_ptr; | |
141 | u8 sta_id = 0; | |
142 | __le16 bc_ent; | |
143 | ||
144 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
145 | ||
13bb9483 | 146 | if (txq_id != priv->cmd_queue) |
b305a080 WYG |
147 | sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; |
148 | ||
149 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
150 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
151 | ||
152 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
153 | scd_bc_tbl[txq_id]. | |
154 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
155 | } | |
156 | ||
157 | static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, | |
158 | u16 txq_id) | |
159 | { | |
160 | u32 tbl_dw_addr; | |
161 | u32 tbl_dw; | |
162 | u16 scd_q2ratid; | |
163 | ||
164 | scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
165 | ||
166 | tbl_dw_addr = priv->scd_base_addr + | |
f4388adc | 167 | IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); |
b305a080 WYG |
168 | |
169 | tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); | |
170 | ||
171 | if (txq_id & 0x1) | |
172 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
173 | else | |
174 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
175 | ||
176 | iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); | |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
181 | static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) | |
182 | { | |
183 | /* Simply stop the queue, but don't change any configuration; | |
184 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
185 | iwl_write_prph(priv, | |
f4388adc WYG |
186 | IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id), |
187 | (0 << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
188 | (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
b305a080 WYG |
189 | } |
190 | ||
191 | void iwlagn_set_wr_ptrs(struct iwl_priv *priv, | |
192 | int txq_id, u32 index) | |
193 | { | |
194 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, | |
195 | (index & 0xff) | (txq_id << 8)); | |
f4388adc | 196 | iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(txq_id), index); |
b305a080 WYG |
197 | } |
198 | ||
199 | void iwlagn_tx_queue_set_status(struct iwl_priv *priv, | |
200 | struct iwl_tx_queue *txq, | |
201 | int tx_fifo_id, int scd_retry) | |
202 | { | |
203 | int txq_id = txq->q.id; | |
204 | int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; | |
205 | ||
f4388adc WYG |
206 | iwl_write_prph(priv, IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id), |
207 | (active << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
208 | (tx_fifo_id << IWLAGN_SCD_QUEUE_STTS_REG_POS_TXF) | | |
209 | (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_WSL) | | |
210 | IWLAGN_SCD_QUEUE_STTS_REG_MSK); | |
b305a080 WYG |
211 | |
212 | txq->sched_retry = scd_retry; | |
213 | ||
214 | IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n", | |
215 | active ? "Activate" : "Deactivate", | |
216 | scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id); | |
217 | } | |
218 | ||
219 | int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id, | |
220 | int tx_fifo, int sta_id, int tid, u16 ssn_idx) | |
221 | { | |
222 | unsigned long flags; | |
223 | u16 ra_tid; | |
4620fefa | 224 | int ret; |
b305a080 | 225 | |
19e6cda0 | 226 | if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) || |
7cb1b088 WYG |
227 | (IWLAGN_FIRST_AMPDU_QUEUE + |
228 | priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) { | |
b305a080 WYG |
229 | IWL_WARN(priv, |
230 | "queue number out of range: %d, must be %d to %d\n", | |
19e6cda0 WYG |
231 | txq_id, IWLAGN_FIRST_AMPDU_QUEUE, |
232 | IWLAGN_FIRST_AMPDU_QUEUE + | |
7cb1b088 | 233 | priv->cfg->base_params->num_of_ampdu_queues - 1); |
b305a080 WYG |
234 | return -EINVAL; |
235 | } | |
236 | ||
237 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
238 | ||
239 | /* Modify device's station table to Tx this TID */ | |
4620fefa JB |
240 | ret = iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); |
241 | if (ret) | |
242 | return ret; | |
b305a080 WYG |
243 | |
244 | spin_lock_irqsave(&priv->lock, flags); | |
245 | ||
246 | /* Stop this Tx queue before configuring it */ | |
247 | iwlagn_tx_queue_stop_scheduler(priv, txq_id); | |
248 | ||
249 | /* Map receiver-address / traffic-ID to this queue */ | |
250 | iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id); | |
251 | ||
252 | /* Set this queue as a chain-building queue */ | |
f4388adc | 253 | iwl_set_bits_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL, (1<<txq_id)); |
b305a080 WYG |
254 | |
255 | /* enable aggregations for the queue */ | |
f4388adc | 256 | iwl_set_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1<<txq_id)); |
b305a080 WYG |
257 | |
258 | /* Place first TFD at index corresponding to start sequence number. | |
259 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
260 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
261 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
262 | iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx); | |
263 | ||
264 | /* Set up Tx window size and frame limit for this queue */ | |
265 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
f4388adc | 266 | IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + |
b305a080 WYG |
267 | sizeof(u32), |
268 | ((SCD_WIN_SIZE << | |
f4388adc WYG |
269 | IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & |
270 | IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
b305a080 | 271 | ((SCD_FRAME_LIMIT << |
f4388adc WYG |
272 | IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & |
273 | IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
b305a080 | 274 | |
f4388adc | 275 | iwl_set_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id)); |
b305a080 WYG |
276 | |
277 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
278 | iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); | |
279 | ||
280 | spin_unlock_irqrestore(&priv->lock, flags); | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
285 | int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, | |
286 | u16 ssn_idx, u8 tx_fifo) | |
287 | { | |
19e6cda0 | 288 | if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) || |
7cb1b088 WYG |
289 | (IWLAGN_FIRST_AMPDU_QUEUE + |
290 | priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) { | |
b305a080 WYG |
291 | IWL_ERR(priv, |
292 | "queue number out of range: %d, must be %d to %d\n", | |
19e6cda0 WYG |
293 | txq_id, IWLAGN_FIRST_AMPDU_QUEUE, |
294 | IWLAGN_FIRST_AMPDU_QUEUE + | |
7cb1b088 | 295 | priv->cfg->base_params->num_of_ampdu_queues - 1); |
b305a080 WYG |
296 | return -EINVAL; |
297 | } | |
298 | ||
299 | iwlagn_tx_queue_stop_scheduler(priv, txq_id); | |
300 | ||
f4388adc | 301 | iwl_clear_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1 << txq_id)); |
b305a080 WYG |
302 | |
303 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
304 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
305 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
306 | iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx); | |
307 | ||
f4388adc | 308 | iwl_clear_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id)); |
b305a080 WYG |
309 | iwl_txq_ctx_deactivate(priv, txq_id); |
310 | iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | /* | |
316 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
317 | * must be called under priv->lock and mac access | |
318 | */ | |
319 | void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask) | |
320 | { | |
f4388adc | 321 | iwl_write_prph(priv, IWLAGN_SCD_TXFACT, mask); |
b305a080 | 322 | } |
74bcdb33 | 323 | |
74bcdb33 WYG |
324 | /* |
325 | * handle build REPLY_TX command notification. | |
326 | */ | |
327 | static void iwlagn_tx_cmd_build_basic(struct iwl_priv *priv, | |
d44ae69e JB |
328 | struct sk_buff *skb, |
329 | struct iwl_tx_cmd *tx_cmd, | |
330 | struct ieee80211_tx_info *info, | |
331 | struct ieee80211_hdr *hdr, | |
332 | u8 std_id) | |
74bcdb33 WYG |
333 | { |
334 | __le16 fc = hdr->frame_control; | |
335 | __le32 tx_flags = tx_cmd->tx_flags; | |
336 | ||
337 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
338 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { | |
339 | tx_flags |= TX_CMD_FLG_ACK_MSK; | |
340 | if (ieee80211_is_mgmt(fc)) | |
341 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
342 | if (ieee80211_is_probe_resp(fc) && | |
343 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) | |
344 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
345 | } else { | |
346 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
347 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
348 | } | |
349 | ||
350 | if (ieee80211_is_back_req(fc)) | |
351 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; | |
d44ae69e | 352 | else if (info->band == IEEE80211_BAND_2GHZ && |
7cb1b088 WYG |
353 | priv->cfg->bt_params && |
354 | priv->cfg->bt_params->advanced_bt_coexist && | |
d44ae69e JB |
355 | (ieee80211_is_auth(fc) || ieee80211_is_assoc_req(fc) || |
356 | ieee80211_is_reassoc_req(fc) || | |
357 | skb->protocol == cpu_to_be16(ETH_P_PAE))) | |
358 | tx_flags |= TX_CMD_FLG_IGNORE_BT; | |
74bcdb33 WYG |
359 | |
360 | ||
361 | tx_cmd->sta_id = std_id; | |
362 | if (ieee80211_has_morefrags(fc)) | |
363 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; | |
364 | ||
365 | if (ieee80211_is_data_qos(fc)) { | |
366 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
367 | tx_cmd->tid_tspec = qc[0] & 0xf; | |
368 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
369 | } else { | |
370 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
371 | } | |
372 | ||
94597ab2 | 373 | priv->cfg->ops->utils->tx_cmd_protection(priv, info, fc, &tx_flags); |
74bcdb33 WYG |
374 | |
375 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
376 | if (ieee80211_is_mgmt(fc)) { | |
377 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
378 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); | |
379 | else | |
380 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); | |
381 | } else { | |
382 | tx_cmd->timeout.pm_frame_timeout = 0; | |
383 | } | |
384 | ||
385 | tx_cmd->driver_txop = 0; | |
386 | tx_cmd->tx_flags = tx_flags; | |
387 | tx_cmd->next_frame_len = 0; | |
388 | } | |
389 | ||
390 | #define RTS_DFAULT_RETRY_LIMIT 60 | |
391 | ||
392 | static void iwlagn_tx_cmd_build_rate(struct iwl_priv *priv, | |
393 | struct iwl_tx_cmd *tx_cmd, | |
394 | struct ieee80211_tx_info *info, | |
395 | __le16 fc) | |
396 | { | |
397 | u32 rate_flags; | |
398 | int rate_idx; | |
399 | u8 rts_retry_limit; | |
400 | u8 data_retry_limit; | |
401 | u8 rate_plcp; | |
402 | ||
403 | /* Set retry limit on DATA packets and Probe Responses*/ | |
404 | if (ieee80211_is_probe_resp(fc)) | |
405 | data_retry_limit = 3; | |
406 | else | |
b744cb79 | 407 | data_retry_limit = IWLAGN_DEFAULT_TX_RETRY; |
74bcdb33 WYG |
408 | tx_cmd->data_retry_limit = data_retry_limit; |
409 | ||
410 | /* Set retry limit on RTS packets */ | |
411 | rts_retry_limit = RTS_DFAULT_RETRY_LIMIT; | |
412 | if (data_retry_limit < rts_retry_limit) | |
413 | rts_retry_limit = data_retry_limit; | |
414 | tx_cmd->rts_retry_limit = rts_retry_limit; | |
415 | ||
416 | /* DATA packets will use the uCode station table for rate/antenna | |
417 | * selection */ | |
418 | if (ieee80211_is_data(fc)) { | |
419 | tx_cmd->initial_rate_index = 0; | |
420 | tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; | |
421 | return; | |
422 | } | |
423 | ||
424 | /** | |
425 | * If the current TX rate stored in mac80211 has the MCS bit set, it's | |
426 | * not really a TX rate. Thus, we use the lowest supported rate for | |
427 | * this band. Also use the lowest supported rate if the stored rate | |
428 | * index is invalid. | |
429 | */ | |
430 | rate_idx = info->control.rates[0].idx; | |
431 | if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS || | |
432 | (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY)) | |
433 | rate_idx = rate_lowest_index(&priv->bands[info->band], | |
434 | info->control.sta); | |
435 | /* For 5 GHZ band, remap mac80211 rate indices into driver indices */ | |
436 | if (info->band == IEEE80211_BAND_5GHZ) | |
437 | rate_idx += IWL_FIRST_OFDM_RATE; | |
438 | /* Get PLCP rate for tx_cmd->rate_n_flags */ | |
439 | rate_plcp = iwl_rates[rate_idx].plcp; | |
440 | /* Zero out flags for this packet */ | |
441 | rate_flags = 0; | |
442 | ||
443 | /* Set CCK flag as needed */ | |
444 | if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE)) | |
445 | rate_flags |= RATE_MCS_CCK_MSK; | |
446 | ||
74bcdb33 | 447 | /* Set up antennas */ |
7cb1b088 WYG |
448 | if (priv->cfg->bt_params && |
449 | priv->cfg->bt_params->advanced_bt_coexist && | |
450 | priv->bt_full_concurrent) { | |
bee008b7 WYG |
451 | /* operated as 1x1 in full concurrency mode */ |
452 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant, | |
453 | first_antenna(priv->hw_params.valid_tx_ant)); | |
454 | } else | |
455 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant, | |
0e1654fa | 456 | priv->hw_params.valid_tx_ant); |
74bcdb33 WYG |
457 | rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant); |
458 | ||
459 | /* Set the rate in the TX cmd */ | |
460 | tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags); | |
461 | } | |
462 | ||
463 | static void iwlagn_tx_cmd_build_hwcrypto(struct iwl_priv *priv, | |
464 | struct ieee80211_tx_info *info, | |
465 | struct iwl_tx_cmd *tx_cmd, | |
466 | struct sk_buff *skb_frag, | |
467 | int sta_id) | |
468 | { | |
469 | struct ieee80211_key_conf *keyconf = info->control.hw_key; | |
470 | ||
97359d12 JB |
471 | switch (keyconf->cipher) { |
472 | case WLAN_CIPHER_SUITE_CCMP: | |
74bcdb33 WYG |
473 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; |
474 | memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); | |
475 | if (info->flags & IEEE80211_TX_CTL_AMPDU) | |
476 | tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; | |
477 | IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n"); | |
478 | break; | |
479 | ||
97359d12 | 480 | case WLAN_CIPHER_SUITE_TKIP: |
74bcdb33 WYG |
481 | tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; |
482 | ieee80211_get_tkip_key(keyconf, skb_frag, | |
483 | IEEE80211_TKIP_P2_KEY, tx_cmd->key); | |
484 | IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n"); | |
485 | break; | |
486 | ||
97359d12 JB |
487 | case WLAN_CIPHER_SUITE_WEP104: |
488 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; | |
489 | /* fall through */ | |
490 | case WLAN_CIPHER_SUITE_WEP40: | |
74bcdb33 WYG |
491 | tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP | |
492 | (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT); | |
493 | ||
74bcdb33 WYG |
494 | memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); |
495 | ||
496 | IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption " | |
497 | "with key %d\n", keyconf->keyidx); | |
498 | break; | |
499 | ||
500 | default: | |
97359d12 | 501 | IWL_ERR(priv, "Unknown encode cipher %x\n", keyconf->cipher); |
74bcdb33 WYG |
502 | break; |
503 | } | |
504 | } | |
505 | ||
506 | /* | |
507 | * start REPLY_TX command process | |
508 | */ | |
509 | int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) | |
510 | { | |
511 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
512 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
513 | struct ieee80211_sta *sta = info->control.sta; | |
514 | struct iwl_station_priv *sta_priv = NULL; | |
515 | struct iwl_tx_queue *txq; | |
516 | struct iwl_queue *q; | |
517 | struct iwl_device_cmd *out_cmd; | |
518 | struct iwl_cmd_meta *out_meta; | |
519 | struct iwl_tx_cmd *tx_cmd; | |
a194e324 | 520 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
74bcdb33 WYG |
521 | int swq_id, txq_id; |
522 | dma_addr_t phys_addr; | |
523 | dma_addr_t txcmd_phys; | |
524 | dma_addr_t scratch_phys; | |
525 | u16 len, len_org, firstlen, secondlen; | |
526 | u16 seq_number = 0; | |
527 | __le16 fc; | |
528 | u8 hdr_len; | |
529 | u8 sta_id; | |
530 | u8 wait_write_ptr = 0; | |
531 | u8 tid = 0; | |
532 | u8 *qc = NULL; | |
533 | unsigned long flags; | |
534 | ||
a194e324 JB |
535 | if (info->control.vif) |
536 | ctx = iwl_rxon_ctx_from_vif(info->control.vif); | |
537 | ||
74bcdb33 WYG |
538 | spin_lock_irqsave(&priv->lock, flags); |
539 | if (iwl_is_rfkill(priv)) { | |
540 | IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n"); | |
541 | goto drop_unlock; | |
542 | } | |
543 | ||
544 | fc = hdr->frame_control; | |
545 | ||
546 | #ifdef CONFIG_IWLWIFI_DEBUG | |
547 | if (ieee80211_is_auth(fc)) | |
548 | IWL_DEBUG_TX(priv, "Sending AUTH frame\n"); | |
549 | else if (ieee80211_is_assoc_req(fc)) | |
550 | IWL_DEBUG_TX(priv, "Sending ASSOC frame\n"); | |
551 | else if (ieee80211_is_reassoc_req(fc)) | |
552 | IWL_DEBUG_TX(priv, "Sending REASSOC frame\n"); | |
553 | #endif | |
554 | ||
555 | hdr_len = ieee80211_hdrlen(fc); | |
556 | ||
2a87c26b | 557 | /* Find index into station table for destination station */ |
a194e324 | 558 | sta_id = iwl_sta_id_or_broadcast(priv, ctx, info->control.sta); |
74bcdb33 WYG |
559 | if (sta_id == IWL_INVALID_STATION) { |
560 | IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n", | |
561 | hdr->addr1); | |
562 | goto drop_unlock; | |
563 | } | |
564 | ||
565 | IWL_DEBUG_TX(priv, "station Id %d\n", sta_id); | |
566 | ||
567 | if (sta) | |
568 | sta_priv = (void *)sta->drv_priv; | |
569 | ||
a194e324 | 570 | if (sta_priv && sta_priv->asleep) { |
74bcdb33 WYG |
571 | WARN_ON(!(info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE)); |
572 | /* | |
573 | * This sends an asynchronous command to the device, | |
574 | * but we can rely on it being processed before the | |
575 | * next frame is processed -- and the next frame to | |
576 | * this station is the one that will consume this | |
577 | * counter. | |
578 | * For now set the counter to just 1 since we do not | |
579 | * support uAPSD yet. | |
580 | */ | |
581 | iwl_sta_modify_sleep_tx_count(priv, sta_id, 1); | |
582 | } | |
583 | ||
e72f368b JB |
584 | /* |
585 | * Send this frame after DTIM -- there's a special queue | |
586 | * reserved for this for contexts that support AP mode. | |
587 | */ | |
588 | if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { | |
589 | txq_id = ctx->mcast_queue; | |
590 | /* | |
591 | * The microcode will clear the more data | |
592 | * bit in the last frame it transmits. | |
593 | */ | |
594 | hdr->frame_control |= | |
595 | cpu_to_le16(IEEE80211_FCTL_MOREDATA); | |
596 | } else | |
597 | txq_id = ctx->ac_to_queue[skb_get_queue_mapping(skb)]; | |
9c5ac091 RC |
598 | |
599 | /* irqs already disabled/saved above when locking priv->lock */ | |
600 | spin_lock(&priv->sta_lock); | |
601 | ||
74bcdb33 WYG |
602 | if (ieee80211_is_data_qos(fc)) { |
603 | qc = ieee80211_get_qos_ctl(hdr); | |
604 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; | |
9c5ac091 RC |
605 | if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) { |
606 | spin_unlock(&priv->sta_lock); | |
74bcdb33 | 607 | goto drop_unlock; |
9c5ac091 | 608 | } |
74bcdb33 WYG |
609 | seq_number = priv->stations[sta_id].tid[tid].seq_number; |
610 | seq_number &= IEEE80211_SCTL_SEQ; | |
611 | hdr->seq_ctrl = hdr->seq_ctrl & | |
612 | cpu_to_le16(IEEE80211_SCTL_FRAG); | |
613 | hdr->seq_ctrl |= cpu_to_le16(seq_number); | |
614 | seq_number += 0x10; | |
615 | /* aggregation is on for this <sta,tid> */ | |
616 | if (info->flags & IEEE80211_TX_CTL_AMPDU && | |
617 | priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) { | |
618 | txq_id = priv->stations[sta_id].tid[tid].agg.txq_id; | |
619 | } | |
620 | } | |
621 | ||
622 | txq = &priv->txq[txq_id]; | |
623 | swq_id = txq->swq_id; | |
624 | q = &txq->q; | |
625 | ||
9c5ac091 RC |
626 | if (unlikely(iwl_queue_space(q) < q->high_mark)) { |
627 | spin_unlock(&priv->sta_lock); | |
74bcdb33 | 628 | goto drop_unlock; |
9c5ac091 | 629 | } |
74bcdb33 | 630 | |
9c5ac091 | 631 | if (ieee80211_is_data_qos(fc)) { |
74bcdb33 | 632 | priv->stations[sta_id].tid[tid].tfds_in_queue++; |
9c5ac091 RC |
633 | if (!ieee80211_has_morefrags(fc)) |
634 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
635 | } | |
636 | ||
637 | spin_unlock(&priv->sta_lock); | |
74bcdb33 WYG |
638 | |
639 | /* Set up driver data for this TFD */ | |
640 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); | |
ff0d91c3 | 641 | txq->txb[q->write_ptr].skb = skb; |
c90cbbbd | 642 | txq->txb[q->write_ptr].ctx = ctx; |
74bcdb33 WYG |
643 | |
644 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
645 | out_cmd = txq->cmd[q->write_ptr]; | |
646 | out_meta = &txq->meta[q->write_ptr]; | |
647 | tx_cmd = &out_cmd->cmd.tx; | |
648 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
649 | memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd)); | |
650 | ||
651 | /* | |
652 | * Set up the Tx-command (not MAC!) header. | |
653 | * Store the chosen Tx queue and TFD index within the sequence field; | |
654 | * after Tx, uCode's Tx response will return this value so driver can | |
655 | * locate the frame within the tx queue and do post-tx processing. | |
656 | */ | |
657 | out_cmd->hdr.cmd = REPLY_TX; | |
658 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
659 | INDEX_TO_SEQ(q->write_ptr))); | |
660 | ||
661 | /* Copy MAC header from skb into command buffer */ | |
662 | memcpy(tx_cmd->hdr, hdr, hdr_len); | |
663 | ||
664 | ||
665 | /* Total # bytes to be transmitted */ | |
666 | len = (u16)skb->len; | |
667 | tx_cmd->len = cpu_to_le16(len); | |
668 | ||
669 | if (info->control.hw_key) | |
670 | iwlagn_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id); | |
671 | ||
672 | /* TODO need this for burst mode later on */ | |
d44ae69e | 673 | iwlagn_tx_cmd_build_basic(priv, skb, tx_cmd, info, hdr, sta_id); |
74bcdb33 WYG |
674 | iwl_dbg_log_tx_data_frame(priv, len, hdr); |
675 | ||
676 | iwlagn_tx_cmd_build_rate(priv, tx_cmd, info, fc); | |
677 | ||
678 | iwl_update_stats(priv, true, fc, len); | |
679 | /* | |
680 | * Use the first empty entry in this queue's command buffer array | |
681 | * to contain the Tx command and MAC header concatenated together | |
682 | * (payload data will be in another buffer). | |
683 | * Size of this varies, due to varying MAC header length. | |
684 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
685 | * of the MAC header (device reads on dword boundaries). | |
686 | * We'll tell device about this padding later. | |
687 | */ | |
688 | len = sizeof(struct iwl_tx_cmd) + | |
689 | sizeof(struct iwl_cmd_header) + hdr_len; | |
690 | ||
691 | len_org = len; | |
692 | firstlen = len = (len + 3) & ~3; | |
693 | ||
694 | if (len_org != len) | |
695 | len_org = 1; | |
696 | else | |
697 | len_org = 0; | |
698 | ||
699 | /* Tell NIC about any 2-byte padding after MAC header */ | |
700 | if (len_org) | |
701 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
702 | ||
703 | /* Physical address of this Tx command's header (not MAC header!), | |
704 | * within command buffer array. */ | |
705 | txcmd_phys = pci_map_single(priv->pci_dev, | |
706 | &out_cmd->hdr, len, | |
707 | PCI_DMA_BIDIRECTIONAL); | |
2e724443 FT |
708 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); |
709 | dma_unmap_len_set(out_meta, len, len); | |
74bcdb33 WYG |
710 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
711 | * first entry */ | |
712 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, | |
713 | txcmd_phys, len, 1, 0); | |
714 | ||
715 | if (!ieee80211_has_morefrags(hdr->frame_control)) { | |
716 | txq->need_update = 1; | |
74bcdb33 WYG |
717 | } else { |
718 | wait_write_ptr = 1; | |
719 | txq->need_update = 0; | |
720 | } | |
721 | ||
722 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
723 | * if any (802.11 null frames have no payload). */ | |
724 | secondlen = len = skb->len - hdr_len; | |
725 | if (len) { | |
726 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
727 | len, PCI_DMA_TODEVICE); | |
728 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, | |
729 | phys_addr, len, | |
730 | 0, 0); | |
731 | } | |
732 | ||
733 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + | |
734 | offsetof(struct iwl_tx_cmd, scratch); | |
735 | ||
736 | len = sizeof(struct iwl_tx_cmd) + | |
737 | sizeof(struct iwl_cmd_header) + hdr_len; | |
738 | /* take back ownership of DMA buffer to enable update */ | |
739 | pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys, | |
740 | len, PCI_DMA_BIDIRECTIONAL); | |
741 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
742 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
743 | ||
91dd6c27 | 744 | IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n", |
74bcdb33 | 745 | le16_to_cpu(out_cmd->hdr.sequence)); |
91dd6c27 | 746 | IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); |
74bcdb33 WYG |
747 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); |
748 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
749 | ||
750 | /* Set up entry for this TFD in Tx byte-count array */ | |
751 | if (info->flags & IEEE80211_TX_CTL_AMPDU) | |
752 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, | |
753 | le16_to_cpu(tx_cmd->len)); | |
754 | ||
755 | pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys, | |
756 | len, PCI_DMA_BIDIRECTIONAL); | |
757 | ||
758 | trace_iwlwifi_dev_tx(priv, | |
759 | &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr], | |
760 | sizeof(struct iwl_tfd), | |
761 | &out_cmd->hdr, firstlen, | |
762 | skb->data + hdr_len, secondlen); | |
763 | ||
764 | /* Tell device the write index *just past* this latest filled TFD */ | |
765 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
766 | iwl_txq_update_write_ptr(priv, txq); | |
767 | spin_unlock_irqrestore(&priv->lock, flags); | |
768 | ||
769 | /* | |
770 | * At this point the frame is "transmitted" successfully | |
771 | * and we will get a TX status notification eventually, | |
772 | * regardless of the value of ret. "ret" only indicates | |
773 | * whether or not we should update the write pointer. | |
774 | */ | |
775 | ||
776 | /* avoid atomic ops if it isn't an associated client */ | |
777 | if (sta_priv && sta_priv->client) | |
778 | atomic_inc(&sta_priv->pending_frames); | |
779 | ||
780 | if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) { | |
781 | if (wait_write_ptr) { | |
782 | spin_lock_irqsave(&priv->lock, flags); | |
783 | txq->need_update = 1; | |
784 | iwl_txq_update_write_ptr(priv, txq); | |
785 | spin_unlock_irqrestore(&priv->lock, flags); | |
786 | } else { | |
787 | iwl_stop_queue(priv, txq->swq_id); | |
788 | } | |
789 | } | |
790 | ||
791 | return 0; | |
792 | ||
793 | drop_unlock: | |
794 | spin_unlock_irqrestore(&priv->lock, flags); | |
795 | return -1; | |
796 | } | |
797 | ||
798 | static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv, | |
799 | struct iwl_dma_ptr *ptr, size_t size) | |
800 | { | |
801 | ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma, | |
802 | GFP_KERNEL); | |
803 | if (!ptr->addr) | |
804 | return -ENOMEM; | |
805 | ptr->size = size; | |
806 | return 0; | |
807 | } | |
808 | ||
809 | static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv, | |
810 | struct iwl_dma_ptr *ptr) | |
811 | { | |
812 | if (unlikely(!ptr->addr)) | |
813 | return; | |
814 | ||
815 | dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma); | |
816 | memset(ptr, 0, sizeof(*ptr)); | |
817 | } | |
818 | ||
819 | /** | |
820 | * iwlagn_hw_txq_ctx_free - Free TXQ Context | |
821 | * | |
822 | * Destroy all TX DMA queues and structures | |
823 | */ | |
824 | void iwlagn_hw_txq_ctx_free(struct iwl_priv *priv) | |
825 | { | |
826 | int txq_id; | |
827 | ||
828 | /* Tx queues */ | |
829 | if (priv->txq) { | |
470058e0 | 830 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) |
13bb9483 | 831 | if (txq_id == priv->cmd_queue) |
74bcdb33 WYG |
832 | iwl_cmd_queue_free(priv); |
833 | else | |
834 | iwl_tx_queue_free(priv, txq_id); | |
835 | } | |
836 | iwlagn_free_dma_ptr(priv, &priv->kw); | |
837 | ||
838 | iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls); | |
839 | ||
840 | /* free tx queue structure */ | |
841 | iwl_free_txq_mem(priv); | |
842 | } | |
843 | ||
844 | /** | |
470058e0 ZY |
845 | * iwlagn_txq_ctx_alloc - allocate TX queue context |
846 | * Allocate all Tx DMA structures and initialize them | |
74bcdb33 WYG |
847 | * |
848 | * @param priv | |
849 | * @return error code | |
850 | */ | |
470058e0 | 851 | int iwlagn_txq_ctx_alloc(struct iwl_priv *priv) |
74bcdb33 | 852 | { |
470058e0 | 853 | int ret; |
74bcdb33 WYG |
854 | int txq_id, slots_num; |
855 | unsigned long flags; | |
856 | ||
857 | /* Free all tx/cmd queues and keep-warm buffer */ | |
858 | iwlagn_hw_txq_ctx_free(priv); | |
859 | ||
860 | ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls, | |
861 | priv->hw_params.scd_bc_tbls_size); | |
862 | if (ret) { | |
863 | IWL_ERR(priv, "Scheduler BC Table allocation failed\n"); | |
864 | goto error_bc_tbls; | |
865 | } | |
866 | /* Alloc keep-warm buffer */ | |
867 | ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE); | |
868 | if (ret) { | |
869 | IWL_ERR(priv, "Keep Warm allocation failed\n"); | |
870 | goto error_kw; | |
871 | } | |
872 | ||
873 | /* allocate tx queue structure */ | |
874 | ret = iwl_alloc_txq_mem(priv); | |
875 | if (ret) | |
876 | goto error; | |
877 | ||
878 | spin_lock_irqsave(&priv->lock, flags); | |
879 | ||
880 | /* Turn off all Tx DMA fifos */ | |
881 | priv->cfg->ops->lib->txq_set_sched(priv, 0); | |
882 | ||
883 | /* Tell NIC where to find the "keep warm" buffer */ | |
884 | iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4); | |
885 | ||
886 | spin_unlock_irqrestore(&priv->lock, flags); | |
887 | ||
13bb9483 | 888 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ |
74bcdb33 | 889 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { |
13bb9483 | 890 | slots_num = (txq_id == priv->cmd_queue) ? |
74bcdb33 WYG |
891 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
892 | ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num, | |
893 | txq_id); | |
894 | if (ret) { | |
895 | IWL_ERR(priv, "Tx %d queue init failed\n", txq_id); | |
896 | goto error; | |
897 | } | |
898 | } | |
899 | ||
900 | return ret; | |
901 | ||
902 | error: | |
903 | iwlagn_hw_txq_ctx_free(priv); | |
904 | iwlagn_free_dma_ptr(priv, &priv->kw); | |
905 | error_kw: | |
906 | iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls); | |
907 | error_bc_tbls: | |
908 | return ret; | |
909 | } | |
910 | ||
470058e0 ZY |
911 | void iwlagn_txq_ctx_reset(struct iwl_priv *priv) |
912 | { | |
913 | int txq_id, slots_num; | |
914 | unsigned long flags; | |
915 | ||
916 | spin_lock_irqsave(&priv->lock, flags); | |
917 | ||
918 | /* Turn off all Tx DMA fifos */ | |
919 | priv->cfg->ops->lib->txq_set_sched(priv, 0); | |
920 | ||
921 | /* Tell NIC where to find the "keep warm" buffer */ | |
922 | iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4); | |
923 | ||
924 | spin_unlock_irqrestore(&priv->lock, flags); | |
925 | ||
926 | /* Alloc and init all Tx queues, including the command queue (#4) */ | |
927 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { | |
13bb9483 | 928 | slots_num = txq_id == priv->cmd_queue ? |
470058e0 ZY |
929 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
930 | iwl_tx_queue_reset(priv, &priv->txq[txq_id], slots_num, txq_id); | |
931 | } | |
932 | } | |
933 | ||
74bcdb33 | 934 | /** |
470058e0 | 935 | * iwlagn_txq_ctx_stop - Stop all Tx DMA channels |
74bcdb33 WYG |
936 | */ |
937 | void iwlagn_txq_ctx_stop(struct iwl_priv *priv) | |
938 | { | |
939 | int ch; | |
940 | unsigned long flags; | |
941 | ||
942 | /* Turn off all Tx DMA fifos */ | |
943 | spin_lock_irqsave(&priv->lock, flags); | |
944 | ||
945 | priv->cfg->ops->lib->txq_set_sched(priv, 0); | |
946 | ||
947 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
948 | for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) { | |
949 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
9726f347 | 950 | if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG, |
74bcdb33 | 951 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), |
9726f347 EG |
952 | 1000)) |
953 | IWL_ERR(priv, "Failing on timeout while stopping" | |
954 | " DMA channel %d [0x%08x]", ch, | |
955 | iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG)); | |
74bcdb33 WYG |
956 | } |
957 | spin_unlock_irqrestore(&priv->lock, flags); | |
74bcdb33 WYG |
958 | } |
959 | ||
960 | /* | |
961 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
962 | * Called only when finding queue for aggregation. | |
963 | * Should never return anything < 7, because they should already | |
964 | * be in use as EDCA AC (0-3), Command (4), reserved (5, 6) | |
965 | */ | |
966 | static int iwlagn_txq_ctx_activate_free(struct iwl_priv *priv) | |
967 | { | |
968 | int txq_id; | |
969 | ||
970 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
971 | if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk)) | |
972 | return txq_id; | |
973 | return -1; | |
974 | } | |
975 | ||
832f47e3 | 976 | int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif, |
619753ff | 977 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) |
74bcdb33 WYG |
978 | { |
979 | int sta_id; | |
980 | int tx_fifo; | |
981 | int txq_id; | |
982 | int ret; | |
983 | unsigned long flags; | |
984 | struct iwl_tid_data *tid_data; | |
985 | ||
e72f368b | 986 | tx_fifo = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid); |
74bcdb33 WYG |
987 | if (unlikely(tx_fifo < 0)) |
988 | return tx_fifo; | |
989 | ||
990 | IWL_WARN(priv, "%s on ra = %pM tid = %d\n", | |
619753ff | 991 | __func__, sta->addr, tid); |
74bcdb33 | 992 | |
619753ff | 993 | sta_id = iwl_sta_id(sta); |
74bcdb33 WYG |
994 | if (sta_id == IWL_INVALID_STATION) { |
995 | IWL_ERR(priv, "Start AGG on invalid station\n"); | |
996 | return -ENXIO; | |
997 | } | |
998 | if (unlikely(tid >= MAX_TID_COUNT)) | |
999 | return -EINVAL; | |
1000 | ||
1001 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) { | |
1002 | IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n"); | |
1003 | return -ENXIO; | |
1004 | } | |
1005 | ||
1006 | txq_id = iwlagn_txq_ctx_activate_free(priv); | |
1007 | if (txq_id == -1) { | |
1008 | IWL_ERR(priv, "No free aggregation queue available\n"); | |
1009 | return -ENXIO; | |
1010 | } | |
1011 | ||
1012 | spin_lock_irqsave(&priv->sta_lock, flags); | |
1013 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1014 | *ssn = SEQ_TO_SN(tid_data->seq_number); | |
1015 | tid_data->agg.txq_id = txq_id; | |
c2845d01 | 1016 | priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(get_ac_from_tid(tid), txq_id); |
74bcdb33 WYG |
1017 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
1018 | ||
1019 | ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo, | |
1020 | sta_id, tid, *ssn); | |
1021 | if (ret) | |
1022 | return ret; | |
1023 | ||
9c5ac091 RC |
1024 | spin_lock_irqsave(&priv->sta_lock, flags); |
1025 | tid_data = &priv->stations[sta_id].tid[tid]; | |
74bcdb33 WYG |
1026 | if (tid_data->tfds_in_queue == 0) { |
1027 | IWL_DEBUG_HT(priv, "HW queue is empty\n"); | |
1028 | tid_data->agg.state = IWL_AGG_ON; | |
619753ff | 1029 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
74bcdb33 WYG |
1030 | } else { |
1031 | IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n", | |
1032 | tid_data->tfds_in_queue); | |
1033 | tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA; | |
1034 | } | |
9c5ac091 | 1035 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
74bcdb33 WYG |
1036 | return ret; |
1037 | } | |
1038 | ||
832f47e3 | 1039 | int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif, |
619753ff | 1040 | struct ieee80211_sta *sta, u16 tid) |
74bcdb33 | 1041 | { |
18c121d7 | 1042 | int tx_fifo_id, txq_id, sta_id, ssn; |
74bcdb33 WYG |
1043 | struct iwl_tid_data *tid_data; |
1044 | int write_ptr, read_ptr; | |
1045 | unsigned long flags; | |
1046 | ||
e72f368b | 1047 | tx_fifo_id = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid); |
74bcdb33 WYG |
1048 | if (unlikely(tx_fifo_id < 0)) |
1049 | return tx_fifo_id; | |
1050 | ||
619753ff | 1051 | sta_id = iwl_sta_id(sta); |
74bcdb33 WYG |
1052 | |
1053 | if (sta_id == IWL_INVALID_STATION) { | |
1054 | IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid); | |
1055 | return -ENXIO; | |
1056 | } | |
1057 | ||
9c5ac091 RC |
1058 | spin_lock_irqsave(&priv->sta_lock, flags); |
1059 | ||
74bcdb33 WYG |
1060 | tid_data = &priv->stations[sta_id].tid[tid]; |
1061 | ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; | |
1062 | txq_id = tid_data->agg.txq_id; | |
18c121d7 JB |
1063 | |
1064 | switch (priv->stations[sta_id].tid[tid].agg.state) { | |
1065 | case IWL_EMPTYING_HW_QUEUE_ADDBA: | |
1066 | /* | |
1067 | * This can happen if the peer stops aggregation | |
1068 | * again before we've had a chance to drain the | |
1069 | * queue we selected previously, i.e. before the | |
1070 | * session was really started completely. | |
1071 | */ | |
1072 | IWL_DEBUG_HT(priv, "AGG stop before setup done\n"); | |
1073 | goto turn_off; | |
1074 | case IWL_AGG_ON: | |
1075 | break; | |
1076 | default: | |
1077 | IWL_WARN(priv, "Stopping AGG while state not ON or starting\n"); | |
1078 | } | |
1079 | ||
74bcdb33 WYG |
1080 | write_ptr = priv->txq[txq_id].q.write_ptr; |
1081 | read_ptr = priv->txq[txq_id].q.read_ptr; | |
1082 | ||
1083 | /* The queue is not empty */ | |
1084 | if (write_ptr != read_ptr) { | |
1085 | IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n"); | |
1086 | priv->stations[sta_id].tid[tid].agg.state = | |
1087 | IWL_EMPTYING_HW_QUEUE_DELBA; | |
9c5ac091 | 1088 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
74bcdb33 WYG |
1089 | return 0; |
1090 | } | |
1091 | ||
1092 | IWL_DEBUG_HT(priv, "HW queue is empty\n"); | |
18c121d7 | 1093 | turn_off: |
74bcdb33 WYG |
1094 | priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF; |
1095 | ||
9c5ac091 RC |
1096 | /* do not restore/save irqs */ |
1097 | spin_unlock(&priv->sta_lock); | |
1098 | spin_lock(&priv->lock); | |
1099 | ||
74bcdb33 WYG |
1100 | /* |
1101 | * the only reason this call can fail is queue number out of range, | |
1102 | * which can happen if uCode is reloaded and all the station | |
1103 | * information are lost. if it is outside the range, there is no need | |
1104 | * to deactivate the uCode queue, just return "success" to allow | |
1105 | * mac80211 to clean up it own data. | |
1106 | */ | |
1107 | priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn, | |
1108 | tx_fifo_id); | |
1109 | spin_unlock_irqrestore(&priv->lock, flags); | |
1110 | ||
619753ff | 1111 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
74bcdb33 WYG |
1112 | |
1113 | return 0; | |
1114 | } | |
1115 | ||
1116 | int iwlagn_txq_check_empty(struct iwl_priv *priv, | |
1117 | int sta_id, u8 tid, int txq_id) | |
1118 | { | |
1119 | struct iwl_queue *q = &priv->txq[txq_id].q; | |
1120 | u8 *addr = priv->stations[sta_id].sta.sta.addr; | |
1121 | struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid]; | |
8bd413e6 JB |
1122 | struct iwl_rxon_context *ctx; |
1123 | ||
1124 | ctx = &priv->contexts[priv->stations[sta_id].ctxid]; | |
74bcdb33 | 1125 | |
a24d52f3 | 1126 | lockdep_assert_held(&priv->sta_lock); |
9c5ac091 | 1127 | |
74bcdb33 WYG |
1128 | switch (priv->stations[sta_id].tid[tid].agg.state) { |
1129 | case IWL_EMPTYING_HW_QUEUE_DELBA: | |
1130 | /* We are reclaiming the last packet of the */ | |
1131 | /* aggregated HW queue */ | |
1132 | if ((txq_id == tid_data->agg.txq_id) && | |
1133 | (q->read_ptr == q->write_ptr)) { | |
1134 | u16 ssn = SEQ_TO_SN(tid_data->seq_number); | |
e72f368b | 1135 | int tx_fifo = get_fifo_from_tid(ctx, tid); |
74bcdb33 WYG |
1136 | IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n"); |
1137 | priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, | |
1138 | ssn, tx_fifo); | |
1139 | tid_data->agg.state = IWL_AGG_OFF; | |
8bd413e6 | 1140 | ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid); |
74bcdb33 WYG |
1141 | } |
1142 | break; | |
1143 | case IWL_EMPTYING_HW_QUEUE_ADDBA: | |
1144 | /* We are reclaiming the last packet of the queue */ | |
1145 | if (tid_data->tfds_in_queue == 0) { | |
1146 | IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n"); | |
1147 | tid_data->agg.state = IWL_AGG_ON; | |
8bd413e6 | 1148 | ieee80211_start_tx_ba_cb_irqsafe(ctx->vif, addr, tid); |
74bcdb33 WYG |
1149 | } |
1150 | break; | |
1151 | } | |
9c5ac091 | 1152 | |
74bcdb33 WYG |
1153 | return 0; |
1154 | } | |
1155 | ||
8bd413e6 | 1156 | static void iwlagn_tx_status(struct iwl_priv *priv, struct iwl_tx_info *tx_info) |
74bcdb33 | 1157 | { |
8bd413e6 | 1158 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) tx_info->skb->data; |
74bcdb33 WYG |
1159 | struct ieee80211_sta *sta; |
1160 | struct iwl_station_priv *sta_priv; | |
1161 | ||
6db6340c | 1162 | rcu_read_lock(); |
8bd413e6 | 1163 | sta = ieee80211_find_sta(tx_info->ctx->vif, hdr->addr1); |
74bcdb33 WYG |
1164 | if (sta) { |
1165 | sta_priv = (void *)sta->drv_priv; | |
1166 | /* avoid atomic ops if this isn't a client */ | |
1167 | if (sta_priv->client && | |
1168 | atomic_dec_return(&sta_priv->pending_frames) == 0) | |
1169 | ieee80211_sta_block_awake(priv->hw, sta, false); | |
1170 | } | |
6db6340c | 1171 | rcu_read_unlock(); |
74bcdb33 | 1172 | |
8bd413e6 | 1173 | ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb); |
74bcdb33 WYG |
1174 | } |
1175 | ||
1176 | int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) | |
1177 | { | |
1178 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1179 | struct iwl_queue *q = &txq->q; | |
1180 | struct iwl_tx_info *tx_info; | |
1181 | int nfreed = 0; | |
1182 | struct ieee80211_hdr *hdr; | |
1183 | ||
1184 | if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { | |
1185 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " | |
1186 | "is out of range [0-%d] %d %d.\n", txq_id, | |
1187 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
1188 | return 0; | |
1189 | } | |
1190 | ||
1191 | for (index = iwl_queue_inc_wrap(index, q->n_bd); | |
1192 | q->read_ptr != index; | |
1193 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
1194 | ||
1195 | tx_info = &txq->txb[txq->q.read_ptr]; | |
8bd413e6 | 1196 | iwlagn_tx_status(priv, tx_info); |
74bcdb33 | 1197 | |
ff0d91c3 | 1198 | hdr = (struct ieee80211_hdr *)tx_info->skb->data; |
74bcdb33 WYG |
1199 | if (hdr && ieee80211_is_data_qos(hdr->frame_control)) |
1200 | nfreed++; | |
ff0d91c3 | 1201 | tx_info->skb = NULL; |
74bcdb33 WYG |
1202 | |
1203 | if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl) | |
1204 | priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq); | |
1205 | ||
1206 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); | |
1207 | } | |
1208 | return nfreed; | |
1209 | } | |
1210 | ||
1211 | /** | |
1212 | * iwlagn_tx_status_reply_compressed_ba - Update tx status from block-ack | |
1213 | * | |
1214 | * Go through block-ack's bitmap of ACK'd frames, update driver's record of | |
1215 | * ACK vs. not. This gets sent to mac80211, then to rate scaling algo. | |
1216 | */ | |
1217 | static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv *priv, | |
1218 | struct iwl_ht_agg *agg, | |
1219 | struct iwl_compressed_ba_resp *ba_resp) | |
1220 | ||
1221 | { | |
1222 | int i, sh, ack; | |
1223 | u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl); | |
1224 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
02cd8dee | 1225 | u64 bitmap, sent_bitmap; |
74bcdb33 WYG |
1226 | int successes = 0; |
1227 | struct ieee80211_tx_info *info; | |
1228 | ||
1229 | if (unlikely(!agg->wait_for_ba)) { | |
1230 | IWL_ERR(priv, "Received BA when not expected\n"); | |
1231 | return -EINVAL; | |
1232 | } | |
1233 | ||
1234 | /* Mark that the expected block-ack response arrived */ | |
1235 | agg->wait_for_ba = 0; | |
1236 | IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl); | |
1237 | ||
1238 | /* Calculate shift to align block-ack bits with our Tx window bits */ | |
1239 | sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4); | |
1240 | if (sh < 0) /* tbw something is wrong with indices */ | |
1241 | sh += 0x100; | |
1242 | ||
1243 | /* don't use 64-bit values for now */ | |
1244 | bitmap = le64_to_cpu(ba_resp->bitmap) >> sh; | |
1245 | ||
1246 | if (agg->frame_count > (64 - sh)) { | |
1247 | IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size"); | |
1248 | return -1; | |
1249 | } | |
1250 | ||
1251 | /* check for success or failure according to the | |
1252 | * transmitted bitmap and block-ack bitmap */ | |
02cd8dee | 1253 | sent_bitmap = bitmap & agg->bitmap; |
74bcdb33 WYG |
1254 | |
1255 | /* For each frame attempted in aggregation, | |
1256 | * update driver's record of tx frame's status. */ | |
02cd8dee DH |
1257 | i = 0; |
1258 | while (sent_bitmap) { | |
1259 | ack = sent_bitmap & 1ULL; | |
1260 | successes += ack; | |
74bcdb33 WYG |
1261 | IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n", |
1262 | ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff, | |
1263 | agg->start_idx + i); | |
02cd8dee DH |
1264 | sent_bitmap >>= 1; |
1265 | ++i; | |
74bcdb33 WYG |
1266 | } |
1267 | ||
ff0d91c3 | 1268 | info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb); |
74bcdb33 WYG |
1269 | memset(&info->status, 0, sizeof(info->status)); |
1270 | info->flags |= IEEE80211_TX_STAT_ACK; | |
1271 | info->flags |= IEEE80211_TX_STAT_AMPDU; | |
e3a3cd87 | 1272 | info->status.ampdu_ack_len = successes; |
e3a3cd87 | 1273 | info->status.ampdu_len = agg->frame_count; |
8d801080 | 1274 | iwlagn_hwrate_to_tx_control(priv, agg->rate_n_flags, info); |
74bcdb33 WYG |
1275 | |
1276 | IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap); | |
1277 | ||
1278 | return 0; | |
1279 | } | |
1280 | ||
8d801080 WYG |
1281 | /** |
1282 | * translate ucode response to mac80211 tx status control values | |
1283 | */ | |
1284 | void iwlagn_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags, | |
1285 | struct ieee80211_tx_info *info) | |
1286 | { | |
1287 | struct ieee80211_tx_rate *r = &info->control.rates[0]; | |
1288 | ||
1289 | info->antenna_sel_tx = | |
1290 | ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS); | |
1291 | if (rate_n_flags & RATE_MCS_HT_MSK) | |
1292 | r->flags |= IEEE80211_TX_RC_MCS; | |
1293 | if (rate_n_flags & RATE_MCS_GF_MSK) | |
1294 | r->flags |= IEEE80211_TX_RC_GREEN_FIELD; | |
1295 | if (rate_n_flags & RATE_MCS_HT40_MSK) | |
1296 | r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; | |
1297 | if (rate_n_flags & RATE_MCS_DUP_MSK) | |
1298 | r->flags |= IEEE80211_TX_RC_DUP_DATA; | |
1299 | if (rate_n_flags & RATE_MCS_SGI_MSK) | |
1300 | r->flags |= IEEE80211_TX_RC_SHORT_GI; | |
1301 | r->idx = iwlagn_hwrate_to_mac80211_idx(rate_n_flags, info->band); | |
1302 | } | |
1303 | ||
74bcdb33 WYG |
1304 | /** |
1305 | * iwlagn_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA | |
1306 | * | |
1307 | * Handles block-acknowledge notification from device, which reports success | |
1308 | * of frames sent via aggregation. | |
1309 | */ | |
1310 | void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv, | |
1311 | struct iwl_rx_mem_buffer *rxb) | |
1312 | { | |
1313 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
1314 | struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba; | |
1315 | struct iwl_tx_queue *txq = NULL; | |
1316 | struct iwl_ht_agg *agg; | |
1317 | int index; | |
1318 | int sta_id; | |
1319 | int tid; | |
9c5ac091 | 1320 | unsigned long flags; |
74bcdb33 WYG |
1321 | |
1322 | /* "flow" corresponds to Tx queue */ | |
1323 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
1324 | ||
1325 | /* "ssn" is start of block-ack Tx window, corresponds to index | |
1326 | * (in Tx queue's circular buffer) of first TFD/frame in window */ | |
1327 | u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); | |
1328 | ||
1329 | if (scd_flow >= priv->hw_params.max_txq_num) { | |
1330 | IWL_ERR(priv, | |
1331 | "BUG_ON scd_flow is bigger than number of queues\n"); | |
1332 | return; | |
1333 | } | |
1334 | ||
1335 | txq = &priv->txq[scd_flow]; | |
1336 | sta_id = ba_resp->sta_id; | |
1337 | tid = ba_resp->tid; | |
1338 | agg = &priv->stations[sta_id].tid[tid].agg; | |
b561e827 | 1339 | if (unlikely(agg->txq_id != scd_flow)) { |
735df29a WYG |
1340 | /* |
1341 | * FIXME: this is a uCode bug which need to be addressed, | |
1342 | * log the information and return for now! | |
1343 | * since it is possible happen very often and in order | |
1344 | * not to fill the syslog, don't enable the logging by default | |
1345 | */ | |
1346 | IWL_DEBUG_TX_REPLY(priv, | |
1347 | "BA scd_flow %d does not match txq_id %d\n", | |
b561e827 SZ |
1348 | scd_flow, agg->txq_id); |
1349 | return; | |
1350 | } | |
74bcdb33 WYG |
1351 | |
1352 | /* Find index just before block-ack window */ | |
1353 | index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd); | |
1354 | ||
9c5ac091 | 1355 | spin_lock_irqsave(&priv->sta_lock, flags); |
74bcdb33 WYG |
1356 | |
1357 | IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, " | |
1358 | "sta_id = %d\n", | |
1359 | agg->wait_for_ba, | |
1360 | (u8 *) &ba_resp->sta_addr_lo32, | |
1361 | ba_resp->sta_id); | |
1362 | IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = " | |
1363 | "%d, scd_ssn = %d\n", | |
1364 | ba_resp->tid, | |
1365 | ba_resp->seq_ctl, | |
1366 | (unsigned long long)le64_to_cpu(ba_resp->bitmap), | |
1367 | ba_resp->scd_flow, | |
1368 | ba_resp->scd_ssn); | |
91dd6c27 | 1369 | IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx\n", |
74bcdb33 WYG |
1370 | agg->start_idx, |
1371 | (unsigned long long)agg->bitmap); | |
1372 | ||
1373 | /* Update driver's record of ACK vs. not for each frame in window */ | |
1374 | iwlagn_tx_status_reply_compressed_ba(priv, agg, ba_resp); | |
1375 | ||
1376 | /* Release all TFDs before the SSN, i.e. all TFDs in front of | |
1377 | * block-ack window (we assume that they've been successfully | |
1378 | * transmitted ... if not, it's too late anyway). */ | |
1379 | if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) { | |
1380 | /* calculate mac80211 ampdu sw queue to wake */ | |
1381 | int freed = iwlagn_tx_queue_reclaim(priv, scd_flow, index); | |
1382 | iwl_free_tfds_in_queue(priv, sta_id, tid, freed); | |
1383 | ||
1384 | if ((iwl_queue_space(&txq->q) > txq->q.low_mark) && | |
1385 | priv->mac80211_registered && | |
1386 | (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) | |
1387 | iwl_wake_queue(priv, txq->swq_id); | |
1388 | ||
1389 | iwlagn_txq_check_empty(priv, sta_id, tid, scd_flow); | |
1390 | } | |
9c5ac091 RC |
1391 | |
1392 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
74bcdb33 | 1393 | } |
69fdb710 JB |
1394 | |
1395 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1396 | const char *iwl_get_tx_fail_reason(u32 status) | |
1397 | { | |
1398 | #define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x | |
1399 | #define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x | |
1400 | ||
1401 | switch (status & TX_STATUS_MSK) { | |
1402 | case TX_STATUS_SUCCESS: | |
1403 | return "SUCCESS"; | |
1404 | TX_STATUS_POSTPONE(DELAY); | |
1405 | TX_STATUS_POSTPONE(FEW_BYTES); | |
1406 | TX_STATUS_POSTPONE(BT_PRIO); | |
1407 | TX_STATUS_POSTPONE(QUIET_PERIOD); | |
1408 | TX_STATUS_POSTPONE(CALC_TTAK); | |
1409 | TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY); | |
1410 | TX_STATUS_FAIL(SHORT_LIMIT); | |
1411 | TX_STATUS_FAIL(LONG_LIMIT); | |
1412 | TX_STATUS_FAIL(FIFO_UNDERRUN); | |
1413 | TX_STATUS_FAIL(DRAIN_FLOW); | |
1414 | TX_STATUS_FAIL(RFKILL_FLUSH); | |
1415 | TX_STATUS_FAIL(LIFE_EXPIRE); | |
1416 | TX_STATUS_FAIL(DEST_PS); | |
1417 | TX_STATUS_FAIL(HOST_ABORTED); | |
1418 | TX_STATUS_FAIL(BT_RETRY); | |
1419 | TX_STATUS_FAIL(STA_INVALID); | |
1420 | TX_STATUS_FAIL(FRAG_DROPPED); | |
1421 | TX_STATUS_FAIL(TID_DISABLE); | |
1422 | TX_STATUS_FAIL(FIFO_FLUSHED); | |
1423 | TX_STATUS_FAIL(INSUFFICIENT_CF_POLL); | |
1424 | TX_STATUS_FAIL(PASSIVE_NO_RX); | |
1425 | TX_STATUS_FAIL(NO_BEACON_ON_RADAR); | |
1426 | } | |
1427 | ||
1428 | return "UNKNOWN"; | |
1429 | ||
1430 | #undef TX_STATUS_FAIL | |
1431 | #undef TX_STATUS_POSTPONE | |
1432 | } | |
1433 | #endif /* CONFIG_IWLWIFI_DEBUG */ |