iwlwifi: new debugging feature for dumping data traffic
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
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43#include <net/mac80211.h>
44
45#include <asm/div64.h>
46
a3139c59
SO
47#define DRV_NAME "iwlagn"
48
6bc913bd 49#include "iwl-eeprom.h"
3e0d4cb1 50#include "iwl-dev.h"
fee1247a 51#include "iwl-core.h"
3395f6e9 52#include "iwl-io.h"
b481de9c 53#include "iwl-helpers.h"
6974e363 54#include "iwl-sta.h"
f0832f13 55#include "iwl-calib.h"
b481de9c 56
416e1438 57
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58/******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
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64/*
65 * module name, copyright, version, etc.
b481de9c 66 */
d783b061 67#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 68
0a6857e7 69#ifdef CONFIG_IWLWIFI_DEBUG
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70#define VD "d"
71#else
72#define VD
73#endif
74
80bc5393 75#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
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76#define VS "s"
77#else
78#define VS
79#endif
80
df48c323 81#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 82
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83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
b481de9c 90/*************** STATION TABLE MANAGEMENT ****
9fbab516 91 * mac80211 should be examined to determine if sta_info is duplicating
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92 * the functionality provided here
93 */
94
95/**************************************************************/
96
b481de9c 97/**
5b9f8cd3 98 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 99 *
01ebd063 100 * The RXON command in staging_rxon is committed to the hardware and
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101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
e0158e61 105int iwl_commit_rxon(struct iwl_priv *priv)
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106{
107 /* cast away the const for active_rxon in this function */
c1adf9fb 108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 112
fee1247a 113 if (!iwl_is_alive(priv))
43d59b32 114 return -EBUSY;
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115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
a326a5d0
EG
118 /* allow CTS-to-self if possible. this is relevant only for
119 * 5000, but will not damage 4965 */
120 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
b481de9c 121
8ccde88a 122 ret = iwl_check_rxon_cmd(priv);
43d59b32 123 if (ret) {
15b1687c 124 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
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125 return -EINVAL;
126 }
127
128 /* If we don't need to send a full RXON, we can use
5b9f8cd3 129 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 130 * and other flags for the current radio configuration. */
54559703 131 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
132 ret = iwl_send_rxon_assoc(priv);
133 if (ret) {
15b1687c 134 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 135 return ret;
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136 }
137
138 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
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139 return 0;
140 }
141
142 /* station table will be cleared */
143 priv->assoc_station_added = 0;
144
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145 /* If we are currently associated and the new config requires
146 * an RXON_ASSOC and the new config wants the associated mask enabled,
147 * we must clear the associated from the active configuration
148 * before we apply the new config */
43d59b32 149 if (iwl_is_associated(priv) && new_assoc) {
e1623446 150 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
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151 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
152
43d59b32 153 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 154 sizeof(struct iwl_rxon_cmd),
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155 &priv->active_rxon);
156
157 /* If the mask clearing failed then we set
158 * active_rxon back to what it was previously */
43d59b32 159 if (ret) {
b481de9c 160 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 161 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 162 return ret;
b481de9c 163 }
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164 }
165
e1623446 166 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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167 "* with%s RXON_FILTER_ASSOC_MSK\n"
168 "* channel = %d\n"
e174961c 169 "* bssid = %pM\n",
43d59b32 170 (new_assoc ? "" : "out"),
b481de9c 171 le16_to_cpu(priv->staging_rxon.channel),
e174961c 172 priv->staging_rxon.bssid_addr);
b481de9c 173
90e8e424 174 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG
175
176 /* Apply the new configuration
177 * RXON unassoc clears the station table in uCode, send it before
178 * we add the bcast station. If assoc bit is set, we will send RXON
179 * after having added the bcast and bssid station.
180 */
181 if (!new_assoc) {
182 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 183 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 184 if (ret) {
15b1687c 185 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
186 return ret;
187 }
188 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
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189 }
190
c587de0b 191 iwl_clear_stations_table(priv);
556f8db7 192
19cc1087 193 priv->start_calib = 0;
b481de9c 194
b481de9c 195 /* Add the broadcast address so we can send broadcast frames */
4f40e4d9 196 if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
43d59b32 197 IWL_INVALID_STATION) {
15b1687c 198 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
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199 return -EIO;
200 }
201
202 /* If we have set the ASSOC_MSK and we are in BSS mode then
203 * add the IWL_AP_ID to the station rate table */
9185159d 204 if (new_assoc) {
05c914fe 205 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW
206 ret = iwl_rxon_add_station(priv,
207 priv->active_rxon.bssid_addr, 1);
208 if (ret == IWL_INVALID_STATION) {
15b1687c
WT
209 IWL_ERR(priv,
210 "Error adding AP address for TX.\n");
9185159d
TW
211 return -EIO;
212 }
213 priv->assoc_station_added = 1;
214 if (priv->default_wep_key &&
215 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT
216 IWL_ERR(priv,
217 "Could not send WEP static key.\n");
b481de9c 218 }
43d59b32
EG
219
220 /* Apply the new configuration
221 * RXON assoc doesn't clear the station table in uCode,
222 */
223 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
224 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
225 if (ret) {
15b1687c 226 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
227 return ret;
228 }
229 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
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230 }
231
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232 iwl_init_sensitivity(priv);
233
234 /* If we issue a new RXON command which required a tune then we must
235 * send a new TXPOWER command or we won't be able to Tx any frames */
236 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
237 if (ret) {
15b1687c 238 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
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239 return ret;
240 }
241
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242 return 0;
243}
244
5b9f8cd3 245void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
246{
247
45823531
AK
248 if (priv->cfg->ops->hcmd->set_rxon_chain)
249 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 250 iwlcore_commit_rxon(priv);
5da4b55f
MA
251}
252
fcab423d 253static void iwl_clear_free_frames(struct iwl_priv *priv)
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254{
255 struct list_head *element;
256
e1623446 257 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
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258 priv->frames_count);
259
260 while (!list_empty(&priv->free_frames)) {
261 element = priv->free_frames.next;
262 list_del(element);
fcab423d 263 kfree(list_entry(element, struct iwl_frame, list));
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264 priv->frames_count--;
265 }
266
267 if (priv->frames_count) {
39aadf8c 268 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
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269 priv->frames_count);
270 priv->frames_count = 0;
271 }
272}
273
fcab423d 274static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 275{
fcab423d 276 struct iwl_frame *frame;
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277 struct list_head *element;
278 if (list_empty(&priv->free_frames)) {
279 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
280 if (!frame) {
15b1687c 281 IWL_ERR(priv, "Could not allocate frame!\n");
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282 return NULL;
283 }
284
285 priv->frames_count++;
286 return frame;
287 }
288
289 element = priv->free_frames.next;
290 list_del(element);
fcab423d 291 return list_entry(element, struct iwl_frame, list);
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292}
293
fcab423d 294static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
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295{
296 memset(frame, 0, sizeof(*frame));
297 list_add(&frame->list, &priv->free_frames);
298}
299
4bf64efd
TW
300static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
301 struct ieee80211_hdr *hdr,
73ec1cc2 302 int left)
b481de9c 303{
3109ece1 304 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
305 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
306 (priv->iw_mode != NL80211_IFTYPE_AP)))
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307 return 0;
308
309 if (priv->ibss_beacon->len > left)
310 return 0;
311
312 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
313
314 return priv->ibss_beacon->len;
315}
316
5b9f8cd3 317static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
4bf64efd
TW
318 struct iwl_frame *frame, u8 rate)
319{
320 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
321 unsigned int frame_size;
322
323 tx_beacon_cmd = &frame->u.beacon;
324 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
325
326 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
327 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
328
329 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd
TW
330 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
331
332 BUG_ON(frame_size > MAX_MPDU_SIZE);
333 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
334
335 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
336 tx_beacon_cmd->tx.rate_n_flags =
337 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
338 else
339 tx_beacon_cmd->tx.rate_n_flags =
340 iwl_hw_set_rate_n_flags(rate, 0);
341
342 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
343 TX_CMD_FLG_TSF_MSK |
344 TX_CMD_FLG_STA_RATE_MSK;
345
346 return sizeof(*tx_beacon_cmd) + frame_size;
347}
5b9f8cd3 348static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 349{
fcab423d 350 struct iwl_frame *frame;
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351 unsigned int frame_size;
352 int rc;
353 u8 rate;
354
fcab423d 355 frame = iwl_get_free_frame(priv);
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356
357 if (!frame) {
15b1687c 358 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
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359 "command.\n");
360 return -ENOMEM;
361 }
362
5b9f8cd3 363 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 364
5b9f8cd3 365 frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 366
857485c0 367 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
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368 &frame->u.cmd[0]);
369
fcab423d 370 iwl_free_frame(priv, frame);
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371
372 return rc;
373}
374
7aaa1d79
SO
375static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
376{
377 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
378
379 dma_addr_t addr = get_unaligned_le32(&tb->lo);
380 if (sizeof(dma_addr_t) > sizeof(u32))
381 addr |=
382 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
383
384 return addr;
385}
386
387static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
388{
389 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
390
391 return le16_to_cpu(tb->hi_n_len) >> 4;
392}
393
394static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
395 dma_addr_t addr, u16 len)
396{
397 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
398 u16 hi_n_len = len << 4;
399
400 put_unaligned_le32(addr, &tb->lo);
401 if (sizeof(dma_addr_t) > sizeof(u32))
402 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
403
404 tb->hi_n_len = cpu_to_le16(hi_n_len);
405
406 tfd->num_tbs = idx + 1;
407}
408
409static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
410{
411 return tfd->num_tbs & 0x1f;
412}
413
414/**
415 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
416 * @priv - driver private data
417 * @txq - tx queue
418 *
419 * Does NOT advance any TFD circular buffer read/write indexes
420 * Does NOT free the TFD itself (which is within circular buffer)
421 */
422void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
423{
59606ffa 424 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
425 struct iwl_tfd *tfd;
426 struct pci_dev *dev = priv->pci_dev;
427 int index = txq->q.read_ptr;
428 int i;
429 int num_tbs;
430
431 tfd = &tfd_tmp[index];
432
433 /* Sanity check on number of chunks */
434 num_tbs = iwl_tfd_get_num_tbs(tfd);
435
436 if (num_tbs >= IWL_NUM_OF_TBS) {
437 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
438 /* @todo issue fatal error, it is quite serious situation */
439 return;
440 }
441
442 /* Unmap tx_cmd */
443 if (num_tbs)
444 pci_unmap_single(dev,
c2acea8e
JB
445 pci_unmap_addr(&txq->meta[index], mapping),
446 pci_unmap_len(&txq->meta[index], len),
96891cee 447 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
448
449 /* Unmap chunks, if any. */
450 for (i = 1; i < num_tbs; i++) {
451 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
452 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
453
454 if (txq->txb) {
455 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
456 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
457 }
458 }
459}
460
461int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
462 struct iwl_tx_queue *txq,
463 dma_addr_t addr, u16 len,
464 u8 reset, u8 pad)
465{
466 struct iwl_queue *q;
59606ffa 467 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
468 u32 num_tbs;
469
470 q = &txq->q;
59606ffa
SO
471 tfd_tmp = (struct iwl_tfd *)txq->tfds;
472 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
473
474 if (reset)
475 memset(tfd, 0, sizeof(*tfd));
476
477 num_tbs = iwl_tfd_get_num_tbs(tfd);
478
479 /* Each TFD can point to a maximum 20 Tx buffers */
480 if (num_tbs >= IWL_NUM_OF_TBS) {
481 IWL_ERR(priv, "Error can not send more than %d chunks\n",
482 IWL_NUM_OF_TBS);
483 return -EINVAL;
484 }
485
486 BUG_ON(addr & ~DMA_BIT_MASK(36));
487 if (unlikely(addr & ~IWL_TX_DMA_MASK))
488 IWL_ERR(priv, "Unaligned address = %llx\n",
489 (unsigned long long)addr);
490
491 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
492
493 return 0;
494}
495
a8e74e27
SO
496/*
497 * Tell nic where to find circular buffer of Tx Frame Descriptors for
498 * given Tx queue, and enable the DMA channel used for that queue.
499 *
500 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
501 * channels supported in hardware.
502 */
503int iwl_hw_tx_queue_init(struct iwl_priv *priv,
504 struct iwl_tx_queue *txq)
505{
a8e74e27
SO
506 int txq_id = txq->q.id;
507
a8e74e27
SO
508 /* Circular buffer (TFD queue in DRAM) physical base address */
509 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
510 txq->q.dma_addr >> 8);
511
a8e74e27
SO
512 return 0;
513}
514
b481de9c
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515/******************************************************************************
516 *
517 * Generic RX handler implementations
518 *
519 ******************************************************************************/
885ba202
TW
520static void iwl_rx_reply_alive(struct iwl_priv *priv,
521 struct iwl_rx_mem_buffer *rxb)
b481de9c 522{
db11d634 523 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
885ba202 524 struct iwl_alive_resp *palive;
b481de9c
ZY
525 struct delayed_work *pwork;
526
527 palive = &pkt->u.alive_frame;
528
e1623446 529 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
530 "0x%01X 0x%01X\n",
531 palive->is_valid, palive->ver_type,
532 palive->ver_subtype);
533
534 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 535 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
34a66de6
WYG
536 set_bit(STATUS_INIT_UCODE_ALIVE, &priv->status);
537 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
538 memcpy(&priv->card_alive_init,
539 &pkt->u.alive_frame,
885ba202 540 sizeof(struct iwl_init_alive_resp));
b481de9c
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541 pwork = &priv->init_alive_start;
542 } else {
e1623446 543 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
34a66de6
WYG
544 set_bit(STATUS_RT_UCODE_ALIVE, &priv->status);
545 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 546 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 547 sizeof(struct iwl_alive_resp));
b481de9c
ZY
548 pwork = &priv->alive_start;
549 }
550
551 /* We delay the ALIVE response by 5ms to
552 * give the HW RF Kill time to activate... */
553 if (palive->is_valid == UCODE_VALID_OK)
554 queue_delayed_work(priv->workqueue, pwork,
555 msecs_to_jiffies(5));
556 else
39aadf8c 557 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
558}
559
5b9f8cd3 560static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 561{
c79dd5b5
TW
562 struct iwl_priv *priv =
563 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
564 struct sk_buff *beacon;
565
566 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 567 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
568
569 if (!beacon) {
15b1687c 570 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
571 return;
572 }
573
574 mutex_lock(&priv->mutex);
575 /* new beacon skb is allocated every time; dispose previous.*/
576 if (priv->ibss_beacon)
577 dev_kfree_skb(priv->ibss_beacon);
578
579 priv->ibss_beacon = beacon;
580 mutex_unlock(&priv->mutex);
581
5b9f8cd3 582 iwl_send_beacon_cmd(priv);
b481de9c
ZY
583}
584
4e39317d 585/**
5b9f8cd3 586 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
587 *
588 * This callback is provided in order to send a statistics request.
589 *
590 * This timer function is continually reset to execute within
591 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
592 * was received. We need to ensure we receive the statistics in order
593 * to update the temperature used for calibrating the TXPOWER.
594 */
5b9f8cd3 595static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
596{
597 struct iwl_priv *priv = (struct iwl_priv *)data;
598
599 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
600 return;
601
61780ee3
MA
602 /* dont send host command if rf-kill is on */
603 if (!iwl_is_ready_rf(priv))
604 return;
605
4e39317d
EG
606 iwl_send_statistics_request(priv, CMD_ASYNC);
607}
608
5b9f8cd3 609static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 610 struct iwl_rx_mem_buffer *rxb)
b481de9c 611{
0a6857e7 612#ifdef CONFIG_IWLWIFI_DEBUG
db11d634 613 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2aa6ab86
TW
614 struct iwl4965_beacon_notif *beacon =
615 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 616 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 617
e1623446 618 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 619 "tsf %d %d rate %d\n",
25a6572c 620 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
621 beacon->beacon_notify_hdr.failure_frame,
622 le32_to_cpu(beacon->ibss_mgr_status),
623 le32_to_cpu(beacon->high_tsf),
624 le32_to_cpu(beacon->low_tsf), rate);
625#endif
626
05c914fe 627 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
628 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
629 queue_work(priv->workqueue, &priv->beacon_update);
630}
631
b481de9c
ZY
632/* Handle notification from uCode that card's power state is changing
633 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 634static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 635 struct iwl_rx_mem_buffer *rxb)
b481de9c 636{
db11d634 637 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
638 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
639 unsigned long status = priv->status;
640
e1623446 641 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
642 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
643 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
644
645 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
646 RF_CARD_DISABLED)) {
647
3395f6e9 648 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
649 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
650
a8b50a0a
MA
651 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
652 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
653
654 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 655 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 656 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 657 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 658 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 659 }
39b73fb1
WYG
660 if (flags & RF_CARD_DISABLED)
661 iwl_tt_enter_ct_kill(priv);
b481de9c 662 }
39b73fb1
WYG
663 if (!(flags & RF_CARD_DISABLED))
664 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY
665
666 if (flags & HW_CARD_DISABLED)
667 set_bit(STATUS_RF_KILL_HW, &priv->status);
668 else
669 clear_bit(STATUS_RF_KILL_HW, &priv->status);
670
671
b481de9c 672 if (!(flags & RXON_CARD_DISABLED))
2a421b91 673 iwl_scan_cancel(priv);
b481de9c
ZY
674
675 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
676 test_bit(STATUS_RF_KILL_HW, &priv->status)))
677 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
678 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
679 else
680 wake_up_interruptible(&priv->wait_command_queue);
681}
682
5b9f8cd3 683int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 684{
e2e3c57b 685 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 686 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
687 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
688 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
689 ~APMG_PS_CTRL_MSK_PWR_SRC);
690 } else {
691 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
692 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
693 ~APMG_PS_CTRL_MSK_PWR_SRC);
694 }
695
a8b50a0a 696 return 0;
e2e3c57b
TW
697}
698
b481de9c 699/**
5b9f8cd3 700 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
701 *
702 * Setup the RX handlers for each of the reply types sent from the uCode
703 * to the host.
704 *
705 * This function chains into the hardware specific files for them to setup
706 * any hardware specific handlers as well.
707 */
653fa4a0 708static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 709{
885ba202 710 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
711 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
712 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
5b9f8cd3 713 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 714 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
715 iwl_rx_pm_debug_statistics_notif;
716 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 717
9fbab516
BC
718 /*
719 * The same handler is used for both the REPLY to a discrete
720 * statistics request from the host as well as for the periodic
721 * statistics notifications (after received beacons) from the uCode.
b481de9c 722 */
8f91aecb
EG
723 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
724 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91 725
21c339bf 726 iwl_setup_spectrum_handlers(priv);
2a421b91
TW
727 iwl_setup_rx_scan_handlers(priv);
728
37a44211 729 /* status change handler */
5b9f8cd3 730 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 731
c1354754
TW
732 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
733 iwl_rx_missed_beacon_notif;
37a44211 734 /* Rx handlers */
1781a07f
EG
735 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
736 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
737 /* block ack */
738 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 739 /* Set up hardware specific Rx handlers */
d4789efe 740 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
741}
742
b481de9c 743/**
a55360e4 744 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
745 *
746 * Uses the priv->rx_handlers callback function array to invoke
747 * the appropriate handlers, including command responses,
748 * frame-received notifications, and other notifications.
749 */
a55360e4 750void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 751{
a55360e4 752 struct iwl_rx_mem_buffer *rxb;
db11d634 753 struct iwl_rx_packet *pkt;
a55360e4 754 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
755 u32 r, i;
756 int reclaim;
757 unsigned long flags;
5c0eef96 758 u8 fill_rx = 0;
d68ab680 759 u32 count = 8;
4752c93c 760 int total_empty;
b481de9c 761
6440adb5
CB
762 /* uCode's read index (stored in shared DRAM) indicates the last Rx
763 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 764 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
765 i = rxq->read;
766
767 /* Rx interrupt, but nothing sent from uCode */
768 if (i == r)
e1623446 769 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 770
4752c93c
MA
771 /* calculate total frames need to be restock after handling RX */
772 total_empty = r - priv->rxq.write_actual;
773 if (total_empty < 0)
774 total_empty += RX_QUEUE_SIZE;
775
776 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
777 fill_rx = 1;
778
b481de9c
ZY
779 while (i != r) {
780 rxb = rxq->queue[i];
781
9fbab516 782 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
783 * then a bug has been introduced in the queue refilling
784 * routines -- catch it here */
785 BUG_ON(rxb == NULL);
786
787 rxq->queue[i] = NULL;
788
df833b1d
RC
789 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
790 priv->hw_params.rx_buf_size + 256,
791 PCI_DMA_FROMDEVICE);
db11d634 792 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
793
794 /* Reclaim a command buffer only if this packet is a response
795 * to a (driver-originated) command.
796 * If the packet (e.g. Rx frame) originated from uCode,
797 * there is no command buffer to reclaim.
798 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
799 * but apparently a few don't get set; catch them here. */
800 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
801 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 802 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 803 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 804 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
805 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
806 (pkt->hdr.cmd != REPLY_TX);
807
808 /* Based on type of command response or notification,
809 * handle those that need handling via function in
5b9f8cd3 810 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 811 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 812 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 813 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
b481de9c 814 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
a83b9141 815 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
b481de9c
ZY
816 } else {
817 /* No handling needed */
e1623446 818 IWL_DEBUG_RX(priv,
b481de9c
ZY
819 "r %d i %d No handler needed for %s, 0x%02x\n",
820 r, i, get_cmd_string(pkt->hdr.cmd),
821 pkt->hdr.cmd);
822 }
823
824 if (reclaim) {
9fbab516 825 /* Invoke any callbacks, transfer the skb to caller, and
857485c0 826 * fire off the (possibly) blocking iwl_send_cmd()
b481de9c
ZY
827 * as we reclaim the driver command queue */
828 if (rxb && rxb->skb)
17b88929 829 iwl_tx_cmd_complete(priv, rxb);
b481de9c 830 else
39aadf8c 831 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
832 }
833
834 /* For now we just don't re-use anything. We can tweak this
835 * later to try and re-use notification packets and SKBs that
836 * fail to Rx correctly */
837 if (rxb->skb != NULL) {
838 priv->alloc_rxb_skb--;
839 dev_kfree_skb_any(rxb->skb);
840 rxb->skb = NULL;
841 }
842
b481de9c
ZY
843 spin_lock_irqsave(&rxq->lock, flags);
844 list_add_tail(&rxb->list, &priv->rxq.rx_used);
845 spin_unlock_irqrestore(&rxq->lock, flags);
846 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
847 /* If there are a lot of unused frames,
848 * restock the Rx queue so ucode wont assert. */
849 if (fill_rx) {
850 count++;
851 if (count >= 8) {
852 priv->rxq.read = i;
4752c93c 853 iwl_rx_replenish_now(priv);
5c0eef96
MA
854 count = 0;
855 }
856 }
b481de9c
ZY
857 }
858
859 /* Backtrack one entry */
860 priv->rxq.read = i;
4752c93c
MA
861 if (fill_rx)
862 iwl_rx_replenish_now(priv);
863 else
864 iwl_rx_queue_restock(priv);
a55360e4 865}
a55360e4 866
0359facc
MA
867/* call this function to flush any scheduled tasklet */
868static inline void iwl_synchronize_irq(struct iwl_priv *priv)
869{
a96a27f9 870 /* wait to make sure we flush pending tasklet*/
0359facc
MA
871 synchronize_irq(priv->pci_dev->irq);
872 tasklet_kill(&priv->irq_tasklet);
873}
874
ef850d7c 875static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
876{
877 u32 inta, handled = 0;
878 u32 inta_fh;
879 unsigned long flags;
0a6857e7 880#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
881 u32 inta_mask;
882#endif
883
884 spin_lock_irqsave(&priv->lock, flags);
885
886 /* Ack/clear/reset pending uCode interrupts.
887 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
888 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
889 inta = iwl_read32(priv, CSR_INT);
890 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
891
892 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
893 * Any new interrupts that happen after this, either while we're
894 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
895 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
896 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 897
0a6857e7 898#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 899 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 900 /* just for debug */
3395f6e9 901 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 902 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
903 inta, inta_mask, inta_fh);
904 }
905#endif
906
907 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
908 * atomic, make sure that inta covers all the interrupts that
909 * we've discovered, even if FH interrupt came in just after
910 * reading CSR_INT. */
6f83eaa1 911 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 912 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 913 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
914 inta |= CSR_INT_BIT_FH_TX;
915
916 /* Now service all interrupt bits discovered above. */
917 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 918 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
919
920 /* Tell the device to stop sending interrupts */
5b9f8cd3 921 iwl_disable_interrupts(priv);
b481de9c 922
a83b9141 923 priv->isr_stats.hw++;
5b9f8cd3 924 iwl_irq_handle_error(priv);
b481de9c
ZY
925
926 handled |= CSR_INT_BIT_HW_ERR;
927
928 spin_unlock_irqrestore(&priv->lock, flags);
929
930 return;
931 }
932
0a6857e7 933#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 934 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 935 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 936 if (inta & CSR_INT_BIT_SCD) {
e1623446 937 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 938 "the frame/frames.\n");
a83b9141
WYG
939 priv->isr_stats.sch++;
940 }
b481de9c
ZY
941
942 /* Alive notification via Rx interrupt will do the real work */
a83b9141 943 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 944 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
945 priv->isr_stats.alive++;
946 }
b481de9c
ZY
947 }
948#endif
949 /* Safely ignore these bits for debug checks below */
25c03d8e 950 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 951
9fbab516 952 /* HW RF KILL switch toggled */
b481de9c
ZY
953 if (inta & CSR_INT_BIT_RF_KILL) {
954 int hw_rf_kill = 0;
3395f6e9 955 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
956 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
957 hw_rf_kill = 1;
958
4c423a2b 959 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 960 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 961
a83b9141
WYG
962 priv->isr_stats.rfkill++;
963
a9efa652 964 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
965 * the driver allows loading the ucode even if the radio
966 * is killed. Hence update the killswitch state here. The
967 * rfkill handler will care about restarting if needed.
a9efa652 968 */
6cd0b1cb
HS
969 if (!test_bit(STATUS_ALIVE, &priv->status)) {
970 if (hw_rf_kill)
971 set_bit(STATUS_RF_KILL_HW, &priv->status);
972 else
973 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 974 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 975 }
b481de9c
ZY
976
977 handled |= CSR_INT_BIT_RF_KILL;
978 }
979
9fbab516 980 /* Chip got too hot and stopped itself */
b481de9c 981 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 982 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 983 priv->isr_stats.ctkill++;
b481de9c
ZY
984 handled |= CSR_INT_BIT_CT_KILL;
985 }
986
987 /* Error detected by uCode */
988 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
989 IWL_ERR(priv, "Microcode SW error detected. "
990 " Restarting 0x%X.\n", inta);
a83b9141
WYG
991 priv->isr_stats.sw++;
992 priv->isr_stats.sw_err = inta;
5b9f8cd3 993 iwl_irq_handle_error(priv);
b481de9c
ZY
994 handled |= CSR_INT_BIT_SW_ERR;
995 }
996
997 /* uCode wakes up after power-down sleep */
998 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 999 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1000 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
babcebfa
TW
1001 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1002 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1003 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1004 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1005 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1006 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1007
a83b9141
WYG
1008 priv->isr_stats.wakeup++;
1009
b481de9c
ZY
1010 handled |= CSR_INT_BIT_WAKEUP;
1011 }
1012
1013 /* All uCode command responses, including Tx command responses,
1014 * Rx "responses" (frame-received notification), and other
1015 * notifications from uCode come through here*/
1016 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1017 iwl_rx_handle(priv);
a83b9141 1018 priv->isr_stats.rx++;
b481de9c
ZY
1019 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1020 }
1021
1022 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1023 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
a83b9141 1024 priv->isr_stats.tx++;
b481de9c 1025 handled |= CSR_INT_BIT_FH_TX;
dbb983b7
RR
1026 /* FH finished to write, send event */
1027 priv->ucode_write_complete = 1;
1028 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1029 }
1030
a83b9141 1031 if (inta & ~handled) {
15b1687c 1032 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1033 priv->isr_stats.unhandled++;
1034 }
b481de9c 1035
40cefda9 1036 if (inta & ~(priv->inta_mask)) {
39aadf8c 1037 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1038 inta & ~priv->inta_mask);
39aadf8c 1039 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1040 }
1041
1042 /* Re-enable all interrupts */
0359facc
MA
1043 /* only Re-enable if diabled by irq */
1044 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1045 iwl_enable_interrupts(priv);
b481de9c 1046
0a6857e7 1047#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1048 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW
1049 inta = iwl_read32(priv, CSR_INT);
1050 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1051 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1052 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1053 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1054 }
1055#endif
1056 spin_unlock_irqrestore(&priv->lock, flags);
1057}
1058
ef850d7c
MA
1059/* tasklet for iwlagn interrupt */
1060static void iwl_irq_tasklet(struct iwl_priv *priv)
1061{
1062 u32 inta = 0;
1063 u32 handled = 0;
1064 unsigned long flags;
1065#ifdef CONFIG_IWLWIFI_DEBUG
1066 u32 inta_mask;
1067#endif
1068
1069 spin_lock_irqsave(&priv->lock, flags);
1070
1071 /* Ack/clear/reset pending uCode interrupts.
1072 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1073 */
1074 iwl_write32(priv, CSR_INT, priv->inta);
1075
1076 inta = priv->inta;
1077
1078#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1079 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA
1080 /* just for debug */
1081 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1082 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1083 inta, inta_mask);
1084 }
1085#endif
1086 /* saved interrupt in inta variable now we can reset priv->inta */
1087 priv->inta = 0;
1088
1089 /* Now service all interrupt bits discovered above. */
1090 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1091 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
1092
1093 /* Tell the device to stop sending interrupts */
1094 iwl_disable_interrupts(priv);
1095
1096 priv->isr_stats.hw++;
1097 iwl_irq_handle_error(priv);
1098
1099 handled |= CSR_INT_BIT_HW_ERR;
1100
1101 spin_unlock_irqrestore(&priv->lock, flags);
1102
1103 return;
1104 }
1105
1106#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1107 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA
1108 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1109 if (inta & CSR_INT_BIT_SCD) {
1110 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1111 "the frame/frames.\n");
1112 priv->isr_stats.sch++;
1113 }
1114
1115 /* Alive notification via Rx interrupt will do the real work */
1116 if (inta & CSR_INT_BIT_ALIVE) {
1117 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1118 priv->isr_stats.alive++;
1119 }
1120 }
1121#endif
1122 /* Safely ignore these bits for debug checks below */
1123 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1124
1125 /* HW RF KILL switch toggled */
1126 if (inta & CSR_INT_BIT_RF_KILL) {
1127 int hw_rf_kill = 0;
1128 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1129 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1130 hw_rf_kill = 1;
1131
4c423a2b 1132 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
1133 hw_rf_kill ? "disable radio" : "enable radio");
1134
1135 priv->isr_stats.rfkill++;
1136
1137 /* driver only loads ucode once setting the interface up.
1138 * the driver allows loading the ucode even if the radio
1139 * is killed. Hence update the killswitch state here. The
1140 * rfkill handler will care about restarting if needed.
1141 */
1142 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1143 if (hw_rf_kill)
1144 set_bit(STATUS_RF_KILL_HW, &priv->status);
1145 else
1146 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1147 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
1148 }
1149
1150 handled |= CSR_INT_BIT_RF_KILL;
1151 }
1152
1153 /* Chip got too hot and stopped itself */
1154 if (inta & CSR_INT_BIT_CT_KILL) {
1155 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1156 priv->isr_stats.ctkill++;
1157 handled |= CSR_INT_BIT_CT_KILL;
1158 }
1159
1160 /* Error detected by uCode */
1161 if (inta & CSR_INT_BIT_SW_ERR) {
1162 IWL_ERR(priv, "Microcode SW error detected. "
1163 " Restarting 0x%X.\n", inta);
1164 priv->isr_stats.sw++;
1165 priv->isr_stats.sw_err = inta;
1166 iwl_irq_handle_error(priv);
1167 handled |= CSR_INT_BIT_SW_ERR;
1168 }
1169
1170 /* uCode wakes up after power-down sleep */
1171 if (inta & CSR_INT_BIT_WAKEUP) {
1172 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1173 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1174 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1175 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1176 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1177 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1178 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1179 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
1180
1181 priv->isr_stats.wakeup++;
1182
1183 handled |= CSR_INT_BIT_WAKEUP;
1184 }
1185
1186 /* All uCode command responses, including Tx command responses,
1187 * Rx "responses" (frame-received notification), and other
1188 * notifications from uCode come through here*/
40cefda9
MA
1189 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1190 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1191 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1192 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1193 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1194 iwl_write32(priv, CSR_FH_INT_STATUS,
1195 CSR49_FH_INT_RX_MASK);
1196 }
1197 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1198 handled |= CSR_INT_BIT_RX_PERIODIC;
1199 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1200 }
1201 /* Sending RX interrupt require many steps to be done in the
1202 * the device:
1203 * 1- write interrupt to current index in ICT table.
1204 * 2- dma RX frame.
1205 * 3- update RX shared data to indicate last write index.
1206 * 4- send interrupt.
1207 * This could lead to RX race, driver could receive RX interrupt
1208 * but the shared data changes does not reflect this.
1209 * this could lead to RX race, RX periodic will solve this race
1210 */
1211 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1212 CSR_INT_PERIODIC_DIS);
ef850d7c 1213 iwl_rx_handle(priv);
40cefda9
MA
1214 /* Only set RX periodic if real RX is received. */
1215 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1216 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1217 CSR_INT_PERIODIC_ENA);
1218
ef850d7c 1219 priv->isr_stats.rx++;
ef850d7c
MA
1220 }
1221
1222 if (inta & CSR_INT_BIT_FH_TX) {
1223 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1224 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
1225 priv->isr_stats.tx++;
1226 handled |= CSR_INT_BIT_FH_TX;
1227 /* FH finished to write, send event */
1228 priv->ucode_write_complete = 1;
1229 wake_up_interruptible(&priv->wait_command_queue);
1230 }
1231
1232 if (inta & ~handled) {
1233 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1234 priv->isr_stats.unhandled++;
1235 }
1236
40cefda9 1237 if (inta & ~(priv->inta_mask)) {
ef850d7c 1238 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1239 inta & ~priv->inta_mask);
ef850d7c
MA
1240 }
1241
1242
1243 /* Re-enable all interrupts */
1244 /* only Re-enable if diabled by irq */
1245 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1246 iwl_enable_interrupts(priv);
1247
1248 spin_unlock_irqrestore(&priv->lock, flags);
1249
1250}
1251
a83b9141 1252
b481de9c
ZY
1253/******************************************************************************
1254 *
1255 * uCode download functions
1256 *
1257 ******************************************************************************/
1258
5b9f8cd3 1259static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1260{
98c92211
TW
1261 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1262 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1263 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1264 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1265 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1266 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1267}
1268
5b9f8cd3 1269static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1270{
1271 /* Remove all resets to allow NIC to operate */
1272 iwl_write32(priv, CSR_RESET, 0);
1273}
1274
1275
b481de9c 1276/**
5b9f8cd3 1277 * iwl_read_ucode - Read uCode images from disk file.
b481de9c
ZY
1278 *
1279 * Copy into buffers for card to fetch via bus-mastering
1280 */
5b9f8cd3 1281static int iwl_read_ucode(struct iwl_priv *priv)
b481de9c 1282{
cc0f555d 1283 struct iwl_ucode_header *ucode;
a0987a8d 1284 int ret = -EINVAL, index;
b481de9c 1285 const struct firmware *ucode_raw;
a0987a8d
RC
1286 const char *name_pre = priv->cfg->fw_name_pre;
1287 const unsigned int api_max = priv->cfg->ucode_api_max;
1288 const unsigned int api_min = priv->cfg->ucode_api_min;
1289 char buf[25];
b481de9c
ZY
1290 u8 *src;
1291 size_t len;
cc0f555d
JS
1292 u32 api_ver, build;
1293 u32 inst_size, data_size, init_size, init_data_size, boot_size;
abdc2d62 1294 u16 eeprom_ver;
b481de9c
ZY
1295
1296 /* Ask kernel firmware_class module to get the boot firmware off disk.
1297 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
1298 for (index = api_max; index >= api_min; index--) {
1299 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1300 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1301 if (ret < 0) {
15b1687c 1302 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
1303 buf, ret);
1304 if (ret == -ENOENT)
1305 continue;
1306 else
1307 goto error;
1308 } else {
1309 if (index < api_max)
15b1687c
WT
1310 IWL_ERR(priv, "Loaded firmware %s, "
1311 "which is deprecated. "
1312 "Please use API v%u instead.\n",
a0987a8d 1313 buf, api_max);
15b1687c 1314
e1623446 1315 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
a0987a8d
RC
1316 buf, ucode_raw->size);
1317 break;
1318 }
b481de9c
ZY
1319 }
1320
a0987a8d
RC
1321 if (ret < 0)
1322 goto error;
b481de9c 1323
cc0f555d
JS
1324 /* Make sure that we got at least the v1 header! */
1325 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 1326 IWL_ERR(priv, "File size way too small!\n");
90e759d1 1327 ret = -EINVAL;
b481de9c
ZY
1328 goto err_release;
1329 }
1330
1331 /* Data from ucode file: header followed by uCode images */
cc0f555d 1332 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1333
c02b3acd 1334 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1335 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
1336 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1337 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1338 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1339 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1340 init_data_size =
1341 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1342 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1343 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 1344
a0987a8d
RC
1345 /* api_ver should match the api version forming part of the
1346 * firmware filename ... but we don't check for that and only rely
877d0310 1347 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1348
1349 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1350 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1351 "Driver supports v%u, firmware is v%u.\n",
1352 api_max, api_ver);
1353 priv->ucode_ver = 0;
1354 ret = -EINVAL;
1355 goto err_release;
1356 }
1357 if (api_ver != api_max)
978785a3 1358 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1359 "got v%u. New firmware can be obtained "
1360 "from http://www.intellinuxwireless.org.\n",
1361 api_max, api_ver);
1362
978785a3
TW
1363 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1364 IWL_UCODE_MAJOR(priv->ucode_ver),
1365 IWL_UCODE_MINOR(priv->ucode_ver),
1366 IWL_UCODE_API(priv->ucode_ver),
1367 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1368
cc0f555d
JS
1369 if (build)
1370 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1371
abdc2d62
JS
1372 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1373 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1374 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1375 ? "OTP" : "EEPROM", eeprom_ver);
1376
e1623446 1377 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1378 priv->ucode_ver);
e1623446 1379 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1380 inst_size);
e1623446 1381 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1382 data_size);
e1623446 1383 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1384 init_size);
e1623446 1385 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1386 init_data_size);
e1623446 1387 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1388 boot_size);
1389
1390 /* Verify size of file vs. image size info in file's header */
cc0f555d
JS
1391 if (ucode_raw->size !=
1392 priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
1393 inst_size + data_size + init_size +
1394 init_data_size + boot_size) {
1395
cc0f555d
JS
1396 IWL_DEBUG_INFO(priv,
1397 "uCode file size %d does not match expected size\n",
1398 (int)ucode_raw->size);
90e759d1 1399 ret = -EINVAL;
b481de9c
ZY
1400 goto err_release;
1401 }
1402
1403 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1404 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1405 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
1406 inst_size);
1407 ret = -EINVAL;
b481de9c
ZY
1408 goto err_release;
1409 }
1410
099b40b7 1411 if (data_size > priv->hw_params.max_data_size) {
e1623446 1412 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
1413 data_size);
1414 ret = -EINVAL;
b481de9c
ZY
1415 goto err_release;
1416 }
099b40b7 1417 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1418 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1419 init_size);
90e759d1 1420 ret = -EINVAL;
b481de9c
ZY
1421 goto err_release;
1422 }
099b40b7 1423 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1424 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1
TW
1425 init_data_size);
1426 ret = -EINVAL;
b481de9c
ZY
1427 goto err_release;
1428 }
099b40b7 1429 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1430 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1431 boot_size);
90e759d1 1432 ret = -EINVAL;
b481de9c
ZY
1433 goto err_release;
1434 }
1435
1436 /* Allocate ucode buffers for card's bus-master loading ... */
1437
1438 /* Runtime instructions and 2 copies of data:
1439 * 1) unmodified from disk
1440 * 2) backup cache for save/restore during power-downs */
1441 priv->ucode_code.len = inst_size;
98c92211 1442 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1443
1444 priv->ucode_data.len = data_size;
98c92211 1445 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1446
1447 priv->ucode_data_backup.len = data_size;
98c92211 1448 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1449
1f304e4e
ZY
1450 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1451 !priv->ucode_data_backup.v_addr)
1452 goto err_pci_alloc;
1453
b481de9c 1454 /* Initialization instructions and data */
90e759d1
TW
1455 if (init_size && init_data_size) {
1456 priv->ucode_init.len = init_size;
98c92211 1457 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1458
1459 priv->ucode_init_data.len = init_data_size;
98c92211 1460 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1461
1462 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1463 goto err_pci_alloc;
1464 }
b481de9c
ZY
1465
1466 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1467 if (boot_size) {
1468 priv->ucode_boot.len = boot_size;
98c92211 1469 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1470
90e759d1
TW
1471 if (!priv->ucode_boot.v_addr)
1472 goto err_pci_alloc;
1473 }
b481de9c
ZY
1474
1475 /* Copy images into buffers for card's bus-master reads ... */
1476
1477 /* Runtime instructions (first block of data in file) */
cc0f555d 1478 len = inst_size;
e1623446 1479 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1480 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
1481 src += len;
1482
e1623446 1483 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1484 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1485
1486 /* Runtime data (2nd block)
5b9f8cd3 1487 * NOTE: Copy into backup buffer will be done in iwl_up() */
cc0f555d 1488 len = data_size;
e1623446 1489 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1490 memcpy(priv->ucode_data.v_addr, src, len);
1491 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 1492 src += len;
b481de9c
ZY
1493
1494 /* Initialization instructions (3rd block) */
1495 if (init_size) {
cc0f555d 1496 len = init_size;
e1623446 1497 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1498 len);
b481de9c 1499 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 1500 src += len;
b481de9c
ZY
1501 }
1502
1503 /* Initialization data (4th block) */
1504 if (init_data_size) {
cc0f555d 1505 len = init_data_size;
e1623446 1506 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1507 len);
b481de9c 1508 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 1509 src += len;
b481de9c
ZY
1510 }
1511
1512 /* Bootstrap instructions (5th block) */
cc0f555d 1513 len = boot_size;
e1623446 1514 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1515 memcpy(priv->ucode_boot.v_addr, src, len);
1516
1517 /* We have our copies now, allow OS release its copies */
1518 release_firmware(ucode_raw);
1519 return 0;
1520
1521 err_pci_alloc:
15b1687c 1522 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 1523 ret = -ENOMEM;
5b9f8cd3 1524 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
1525
1526 err_release:
1527 release_firmware(ucode_raw);
1528
1529 error:
90e759d1 1530 return ret;
b481de9c
ZY
1531}
1532
b481de9c 1533/**
4a4a9e81 1534 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1535 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1536 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1537 */
4a4a9e81 1538static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 1539{
57aab75a 1540 int ret = 0;
b481de9c 1541
e1623446 1542 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
1543
1544 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1545 /* We had an error bringing up the hardware, so take it
1546 * all the way back down so we can try again */
e1623446 1547 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
1548 goto restart;
1549 }
1550
1551 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1552 * This is a paranoid check, because we would not have gotten the
1553 * "runtime" alive if code weren't properly loaded. */
b0692f2f 1554 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
1555 /* Runtime instruction load was bad;
1556 * take it all the way back down so we can try again */
e1623446 1557 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
1558 goto restart;
1559 }
1560
c587de0b 1561 iwl_clear_stations_table(priv);
57aab75a
TW
1562 ret = priv->cfg->ops->lib->alive_notify(priv);
1563 if (ret) {
39aadf8c
WT
1564 IWL_WARN(priv,
1565 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
1566 goto restart;
1567 }
1568
5b9f8cd3 1569 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
1570 set_bit(STATUS_ALIVE, &priv->status);
1571
fee1247a 1572 if (iwl_is_rfkill(priv))
b481de9c
ZY
1573 return;
1574
36d6825b 1575 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
1576
1577 priv->active_rate = priv->rates_mask;
1578 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1579
3109ece1 1580 if (iwl_is_associated(priv)) {
c1adf9fb
GG
1581 struct iwl_rxon_cmd *active_rxon =
1582 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
1583 /* apply any changes in staging */
1584 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
1585 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1586 } else {
1587 /* Initialize our rx_config data */
5b9f8cd3 1588 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
1589
1590 if (priv->cfg->ops->hcmd->set_rxon_chain)
1591 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1592
b481de9c
ZY
1593 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1594 }
1595
9fbab516 1596 /* Configure Bluetooth device coexistence support */
5b9f8cd3 1597 iwl_send_bt_config(priv);
b481de9c 1598
4a4a9e81
TW
1599 iwl_reset_run_time_calib(priv);
1600
b481de9c 1601 /* Configure the adapter for unassociated operation */
e0158e61 1602 iwlcore_commit_rxon(priv);
b481de9c
ZY
1603
1604 /* At this point, the NIC is initialized and operational */
47f4a587 1605 iwl_rf_kill_ct_config(priv);
5a66926a 1606
fe00b5a5
RC
1607 iwl_leds_register(priv);
1608
e1623446 1609 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 1610 set_bit(STATUS_READY, &priv->status);
5a66926a 1611 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 1612
58d0f361 1613 iwl_power_update_mode(priv, 1);
c46fbefa 1614
ada17513
MA
1615 /* reassociate for ADHOC mode */
1616 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1617 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1618 priv->vif);
1619 if (beacon)
1620 iwl_mac_beacon_update(priv->hw, beacon);
1621 }
1622
1623
c46fbefa 1624 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 1625 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 1626
b481de9c
ZY
1627 return;
1628
1629 restart:
1630 queue_work(priv->workqueue, &priv->restart);
1631}
1632
4e39317d 1633static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 1634
5b9f8cd3 1635static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1636{
1637 unsigned long flags;
1638 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 1639
e1623446 1640 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 1641
b481de9c
ZY
1642 if (!exit_pending)
1643 set_bit(STATUS_EXIT_PENDING, &priv->status);
1644
ab53d8af
MA
1645 iwl_leds_unregister(priv);
1646
c587de0b 1647 iwl_clear_stations_table(priv);
b481de9c
ZY
1648
1649 /* Unblock any waiting calls */
1650 wake_up_interruptible_all(&priv->wait_command_queue);
1651
b481de9c
ZY
1652 /* Wipe out the EXIT_PENDING status bit if we are not actually
1653 * exiting the module */
1654 if (!exit_pending)
1655 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1656
1657 /* stop and reset the on-board processor */
3395f6e9 1658 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
1659
1660 /* tell the device to stop sending interrupts */
0359facc 1661 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 1662 iwl_disable_interrupts(priv);
0359facc
MA
1663 spin_unlock_irqrestore(&priv->lock, flags);
1664 iwl_synchronize_irq(priv);
b481de9c
ZY
1665
1666 if (priv->mac80211_registered)
1667 ieee80211_stop_queues(priv->hw);
1668
5b9f8cd3 1669 /* If we have not previously called iwl_init() then
a60e77e5 1670 * clear all bits but the RF Kill bit and return */
fee1247a 1671 if (!iwl_is_init(priv)) {
b481de9c
ZY
1672 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1673 STATUS_RF_KILL_HW |
9788864e
RC
1674 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1675 STATUS_GEO_CONFIGURED |
052ec3f1
MA
1676 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1677 STATUS_EXIT_PENDING;
b481de9c
ZY
1678 goto exit;
1679 }
1680
6da3a13e 1681 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 1682 * bit and continue taking the NIC down. */
b481de9c
ZY
1683 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1684 STATUS_RF_KILL_HW |
9788864e
RC
1685 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1686 STATUS_GEO_CONFIGURED |
b481de9c 1687 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
1688 STATUS_FW_ERROR |
1689 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1690 STATUS_EXIT_PENDING;
b481de9c 1691
ef850d7c
MA
1692 /* device going down, Stop using ICT table */
1693 iwl_disable_ict(priv);
b481de9c 1694 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 1695 iwl_clear_bit(priv, CSR_GP_CNTRL,
9fbab516 1696 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
1697 spin_unlock_irqrestore(&priv->lock, flags);
1698
da1bc453 1699 iwl_txq_ctx_stop(priv);
b3bbacb7 1700 iwl_rxq_stop(priv);
b481de9c 1701
a8b50a0a
MA
1702 iwl_write_prph(priv, APMG_CLK_DIS_REG,
1703 APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
1704
1705 udelay(5);
1706
7f066108 1707 /* FIXME: apm_ops.suspend(priv) */
6da3a13e 1708 if (exit_pending)
d535311e
GG
1709 priv->cfg->ops->lib->apm_ops.stop(priv);
1710 else
1711 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 1712 exit:
885ba202 1713 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
1714
1715 if (priv->ibss_beacon)
1716 dev_kfree_skb(priv->ibss_beacon);
1717 priv->ibss_beacon = NULL;
1718
1719 /* clear out any free frames */
fcab423d 1720 iwl_clear_free_frames(priv);
b481de9c
ZY
1721}
1722
5b9f8cd3 1723static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1724{
1725 mutex_lock(&priv->mutex);
5b9f8cd3 1726 __iwl_down(priv);
b481de9c 1727 mutex_unlock(&priv->mutex);
b24d22b1 1728
4e39317d 1729 iwl_cancel_deferred_work(priv);
b481de9c
ZY
1730}
1731
086ed117
MA
1732#define HW_READY_TIMEOUT (50)
1733
1734static int iwl_set_hw_ready(struct iwl_priv *priv)
1735{
1736 int ret = 0;
1737
1738 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1739 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
1740
1741 /* See if we got it */
1742 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1743 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1744 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1745 HW_READY_TIMEOUT);
1746 if (ret != -ETIMEDOUT)
1747 priv->hw_ready = true;
1748 else
1749 priv->hw_ready = false;
1750
1751 IWL_DEBUG_INFO(priv, "hardware %s\n",
1752 (priv->hw_ready == 1) ? "ready" : "not ready");
1753 return ret;
1754}
1755
1756static int iwl_prepare_card_hw(struct iwl_priv *priv)
1757{
1758 int ret = 0;
1759
1760 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
1761
3354a0f6
MA
1762 ret = iwl_set_hw_ready(priv);
1763 if (priv->hw_ready)
1764 return ret;
1765
1766 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
1767 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1768 CSR_HW_IF_CONFIG_REG_PREPARE);
1769
1770 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1771 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
1772 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
1773
3354a0f6 1774 /* HW should be ready by now, check again. */
086ed117
MA
1775 if (ret != -ETIMEDOUT)
1776 iwl_set_hw_ready(priv);
1777
1778 return ret;
1779}
1780
b481de9c
ZY
1781#define MAX_HW_RESTARTS 5
1782
5b9f8cd3 1783static int __iwl_up(struct iwl_priv *priv)
b481de9c 1784{
57aab75a
TW
1785 int i;
1786 int ret;
34a66de6 1787 unsigned long status;
b481de9c
ZY
1788
1789 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 1790 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
1791 return -EIO;
1792 }
1793
e903fbd4 1794 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 1795 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
1796 return -EIO;
1797 }
1798
086ed117
MA
1799 iwl_prepare_card_hw(priv);
1800
1801 if (!priv->hw_ready) {
1802 IWL_WARN(priv, "Exit HW not ready\n");
1803 return -EIO;
1804 }
1805
e655b9f0 1806 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 1807 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 1808 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 1809 else
e655b9f0 1810 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 1811
c1842d61 1812 if (iwl_is_rfkill(priv)) {
a60e77e5
JB
1813 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
1814
5b9f8cd3 1815 iwl_enable_interrupts(priv);
a60e77e5 1816 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 1817 return 0;
b481de9c
ZY
1818 }
1819
3395f6e9 1820 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 1821
1053d35f 1822 ret = iwl_hw_nic_init(priv);
57aab75a 1823 if (ret) {
15b1687c 1824 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 1825 return ret;
b481de9c
ZY
1826 }
1827
1828 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
1829 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1830 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
1831 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1832
1833 /* clear (again), then enable host interrupts */
3395f6e9 1834 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 1835 iwl_enable_interrupts(priv);
b481de9c
ZY
1836
1837 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
1838 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1839 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
1840
1841 /* Copy original ucode data image from disk into backup cache.
1842 * This will be used to initialize the on-board processor's
1843 * data SRAM for a clean start when the runtime program first loads. */
1844 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 1845 priv->ucode_data.len);
b481de9c 1846
b481de9c
ZY
1847 for (i = 0; i < MAX_HW_RESTARTS; i++) {
1848
c587de0b 1849 iwl_clear_stations_table(priv);
b481de9c
ZY
1850
1851 /* load bootstrap state machine,
1852 * load bootstrap program into processor's memory,
1853 * prepare to load the "initialize" uCode */
57aab75a 1854 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 1855
57aab75a 1856 if (ret) {
15b1687c
WT
1857 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
1858 ret);
b481de9c
ZY
1859 continue;
1860 }
1861
1862 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 1863 iwl_nic_start(priv);
b481de9c 1864
34a66de6
WYG
1865 /* Just finish download Init or Runtime uCode image to device
1866 * now we wait here for uCode send REPLY_ALIVE notification
1867 * to indicate uCode is ready.
1868 * 1) For Init uCode image, all iwlagn devices should wait here
1869 * on STATUS_INIT_UCODE_ALIVE status bit; if timeout before
1870 * receive the REPLY_ALIVE notification, go back and try to
1871 * download the Init uCode image again.
1872 * 2) For Runtime uCode image, all iwlagn devices except 4965
1873 * wait here on STATUS_RT_UCODE_ALIVE status bit; if
1874 * timeout before receive the REPLY_ALIVE notification, go back
1875 * and download the Runtime uCode image again.
1876 * 3) For 4965 Runtime uCode, it will not go through this path,
1877 * need to wait for STATUS_RT_UCODE_ALIVE status bit in
1878 * iwl4965_init_alive_start() function; if timeout, need to
1879 * restart and download Init uCode image.
1880 */
1881 if (priv->ucode_type == UCODE_INIT)
1882 status = STATUS_INIT_UCODE_ALIVE;
1883 else
1884 status = STATUS_RT_UCODE_ALIVE;
1885 if (test_bit(status, &priv->status)) {
1886 IWL_WARN(priv,
1887 "%s uCode already alive? "
1888 "Waiting for alive anyway\n",
1889 (status == STATUS_INIT_UCODE_ALIVE)
1890 ? "INIT" : "Runtime");
1891 clear_bit(status, &priv->status);
1892 }
1893 ret = wait_event_interruptible_timeout(
1894 priv->wait_command_queue,
1895 test_bit(status, &priv->status),
1896 UCODE_ALIVE_TIMEOUT);
1897 if (!ret) {
1898 if (!test_bit(status, &priv->status)) {
1899 priv->ucode_type =
1900 (status == STATUS_INIT_UCODE_ALIVE)
1901 ? UCODE_NONE : UCODE_INIT;
1902 IWL_ERR(priv,
1903 "%s timeout after %dms\n",
1904 (status == STATUS_INIT_UCODE_ALIVE)
1905 ? "INIT" : "Runtime",
1906 jiffies_to_msecs(UCODE_ALIVE_TIMEOUT));
1907 continue;
1908 }
1909 }
e1623446 1910 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
1911
1912 return 0;
1913 }
1914
1915 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 1916 __iwl_down(priv);
64e72c3e 1917 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
1918
1919 /* tried to restart and config the device for as long as our
1920 * patience could withstand */
15b1687c 1921 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
1922 return -EIO;
1923}
1924
1925
1926/*****************************************************************************
1927 *
1928 * Workqueue callbacks
1929 *
1930 *****************************************************************************/
1931
4a4a9e81 1932static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 1933{
c79dd5b5
TW
1934 struct iwl_priv *priv =
1935 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
1936
1937 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1938 return;
1939
1940 mutex_lock(&priv->mutex);
f3ccc08c 1941 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
1942 mutex_unlock(&priv->mutex);
1943}
1944
4a4a9e81 1945static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 1946{
c79dd5b5
TW
1947 struct iwl_priv *priv =
1948 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
1949
1950 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1951 return;
1952
258c44a0
MA
1953 /* enable dram interrupt */
1954 iwl_reset_ict(priv);
1955
b481de9c 1956 mutex_lock(&priv->mutex);
4a4a9e81 1957 iwl_alive_start(priv);
b481de9c
ZY
1958 mutex_unlock(&priv->mutex);
1959}
1960
16e727e8
EG
1961static void iwl_bg_run_time_calib_work(struct work_struct *work)
1962{
1963 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1964 run_time_calib_work);
1965
1966 mutex_lock(&priv->mutex);
1967
1968 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1969 test_bit(STATUS_SCANNING, &priv->status)) {
1970 mutex_unlock(&priv->mutex);
1971 return;
1972 }
1973
1974 if (priv->start_calib) {
1975 iwl_chain_noise_calibration(priv, &priv->statistics);
1976
1977 iwl_sensitivity_calibration(priv, &priv->statistics);
1978 }
1979
1980 mutex_unlock(&priv->mutex);
1981 return;
1982}
1983
5b9f8cd3 1984static void iwl_bg_up(struct work_struct *data)
b481de9c 1985{
c79dd5b5 1986 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
1987
1988 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1989 return;
1990
1991 mutex_lock(&priv->mutex);
5b9f8cd3 1992 __iwl_up(priv);
b481de9c
ZY
1993 mutex_unlock(&priv->mutex);
1994}
1995
5b9f8cd3 1996static void iwl_bg_restart(struct work_struct *data)
b481de9c 1997{
c79dd5b5 1998 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
1999
2000 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2001 return;
2002
19cc1087
JB
2003 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2004 mutex_lock(&priv->mutex);
2005 priv->vif = NULL;
2006 priv->is_open = 0;
2007 mutex_unlock(&priv->mutex);
2008 iwl_down(priv);
2009 ieee80211_restart_hw(priv->hw);
2010 } else {
2011 iwl_down(priv);
2012 queue_work(priv->workqueue, &priv->up);
2013 }
b481de9c
ZY
2014}
2015
5b9f8cd3 2016static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2017{
c79dd5b5
TW
2018 struct iwl_priv *priv =
2019 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2020
2021 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2022 return;
2023
2024 mutex_lock(&priv->mutex);
a55360e4 2025 iwl_rx_replenish(priv);
b481de9c
ZY
2026 mutex_unlock(&priv->mutex);
2027}
2028
7878a5a4
MA
2029#define IWL_DELAY_NEXT_SCAN (HZ*2)
2030
5bbe233b 2031void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2032{
b481de9c 2033 struct ieee80211_conf *conf = NULL;
857485c0 2034 int ret = 0;
1ff50bda 2035 unsigned long flags;
b481de9c 2036
05c914fe 2037 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2038 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2039 return;
2040 }
2041
e1623446 2042 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 2043 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
2044
2045
2046 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2047 return;
2048
b481de9c 2049
508e32e1 2050 if (!priv->vif || !priv->is_open)
948c171c 2051 return;
508e32e1 2052
2a421b91 2053 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2054
b481de9c
ZY
2055 conf = ieee80211_get_hw_conf(priv->hw);
2056
2057 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2058 iwlcore_commit_rxon(priv);
b481de9c 2059
3195c1f3 2060 iwl_setup_rxon_timing(priv);
857485c0 2061 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2062 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2063 if (ret)
39aadf8c 2064 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2065 "Attempting to continue.\n");
2066
2067 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2068
42eb7c64 2069 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2070
45823531
AK
2071 if (priv->cfg->ops->hcmd->set_rxon_chain)
2072 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2073
b481de9c
ZY
2074 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2075
e1623446 2076 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2077 priv->assoc_id, priv->beacon_int);
2078
2079 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2080 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2081 else
2082 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2083
2084 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2085 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2086 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2087 else
2088 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2089
05c914fe 2090 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2091 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2092
2093 }
2094
e0158e61 2095 iwlcore_commit_rxon(priv);
b481de9c
ZY
2096
2097 switch (priv->iw_mode) {
05c914fe 2098 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2099 break;
2100
05c914fe 2101 case NL80211_IFTYPE_ADHOC:
b481de9c 2102
c46fbefa
AK
2103 /* assume default assoc id */
2104 priv->assoc_id = 1;
b481de9c 2105
4f40e4d9 2106 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 2107 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2108
2109 break;
2110
2111 default:
15b1687c 2112 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2113 __func__, priv->iw_mode);
b481de9c
ZY
2114 break;
2115 }
2116
05c914fe 2117 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2118 priv->assoc_station_added = 1;
2119
1ff50bda
EG
2120 spin_lock_irqsave(&priv->lock, flags);
2121 iwl_activate_qos(priv, 0);
2122 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 2123
04816448
GE
2124 /* the chain noise calibration will enabled PM upon completion
2125 * If chain noise has already been run, then we need to enable
2126 * power management here */
2127 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
7af2c460 2128 iwl_power_update_mode(priv, 0);
c90a74ba
EG
2129
2130 /* Enable Rx differential gain and sensitivity calibrations */
2131 iwl_chain_noise_reset(priv);
2132 priv->start_calib = 1;
2133
508e32e1
RC
2134}
2135
b481de9c
ZY
2136/*****************************************************************************
2137 *
2138 * mac80211 entry point functions
2139 *
2140 *****************************************************************************/
2141
154b25ce 2142#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2143
5b9f8cd3 2144static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2145{
c79dd5b5 2146 struct iwl_priv *priv = hw->priv;
5a66926a 2147 int ret;
b481de9c 2148
e1623446 2149 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2150
2151 /* we should be verifying the device is ready to be opened */
2152 mutex_lock(&priv->mutex);
2153
5a66926a
ZY
2154 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2155 * ucode filename and max sizes are card-specific. */
b481de9c 2156
5a66926a 2157 if (!priv->ucode_code.len) {
5b9f8cd3 2158 ret = iwl_read_ucode(priv);
5a66926a 2159 if (ret) {
15b1687c 2160 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a 2161 mutex_unlock(&priv->mutex);
6cd0b1cb 2162 return ret;
5a66926a
ZY
2163 }
2164 }
b481de9c 2165
5b9f8cd3 2166 ret = __iwl_up(priv);
5a66926a 2167
b481de9c 2168 mutex_unlock(&priv->mutex);
5a66926a 2169
e655b9f0 2170 if (ret)
6cd0b1cb 2171 return ret;
e655b9f0 2172
c1842d61
TW
2173 if (iwl_is_rfkill(priv))
2174 goto out;
2175
e1623446 2176 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2177
fe9b6b72 2178 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2179 * mac80211 will not be run successfully. */
154b25ce
EG
2180 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2181 test_bit(STATUS_READY, &priv->status),
2182 UCODE_READY_TIMEOUT);
2183 if (!ret) {
2184 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2185 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2186 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2187 return -ETIMEDOUT;
5a66926a 2188 }
fe9b6b72 2189 }
0a078ffa 2190
c1842d61 2191out:
0a078ffa 2192 priv->is_open = 1;
e1623446 2193 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2194 return 0;
2195}
2196
5b9f8cd3 2197static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2198{
c79dd5b5 2199 struct iwl_priv *priv = hw->priv;
b481de9c 2200
e1623446 2201 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2202
19cc1087 2203 if (!priv->is_open)
e655b9f0 2204 return;
e655b9f0 2205
b481de9c 2206 priv->is_open = 0;
5a66926a 2207
fee1247a 2208 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
2209 /* stop mac, cancel any scan request and clear
2210 * RXON_FILTER_ASSOC_MSK BIT
2211 */
5a66926a 2212 mutex_lock(&priv->mutex);
2a421b91 2213 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2214 mutex_unlock(&priv->mutex);
fde3571f
MA
2215 }
2216
5b9f8cd3 2217 iwl_down(priv);
5a66926a
ZY
2218
2219 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2220
2221 /* enable interrupts again in order to receive rfkill changes */
2222 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2223 iwl_enable_interrupts(priv);
948c171c 2224
e1623446 2225 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2226}
2227
5b9f8cd3 2228static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2229{
c79dd5b5 2230 struct iwl_priv *priv = hw->priv;
b481de9c 2231
e1623446 2232 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2233
e1623446 2234 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2235 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2236
e039fa4a 2237 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2238 dev_kfree_skb_any(skb);
2239
e1623446 2240 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2241 return NETDEV_TX_OK;
b481de9c
ZY
2242}
2243
60690a6a 2244void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2245{
857485c0 2246 int ret = 0;
1ff50bda 2247 unsigned long flags;
b481de9c 2248
d986bcd1 2249 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2250 return;
2251
2252 /* The following should be done only at AP bring up */
3195c1f3 2253 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2254
2255 /* RXON - unassoc (to set timing command) */
2256 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2257 iwlcore_commit_rxon(priv);
b481de9c
ZY
2258
2259 /* RXON Timing */
3195c1f3 2260 iwl_setup_rxon_timing(priv);
857485c0 2261 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2262 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2263 if (ret)
39aadf8c 2264 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2265 "Attempting to continue.\n");
2266
45823531
AK
2267 if (priv->cfg->ops->hcmd->set_rxon_chain)
2268 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2269
2270 /* FIXME: what should be the assoc_id for AP? */
2271 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2272 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2273 priv->staging_rxon.flags |=
2274 RXON_FLG_SHORT_PREAMBLE_MSK;
2275 else
2276 priv->staging_rxon.flags &=
2277 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2278
2279 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2280 if (priv->assoc_capability &
2281 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2282 priv->staging_rxon.flags |=
2283 RXON_FLG_SHORT_SLOT_MSK;
2284 else
2285 priv->staging_rxon.flags &=
2286 ~RXON_FLG_SHORT_SLOT_MSK;
2287
05c914fe 2288 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2289 priv->staging_rxon.flags &=
2290 ~RXON_FLG_SHORT_SLOT_MSK;
2291 }
2292 /* restore RXON assoc */
2293 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2294 iwlcore_commit_rxon(priv);
1ff50bda
EG
2295 spin_lock_irqsave(&priv->lock, flags);
2296 iwl_activate_qos(priv, 1);
2297 spin_unlock_irqrestore(&priv->lock, flags);
4f40e4d9 2298 iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
e1493deb 2299 }
5b9f8cd3 2300 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2301
2302 /* FIXME - we need to add code here to detect a totally new
2303 * configuration, reset the AP, unassoc, rxon timing, assoc,
2304 * clear sta table, add BCAST sta... */
2305}
2306
5b9f8cd3 2307static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
ab885f8c
EG
2308 struct ieee80211_key_conf *keyconf, const u8 *addr,
2309 u32 iv32, u16 *phase1key)
2310{
ab885f8c 2311
9f58671e 2312 struct iwl_priv *priv = hw->priv;
e1623446 2313 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2314
9f58671e 2315 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
ab885f8c 2316
e1623446 2317 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2318}
2319
5b9f8cd3 2320static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2321 struct ieee80211_vif *vif,
2322 struct ieee80211_sta *sta,
b481de9c
ZY
2323 struct ieee80211_key_conf *key)
2324{
c79dd5b5 2325 struct iwl_priv *priv = hw->priv;
42986796
WT
2326 const u8 *addr;
2327 int ret;
2328 u8 sta_id;
2329 bool is_default_wep_key = false;
b481de9c 2330
e1623446 2331 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2332
90e8e424 2333 if (priv->cfg->mod_params->sw_crypto) {
e1623446 2334 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2335 return -EOPNOTSUPP;
2336 }
42986796 2337 addr = sta ? sta->addr : iwl_bcast_addr;
c587de0b 2338 sta_id = iwl_find_station(priv, addr);
6974e363 2339 if (sta_id == IWL_INVALID_STATION) {
e1623446 2340 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2341 addr);
6974e363 2342 return -EINVAL;
b481de9c 2343
deb09c43 2344 }
b481de9c 2345
6974e363 2346 mutex_lock(&priv->mutex);
2a421b91 2347 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2348 mutex_unlock(&priv->mutex);
2349
2350 /* If we are getting WEP group key and we didn't receive any key mapping
2351 * so far, we are in legacy wep mode (group key only), otherwise we are
2352 * in 1X mode.
2353 * In legacy wep mode, we use another host command to the uCode */
5425e490 2354 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2355 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2356 if (cmd == SET_KEY)
2357 is_default_wep_key = !priv->key_mapping_key;
2358 else
ccc038ab
EG
2359 is_default_wep_key =
2360 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2361 }
052c4b9f 2362
b481de9c 2363 switch (cmd) {
deb09c43 2364 case SET_KEY:
6974e363
EG
2365 if (is_default_wep_key)
2366 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2367 else
7480513f 2368 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2369
e1623446 2370 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2371 break;
2372 case DISABLE_KEY:
6974e363
EG
2373 if (is_default_wep_key)
2374 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2375 else
3ec47732 2376 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2377
e1623446 2378 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2379 break;
2380 default:
deb09c43 2381 ret = -EINVAL;
b481de9c
ZY
2382 }
2383
e1623446 2384 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2385
deb09c43 2386 return ret;
b481de9c
ZY
2387}
2388
5b9f8cd3 2389static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
d783b061 2390 enum ieee80211_ampdu_mlme_action action,
17741cdc 2391 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2392{
2393 struct iwl_priv *priv = hw->priv;
5c2207c6 2394 int ret;
d783b061 2395
e1623446 2396 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2397 sta->addr, tid);
d783b061
TW
2398
2399 if (!(priv->cfg->sku & IWL_SKU_N))
2400 return -EACCES;
2401
2402 switch (action) {
2403 case IEEE80211_AMPDU_RX_START:
e1623446 2404 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2405 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2406 case IEEE80211_AMPDU_RX_STOP:
e1623446 2407 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2408 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2409 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2410 return 0;
2411 else
2412 return ret;
d783b061 2413 case IEEE80211_AMPDU_TX_START:
e1623446 2414 IWL_DEBUG_HT(priv, "start Tx\n");
17741cdc 2415 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2416 case IEEE80211_AMPDU_TX_STOP:
e1623446 2417 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2418 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2419 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2420 return 0;
2421 else
2422 return ret;
d783b061 2423 default:
e1623446 2424 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2425 return -EINVAL;
2426 break;
2427 }
2428 return 0;
2429}
9f58671e 2430
5b9f8cd3 2431static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2432 struct ieee80211_low_level_stats *stats)
2433{
bf403db8
EK
2434 struct iwl_priv *priv = hw->priv;
2435
2436 priv = hw->priv;
e1623446
TW
2437 IWL_DEBUG_MAC80211(priv, "enter\n");
2438 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2439
2440 return 0;
2441}
2442
b481de9c
ZY
2443/*****************************************************************************
2444 *
2445 * sysfs attributes
2446 *
2447 *****************************************************************************/
2448
0a6857e7 2449#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2450
2451/*
2452 * The following adds a new attribute to the sysfs representation
c3a739fa 2453 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
2454 * used for controlling the debug level.
2455 *
2456 * See the level definitions in iwl for details.
a562a9dd 2457 *
3d816c77
RC
2458 * The debug_level being managed using sysfs below is a per device debug
2459 * level that is used instead of the global debug level if it (the per
2460 * device debug level) is set.
b481de9c 2461 */
8cf769c6
EK
2462static ssize_t show_debug_level(struct device *d,
2463 struct device_attribute *attr, char *buf)
b481de9c 2464{
3d816c77
RC
2465 struct iwl_priv *priv = dev_get_drvdata(d);
2466 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 2467}
8cf769c6
EK
2468static ssize_t store_debug_level(struct device *d,
2469 struct device_attribute *attr,
b481de9c
ZY
2470 const char *buf, size_t count)
2471{
928841b1 2472 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2473 unsigned long val;
2474 int ret;
b481de9c 2475
9257746f
TW
2476 ret = strict_strtoul(buf, 0, &val);
2477 if (ret)
978785a3 2478 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 2479 else {
3d816c77 2480 priv->debug_level = val;
20594eb0
WYG
2481 if (iwl_alloc_traffic_mem(priv))
2482 IWL_ERR(priv,
2483 "Not enough memory to generate traffic log\n");
2484 }
b481de9c
ZY
2485 return strnlen(buf, count);
2486}
2487
8cf769c6
EK
2488static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2489 show_debug_level, store_debug_level);
2490
b481de9c 2491
0a6857e7 2492#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 2493
b481de9c
ZY
2494
2495static ssize_t show_temperature(struct device *d,
2496 struct device_attribute *attr, char *buf)
2497{
928841b1 2498 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 2499
fee1247a 2500 if (!iwl_is_alive(priv))
b481de9c
ZY
2501 return -EAGAIN;
2502
91dbc5bd 2503 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
2504}
2505
2506static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2507
b481de9c
ZY
2508static ssize_t show_tx_power(struct device *d,
2509 struct device_attribute *attr, char *buf)
2510{
928841b1 2511 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
2512
2513 if (!iwl_is_ready_rf(priv))
2514 return sprintf(buf, "off\n");
2515 else
2516 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
2517}
2518
2519static ssize_t store_tx_power(struct device *d,
2520 struct device_attribute *attr,
2521 const char *buf, size_t count)
2522{
928841b1 2523 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2524 unsigned long val;
2525 int ret;
b481de9c 2526
9257746f
TW
2527 ret = strict_strtoul(buf, 10, &val);
2528 if (ret)
978785a3 2529 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
b481de9c 2530 else
630fe9b6 2531 iwl_set_tx_power(priv, val, false);
b481de9c
ZY
2532
2533 return count;
2534}
2535
2536static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2537
2538static ssize_t show_flags(struct device *d,
2539 struct device_attribute *attr, char *buf)
2540{
928841b1 2541 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2542
2543 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2544}
2545
2546static ssize_t store_flags(struct device *d,
2547 struct device_attribute *attr,
2548 const char *buf, size_t count)
2549{
928841b1 2550 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2551 unsigned long val;
2552 u32 flags;
2553 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2554 if (ret)
9257746f
TW
2555 return ret;
2556 flags = (u32)val;
b481de9c
ZY
2557
2558 mutex_lock(&priv->mutex);
2559 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2560 /* Cancel any currently running scans... */
2a421b91 2561 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2562 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2563 else {
e1623446 2564 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 2565 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 2566 iwlcore_commit_rxon(priv);
b481de9c
ZY
2567 }
2568 }
2569 mutex_unlock(&priv->mutex);
2570
2571 return count;
2572}
2573
2574static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2575
2576static ssize_t show_filter_flags(struct device *d,
2577 struct device_attribute *attr, char *buf)
2578{
928841b1 2579 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2580
2581 return sprintf(buf, "0x%04X\n",
2582 le32_to_cpu(priv->active_rxon.filter_flags));
2583}
2584
2585static ssize_t store_filter_flags(struct device *d,
2586 struct device_attribute *attr,
2587 const char *buf, size_t count)
2588{
928841b1 2589 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2590 unsigned long val;
2591 u32 filter_flags;
2592 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2593 if (ret)
9257746f
TW
2594 return ret;
2595 filter_flags = (u32)val;
b481de9c
ZY
2596
2597 mutex_lock(&priv->mutex);
2598 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2599 /* Cancel any currently running scans... */
2a421b91 2600 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2601 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2602 else {
e1623446 2603 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY
2604 "0x%04X\n", filter_flags);
2605 priv->staging_rxon.filter_flags =
2606 cpu_to_le32(filter_flags);
e0158e61 2607 iwlcore_commit_rxon(priv);
b481de9c
ZY
2608 }
2609 }
2610 mutex_unlock(&priv->mutex);
2611
2612 return count;
2613}
2614
2615static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2616 store_filter_flags);
2617
b481de9c
ZY
2618static ssize_t store_power_level(struct device *d,
2619 struct device_attribute *attr,
2620 const char *buf, size_t count)
2621{
c79dd5b5 2622 struct iwl_priv *priv = dev_get_drvdata(d);
298df1f6 2623 int ret;
9257746f
TW
2624 unsigned long mode;
2625
b481de9c 2626
b481de9c
ZY
2627 mutex_lock(&priv->mutex);
2628
9257746f 2629 ret = strict_strtoul(buf, 10, &mode);
926f0b2e 2630 if (ret)
9257746f
TW
2631 goto out;
2632
298df1f6
EK
2633 ret = iwl_power_set_user_mode(priv, mode);
2634 if (ret) {
e1623446 2635 IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
5da4b55f 2636 goto out;
b481de9c 2637 }
298df1f6 2638 ret = count;
b481de9c
ZY
2639
2640 out:
2641 mutex_unlock(&priv->mutex);
298df1f6 2642 return ret;
b481de9c
ZY
2643}
2644
b481de9c
ZY
2645static ssize_t show_power_level(struct device *d,
2646 struct device_attribute *attr, char *buf)
2647{
c79dd5b5 2648 struct iwl_priv *priv = dev_get_drvdata(d);
5da4b55f 2649 int level = priv->power_data.power_mode;
b481de9c
ZY
2650 char *p = buf;
2651
872ed190 2652 p += sprintf(p, "%d\n", level);
3ac7f146 2653 return p - buf + 1;
b481de9c
ZY
2654}
2655
2656static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
2657 store_power_level);
2658
b481de9c
ZY
2659
2660static ssize_t show_statistics(struct device *d,
2661 struct device_attribute *attr, char *buf)
2662{
c79dd5b5 2663 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 2664 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 2665 u32 len = 0, ofs = 0;
3ac7f146 2666 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
2667 int rc = 0;
2668
fee1247a 2669 if (!iwl_is_alive(priv))
b481de9c
ZY
2670 return -EAGAIN;
2671
2672 mutex_lock(&priv->mutex);
49ea8596 2673 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
2674 mutex_unlock(&priv->mutex);
2675
2676 if (rc) {
2677 len = sprintf(buf,
2678 "Error sending statistics request: 0x%08X\n", rc);
2679 return len;
2680 }
2681
2682 while (size && (PAGE_SIZE - len)) {
2683 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2684 PAGE_SIZE - len, 1);
2685 len = strlen(buf);
2686 if (PAGE_SIZE - len)
2687 buf[len++] = '\n';
2688
2689 ofs += 16;
2690 size -= min(size, 16U);
2691 }
2692
2693 return len;
2694}
2695
2696static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
2697
b481de9c 2698
b481de9c
ZY
2699/*****************************************************************************
2700 *
2701 * driver setup and teardown
2702 *
2703 *****************************************************************************/
2704
4e39317d 2705static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2706{
d21050c7 2707 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
2708
2709 init_waitqueue_head(&priv->wait_command_queue);
2710
5b9f8cd3
EG
2711 INIT_WORK(&priv->up, iwl_bg_up);
2712 INIT_WORK(&priv->restart, iwl_bg_restart);
2713 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 2714 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 2715 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
2716 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
2717 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 2718
2a421b91 2719 iwl_setup_scan_deferred_work(priv);
bb8c093b 2720
4e39317d
EG
2721 if (priv->cfg->ops->lib->setup_deferred_work)
2722 priv->cfg->ops->lib->setup_deferred_work(priv);
2723
2724 init_timer(&priv->statistics_periodic);
2725 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 2726 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 2727
ef850d7c
MA
2728 if (!priv->cfg->use_isr_legacy)
2729 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2730 iwl_irq_tasklet, (unsigned long)priv);
2731 else
2732 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2733 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
2734}
2735
4e39317d 2736static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2737{
4e39317d
EG
2738 if (priv->cfg->ops->lib->cancel_deferred_work)
2739 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 2740
3ae6a054 2741 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
2742 cancel_delayed_work(&priv->scan_check);
2743 cancel_delayed_work(&priv->alive_start);
b481de9c 2744 cancel_work_sync(&priv->beacon_update);
4e39317d 2745 del_timer_sync(&priv->statistics_periodic);
b481de9c
ZY
2746}
2747
5b9f8cd3 2748static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY
2749 &dev_attr_flags.attr,
2750 &dev_attr_filter_flags.attr,
b481de9c 2751 &dev_attr_power_level.attr,
b481de9c 2752 &dev_attr_statistics.attr,
b481de9c 2753 &dev_attr_temperature.attr,
b481de9c 2754 &dev_attr_tx_power.attr,
8cf769c6
EK
2755#ifdef CONFIG_IWLWIFI_DEBUG
2756 &dev_attr_debug_level.attr,
2757#endif
b481de9c
ZY
2758 NULL
2759};
2760
5b9f8cd3 2761static struct attribute_group iwl_attribute_group = {
b481de9c 2762 .name = NULL, /* put in device directory */
5b9f8cd3 2763 .attrs = iwl_sysfs_entries,
b481de9c
ZY
2764};
2765
5b9f8cd3
EG
2766static struct ieee80211_ops iwl_hw_ops = {
2767 .tx = iwl_mac_tx,
2768 .start = iwl_mac_start,
2769 .stop = iwl_mac_stop,
2770 .add_interface = iwl_mac_add_interface,
2771 .remove_interface = iwl_mac_remove_interface,
2772 .config = iwl_mac_config,
5b9f8cd3
EG
2773 .configure_filter = iwl_configure_filter,
2774 .set_key = iwl_mac_set_key,
2775 .update_tkip_key = iwl_mac_update_tkip_key,
2776 .get_stats = iwl_mac_get_stats,
2777 .get_tx_stats = iwl_mac_get_tx_stats,
2778 .conf_tx = iwl_mac_conf_tx,
2779 .reset_tsf = iwl_mac_reset_tsf,
2780 .bss_info_changed = iwl_bss_info_changed,
2781 .ampdu_action = iwl_mac_ampdu_action,
cb43dc25 2782 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
2783};
2784
5b9f8cd3 2785static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
2786{
2787 int err = 0;
c79dd5b5 2788 struct iwl_priv *priv;
b481de9c 2789 struct ieee80211_hw *hw;
82b9a121 2790 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 2791 unsigned long flags;
6cd0b1cb 2792 u16 pci_cmd;
b481de9c 2793
316c30d9
AK
2794 /************************
2795 * 1. Allocating HW data
2796 ************************/
2797
6440adb5
CB
2798 /* Disabling hardware scan means that mac80211 will perform scans
2799 * "the hard way", rather than using device's scan. */
1ea87396 2800 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 2801 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK
2802 dev_printk(KERN_DEBUG, &(pdev->dev),
2803 "Disabling hw_scan\n");
5b9f8cd3 2804 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
2805 }
2806
5b9f8cd3 2807 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 2808 if (!hw) {
b481de9c
ZY
2809 err = -ENOMEM;
2810 goto out;
2811 }
1d0a082d
AK
2812 priv = hw->priv;
2813 /* At this point both hw and priv are allocated. */
2814
b481de9c
ZY
2815 SET_IEEE80211_DEV(hw, &pdev->dev);
2816
e1623446 2817 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 2818 priv->cfg = cfg;
b481de9c 2819 priv->pci_dev = pdev;
40cefda9 2820 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 2821
0a6857e7 2822#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2823 atomic_set(&priv->restrict_refcnt, 0);
2824#endif
20594eb0
WYG
2825 if (iwl_alloc_traffic_mem(priv))
2826 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 2827
316c30d9
AK
2828 /**************************
2829 * 2. Initializing PCI bus
2830 **************************/
2831 if (pci_enable_device(pdev)) {
2832 err = -ENODEV;
2833 goto out_ieee80211_free_hw;
2834 }
2835
2836 pci_set_master(pdev);
2837
093d874c 2838 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 2839 if (!err)
093d874c 2840 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 2841 if (err) {
093d874c 2842 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 2843 if (!err)
093d874c 2844 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 2845 /* both attempts failed: */
316c30d9 2846 if (err) {
978785a3 2847 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 2848 goto out_pci_disable_device;
cc2a8ea8 2849 }
316c30d9
AK
2850 }
2851
2852 err = pci_request_regions(pdev, DRV_NAME);
2853 if (err)
2854 goto out_pci_disable_device;
2855
2856 pci_set_drvdata(pdev, priv);
2857
316c30d9
AK
2858
2859 /***********************
2860 * 3. Read REV register
2861 ***********************/
2862 priv->hw_base = pci_iomap(pdev, 0, 0);
2863 if (!priv->hw_base) {
2864 err = -ENODEV;
2865 goto out_pci_release_regions;
2866 }
2867
e1623446 2868 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 2869 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 2870 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 2871
a8b50a0a
MA
2872 /* this spin lock will be used in apm_ops.init and EEPROM access
2873 * we should init now
2874 */
2875 spin_lock_init(&priv->reg_lock);
b661c819 2876 iwl_hw_detect(priv);
978785a3 2877 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 2878 priv->cfg->name, priv->hw_rev);
316c30d9 2879
e7b63581
TW
2880 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2881 * PCI Tx retries from interfering with C3 CPU state */
2882 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2883
086ed117
MA
2884 iwl_prepare_card_hw(priv);
2885 if (!priv->hw_ready) {
2886 IWL_WARN(priv, "Failed, HW not ready\n");
2887 goto out_iounmap;
2888 }
2889
91238714
TW
2890 /* amp init */
2891 err = priv->cfg->ops->lib->apm_ops.init(priv);
316c30d9 2892 if (err < 0) {
808ff697 2893 IWL_ERR(priv, "Failed to init APMG\n");
316c30d9
AK
2894 goto out_iounmap;
2895 }
91238714
TW
2896 /*****************
2897 * 4. Read EEPROM
2898 *****************/
316c30d9
AK
2899 /* Read the EEPROM */
2900 err = iwl_eeprom_init(priv);
2901 if (err) {
15b1687c 2902 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
2903 goto out_iounmap;
2904 }
8614f360
TW
2905 err = iwl_eeprom_check_version(priv);
2906 if (err)
c8f16138 2907 goto out_free_eeprom;
8614f360 2908
02883017 2909 /* extract MAC Address */
316c30d9 2910 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 2911 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
2912 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
2913
2914 /************************
2915 * 5. Setup HW constants
2916 ************************/
da154e30 2917 if (iwl_set_hw_params(priv)) {
15b1687c 2918 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 2919 goto out_free_eeprom;
316c30d9
AK
2920 }
2921
2922 /*******************
6ba87956 2923 * 6. Setup priv
316c30d9 2924 *******************/
b481de9c 2925
6ba87956 2926 err = iwl_init_drv(priv);
bf85ea4f 2927 if (err)
399f4900 2928 goto out_free_eeprom;
bf85ea4f 2929 /* At this point both hw and priv are initialized. */
316c30d9 2930
316c30d9 2931 /********************
09f9bf79 2932 * 7. Setup services
316c30d9 2933 ********************/
0359facc 2934 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2935 iwl_disable_interrupts(priv);
0359facc 2936 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 2937
6cd0b1cb
HS
2938 pci_enable_msi(priv->pci_dev);
2939
ef850d7c
MA
2940 iwl_alloc_isr_ict(priv);
2941 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
2942 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
2943 if (err) {
2944 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
2945 goto out_disable_msi;
2946 }
5b9f8cd3 2947 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 2948 if (err) {
15b1687c 2949 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 2950 goto out_free_irq;
316c30d9
AK
2951 }
2952
4e39317d 2953 iwl_setup_deferred_work(priv);
653fa4a0 2954 iwl_setup_rx_handlers(priv);
316c30d9 2955
6ba87956 2956 /**********************************
09f9bf79 2957 * 8. Setup and register mac80211
6ba87956
TW
2958 **********************************/
2959
6cd0b1cb
HS
2960 /* enable interrupts if needed: hw bug w/a */
2961 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
2962 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2963 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2964 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
2965 }
2966
2967 iwl_enable_interrupts(priv);
2968
6ba87956
TW
2969 err = iwl_setup_mac(priv);
2970 if (err)
2971 goto out_remove_sysfs;
2972
2973 err = iwl_dbgfs_register(priv, DRV_NAME);
2974 if (err)
a75fbe8d 2975 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
6ba87956 2976
6cd0b1cb
HS
2977 /* If platform's RF_KILL switch is NOT set to KILL */
2978 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2979 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2980 else
2981 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 2982
a60e77e5
JB
2983 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
2984 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 2985
58d0f361 2986 iwl_power_initialize(priv);
39b73fb1 2987 iwl_tt_initialize(priv);
b481de9c
ZY
2988 return 0;
2989
316c30d9 2990 out_remove_sysfs:
c8f16138
RC
2991 destroy_workqueue(priv->workqueue);
2992 priv->workqueue = NULL;
5b9f8cd3 2993 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
2994 out_free_irq:
2995 free_irq(priv->pci_dev->irq, priv);
ef850d7c 2996 iwl_free_isr_ict(priv);
6cd0b1cb
HS
2997 out_disable_msi:
2998 pci_disable_msi(priv->pci_dev);
6ba87956 2999 iwl_uninit_drv(priv);
073d3f5f
TW
3000 out_free_eeprom:
3001 iwl_eeprom_free(priv);
b481de9c
ZY
3002 out_iounmap:
3003 pci_iounmap(pdev, priv->hw_base);
3004 out_pci_release_regions:
316c30d9 3005 pci_set_drvdata(pdev, NULL);
623d563e 3006 pci_release_regions(pdev);
b481de9c
ZY
3007 out_pci_disable_device:
3008 pci_disable_device(pdev);
b481de9c
ZY
3009 out_ieee80211_free_hw:
3010 ieee80211_free_hw(priv->hw);
20594eb0 3011 iwl_free_traffic_mem(priv);
b481de9c
ZY
3012 out:
3013 return err;
3014}
3015
5b9f8cd3 3016static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3017{
c79dd5b5 3018 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3019 unsigned long flags;
b481de9c
ZY
3020
3021 if (!priv)
3022 return;
3023
e1623446 3024 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3025
67249625 3026 iwl_dbgfs_unregister(priv);
5b9f8cd3 3027 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3028
5b9f8cd3
EG
3029 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3030 * to be called and iwl_down since we are removing the device
0b124c31
GG
3031 * we need to set STATUS_EXIT_PENDING bit.
3032 */
3033 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3034 if (priv->mac80211_registered) {
3035 ieee80211_unregister_hw(priv->hw);
3036 priv->mac80211_registered = 0;
0b124c31 3037 } else {
5b9f8cd3 3038 iwl_down(priv);
c4f55232
RR
3039 }
3040
39b73fb1
WYG
3041 iwl_tt_exit(priv);
3042
0359facc
MA
3043 /* make sure we flush any pending irq or
3044 * tasklet for the driver
3045 */
3046 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3047 iwl_disable_interrupts(priv);
0359facc
MA
3048 spin_unlock_irqrestore(&priv->lock, flags);
3049
3050 iwl_synchronize_irq(priv);
3051
5b9f8cd3 3052 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3053
3054 if (priv->rxq.bd)
a55360e4 3055 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3056 iwl_hw_txq_ctx_free(priv);
b481de9c 3057
c587de0b 3058 iwl_clear_stations_table(priv);
073d3f5f 3059 iwl_eeprom_free(priv);
b481de9c 3060
b481de9c 3061
948c171c
MA
3062 /*netif_stop_queue(dev); */
3063 flush_workqueue(priv->workqueue);
3064
5b9f8cd3 3065 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3066 * priv->workqueue... so we can't take down the workqueue
3067 * until now... */
3068 destroy_workqueue(priv->workqueue);
3069 priv->workqueue = NULL;
20594eb0 3070 iwl_free_traffic_mem(priv);
b481de9c 3071
6cd0b1cb
HS
3072 free_irq(priv->pci_dev->irq, priv);
3073 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3074 pci_iounmap(pdev, priv->hw_base);
3075 pci_release_regions(pdev);
3076 pci_disable_device(pdev);
3077 pci_set_drvdata(pdev, NULL);
3078
6ba87956 3079 iwl_uninit_drv(priv);
b481de9c 3080
ef850d7c
MA
3081 iwl_free_isr_ict(priv);
3082
b481de9c
ZY
3083 if (priv->ibss_beacon)
3084 dev_kfree_skb(priv->ibss_beacon);
3085
3086 ieee80211_free_hw(priv->hw);
3087}
3088
b481de9c
ZY
3089
3090/*****************************************************************************
3091 *
3092 * driver and module entry point
3093 *
3094 *****************************************************************************/
3095
fed9017e
RR
3096/* Hardware specific file defines the PCI IDs table for that hardware module */
3097static struct pci_device_id iwl_hw_card_ids[] = {
4fc22b21 3098#ifdef CONFIG_IWL4965
fed9017e
RR
3099 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3100 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3101#endif /* CONFIG_IWL4965 */
5a6a256e 3102#ifdef CONFIG_IWL5000
47408639
EK
3103 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3104 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3105 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3106 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3107 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3108 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
5a6a256e 3109 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
47408639
EK
3110 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3111 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3112 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
e96a8495
TW
3113/* 5350 WiFi/WiMax */
3114 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3115 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3116 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
7100e924
TW
3117/* 5150 Wifi/WiMax */
3118 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3119 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
e1228374 3120/* 6000/6050 Series */
65b7998a
WYG
3121 {IWL_PCI_DEVICE(0x008D, PCI_ANY_ID, iwl6000h_2agn_cfg)},
3122 {IWL_PCI_DEVICE(0x008E, PCI_ANY_ID, iwl6000h_2agn_cfg)},
e1228374 3123 {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
65b7998a 3124 {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000i_2agn_cfg)},
e1228374 3125 {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
65b7998a 3126 {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000i_2agn_cfg)},
e1228374
JS
3127 {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
3128 {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
3129 {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
3130 {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
77dcb6a9
JS
3131/* 1000 Series WiFi */
3132 {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
3133 {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
5a6a256e 3134#endif /* CONFIG_IWL5000 */
7100e924 3135
fed9017e
RR
3136 {0}
3137};
3138MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3139
3140static struct pci_driver iwl_driver = {
b481de9c 3141 .name = DRV_NAME,
fed9017e 3142 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3143 .probe = iwl_pci_probe,
3144 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3145#ifdef CONFIG_PM
5b9f8cd3
EG
3146 .suspend = iwl_pci_suspend,
3147 .resume = iwl_pci_resume,
b481de9c
ZY
3148#endif
3149};
3150
5b9f8cd3 3151static int __init iwl_init(void)
b481de9c
ZY
3152{
3153
3154 int ret;
3155 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3156 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3157
e227ceac 3158 ret = iwlagn_rate_control_register();
897e1cf2 3159 if (ret) {
a3139c59
SO
3160 printk(KERN_ERR DRV_NAME
3161 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3162 return ret;
3163 }
3164
fed9017e 3165 ret = pci_register_driver(&iwl_driver);
b481de9c 3166 if (ret) {
a3139c59 3167 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3168 goto error_register;
b481de9c 3169 }
b481de9c
ZY
3170
3171 return ret;
897e1cf2 3172
897e1cf2 3173error_register:
e227ceac 3174 iwlagn_rate_control_unregister();
897e1cf2 3175 return ret;
b481de9c
ZY
3176}
3177
5b9f8cd3 3178static void __exit iwl_exit(void)
b481de9c 3179{
fed9017e 3180 pci_unregister_driver(&iwl_driver);
e227ceac 3181 iwlagn_rate_control_unregister();
b481de9c
ZY
3182}
3183
5b9f8cd3
EG
3184module_exit(iwl_exit);
3185module_init(iwl_init);
a562a9dd
RC
3186
3187#ifdef CONFIG_IWLWIFI_DEBUG
3188module_param_named(debug50, iwl_debug_level, uint, 0444);
3189MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
3190module_param_named(debug, iwl_debug_level, uint, 0644);
3191MODULE_PARM_DESC(debug, "debug output mask");
3192#endif
3193
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