Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/wireless.h> | |
39 | #include <linux/firmware.h> | |
b481de9c ZY |
40 | #include <linux/etherdevice.h> |
41 | #include <linux/if_arp.h> | |
42 | ||
b481de9c ZY |
43 | #include <net/mac80211.h> |
44 | ||
45 | #include <asm/div64.h> | |
46 | ||
a3139c59 SO |
47 | #define DRV_NAME "iwlagn" |
48 | ||
6bc913bd | 49 | #include "iwl-eeprom.h" |
3e0d4cb1 | 50 | #include "iwl-dev.h" |
fee1247a | 51 | #include "iwl-core.h" |
3395f6e9 | 52 | #include "iwl-io.h" |
b481de9c | 53 | #include "iwl-helpers.h" |
6974e363 | 54 | #include "iwl-sta.h" |
f0832f13 | 55 | #include "iwl-calib.h" |
b481de9c | 56 | |
416e1438 | 57 | |
b481de9c ZY |
58 | /****************************************************************************** |
59 | * | |
60 | * module boiler plate | |
61 | * | |
62 | ******************************************************************************/ | |
63 | ||
b481de9c ZY |
64 | /* |
65 | * module name, copyright, version, etc. | |
b481de9c | 66 | */ |
d783b061 | 67 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 68 | |
0a6857e7 | 69 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
70 | #define VD "d" |
71 | #else | |
72 | #define VD | |
73 | #endif | |
74 | ||
80bc5393 | 75 | #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT |
b481de9c ZY |
76 | #define VS "s" |
77 | #else | |
78 | #define VS | |
79 | #endif | |
80 | ||
df48c323 | 81 | #define DRV_VERSION IWLWIFI_VERSION VD VS |
b481de9c | 82 | |
b481de9c ZY |
83 | |
84 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
85 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 86 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c | 87 | MODULE_LICENSE("GPL"); |
4fc22b21 | 88 | MODULE_ALIAS("iwl4965"); |
b481de9c | 89 | |
b481de9c | 90 | /*************** STATION TABLE MANAGEMENT **** |
9fbab516 | 91 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
92 | * the functionality provided here |
93 | */ | |
94 | ||
95 | /**************************************************************/ | |
96 | ||
b481de9c | 97 | /** |
5b9f8cd3 | 98 | * iwl_commit_rxon - commit staging_rxon to hardware |
b481de9c | 99 | * |
01ebd063 | 100 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
101 | * the active_rxon structure is updated with the new data. This |
102 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
103 | * a HW tune is required based on the RXON structure changes. | |
104 | */ | |
e0158e61 | 105 | int iwl_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
106 | { |
107 | /* cast away the const for active_rxon in this function */ | |
c1adf9fb | 108 | struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
43d59b32 EG |
109 | int ret; |
110 | bool new_assoc = | |
111 | !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK); | |
b481de9c | 112 | |
fee1247a | 113 | if (!iwl_is_alive(priv)) |
43d59b32 | 114 | return -EBUSY; |
b481de9c ZY |
115 | |
116 | /* always get timestamp with Rx frame */ | |
117 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
a326a5d0 EG |
118 | /* allow CTS-to-self if possible. this is relevant only for |
119 | * 5000, but will not damage 4965 */ | |
120 | priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN; | |
b481de9c | 121 | |
8ccde88a | 122 | ret = iwl_check_rxon_cmd(priv); |
43d59b32 | 123 | if (ret) { |
15b1687c | 124 | IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); |
b481de9c ZY |
125 | return -EINVAL; |
126 | } | |
127 | ||
128 | /* If we don't need to send a full RXON, we can use | |
5b9f8cd3 | 129 | * iwl_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 130 | * and other flags for the current radio configuration. */ |
54559703 | 131 | if (!iwl_full_rxon_required(priv)) { |
43d59b32 EG |
132 | ret = iwl_send_rxon_assoc(priv); |
133 | if (ret) { | |
15b1687c | 134 | IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret); |
43d59b32 | 135 | return ret; |
b481de9c ZY |
136 | } |
137 | ||
138 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
139 | return 0; |
140 | } | |
141 | ||
142 | /* station table will be cleared */ | |
143 | priv->assoc_station_added = 0; | |
144 | ||
b481de9c ZY |
145 | /* If we are currently associated and the new config requires |
146 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
147 | * we must clear the associated from the active configuration | |
148 | * before we apply the new config */ | |
43d59b32 | 149 | if (iwl_is_associated(priv) && new_assoc) { |
e1623446 | 150 | IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n"); |
b481de9c ZY |
151 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
152 | ||
43d59b32 | 153 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, |
c1adf9fb | 154 | sizeof(struct iwl_rxon_cmd), |
b481de9c ZY |
155 | &priv->active_rxon); |
156 | ||
157 | /* If the mask clearing failed then we set | |
158 | * active_rxon back to what it was previously */ | |
43d59b32 | 159 | if (ret) { |
b481de9c | 160 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; |
15b1687c | 161 | IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret); |
43d59b32 | 162 | return ret; |
b481de9c | 163 | } |
b481de9c ZY |
164 | } |
165 | ||
e1623446 | 166 | IWL_DEBUG_INFO(priv, "Sending RXON\n" |
b481de9c ZY |
167 | "* with%s RXON_FILTER_ASSOC_MSK\n" |
168 | "* channel = %d\n" | |
e174961c | 169 | "* bssid = %pM\n", |
43d59b32 | 170 | (new_assoc ? "" : "out"), |
b481de9c | 171 | le16_to_cpu(priv->staging_rxon.channel), |
e174961c | 172 | priv->staging_rxon.bssid_addr); |
b481de9c | 173 | |
5b9f8cd3 | 174 | iwl_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto); |
43d59b32 EG |
175 | |
176 | /* Apply the new configuration | |
177 | * RXON unassoc clears the station table in uCode, send it before | |
178 | * we add the bcast station. If assoc bit is set, we will send RXON | |
179 | * after having added the bcast and bssid station. | |
180 | */ | |
181 | if (!new_assoc) { | |
182 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
c1adf9fb | 183 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); |
43d59b32 | 184 | if (ret) { |
15b1687c | 185 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
186 | return ret; |
187 | } | |
188 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
189 | } |
190 | ||
e11bc028 | 191 | priv->cfg->ops->smgmt->clear_station_table(priv); |
556f8db7 | 192 | |
b481de9c ZY |
193 | if (!priv->error_recovering) |
194 | priv->start_calib = 0; | |
195 | ||
b481de9c | 196 | /* Add the broadcast address so we can send broadcast frames */ |
4f40e4d9 | 197 | if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) == |
43d59b32 | 198 | IWL_INVALID_STATION) { |
15b1687c | 199 | IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n"); |
b481de9c ZY |
200 | return -EIO; |
201 | } | |
202 | ||
203 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
204 | * add the IWL_AP_ID to the station rate table */ | |
9185159d | 205 | if (new_assoc) { |
05c914fe | 206 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
9185159d TW |
207 | ret = iwl_rxon_add_station(priv, |
208 | priv->active_rxon.bssid_addr, 1); | |
209 | if (ret == IWL_INVALID_STATION) { | |
15b1687c WT |
210 | IWL_ERR(priv, |
211 | "Error adding AP address for TX.\n"); | |
9185159d TW |
212 | return -EIO; |
213 | } | |
214 | priv->assoc_station_added = 1; | |
215 | if (priv->default_wep_key && | |
216 | iwl_send_static_wepkey_cmd(priv, 0)) | |
15b1687c WT |
217 | IWL_ERR(priv, |
218 | "Could not send WEP static key.\n"); | |
b481de9c | 219 | } |
43d59b32 EG |
220 | |
221 | /* Apply the new configuration | |
222 | * RXON assoc doesn't clear the station table in uCode, | |
223 | */ | |
224 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
225 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); | |
226 | if (ret) { | |
15b1687c | 227 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
228 | return ret; |
229 | } | |
230 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
231 | } |
232 | ||
36da7d70 ZY |
233 | iwl_init_sensitivity(priv); |
234 | ||
235 | /* If we issue a new RXON command which required a tune then we must | |
236 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
237 | ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true); | |
238 | if (ret) { | |
15b1687c | 239 | IWL_ERR(priv, "Error sending TX power (%d)\n", ret); |
36da7d70 ZY |
240 | return ret; |
241 | } | |
242 | ||
b481de9c ZY |
243 | return 0; |
244 | } | |
245 | ||
5b9f8cd3 | 246 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f MA |
247 | { |
248 | ||
45823531 AK |
249 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
250 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
e0158e61 | 251 | iwlcore_commit_rxon(priv); |
5da4b55f MA |
252 | } |
253 | ||
fcab423d | 254 | static void iwl_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
255 | { |
256 | struct list_head *element; | |
257 | ||
e1623446 | 258 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
259 | priv->frames_count); |
260 | ||
261 | while (!list_empty(&priv->free_frames)) { | |
262 | element = priv->free_frames.next; | |
263 | list_del(element); | |
fcab423d | 264 | kfree(list_entry(element, struct iwl_frame, list)); |
b481de9c ZY |
265 | priv->frames_count--; |
266 | } | |
267 | ||
268 | if (priv->frames_count) { | |
39aadf8c | 269 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
270 | priv->frames_count); |
271 | priv->frames_count = 0; | |
272 | } | |
273 | } | |
274 | ||
fcab423d | 275 | static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv) |
b481de9c | 276 | { |
fcab423d | 277 | struct iwl_frame *frame; |
b481de9c ZY |
278 | struct list_head *element; |
279 | if (list_empty(&priv->free_frames)) { | |
280 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
281 | if (!frame) { | |
15b1687c | 282 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
283 | return NULL; |
284 | } | |
285 | ||
286 | priv->frames_count++; | |
287 | return frame; | |
288 | } | |
289 | ||
290 | element = priv->free_frames.next; | |
291 | list_del(element); | |
fcab423d | 292 | return list_entry(element, struct iwl_frame, list); |
b481de9c ZY |
293 | } |
294 | ||
fcab423d | 295 | static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) |
b481de9c ZY |
296 | { |
297 | memset(frame, 0, sizeof(*frame)); | |
298 | list_add(&frame->list, &priv->free_frames); | |
299 | } | |
300 | ||
4bf64efd TW |
301 | static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv, |
302 | struct ieee80211_hdr *hdr, | |
73ec1cc2 | 303 | int left) |
b481de9c | 304 | { |
3109ece1 | 305 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
306 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
307 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
308 | return 0; |
309 | ||
310 | if (priv->ibss_beacon->len > left) | |
311 | return 0; | |
312 | ||
313 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
314 | ||
315 | return priv->ibss_beacon->len; | |
316 | } | |
317 | ||
5b9f8cd3 | 318 | static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, |
4bf64efd TW |
319 | struct iwl_frame *frame, u8 rate) |
320 | { | |
321 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
322 | unsigned int frame_size; | |
323 | ||
324 | tx_beacon_cmd = &frame->u.beacon; | |
325 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
326 | ||
327 | tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id; | |
328 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
329 | ||
330 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, | |
4bf64efd TW |
331 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
332 | ||
333 | BUG_ON(frame_size > MAX_MPDU_SIZE); | |
334 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); | |
335 | ||
336 | if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP)) | |
337 | tx_beacon_cmd->tx.rate_n_flags = | |
338 | iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK); | |
339 | else | |
340 | tx_beacon_cmd->tx.rate_n_flags = | |
341 | iwl_hw_set_rate_n_flags(rate, 0); | |
342 | ||
343 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
344 | TX_CMD_FLG_TSF_MSK | | |
345 | TX_CMD_FLG_STA_RATE_MSK; | |
346 | ||
347 | return sizeof(*tx_beacon_cmd) + frame_size; | |
348 | } | |
5b9f8cd3 | 349 | static int iwl_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 350 | { |
fcab423d | 351 | struct iwl_frame *frame; |
b481de9c ZY |
352 | unsigned int frame_size; |
353 | int rc; | |
354 | u8 rate; | |
355 | ||
fcab423d | 356 | frame = iwl_get_free_frame(priv); |
b481de9c ZY |
357 | |
358 | if (!frame) { | |
15b1687c | 359 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
360 | "command.\n"); |
361 | return -ENOMEM; | |
362 | } | |
363 | ||
5b9f8cd3 | 364 | rate = iwl_rate_get_lowest_plcp(priv); |
b481de9c | 365 | |
5b9f8cd3 | 366 | frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 367 | |
857485c0 | 368 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
369 | &frame->u.cmd[0]); |
370 | ||
fcab423d | 371 | iwl_free_frame(priv, frame); |
b481de9c ZY |
372 | |
373 | return rc; | |
374 | } | |
375 | ||
7aaa1d79 SO |
376 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
377 | { | |
378 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
379 | ||
380 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
381 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
382 | addr |= | |
383 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
384 | ||
385 | return addr; | |
386 | } | |
387 | ||
388 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
389 | { | |
390 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
391 | ||
392 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
393 | } | |
394 | ||
395 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
396 | dma_addr_t addr, u16 len) | |
397 | { | |
398 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
399 | u16 hi_n_len = len << 4; | |
400 | ||
401 | put_unaligned_le32(addr, &tb->lo); | |
402 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
403 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
404 | ||
405 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
406 | ||
407 | tfd->num_tbs = idx + 1; | |
408 | } | |
409 | ||
410 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
411 | { | |
412 | return tfd->num_tbs & 0x1f; | |
413 | } | |
414 | ||
415 | /** | |
416 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
417 | * @priv - driver private data | |
418 | * @txq - tx queue | |
419 | * | |
420 | * Does NOT advance any TFD circular buffer read/write indexes | |
421 | * Does NOT free the TFD itself (which is within circular buffer) | |
422 | */ | |
423 | void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
424 | { | |
59606ffa | 425 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; |
7aaa1d79 SO |
426 | struct iwl_tfd *tfd; |
427 | struct pci_dev *dev = priv->pci_dev; | |
428 | int index = txq->q.read_ptr; | |
429 | int i; | |
430 | int num_tbs; | |
431 | ||
432 | tfd = &tfd_tmp[index]; | |
433 | ||
434 | /* Sanity check on number of chunks */ | |
435 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
436 | ||
437 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
438 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
439 | /* @todo issue fatal error, it is quite serious situation */ | |
440 | return; | |
441 | } | |
442 | ||
443 | /* Unmap tx_cmd */ | |
444 | if (num_tbs) | |
445 | pci_unmap_single(dev, | |
446 | pci_unmap_addr(&txq->cmd[index]->meta, mapping), | |
447 | pci_unmap_len(&txq->cmd[index]->meta, len), | |
96891cee | 448 | PCI_DMA_BIDIRECTIONAL); |
7aaa1d79 SO |
449 | |
450 | /* Unmap chunks, if any. */ | |
451 | for (i = 1; i < num_tbs; i++) { | |
452 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), | |
453 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
454 | ||
455 | if (txq->txb) { | |
456 | dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]); | |
457 | txq->txb[txq->q.read_ptr].skb[i - 1] = NULL; | |
458 | } | |
459 | } | |
460 | } | |
461 | ||
462 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
463 | struct iwl_tx_queue *txq, | |
464 | dma_addr_t addr, u16 len, | |
465 | u8 reset, u8 pad) | |
466 | { | |
467 | struct iwl_queue *q; | |
59606ffa | 468 | struct iwl_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
469 | u32 num_tbs; |
470 | ||
471 | q = &txq->q; | |
59606ffa SO |
472 | tfd_tmp = (struct iwl_tfd *)txq->tfds; |
473 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
474 | |
475 | if (reset) | |
476 | memset(tfd, 0, sizeof(*tfd)); | |
477 | ||
478 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
479 | ||
480 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
481 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
482 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
483 | IWL_NUM_OF_TBS); | |
484 | return -EINVAL; | |
485 | } | |
486 | ||
487 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
488 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
489 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
490 | (unsigned long long)addr); | |
491 | ||
492 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
a8e74e27 SO |
497 | /* |
498 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
499 | * given Tx queue, and enable the DMA channel used for that queue. | |
500 | * | |
501 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
502 | * channels supported in hardware. | |
503 | */ | |
504 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
505 | struct iwl_tx_queue *txq) | |
506 | { | |
507 | int ret; | |
508 | unsigned long flags; | |
509 | int txq_id = txq->q.id; | |
510 | ||
511 | spin_lock_irqsave(&priv->lock, flags); | |
512 | ret = iwl_grab_nic_access(priv); | |
513 | if (ret) { | |
514 | spin_unlock_irqrestore(&priv->lock, flags); | |
515 | return ret; | |
516 | } | |
517 | ||
518 | /* Circular buffer (TFD queue in DRAM) physical base address */ | |
519 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
520 | txq->q.dma_addr >> 8); | |
521 | ||
522 | iwl_release_nic_access(priv); | |
523 | spin_unlock_irqrestore(&priv->lock, flags); | |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
528 | ||
b481de9c ZY |
529 | /****************************************************************************** |
530 | * | |
531 | * Misc. internal state and helper functions | |
532 | * | |
533 | ******************************************************************************/ | |
b481de9c | 534 | |
b481de9c | 535 | #define MAX_UCODE_BEACON_INTERVAL 4096 |
b481de9c | 536 | |
3195c1f3 | 537 | static u16 iwl_adjust_beacon_interval(u16 beacon_val) |
b481de9c ZY |
538 | { |
539 | u16 new_val = 0; | |
540 | u16 beacon_factor = 0; | |
541 | ||
3195c1f3 TW |
542 | beacon_factor = (beacon_val + MAX_UCODE_BEACON_INTERVAL) |
543 | / MAX_UCODE_BEACON_INTERVAL; | |
b481de9c ZY |
544 | new_val = beacon_val / beacon_factor; |
545 | ||
41d2f291 JL |
546 | if (!new_val) |
547 | new_val = MAX_UCODE_BEACON_INTERVAL; | |
548 | ||
3195c1f3 | 549 | return new_val; |
b481de9c ZY |
550 | } |
551 | ||
3195c1f3 | 552 | static void iwl_setup_rxon_timing(struct iwl_priv *priv) |
b481de9c | 553 | { |
3195c1f3 TW |
554 | u64 tsf; |
555 | s32 interval_tm, rem; | |
b481de9c ZY |
556 | unsigned long flags; |
557 | struct ieee80211_conf *conf = NULL; | |
558 | u16 beacon_int = 0; | |
559 | ||
560 | conf = ieee80211_get_hw_conf(priv->hw); | |
561 | ||
562 | spin_lock_irqsave(&priv->lock, flags); | |
3195c1f3 | 563 | priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp); |
b5d7be5e | 564 | priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval); |
b481de9c | 565 | |
05c914fe | 566 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
3195c1f3 | 567 | beacon_int = iwl_adjust_beacon_interval(priv->beacon_int); |
b481de9c ZY |
568 | priv->rxon_timing.atim_window = 0; |
569 | } else { | |
3195c1f3 TW |
570 | beacon_int = iwl_adjust_beacon_interval(conf->beacon_int); |
571 | ||
b481de9c ZY |
572 | /* TODO: we need to get atim_window from upper stack |
573 | * for now we set to 0 */ | |
574 | priv->rxon_timing.atim_window = 0; | |
575 | } | |
576 | ||
3195c1f3 | 577 | priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int); |
b481de9c | 578 | |
3195c1f3 TW |
579 | tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */ |
580 | interval_tm = beacon_int * 1024; | |
581 | rem = do_div(tsf, interval_tm); | |
582 | priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem); | |
583 | ||
584 | spin_unlock_irqrestore(&priv->lock, flags); | |
e1623446 | 585 | IWL_DEBUG_ASSOC(priv, "beacon interval %d beacon timer %d beacon tim %d\n", |
3195c1f3 TW |
586 | le16_to_cpu(priv->rxon_timing.beacon_interval), |
587 | le32_to_cpu(priv->rxon_timing.beacon_init_val), | |
588 | le16_to_cpu(priv->rxon_timing.atim_window)); | |
b481de9c ZY |
589 | } |
590 | ||
b481de9c ZY |
591 | /****************************************************************************** |
592 | * | |
593 | * Generic RX handler implementations | |
594 | * | |
595 | ******************************************************************************/ | |
885ba202 TW |
596 | static void iwl_rx_reply_alive(struct iwl_priv *priv, |
597 | struct iwl_rx_mem_buffer *rxb) | |
b481de9c | 598 | { |
db11d634 | 599 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
885ba202 | 600 | struct iwl_alive_resp *palive; |
b481de9c ZY |
601 | struct delayed_work *pwork; |
602 | ||
603 | palive = &pkt->u.alive_frame; | |
604 | ||
e1623446 | 605 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
606 | "0x%01X 0x%01X\n", |
607 | palive->is_valid, palive->ver_type, | |
608 | palive->ver_subtype); | |
609 | ||
610 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 611 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
b481de9c ZY |
612 | memcpy(&priv->card_alive_init, |
613 | &pkt->u.alive_frame, | |
885ba202 | 614 | sizeof(struct iwl_init_alive_resp)); |
b481de9c ZY |
615 | pwork = &priv->init_alive_start; |
616 | } else { | |
e1623446 | 617 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 618 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
885ba202 | 619 | sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
620 | pwork = &priv->alive_start; |
621 | } | |
622 | ||
623 | /* We delay the ALIVE response by 5ms to | |
624 | * give the HW RF Kill time to activate... */ | |
625 | if (palive->is_valid == UCODE_VALID_OK) | |
626 | queue_delayed_work(priv->workqueue, pwork, | |
627 | msecs_to_jiffies(5)); | |
628 | else | |
39aadf8c | 629 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
630 | } |
631 | ||
5b9f8cd3 | 632 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 633 | { |
c79dd5b5 TW |
634 | struct iwl_priv *priv = |
635 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
636 | struct sk_buff *beacon; |
637 | ||
638 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 639 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
640 | |
641 | if (!beacon) { | |
15b1687c | 642 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
643 | return; |
644 | } | |
645 | ||
646 | mutex_lock(&priv->mutex); | |
647 | /* new beacon skb is allocated every time; dispose previous.*/ | |
648 | if (priv->ibss_beacon) | |
649 | dev_kfree_skb(priv->ibss_beacon); | |
650 | ||
651 | priv->ibss_beacon = beacon; | |
652 | mutex_unlock(&priv->mutex); | |
653 | ||
5b9f8cd3 | 654 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
655 | } |
656 | ||
4e39317d | 657 | /** |
5b9f8cd3 | 658 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
659 | * |
660 | * This callback is provided in order to send a statistics request. | |
661 | * | |
662 | * This timer function is continually reset to execute within | |
663 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
664 | * was received. We need to ensure we receive the statistics in order | |
665 | * to update the temperature used for calibrating the TXPOWER. | |
666 | */ | |
5b9f8cd3 | 667 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
668 | { |
669 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
670 | ||
671 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
672 | return; | |
673 | ||
61780ee3 MA |
674 | /* dont send host command if rf-kill is on */ |
675 | if (!iwl_is_ready_rf(priv)) | |
676 | return; | |
677 | ||
4e39317d EG |
678 | iwl_send_statistics_request(priv, CMD_ASYNC); |
679 | } | |
680 | ||
5b9f8cd3 | 681 | static void iwl_rx_beacon_notif(struct iwl_priv *priv, |
a55360e4 | 682 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 683 | { |
0a6857e7 | 684 | #ifdef CONFIG_IWLWIFI_DEBUG |
db11d634 | 685 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
2aa6ab86 TW |
686 | struct iwl4965_beacon_notif *beacon = |
687 | (struct iwl4965_beacon_notif *)pkt->u.raw; | |
e7d326ac | 688 | u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
b481de9c | 689 | |
e1623446 | 690 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c | 691 | "tsf %d %d rate %d\n", |
25a6572c | 692 | le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, |
b481de9c ZY |
693 | beacon->beacon_notify_hdr.failure_frame, |
694 | le32_to_cpu(beacon->ibss_mgr_status), | |
695 | le32_to_cpu(beacon->high_tsf), | |
696 | le32_to_cpu(beacon->low_tsf), rate); | |
697 | #endif | |
698 | ||
05c914fe | 699 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
700 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
701 | queue_work(priv->workqueue, &priv->beacon_update); | |
702 | } | |
703 | ||
b481de9c ZY |
704 | /* Handle notification from uCode that card's power state is changing |
705 | * due to software, hardware, or critical temperature RFKILL */ | |
5b9f8cd3 | 706 | static void iwl_rx_card_state_notif(struct iwl_priv *priv, |
a55360e4 | 707 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 708 | { |
db11d634 | 709 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
710 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
711 | unsigned long status = priv->status; | |
712 | ||
e1623446 | 713 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n", |
b481de9c ZY |
714 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
715 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
716 | ||
717 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
718 | RF_CARD_DISABLED)) { | |
719 | ||
3395f6e9 | 720 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
721 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
722 | ||
3395f6e9 TW |
723 | if (!iwl_grab_nic_access(priv)) { |
724 | iwl_write_direct32( | |
b481de9c ZY |
725 | priv, HBUS_TARG_MBX_C, |
726 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
727 | ||
3395f6e9 | 728 | iwl_release_nic_access(priv); |
b481de9c ZY |
729 | } |
730 | ||
731 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 732 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 733 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
3395f6e9 TW |
734 | if (!iwl_grab_nic_access(priv)) { |
735 | iwl_write_direct32( | |
b481de9c ZY |
736 | priv, HBUS_TARG_MBX_C, |
737 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
738 | ||
3395f6e9 | 739 | iwl_release_nic_access(priv); |
b481de9c ZY |
740 | } |
741 | } | |
742 | ||
743 | if (flags & RF_CARD_DISABLED) { | |
3395f6e9 | 744 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c | 745 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
3395f6e9 TW |
746 | iwl_read32(priv, CSR_UCODE_DRV_GP1); |
747 | if (!iwl_grab_nic_access(priv)) | |
748 | iwl_release_nic_access(priv); | |
b481de9c ZY |
749 | } |
750 | } | |
751 | ||
752 | if (flags & HW_CARD_DISABLED) | |
753 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
754 | else | |
755 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
756 | ||
757 | ||
758 | if (flags & SW_CARD_DISABLED) | |
759 | set_bit(STATUS_RF_KILL_SW, &priv->status); | |
760 | else | |
761 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
762 | ||
763 | if (!(flags & RXON_CARD_DISABLED)) | |
2a421b91 | 764 | iwl_scan_cancel(priv); |
b481de9c ZY |
765 | |
766 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
767 | test_bit(STATUS_RF_KILL_HW, &priv->status)) || | |
768 | (test_bit(STATUS_RF_KILL_SW, &status) != | |
769 | test_bit(STATUS_RF_KILL_SW, &priv->status))) | |
770 | queue_work(priv->workqueue, &priv->rf_kill); | |
771 | else | |
772 | wake_up_interruptible(&priv->wait_command_queue); | |
773 | } | |
774 | ||
5b9f8cd3 | 775 | int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) |
e2e3c57b TW |
776 | { |
777 | int ret; | |
778 | unsigned long flags; | |
779 | ||
780 | spin_lock_irqsave(&priv->lock, flags); | |
781 | ret = iwl_grab_nic_access(priv); | |
782 | if (ret) | |
783 | goto err; | |
784 | ||
785 | if (src == IWL_PWR_SRC_VAUX) { | |
3fdb68de | 786 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) |
e2e3c57b TW |
787 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
788 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
789 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
790 | } else { | |
791 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
792 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
793 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
794 | } | |
795 | ||
796 | iwl_release_nic_access(priv); | |
797 | err: | |
798 | spin_unlock_irqrestore(&priv->lock, flags); | |
799 | return ret; | |
800 | } | |
801 | ||
b481de9c | 802 | /** |
5b9f8cd3 | 803 | * iwl_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
804 | * |
805 | * Setup the RX handlers for each of the reply types sent from the uCode | |
806 | * to the host. | |
807 | * | |
808 | * This function chains into the hardware specific files for them to setup | |
809 | * any hardware specific handlers as well. | |
810 | */ | |
653fa4a0 | 811 | static void iwl_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 812 | { |
885ba202 | 813 | priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive; |
5b9f8cd3 EG |
814 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
815 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; | |
5b9f8cd3 | 816 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 817 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
5b9f8cd3 EG |
818 | iwl_rx_pm_debug_statistics_notif; |
819 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif; | |
b481de9c | 820 | |
9fbab516 BC |
821 | /* |
822 | * The same handler is used for both the REPLY to a discrete | |
823 | * statistics request from the host as well as for the periodic | |
824 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 825 | */ |
8f91aecb EG |
826 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics; |
827 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics; | |
2a421b91 | 828 | |
21c339bf | 829 | iwl_setup_spectrum_handlers(priv); |
2a421b91 TW |
830 | iwl_setup_rx_scan_handlers(priv); |
831 | ||
37a44211 | 832 | /* status change handler */ |
5b9f8cd3 | 833 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif; |
b481de9c | 834 | |
c1354754 TW |
835 | priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] = |
836 | iwl_rx_missed_beacon_notif; | |
37a44211 | 837 | /* Rx handlers */ |
1781a07f EG |
838 | priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy; |
839 | priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx; | |
653fa4a0 EG |
840 | /* block ack */ |
841 | priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba; | |
9fbab516 | 842 | /* Set up hardware specific Rx handlers */ |
d4789efe | 843 | priv->cfg->ops->lib->rx_handler_setup(priv); |
b481de9c ZY |
844 | } |
845 | ||
b481de9c | 846 | /** |
a55360e4 | 847 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
848 | * |
849 | * Uses the priv->rx_handlers callback function array to invoke | |
850 | * the appropriate handlers, including command responses, | |
851 | * frame-received notifications, and other notifications. | |
852 | */ | |
a55360e4 | 853 | void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 854 | { |
a55360e4 | 855 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 856 | struct iwl_rx_packet *pkt; |
a55360e4 | 857 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
858 | u32 r, i; |
859 | int reclaim; | |
860 | unsigned long flags; | |
5c0eef96 | 861 | u8 fill_rx = 0; |
d68ab680 | 862 | u32 count = 8; |
b481de9c | 863 | |
6440adb5 CB |
864 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
865 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 866 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
867 | i = rxq->read; |
868 | ||
869 | /* Rx interrupt, but nothing sent from uCode */ | |
870 | if (i == r) | |
e1623446 | 871 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c | 872 | |
a55360e4 | 873 | if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2)) |
5c0eef96 MA |
874 | fill_rx = 1; |
875 | ||
b481de9c ZY |
876 | while (i != r) { |
877 | rxb = rxq->queue[i]; | |
878 | ||
9fbab516 | 879 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
880 | * then a bug has been introduced in the queue refilling |
881 | * routines -- catch it here */ | |
882 | BUG_ON(rxb == NULL); | |
883 | ||
884 | rxq->queue[i] = NULL; | |
885 | ||
e91af0af JB |
886 | dma_sync_single_range_for_cpu( |
887 | &priv->pci_dev->dev, rxb->real_dma_addr, | |
888 | rxb->aligned_dma_addr - rxb->real_dma_addr, | |
889 | priv->hw_params.rx_buf_size, | |
890 | PCI_DMA_FROMDEVICE); | |
db11d634 | 891 | pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
892 | |
893 | /* Reclaim a command buffer only if this packet is a response | |
894 | * to a (driver-originated) command. | |
895 | * If the packet (e.g. Rx frame) originated from uCode, | |
896 | * there is no command buffer to reclaim. | |
897 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
898 | * but apparently a few don't get set; catch them here. */ | |
899 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
900 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 901 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 902 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 903 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
904 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
905 | (pkt->hdr.cmd != REPLY_TX); | |
906 | ||
907 | /* Based on type of command response or notification, | |
908 | * handle those that need handling via function in | |
5b9f8cd3 | 909 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 910 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 911 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, |
f3d67999 | 912 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
b481de9c | 913 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
a83b9141 | 914 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
b481de9c ZY |
915 | } else { |
916 | /* No handling needed */ | |
e1623446 | 917 | IWL_DEBUG_RX(priv, |
b481de9c ZY |
918 | "r %d i %d No handler needed for %s, 0x%02x\n", |
919 | r, i, get_cmd_string(pkt->hdr.cmd), | |
920 | pkt->hdr.cmd); | |
921 | } | |
922 | ||
923 | if (reclaim) { | |
9fbab516 | 924 | /* Invoke any callbacks, transfer the skb to caller, and |
857485c0 | 925 | * fire off the (possibly) blocking iwl_send_cmd() |
b481de9c ZY |
926 | * as we reclaim the driver command queue */ |
927 | if (rxb && rxb->skb) | |
17b88929 | 928 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 929 | else |
39aadf8c | 930 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
931 | } |
932 | ||
933 | /* For now we just don't re-use anything. We can tweak this | |
934 | * later to try and re-use notification packets and SKBs that | |
935 | * fail to Rx correctly */ | |
936 | if (rxb->skb != NULL) { | |
937 | priv->alloc_rxb_skb--; | |
938 | dev_kfree_skb_any(rxb->skb); | |
939 | rxb->skb = NULL; | |
940 | } | |
941 | ||
4018517a JB |
942 | pci_unmap_single(priv->pci_dev, rxb->real_dma_addr, |
943 | priv->hw_params.rx_buf_size + 256, | |
9ee1ba47 | 944 | PCI_DMA_FROMDEVICE); |
b481de9c ZY |
945 | spin_lock_irqsave(&rxq->lock, flags); |
946 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
947 | spin_unlock_irqrestore(&rxq->lock, flags); | |
948 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
949 | /* If there are a lot of unused frames, |
950 | * restock the Rx queue so ucode wont assert. */ | |
951 | if (fill_rx) { | |
952 | count++; | |
953 | if (count >= 8) { | |
954 | priv->rxq.read = i; | |
f1bc4ac6 | 955 | iwl_rx_queue_restock(priv); |
5c0eef96 MA |
956 | count = 0; |
957 | } | |
958 | } | |
b481de9c ZY |
959 | } |
960 | ||
961 | /* Backtrack one entry */ | |
962 | priv->rxq.read = i; | |
a55360e4 TW |
963 | iwl_rx_queue_restock(priv); |
964 | } | |
a55360e4 | 965 | |
0359facc MA |
966 | /* call this function to flush any scheduled tasklet */ |
967 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
968 | { | |
a96a27f9 | 969 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
970 | synchronize_irq(priv->pci_dev->irq); |
971 | tasklet_kill(&priv->irq_tasklet); | |
972 | } | |
973 | ||
5b9f8cd3 | 974 | static void iwl_error_recovery(struct iwl_priv *priv) |
b481de9c ZY |
975 | { |
976 | unsigned long flags; | |
977 | ||
978 | memcpy(&priv->staging_rxon, &priv->recovery_rxon, | |
979 | sizeof(priv->staging_rxon)); | |
980 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 981 | iwlcore_commit_rxon(priv); |
b481de9c | 982 | |
4f40e4d9 | 983 | iwl_rxon_add_station(priv, priv->bssid, 1); |
b481de9c ZY |
984 | |
985 | spin_lock_irqsave(&priv->lock, flags); | |
986 | priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id); | |
987 | priv->error_recovering = 0; | |
988 | spin_unlock_irqrestore(&priv->lock, flags); | |
989 | } | |
990 | ||
5b9f8cd3 | 991 | static void iwl_irq_tasklet(struct iwl_priv *priv) |
b481de9c ZY |
992 | { |
993 | u32 inta, handled = 0; | |
994 | u32 inta_fh; | |
995 | unsigned long flags; | |
0a6857e7 | 996 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
997 | u32 inta_mask; |
998 | #endif | |
999 | ||
1000 | spin_lock_irqsave(&priv->lock, flags); | |
1001 | ||
1002 | /* Ack/clear/reset pending uCode interrupts. | |
1003 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1004 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
1005 | inta = iwl_read32(priv, CSR_INT); |
1006 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
1007 | |
1008 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1009 | * Any new interrupts that happen after this, either while we're | |
1010 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
1011 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1012 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 1013 | |
0a6857e7 | 1014 | #ifdef CONFIG_IWLWIFI_DEBUG |
bf403db8 | 1015 | if (priv->debug_level & IWL_DL_ISR) { |
9fbab516 | 1016 | /* just for debug */ |
3395f6e9 | 1017 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 1018 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
1019 | inta, inta_mask, inta_fh); |
1020 | } | |
1021 | #endif | |
1022 | ||
1023 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
1024 | * atomic, make sure that inta covers all the interrupts that | |
1025 | * we've discovered, even if FH interrupt came in just after | |
1026 | * reading CSR_INT. */ | |
6f83eaa1 | 1027 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 1028 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 1029 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
1030 | inta |= CSR_INT_BIT_FH_TX; |
1031 | ||
1032 | /* Now service all interrupt bits discovered above. */ | |
1033 | if (inta & CSR_INT_BIT_HW_ERR) { | |
15b1687c | 1034 | IWL_ERR(priv, "Microcode HW error detected. Restarting.\n"); |
b481de9c ZY |
1035 | |
1036 | /* Tell the device to stop sending interrupts */ | |
5b9f8cd3 | 1037 | iwl_disable_interrupts(priv); |
b481de9c | 1038 | |
a83b9141 | 1039 | priv->isr_stats.hw++; |
5b9f8cd3 | 1040 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1041 | |
1042 | handled |= CSR_INT_BIT_HW_ERR; | |
1043 | ||
1044 | spin_unlock_irqrestore(&priv->lock, flags); | |
1045 | ||
1046 | return; | |
1047 | } | |
1048 | ||
0a6857e7 | 1049 | #ifdef CONFIG_IWLWIFI_DEBUG |
bf403db8 | 1050 | if (priv->debug_level & (IWL_DL_ISR)) { |
b481de9c | 1051 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
a83b9141 | 1052 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 1053 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 1054 | "the frame/frames.\n"); |
a83b9141 WYG |
1055 | priv->isr_stats.sch++; |
1056 | } | |
b481de9c ZY |
1057 | |
1058 | /* Alive notification via Rx interrupt will do the real work */ | |
a83b9141 | 1059 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 1060 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
a83b9141 WYG |
1061 | priv->isr_stats.alive++; |
1062 | } | |
b481de9c ZY |
1063 | } |
1064 | #endif | |
1065 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1066 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1067 | |
9fbab516 | 1068 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
1069 | if (inta & CSR_INT_BIT_RF_KILL) { |
1070 | int hw_rf_kill = 0; | |
3395f6e9 | 1071 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
1072 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
1073 | hw_rf_kill = 1; | |
1074 | ||
e1623446 | 1075 | IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n", |
c3056065 | 1076 | hw_rf_kill ? "disable radio" : "enable radio"); |
b481de9c | 1077 | |
a83b9141 WYG |
1078 | priv->isr_stats.rfkill++; |
1079 | ||
a9efa652 | 1080 | /* driver only loads ucode once setting the interface up. |
6cd0b1cb HS |
1081 | * the driver allows loading the ucode even if the radio |
1082 | * is killed. Hence update the killswitch state here. The | |
1083 | * rfkill handler will care about restarting if needed. | |
a9efa652 | 1084 | */ |
6cd0b1cb HS |
1085 | if (!test_bit(STATUS_ALIVE, &priv->status)) { |
1086 | if (hw_rf_kill) | |
1087 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1088 | else | |
1089 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
1090 | queue_work(priv->workqueue, &priv->rf_kill); | |
edb34228 | 1091 | } |
b481de9c ZY |
1092 | |
1093 | handled |= CSR_INT_BIT_RF_KILL; | |
1094 | } | |
1095 | ||
9fbab516 | 1096 | /* Chip got too hot and stopped itself */ |
b481de9c | 1097 | if (inta & CSR_INT_BIT_CT_KILL) { |
15b1687c | 1098 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); |
a83b9141 | 1099 | priv->isr_stats.ctkill++; |
b481de9c ZY |
1100 | handled |= CSR_INT_BIT_CT_KILL; |
1101 | } | |
1102 | ||
1103 | /* Error detected by uCode */ | |
1104 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1105 | IWL_ERR(priv, "Microcode SW error detected. " |
1106 | " Restarting 0x%X.\n", inta); | |
a83b9141 WYG |
1107 | priv->isr_stats.sw++; |
1108 | priv->isr_stats.sw_err = inta; | |
5b9f8cd3 | 1109 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1110 | handled |= CSR_INT_BIT_SW_ERR; |
1111 | } | |
1112 | ||
1113 | /* uCode wakes up after power-down sleep */ | |
1114 | if (inta & CSR_INT_BIT_WAKEUP) { | |
e1623446 | 1115 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
a55360e4 | 1116 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
babcebfa TW |
1117 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); |
1118 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1119 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1120 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1121 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1122 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c | 1123 | |
a83b9141 WYG |
1124 | priv->isr_stats.wakeup++; |
1125 | ||
b481de9c ZY |
1126 | handled |= CSR_INT_BIT_WAKEUP; |
1127 | } | |
1128 | ||
1129 | /* All uCode command responses, including Tx command responses, | |
1130 | * Rx "responses" (frame-received notification), and other | |
1131 | * notifications from uCode come through here*/ | |
1132 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
a55360e4 | 1133 | iwl_rx_handle(priv); |
a83b9141 | 1134 | priv->isr_stats.rx++; |
b481de9c ZY |
1135 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1136 | } | |
1137 | ||
1138 | if (inta & CSR_INT_BIT_FH_TX) { | |
e1623446 | 1139 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); |
a83b9141 | 1140 | priv->isr_stats.tx++; |
b481de9c | 1141 | handled |= CSR_INT_BIT_FH_TX; |
dbb983b7 RR |
1142 | /* FH finished to write, send event */ |
1143 | priv->ucode_write_complete = 1; | |
1144 | wake_up_interruptible(&priv->wait_command_queue); | |
b481de9c ZY |
1145 | } |
1146 | ||
a83b9141 | 1147 | if (inta & ~handled) { |
15b1687c | 1148 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
a83b9141 WYG |
1149 | priv->isr_stats.unhandled++; |
1150 | } | |
b481de9c ZY |
1151 | |
1152 | if (inta & ~CSR_INI_SET_MASK) { | |
39aadf8c | 1153 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
b481de9c | 1154 | inta & ~CSR_INI_SET_MASK); |
39aadf8c | 1155 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1156 | } |
1157 | ||
1158 | /* Re-enable all interrupts */ | |
0359facc MA |
1159 | /* only Re-enable if diabled by irq */ |
1160 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
5b9f8cd3 | 1161 | iwl_enable_interrupts(priv); |
b481de9c | 1162 | |
0a6857e7 | 1163 | #ifdef CONFIG_IWLWIFI_DEBUG |
bf403db8 | 1164 | if (priv->debug_level & (IWL_DL_ISR)) { |
3395f6e9 TW |
1165 | inta = iwl_read32(priv, CSR_INT); |
1166 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1167 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1168 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1169 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1170 | } | |
1171 | #endif | |
1172 | spin_unlock_irqrestore(&priv->lock, flags); | |
1173 | } | |
1174 | ||
a83b9141 | 1175 | |
b481de9c ZY |
1176 | /****************************************************************************** |
1177 | * | |
1178 | * uCode download functions | |
1179 | * | |
1180 | ******************************************************************************/ | |
1181 | ||
5b9f8cd3 | 1182 | static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1183 | { |
98c92211 TW |
1184 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1185 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1186 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1187 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1188 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1189 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1190 | } |
1191 | ||
5b9f8cd3 | 1192 | static void iwl_nic_start(struct iwl_priv *priv) |
edcdf8b2 RR |
1193 | { |
1194 | /* Remove all resets to allow NIC to operate */ | |
1195 | iwl_write32(priv, CSR_RESET, 0); | |
1196 | } | |
1197 | ||
1198 | ||
b481de9c | 1199 | /** |
5b9f8cd3 | 1200 | * iwl_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
1201 | * |
1202 | * Copy into buffers for card to fetch via bus-mastering | |
1203 | */ | |
5b9f8cd3 | 1204 | static int iwl_read_ucode(struct iwl_priv *priv) |
b481de9c | 1205 | { |
14b3d338 | 1206 | struct iwl_ucode *ucode; |
a0987a8d | 1207 | int ret = -EINVAL, index; |
b481de9c | 1208 | const struct firmware *ucode_raw; |
a0987a8d RC |
1209 | const char *name_pre = priv->cfg->fw_name_pre; |
1210 | const unsigned int api_max = priv->cfg->ucode_api_max; | |
1211 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
1212 | char buf[25]; | |
b481de9c ZY |
1213 | u8 *src; |
1214 | size_t len; | |
a0987a8d | 1215 | u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size; |
b481de9c ZY |
1216 | |
1217 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
1218 | * request_firmware() is synchronous, file is in memory on return. */ | |
a0987a8d RC |
1219 | for (index = api_max; index >= api_min; index--) { |
1220 | sprintf(buf, "%s%d%s", name_pre, index, ".ucode"); | |
1221 | ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); | |
1222 | if (ret < 0) { | |
15b1687c | 1223 | IWL_ERR(priv, "%s firmware file req failed: %d\n", |
a0987a8d RC |
1224 | buf, ret); |
1225 | if (ret == -ENOENT) | |
1226 | continue; | |
1227 | else | |
1228 | goto error; | |
1229 | } else { | |
1230 | if (index < api_max) | |
15b1687c WT |
1231 | IWL_ERR(priv, "Loaded firmware %s, " |
1232 | "which is deprecated. " | |
1233 | "Please use API v%u instead.\n", | |
a0987a8d | 1234 | buf, api_max); |
15b1687c | 1235 | |
e1623446 | 1236 | IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n", |
a0987a8d RC |
1237 | buf, ucode_raw->size); |
1238 | break; | |
1239 | } | |
b481de9c ZY |
1240 | } |
1241 | ||
a0987a8d RC |
1242 | if (ret < 0) |
1243 | goto error; | |
b481de9c ZY |
1244 | |
1245 | /* Make sure that we got at least our header! */ | |
1246 | if (ucode_raw->size < sizeof(*ucode)) { | |
15b1687c | 1247 | IWL_ERR(priv, "File size way too small!\n"); |
90e759d1 | 1248 | ret = -EINVAL; |
b481de9c ZY |
1249 | goto err_release; |
1250 | } | |
1251 | ||
1252 | /* Data from ucode file: header followed by uCode images */ | |
1253 | ucode = (void *)ucode_raw->data; | |
1254 | ||
c02b3acd | 1255 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 1256 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
b481de9c ZY |
1257 | inst_size = le32_to_cpu(ucode->inst_size); |
1258 | data_size = le32_to_cpu(ucode->data_size); | |
1259 | init_size = le32_to_cpu(ucode->init_size); | |
1260 | init_data_size = le32_to_cpu(ucode->init_data_size); | |
1261 | boot_size = le32_to_cpu(ucode->boot_size); | |
1262 | ||
a0987a8d RC |
1263 | /* api_ver should match the api version forming part of the |
1264 | * firmware filename ... but we don't check for that and only rely | |
877d0310 | 1265 | * on the API version read from firmware header from here on forward */ |
a0987a8d RC |
1266 | |
1267 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 1268 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
1269 | "Driver supports v%u, firmware is v%u.\n", |
1270 | api_max, api_ver); | |
1271 | priv->ucode_ver = 0; | |
1272 | ret = -EINVAL; | |
1273 | goto err_release; | |
1274 | } | |
1275 | if (api_ver != api_max) | |
978785a3 | 1276 | IWL_ERR(priv, "Firmware has old API version. Expected v%u, " |
a0987a8d RC |
1277 | "got v%u. New firmware can be obtained " |
1278 | "from http://www.intellinuxwireless.org.\n", | |
1279 | api_max, api_ver); | |
1280 | ||
978785a3 TW |
1281 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
1282 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
1283 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1284 | IWL_UCODE_API(priv->ucode_ver), | |
1285 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
a0987a8d | 1286 | |
e1623446 | 1287 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
a0987a8d | 1288 | priv->ucode_ver); |
e1623446 | 1289 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n", |
b481de9c | 1290 | inst_size); |
e1623446 | 1291 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n", |
b481de9c | 1292 | data_size); |
e1623446 | 1293 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n", |
b481de9c | 1294 | init_size); |
e1623446 | 1295 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n", |
b481de9c | 1296 | init_data_size); |
e1623446 | 1297 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n", |
b481de9c ZY |
1298 | boot_size); |
1299 | ||
1300 | /* Verify size of file vs. image size info in file's header */ | |
1301 | if (ucode_raw->size < sizeof(*ucode) + | |
1302 | inst_size + data_size + init_size + | |
1303 | init_data_size + boot_size) { | |
1304 | ||
e1623446 | 1305 | IWL_DEBUG_INFO(priv, "uCode file size %d too small\n", |
b481de9c | 1306 | (int)ucode_raw->size); |
90e759d1 | 1307 | ret = -EINVAL; |
b481de9c ZY |
1308 | goto err_release; |
1309 | } | |
1310 | ||
1311 | /* Verify that uCode images will fit in card's SRAM */ | |
099b40b7 | 1312 | if (inst_size > priv->hw_params.max_inst_size) { |
e1623446 | 1313 | IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n", |
90e759d1 TW |
1314 | inst_size); |
1315 | ret = -EINVAL; | |
b481de9c ZY |
1316 | goto err_release; |
1317 | } | |
1318 | ||
099b40b7 | 1319 | if (data_size > priv->hw_params.max_data_size) { |
e1623446 | 1320 | IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n", |
90e759d1 TW |
1321 | data_size); |
1322 | ret = -EINVAL; | |
b481de9c ZY |
1323 | goto err_release; |
1324 | } | |
099b40b7 | 1325 | if (init_size > priv->hw_params.max_inst_size) { |
e1623446 TW |
1326 | IWL_INFO(priv, "uCode init instr len %d too large to fit in\n", |
1327 | init_size); | |
90e759d1 | 1328 | ret = -EINVAL; |
b481de9c ZY |
1329 | goto err_release; |
1330 | } | |
099b40b7 | 1331 | if (init_data_size > priv->hw_params.max_data_size) { |
e1623446 | 1332 | IWL_INFO(priv, "uCode init data len %d too large to fit in\n", |
90e759d1 TW |
1333 | init_data_size); |
1334 | ret = -EINVAL; | |
b481de9c ZY |
1335 | goto err_release; |
1336 | } | |
099b40b7 | 1337 | if (boot_size > priv->hw_params.max_bsm_size) { |
e1623446 TW |
1338 | IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n", |
1339 | boot_size); | |
90e759d1 | 1340 | ret = -EINVAL; |
b481de9c ZY |
1341 | goto err_release; |
1342 | } | |
1343 | ||
1344 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
1345 | ||
1346 | /* Runtime instructions and 2 copies of data: | |
1347 | * 1) unmodified from disk | |
1348 | * 2) backup cache for save/restore during power-downs */ | |
1349 | priv->ucode_code.len = inst_size; | |
98c92211 | 1350 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
1351 | |
1352 | priv->ucode_data.len = data_size; | |
98c92211 | 1353 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
1354 | |
1355 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 1356 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 1357 | |
1f304e4e ZY |
1358 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
1359 | !priv->ucode_data_backup.v_addr) | |
1360 | goto err_pci_alloc; | |
1361 | ||
b481de9c | 1362 | /* Initialization instructions and data */ |
90e759d1 TW |
1363 | if (init_size && init_data_size) { |
1364 | priv->ucode_init.len = init_size; | |
98c92211 | 1365 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
1366 | |
1367 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 1368 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
1369 | |
1370 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
1371 | goto err_pci_alloc; | |
1372 | } | |
b481de9c ZY |
1373 | |
1374 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
1375 | if (boot_size) { |
1376 | priv->ucode_boot.len = boot_size; | |
98c92211 | 1377 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 1378 | |
90e759d1 TW |
1379 | if (!priv->ucode_boot.v_addr) |
1380 | goto err_pci_alloc; | |
1381 | } | |
b481de9c ZY |
1382 | |
1383 | /* Copy images into buffers for card's bus-master reads ... */ | |
1384 | ||
1385 | /* Runtime instructions (first block of data in file) */ | |
1386 | src = &ucode->data[0]; | |
1387 | len = priv->ucode_code.len; | |
e1623446 | 1388 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c | 1389 | memcpy(priv->ucode_code.v_addr, src, len); |
e1623446 | 1390 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
1391 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
1392 | ||
1393 | /* Runtime data (2nd block) | |
5b9f8cd3 | 1394 | * NOTE: Copy into backup buffer will be done in iwl_up() */ |
b481de9c ZY |
1395 | src = &ucode->data[inst_size]; |
1396 | len = priv->ucode_data.len; | |
e1623446 | 1397 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
1398 | memcpy(priv->ucode_data.v_addr, src, len); |
1399 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
1400 | ||
1401 | /* Initialization instructions (3rd block) */ | |
1402 | if (init_size) { | |
1403 | src = &ucode->data[inst_size + data_size]; | |
1404 | len = priv->ucode_init.len; | |
e1623446 | 1405 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n", |
90e759d1 | 1406 | len); |
b481de9c ZY |
1407 | memcpy(priv->ucode_init.v_addr, src, len); |
1408 | } | |
1409 | ||
1410 | /* Initialization data (4th block) */ | |
1411 | if (init_data_size) { | |
1412 | src = &ucode->data[inst_size + data_size + init_size]; | |
1413 | len = priv->ucode_init_data.len; | |
e1623446 | 1414 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n", |
90e759d1 | 1415 | len); |
b481de9c ZY |
1416 | memcpy(priv->ucode_init_data.v_addr, src, len); |
1417 | } | |
1418 | ||
1419 | /* Bootstrap instructions (5th block) */ | |
1420 | src = &ucode->data[inst_size + data_size + init_size + init_data_size]; | |
1421 | len = priv->ucode_boot.len; | |
e1623446 | 1422 | IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len); |
b481de9c ZY |
1423 | memcpy(priv->ucode_boot.v_addr, src, len); |
1424 | ||
1425 | /* We have our copies now, allow OS release its copies */ | |
1426 | release_firmware(ucode_raw); | |
1427 | return 0; | |
1428 | ||
1429 | err_pci_alloc: | |
15b1687c | 1430 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
90e759d1 | 1431 | ret = -ENOMEM; |
5b9f8cd3 | 1432 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
1433 | |
1434 | err_release: | |
1435 | release_firmware(ucode_raw); | |
1436 | ||
1437 | error: | |
90e759d1 | 1438 | return ret; |
b481de9c ZY |
1439 | } |
1440 | ||
b481de9c | 1441 | /** |
4a4a9e81 | 1442 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 1443 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 1444 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 1445 | */ |
4a4a9e81 | 1446 | static void iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 1447 | { |
57aab75a | 1448 | int ret = 0; |
b481de9c | 1449 | |
e1623446 | 1450 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
1451 | |
1452 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
1453 | /* We had an error bringing up the hardware, so take it | |
1454 | * all the way back down so we can try again */ | |
e1623446 | 1455 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
1456 | goto restart; |
1457 | } | |
1458 | ||
1459 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
1460 | * This is a paranoid check, because we would not have gotten the | |
1461 | * "runtime" alive if code weren't properly loaded. */ | |
b0692f2f | 1462 | if (iwl_verify_ucode(priv)) { |
b481de9c ZY |
1463 | /* Runtime instruction load was bad; |
1464 | * take it all the way back down so we can try again */ | |
e1623446 | 1465 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
1466 | goto restart; |
1467 | } | |
1468 | ||
e11bc028 | 1469 | priv->cfg->ops->smgmt->clear_station_table(priv); |
57aab75a TW |
1470 | ret = priv->cfg->ops->lib->alive_notify(priv); |
1471 | if (ret) { | |
39aadf8c WT |
1472 | IWL_WARN(priv, |
1473 | "Could not complete ALIVE transition [ntf]: %d\n", ret); | |
b481de9c ZY |
1474 | goto restart; |
1475 | } | |
1476 | ||
5b9f8cd3 | 1477 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
1478 | set_bit(STATUS_ALIVE, &priv->status); |
1479 | ||
fee1247a | 1480 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
1481 | return; |
1482 | ||
36d6825b | 1483 | ieee80211_wake_queues(priv->hw); |
b481de9c ZY |
1484 | |
1485 | priv->active_rate = priv->rates_mask; | |
1486 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
1487 | ||
3109ece1 | 1488 | if (iwl_is_associated(priv)) { |
c1adf9fb GG |
1489 | struct iwl_rxon_cmd *active_rxon = |
1490 | (struct iwl_rxon_cmd *)&priv->active_rxon; | |
019fb97d MA |
1491 | /* apply any changes in staging */ |
1492 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
b481de9c ZY |
1493 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
1494 | } else { | |
1495 | /* Initialize our rx_config data */ | |
5b9f8cd3 | 1496 | iwl_connection_init_rx_config(priv, priv->iw_mode); |
45823531 AK |
1497 | |
1498 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
1499 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
1500 | ||
b481de9c ZY |
1501 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
1502 | } | |
1503 | ||
9fbab516 | 1504 | /* Configure Bluetooth device coexistence support */ |
5b9f8cd3 | 1505 | iwl_send_bt_config(priv); |
b481de9c | 1506 | |
4a4a9e81 TW |
1507 | iwl_reset_run_time_calib(priv); |
1508 | ||
b481de9c | 1509 | /* Configure the adapter for unassociated operation */ |
e0158e61 | 1510 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
1511 | |
1512 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 1513 | iwl_rf_kill_ct_config(priv); |
5a66926a | 1514 | |
fe00b5a5 RC |
1515 | iwl_leds_register(priv); |
1516 | ||
e1623446 | 1517 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 1518 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 1519 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c ZY |
1520 | |
1521 | if (priv->error_recovering) | |
5b9f8cd3 | 1522 | iwl_error_recovery(priv); |
b481de9c | 1523 | |
58d0f361 | 1524 | iwl_power_update_mode(priv, 1); |
c46fbefa | 1525 | |
ada17513 MA |
1526 | /* reassociate for ADHOC mode */ |
1527 | if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) { | |
1528 | struct sk_buff *beacon = ieee80211_beacon_get(priv->hw, | |
1529 | priv->vif); | |
1530 | if (beacon) | |
1531 | iwl_mac_beacon_update(priv->hw, beacon); | |
1532 | } | |
1533 | ||
1534 | ||
c46fbefa | 1535 | if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status)) |
5b9f8cd3 | 1536 | iwl_set_mode(priv, priv->iw_mode); |
c46fbefa | 1537 | |
b481de9c ZY |
1538 | return; |
1539 | ||
1540 | restart: | |
1541 | queue_work(priv->workqueue, &priv->restart); | |
1542 | } | |
1543 | ||
4e39317d | 1544 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 1545 | |
5b9f8cd3 | 1546 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
1547 | { |
1548 | unsigned long flags; | |
1549 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 1550 | |
e1623446 | 1551 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 1552 | |
b481de9c ZY |
1553 | if (!exit_pending) |
1554 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
1555 | ||
ab53d8af MA |
1556 | iwl_leds_unregister(priv); |
1557 | ||
e11bc028 | 1558 | priv->cfg->ops->smgmt->clear_station_table(priv); |
b481de9c ZY |
1559 | |
1560 | /* Unblock any waiting calls */ | |
1561 | wake_up_interruptible_all(&priv->wait_command_queue); | |
1562 | ||
b481de9c ZY |
1563 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
1564 | * exiting the module */ | |
1565 | if (!exit_pending) | |
1566 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
1567 | ||
1568 | /* stop and reset the on-board processor */ | |
3395f6e9 | 1569 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
1570 | |
1571 | /* tell the device to stop sending interrupts */ | |
0359facc | 1572 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 1573 | iwl_disable_interrupts(priv); |
0359facc MA |
1574 | spin_unlock_irqrestore(&priv->lock, flags); |
1575 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
1576 | |
1577 | if (priv->mac80211_registered) | |
1578 | ieee80211_stop_queues(priv->hw); | |
1579 | ||
5b9f8cd3 | 1580 | /* If we have not previously called iwl_init() then |
6da3a13e | 1581 | * clear all bits but the RF Kill bits and return */ |
fee1247a | 1582 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
1583 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
1584 | STATUS_RF_KILL_HW | | |
1585 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
1586 | STATUS_RF_KILL_SW | | |
9788864e RC |
1587 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
1588 | STATUS_GEO_CONFIGURED | | |
052ec3f1 MA |
1589 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
1590 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
1591 | goto exit; |
1592 | } | |
1593 | ||
6da3a13e WYG |
1594 | /* ...otherwise clear out all the status bits but the RF Kill |
1595 | * bits and continue taking the NIC down. */ | |
b481de9c ZY |
1596 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
1597 | STATUS_RF_KILL_HW | | |
1598 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
1599 | STATUS_RF_KILL_SW | | |
9788864e RC |
1600 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
1601 | STATUS_GEO_CONFIGURED | | |
b481de9c | 1602 | test_bit(STATUS_FW_ERROR, &priv->status) << |
052ec3f1 MA |
1603 | STATUS_FW_ERROR | |
1604 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
1605 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
1606 | |
1607 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 | 1608 | iwl_clear_bit(priv, CSR_GP_CNTRL, |
9fbab516 | 1609 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
1610 | spin_unlock_irqrestore(&priv->lock, flags); |
1611 | ||
da1bc453 | 1612 | iwl_txq_ctx_stop(priv); |
b3bbacb7 | 1613 | iwl_rxq_stop(priv); |
b481de9c ZY |
1614 | |
1615 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 TW |
1616 | if (!iwl_grab_nic_access(priv)) { |
1617 | iwl_write_prph(priv, APMG_CLK_DIS_REG, | |
b481de9c | 1618 | APMG_CLK_VAL_DMA_CLK_RQT); |
3395f6e9 | 1619 | iwl_release_nic_access(priv); |
b481de9c ZY |
1620 | } |
1621 | spin_unlock_irqrestore(&priv->lock, flags); | |
1622 | ||
1623 | udelay(5); | |
1624 | ||
7f066108 | 1625 | /* FIXME: apm_ops.suspend(priv) */ |
6da3a13e | 1626 | if (exit_pending) |
d535311e GG |
1627 | priv->cfg->ops->lib->apm_ops.stop(priv); |
1628 | else | |
1629 | priv->cfg->ops->lib->apm_ops.reset(priv); | |
b481de9c | 1630 | exit: |
885ba202 | 1631 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
1632 | |
1633 | if (priv->ibss_beacon) | |
1634 | dev_kfree_skb(priv->ibss_beacon); | |
1635 | priv->ibss_beacon = NULL; | |
1636 | ||
1637 | /* clear out any free frames */ | |
fcab423d | 1638 | iwl_clear_free_frames(priv); |
b481de9c ZY |
1639 | } |
1640 | ||
5b9f8cd3 | 1641 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
1642 | { |
1643 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 1644 | __iwl_down(priv); |
b481de9c | 1645 | mutex_unlock(&priv->mutex); |
b24d22b1 | 1646 | |
4e39317d | 1647 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
1648 | } |
1649 | ||
1650 | #define MAX_HW_RESTARTS 5 | |
1651 | ||
5b9f8cd3 | 1652 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 1653 | { |
57aab75a TW |
1654 | int i; |
1655 | int ret; | |
b481de9c ZY |
1656 | |
1657 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 1658 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
1659 | return -EIO; |
1660 | } | |
1661 | ||
e903fbd4 | 1662 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 1663 | IWL_ERR(priv, "ucode not available for device bringup\n"); |
e903fbd4 RC |
1664 | return -EIO; |
1665 | } | |
1666 | ||
e655b9f0 | 1667 | /* If platform's RF_KILL switch is NOT set to KILL */ |
c1842d61 | 1668 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
e655b9f0 | 1669 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 1670 | else |
e655b9f0 | 1671 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 1672 | |
c1842d61 | 1673 | if (iwl_is_rfkill(priv)) { |
5b9f8cd3 | 1674 | iwl_enable_interrupts(priv); |
39aadf8c | 1675 | IWL_WARN(priv, "Radio disabled by %s RF Kill switch\n", |
3bff19c2 | 1676 | test_bit(STATUS_RF_KILL_HW, &priv->status) ? "HW" : "SW"); |
c1842d61 | 1677 | return 0; |
b481de9c ZY |
1678 | } |
1679 | ||
3395f6e9 | 1680 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 1681 | |
1053d35f | 1682 | ret = iwl_hw_nic_init(priv); |
57aab75a | 1683 | if (ret) { |
15b1687c | 1684 | IWL_ERR(priv, "Unable to init nic\n"); |
57aab75a | 1685 | return ret; |
b481de9c ZY |
1686 | } |
1687 | ||
1688 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
1689 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1690 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
1691 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
1692 | ||
1693 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 1694 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
5b9f8cd3 | 1695 | iwl_enable_interrupts(priv); |
b481de9c ZY |
1696 | |
1697 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
1698 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1699 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
1700 | |
1701 | /* Copy original ucode data image from disk into backup cache. | |
1702 | * This will be used to initialize the on-board processor's | |
1703 | * data SRAM for a clean start when the runtime program first loads. */ | |
1704 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 1705 | priv->ucode_data.len); |
b481de9c | 1706 | |
b481de9c ZY |
1707 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
1708 | ||
e11bc028 | 1709 | priv->cfg->ops->smgmt->clear_station_table(priv); |
b481de9c ZY |
1710 | |
1711 | /* load bootstrap state machine, | |
1712 | * load bootstrap program into processor's memory, | |
1713 | * prepare to load the "initialize" uCode */ | |
57aab75a | 1714 | ret = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c | 1715 | |
57aab75a | 1716 | if (ret) { |
15b1687c WT |
1717 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", |
1718 | ret); | |
b481de9c ZY |
1719 | continue; |
1720 | } | |
1721 | ||
f3d5b45b EG |
1722 | /* Clear out the uCode error bit if it is set */ |
1723 | clear_bit(STATUS_FW_ERROR, &priv->status); | |
1724 | ||
b481de9c | 1725 | /* start card; "initialize" will load runtime ucode */ |
5b9f8cd3 | 1726 | iwl_nic_start(priv); |
b481de9c | 1727 | |
e1623446 | 1728 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
1729 | |
1730 | return 0; | |
1731 | } | |
1732 | ||
1733 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5b9f8cd3 | 1734 | __iwl_down(priv); |
64e72c3e | 1735 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
1736 | |
1737 | /* tried to restart and config the device for as long as our | |
1738 | * patience could withstand */ | |
15b1687c | 1739 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
1740 | return -EIO; |
1741 | } | |
1742 | ||
1743 | ||
1744 | /***************************************************************************** | |
1745 | * | |
1746 | * Workqueue callbacks | |
1747 | * | |
1748 | *****************************************************************************/ | |
1749 | ||
4a4a9e81 | 1750 | static void iwl_bg_init_alive_start(struct work_struct *data) |
b481de9c | 1751 | { |
c79dd5b5 TW |
1752 | struct iwl_priv *priv = |
1753 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
1754 | |
1755 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1756 | return; | |
1757 | ||
1758 | mutex_lock(&priv->mutex); | |
f3ccc08c | 1759 | priv->cfg->ops->lib->init_alive_start(priv); |
b481de9c ZY |
1760 | mutex_unlock(&priv->mutex); |
1761 | } | |
1762 | ||
4a4a9e81 | 1763 | static void iwl_bg_alive_start(struct work_struct *data) |
b481de9c | 1764 | { |
c79dd5b5 TW |
1765 | struct iwl_priv *priv = |
1766 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
1767 | |
1768 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1769 | return; | |
1770 | ||
1771 | mutex_lock(&priv->mutex); | |
4a4a9e81 | 1772 | iwl_alive_start(priv); |
b481de9c ZY |
1773 | mutex_unlock(&priv->mutex); |
1774 | } | |
1775 | ||
16e727e8 EG |
1776 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
1777 | { | |
1778 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
1779 | run_time_calib_work); | |
1780 | ||
1781 | mutex_lock(&priv->mutex); | |
1782 | ||
1783 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
1784 | test_bit(STATUS_SCANNING, &priv->status)) { | |
1785 | mutex_unlock(&priv->mutex); | |
1786 | return; | |
1787 | } | |
1788 | ||
1789 | if (priv->start_calib) { | |
1790 | iwl_chain_noise_calibration(priv, &priv->statistics); | |
1791 | ||
1792 | iwl_sensitivity_calibration(priv, &priv->statistics); | |
1793 | } | |
1794 | ||
1795 | mutex_unlock(&priv->mutex); | |
1796 | return; | |
1797 | } | |
1798 | ||
5b9f8cd3 | 1799 | static void iwl_bg_up(struct work_struct *data) |
b481de9c | 1800 | { |
c79dd5b5 | 1801 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
1802 | |
1803 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1804 | return; | |
1805 | ||
1806 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 1807 | __iwl_up(priv); |
b481de9c | 1808 | mutex_unlock(&priv->mutex); |
80fcc9e2 | 1809 | iwl_rfkill_set_hw_state(priv); |
b481de9c ZY |
1810 | } |
1811 | ||
5b9f8cd3 | 1812 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 1813 | { |
c79dd5b5 | 1814 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
1815 | |
1816 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1817 | return; | |
1818 | ||
5b9f8cd3 | 1819 | iwl_down(priv); |
b481de9c ZY |
1820 | queue_work(priv->workqueue, &priv->up); |
1821 | } | |
1822 | ||
5b9f8cd3 | 1823 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 1824 | { |
c79dd5b5 TW |
1825 | struct iwl_priv *priv = |
1826 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
1827 | |
1828 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1829 | return; | |
1830 | ||
1831 | mutex_lock(&priv->mutex); | |
a55360e4 | 1832 | iwl_rx_replenish(priv); |
b481de9c ZY |
1833 | mutex_unlock(&priv->mutex); |
1834 | } | |
1835 | ||
7878a5a4 MA |
1836 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
1837 | ||
5bbe233b | 1838 | void iwl_post_associate(struct iwl_priv *priv) |
b481de9c | 1839 | { |
b481de9c | 1840 | struct ieee80211_conf *conf = NULL; |
857485c0 | 1841 | int ret = 0; |
1ff50bda | 1842 | unsigned long flags; |
b481de9c | 1843 | |
05c914fe | 1844 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
15b1687c | 1845 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
1846 | return; |
1847 | } | |
1848 | ||
e1623446 | 1849 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
e174961c | 1850 | priv->assoc_id, priv->active_rxon.bssid_addr); |
b481de9c ZY |
1851 | |
1852 | ||
1853 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1854 | return; | |
1855 | ||
b481de9c | 1856 | |
508e32e1 | 1857 | if (!priv->vif || !priv->is_open) |
948c171c | 1858 | return; |
508e32e1 | 1859 | |
c90a74ba | 1860 | iwl_power_cancel_timeout(priv); |
2a421b91 | 1861 | iwl_scan_cancel_timeout(priv, 200); |
052c4b9f | 1862 | |
b481de9c ZY |
1863 | conf = ieee80211_get_hw_conf(priv->hw); |
1864 | ||
1865 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 1866 | iwlcore_commit_rxon(priv); |
b481de9c | 1867 | |
3195c1f3 | 1868 | iwl_setup_rxon_timing(priv); |
857485c0 | 1869 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 1870 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 1871 | if (ret) |
39aadf8c | 1872 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
1873 | "Attempting to continue.\n"); |
1874 | ||
1875 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
1876 | ||
42eb7c64 | 1877 | iwl_set_rxon_ht(priv, &priv->current_ht_config); |
4f85f5b3 | 1878 | |
45823531 AK |
1879 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
1880 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
1881 | ||
b481de9c ZY |
1882 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
1883 | ||
e1623446 | 1884 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
b481de9c ZY |
1885 | priv->assoc_id, priv->beacon_int); |
1886 | ||
1887 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
1888 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
1889 | else | |
1890 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
1891 | ||
1892 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
1893 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
1894 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
1895 | else | |
1896 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
1897 | ||
05c914fe | 1898 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
1899 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
1900 | ||
1901 | } | |
1902 | ||
e0158e61 | 1903 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
1904 | |
1905 | switch (priv->iw_mode) { | |
05c914fe | 1906 | case NL80211_IFTYPE_STATION: |
b481de9c ZY |
1907 | break; |
1908 | ||
05c914fe | 1909 | case NL80211_IFTYPE_ADHOC: |
b481de9c | 1910 | |
c46fbefa AK |
1911 | /* assume default assoc id */ |
1912 | priv->assoc_id = 1; | |
b481de9c | 1913 | |
4f40e4d9 | 1914 | iwl_rxon_add_station(priv, priv->bssid, 0); |
5b9f8cd3 | 1915 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
1916 | |
1917 | break; | |
1918 | ||
1919 | default: | |
15b1687c | 1920 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3ac7f146 | 1921 | __func__, priv->iw_mode); |
b481de9c ZY |
1922 | break; |
1923 | } | |
1924 | ||
05c914fe | 1925 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
1926 | priv->assoc_station_added = 1; |
1927 | ||
1ff50bda EG |
1928 | spin_lock_irqsave(&priv->lock, flags); |
1929 | iwl_activate_qos(priv, 0); | |
1930 | spin_unlock_irqrestore(&priv->lock, flags); | |
292ae174 | 1931 | |
04816448 GE |
1932 | /* the chain noise calibration will enabled PM upon completion |
1933 | * If chain noise has already been run, then we need to enable | |
1934 | * power management here */ | |
1935 | if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE) | |
1936 | iwl_power_enable_management(priv); | |
c90a74ba EG |
1937 | |
1938 | /* Enable Rx differential gain and sensitivity calibrations */ | |
1939 | iwl_chain_noise_reset(priv); | |
1940 | priv->start_calib = 1; | |
1941 | ||
508e32e1 RC |
1942 | } |
1943 | ||
b481de9c ZY |
1944 | /***************************************************************************** |
1945 | * | |
1946 | * mac80211 entry point functions | |
1947 | * | |
1948 | *****************************************************************************/ | |
1949 | ||
154b25ce | 1950 | #define UCODE_READY_TIMEOUT (4 * HZ) |
5a66926a | 1951 | |
5b9f8cd3 | 1952 | static int iwl_mac_start(struct ieee80211_hw *hw) |
b481de9c | 1953 | { |
c79dd5b5 | 1954 | struct iwl_priv *priv = hw->priv; |
5a66926a | 1955 | int ret; |
b481de9c | 1956 | |
e1623446 | 1957 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
1958 | |
1959 | /* we should be verifying the device is ready to be opened */ | |
1960 | mutex_lock(&priv->mutex); | |
1961 | ||
c1adf9fb | 1962 | memset(&priv->staging_rxon, 0, sizeof(struct iwl_rxon_cmd)); |
5a66926a ZY |
1963 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... |
1964 | * ucode filename and max sizes are card-specific. */ | |
b481de9c | 1965 | |
5a66926a | 1966 | if (!priv->ucode_code.len) { |
5b9f8cd3 | 1967 | ret = iwl_read_ucode(priv); |
5a66926a | 1968 | if (ret) { |
15b1687c | 1969 | IWL_ERR(priv, "Could not read microcode: %d\n", ret); |
5a66926a | 1970 | mutex_unlock(&priv->mutex); |
6cd0b1cb | 1971 | return ret; |
5a66926a ZY |
1972 | } |
1973 | } | |
b481de9c | 1974 | |
5b9f8cd3 | 1975 | ret = __iwl_up(priv); |
5a66926a | 1976 | |
b481de9c | 1977 | mutex_unlock(&priv->mutex); |
5a66926a | 1978 | |
80fcc9e2 AG |
1979 | iwl_rfkill_set_hw_state(priv); |
1980 | ||
e655b9f0 | 1981 | if (ret) |
6cd0b1cb | 1982 | return ret; |
e655b9f0 | 1983 | |
c1842d61 TW |
1984 | if (iwl_is_rfkill(priv)) |
1985 | goto out; | |
1986 | ||
e1623446 | 1987 | IWL_DEBUG_INFO(priv, "Start UP work done.\n"); |
e655b9f0 | 1988 | |
fe9b6b72 | 1989 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from |
5a66926a | 1990 | * mac80211 will not be run successfully. */ |
154b25ce EG |
1991 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
1992 | test_bit(STATUS_READY, &priv->status), | |
1993 | UCODE_READY_TIMEOUT); | |
1994 | if (!ret) { | |
1995 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c | 1996 | IWL_ERR(priv, "START_ALIVE timeout after %dms.\n", |
154b25ce | 1997 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
6cd0b1cb | 1998 | return -ETIMEDOUT; |
5a66926a | 1999 | } |
fe9b6b72 | 2000 | } |
0a078ffa | 2001 | |
c1842d61 | 2002 | out: |
0a078ffa | 2003 | priv->is_open = 1; |
e1623446 | 2004 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2005 | return 0; |
2006 | } | |
2007 | ||
5b9f8cd3 | 2008 | static void iwl_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 2009 | { |
c79dd5b5 | 2010 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2011 | |
e1623446 | 2012 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
948c171c | 2013 | |
e655b9f0 | 2014 | if (!priv->is_open) { |
e1623446 | 2015 | IWL_DEBUG_MAC80211(priv, "leave - skip\n"); |
e655b9f0 ZY |
2016 | return; |
2017 | } | |
2018 | ||
b481de9c | 2019 | priv->is_open = 0; |
5a66926a | 2020 | |
fee1247a | 2021 | if (iwl_is_ready_rf(priv)) { |
e655b9f0 ZY |
2022 | /* stop mac, cancel any scan request and clear |
2023 | * RXON_FILTER_ASSOC_MSK BIT | |
2024 | */ | |
5a66926a | 2025 | mutex_lock(&priv->mutex); |
2a421b91 | 2026 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 2027 | mutex_unlock(&priv->mutex); |
fde3571f MA |
2028 | } |
2029 | ||
5b9f8cd3 | 2030 | iwl_down(priv); |
5a66926a ZY |
2031 | |
2032 | flush_workqueue(priv->workqueue); | |
6cd0b1cb HS |
2033 | |
2034 | /* enable interrupts again in order to receive rfkill changes */ | |
2035 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | |
2036 | iwl_enable_interrupts(priv); | |
948c171c | 2037 | |
e1623446 | 2038 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2039 | } |
2040 | ||
5b9f8cd3 | 2041 | static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 2042 | { |
c79dd5b5 | 2043 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2044 | |
e1623446 | 2045 | IWL_DEBUG_MACDUMP(priv, "enter\n"); |
b481de9c | 2046 | |
e1623446 | 2047 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 2048 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 2049 | |
e039fa4a | 2050 | if (iwl_tx_skb(priv, skb)) |
b481de9c ZY |
2051 | dev_kfree_skb_any(skb); |
2052 | ||
e1623446 | 2053 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
637f8837 | 2054 | return NETDEV_TX_OK; |
b481de9c ZY |
2055 | } |
2056 | ||
60690a6a | 2057 | void iwl_config_ap(struct iwl_priv *priv) |
b481de9c | 2058 | { |
857485c0 | 2059 | int ret = 0; |
1ff50bda | 2060 | unsigned long flags; |
b481de9c | 2061 | |
d986bcd1 | 2062 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
2063 | return; |
2064 | ||
2065 | /* The following should be done only at AP bring up */ | |
3195c1f3 | 2066 | if (!iwl_is_associated(priv)) { |
b481de9c ZY |
2067 | |
2068 | /* RXON - unassoc (to set timing command) */ | |
2069 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2070 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2071 | |
2072 | /* RXON Timing */ | |
3195c1f3 | 2073 | iwl_setup_rxon_timing(priv); |
857485c0 | 2074 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2075 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2076 | if (ret) |
39aadf8c | 2077 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2078 | "Attempting to continue.\n"); |
2079 | ||
45823531 AK |
2080 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
2081 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
b481de9c ZY |
2082 | |
2083 | /* FIXME: what should be the assoc_id for AP? */ | |
2084 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
2085 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2086 | priv->staging_rxon.flags |= | |
2087 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
2088 | else | |
2089 | priv->staging_rxon.flags &= | |
2090 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2091 | ||
2092 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2093 | if (priv->assoc_capability & | |
2094 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2095 | priv->staging_rxon.flags |= | |
2096 | RXON_FLG_SHORT_SLOT_MSK; | |
2097 | else | |
2098 | priv->staging_rxon.flags &= | |
2099 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2100 | ||
05c914fe | 2101 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2102 | priv->staging_rxon.flags &= |
2103 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2104 | } | |
2105 | /* restore RXON assoc */ | |
2106 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2107 | iwlcore_commit_rxon(priv); |
1ff50bda EG |
2108 | spin_lock_irqsave(&priv->lock, flags); |
2109 | iwl_activate_qos(priv, 1); | |
2110 | spin_unlock_irqrestore(&priv->lock, flags); | |
4f40e4d9 | 2111 | iwl_rxon_add_station(priv, iwl_bcast_addr, 0); |
e1493deb | 2112 | } |
5b9f8cd3 | 2113 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2114 | |
2115 | /* FIXME - we need to add code here to detect a totally new | |
2116 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
2117 | * clear sta table, add BCAST sta... */ | |
2118 | } | |
2119 | ||
5b9f8cd3 | 2120 | static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw, |
ab885f8c EG |
2121 | struct ieee80211_key_conf *keyconf, const u8 *addr, |
2122 | u32 iv32, u16 *phase1key) | |
2123 | { | |
ab885f8c | 2124 | |
9f58671e | 2125 | struct iwl_priv *priv = hw->priv; |
e1623446 | 2126 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
ab885f8c | 2127 | |
9f58671e | 2128 | iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key); |
ab885f8c | 2129 | |
e1623446 | 2130 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
ab885f8c EG |
2131 | } |
2132 | ||
5b9f8cd3 | 2133 | static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
2134 | struct ieee80211_vif *vif, |
2135 | struct ieee80211_sta *sta, | |
b481de9c ZY |
2136 | struct ieee80211_key_conf *key) |
2137 | { | |
c79dd5b5 | 2138 | struct iwl_priv *priv = hw->priv; |
42986796 WT |
2139 | const u8 *addr; |
2140 | int ret; | |
2141 | u8 sta_id; | |
2142 | bool is_default_wep_key = false; | |
b481de9c | 2143 | |
e1623446 | 2144 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 2145 | |
099b40b7 | 2146 | if (priv->hw_params.sw_crypto) { |
e1623446 | 2147 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
2148 | return -EOPNOTSUPP; |
2149 | } | |
42986796 | 2150 | addr = sta ? sta->addr : iwl_bcast_addr; |
e11bc028 | 2151 | sta_id = priv->cfg->ops->smgmt->find_station(priv, addr); |
6974e363 | 2152 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 2153 | IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n", |
e174961c | 2154 | addr); |
6974e363 | 2155 | return -EINVAL; |
b481de9c | 2156 | |
deb09c43 | 2157 | } |
b481de9c | 2158 | |
6974e363 | 2159 | mutex_lock(&priv->mutex); |
2a421b91 | 2160 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 EG |
2161 | mutex_unlock(&priv->mutex); |
2162 | ||
2163 | /* If we are getting WEP group key and we didn't receive any key mapping | |
2164 | * so far, we are in legacy wep mode (group key only), otherwise we are | |
2165 | * in 1X mode. | |
2166 | * In legacy wep mode, we use another host command to the uCode */ | |
5425e490 | 2167 | if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id && |
05c914fe | 2168 | priv->iw_mode != NL80211_IFTYPE_AP) { |
6974e363 EG |
2169 | if (cmd == SET_KEY) |
2170 | is_default_wep_key = !priv->key_mapping_key; | |
2171 | else | |
ccc038ab EG |
2172 | is_default_wep_key = |
2173 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 2174 | } |
052c4b9f | 2175 | |
b481de9c | 2176 | switch (cmd) { |
deb09c43 | 2177 | case SET_KEY: |
6974e363 EG |
2178 | if (is_default_wep_key) |
2179 | ret = iwl_set_default_wep_key(priv, key); | |
deb09c43 | 2180 | else |
7480513f | 2181 | ret = iwl_set_dynamic_key(priv, key, sta_id); |
deb09c43 | 2182 | |
e1623446 | 2183 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); |
b481de9c ZY |
2184 | break; |
2185 | case DISABLE_KEY: | |
6974e363 EG |
2186 | if (is_default_wep_key) |
2187 | ret = iwl_remove_default_wep_key(priv, key); | |
deb09c43 | 2188 | else |
3ec47732 | 2189 | ret = iwl_remove_dynamic_key(priv, key, sta_id); |
deb09c43 | 2190 | |
e1623446 | 2191 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); |
b481de9c ZY |
2192 | break; |
2193 | default: | |
deb09c43 | 2194 | ret = -EINVAL; |
b481de9c ZY |
2195 | } |
2196 | ||
e1623446 | 2197 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 2198 | |
deb09c43 | 2199 | return ret; |
b481de9c ZY |
2200 | } |
2201 | ||
5b9f8cd3 | 2202 | static int iwl_mac_ampdu_action(struct ieee80211_hw *hw, |
d783b061 | 2203 | enum ieee80211_ampdu_mlme_action action, |
17741cdc | 2204 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) |
d783b061 TW |
2205 | { |
2206 | struct iwl_priv *priv = hw->priv; | |
5c2207c6 | 2207 | int ret; |
d783b061 | 2208 | |
e1623446 | 2209 | IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", |
e174961c | 2210 | sta->addr, tid); |
d783b061 TW |
2211 | |
2212 | if (!(priv->cfg->sku & IWL_SKU_N)) | |
2213 | return -EACCES; | |
2214 | ||
2215 | switch (action) { | |
2216 | case IEEE80211_AMPDU_RX_START: | |
e1623446 | 2217 | IWL_DEBUG_HT(priv, "start Rx\n"); |
9f58671e | 2218 | return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn); |
d783b061 | 2219 | case IEEE80211_AMPDU_RX_STOP: |
e1623446 | 2220 | IWL_DEBUG_HT(priv, "stop Rx\n"); |
5c2207c6 WYG |
2221 | ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid); |
2222 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2223 | return 0; | |
2224 | else | |
2225 | return ret; | |
d783b061 | 2226 | case IEEE80211_AMPDU_TX_START: |
e1623446 | 2227 | IWL_DEBUG_HT(priv, "start Tx\n"); |
17741cdc | 2228 | return iwl_tx_agg_start(priv, sta->addr, tid, ssn); |
d783b061 | 2229 | case IEEE80211_AMPDU_TX_STOP: |
e1623446 | 2230 | IWL_DEBUG_HT(priv, "stop Tx\n"); |
5c2207c6 WYG |
2231 | ret = iwl_tx_agg_stop(priv, sta->addr, tid); |
2232 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2233 | return 0; | |
2234 | else | |
2235 | return ret; | |
d783b061 | 2236 | default: |
e1623446 | 2237 | IWL_DEBUG_HT(priv, "unknown\n"); |
d783b061 TW |
2238 | return -EINVAL; |
2239 | break; | |
2240 | } | |
2241 | return 0; | |
2242 | } | |
9f58671e | 2243 | |
5b9f8cd3 | 2244 | static int iwl_mac_get_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
2245 | struct ieee80211_low_level_stats *stats) |
2246 | { | |
bf403db8 EK |
2247 | struct iwl_priv *priv = hw->priv; |
2248 | ||
2249 | priv = hw->priv; | |
e1623446 TW |
2250 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
2251 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
b481de9c ZY |
2252 | |
2253 | return 0; | |
2254 | } | |
2255 | ||
b481de9c ZY |
2256 | /***************************************************************************** |
2257 | * | |
2258 | * sysfs attributes | |
2259 | * | |
2260 | *****************************************************************************/ | |
2261 | ||
0a6857e7 | 2262 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
2263 | |
2264 | /* | |
2265 | * The following adds a new attribute to the sysfs representation | |
c3a739fa | 2266 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) |
b481de9c ZY |
2267 | * used for controlling the debug level. |
2268 | * | |
2269 | * See the level definitions in iwl for details. | |
2270 | */ | |
2271 | ||
8cf769c6 EK |
2272 | static ssize_t show_debug_level(struct device *d, |
2273 | struct device_attribute *attr, char *buf) | |
b481de9c | 2274 | { |
8cf769c6 EK |
2275 | struct iwl_priv *priv = d->driver_data; |
2276 | ||
2277 | return sprintf(buf, "0x%08X\n", priv->debug_level); | |
b481de9c | 2278 | } |
8cf769c6 EK |
2279 | static ssize_t store_debug_level(struct device *d, |
2280 | struct device_attribute *attr, | |
b481de9c ZY |
2281 | const char *buf, size_t count) |
2282 | { | |
8cf769c6 | 2283 | struct iwl_priv *priv = d->driver_data; |
9257746f TW |
2284 | unsigned long val; |
2285 | int ret; | |
b481de9c | 2286 | |
9257746f TW |
2287 | ret = strict_strtoul(buf, 0, &val); |
2288 | if (ret) | |
978785a3 | 2289 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); |
b481de9c | 2290 | else |
8cf769c6 | 2291 | priv->debug_level = val; |
b481de9c ZY |
2292 | |
2293 | return strnlen(buf, count); | |
2294 | } | |
2295 | ||
8cf769c6 EK |
2296 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
2297 | show_debug_level, store_debug_level); | |
2298 | ||
b481de9c | 2299 | |
0a6857e7 | 2300 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 2301 | |
b481de9c | 2302 | |
bc6f59bc TW |
2303 | static ssize_t show_version(struct device *d, |
2304 | struct device_attribute *attr, char *buf) | |
2305 | { | |
2306 | struct iwl_priv *priv = d->driver_data; | |
885ba202 | 2307 | struct iwl_alive_resp *palive = &priv->card_alive; |
f236a265 TW |
2308 | ssize_t pos = 0; |
2309 | u16 eeprom_ver; | |
bc6f59bc TW |
2310 | |
2311 | if (palive->is_valid) | |
f236a265 TW |
2312 | pos += sprintf(buf + pos, |
2313 | "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n" | |
2314 | "fw type: 0x%01X 0x%01X\n", | |
bc6f59bc TW |
2315 | palive->ucode_major, palive->ucode_minor, |
2316 | palive->sw_rev[0], palive->sw_rev[1], | |
2317 | palive->ver_type, palive->ver_subtype); | |
bc6f59bc | 2318 | else |
f236a265 TW |
2319 | pos += sprintf(buf + pos, "fw not loaded\n"); |
2320 | ||
2321 | if (priv->eeprom) { | |
2322 | eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION); | |
2323 | pos += sprintf(buf + pos, "EEPROM version: 0x%x\n", | |
2324 | eeprom_ver); | |
2325 | } else { | |
2326 | pos += sprintf(buf + pos, "EEPROM not initialzed\n"); | |
2327 | } | |
2328 | ||
2329 | return pos; | |
bc6f59bc TW |
2330 | } |
2331 | ||
2332 | static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL); | |
2333 | ||
b481de9c ZY |
2334 | static ssize_t show_temperature(struct device *d, |
2335 | struct device_attribute *attr, char *buf) | |
2336 | { | |
c79dd5b5 | 2337 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c | 2338 | |
fee1247a | 2339 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
2340 | return -EAGAIN; |
2341 | ||
91dbc5bd | 2342 | return sprintf(buf, "%d\n", priv->temperature); |
b481de9c ZY |
2343 | } |
2344 | ||
2345 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
2346 | ||
b481de9c ZY |
2347 | static ssize_t show_tx_power(struct device *d, |
2348 | struct device_attribute *attr, char *buf) | |
2349 | { | |
c79dd5b5 | 2350 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
91f39e8e JS |
2351 | |
2352 | if (!iwl_is_ready_rf(priv)) | |
2353 | return sprintf(buf, "off\n"); | |
2354 | else | |
2355 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
b481de9c ZY |
2356 | } |
2357 | ||
2358 | static ssize_t store_tx_power(struct device *d, | |
2359 | struct device_attribute *attr, | |
2360 | const char *buf, size_t count) | |
2361 | { | |
c79dd5b5 | 2362 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
9257746f TW |
2363 | unsigned long val; |
2364 | int ret; | |
b481de9c | 2365 | |
9257746f TW |
2366 | ret = strict_strtoul(buf, 10, &val); |
2367 | if (ret) | |
978785a3 | 2368 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); |
b481de9c | 2369 | else |
630fe9b6 | 2370 | iwl_set_tx_power(priv, val, false); |
b481de9c ZY |
2371 | |
2372 | return count; | |
2373 | } | |
2374 | ||
2375 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
2376 | ||
2377 | static ssize_t show_flags(struct device *d, | |
2378 | struct device_attribute *attr, char *buf) | |
2379 | { | |
c79dd5b5 | 2380 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
2381 | |
2382 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); | |
2383 | } | |
2384 | ||
2385 | static ssize_t store_flags(struct device *d, | |
2386 | struct device_attribute *attr, | |
2387 | const char *buf, size_t count) | |
2388 | { | |
c79dd5b5 | 2389 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
9257746f TW |
2390 | unsigned long val; |
2391 | u32 flags; | |
2392 | int ret = strict_strtoul(buf, 0, &val); | |
926f0b2e | 2393 | if (ret) |
9257746f TW |
2394 | return ret; |
2395 | flags = (u32)val; | |
b481de9c ZY |
2396 | |
2397 | mutex_lock(&priv->mutex); | |
2398 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { | |
2399 | /* Cancel any currently running scans... */ | |
2a421b91 | 2400 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 2401 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 2402 | else { |
e1623446 | 2403 | IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags); |
b481de9c | 2404 | priv->staging_rxon.flags = cpu_to_le32(flags); |
e0158e61 | 2405 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2406 | } |
2407 | } | |
2408 | mutex_unlock(&priv->mutex); | |
2409 | ||
2410 | return count; | |
2411 | } | |
2412 | ||
2413 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
2414 | ||
2415 | static ssize_t show_filter_flags(struct device *d, | |
2416 | struct device_attribute *attr, char *buf) | |
2417 | { | |
c79dd5b5 | 2418 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
2419 | |
2420 | return sprintf(buf, "0x%04X\n", | |
2421 | le32_to_cpu(priv->active_rxon.filter_flags)); | |
2422 | } | |
2423 | ||
2424 | static ssize_t store_filter_flags(struct device *d, | |
2425 | struct device_attribute *attr, | |
2426 | const char *buf, size_t count) | |
2427 | { | |
c79dd5b5 | 2428 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
9257746f TW |
2429 | unsigned long val; |
2430 | u32 filter_flags; | |
2431 | int ret = strict_strtoul(buf, 0, &val); | |
926f0b2e | 2432 | if (ret) |
9257746f TW |
2433 | return ret; |
2434 | filter_flags = (u32)val; | |
b481de9c ZY |
2435 | |
2436 | mutex_lock(&priv->mutex); | |
2437 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { | |
2438 | /* Cancel any currently running scans... */ | |
2a421b91 | 2439 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 2440 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 2441 | else { |
e1623446 | 2442 | IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = " |
b481de9c ZY |
2443 | "0x%04X\n", filter_flags); |
2444 | priv->staging_rxon.filter_flags = | |
2445 | cpu_to_le32(filter_flags); | |
e0158e61 | 2446 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2447 | } |
2448 | } | |
2449 | mutex_unlock(&priv->mutex); | |
2450 | ||
2451 | return count; | |
2452 | } | |
2453 | ||
2454 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
2455 | store_filter_flags); | |
2456 | ||
b481de9c ZY |
2457 | static ssize_t store_power_level(struct device *d, |
2458 | struct device_attribute *attr, | |
2459 | const char *buf, size_t count) | |
2460 | { | |
c79dd5b5 | 2461 | struct iwl_priv *priv = dev_get_drvdata(d); |
298df1f6 | 2462 | int ret; |
9257746f TW |
2463 | unsigned long mode; |
2464 | ||
b481de9c | 2465 | |
b481de9c ZY |
2466 | mutex_lock(&priv->mutex); |
2467 | ||
9257746f | 2468 | ret = strict_strtoul(buf, 10, &mode); |
926f0b2e | 2469 | if (ret) |
9257746f TW |
2470 | goto out; |
2471 | ||
298df1f6 EK |
2472 | ret = iwl_power_set_user_mode(priv, mode); |
2473 | if (ret) { | |
e1623446 | 2474 | IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n"); |
5da4b55f | 2475 | goto out; |
b481de9c | 2476 | } |
298df1f6 | 2477 | ret = count; |
b481de9c ZY |
2478 | |
2479 | out: | |
2480 | mutex_unlock(&priv->mutex); | |
298df1f6 | 2481 | return ret; |
b481de9c ZY |
2482 | } |
2483 | ||
b481de9c ZY |
2484 | static ssize_t show_power_level(struct device *d, |
2485 | struct device_attribute *attr, char *buf) | |
2486 | { | |
c79dd5b5 | 2487 | struct iwl_priv *priv = dev_get_drvdata(d); |
298df1f6 EK |
2488 | int mode = priv->power_data.user_power_setting; |
2489 | int system = priv->power_data.system_power_setting; | |
5da4b55f | 2490 | int level = priv->power_data.power_mode; |
b481de9c ZY |
2491 | char *p = buf; |
2492 | ||
298df1f6 EK |
2493 | switch (system) { |
2494 | case IWL_POWER_SYS_AUTO: | |
2495 | p += sprintf(p, "SYSTEM:auto"); | |
b481de9c | 2496 | break; |
298df1f6 EK |
2497 | case IWL_POWER_SYS_AC: |
2498 | p += sprintf(p, "SYSTEM:ac"); | |
2499 | break; | |
2500 | case IWL_POWER_SYS_BATTERY: | |
2501 | p += sprintf(p, "SYSTEM:battery"); | |
b481de9c | 2502 | break; |
b481de9c | 2503 | } |
298df1f6 | 2504 | |
c3056065 AK |
2505 | p += sprintf(p, "\tMODE:%s", (mode < IWL_POWER_AUTO) ? |
2506 | "fixed" : "auto"); | |
298df1f6 EK |
2507 | p += sprintf(p, "\tINDEX:%d", level); |
2508 | p += sprintf(p, "\n"); | |
3ac7f146 | 2509 | return p - buf + 1; |
b481de9c ZY |
2510 | } |
2511 | ||
2512 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, | |
2513 | store_power_level); | |
2514 | ||
b481de9c ZY |
2515 | |
2516 | static ssize_t show_statistics(struct device *d, | |
2517 | struct device_attribute *attr, char *buf) | |
2518 | { | |
c79dd5b5 | 2519 | struct iwl_priv *priv = dev_get_drvdata(d); |
8f91aecb | 2520 | u32 size = sizeof(struct iwl_notif_statistics); |
b481de9c | 2521 | u32 len = 0, ofs = 0; |
3ac7f146 | 2522 | u8 *data = (u8 *)&priv->statistics; |
b481de9c ZY |
2523 | int rc = 0; |
2524 | ||
fee1247a | 2525 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
2526 | return -EAGAIN; |
2527 | ||
2528 | mutex_lock(&priv->mutex); | |
49ea8596 | 2529 | rc = iwl_send_statistics_request(priv, 0); |
b481de9c ZY |
2530 | mutex_unlock(&priv->mutex); |
2531 | ||
2532 | if (rc) { | |
2533 | len = sprintf(buf, | |
2534 | "Error sending statistics request: 0x%08X\n", rc); | |
2535 | return len; | |
2536 | } | |
2537 | ||
2538 | while (size && (PAGE_SIZE - len)) { | |
2539 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
2540 | PAGE_SIZE - len, 1); | |
2541 | len = strlen(buf); | |
2542 | if (PAGE_SIZE - len) | |
2543 | buf[len++] = '\n'; | |
2544 | ||
2545 | ofs += 16; | |
2546 | size -= min(size, 16U); | |
2547 | } | |
2548 | ||
2549 | return len; | |
2550 | } | |
2551 | ||
2552 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
2553 | ||
b481de9c | 2554 | |
b481de9c ZY |
2555 | /***************************************************************************** |
2556 | * | |
2557 | * driver setup and teardown | |
2558 | * | |
2559 | *****************************************************************************/ | |
2560 | ||
4e39317d | 2561 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 2562 | { |
d21050c7 | 2563 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
2564 | |
2565 | init_waitqueue_head(&priv->wait_command_queue); | |
2566 | ||
5b9f8cd3 EG |
2567 | INIT_WORK(&priv->up, iwl_bg_up); |
2568 | INIT_WORK(&priv->restart, iwl_bg_restart); | |
2569 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
2570 | INIT_WORK(&priv->rf_kill, iwl_bg_rf_kill); | |
2571 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); | |
16e727e8 | 2572 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
4a4a9e81 TW |
2573 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start); |
2574 | INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start); | |
2a421b91 | 2575 | |
2a421b91 | 2576 | iwl_setup_scan_deferred_work(priv); |
c90a74ba | 2577 | iwl_setup_power_deferred_work(priv); |
bb8c093b | 2578 | |
4e39317d EG |
2579 | if (priv->cfg->ops->lib->setup_deferred_work) |
2580 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
2581 | ||
2582 | init_timer(&priv->statistics_periodic); | |
2583 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 2584 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c ZY |
2585 | |
2586 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
5b9f8cd3 | 2587 | iwl_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
2588 | } |
2589 | ||
4e39317d | 2590 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 2591 | { |
4e39317d EG |
2592 | if (priv->cfg->ops->lib->cancel_deferred_work) |
2593 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 2594 | |
3ae6a054 | 2595 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c | 2596 | cancel_delayed_work(&priv->scan_check); |
c90a74ba | 2597 | cancel_delayed_work_sync(&priv->set_power_save); |
b481de9c | 2598 | cancel_delayed_work(&priv->alive_start); |
b481de9c | 2599 | cancel_work_sync(&priv->beacon_update); |
4e39317d | 2600 | del_timer_sync(&priv->statistics_periodic); |
b481de9c ZY |
2601 | } |
2602 | ||
5b9f8cd3 | 2603 | static struct attribute *iwl_sysfs_entries[] = { |
b481de9c ZY |
2604 | &dev_attr_flags.attr, |
2605 | &dev_attr_filter_flags.attr, | |
b481de9c | 2606 | &dev_attr_power_level.attr, |
b481de9c | 2607 | &dev_attr_statistics.attr, |
b481de9c | 2608 | &dev_attr_temperature.attr, |
b481de9c | 2609 | &dev_attr_tx_power.attr, |
8cf769c6 EK |
2610 | #ifdef CONFIG_IWLWIFI_DEBUG |
2611 | &dev_attr_debug_level.attr, | |
2612 | #endif | |
bc6f59bc | 2613 | &dev_attr_version.attr, |
b481de9c ZY |
2614 | |
2615 | NULL | |
2616 | }; | |
2617 | ||
5b9f8cd3 | 2618 | static struct attribute_group iwl_attribute_group = { |
b481de9c | 2619 | .name = NULL, /* put in device directory */ |
5b9f8cd3 | 2620 | .attrs = iwl_sysfs_entries, |
b481de9c ZY |
2621 | }; |
2622 | ||
5b9f8cd3 EG |
2623 | static struct ieee80211_ops iwl_hw_ops = { |
2624 | .tx = iwl_mac_tx, | |
2625 | .start = iwl_mac_start, | |
2626 | .stop = iwl_mac_stop, | |
2627 | .add_interface = iwl_mac_add_interface, | |
2628 | .remove_interface = iwl_mac_remove_interface, | |
2629 | .config = iwl_mac_config, | |
2630 | .config_interface = iwl_mac_config_interface, | |
2631 | .configure_filter = iwl_configure_filter, | |
2632 | .set_key = iwl_mac_set_key, | |
2633 | .update_tkip_key = iwl_mac_update_tkip_key, | |
2634 | .get_stats = iwl_mac_get_stats, | |
2635 | .get_tx_stats = iwl_mac_get_tx_stats, | |
2636 | .conf_tx = iwl_mac_conf_tx, | |
2637 | .reset_tsf = iwl_mac_reset_tsf, | |
2638 | .bss_info_changed = iwl_bss_info_changed, | |
2639 | .ampdu_action = iwl_mac_ampdu_action, | |
cb43dc25 | 2640 | .hw_scan = iwl_mac_hw_scan |
b481de9c ZY |
2641 | }; |
2642 | ||
5b9f8cd3 | 2643 | static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
2644 | { |
2645 | int err = 0; | |
c79dd5b5 | 2646 | struct iwl_priv *priv; |
b481de9c | 2647 | struct ieee80211_hw *hw; |
82b9a121 | 2648 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 2649 | unsigned long flags; |
6cd0b1cb | 2650 | u16 pci_cmd; |
b481de9c | 2651 | |
316c30d9 AK |
2652 | /************************ |
2653 | * 1. Allocating HW data | |
2654 | ************************/ | |
2655 | ||
6440adb5 CB |
2656 | /* Disabling hardware scan means that mac80211 will perform scans |
2657 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 2658 | if (cfg->mod_params->disable_hw_scan) { |
bf403db8 EK |
2659 | if (cfg->mod_params->debug & IWL_DL_INFO) |
2660 | dev_printk(KERN_DEBUG, &(pdev->dev), | |
2661 | "Disabling hw_scan\n"); | |
5b9f8cd3 | 2662 | iwl_hw_ops.hw_scan = NULL; |
b481de9c ZY |
2663 | } |
2664 | ||
5b9f8cd3 | 2665 | hw = iwl_alloc_all(cfg, &iwl_hw_ops); |
1d0a082d | 2666 | if (!hw) { |
b481de9c ZY |
2667 | err = -ENOMEM; |
2668 | goto out; | |
2669 | } | |
1d0a082d AK |
2670 | priv = hw->priv; |
2671 | /* At this point both hw and priv are allocated. */ | |
2672 | ||
b481de9c ZY |
2673 | SET_IEEE80211_DEV(hw, &pdev->dev); |
2674 | ||
e1623446 | 2675 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
82b9a121 | 2676 | priv->cfg = cfg; |
b481de9c | 2677 | priv->pci_dev = pdev; |
316c30d9 | 2678 | |
0a6857e7 | 2679 | #ifdef CONFIG_IWLWIFI_DEBUG |
bf403db8 | 2680 | priv->debug_level = priv->cfg->mod_params->debug; |
b481de9c ZY |
2681 | atomic_set(&priv->restrict_refcnt, 0); |
2682 | #endif | |
b481de9c | 2683 | |
316c30d9 AK |
2684 | /************************** |
2685 | * 2. Initializing PCI bus | |
2686 | **************************/ | |
2687 | if (pci_enable_device(pdev)) { | |
2688 | err = -ENODEV; | |
2689 | goto out_ieee80211_free_hw; | |
2690 | } | |
2691 | ||
2692 | pci_set_master(pdev); | |
2693 | ||
093d874c | 2694 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); |
316c30d9 | 2695 | if (!err) |
093d874c | 2696 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); |
cc2a8ea8 | 2697 | if (err) { |
093d874c | 2698 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 2699 | if (!err) |
093d874c | 2700 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 2701 | /* both attempts failed: */ |
316c30d9 | 2702 | if (err) { |
978785a3 | 2703 | IWL_WARN(priv, "No suitable DMA available.\n"); |
316c30d9 | 2704 | goto out_pci_disable_device; |
cc2a8ea8 | 2705 | } |
316c30d9 AK |
2706 | } |
2707 | ||
2708 | err = pci_request_regions(pdev, DRV_NAME); | |
2709 | if (err) | |
2710 | goto out_pci_disable_device; | |
2711 | ||
2712 | pci_set_drvdata(pdev, priv); | |
2713 | ||
316c30d9 AK |
2714 | |
2715 | /*********************** | |
2716 | * 3. Read REV register | |
2717 | ***********************/ | |
2718 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
2719 | if (!priv->hw_base) { | |
2720 | err = -ENODEV; | |
2721 | goto out_pci_release_regions; | |
2722 | } | |
2723 | ||
e1623446 | 2724 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
316c30d9 | 2725 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 2726 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
316c30d9 | 2727 | |
b661c819 | 2728 | iwl_hw_detect(priv); |
978785a3 | 2729 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n", |
b661c819 | 2730 | priv->cfg->name, priv->hw_rev); |
316c30d9 | 2731 | |
e7b63581 TW |
2732 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
2733 | * PCI Tx retries from interfering with C3 CPU state */ | |
2734 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
2735 | ||
91238714 TW |
2736 | /* amp init */ |
2737 | err = priv->cfg->ops->lib->apm_ops.init(priv); | |
316c30d9 | 2738 | if (err < 0) { |
808ff697 | 2739 | IWL_ERR(priv, "Failed to init APMG\n"); |
316c30d9 AK |
2740 | goto out_iounmap; |
2741 | } | |
91238714 TW |
2742 | /***************** |
2743 | * 4. Read EEPROM | |
2744 | *****************/ | |
316c30d9 AK |
2745 | /* Read the EEPROM */ |
2746 | err = iwl_eeprom_init(priv); | |
2747 | if (err) { | |
15b1687c | 2748 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
316c30d9 AK |
2749 | goto out_iounmap; |
2750 | } | |
8614f360 TW |
2751 | err = iwl_eeprom_check_version(priv); |
2752 | if (err) | |
c8f16138 | 2753 | goto out_free_eeprom; |
8614f360 | 2754 | |
02883017 | 2755 | /* extract MAC Address */ |
316c30d9 | 2756 | iwl_eeprom_get_mac(priv, priv->mac_addr); |
e1623446 | 2757 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr); |
316c30d9 AK |
2758 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); |
2759 | ||
2760 | /************************ | |
2761 | * 5. Setup HW constants | |
2762 | ************************/ | |
da154e30 | 2763 | if (iwl_set_hw_params(priv)) { |
15b1687c | 2764 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 2765 | goto out_free_eeprom; |
316c30d9 AK |
2766 | } |
2767 | ||
2768 | /******************* | |
6ba87956 | 2769 | * 6. Setup priv |
316c30d9 | 2770 | *******************/ |
b481de9c | 2771 | |
6ba87956 | 2772 | err = iwl_init_drv(priv); |
bf85ea4f | 2773 | if (err) |
399f4900 | 2774 | goto out_free_eeprom; |
bf85ea4f | 2775 | /* At this point both hw and priv are initialized. */ |
316c30d9 AK |
2776 | |
2777 | /********************************** | |
2778 | * 7. Initialize module parameters | |
2779 | **********************************/ | |
2780 | ||
2781 | /* Disable radio (SW RF KILL) via parameter when loading driver */ | |
1ea87396 | 2782 | if (priv->cfg->mod_params->disable) { |
316c30d9 | 2783 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
e1623446 | 2784 | IWL_DEBUG_INFO(priv, "Radio disabled.\n"); |
316c30d9 AK |
2785 | } |
2786 | ||
316c30d9 AK |
2787 | /******************** |
2788 | * 8. Setup services | |
2789 | ********************/ | |
0359facc | 2790 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 2791 | iwl_disable_interrupts(priv); |
0359facc | 2792 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 | 2793 | |
6cd0b1cb HS |
2794 | pci_enable_msi(priv->pci_dev); |
2795 | ||
2796 | err = request_irq(priv->pci_dev->irq, iwl_isr, IRQF_SHARED, | |
2797 | DRV_NAME, priv); | |
2798 | if (err) { | |
2799 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
2800 | goto out_disable_msi; | |
2801 | } | |
5b9f8cd3 | 2802 | err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group); |
316c30d9 | 2803 | if (err) { |
15b1687c | 2804 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
795cc0ad | 2805 | goto out_free_irq; |
316c30d9 AK |
2806 | } |
2807 | ||
4e39317d | 2808 | iwl_setup_deferred_work(priv); |
653fa4a0 | 2809 | iwl_setup_rx_handlers(priv); |
316c30d9 | 2810 | |
6ba87956 | 2811 | /********************************** |
6cd0b1cb | 2812 | * 9. Setup and register mac80211 |
6ba87956 TW |
2813 | **********************************/ |
2814 | ||
6cd0b1cb HS |
2815 | /* enable interrupts if needed: hw bug w/a */ |
2816 | pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd); | |
2817 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
2818 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
2819 | pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd); | |
2820 | } | |
2821 | ||
2822 | iwl_enable_interrupts(priv); | |
2823 | ||
6ba87956 TW |
2824 | err = iwl_setup_mac(priv); |
2825 | if (err) | |
2826 | goto out_remove_sysfs; | |
2827 | ||
2828 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
2829 | if (err) | |
a75fbe8d | 2830 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); |
6ba87956 | 2831 | |
6cd0b1cb HS |
2832 | /* If platform's RF_KILL switch is NOT set to KILL */ |
2833 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
2834 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2835 | else | |
2836 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 2837 | |
58d0f361 EG |
2838 | err = iwl_rfkill_init(priv); |
2839 | if (err) | |
15b1687c | 2840 | IWL_ERR(priv, "Unable to initialize RFKILL system. " |
58d0f361 | 2841 | "Ignoring error: %d\n", err); |
6cd0b1cb HS |
2842 | else |
2843 | iwl_rfkill_set_hw_state(priv); | |
2844 | ||
58d0f361 | 2845 | iwl_power_initialize(priv); |
b481de9c ZY |
2846 | return 0; |
2847 | ||
316c30d9 | 2848 | out_remove_sysfs: |
c8f16138 RC |
2849 | destroy_workqueue(priv->workqueue); |
2850 | priv->workqueue = NULL; | |
5b9f8cd3 | 2851 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
795cc0ad HS |
2852 | out_free_irq: |
2853 | free_irq(priv->pci_dev->irq, priv); | |
6cd0b1cb HS |
2854 | out_disable_msi: |
2855 | pci_disable_msi(priv->pci_dev); | |
6ba87956 | 2856 | iwl_uninit_drv(priv); |
073d3f5f TW |
2857 | out_free_eeprom: |
2858 | iwl_eeprom_free(priv); | |
b481de9c ZY |
2859 | out_iounmap: |
2860 | pci_iounmap(pdev, priv->hw_base); | |
2861 | out_pci_release_regions: | |
316c30d9 | 2862 | pci_set_drvdata(pdev, NULL); |
623d563e | 2863 | pci_release_regions(pdev); |
b481de9c ZY |
2864 | out_pci_disable_device: |
2865 | pci_disable_device(pdev); | |
b481de9c ZY |
2866 | out_ieee80211_free_hw: |
2867 | ieee80211_free_hw(priv->hw); | |
2868 | out: | |
2869 | return err; | |
2870 | } | |
2871 | ||
5b9f8cd3 | 2872 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
b481de9c | 2873 | { |
c79dd5b5 | 2874 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 2875 | unsigned long flags; |
b481de9c ZY |
2876 | |
2877 | if (!priv) | |
2878 | return; | |
2879 | ||
e1623446 | 2880 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 2881 | |
67249625 | 2882 | iwl_dbgfs_unregister(priv); |
5b9f8cd3 | 2883 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
67249625 | 2884 | |
5b9f8cd3 EG |
2885 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
2886 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
2887 | * we need to set STATUS_EXIT_PENDING bit. |
2888 | */ | |
2889 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
c4f55232 RR |
2890 | if (priv->mac80211_registered) { |
2891 | ieee80211_unregister_hw(priv->hw); | |
2892 | priv->mac80211_registered = 0; | |
0b124c31 | 2893 | } else { |
5b9f8cd3 | 2894 | iwl_down(priv); |
c4f55232 RR |
2895 | } |
2896 | ||
0359facc MA |
2897 | /* make sure we flush any pending irq or |
2898 | * tasklet for the driver | |
2899 | */ | |
2900 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 2901 | iwl_disable_interrupts(priv); |
0359facc MA |
2902 | spin_unlock_irqrestore(&priv->lock, flags); |
2903 | ||
2904 | iwl_synchronize_irq(priv); | |
2905 | ||
58d0f361 | 2906 | iwl_rfkill_unregister(priv); |
5b9f8cd3 | 2907 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
2908 | |
2909 | if (priv->rxq.bd) | |
a55360e4 | 2910 | iwl_rx_queue_free(priv, &priv->rxq); |
1053d35f | 2911 | iwl_hw_txq_ctx_free(priv); |
b481de9c | 2912 | |
e11bc028 | 2913 | priv->cfg->ops->smgmt->clear_station_table(priv); |
073d3f5f | 2914 | iwl_eeprom_free(priv); |
b481de9c | 2915 | |
b481de9c | 2916 | |
948c171c MA |
2917 | /*netif_stop_queue(dev); */ |
2918 | flush_workqueue(priv->workqueue); | |
2919 | ||
5b9f8cd3 | 2920 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
2921 | * priv->workqueue... so we can't take down the workqueue |
2922 | * until now... */ | |
2923 | destroy_workqueue(priv->workqueue); | |
2924 | priv->workqueue = NULL; | |
2925 | ||
6cd0b1cb HS |
2926 | free_irq(priv->pci_dev->irq, priv); |
2927 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
2928 | pci_iounmap(pdev, priv->hw_base); |
2929 | pci_release_regions(pdev); | |
2930 | pci_disable_device(pdev); | |
2931 | pci_set_drvdata(pdev, NULL); | |
2932 | ||
6ba87956 | 2933 | iwl_uninit_drv(priv); |
b481de9c ZY |
2934 | |
2935 | if (priv->ibss_beacon) | |
2936 | dev_kfree_skb(priv->ibss_beacon); | |
2937 | ||
2938 | ieee80211_free_hw(priv->hw); | |
2939 | } | |
2940 | ||
b481de9c ZY |
2941 | |
2942 | /***************************************************************************** | |
2943 | * | |
2944 | * driver and module entry point | |
2945 | * | |
2946 | *****************************************************************************/ | |
2947 | ||
fed9017e RR |
2948 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
2949 | static struct pci_device_id iwl_hw_card_ids[] = { | |
4fc22b21 | 2950 | #ifdef CONFIG_IWL4965 |
fed9017e RR |
2951 | {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, |
2952 | {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, | |
4fc22b21 | 2953 | #endif /* CONFIG_IWL4965 */ |
5a6a256e | 2954 | #ifdef CONFIG_IWL5000 |
47408639 EK |
2955 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)}, |
2956 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)}, | |
2957 | {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, | |
2958 | {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, | |
2959 | {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, | |
2960 | {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, | |
5a6a256e | 2961 | {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)}, |
47408639 EK |
2962 | {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)}, |
2963 | {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)}, | |
2964 | {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)}, | |
e96a8495 TW |
2965 | /* 5350 WiFi/WiMax */ |
2966 | {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, | |
2967 | {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, | |
2968 | {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, | |
7100e924 TW |
2969 | /* 5150 Wifi/WiMax */ |
2970 | {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)}, | |
2971 | {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)}, | |
e1228374 JS |
2972 | /* 6000/6050 Series */ |
2973 | {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)}, | |
2974 | {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)}, | |
2975 | {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)}, | |
2976 | {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)}, | |
2977 | {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)}, | |
2978 | {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)}, | |
2979 | {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)}, | |
2980 | {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)}, | |
2981 | {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)}, | |
2982 | {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)}, | |
2983 | {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)}, | |
77dcb6a9 JS |
2984 | /* 1000 Series WiFi */ |
2985 | {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)}, | |
2986 | {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)}, | |
5a6a256e | 2987 | #endif /* CONFIG_IWL5000 */ |
7100e924 | 2988 | |
fed9017e RR |
2989 | {0} |
2990 | }; | |
2991 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | |
2992 | ||
2993 | static struct pci_driver iwl_driver = { | |
b481de9c | 2994 | .name = DRV_NAME, |
fed9017e | 2995 | .id_table = iwl_hw_card_ids, |
5b9f8cd3 EG |
2996 | .probe = iwl_pci_probe, |
2997 | .remove = __devexit_p(iwl_pci_remove), | |
b481de9c | 2998 | #ifdef CONFIG_PM |
5b9f8cd3 EG |
2999 | .suspend = iwl_pci_suspend, |
3000 | .resume = iwl_pci_resume, | |
b481de9c ZY |
3001 | #endif |
3002 | }; | |
3003 | ||
5b9f8cd3 | 3004 | static int __init iwl_init(void) |
b481de9c ZY |
3005 | { |
3006 | ||
3007 | int ret; | |
3008 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
3009 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 | 3010 | |
e227ceac | 3011 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 3012 | if (ret) { |
a3139c59 SO |
3013 | printk(KERN_ERR DRV_NAME |
3014 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
3015 | return ret; |
3016 | } | |
3017 | ||
fed9017e | 3018 | ret = pci_register_driver(&iwl_driver); |
b481de9c | 3019 | if (ret) { |
a3139c59 | 3020 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 3021 | goto error_register; |
b481de9c | 3022 | } |
b481de9c ZY |
3023 | |
3024 | return ret; | |
897e1cf2 | 3025 | |
897e1cf2 | 3026 | error_register: |
e227ceac | 3027 | iwlagn_rate_control_unregister(); |
897e1cf2 | 3028 | return ret; |
b481de9c ZY |
3029 | } |
3030 | ||
5b9f8cd3 | 3031 | static void __exit iwl_exit(void) |
b481de9c | 3032 | { |
fed9017e | 3033 | pci_unregister_driver(&iwl_driver); |
e227ceac | 3034 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
3035 | } |
3036 | ||
5b9f8cd3 EG |
3037 | module_exit(iwl_exit); |
3038 | module_init(iwl_init); |