iwl3945: use iwl_mac_config_interface from iwlwifi
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
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43#include <net/mac80211.h>
44
45#include <asm/div64.h>
46
a3139c59
SO
47#define DRV_NAME "iwlagn"
48
6bc913bd 49#include "iwl-eeprom.h"
3e0d4cb1 50#include "iwl-dev.h"
fee1247a 51#include "iwl-core.h"
3395f6e9 52#include "iwl-io.h"
b481de9c 53#include "iwl-helpers.h"
6974e363 54#include "iwl-sta.h"
f0832f13 55#include "iwl-calib.h"
b481de9c 56
416e1438 57
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58/******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
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64/*
65 * module name, copyright, version, etc.
b481de9c 66 */
d783b061 67#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 68
0a6857e7 69#ifdef CONFIG_IWLWIFI_DEBUG
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70#define VD "d"
71#else
72#define VD
73#endif
74
80bc5393 75#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
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76#define VS "s"
77#else
78#define VS
79#endif
80
df48c323 81#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 82
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83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
b481de9c 90/*************** STATION TABLE MANAGEMENT ****
9fbab516 91 * mac80211 should be examined to determine if sta_info is duplicating
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92 * the functionality provided here
93 */
94
95/**************************************************************/
96
b481de9c 97/**
5b9f8cd3 98 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 99 *
01ebd063 100 * The RXON command in staging_rxon is committed to the hardware and
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101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
e0158e61 105int iwl_commit_rxon(struct iwl_priv *priv)
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106{
107 /* cast away the const for active_rxon in this function */
c1adf9fb 108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 112
fee1247a 113 if (!iwl_is_alive(priv))
43d59b32 114 return -EBUSY;
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115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
a326a5d0
EG
118 /* allow CTS-to-self if possible. this is relevant only for
119 * 5000, but will not damage 4965 */
120 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
b481de9c 121
8ccde88a 122 ret = iwl_check_rxon_cmd(priv);
43d59b32 123 if (ret) {
15b1687c 124 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
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125 return -EINVAL;
126 }
127
128 /* If we don't need to send a full RXON, we can use
5b9f8cd3 129 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 130 * and other flags for the current radio configuration. */
54559703 131 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
132 ret = iwl_send_rxon_assoc(priv);
133 if (ret) {
15b1687c 134 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 135 return ret;
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136 }
137
138 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
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139 return 0;
140 }
141
142 /* station table will be cleared */
143 priv->assoc_station_added = 0;
144
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145 /* If we are currently associated and the new config requires
146 * an RXON_ASSOC and the new config wants the associated mask enabled,
147 * we must clear the associated from the active configuration
148 * before we apply the new config */
43d59b32 149 if (iwl_is_associated(priv) && new_assoc) {
e1623446 150 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
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151 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
152
43d59b32 153 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 154 sizeof(struct iwl_rxon_cmd),
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155 &priv->active_rxon);
156
157 /* If the mask clearing failed then we set
158 * active_rxon back to what it was previously */
43d59b32 159 if (ret) {
b481de9c 160 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 161 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 162 return ret;
b481de9c 163 }
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164 }
165
e1623446 166 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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167 "* with%s RXON_FILTER_ASSOC_MSK\n"
168 "* channel = %d\n"
e174961c 169 "* bssid = %pM\n",
43d59b32 170 (new_assoc ? "" : "out"),
b481de9c 171 le16_to_cpu(priv->staging_rxon.channel),
e174961c 172 priv->staging_rxon.bssid_addr);
b481de9c 173
5b9f8cd3 174 iwl_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto);
43d59b32
EG
175
176 /* Apply the new configuration
177 * RXON unassoc clears the station table in uCode, send it before
178 * we add the bcast station. If assoc bit is set, we will send RXON
179 * after having added the bcast and bssid station.
180 */
181 if (!new_assoc) {
182 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 183 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 184 if (ret) {
15b1687c 185 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
186 return ret;
187 }
188 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
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189 }
190
e11bc028 191 priv->cfg->ops->smgmt->clear_station_table(priv);
556f8db7 192
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193 if (!priv->error_recovering)
194 priv->start_calib = 0;
195
b481de9c 196 /* Add the broadcast address so we can send broadcast frames */
4f40e4d9 197 if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
43d59b32 198 IWL_INVALID_STATION) {
15b1687c 199 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
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200 return -EIO;
201 }
202
203 /* If we have set the ASSOC_MSK and we are in BSS mode then
204 * add the IWL_AP_ID to the station rate table */
9185159d 205 if (new_assoc) {
05c914fe 206 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW
207 ret = iwl_rxon_add_station(priv,
208 priv->active_rxon.bssid_addr, 1);
209 if (ret == IWL_INVALID_STATION) {
15b1687c
WT
210 IWL_ERR(priv,
211 "Error adding AP address for TX.\n");
9185159d
TW
212 return -EIO;
213 }
214 priv->assoc_station_added = 1;
215 if (priv->default_wep_key &&
216 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT
217 IWL_ERR(priv,
218 "Could not send WEP static key.\n");
b481de9c 219 }
43d59b32
EG
220
221 /* Apply the new configuration
222 * RXON assoc doesn't clear the station table in uCode,
223 */
224 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
225 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
226 if (ret) {
15b1687c 227 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
228 return ret;
229 }
230 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
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231 }
232
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233 iwl_init_sensitivity(priv);
234
235 /* If we issue a new RXON command which required a tune then we must
236 * send a new TXPOWER command or we won't be able to Tx any frames */
237 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
238 if (ret) {
15b1687c 239 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
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240 return ret;
241 }
242
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243 return 0;
244}
245
5b9f8cd3 246void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
247{
248
45823531
AK
249 if (priv->cfg->ops->hcmd->set_rxon_chain)
250 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 251 iwlcore_commit_rxon(priv);
5da4b55f
MA
252}
253
fcab423d 254static void iwl_clear_free_frames(struct iwl_priv *priv)
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255{
256 struct list_head *element;
257
e1623446 258 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
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259 priv->frames_count);
260
261 while (!list_empty(&priv->free_frames)) {
262 element = priv->free_frames.next;
263 list_del(element);
fcab423d 264 kfree(list_entry(element, struct iwl_frame, list));
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265 priv->frames_count--;
266 }
267
268 if (priv->frames_count) {
39aadf8c 269 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
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270 priv->frames_count);
271 priv->frames_count = 0;
272 }
273}
274
fcab423d 275static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 276{
fcab423d 277 struct iwl_frame *frame;
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278 struct list_head *element;
279 if (list_empty(&priv->free_frames)) {
280 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
281 if (!frame) {
15b1687c 282 IWL_ERR(priv, "Could not allocate frame!\n");
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283 return NULL;
284 }
285
286 priv->frames_count++;
287 return frame;
288 }
289
290 element = priv->free_frames.next;
291 list_del(element);
fcab423d 292 return list_entry(element, struct iwl_frame, list);
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293}
294
fcab423d 295static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
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296{
297 memset(frame, 0, sizeof(*frame));
298 list_add(&frame->list, &priv->free_frames);
299}
300
4bf64efd
TW
301static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
302 struct ieee80211_hdr *hdr,
73ec1cc2 303 int left)
b481de9c 304{
3109ece1 305 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
306 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
307 (priv->iw_mode != NL80211_IFTYPE_AP)))
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308 return 0;
309
310 if (priv->ibss_beacon->len > left)
311 return 0;
312
313 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
314
315 return priv->ibss_beacon->len;
316}
317
5b9f8cd3 318static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
4bf64efd
TW
319 struct iwl_frame *frame, u8 rate)
320{
321 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
322 unsigned int frame_size;
323
324 tx_beacon_cmd = &frame->u.beacon;
325 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
326
327 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
328 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
329
330 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd
TW
331 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
332
333 BUG_ON(frame_size > MAX_MPDU_SIZE);
334 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
335
336 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
337 tx_beacon_cmd->tx.rate_n_flags =
338 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
339 else
340 tx_beacon_cmd->tx.rate_n_flags =
341 iwl_hw_set_rate_n_flags(rate, 0);
342
343 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
344 TX_CMD_FLG_TSF_MSK |
345 TX_CMD_FLG_STA_RATE_MSK;
346
347 return sizeof(*tx_beacon_cmd) + frame_size;
348}
5b9f8cd3 349static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 350{
fcab423d 351 struct iwl_frame *frame;
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352 unsigned int frame_size;
353 int rc;
354 u8 rate;
355
fcab423d 356 frame = iwl_get_free_frame(priv);
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357
358 if (!frame) {
15b1687c 359 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
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360 "command.\n");
361 return -ENOMEM;
362 }
363
5b9f8cd3 364 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 365
5b9f8cd3 366 frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 367
857485c0 368 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
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369 &frame->u.cmd[0]);
370
fcab423d 371 iwl_free_frame(priv, frame);
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372
373 return rc;
374}
375
7aaa1d79
SO
376static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
377{
378 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
379
380 dma_addr_t addr = get_unaligned_le32(&tb->lo);
381 if (sizeof(dma_addr_t) > sizeof(u32))
382 addr |=
383 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
384
385 return addr;
386}
387
388static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
389{
390 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
391
392 return le16_to_cpu(tb->hi_n_len) >> 4;
393}
394
395static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
396 dma_addr_t addr, u16 len)
397{
398 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
399 u16 hi_n_len = len << 4;
400
401 put_unaligned_le32(addr, &tb->lo);
402 if (sizeof(dma_addr_t) > sizeof(u32))
403 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
404
405 tb->hi_n_len = cpu_to_le16(hi_n_len);
406
407 tfd->num_tbs = idx + 1;
408}
409
410static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
411{
412 return tfd->num_tbs & 0x1f;
413}
414
415/**
416 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
417 * @priv - driver private data
418 * @txq - tx queue
419 *
420 * Does NOT advance any TFD circular buffer read/write indexes
421 * Does NOT free the TFD itself (which is within circular buffer)
422 */
423void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
424{
59606ffa 425 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
426 struct iwl_tfd *tfd;
427 struct pci_dev *dev = priv->pci_dev;
428 int index = txq->q.read_ptr;
429 int i;
430 int num_tbs;
431
432 tfd = &tfd_tmp[index];
433
434 /* Sanity check on number of chunks */
435 num_tbs = iwl_tfd_get_num_tbs(tfd);
436
437 if (num_tbs >= IWL_NUM_OF_TBS) {
438 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
439 /* @todo issue fatal error, it is quite serious situation */
440 return;
441 }
442
443 /* Unmap tx_cmd */
444 if (num_tbs)
445 pci_unmap_single(dev,
446 pci_unmap_addr(&txq->cmd[index]->meta, mapping),
447 pci_unmap_len(&txq->cmd[index]->meta, len),
96891cee 448 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
449
450 /* Unmap chunks, if any. */
451 for (i = 1; i < num_tbs; i++) {
452 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
453 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
454
455 if (txq->txb) {
456 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
457 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
458 }
459 }
460}
461
462int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
463 struct iwl_tx_queue *txq,
464 dma_addr_t addr, u16 len,
465 u8 reset, u8 pad)
466{
467 struct iwl_queue *q;
59606ffa 468 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
469 u32 num_tbs;
470
471 q = &txq->q;
59606ffa
SO
472 tfd_tmp = (struct iwl_tfd *)txq->tfds;
473 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
474
475 if (reset)
476 memset(tfd, 0, sizeof(*tfd));
477
478 num_tbs = iwl_tfd_get_num_tbs(tfd);
479
480 /* Each TFD can point to a maximum 20 Tx buffers */
481 if (num_tbs >= IWL_NUM_OF_TBS) {
482 IWL_ERR(priv, "Error can not send more than %d chunks\n",
483 IWL_NUM_OF_TBS);
484 return -EINVAL;
485 }
486
487 BUG_ON(addr & ~DMA_BIT_MASK(36));
488 if (unlikely(addr & ~IWL_TX_DMA_MASK))
489 IWL_ERR(priv, "Unaligned address = %llx\n",
490 (unsigned long long)addr);
491
492 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
493
494 return 0;
495}
496
a8e74e27
SO
497/*
498 * Tell nic where to find circular buffer of Tx Frame Descriptors for
499 * given Tx queue, and enable the DMA channel used for that queue.
500 *
501 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
502 * channels supported in hardware.
503 */
504int iwl_hw_tx_queue_init(struct iwl_priv *priv,
505 struct iwl_tx_queue *txq)
506{
507 int ret;
508 unsigned long flags;
509 int txq_id = txq->q.id;
510
511 spin_lock_irqsave(&priv->lock, flags);
512 ret = iwl_grab_nic_access(priv);
513 if (ret) {
514 spin_unlock_irqrestore(&priv->lock, flags);
515 return ret;
516 }
517
518 /* Circular buffer (TFD queue in DRAM) physical base address */
519 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
520 txq->q.dma_addr >> 8);
521
522 iwl_release_nic_access(priv);
523 spin_unlock_irqrestore(&priv->lock, flags);
524
525 return 0;
526}
527
528
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529/******************************************************************************
530 *
531 * Misc. internal state and helper functions
532 *
533 ******************************************************************************/
b481de9c 534
b481de9c 535#define MAX_UCODE_BEACON_INTERVAL 4096
b481de9c 536
3195c1f3 537static u16 iwl_adjust_beacon_interval(u16 beacon_val)
b481de9c
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538{
539 u16 new_val = 0;
540 u16 beacon_factor = 0;
541
3195c1f3
TW
542 beacon_factor = (beacon_val + MAX_UCODE_BEACON_INTERVAL)
543 / MAX_UCODE_BEACON_INTERVAL;
b481de9c
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544 new_val = beacon_val / beacon_factor;
545
41d2f291
JL
546 if (!new_val)
547 new_val = MAX_UCODE_BEACON_INTERVAL;
548
3195c1f3 549 return new_val;
b481de9c
ZY
550}
551
3195c1f3 552static void iwl_setup_rxon_timing(struct iwl_priv *priv)
b481de9c 553{
3195c1f3
TW
554 u64 tsf;
555 s32 interval_tm, rem;
b481de9c
ZY
556 unsigned long flags;
557 struct ieee80211_conf *conf = NULL;
558 u16 beacon_int = 0;
559
560 conf = ieee80211_get_hw_conf(priv->hw);
561
562 spin_lock_irqsave(&priv->lock, flags);
3195c1f3 563 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
b5d7be5e 564 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
b481de9c 565
05c914fe 566 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
3195c1f3 567 beacon_int = iwl_adjust_beacon_interval(priv->beacon_int);
b481de9c
ZY
568 priv->rxon_timing.atim_window = 0;
569 } else {
3195c1f3
TW
570 beacon_int = iwl_adjust_beacon_interval(conf->beacon_int);
571
b481de9c
ZY
572 /* TODO: we need to get atim_window from upper stack
573 * for now we set to 0 */
574 priv->rxon_timing.atim_window = 0;
575 }
576
3195c1f3 577 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
b481de9c 578
3195c1f3
TW
579 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
580 interval_tm = beacon_int * 1024;
581 rem = do_div(tsf, interval_tm);
582 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
583
584 spin_unlock_irqrestore(&priv->lock, flags);
e1623446 585 IWL_DEBUG_ASSOC(priv, "beacon interval %d beacon timer %d beacon tim %d\n",
3195c1f3
TW
586 le16_to_cpu(priv->rxon_timing.beacon_interval),
587 le32_to_cpu(priv->rxon_timing.beacon_init_val),
588 le16_to_cpu(priv->rxon_timing.atim_window));
b481de9c
ZY
589}
590
b481de9c
ZY
591/******************************************************************************
592 *
593 * Generic RX handler implementations
594 *
595 ******************************************************************************/
885ba202
TW
596static void iwl_rx_reply_alive(struct iwl_priv *priv,
597 struct iwl_rx_mem_buffer *rxb)
b481de9c 598{
db11d634 599 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
885ba202 600 struct iwl_alive_resp *palive;
b481de9c
ZY
601 struct delayed_work *pwork;
602
603 palive = &pkt->u.alive_frame;
604
e1623446 605 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
606 "0x%01X 0x%01X\n",
607 palive->is_valid, palive->ver_type,
608 palive->ver_subtype);
609
610 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 611 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
612 memcpy(&priv->card_alive_init,
613 &pkt->u.alive_frame,
885ba202 614 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
615 pwork = &priv->init_alive_start;
616 } else {
e1623446 617 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 618 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 619 sizeof(struct iwl_alive_resp));
b481de9c
ZY
620 pwork = &priv->alive_start;
621 }
622
623 /* We delay the ALIVE response by 5ms to
624 * give the HW RF Kill time to activate... */
625 if (palive->is_valid == UCODE_VALID_OK)
626 queue_delayed_work(priv->workqueue, pwork,
627 msecs_to_jiffies(5));
628 else
39aadf8c 629 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
630}
631
5b9f8cd3 632static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 633{
c79dd5b5
TW
634 struct iwl_priv *priv =
635 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
636 struct sk_buff *beacon;
637
638 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 639 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
640
641 if (!beacon) {
15b1687c 642 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
643 return;
644 }
645
646 mutex_lock(&priv->mutex);
647 /* new beacon skb is allocated every time; dispose previous.*/
648 if (priv->ibss_beacon)
649 dev_kfree_skb(priv->ibss_beacon);
650
651 priv->ibss_beacon = beacon;
652 mutex_unlock(&priv->mutex);
653
5b9f8cd3 654 iwl_send_beacon_cmd(priv);
b481de9c
ZY
655}
656
4e39317d 657/**
5b9f8cd3 658 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
659 *
660 * This callback is provided in order to send a statistics request.
661 *
662 * This timer function is continually reset to execute within
663 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
664 * was received. We need to ensure we receive the statistics in order
665 * to update the temperature used for calibrating the TXPOWER.
666 */
5b9f8cd3 667static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
668{
669 struct iwl_priv *priv = (struct iwl_priv *)data;
670
671 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
672 return;
673
61780ee3
MA
674 /* dont send host command if rf-kill is on */
675 if (!iwl_is_ready_rf(priv))
676 return;
677
4e39317d
EG
678 iwl_send_statistics_request(priv, CMD_ASYNC);
679}
680
5b9f8cd3 681static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 682 struct iwl_rx_mem_buffer *rxb)
b481de9c 683{
0a6857e7 684#ifdef CONFIG_IWLWIFI_DEBUG
db11d634 685 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2aa6ab86
TW
686 struct iwl4965_beacon_notif *beacon =
687 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 688 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 689
e1623446 690 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 691 "tsf %d %d rate %d\n",
25a6572c 692 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
693 beacon->beacon_notify_hdr.failure_frame,
694 le32_to_cpu(beacon->ibss_mgr_status),
695 le32_to_cpu(beacon->high_tsf),
696 le32_to_cpu(beacon->low_tsf), rate);
697#endif
698
05c914fe 699 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
700 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
701 queue_work(priv->workqueue, &priv->beacon_update);
702}
703
b481de9c
ZY
704/* Handle notification from uCode that card's power state is changing
705 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 706static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 707 struct iwl_rx_mem_buffer *rxb)
b481de9c 708{
db11d634 709 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
710 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
711 unsigned long status = priv->status;
712
e1623446 713 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
714 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
715 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
716
717 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
718 RF_CARD_DISABLED)) {
719
3395f6e9 720 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
721 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
722
3395f6e9
TW
723 if (!iwl_grab_nic_access(priv)) {
724 iwl_write_direct32(
b481de9c
ZY
725 priv, HBUS_TARG_MBX_C,
726 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
727
3395f6e9 728 iwl_release_nic_access(priv);
b481de9c
ZY
729 }
730
731 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 732 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 733 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3395f6e9
TW
734 if (!iwl_grab_nic_access(priv)) {
735 iwl_write_direct32(
b481de9c
ZY
736 priv, HBUS_TARG_MBX_C,
737 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
738
3395f6e9 739 iwl_release_nic_access(priv);
b481de9c
ZY
740 }
741 }
742
743 if (flags & RF_CARD_DISABLED) {
3395f6e9 744 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c 745 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
3395f6e9
TW
746 iwl_read32(priv, CSR_UCODE_DRV_GP1);
747 if (!iwl_grab_nic_access(priv))
748 iwl_release_nic_access(priv);
b481de9c
ZY
749 }
750 }
751
752 if (flags & HW_CARD_DISABLED)
753 set_bit(STATUS_RF_KILL_HW, &priv->status);
754 else
755 clear_bit(STATUS_RF_KILL_HW, &priv->status);
756
757
758 if (flags & SW_CARD_DISABLED)
759 set_bit(STATUS_RF_KILL_SW, &priv->status);
760 else
761 clear_bit(STATUS_RF_KILL_SW, &priv->status);
762
763 if (!(flags & RXON_CARD_DISABLED))
2a421b91 764 iwl_scan_cancel(priv);
b481de9c
ZY
765
766 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
767 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
768 (test_bit(STATUS_RF_KILL_SW, &status) !=
769 test_bit(STATUS_RF_KILL_SW, &priv->status)))
770 queue_work(priv->workqueue, &priv->rf_kill);
771 else
772 wake_up_interruptible(&priv->wait_command_queue);
773}
774
5b9f8cd3 775int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b
TW
776{
777 int ret;
778 unsigned long flags;
779
780 spin_lock_irqsave(&priv->lock, flags);
781 ret = iwl_grab_nic_access(priv);
782 if (ret)
783 goto err;
784
785 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 786 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
787 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
788 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
789 ~APMG_PS_CTRL_MSK_PWR_SRC);
790 } else {
791 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
792 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
793 ~APMG_PS_CTRL_MSK_PWR_SRC);
794 }
795
796 iwl_release_nic_access(priv);
797err:
798 spin_unlock_irqrestore(&priv->lock, flags);
799 return ret;
800}
801
b481de9c 802/**
5b9f8cd3 803 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
804 *
805 * Setup the RX handlers for each of the reply types sent from the uCode
806 * to the host.
807 *
808 * This function chains into the hardware specific files for them to setup
809 * any hardware specific handlers as well.
810 */
653fa4a0 811static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 812{
885ba202 813 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
814 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
815 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
5b9f8cd3 816 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 817 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
818 iwl_rx_pm_debug_statistics_notif;
819 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 820
9fbab516
BC
821 /*
822 * The same handler is used for both the REPLY to a discrete
823 * statistics request from the host as well as for the periodic
824 * statistics notifications (after received beacons) from the uCode.
b481de9c 825 */
8f91aecb
EG
826 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
827 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91 828
21c339bf 829 iwl_setup_spectrum_handlers(priv);
2a421b91
TW
830 iwl_setup_rx_scan_handlers(priv);
831
37a44211 832 /* status change handler */
5b9f8cd3 833 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 834
c1354754
TW
835 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
836 iwl_rx_missed_beacon_notif;
37a44211 837 /* Rx handlers */
1781a07f
EG
838 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
839 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
840 /* block ack */
841 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 842 /* Set up hardware specific Rx handlers */
d4789efe 843 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
844}
845
b481de9c 846/**
a55360e4 847 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
848 *
849 * Uses the priv->rx_handlers callback function array to invoke
850 * the appropriate handlers, including command responses,
851 * frame-received notifications, and other notifications.
852 */
a55360e4 853void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 854{
a55360e4 855 struct iwl_rx_mem_buffer *rxb;
db11d634 856 struct iwl_rx_packet *pkt;
a55360e4 857 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
858 u32 r, i;
859 int reclaim;
860 unsigned long flags;
5c0eef96 861 u8 fill_rx = 0;
d68ab680 862 u32 count = 8;
b481de9c 863
6440adb5
CB
864 /* uCode's read index (stored in shared DRAM) indicates the last Rx
865 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 866 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
867 i = rxq->read;
868
869 /* Rx interrupt, but nothing sent from uCode */
870 if (i == r)
e1623446 871 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 872
a55360e4 873 if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
874 fill_rx = 1;
875
b481de9c
ZY
876 while (i != r) {
877 rxb = rxq->queue[i];
878
9fbab516 879 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
880 * then a bug has been introduced in the queue refilling
881 * routines -- catch it here */
882 BUG_ON(rxb == NULL);
883
884 rxq->queue[i] = NULL;
885
e91af0af
JB
886 dma_sync_single_range_for_cpu(
887 &priv->pci_dev->dev, rxb->real_dma_addr,
888 rxb->aligned_dma_addr - rxb->real_dma_addr,
889 priv->hw_params.rx_buf_size,
890 PCI_DMA_FROMDEVICE);
db11d634 891 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
892
893 /* Reclaim a command buffer only if this packet is a response
894 * to a (driver-originated) command.
895 * If the packet (e.g. Rx frame) originated from uCode,
896 * there is no command buffer to reclaim.
897 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
898 * but apparently a few don't get set; catch them here. */
899 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
900 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 901 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 902 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 903 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
904 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
905 (pkt->hdr.cmd != REPLY_TX);
906
907 /* Based on type of command response or notification,
908 * handle those that need handling via function in
5b9f8cd3 909 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 910 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 911 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 912 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
b481de9c
ZY
913 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
914 } else {
915 /* No handling needed */
e1623446 916 IWL_DEBUG_RX(priv,
b481de9c
ZY
917 "r %d i %d No handler needed for %s, 0x%02x\n",
918 r, i, get_cmd_string(pkt->hdr.cmd),
919 pkt->hdr.cmd);
920 }
921
922 if (reclaim) {
9fbab516 923 /* Invoke any callbacks, transfer the skb to caller, and
857485c0 924 * fire off the (possibly) blocking iwl_send_cmd()
b481de9c
ZY
925 * as we reclaim the driver command queue */
926 if (rxb && rxb->skb)
17b88929 927 iwl_tx_cmd_complete(priv, rxb);
b481de9c 928 else
39aadf8c 929 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
930 }
931
932 /* For now we just don't re-use anything. We can tweak this
933 * later to try and re-use notification packets and SKBs that
934 * fail to Rx correctly */
935 if (rxb->skb != NULL) {
936 priv->alloc_rxb_skb--;
937 dev_kfree_skb_any(rxb->skb);
938 rxb->skb = NULL;
939 }
940
4018517a
JB
941 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
942 priv->hw_params.rx_buf_size + 256,
9ee1ba47 943 PCI_DMA_FROMDEVICE);
b481de9c
ZY
944 spin_lock_irqsave(&rxq->lock, flags);
945 list_add_tail(&rxb->list, &priv->rxq.rx_used);
946 spin_unlock_irqrestore(&rxq->lock, flags);
947 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
948 /* If there are a lot of unused frames,
949 * restock the Rx queue so ucode wont assert. */
950 if (fill_rx) {
951 count++;
952 if (count >= 8) {
953 priv->rxq.read = i;
f1bc4ac6 954 iwl_rx_queue_restock(priv);
5c0eef96
MA
955 count = 0;
956 }
957 }
b481de9c
ZY
958 }
959
960 /* Backtrack one entry */
961 priv->rxq.read = i;
a55360e4
TW
962 iwl_rx_queue_restock(priv);
963}
a55360e4 964
0359facc
MA
965/* call this function to flush any scheduled tasklet */
966static inline void iwl_synchronize_irq(struct iwl_priv *priv)
967{
a96a27f9 968 /* wait to make sure we flush pending tasklet*/
0359facc
MA
969 synchronize_irq(priv->pci_dev->irq);
970 tasklet_kill(&priv->irq_tasklet);
971}
972
5b9f8cd3 973static void iwl_error_recovery(struct iwl_priv *priv)
b481de9c
ZY
974{
975 unsigned long flags;
976
977 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
978 sizeof(priv->staging_rxon));
979 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 980 iwlcore_commit_rxon(priv);
b481de9c 981
4f40e4d9 982 iwl_rxon_add_station(priv, priv->bssid, 1);
b481de9c
ZY
983
984 spin_lock_irqsave(&priv->lock, flags);
985 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
986 priv->error_recovering = 0;
987 spin_unlock_irqrestore(&priv->lock, flags);
988}
989
5b9f8cd3 990static void iwl_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
991{
992 u32 inta, handled = 0;
993 u32 inta_fh;
994 unsigned long flags;
0a6857e7 995#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
996 u32 inta_mask;
997#endif
998
999 spin_lock_irqsave(&priv->lock, flags);
1000
1001 /* Ack/clear/reset pending uCode interrupts.
1002 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1003 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
1004 inta = iwl_read32(priv, CSR_INT);
1005 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1006
1007 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1008 * Any new interrupts that happen after this, either while we're
1009 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
1010 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1011 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1012
0a6857e7 1013#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 1014 if (priv->debug_level & IWL_DL_ISR) {
9fbab516 1015 /* just for debug */
3395f6e9 1016 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1017 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1018 inta, inta_mask, inta_fh);
1019 }
1020#endif
1021
1022 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1023 * atomic, make sure that inta covers all the interrupts that
1024 * we've discovered, even if FH interrupt came in just after
1025 * reading CSR_INT. */
6f83eaa1 1026 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1027 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1028 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
1029 inta |= CSR_INT_BIT_FH_TX;
1030
1031 /* Now service all interrupt bits discovered above. */
1032 if (inta & CSR_INT_BIT_HW_ERR) {
15b1687c 1033 IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
b481de9c
ZY
1034
1035 /* Tell the device to stop sending interrupts */
5b9f8cd3 1036 iwl_disable_interrupts(priv);
b481de9c 1037
5b9f8cd3 1038 iwl_irq_handle_error(priv);
b481de9c
ZY
1039
1040 handled |= CSR_INT_BIT_HW_ERR;
1041
1042 spin_unlock_irqrestore(&priv->lock, flags);
1043
1044 return;
1045 }
1046
0a6857e7 1047#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 1048 if (priv->debug_level & (IWL_DL_ISR)) {
b481de9c 1049 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e 1050 if (inta & CSR_INT_BIT_SCD)
e1623446 1051 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1052 "the frame/frames.\n");
b481de9c
ZY
1053
1054 /* Alive notification via Rx interrupt will do the real work */
1055 if (inta & CSR_INT_BIT_ALIVE)
e1623446 1056 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
b481de9c
ZY
1057 }
1058#endif
1059 /* Safely ignore these bits for debug checks below */
25c03d8e 1060 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1061
9fbab516 1062 /* HW RF KILL switch toggled */
b481de9c
ZY
1063 if (inta & CSR_INT_BIT_RF_KILL) {
1064 int hw_rf_kill = 0;
3395f6e9 1065 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
1066 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1067 hw_rf_kill = 1;
1068
e1623446 1069 IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1070 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1071
a9efa652 1072 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
1073 * the driver allows loading the ucode even if the radio
1074 * is killed. Hence update the killswitch state here. The
1075 * rfkill handler will care about restarting if needed.
a9efa652 1076 */
6cd0b1cb
HS
1077 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1078 if (hw_rf_kill)
1079 set_bit(STATUS_RF_KILL_HW, &priv->status);
1080 else
1081 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1082 queue_work(priv->workqueue, &priv->rf_kill);
edb34228 1083 }
b481de9c
ZY
1084
1085 handled |= CSR_INT_BIT_RF_KILL;
1086 }
1087
9fbab516 1088 /* Chip got too hot and stopped itself */
b481de9c 1089 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1090 IWL_ERR(priv, "Microcode CT kill error detected.\n");
b481de9c
ZY
1091 handled |= CSR_INT_BIT_CT_KILL;
1092 }
1093
1094 /* Error detected by uCode */
1095 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1096 IWL_ERR(priv, "Microcode SW error detected. "
1097 " Restarting 0x%X.\n", inta);
5b9f8cd3 1098 iwl_irq_handle_error(priv);
b481de9c
ZY
1099 handled |= CSR_INT_BIT_SW_ERR;
1100 }
1101
1102 /* uCode wakes up after power-down sleep */
1103 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1104 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1105 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
babcebfa
TW
1106 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1107 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1108 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1109 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1110 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1111 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY
1112
1113 handled |= CSR_INT_BIT_WAKEUP;
1114 }
1115
1116 /* All uCode command responses, including Tx command responses,
1117 * Rx "responses" (frame-received notification), and other
1118 * notifications from uCode come through here*/
1119 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1120 iwl_rx_handle(priv);
b481de9c
ZY
1121 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1122 }
1123
1124 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1125 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
b481de9c 1126 handled |= CSR_INT_BIT_FH_TX;
dbb983b7
RR
1127 /* FH finished to write, send event */
1128 priv->ucode_write_complete = 1;
1129 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1130 }
1131
1132 if (inta & ~handled)
15b1687c 1133 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
b481de9c
ZY
1134
1135 if (inta & ~CSR_INI_SET_MASK) {
39aadf8c 1136 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
b481de9c 1137 inta & ~CSR_INI_SET_MASK);
39aadf8c 1138 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1139 }
1140
1141 /* Re-enable all interrupts */
0359facc
MA
1142 /* only Re-enable if diabled by irq */
1143 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1144 iwl_enable_interrupts(priv);
b481de9c 1145
0a6857e7 1146#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 1147 if (priv->debug_level & (IWL_DL_ISR)) {
3395f6e9
TW
1148 inta = iwl_read32(priv, CSR_INT);
1149 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1150 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1151 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1152 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1153 }
1154#endif
1155 spin_unlock_irqrestore(&priv->lock, flags);
1156}
1157
b481de9c
ZY
1158/******************************************************************************
1159 *
1160 * uCode download functions
1161 *
1162 ******************************************************************************/
1163
5b9f8cd3 1164static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1165{
98c92211
TW
1166 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1167 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1168 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1169 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1170 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1171 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1172}
1173
5b9f8cd3 1174static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1175{
1176 /* Remove all resets to allow NIC to operate */
1177 iwl_write32(priv, CSR_RESET, 0);
1178}
1179
1180
b481de9c 1181/**
5b9f8cd3 1182 * iwl_read_ucode - Read uCode images from disk file.
b481de9c
ZY
1183 *
1184 * Copy into buffers for card to fetch via bus-mastering
1185 */
5b9f8cd3 1186static int iwl_read_ucode(struct iwl_priv *priv)
b481de9c 1187{
14b3d338 1188 struct iwl_ucode *ucode;
a0987a8d 1189 int ret = -EINVAL, index;
b481de9c 1190 const struct firmware *ucode_raw;
a0987a8d
RC
1191 const char *name_pre = priv->cfg->fw_name_pre;
1192 const unsigned int api_max = priv->cfg->ucode_api_max;
1193 const unsigned int api_min = priv->cfg->ucode_api_min;
1194 char buf[25];
b481de9c
ZY
1195 u8 *src;
1196 size_t len;
a0987a8d 1197 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
1198
1199 /* Ask kernel firmware_class module to get the boot firmware off disk.
1200 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
1201 for (index = api_max; index >= api_min; index--) {
1202 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1203 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1204 if (ret < 0) {
15b1687c 1205 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
1206 buf, ret);
1207 if (ret == -ENOENT)
1208 continue;
1209 else
1210 goto error;
1211 } else {
1212 if (index < api_max)
15b1687c
WT
1213 IWL_ERR(priv, "Loaded firmware %s, "
1214 "which is deprecated. "
1215 "Please use API v%u instead.\n",
a0987a8d 1216 buf, api_max);
15b1687c 1217
e1623446 1218 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
a0987a8d
RC
1219 buf, ucode_raw->size);
1220 break;
1221 }
b481de9c
ZY
1222 }
1223
a0987a8d
RC
1224 if (ret < 0)
1225 goto error;
b481de9c
ZY
1226
1227 /* Make sure that we got at least our header! */
1228 if (ucode_raw->size < sizeof(*ucode)) {
15b1687c 1229 IWL_ERR(priv, "File size way too small!\n");
90e759d1 1230 ret = -EINVAL;
b481de9c
ZY
1231 goto err_release;
1232 }
1233
1234 /* Data from ucode file: header followed by uCode images */
1235 ucode = (void *)ucode_raw->data;
1236
c02b3acd 1237 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1238 api_ver = IWL_UCODE_API(priv->ucode_ver);
b481de9c
ZY
1239 inst_size = le32_to_cpu(ucode->inst_size);
1240 data_size = le32_to_cpu(ucode->data_size);
1241 init_size = le32_to_cpu(ucode->init_size);
1242 init_data_size = le32_to_cpu(ucode->init_data_size);
1243 boot_size = le32_to_cpu(ucode->boot_size);
1244
a0987a8d
RC
1245 /* api_ver should match the api version forming part of the
1246 * firmware filename ... but we don't check for that and only rely
877d0310 1247 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1248
1249 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1250 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1251 "Driver supports v%u, firmware is v%u.\n",
1252 api_max, api_ver);
1253 priv->ucode_ver = 0;
1254 ret = -EINVAL;
1255 goto err_release;
1256 }
1257 if (api_ver != api_max)
978785a3 1258 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1259 "got v%u. New firmware can be obtained "
1260 "from http://www.intellinuxwireless.org.\n",
1261 api_max, api_ver);
1262
978785a3
TW
1263 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1264 IWL_UCODE_MAJOR(priv->ucode_ver),
1265 IWL_UCODE_MINOR(priv->ucode_ver),
1266 IWL_UCODE_API(priv->ucode_ver),
1267 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1268
e1623446 1269 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1270 priv->ucode_ver);
e1623446 1271 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1272 inst_size);
e1623446 1273 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1274 data_size);
e1623446 1275 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1276 init_size);
e1623446 1277 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1278 init_data_size);
e1623446 1279 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1280 boot_size);
1281
1282 /* Verify size of file vs. image size info in file's header */
1283 if (ucode_raw->size < sizeof(*ucode) +
1284 inst_size + data_size + init_size +
1285 init_data_size + boot_size) {
1286
e1623446 1287 IWL_DEBUG_INFO(priv, "uCode file size %d too small\n",
b481de9c 1288 (int)ucode_raw->size);
90e759d1 1289 ret = -EINVAL;
b481de9c
ZY
1290 goto err_release;
1291 }
1292
1293 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1294 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1295 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
1296 inst_size);
1297 ret = -EINVAL;
b481de9c
ZY
1298 goto err_release;
1299 }
1300
099b40b7 1301 if (data_size > priv->hw_params.max_data_size) {
e1623446 1302 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
1303 data_size);
1304 ret = -EINVAL;
b481de9c
ZY
1305 goto err_release;
1306 }
099b40b7 1307 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1308 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1309 init_size);
90e759d1 1310 ret = -EINVAL;
b481de9c
ZY
1311 goto err_release;
1312 }
099b40b7 1313 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1314 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1
TW
1315 init_data_size);
1316 ret = -EINVAL;
b481de9c
ZY
1317 goto err_release;
1318 }
099b40b7 1319 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1320 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1321 boot_size);
90e759d1 1322 ret = -EINVAL;
b481de9c
ZY
1323 goto err_release;
1324 }
1325
1326 /* Allocate ucode buffers for card's bus-master loading ... */
1327
1328 /* Runtime instructions and 2 copies of data:
1329 * 1) unmodified from disk
1330 * 2) backup cache for save/restore during power-downs */
1331 priv->ucode_code.len = inst_size;
98c92211 1332 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1333
1334 priv->ucode_data.len = data_size;
98c92211 1335 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1336
1337 priv->ucode_data_backup.len = data_size;
98c92211 1338 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1339
1f304e4e
ZY
1340 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1341 !priv->ucode_data_backup.v_addr)
1342 goto err_pci_alloc;
1343
b481de9c 1344 /* Initialization instructions and data */
90e759d1
TW
1345 if (init_size && init_data_size) {
1346 priv->ucode_init.len = init_size;
98c92211 1347 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1348
1349 priv->ucode_init_data.len = init_data_size;
98c92211 1350 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1351
1352 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1353 goto err_pci_alloc;
1354 }
b481de9c
ZY
1355
1356 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1357 if (boot_size) {
1358 priv->ucode_boot.len = boot_size;
98c92211 1359 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1360
90e759d1
TW
1361 if (!priv->ucode_boot.v_addr)
1362 goto err_pci_alloc;
1363 }
b481de9c
ZY
1364
1365 /* Copy images into buffers for card's bus-master reads ... */
1366
1367 /* Runtime instructions (first block of data in file) */
1368 src = &ucode->data[0];
1369 len = priv->ucode_code.len;
e1623446 1370 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1371 memcpy(priv->ucode_code.v_addr, src, len);
e1623446 1372 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1373 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1374
1375 /* Runtime data (2nd block)
5b9f8cd3 1376 * NOTE: Copy into backup buffer will be done in iwl_up() */
b481de9c
ZY
1377 src = &ucode->data[inst_size];
1378 len = priv->ucode_data.len;
e1623446 1379 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1380 memcpy(priv->ucode_data.v_addr, src, len);
1381 memcpy(priv->ucode_data_backup.v_addr, src, len);
1382
1383 /* Initialization instructions (3rd block) */
1384 if (init_size) {
1385 src = &ucode->data[inst_size + data_size];
1386 len = priv->ucode_init.len;
e1623446 1387 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1388 len);
b481de9c
ZY
1389 memcpy(priv->ucode_init.v_addr, src, len);
1390 }
1391
1392 /* Initialization data (4th block) */
1393 if (init_data_size) {
1394 src = &ucode->data[inst_size + data_size + init_size];
1395 len = priv->ucode_init_data.len;
e1623446 1396 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1397 len);
b481de9c
ZY
1398 memcpy(priv->ucode_init_data.v_addr, src, len);
1399 }
1400
1401 /* Bootstrap instructions (5th block) */
1402 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
1403 len = priv->ucode_boot.len;
e1623446 1404 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1405 memcpy(priv->ucode_boot.v_addr, src, len);
1406
1407 /* We have our copies now, allow OS release its copies */
1408 release_firmware(ucode_raw);
1409 return 0;
1410
1411 err_pci_alloc:
15b1687c 1412 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 1413 ret = -ENOMEM;
5b9f8cd3 1414 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
1415
1416 err_release:
1417 release_firmware(ucode_raw);
1418
1419 error:
90e759d1 1420 return ret;
b481de9c
ZY
1421}
1422
b481de9c 1423/**
4a4a9e81 1424 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1425 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1426 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1427 */
4a4a9e81 1428static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 1429{
57aab75a 1430 int ret = 0;
b481de9c 1431
e1623446 1432 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
1433
1434 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1435 /* We had an error bringing up the hardware, so take it
1436 * all the way back down so we can try again */
e1623446 1437 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
1438 goto restart;
1439 }
1440
1441 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1442 * This is a paranoid check, because we would not have gotten the
1443 * "runtime" alive if code weren't properly loaded. */
b0692f2f 1444 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
1445 /* Runtime instruction load was bad;
1446 * take it all the way back down so we can try again */
e1623446 1447 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
1448 goto restart;
1449 }
1450
e11bc028 1451 priv->cfg->ops->smgmt->clear_station_table(priv);
57aab75a
TW
1452 ret = priv->cfg->ops->lib->alive_notify(priv);
1453 if (ret) {
39aadf8c
WT
1454 IWL_WARN(priv,
1455 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
1456 goto restart;
1457 }
1458
5b9f8cd3 1459 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
1460 set_bit(STATUS_ALIVE, &priv->status);
1461
fee1247a 1462 if (iwl_is_rfkill(priv))
b481de9c
ZY
1463 return;
1464
36d6825b 1465 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
1466
1467 priv->active_rate = priv->rates_mask;
1468 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1469
3109ece1 1470 if (iwl_is_associated(priv)) {
c1adf9fb
GG
1471 struct iwl_rxon_cmd *active_rxon =
1472 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
1473 /* apply any changes in staging */
1474 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
1475 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1476 } else {
1477 /* Initialize our rx_config data */
5b9f8cd3 1478 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
1479
1480 if (priv->cfg->ops->hcmd->set_rxon_chain)
1481 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1482
b481de9c
ZY
1483 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1484 }
1485
9fbab516 1486 /* Configure Bluetooth device coexistence support */
5b9f8cd3 1487 iwl_send_bt_config(priv);
b481de9c 1488
4a4a9e81
TW
1489 iwl_reset_run_time_calib(priv);
1490
b481de9c 1491 /* Configure the adapter for unassociated operation */
e0158e61 1492 iwlcore_commit_rxon(priv);
b481de9c
ZY
1493
1494 /* At this point, the NIC is initialized and operational */
47f4a587 1495 iwl_rf_kill_ct_config(priv);
5a66926a 1496
fe00b5a5
RC
1497 iwl_leds_register(priv);
1498
e1623446 1499 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 1500 set_bit(STATUS_READY, &priv->status);
5a66926a 1501 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1502
1503 if (priv->error_recovering)
5b9f8cd3 1504 iwl_error_recovery(priv);
b481de9c 1505
58d0f361 1506 iwl_power_update_mode(priv, 1);
c46fbefa 1507
ada17513
MA
1508 /* reassociate for ADHOC mode */
1509 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1510 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1511 priv->vif);
1512 if (beacon)
1513 iwl_mac_beacon_update(priv->hw, beacon);
1514 }
1515
1516
c46fbefa 1517 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 1518 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 1519
b481de9c
ZY
1520 return;
1521
1522 restart:
1523 queue_work(priv->workqueue, &priv->restart);
1524}
1525
4e39317d 1526static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 1527
5b9f8cd3 1528static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1529{
1530 unsigned long flags;
1531 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 1532
e1623446 1533 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 1534
b481de9c
ZY
1535 if (!exit_pending)
1536 set_bit(STATUS_EXIT_PENDING, &priv->status);
1537
ab53d8af
MA
1538 iwl_leds_unregister(priv);
1539
e11bc028 1540 priv->cfg->ops->smgmt->clear_station_table(priv);
b481de9c
ZY
1541
1542 /* Unblock any waiting calls */
1543 wake_up_interruptible_all(&priv->wait_command_queue);
1544
b481de9c
ZY
1545 /* Wipe out the EXIT_PENDING status bit if we are not actually
1546 * exiting the module */
1547 if (!exit_pending)
1548 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1549
1550 /* stop and reset the on-board processor */
3395f6e9 1551 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
1552
1553 /* tell the device to stop sending interrupts */
0359facc 1554 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 1555 iwl_disable_interrupts(priv);
0359facc
MA
1556 spin_unlock_irqrestore(&priv->lock, flags);
1557 iwl_synchronize_irq(priv);
b481de9c
ZY
1558
1559 if (priv->mac80211_registered)
1560 ieee80211_stop_queues(priv->hw);
1561
5b9f8cd3 1562 /* If we have not previously called iwl_init() then
6da3a13e 1563 * clear all bits but the RF Kill bits and return */
fee1247a 1564 if (!iwl_is_init(priv)) {
b481de9c
ZY
1565 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1566 STATUS_RF_KILL_HW |
1567 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
1568 STATUS_RF_KILL_SW |
9788864e
RC
1569 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1570 STATUS_GEO_CONFIGURED |
052ec3f1
MA
1571 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1572 STATUS_EXIT_PENDING;
b481de9c
ZY
1573 goto exit;
1574 }
1575
6da3a13e
WYG
1576 /* ...otherwise clear out all the status bits but the RF Kill
1577 * bits and continue taking the NIC down. */
b481de9c
ZY
1578 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1579 STATUS_RF_KILL_HW |
1580 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
1581 STATUS_RF_KILL_SW |
9788864e
RC
1582 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1583 STATUS_GEO_CONFIGURED |
b481de9c 1584 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
1585 STATUS_FW_ERROR |
1586 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1587 STATUS_EXIT_PENDING;
b481de9c
ZY
1588
1589 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 1590 iwl_clear_bit(priv, CSR_GP_CNTRL,
9fbab516 1591 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
1592 spin_unlock_irqrestore(&priv->lock, flags);
1593
da1bc453 1594 iwl_txq_ctx_stop(priv);
b3bbacb7 1595 iwl_rxq_stop(priv);
b481de9c
ZY
1596
1597 spin_lock_irqsave(&priv->lock, flags);
3395f6e9
TW
1598 if (!iwl_grab_nic_access(priv)) {
1599 iwl_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 1600 APMG_CLK_VAL_DMA_CLK_RQT);
3395f6e9 1601 iwl_release_nic_access(priv);
b481de9c
ZY
1602 }
1603 spin_unlock_irqrestore(&priv->lock, flags);
1604
1605 udelay(5);
1606
7f066108 1607 /* FIXME: apm_ops.suspend(priv) */
6da3a13e 1608 if (exit_pending)
d535311e
GG
1609 priv->cfg->ops->lib->apm_ops.stop(priv);
1610 else
1611 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 1612 exit:
885ba202 1613 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
1614
1615 if (priv->ibss_beacon)
1616 dev_kfree_skb(priv->ibss_beacon);
1617 priv->ibss_beacon = NULL;
1618
1619 /* clear out any free frames */
fcab423d 1620 iwl_clear_free_frames(priv);
b481de9c
ZY
1621}
1622
5b9f8cd3 1623static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1624{
1625 mutex_lock(&priv->mutex);
5b9f8cd3 1626 __iwl_down(priv);
b481de9c 1627 mutex_unlock(&priv->mutex);
b24d22b1 1628
4e39317d 1629 iwl_cancel_deferred_work(priv);
b481de9c
ZY
1630}
1631
1632#define MAX_HW_RESTARTS 5
1633
5b9f8cd3 1634static int __iwl_up(struct iwl_priv *priv)
b481de9c 1635{
57aab75a
TW
1636 int i;
1637 int ret;
b481de9c
ZY
1638
1639 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 1640 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
1641 return -EIO;
1642 }
1643
e903fbd4 1644 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 1645 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
1646 return -EIO;
1647 }
1648
e655b9f0 1649 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 1650 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 1651 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 1652 else
e655b9f0 1653 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 1654
c1842d61 1655 if (iwl_is_rfkill(priv)) {
5b9f8cd3 1656 iwl_enable_interrupts(priv);
39aadf8c 1657 IWL_WARN(priv, "Radio disabled by %s RF Kill switch\n",
3bff19c2 1658 test_bit(STATUS_RF_KILL_HW, &priv->status) ? "HW" : "SW");
c1842d61 1659 return 0;
b481de9c
ZY
1660 }
1661
3395f6e9 1662 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 1663
1053d35f 1664 ret = iwl_hw_nic_init(priv);
57aab75a 1665 if (ret) {
15b1687c 1666 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 1667 return ret;
b481de9c
ZY
1668 }
1669
1670 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
1671 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1672 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
1673 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1674
1675 /* clear (again), then enable host interrupts */
3395f6e9 1676 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 1677 iwl_enable_interrupts(priv);
b481de9c
ZY
1678
1679 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
1680 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1681 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
1682
1683 /* Copy original ucode data image from disk into backup cache.
1684 * This will be used to initialize the on-board processor's
1685 * data SRAM for a clean start when the runtime program first loads. */
1686 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 1687 priv->ucode_data.len);
b481de9c 1688
b481de9c
ZY
1689 for (i = 0; i < MAX_HW_RESTARTS; i++) {
1690
e11bc028 1691 priv->cfg->ops->smgmt->clear_station_table(priv);
b481de9c
ZY
1692
1693 /* load bootstrap state machine,
1694 * load bootstrap program into processor's memory,
1695 * prepare to load the "initialize" uCode */
57aab75a 1696 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 1697
57aab75a 1698 if (ret) {
15b1687c
WT
1699 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
1700 ret);
b481de9c
ZY
1701 continue;
1702 }
1703
f3d5b45b
EG
1704 /* Clear out the uCode error bit if it is set */
1705 clear_bit(STATUS_FW_ERROR, &priv->status);
1706
b481de9c 1707 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 1708 iwl_nic_start(priv);
b481de9c 1709
e1623446 1710 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
1711
1712 return 0;
1713 }
1714
1715 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 1716 __iwl_down(priv);
64e72c3e 1717 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
1718
1719 /* tried to restart and config the device for as long as our
1720 * patience could withstand */
15b1687c 1721 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
1722 return -EIO;
1723}
1724
1725
1726/*****************************************************************************
1727 *
1728 * Workqueue callbacks
1729 *
1730 *****************************************************************************/
1731
4a4a9e81 1732static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 1733{
c79dd5b5
TW
1734 struct iwl_priv *priv =
1735 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
1736
1737 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1738 return;
1739
1740 mutex_lock(&priv->mutex);
f3ccc08c 1741 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
1742 mutex_unlock(&priv->mutex);
1743}
1744
4a4a9e81 1745static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 1746{
c79dd5b5
TW
1747 struct iwl_priv *priv =
1748 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
1749
1750 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1751 return;
1752
1753 mutex_lock(&priv->mutex);
4a4a9e81 1754 iwl_alive_start(priv);
b481de9c
ZY
1755 mutex_unlock(&priv->mutex);
1756}
1757
16e727e8
EG
1758static void iwl_bg_run_time_calib_work(struct work_struct *work)
1759{
1760 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1761 run_time_calib_work);
1762
1763 mutex_lock(&priv->mutex);
1764
1765 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1766 test_bit(STATUS_SCANNING, &priv->status)) {
1767 mutex_unlock(&priv->mutex);
1768 return;
1769 }
1770
1771 if (priv->start_calib) {
1772 iwl_chain_noise_calibration(priv, &priv->statistics);
1773
1774 iwl_sensitivity_calibration(priv, &priv->statistics);
1775 }
1776
1777 mutex_unlock(&priv->mutex);
1778 return;
1779}
1780
5b9f8cd3 1781static void iwl_bg_up(struct work_struct *data)
b481de9c 1782{
c79dd5b5 1783 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
1784
1785 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1786 return;
1787
1788 mutex_lock(&priv->mutex);
5b9f8cd3 1789 __iwl_up(priv);
b481de9c 1790 mutex_unlock(&priv->mutex);
80fcc9e2 1791 iwl_rfkill_set_hw_state(priv);
b481de9c
ZY
1792}
1793
5b9f8cd3 1794static void iwl_bg_restart(struct work_struct *data)
b481de9c 1795{
c79dd5b5 1796 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
1797
1798 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1799 return;
1800
5b9f8cd3 1801 iwl_down(priv);
b481de9c
ZY
1802 queue_work(priv->workqueue, &priv->up);
1803}
1804
5b9f8cd3 1805static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 1806{
c79dd5b5
TW
1807 struct iwl_priv *priv =
1808 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
1809
1810 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1811 return;
1812
1813 mutex_lock(&priv->mutex);
a55360e4 1814 iwl_rx_replenish(priv);
b481de9c
ZY
1815 mutex_unlock(&priv->mutex);
1816}
1817
7878a5a4
MA
1818#define IWL_DELAY_NEXT_SCAN (HZ*2)
1819
5bbe233b 1820void iwl_post_associate(struct iwl_priv *priv)
b481de9c 1821{
b481de9c 1822 struct ieee80211_conf *conf = NULL;
857485c0 1823 int ret = 0;
1ff50bda 1824 unsigned long flags;
b481de9c 1825
05c914fe 1826 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 1827 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
1828 return;
1829 }
1830
e1623446 1831 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 1832 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
1833
1834
1835 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1836 return;
1837
b481de9c 1838
508e32e1 1839 if (!priv->vif || !priv->is_open)
948c171c 1840 return;
508e32e1 1841
c90a74ba 1842 iwl_power_cancel_timeout(priv);
2a421b91 1843 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 1844
b481de9c
ZY
1845 conf = ieee80211_get_hw_conf(priv->hw);
1846
1847 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 1848 iwlcore_commit_rxon(priv);
b481de9c 1849
3195c1f3 1850 iwl_setup_rxon_timing(priv);
857485c0 1851 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 1852 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 1853 if (ret)
39aadf8c 1854 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
1855 "Attempting to continue.\n");
1856
1857 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
1858
42eb7c64 1859 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 1860
45823531
AK
1861 if (priv->cfg->ops->hcmd->set_rxon_chain)
1862 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1863
b481de9c
ZY
1864 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
1865
e1623446 1866 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
1867 priv->assoc_id, priv->beacon_int);
1868
1869 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
1870 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1871 else
1872 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1873
1874 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
1875 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
1876 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1877 else
1878 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1879
05c914fe 1880 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
1881 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1882
1883 }
1884
e0158e61 1885 iwlcore_commit_rxon(priv);
b481de9c
ZY
1886
1887 switch (priv->iw_mode) {
05c914fe 1888 case NL80211_IFTYPE_STATION:
b481de9c
ZY
1889 break;
1890
05c914fe 1891 case NL80211_IFTYPE_ADHOC:
b481de9c 1892
c46fbefa
AK
1893 /* assume default assoc id */
1894 priv->assoc_id = 1;
b481de9c 1895
4f40e4d9 1896 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 1897 iwl_send_beacon_cmd(priv);
b481de9c
ZY
1898
1899 break;
1900
1901 default:
15b1687c 1902 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 1903 __func__, priv->iw_mode);
b481de9c
ZY
1904 break;
1905 }
1906
05c914fe 1907 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
1908 priv->assoc_station_added = 1;
1909
1ff50bda
EG
1910 spin_lock_irqsave(&priv->lock, flags);
1911 iwl_activate_qos(priv, 0);
1912 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 1913
04816448
GE
1914 /* the chain noise calibration will enabled PM upon completion
1915 * If chain noise has already been run, then we need to enable
1916 * power management here */
1917 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
1918 iwl_power_enable_management(priv);
c90a74ba
EG
1919
1920 /* Enable Rx differential gain and sensitivity calibrations */
1921 iwl_chain_noise_reset(priv);
1922 priv->start_calib = 1;
1923
508e32e1
RC
1924}
1925
b481de9c
ZY
1926/*****************************************************************************
1927 *
1928 * mac80211 entry point functions
1929 *
1930 *****************************************************************************/
1931
154b25ce 1932#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 1933
5b9f8cd3 1934static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 1935{
c79dd5b5 1936 struct iwl_priv *priv = hw->priv;
5a66926a 1937 int ret;
b481de9c 1938
e1623446 1939 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
1940
1941 /* we should be verifying the device is ready to be opened */
1942 mutex_lock(&priv->mutex);
1943
c1adf9fb 1944 memset(&priv->staging_rxon, 0, sizeof(struct iwl_rxon_cmd));
5a66926a
ZY
1945 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
1946 * ucode filename and max sizes are card-specific. */
b481de9c 1947
5a66926a 1948 if (!priv->ucode_code.len) {
5b9f8cd3 1949 ret = iwl_read_ucode(priv);
5a66926a 1950 if (ret) {
15b1687c 1951 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a 1952 mutex_unlock(&priv->mutex);
6cd0b1cb 1953 return ret;
5a66926a
ZY
1954 }
1955 }
b481de9c 1956
5b9f8cd3 1957 ret = __iwl_up(priv);
5a66926a 1958
b481de9c 1959 mutex_unlock(&priv->mutex);
5a66926a 1960
80fcc9e2
AG
1961 iwl_rfkill_set_hw_state(priv);
1962
e655b9f0 1963 if (ret)
6cd0b1cb 1964 return ret;
e655b9f0 1965
c1842d61
TW
1966 if (iwl_is_rfkill(priv))
1967 goto out;
1968
e1623446 1969 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 1970
fe9b6b72 1971 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 1972 * mac80211 will not be run successfully. */
154b25ce
EG
1973 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
1974 test_bit(STATUS_READY, &priv->status),
1975 UCODE_READY_TIMEOUT);
1976 if (!ret) {
1977 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 1978 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 1979 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 1980 return -ETIMEDOUT;
5a66926a 1981 }
fe9b6b72 1982 }
0a078ffa 1983
c1842d61 1984out:
0a078ffa 1985 priv->is_open = 1;
e1623446 1986 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
1987 return 0;
1988}
1989
5b9f8cd3 1990static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 1991{
c79dd5b5 1992 struct iwl_priv *priv = hw->priv;
b481de9c 1993
e1623446 1994 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 1995
e655b9f0 1996 if (!priv->is_open) {
e1623446 1997 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
e655b9f0
ZY
1998 return;
1999 }
2000
b481de9c 2001 priv->is_open = 0;
5a66926a 2002
fee1247a 2003 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
2004 /* stop mac, cancel any scan request and clear
2005 * RXON_FILTER_ASSOC_MSK BIT
2006 */
5a66926a 2007 mutex_lock(&priv->mutex);
2a421b91 2008 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2009 mutex_unlock(&priv->mutex);
fde3571f
MA
2010 }
2011
5b9f8cd3 2012 iwl_down(priv);
5a66926a
ZY
2013
2014 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2015
2016 /* enable interrupts again in order to receive rfkill changes */
2017 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2018 iwl_enable_interrupts(priv);
948c171c 2019
e1623446 2020 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2021}
2022
5b9f8cd3 2023static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2024{
c79dd5b5 2025 struct iwl_priv *priv = hw->priv;
b481de9c 2026
e1623446 2027 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2028
e1623446 2029 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2030 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2031
e039fa4a 2032 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2033 dev_kfree_skb_any(skb);
2034
e1623446 2035 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2036 return NETDEV_TX_OK;
b481de9c
ZY
2037}
2038
60690a6a 2039void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2040{
857485c0 2041 int ret = 0;
1ff50bda 2042 unsigned long flags;
b481de9c 2043
d986bcd1 2044 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2045 return;
2046
2047 /* The following should be done only at AP bring up */
3195c1f3 2048 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2049
2050 /* RXON - unassoc (to set timing command) */
2051 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2052 iwlcore_commit_rxon(priv);
b481de9c
ZY
2053
2054 /* RXON Timing */
3195c1f3 2055 iwl_setup_rxon_timing(priv);
857485c0 2056 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2057 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2058 if (ret)
39aadf8c 2059 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2060 "Attempting to continue.\n");
2061
45823531
AK
2062 if (priv->cfg->ops->hcmd->set_rxon_chain)
2063 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2064
2065 /* FIXME: what should be the assoc_id for AP? */
2066 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2067 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2068 priv->staging_rxon.flags |=
2069 RXON_FLG_SHORT_PREAMBLE_MSK;
2070 else
2071 priv->staging_rxon.flags &=
2072 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2073
2074 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2075 if (priv->assoc_capability &
2076 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2077 priv->staging_rxon.flags |=
2078 RXON_FLG_SHORT_SLOT_MSK;
2079 else
2080 priv->staging_rxon.flags &=
2081 ~RXON_FLG_SHORT_SLOT_MSK;
2082
05c914fe 2083 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2084 priv->staging_rxon.flags &=
2085 ~RXON_FLG_SHORT_SLOT_MSK;
2086 }
2087 /* restore RXON assoc */
2088 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2089 iwlcore_commit_rxon(priv);
1ff50bda
EG
2090 spin_lock_irqsave(&priv->lock, flags);
2091 iwl_activate_qos(priv, 1);
2092 spin_unlock_irqrestore(&priv->lock, flags);
4f40e4d9 2093 iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
e1493deb 2094 }
5b9f8cd3 2095 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2096
2097 /* FIXME - we need to add code here to detect a totally new
2098 * configuration, reset the AP, unassoc, rxon timing, assoc,
2099 * clear sta table, add BCAST sta... */
2100}
2101
5b9f8cd3 2102static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
ab885f8c
EG
2103 struct ieee80211_key_conf *keyconf, const u8 *addr,
2104 u32 iv32, u16 *phase1key)
2105{
ab885f8c 2106
9f58671e 2107 struct iwl_priv *priv = hw->priv;
e1623446 2108 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2109
9f58671e 2110 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
ab885f8c 2111
e1623446 2112 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2113}
2114
5b9f8cd3 2115static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2116 struct ieee80211_vif *vif,
2117 struct ieee80211_sta *sta,
b481de9c
ZY
2118 struct ieee80211_key_conf *key)
2119{
c79dd5b5 2120 struct iwl_priv *priv = hw->priv;
42986796
WT
2121 const u8 *addr;
2122 int ret;
2123 u8 sta_id;
2124 bool is_default_wep_key = false;
b481de9c 2125
e1623446 2126 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2127
099b40b7 2128 if (priv->hw_params.sw_crypto) {
e1623446 2129 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2130 return -EOPNOTSUPP;
2131 }
42986796 2132 addr = sta ? sta->addr : iwl_bcast_addr;
e11bc028 2133 sta_id = priv->cfg->ops->smgmt->find_station(priv, addr);
6974e363 2134 if (sta_id == IWL_INVALID_STATION) {
e1623446 2135 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2136 addr);
6974e363 2137 return -EINVAL;
b481de9c 2138
deb09c43 2139 }
b481de9c 2140
6974e363 2141 mutex_lock(&priv->mutex);
2a421b91 2142 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2143 mutex_unlock(&priv->mutex);
2144
2145 /* If we are getting WEP group key and we didn't receive any key mapping
2146 * so far, we are in legacy wep mode (group key only), otherwise we are
2147 * in 1X mode.
2148 * In legacy wep mode, we use another host command to the uCode */
5425e490 2149 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2150 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2151 if (cmd == SET_KEY)
2152 is_default_wep_key = !priv->key_mapping_key;
2153 else
ccc038ab
EG
2154 is_default_wep_key =
2155 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2156 }
052c4b9f 2157
b481de9c 2158 switch (cmd) {
deb09c43 2159 case SET_KEY:
6974e363
EG
2160 if (is_default_wep_key)
2161 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2162 else
7480513f 2163 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2164
e1623446 2165 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2166 break;
2167 case DISABLE_KEY:
6974e363
EG
2168 if (is_default_wep_key)
2169 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2170 else
3ec47732 2171 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2172
e1623446 2173 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2174 break;
2175 default:
deb09c43 2176 ret = -EINVAL;
b481de9c
ZY
2177 }
2178
e1623446 2179 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2180
deb09c43 2181 return ret;
b481de9c
ZY
2182}
2183
5b9f8cd3 2184static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
d783b061 2185 enum ieee80211_ampdu_mlme_action action,
17741cdc 2186 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2187{
2188 struct iwl_priv *priv = hw->priv;
5c2207c6 2189 int ret;
d783b061 2190
e1623446 2191 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2192 sta->addr, tid);
d783b061
TW
2193
2194 if (!(priv->cfg->sku & IWL_SKU_N))
2195 return -EACCES;
2196
2197 switch (action) {
2198 case IEEE80211_AMPDU_RX_START:
e1623446 2199 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2200 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2201 case IEEE80211_AMPDU_RX_STOP:
e1623446 2202 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2203 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2204 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2205 return 0;
2206 else
2207 return ret;
d783b061 2208 case IEEE80211_AMPDU_TX_START:
e1623446 2209 IWL_DEBUG_HT(priv, "start Tx\n");
17741cdc 2210 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2211 case IEEE80211_AMPDU_TX_STOP:
e1623446 2212 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2213 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2214 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2215 return 0;
2216 else
2217 return ret;
d783b061 2218 default:
e1623446 2219 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2220 return -EINVAL;
2221 break;
2222 }
2223 return 0;
2224}
9f58671e 2225
5b9f8cd3 2226static int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2227 struct ieee80211_tx_queue_stats *stats)
2228{
c79dd5b5 2229 struct iwl_priv *priv = hw->priv;
b481de9c 2230 int i, avail;
16466903 2231 struct iwl_tx_queue *txq;
443cfd45 2232 struct iwl_queue *q;
b481de9c
ZY
2233 unsigned long flags;
2234
e1623446 2235 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2236
fee1247a 2237 if (!iwl_is_ready_rf(priv)) {
e1623446 2238 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
b481de9c
ZY
2239 return -EIO;
2240 }
2241
2242 spin_lock_irqsave(&priv->lock, flags);
2243
2244 for (i = 0; i < AC_NUM; i++) {
2245 txq = &priv->txq[i];
2246 q = &txq->q;
443cfd45 2247 avail = iwl_queue_space(q);
b481de9c 2248
57ffc589
JB
2249 stats[i].len = q->n_window - avail;
2250 stats[i].limit = q->n_window - q->high_mark;
2251 stats[i].count = q->n_window;
b481de9c
ZY
2252
2253 }
2254 spin_unlock_irqrestore(&priv->lock, flags);
2255
e1623446 2256 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2257
2258 return 0;
2259}
2260
5b9f8cd3 2261static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2262 struct ieee80211_low_level_stats *stats)
2263{
bf403db8
EK
2264 struct iwl_priv *priv = hw->priv;
2265
2266 priv = hw->priv;
e1623446
TW
2267 IWL_DEBUG_MAC80211(priv, "enter\n");
2268 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2269
2270 return 0;
2271}
2272
5b9f8cd3 2273static void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 2274{
c79dd5b5 2275 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
2276 unsigned long flags;
2277
2278 mutex_lock(&priv->mutex);
e1623446 2279 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2280
b481de9c 2281 spin_lock_irqsave(&priv->lock, flags);
fd105e79 2282 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info));
b481de9c 2283 spin_unlock_irqrestore(&priv->lock, flags);
b481de9c 2284
c7de35cd 2285 iwl_reset_qos(priv);
b481de9c 2286
b481de9c
ZY
2287 spin_lock_irqsave(&priv->lock, flags);
2288 priv->assoc_id = 0;
2289 priv->assoc_capability = 0;
b481de9c
ZY
2290 priv->assoc_station_added = 0;
2291
2292 /* new association get rid of ibss beacon skb */
2293 if (priv->ibss_beacon)
2294 dev_kfree_skb(priv->ibss_beacon);
2295
2296 priv->ibss_beacon = NULL;
2297
2298 priv->beacon_int = priv->hw->conf.beacon_int;
3109ece1 2299 priv->timestamp = 0;
05c914fe 2300 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
b481de9c
ZY
2301 priv->beacon_int = 0;
2302
2303 spin_unlock_irqrestore(&priv->lock, flags);
2304
fee1247a 2305 if (!iwl_is_ready_rf(priv)) {
e1623446 2306 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
fde3571f
MA
2307 mutex_unlock(&priv->mutex);
2308 return;
2309 }
2310
052c4b9f 2311 /* we are restarting association process
2312 * clear RXON_FILTER_ASSOC_MSK bit
2313 */
05c914fe 2314 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2a421b91 2315 iwl_scan_cancel_timeout(priv, 100);
052c4b9f 2316 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2317 iwlcore_commit_rxon(priv);
052c4b9f 2318 }
2319
5da4b55f
MA
2320 iwl_power_update_mode(priv, 0);
2321
b481de9c 2322 /* Per mac80211.h: This is only used in IBSS mode... */
05c914fe 2323 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
052c4b9f 2324
c90a74ba
EG
2325 /* switch to CAM during association period.
2326 * the ucode will block any association/authentication
2327 * frome during assiciation period if it can not hear
2328 * the AP because of PM. the timer enable PM back is
2329 * association do not complete
2330 */
2331 if (priv->hw->conf.channel->flags & (IEEE80211_CHAN_PASSIVE_SCAN |
2332 IEEE80211_CHAN_RADAR))
2333 iwl_power_disable_management(priv, 3000);
2334
e1623446 2335 IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
b481de9c
ZY
2336 mutex_unlock(&priv->mutex);
2337 return;
2338 }
2339
5b9f8cd3 2340 iwl_set_rate(priv);
b481de9c
ZY
2341
2342 mutex_unlock(&priv->mutex);
2343
e1623446 2344 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2345}
2346
b481de9c 2347
b481de9c
ZY
2348/*****************************************************************************
2349 *
2350 * sysfs attributes
2351 *
2352 *****************************************************************************/
2353
0a6857e7 2354#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2355
2356/*
2357 * The following adds a new attribute to the sysfs representation
c3a739fa 2358 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
2359 * used for controlling the debug level.
2360 *
2361 * See the level definitions in iwl for details.
2362 */
2363
8cf769c6
EK
2364static ssize_t show_debug_level(struct device *d,
2365 struct device_attribute *attr, char *buf)
b481de9c 2366{
8cf769c6
EK
2367 struct iwl_priv *priv = d->driver_data;
2368
2369 return sprintf(buf, "0x%08X\n", priv->debug_level);
b481de9c 2370}
8cf769c6
EK
2371static ssize_t store_debug_level(struct device *d,
2372 struct device_attribute *attr,
b481de9c
ZY
2373 const char *buf, size_t count)
2374{
8cf769c6 2375 struct iwl_priv *priv = d->driver_data;
9257746f
TW
2376 unsigned long val;
2377 int ret;
b481de9c 2378
9257746f
TW
2379 ret = strict_strtoul(buf, 0, &val);
2380 if (ret)
978785a3 2381 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
b481de9c 2382 else
8cf769c6 2383 priv->debug_level = val;
b481de9c
ZY
2384
2385 return strnlen(buf, count);
2386}
2387
8cf769c6
EK
2388static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2389 show_debug_level, store_debug_level);
2390
b481de9c 2391
0a6857e7 2392#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 2393
b481de9c 2394
bc6f59bc
TW
2395static ssize_t show_version(struct device *d,
2396 struct device_attribute *attr, char *buf)
2397{
2398 struct iwl_priv *priv = d->driver_data;
885ba202 2399 struct iwl_alive_resp *palive = &priv->card_alive;
f236a265
TW
2400 ssize_t pos = 0;
2401 u16 eeprom_ver;
bc6f59bc
TW
2402
2403 if (palive->is_valid)
f236a265
TW
2404 pos += sprintf(buf + pos,
2405 "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n"
2406 "fw type: 0x%01X 0x%01X\n",
bc6f59bc
TW
2407 palive->ucode_major, palive->ucode_minor,
2408 palive->sw_rev[0], palive->sw_rev[1],
2409 palive->ver_type, palive->ver_subtype);
bc6f59bc 2410 else
f236a265
TW
2411 pos += sprintf(buf + pos, "fw not loaded\n");
2412
2413 if (priv->eeprom) {
2414 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
2415 pos += sprintf(buf + pos, "EEPROM version: 0x%x\n",
2416 eeprom_ver);
2417 } else {
2418 pos += sprintf(buf + pos, "EEPROM not initialzed\n");
2419 }
2420
2421 return pos;
bc6f59bc
TW
2422}
2423
2424static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL);
2425
b481de9c
ZY
2426static ssize_t show_temperature(struct device *d,
2427 struct device_attribute *attr, char *buf)
2428{
c79dd5b5 2429 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c 2430
fee1247a 2431 if (!iwl_is_alive(priv))
b481de9c
ZY
2432 return -EAGAIN;
2433
91dbc5bd 2434 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
2435}
2436
2437static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2438
b481de9c
ZY
2439static ssize_t show_tx_power(struct device *d,
2440 struct device_attribute *attr, char *buf)
2441{
c79dd5b5 2442 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
91f39e8e
JS
2443
2444 if (!iwl_is_ready_rf(priv))
2445 return sprintf(buf, "off\n");
2446 else
2447 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
2448}
2449
2450static ssize_t store_tx_power(struct device *d,
2451 struct device_attribute *attr,
2452 const char *buf, size_t count)
2453{
c79dd5b5 2454 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
9257746f
TW
2455 unsigned long val;
2456 int ret;
b481de9c 2457
9257746f
TW
2458 ret = strict_strtoul(buf, 10, &val);
2459 if (ret)
978785a3 2460 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
b481de9c 2461 else
630fe9b6 2462 iwl_set_tx_power(priv, val, false);
b481de9c
ZY
2463
2464 return count;
2465}
2466
2467static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2468
2469static ssize_t show_flags(struct device *d,
2470 struct device_attribute *attr, char *buf)
2471{
c79dd5b5 2472 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY
2473
2474 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2475}
2476
2477static ssize_t store_flags(struct device *d,
2478 struct device_attribute *attr,
2479 const char *buf, size_t count)
2480{
c79dd5b5 2481 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
9257746f
TW
2482 unsigned long val;
2483 u32 flags;
2484 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2485 if (ret)
9257746f
TW
2486 return ret;
2487 flags = (u32)val;
b481de9c
ZY
2488
2489 mutex_lock(&priv->mutex);
2490 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2491 /* Cancel any currently running scans... */
2a421b91 2492 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2493 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2494 else {
e1623446 2495 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 2496 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 2497 iwlcore_commit_rxon(priv);
b481de9c
ZY
2498 }
2499 }
2500 mutex_unlock(&priv->mutex);
2501
2502 return count;
2503}
2504
2505static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2506
2507static ssize_t show_filter_flags(struct device *d,
2508 struct device_attribute *attr, char *buf)
2509{
c79dd5b5 2510 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY
2511
2512 return sprintf(buf, "0x%04X\n",
2513 le32_to_cpu(priv->active_rxon.filter_flags));
2514}
2515
2516static ssize_t store_filter_flags(struct device *d,
2517 struct device_attribute *attr,
2518 const char *buf, size_t count)
2519{
c79dd5b5 2520 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
9257746f
TW
2521 unsigned long val;
2522 u32 filter_flags;
2523 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2524 if (ret)
9257746f
TW
2525 return ret;
2526 filter_flags = (u32)val;
b481de9c
ZY
2527
2528 mutex_lock(&priv->mutex);
2529 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2530 /* Cancel any currently running scans... */
2a421b91 2531 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2532 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2533 else {
e1623446 2534 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY
2535 "0x%04X\n", filter_flags);
2536 priv->staging_rxon.filter_flags =
2537 cpu_to_le32(filter_flags);
e0158e61 2538 iwlcore_commit_rxon(priv);
b481de9c
ZY
2539 }
2540 }
2541 mutex_unlock(&priv->mutex);
2542
2543 return count;
2544}
2545
2546static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2547 store_filter_flags);
2548
b481de9c
ZY
2549static ssize_t store_power_level(struct device *d,
2550 struct device_attribute *attr,
2551 const char *buf, size_t count)
2552{
c79dd5b5 2553 struct iwl_priv *priv = dev_get_drvdata(d);
298df1f6 2554 int ret;
9257746f
TW
2555 unsigned long mode;
2556
b481de9c 2557
b481de9c
ZY
2558 mutex_lock(&priv->mutex);
2559
9257746f 2560 ret = strict_strtoul(buf, 10, &mode);
926f0b2e 2561 if (ret)
9257746f
TW
2562 goto out;
2563
298df1f6
EK
2564 ret = iwl_power_set_user_mode(priv, mode);
2565 if (ret) {
e1623446 2566 IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
5da4b55f 2567 goto out;
b481de9c 2568 }
298df1f6 2569 ret = count;
b481de9c
ZY
2570
2571 out:
2572 mutex_unlock(&priv->mutex);
298df1f6 2573 return ret;
b481de9c
ZY
2574}
2575
b481de9c
ZY
2576static ssize_t show_power_level(struct device *d,
2577 struct device_attribute *attr, char *buf)
2578{
c79dd5b5 2579 struct iwl_priv *priv = dev_get_drvdata(d);
298df1f6
EK
2580 int mode = priv->power_data.user_power_setting;
2581 int system = priv->power_data.system_power_setting;
5da4b55f 2582 int level = priv->power_data.power_mode;
b481de9c
ZY
2583 char *p = buf;
2584
298df1f6
EK
2585 switch (system) {
2586 case IWL_POWER_SYS_AUTO:
2587 p += sprintf(p, "SYSTEM:auto");
b481de9c 2588 break;
298df1f6
EK
2589 case IWL_POWER_SYS_AC:
2590 p += sprintf(p, "SYSTEM:ac");
2591 break;
2592 case IWL_POWER_SYS_BATTERY:
2593 p += sprintf(p, "SYSTEM:battery");
b481de9c 2594 break;
b481de9c 2595 }
298df1f6 2596
c3056065
AK
2597 p += sprintf(p, "\tMODE:%s", (mode < IWL_POWER_AUTO) ?
2598 "fixed" : "auto");
298df1f6
EK
2599 p += sprintf(p, "\tINDEX:%d", level);
2600 p += sprintf(p, "\n");
3ac7f146 2601 return p - buf + 1;
b481de9c
ZY
2602}
2603
2604static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
2605 store_power_level);
2606
b481de9c
ZY
2607
2608static ssize_t show_statistics(struct device *d,
2609 struct device_attribute *attr, char *buf)
2610{
c79dd5b5 2611 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 2612 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 2613 u32 len = 0, ofs = 0;
3ac7f146 2614 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
2615 int rc = 0;
2616
fee1247a 2617 if (!iwl_is_alive(priv))
b481de9c
ZY
2618 return -EAGAIN;
2619
2620 mutex_lock(&priv->mutex);
49ea8596 2621 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
2622 mutex_unlock(&priv->mutex);
2623
2624 if (rc) {
2625 len = sprintf(buf,
2626 "Error sending statistics request: 0x%08X\n", rc);
2627 return len;
2628 }
2629
2630 while (size && (PAGE_SIZE - len)) {
2631 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2632 PAGE_SIZE - len, 1);
2633 len = strlen(buf);
2634 if (PAGE_SIZE - len)
2635 buf[len++] = '\n';
2636
2637 ofs += 16;
2638 size -= min(size, 16U);
2639 }
2640
2641 return len;
2642}
2643
2644static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
2645
b481de9c 2646
b481de9c
ZY
2647/*****************************************************************************
2648 *
2649 * driver setup and teardown
2650 *
2651 *****************************************************************************/
2652
4e39317d 2653static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2654{
d21050c7 2655 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
2656
2657 init_waitqueue_head(&priv->wait_command_queue);
2658
5b9f8cd3
EG
2659 INIT_WORK(&priv->up, iwl_bg_up);
2660 INIT_WORK(&priv->restart, iwl_bg_restart);
2661 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
2662 INIT_WORK(&priv->rf_kill, iwl_bg_rf_kill);
2663 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 2664 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
2665 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
2666 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 2667
2a421b91 2668 iwl_setup_scan_deferred_work(priv);
c90a74ba 2669 iwl_setup_power_deferred_work(priv);
bb8c093b 2670
4e39317d
EG
2671 if (priv->cfg->ops->lib->setup_deferred_work)
2672 priv->cfg->ops->lib->setup_deferred_work(priv);
2673
2674 init_timer(&priv->statistics_periodic);
2675 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 2676 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c
ZY
2677
2678 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
5b9f8cd3 2679 iwl_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
2680}
2681
4e39317d 2682static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2683{
4e39317d
EG
2684 if (priv->cfg->ops->lib->cancel_deferred_work)
2685 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 2686
3ae6a054 2687 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 2688 cancel_delayed_work(&priv->scan_check);
c90a74ba 2689 cancel_delayed_work_sync(&priv->set_power_save);
b481de9c 2690 cancel_delayed_work(&priv->alive_start);
b481de9c 2691 cancel_work_sync(&priv->beacon_update);
4e39317d 2692 del_timer_sync(&priv->statistics_periodic);
b481de9c
ZY
2693}
2694
5b9f8cd3 2695static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY
2696 &dev_attr_flags.attr,
2697 &dev_attr_filter_flags.attr,
b481de9c 2698 &dev_attr_power_level.attr,
b481de9c 2699 &dev_attr_statistics.attr,
b481de9c 2700 &dev_attr_temperature.attr,
b481de9c 2701 &dev_attr_tx_power.attr,
8cf769c6
EK
2702#ifdef CONFIG_IWLWIFI_DEBUG
2703 &dev_attr_debug_level.attr,
2704#endif
bc6f59bc 2705 &dev_attr_version.attr,
b481de9c
ZY
2706
2707 NULL
2708};
2709
5b9f8cd3 2710static struct attribute_group iwl_attribute_group = {
b481de9c 2711 .name = NULL, /* put in device directory */
5b9f8cd3 2712 .attrs = iwl_sysfs_entries,
b481de9c
ZY
2713};
2714
5b9f8cd3
EG
2715static struct ieee80211_ops iwl_hw_ops = {
2716 .tx = iwl_mac_tx,
2717 .start = iwl_mac_start,
2718 .stop = iwl_mac_stop,
2719 .add_interface = iwl_mac_add_interface,
2720 .remove_interface = iwl_mac_remove_interface,
2721 .config = iwl_mac_config,
2722 .config_interface = iwl_mac_config_interface,
2723 .configure_filter = iwl_configure_filter,
2724 .set_key = iwl_mac_set_key,
2725 .update_tkip_key = iwl_mac_update_tkip_key,
2726 .get_stats = iwl_mac_get_stats,
2727 .get_tx_stats = iwl_mac_get_tx_stats,
2728 .conf_tx = iwl_mac_conf_tx,
2729 .reset_tsf = iwl_mac_reset_tsf,
2730 .bss_info_changed = iwl_bss_info_changed,
2731 .ampdu_action = iwl_mac_ampdu_action,
cb43dc25 2732 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
2733};
2734
5b9f8cd3 2735static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
2736{
2737 int err = 0;
c79dd5b5 2738 struct iwl_priv *priv;
b481de9c 2739 struct ieee80211_hw *hw;
82b9a121 2740 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 2741 unsigned long flags;
6cd0b1cb 2742 u16 pci_cmd;
b481de9c 2743
316c30d9
AK
2744 /************************
2745 * 1. Allocating HW data
2746 ************************/
2747
6440adb5
CB
2748 /* Disabling hardware scan means that mac80211 will perform scans
2749 * "the hard way", rather than using device's scan. */
1ea87396 2750 if (cfg->mod_params->disable_hw_scan) {
bf403db8
EK
2751 if (cfg->mod_params->debug & IWL_DL_INFO)
2752 dev_printk(KERN_DEBUG, &(pdev->dev),
2753 "Disabling hw_scan\n");
5b9f8cd3 2754 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
2755 }
2756
5b9f8cd3 2757 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 2758 if (!hw) {
b481de9c
ZY
2759 err = -ENOMEM;
2760 goto out;
2761 }
1d0a082d
AK
2762 priv = hw->priv;
2763 /* At this point both hw and priv are allocated. */
2764
b481de9c
ZY
2765 SET_IEEE80211_DEV(hw, &pdev->dev);
2766
e1623446 2767 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 2768 priv->cfg = cfg;
b481de9c 2769 priv->pci_dev = pdev;
316c30d9 2770
0a6857e7 2771#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 2772 priv->debug_level = priv->cfg->mod_params->debug;
b481de9c
ZY
2773 atomic_set(&priv->restrict_refcnt, 0);
2774#endif
b481de9c 2775
316c30d9
AK
2776 /**************************
2777 * 2. Initializing PCI bus
2778 **************************/
2779 if (pci_enable_device(pdev)) {
2780 err = -ENODEV;
2781 goto out_ieee80211_free_hw;
2782 }
2783
2784 pci_set_master(pdev);
2785
093d874c 2786 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 2787 if (!err)
093d874c 2788 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 2789 if (err) {
093d874c 2790 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 2791 if (!err)
093d874c 2792 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 2793 /* both attempts failed: */
316c30d9 2794 if (err) {
978785a3 2795 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 2796 goto out_pci_disable_device;
cc2a8ea8 2797 }
316c30d9
AK
2798 }
2799
2800 err = pci_request_regions(pdev, DRV_NAME);
2801 if (err)
2802 goto out_pci_disable_device;
2803
2804 pci_set_drvdata(pdev, priv);
2805
316c30d9
AK
2806
2807 /***********************
2808 * 3. Read REV register
2809 ***********************/
2810 priv->hw_base = pci_iomap(pdev, 0, 0);
2811 if (!priv->hw_base) {
2812 err = -ENODEV;
2813 goto out_pci_release_regions;
2814 }
2815
e1623446 2816 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 2817 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 2818 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 2819
b661c819 2820 iwl_hw_detect(priv);
978785a3 2821 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 2822 priv->cfg->name, priv->hw_rev);
316c30d9 2823
e7b63581
TW
2824 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2825 * PCI Tx retries from interfering with C3 CPU state */
2826 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2827
91238714
TW
2828 /* amp init */
2829 err = priv->cfg->ops->lib->apm_ops.init(priv);
316c30d9 2830 if (err < 0) {
808ff697 2831 IWL_ERR(priv, "Failed to init APMG\n");
316c30d9
AK
2832 goto out_iounmap;
2833 }
91238714
TW
2834 /*****************
2835 * 4. Read EEPROM
2836 *****************/
316c30d9
AK
2837 /* Read the EEPROM */
2838 err = iwl_eeprom_init(priv);
2839 if (err) {
15b1687c 2840 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
2841 goto out_iounmap;
2842 }
8614f360
TW
2843 err = iwl_eeprom_check_version(priv);
2844 if (err)
c8f16138 2845 goto out_free_eeprom;
8614f360 2846
02883017 2847 /* extract MAC Address */
316c30d9 2848 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 2849 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
2850 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
2851
2852 /************************
2853 * 5. Setup HW constants
2854 ************************/
da154e30 2855 if (iwl_set_hw_params(priv)) {
15b1687c 2856 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 2857 goto out_free_eeprom;
316c30d9
AK
2858 }
2859
2860 /*******************
6ba87956 2861 * 6. Setup priv
316c30d9 2862 *******************/
b481de9c 2863
6ba87956 2864 err = iwl_init_drv(priv);
bf85ea4f 2865 if (err)
399f4900 2866 goto out_free_eeprom;
bf85ea4f 2867 /* At this point both hw and priv are initialized. */
316c30d9
AK
2868
2869 /**********************************
2870 * 7. Initialize module parameters
2871 **********************************/
2872
2873 /* Disable radio (SW RF KILL) via parameter when loading driver */
1ea87396 2874 if (priv->cfg->mod_params->disable) {
316c30d9 2875 set_bit(STATUS_RF_KILL_SW, &priv->status);
e1623446 2876 IWL_DEBUG_INFO(priv, "Radio disabled.\n");
316c30d9
AK
2877 }
2878
316c30d9
AK
2879 /********************
2880 * 8. Setup services
2881 ********************/
0359facc 2882 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2883 iwl_disable_interrupts(priv);
0359facc 2884 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 2885
6cd0b1cb
HS
2886 pci_enable_msi(priv->pci_dev);
2887
2888 err = request_irq(priv->pci_dev->irq, iwl_isr, IRQF_SHARED,
2889 DRV_NAME, priv);
2890 if (err) {
2891 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
2892 goto out_disable_msi;
2893 }
5b9f8cd3 2894 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 2895 if (err) {
15b1687c 2896 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 2897 goto out_free_irq;
316c30d9
AK
2898 }
2899
4e39317d 2900 iwl_setup_deferred_work(priv);
653fa4a0 2901 iwl_setup_rx_handlers(priv);
316c30d9 2902
6ba87956 2903 /**********************************
6cd0b1cb 2904 * 9. Setup and register mac80211
6ba87956
TW
2905 **********************************/
2906
6cd0b1cb
HS
2907 /* enable interrupts if needed: hw bug w/a */
2908 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
2909 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2910 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2911 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
2912 }
2913
2914 iwl_enable_interrupts(priv);
2915
6ba87956
TW
2916 err = iwl_setup_mac(priv);
2917 if (err)
2918 goto out_remove_sysfs;
2919
2920 err = iwl_dbgfs_register(priv, DRV_NAME);
2921 if (err)
15b1687c 2922 IWL_ERR(priv, "failed to create debugfs files\n");
6ba87956 2923
6cd0b1cb
HS
2924 /* If platform's RF_KILL switch is NOT set to KILL */
2925 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2926 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2927 else
2928 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 2929
58d0f361
EG
2930 err = iwl_rfkill_init(priv);
2931 if (err)
15b1687c 2932 IWL_ERR(priv, "Unable to initialize RFKILL system. "
58d0f361 2933 "Ignoring error: %d\n", err);
6cd0b1cb
HS
2934 else
2935 iwl_rfkill_set_hw_state(priv);
2936
58d0f361 2937 iwl_power_initialize(priv);
b481de9c
ZY
2938 return 0;
2939
316c30d9 2940 out_remove_sysfs:
c8f16138
RC
2941 destroy_workqueue(priv->workqueue);
2942 priv->workqueue = NULL;
5b9f8cd3 2943 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
2944 out_free_irq:
2945 free_irq(priv->pci_dev->irq, priv);
6cd0b1cb
HS
2946 out_disable_msi:
2947 pci_disable_msi(priv->pci_dev);
6ba87956 2948 iwl_uninit_drv(priv);
073d3f5f
TW
2949 out_free_eeprom:
2950 iwl_eeprom_free(priv);
b481de9c
ZY
2951 out_iounmap:
2952 pci_iounmap(pdev, priv->hw_base);
2953 out_pci_release_regions:
316c30d9 2954 pci_set_drvdata(pdev, NULL);
623d563e 2955 pci_release_regions(pdev);
b481de9c
ZY
2956 out_pci_disable_device:
2957 pci_disable_device(pdev);
b481de9c
ZY
2958 out_ieee80211_free_hw:
2959 ieee80211_free_hw(priv->hw);
2960 out:
2961 return err;
2962}
2963
5b9f8cd3 2964static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 2965{
c79dd5b5 2966 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 2967 unsigned long flags;
b481de9c
ZY
2968
2969 if (!priv)
2970 return;
2971
e1623446 2972 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 2973
67249625 2974 iwl_dbgfs_unregister(priv);
5b9f8cd3 2975 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 2976
5b9f8cd3
EG
2977 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
2978 * to be called and iwl_down since we are removing the device
0b124c31
GG
2979 * we need to set STATUS_EXIT_PENDING bit.
2980 */
2981 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
2982 if (priv->mac80211_registered) {
2983 ieee80211_unregister_hw(priv->hw);
2984 priv->mac80211_registered = 0;
0b124c31 2985 } else {
5b9f8cd3 2986 iwl_down(priv);
c4f55232
RR
2987 }
2988
0359facc
MA
2989 /* make sure we flush any pending irq or
2990 * tasklet for the driver
2991 */
2992 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2993 iwl_disable_interrupts(priv);
0359facc
MA
2994 spin_unlock_irqrestore(&priv->lock, flags);
2995
2996 iwl_synchronize_irq(priv);
2997
58d0f361 2998 iwl_rfkill_unregister(priv);
5b9f8cd3 2999 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3000
3001 if (priv->rxq.bd)
a55360e4 3002 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3003 iwl_hw_txq_ctx_free(priv);
b481de9c 3004
e11bc028 3005 priv->cfg->ops->smgmt->clear_station_table(priv);
073d3f5f 3006 iwl_eeprom_free(priv);
b481de9c 3007
b481de9c 3008
948c171c
MA
3009 /*netif_stop_queue(dev); */
3010 flush_workqueue(priv->workqueue);
3011
5b9f8cd3 3012 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3013 * priv->workqueue... so we can't take down the workqueue
3014 * until now... */
3015 destroy_workqueue(priv->workqueue);
3016 priv->workqueue = NULL;
3017
6cd0b1cb
HS
3018 free_irq(priv->pci_dev->irq, priv);
3019 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3020 pci_iounmap(pdev, priv->hw_base);
3021 pci_release_regions(pdev);
3022 pci_disable_device(pdev);
3023 pci_set_drvdata(pdev, NULL);
3024
6ba87956 3025 iwl_uninit_drv(priv);
b481de9c
ZY
3026
3027 if (priv->ibss_beacon)
3028 dev_kfree_skb(priv->ibss_beacon);
3029
3030 ieee80211_free_hw(priv->hw);
3031}
3032
b481de9c
ZY
3033
3034/*****************************************************************************
3035 *
3036 * driver and module entry point
3037 *
3038 *****************************************************************************/
3039
fed9017e
RR
3040/* Hardware specific file defines the PCI IDs table for that hardware module */
3041static struct pci_device_id iwl_hw_card_ids[] = {
4fc22b21 3042#ifdef CONFIG_IWL4965
fed9017e
RR
3043 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3044 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3045#endif /* CONFIG_IWL4965 */
5a6a256e 3046#ifdef CONFIG_IWL5000
47408639
EK
3047 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3048 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3049 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3050 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3051 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3052 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
5a6a256e 3053 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
47408639
EK
3054 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3055 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3056 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
e96a8495
TW
3057/* 5350 WiFi/WiMax */
3058 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3059 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3060 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
7100e924
TW
3061/* 5150 Wifi/WiMax */
3062 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3063 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
e1228374
JS
3064/* 6000/6050 Series */
3065 {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)},
3066 {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)},
3067 {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)},
3068 {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
3069 {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
3070 {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)},
3071 {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)},
3072 {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
3073 {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
3074 {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
3075 {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
77dcb6a9
JS
3076/* 1000 Series WiFi */
3077 {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
3078 {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
5a6a256e 3079#endif /* CONFIG_IWL5000 */
7100e924 3080
fed9017e
RR
3081 {0}
3082};
3083MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3084
3085static struct pci_driver iwl_driver = {
b481de9c 3086 .name = DRV_NAME,
fed9017e 3087 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3088 .probe = iwl_pci_probe,
3089 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3090#ifdef CONFIG_PM
5b9f8cd3
EG
3091 .suspend = iwl_pci_suspend,
3092 .resume = iwl_pci_resume,
b481de9c
ZY
3093#endif
3094};
3095
5b9f8cd3 3096static int __init iwl_init(void)
b481de9c
ZY
3097{
3098
3099 int ret;
3100 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3101 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3102
e227ceac 3103 ret = iwlagn_rate_control_register();
897e1cf2 3104 if (ret) {
a3139c59
SO
3105 printk(KERN_ERR DRV_NAME
3106 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3107 return ret;
3108 }
3109
fed9017e 3110 ret = pci_register_driver(&iwl_driver);
b481de9c 3111 if (ret) {
a3139c59 3112 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3113 goto error_register;
b481de9c 3114 }
b481de9c
ZY
3115
3116 return ret;
897e1cf2 3117
897e1cf2 3118error_register:
e227ceac 3119 iwlagn_rate_control_unregister();
897e1cf2 3120 return ret;
b481de9c
ZY
3121}
3122
5b9f8cd3 3123static void __exit iwl_exit(void)
b481de9c 3124{
fed9017e 3125 pci_unregister_driver(&iwl_driver);
e227ceac 3126 iwlagn_rate_control_unregister();
b481de9c
ZY
3127}
3128
5b9f8cd3
EG
3129module_exit(iwl_exit);
3130module_init(iwl_init);
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