iwlagn: invoke L0S workaround for 6000/1000 series
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
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43#include <net/mac80211.h>
44
45#include <asm/div64.h>
46
a3139c59
SO
47#define DRV_NAME "iwlagn"
48
6bc913bd 49#include "iwl-eeprom.h"
3e0d4cb1 50#include "iwl-dev.h"
fee1247a 51#include "iwl-core.h"
3395f6e9 52#include "iwl-io.h"
b481de9c 53#include "iwl-helpers.h"
6974e363 54#include "iwl-sta.h"
f0832f13 55#include "iwl-calib.h"
b481de9c 56
416e1438 57
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58/******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
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64/*
65 * module name, copyright, version, etc.
b481de9c 66 */
d783b061 67#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 68
0a6857e7 69#ifdef CONFIG_IWLWIFI_DEBUG
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70#define VD "d"
71#else
72#define VD
73#endif
74
80bc5393 75#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
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76#define VS "s"
77#else
78#define VS
79#endif
80
df48c323 81#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 82
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83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
b481de9c 90/*************** STATION TABLE MANAGEMENT ****
9fbab516 91 * mac80211 should be examined to determine if sta_info is duplicating
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92 * the functionality provided here
93 */
94
95/**************************************************************/
96
b481de9c 97/**
5b9f8cd3 98 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 99 *
01ebd063 100 * The RXON command in staging_rxon is committed to the hardware and
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101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
e0158e61 105int iwl_commit_rxon(struct iwl_priv *priv)
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106{
107 /* cast away the const for active_rxon in this function */
c1adf9fb 108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 112
fee1247a 113 if (!iwl_is_alive(priv))
43d59b32 114 return -EBUSY;
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115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
118
8ccde88a 119 ret = iwl_check_rxon_cmd(priv);
43d59b32 120 if (ret) {
15b1687c 121 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
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122 return -EINVAL;
123 }
124
125 /* If we don't need to send a full RXON, we can use
5b9f8cd3 126 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 127 * and other flags for the current radio configuration. */
54559703 128 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
129 ret = iwl_send_rxon_assoc(priv);
130 if (ret) {
15b1687c 131 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 132 return ret;
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133 }
134
135 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
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136 return 0;
137 }
138
139 /* station table will be cleared */
140 priv->assoc_station_added = 0;
141
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142 /* If we are currently associated and the new config requires
143 * an RXON_ASSOC and the new config wants the associated mask enabled,
144 * we must clear the associated from the active configuration
145 * before we apply the new config */
43d59b32 146 if (iwl_is_associated(priv) && new_assoc) {
e1623446 147 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
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148 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
149
43d59b32 150 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 151 sizeof(struct iwl_rxon_cmd),
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152 &priv->active_rxon);
153
154 /* If the mask clearing failed then we set
155 * active_rxon back to what it was previously */
43d59b32 156 if (ret) {
b481de9c 157 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 158 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 159 return ret;
b481de9c 160 }
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161 }
162
e1623446 163 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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164 "* with%s RXON_FILTER_ASSOC_MSK\n"
165 "* channel = %d\n"
e174961c 166 "* bssid = %pM\n",
43d59b32 167 (new_assoc ? "" : "out"),
b481de9c 168 le16_to_cpu(priv->staging_rxon.channel),
e174961c 169 priv->staging_rxon.bssid_addr);
b481de9c 170
90e8e424 171 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG
172
173 /* Apply the new configuration
174 * RXON unassoc clears the station table in uCode, send it before
175 * we add the bcast station. If assoc bit is set, we will send RXON
176 * after having added the bcast and bssid station.
177 */
178 if (!new_assoc) {
179 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 180 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 181 if (ret) {
15b1687c 182 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
183 return ret;
184 }
185 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
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186 }
187
c587de0b 188 iwl_clear_stations_table(priv);
556f8db7 189
19cc1087 190 priv->start_calib = 0;
b481de9c 191
b481de9c 192 /* Add the broadcast address so we can send broadcast frames */
4f40e4d9 193 if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
43d59b32 194 IWL_INVALID_STATION) {
15b1687c 195 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
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196 return -EIO;
197 }
198
199 /* If we have set the ASSOC_MSK and we are in BSS mode then
200 * add the IWL_AP_ID to the station rate table */
9185159d 201 if (new_assoc) {
05c914fe 202 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW
203 ret = iwl_rxon_add_station(priv,
204 priv->active_rxon.bssid_addr, 1);
205 if (ret == IWL_INVALID_STATION) {
15b1687c
WT
206 IWL_ERR(priv,
207 "Error adding AP address for TX.\n");
9185159d
TW
208 return -EIO;
209 }
210 priv->assoc_station_added = 1;
211 if (priv->default_wep_key &&
212 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT
213 IWL_ERR(priv,
214 "Could not send WEP static key.\n");
b481de9c 215 }
43d59b32 216
47eef9bd
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217 /*
218 * allow CTS-to-self if possible for new association.
219 * this is relevant only for 5000 series and up,
220 * but will not damage 4965
221 */
222 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
223
43d59b32
EG
224 /* Apply the new configuration
225 * RXON assoc doesn't clear the station table in uCode,
226 */
227 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
228 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
229 if (ret) {
15b1687c 230 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
231 return ret;
232 }
233 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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234 }
235
36da7d70
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236 iwl_init_sensitivity(priv);
237
238 /* If we issue a new RXON command which required a tune then we must
239 * send a new TXPOWER command or we won't be able to Tx any frames */
240 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
241 if (ret) {
15b1687c 242 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
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243 return ret;
244 }
245
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246 return 0;
247}
248
5b9f8cd3 249void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
250{
251
45823531
AK
252 if (priv->cfg->ops->hcmd->set_rxon_chain)
253 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 254 iwlcore_commit_rxon(priv);
5da4b55f
MA
255}
256
fcab423d 257static void iwl_clear_free_frames(struct iwl_priv *priv)
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258{
259 struct list_head *element;
260
e1623446 261 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
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262 priv->frames_count);
263
264 while (!list_empty(&priv->free_frames)) {
265 element = priv->free_frames.next;
266 list_del(element);
fcab423d 267 kfree(list_entry(element, struct iwl_frame, list));
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268 priv->frames_count--;
269 }
270
271 if (priv->frames_count) {
39aadf8c 272 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
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273 priv->frames_count);
274 priv->frames_count = 0;
275 }
276}
277
fcab423d 278static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 279{
fcab423d 280 struct iwl_frame *frame;
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281 struct list_head *element;
282 if (list_empty(&priv->free_frames)) {
283 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
284 if (!frame) {
15b1687c 285 IWL_ERR(priv, "Could not allocate frame!\n");
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286 return NULL;
287 }
288
289 priv->frames_count++;
290 return frame;
291 }
292
293 element = priv->free_frames.next;
294 list_del(element);
fcab423d 295 return list_entry(element, struct iwl_frame, list);
b481de9c
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296}
297
fcab423d 298static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
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299{
300 memset(frame, 0, sizeof(*frame));
301 list_add(&frame->list, &priv->free_frames);
302}
303
4bf64efd
TW
304static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
305 struct ieee80211_hdr *hdr,
73ec1cc2 306 int left)
b481de9c 307{
3109ece1 308 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
309 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
310 (priv->iw_mode != NL80211_IFTYPE_AP)))
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311 return 0;
312
313 if (priv->ibss_beacon->len > left)
314 return 0;
315
316 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
317
318 return priv->ibss_beacon->len;
319}
320
5b9f8cd3 321static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
4bf64efd
TW
322 struct iwl_frame *frame, u8 rate)
323{
324 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
325 unsigned int frame_size;
326
327 tx_beacon_cmd = &frame->u.beacon;
328 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
329
330 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
331 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
332
333 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd
TW
334 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
335
336 BUG_ON(frame_size > MAX_MPDU_SIZE);
337 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
338
339 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
340 tx_beacon_cmd->tx.rate_n_flags =
341 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
342 else
343 tx_beacon_cmd->tx.rate_n_flags =
344 iwl_hw_set_rate_n_flags(rate, 0);
345
346 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
347 TX_CMD_FLG_TSF_MSK |
348 TX_CMD_FLG_STA_RATE_MSK;
349
350 return sizeof(*tx_beacon_cmd) + frame_size;
351}
5b9f8cd3 352static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 353{
fcab423d 354 struct iwl_frame *frame;
b481de9c
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355 unsigned int frame_size;
356 int rc;
357 u8 rate;
358
fcab423d 359 frame = iwl_get_free_frame(priv);
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360
361 if (!frame) {
15b1687c 362 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
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363 "command.\n");
364 return -ENOMEM;
365 }
366
5b9f8cd3 367 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 368
5b9f8cd3 369 frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 370
857485c0 371 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
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372 &frame->u.cmd[0]);
373
fcab423d 374 iwl_free_frame(priv, frame);
b481de9c
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375
376 return rc;
377}
378
7aaa1d79
SO
379static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
380{
381 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
382
383 dma_addr_t addr = get_unaligned_le32(&tb->lo);
384 if (sizeof(dma_addr_t) > sizeof(u32))
385 addr |=
386 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
387
388 return addr;
389}
390
391static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
392{
393 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
394
395 return le16_to_cpu(tb->hi_n_len) >> 4;
396}
397
398static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
399 dma_addr_t addr, u16 len)
400{
401 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
402 u16 hi_n_len = len << 4;
403
404 put_unaligned_le32(addr, &tb->lo);
405 if (sizeof(dma_addr_t) > sizeof(u32))
406 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
407
408 tb->hi_n_len = cpu_to_le16(hi_n_len);
409
410 tfd->num_tbs = idx + 1;
411}
412
413static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
414{
415 return tfd->num_tbs & 0x1f;
416}
417
418/**
419 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
420 * @priv - driver private data
421 * @txq - tx queue
422 *
423 * Does NOT advance any TFD circular buffer read/write indexes
424 * Does NOT free the TFD itself (which is within circular buffer)
425 */
426void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
427{
59606ffa 428 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
429 struct iwl_tfd *tfd;
430 struct pci_dev *dev = priv->pci_dev;
431 int index = txq->q.read_ptr;
432 int i;
433 int num_tbs;
434
435 tfd = &tfd_tmp[index];
436
437 /* Sanity check on number of chunks */
438 num_tbs = iwl_tfd_get_num_tbs(tfd);
439
440 if (num_tbs >= IWL_NUM_OF_TBS) {
441 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
442 /* @todo issue fatal error, it is quite serious situation */
443 return;
444 }
445
446 /* Unmap tx_cmd */
447 if (num_tbs)
448 pci_unmap_single(dev,
c2acea8e
JB
449 pci_unmap_addr(&txq->meta[index], mapping),
450 pci_unmap_len(&txq->meta[index], len),
96891cee 451 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
452
453 /* Unmap chunks, if any. */
454 for (i = 1; i < num_tbs; i++) {
455 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
456 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
457
458 if (txq->txb) {
459 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
460 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
461 }
462 }
463}
464
465int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
466 struct iwl_tx_queue *txq,
467 dma_addr_t addr, u16 len,
468 u8 reset, u8 pad)
469{
470 struct iwl_queue *q;
59606ffa 471 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
472 u32 num_tbs;
473
474 q = &txq->q;
59606ffa
SO
475 tfd_tmp = (struct iwl_tfd *)txq->tfds;
476 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
477
478 if (reset)
479 memset(tfd, 0, sizeof(*tfd));
480
481 num_tbs = iwl_tfd_get_num_tbs(tfd);
482
483 /* Each TFD can point to a maximum 20 Tx buffers */
484 if (num_tbs >= IWL_NUM_OF_TBS) {
485 IWL_ERR(priv, "Error can not send more than %d chunks\n",
486 IWL_NUM_OF_TBS);
487 return -EINVAL;
488 }
489
490 BUG_ON(addr & ~DMA_BIT_MASK(36));
491 if (unlikely(addr & ~IWL_TX_DMA_MASK))
492 IWL_ERR(priv, "Unaligned address = %llx\n",
493 (unsigned long long)addr);
494
495 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
496
497 return 0;
498}
499
a8e74e27
SO
500/*
501 * Tell nic where to find circular buffer of Tx Frame Descriptors for
502 * given Tx queue, and enable the DMA channel used for that queue.
503 *
504 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
505 * channels supported in hardware.
506 */
507int iwl_hw_tx_queue_init(struct iwl_priv *priv,
508 struct iwl_tx_queue *txq)
509{
a8e74e27
SO
510 int txq_id = txq->q.id;
511
a8e74e27
SO
512 /* Circular buffer (TFD queue in DRAM) physical base address */
513 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
514 txq->q.dma_addr >> 8);
515
a8e74e27
SO
516 return 0;
517}
518
b481de9c
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519/******************************************************************************
520 *
521 * Generic RX handler implementations
522 *
523 ******************************************************************************/
885ba202
TW
524static void iwl_rx_reply_alive(struct iwl_priv *priv,
525 struct iwl_rx_mem_buffer *rxb)
b481de9c 526{
2f301227 527 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 528 struct iwl_alive_resp *palive;
b481de9c
ZY
529 struct delayed_work *pwork;
530
531 palive = &pkt->u.alive_frame;
532
e1623446 533 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
534 "0x%01X 0x%01X\n",
535 palive->is_valid, palive->ver_type,
536 palive->ver_subtype);
537
538 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 539 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
540 memcpy(&priv->card_alive_init,
541 &pkt->u.alive_frame,
885ba202 542 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
543 pwork = &priv->init_alive_start;
544 } else {
e1623446 545 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 546 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 547 sizeof(struct iwl_alive_resp));
b481de9c
ZY
548 pwork = &priv->alive_start;
549 }
550
551 /* We delay the ALIVE response by 5ms to
552 * give the HW RF Kill time to activate... */
553 if (palive->is_valid == UCODE_VALID_OK)
554 queue_delayed_work(priv->workqueue, pwork,
555 msecs_to_jiffies(5));
556 else
39aadf8c 557 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
558}
559
5b9f8cd3 560static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 561{
c79dd5b5
TW
562 struct iwl_priv *priv =
563 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
564 struct sk_buff *beacon;
565
566 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 567 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
568
569 if (!beacon) {
15b1687c 570 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
571 return;
572 }
573
574 mutex_lock(&priv->mutex);
575 /* new beacon skb is allocated every time; dispose previous.*/
576 if (priv->ibss_beacon)
577 dev_kfree_skb(priv->ibss_beacon);
578
579 priv->ibss_beacon = beacon;
580 mutex_unlock(&priv->mutex);
581
5b9f8cd3 582 iwl_send_beacon_cmd(priv);
b481de9c
ZY
583}
584
4e39317d 585/**
5b9f8cd3 586 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
587 *
588 * This callback is provided in order to send a statistics request.
589 *
590 * This timer function is continually reset to execute within
591 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
592 * was received. We need to ensure we receive the statistics in order
593 * to update the temperature used for calibrating the TXPOWER.
594 */
5b9f8cd3 595static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
596{
597 struct iwl_priv *priv = (struct iwl_priv *)data;
598
599 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
600 return;
601
61780ee3
MA
602 /* dont send host command if rf-kill is on */
603 if (!iwl_is_ready_rf(priv))
604 return;
605
4e39317d
EG
606 iwl_send_statistics_request(priv, CMD_ASYNC);
607}
608
5b9f8cd3 609static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 610 struct iwl_rx_mem_buffer *rxb)
b481de9c 611{
0a6857e7 612#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 613 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW
614 struct iwl4965_beacon_notif *beacon =
615 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 616 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 617
e1623446 618 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 619 "tsf %d %d rate %d\n",
25a6572c 620 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
621 beacon->beacon_notify_hdr.failure_frame,
622 le32_to_cpu(beacon->ibss_mgr_status),
623 le32_to_cpu(beacon->high_tsf),
624 le32_to_cpu(beacon->low_tsf), rate);
625#endif
626
05c914fe 627 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
628 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
629 queue_work(priv->workqueue, &priv->beacon_update);
630}
631
b481de9c
ZY
632/* Handle notification from uCode that card's power state is changing
633 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 634static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 635 struct iwl_rx_mem_buffer *rxb)
b481de9c 636{
2f301227 637 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
638 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
639 unsigned long status = priv->status;
640
e1623446 641 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
642 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
643 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
644
645 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
646 RF_CARD_DISABLED)) {
647
3395f6e9 648 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
649 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
650
a8b50a0a
MA
651 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
652 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
653
654 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 655 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 656 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 657 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 658 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 659 }
39b73fb1
WYG
660 if (flags & RF_CARD_DISABLED)
661 iwl_tt_enter_ct_kill(priv);
b481de9c 662 }
39b73fb1
WYG
663 if (!(flags & RF_CARD_DISABLED))
664 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY
665
666 if (flags & HW_CARD_DISABLED)
667 set_bit(STATUS_RF_KILL_HW, &priv->status);
668 else
669 clear_bit(STATUS_RF_KILL_HW, &priv->status);
670
671
b481de9c 672 if (!(flags & RXON_CARD_DISABLED))
2a421b91 673 iwl_scan_cancel(priv);
b481de9c
ZY
674
675 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
676 test_bit(STATUS_RF_KILL_HW, &priv->status)))
677 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
678 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
679 else
680 wake_up_interruptible(&priv->wait_command_queue);
681}
682
5b9f8cd3 683int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 684{
e2e3c57b 685 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 686 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
687 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
688 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
689 ~APMG_PS_CTRL_MSK_PWR_SRC);
690 } else {
691 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
692 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
693 ~APMG_PS_CTRL_MSK_PWR_SRC);
694 }
695
a8b50a0a 696 return 0;
e2e3c57b
TW
697}
698
b481de9c 699/**
5b9f8cd3 700 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
701 *
702 * Setup the RX handlers for each of the reply types sent from the uCode
703 * to the host.
704 *
705 * This function chains into the hardware specific files for them to setup
706 * any hardware specific handlers as well.
707 */
653fa4a0 708static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 709{
885ba202 710 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
711 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
712 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
5b9f8cd3 713 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 714 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
715 iwl_rx_pm_debug_statistics_notif;
716 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 717
9fbab516
BC
718 /*
719 * The same handler is used for both the REPLY to a discrete
720 * statistics request from the host as well as for the periodic
721 * statistics notifications (after received beacons) from the uCode.
b481de9c 722 */
8f91aecb
EG
723 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
724 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91 725
21c339bf 726 iwl_setup_spectrum_handlers(priv);
2a421b91
TW
727 iwl_setup_rx_scan_handlers(priv);
728
37a44211 729 /* status change handler */
5b9f8cd3 730 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 731
c1354754
TW
732 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
733 iwl_rx_missed_beacon_notif;
37a44211 734 /* Rx handlers */
1781a07f
EG
735 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
736 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
737 /* block ack */
738 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 739 /* Set up hardware specific Rx handlers */
d4789efe 740 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
741}
742
b481de9c 743/**
a55360e4 744 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
745 *
746 * Uses the priv->rx_handlers callback function array to invoke
747 * the appropriate handlers, including command responses,
748 * frame-received notifications, and other notifications.
749 */
a55360e4 750void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 751{
a55360e4 752 struct iwl_rx_mem_buffer *rxb;
db11d634 753 struct iwl_rx_packet *pkt;
a55360e4 754 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
755 u32 r, i;
756 int reclaim;
757 unsigned long flags;
5c0eef96 758 u8 fill_rx = 0;
d68ab680 759 u32 count = 8;
4752c93c 760 int total_empty;
b481de9c 761
6440adb5
CB
762 /* uCode's read index (stored in shared DRAM) indicates the last Rx
763 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 764 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
765 i = rxq->read;
766
767 /* Rx interrupt, but nothing sent from uCode */
768 if (i == r)
e1623446 769 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 770
4752c93c 771 /* calculate total frames need to be restock after handling RX */
7300515d 772 total_empty = r - rxq->write_actual;
4752c93c
MA
773 if (total_empty < 0)
774 total_empty += RX_QUEUE_SIZE;
775
776 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
777 fill_rx = 1;
778
b481de9c
ZY
779 while (i != r) {
780 rxb = rxq->queue[i];
781
9fbab516 782 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
783 * then a bug has been introduced in the queue refilling
784 * routines -- catch it here */
785 BUG_ON(rxb == NULL);
786
787 rxq->queue[i] = NULL;
788
2f301227
ZY
789 pci_unmap_page(priv->pci_dev, rxb->page_dma,
790 PAGE_SIZE << priv->hw_params.rx_page_order,
791 PCI_DMA_FROMDEVICE);
792 pkt = rxb_addr(rxb);
b481de9c 793
be1a71a1
JB
794 trace_iwlwifi_dev_rx(priv, pkt,
795 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
796
b481de9c
ZY
797 /* Reclaim a command buffer only if this packet is a response
798 * to a (driver-originated) command.
799 * If the packet (e.g. Rx frame) originated from uCode,
800 * there is no command buffer to reclaim.
801 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
802 * but apparently a few don't get set; catch them here. */
803 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
804 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 805 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 806 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 807 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
808 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
809 (pkt->hdr.cmd != REPLY_TX);
810
811 /* Based on type of command response or notification,
812 * handle those that need handling via function in
5b9f8cd3 813 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 814 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 815 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 816 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 817 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 818 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
819 } else {
820 /* No handling needed */
e1623446 821 IWL_DEBUG_RX(priv,
b481de9c
ZY
822 "r %d i %d No handler needed for %s, 0x%02x\n",
823 r, i, get_cmd_string(pkt->hdr.cmd),
824 pkt->hdr.cmd);
825 }
826
29b1b268
ZY
827 /*
828 * XXX: After here, we should always check rxb->page
829 * against NULL before touching it or its virtual
830 * memory (pkt). Because some rx_handler might have
831 * already taken or freed the pages.
832 */
833
b481de9c 834 if (reclaim) {
2f301227
ZY
835 /* Invoke any callbacks, transfer the buffer to caller,
836 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 837 * as we reclaim the driver command queue */
29b1b268 838 if (rxb->page)
17b88929 839 iwl_tx_cmd_complete(priv, rxb);
b481de9c 840 else
39aadf8c 841 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
842 }
843
7300515d
ZY
844 /* Reuse the page if possible. For notification packets and
845 * SKBs that fail to Rx correctly, add them back into the
846 * rx_free list for reuse later. */
847 spin_lock_irqsave(&rxq->lock, flags);
2f301227 848 if (rxb->page != NULL) {
7300515d
ZY
849 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
850 0, PAGE_SIZE << priv->hw_params.rx_page_order,
851 PCI_DMA_FROMDEVICE);
852 list_add_tail(&rxb->list, &rxq->rx_free);
853 rxq->free_count++;
854 } else
855 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 856
b481de9c 857 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 858
b481de9c 859 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
860 /* If there are a lot of unused frames,
861 * restock the Rx queue so ucode wont assert. */
862 if (fill_rx) {
863 count++;
864 if (count >= 8) {
7300515d 865 rxq->read = i;
4752c93c 866 iwl_rx_replenish_now(priv);
5c0eef96
MA
867 count = 0;
868 }
869 }
b481de9c
ZY
870 }
871
872 /* Backtrack one entry */
7300515d 873 rxq->read = i;
4752c93c
MA
874 if (fill_rx)
875 iwl_rx_replenish_now(priv);
876 else
877 iwl_rx_queue_restock(priv);
a55360e4 878}
a55360e4 879
0359facc
MA
880/* call this function to flush any scheduled tasklet */
881static inline void iwl_synchronize_irq(struct iwl_priv *priv)
882{
a96a27f9 883 /* wait to make sure we flush pending tasklet*/
0359facc
MA
884 synchronize_irq(priv->pci_dev->irq);
885 tasklet_kill(&priv->irq_tasklet);
886}
887
ef850d7c 888static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
889{
890 u32 inta, handled = 0;
891 u32 inta_fh;
892 unsigned long flags;
0a6857e7 893#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
894 u32 inta_mask;
895#endif
896
897 spin_lock_irqsave(&priv->lock, flags);
898
899 /* Ack/clear/reset pending uCode interrupts.
900 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
901 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
902 inta = iwl_read32(priv, CSR_INT);
903 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
904
905 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
906 * Any new interrupts that happen after this, either while we're
907 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
908 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
909 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 910
0a6857e7 911#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 912 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 913 /* just for debug */
3395f6e9 914 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 915 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
916 inta, inta_mask, inta_fh);
917 }
918#endif
919
2f301227
ZY
920 spin_unlock_irqrestore(&priv->lock, flags);
921
b481de9c
ZY
922 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
923 * atomic, make sure that inta covers all the interrupts that
924 * we've discovered, even if FH interrupt came in just after
925 * reading CSR_INT. */
6f83eaa1 926 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 927 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 928 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
929 inta |= CSR_INT_BIT_FH_TX;
930
931 /* Now service all interrupt bits discovered above. */
932 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 933 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
934
935 /* Tell the device to stop sending interrupts */
5b9f8cd3 936 iwl_disable_interrupts(priv);
b481de9c 937
a83b9141 938 priv->isr_stats.hw++;
5b9f8cd3 939 iwl_irq_handle_error(priv);
b481de9c
ZY
940
941 handled |= CSR_INT_BIT_HW_ERR;
942
b481de9c
ZY
943 return;
944 }
945
0a6857e7 946#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 947 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 948 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 949 if (inta & CSR_INT_BIT_SCD) {
e1623446 950 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 951 "the frame/frames.\n");
a83b9141
WYG
952 priv->isr_stats.sch++;
953 }
b481de9c
ZY
954
955 /* Alive notification via Rx interrupt will do the real work */
a83b9141 956 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 957 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
958 priv->isr_stats.alive++;
959 }
b481de9c
ZY
960 }
961#endif
962 /* Safely ignore these bits for debug checks below */
25c03d8e 963 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 964
9fbab516 965 /* HW RF KILL switch toggled */
b481de9c
ZY
966 if (inta & CSR_INT_BIT_RF_KILL) {
967 int hw_rf_kill = 0;
3395f6e9 968 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
969 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
970 hw_rf_kill = 1;
971
4c423a2b 972 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 973 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 974
a83b9141
WYG
975 priv->isr_stats.rfkill++;
976
a9efa652 977 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
978 * the driver allows loading the ucode even if the radio
979 * is killed. Hence update the killswitch state here. The
980 * rfkill handler will care about restarting if needed.
a9efa652 981 */
6cd0b1cb
HS
982 if (!test_bit(STATUS_ALIVE, &priv->status)) {
983 if (hw_rf_kill)
984 set_bit(STATUS_RF_KILL_HW, &priv->status);
985 else
986 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 987 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 988 }
b481de9c
ZY
989
990 handled |= CSR_INT_BIT_RF_KILL;
991 }
992
9fbab516 993 /* Chip got too hot and stopped itself */
b481de9c 994 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 995 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 996 priv->isr_stats.ctkill++;
b481de9c
ZY
997 handled |= CSR_INT_BIT_CT_KILL;
998 }
999
1000 /* Error detected by uCode */
1001 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1002 IWL_ERR(priv, "Microcode SW error detected. "
1003 " Restarting 0x%X.\n", inta);
a83b9141
WYG
1004 priv->isr_stats.sw++;
1005 priv->isr_stats.sw_err = inta;
5b9f8cd3 1006 iwl_irq_handle_error(priv);
b481de9c
ZY
1007 handled |= CSR_INT_BIT_SW_ERR;
1008 }
1009
1010 /* uCode wakes up after power-down sleep */
1011 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1012 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1013 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
babcebfa
TW
1014 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1015 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1016 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1017 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1018 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1019 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1020
a83b9141
WYG
1021 priv->isr_stats.wakeup++;
1022
b481de9c
ZY
1023 handled |= CSR_INT_BIT_WAKEUP;
1024 }
1025
1026 /* All uCode command responses, including Tx command responses,
1027 * Rx "responses" (frame-received notification), and other
1028 * notifications from uCode come through here*/
1029 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1030 iwl_rx_handle(priv);
a83b9141 1031 priv->isr_stats.rx++;
1ed2a3d2 1032 iwl_leds_background(priv);
b481de9c
ZY
1033 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1034 }
1035
1036 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1037 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
a83b9141 1038 priv->isr_stats.tx++;
b481de9c 1039 handled |= CSR_INT_BIT_FH_TX;
dbb983b7
RR
1040 /* FH finished to write, send event */
1041 priv->ucode_write_complete = 1;
1042 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1043 }
1044
a83b9141 1045 if (inta & ~handled) {
15b1687c 1046 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1047 priv->isr_stats.unhandled++;
1048 }
b481de9c 1049
40cefda9 1050 if (inta & ~(priv->inta_mask)) {
39aadf8c 1051 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1052 inta & ~priv->inta_mask);
39aadf8c 1053 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1054 }
1055
1056 /* Re-enable all interrupts */
0359facc
MA
1057 /* only Re-enable if diabled by irq */
1058 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1059 iwl_enable_interrupts(priv);
b481de9c 1060
0a6857e7 1061#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1062 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW
1063 inta = iwl_read32(priv, CSR_INT);
1064 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1065 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1066 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1067 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1068 }
1069#endif
b481de9c
ZY
1070}
1071
ef850d7c
MA
1072/* tasklet for iwlagn interrupt */
1073static void iwl_irq_tasklet(struct iwl_priv *priv)
1074{
1075 u32 inta = 0;
1076 u32 handled = 0;
1077 unsigned long flags;
1078#ifdef CONFIG_IWLWIFI_DEBUG
1079 u32 inta_mask;
1080#endif
1081
1082 spin_lock_irqsave(&priv->lock, flags);
1083
1084 /* Ack/clear/reset pending uCode interrupts.
1085 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1086 */
1087 iwl_write32(priv, CSR_INT, priv->inta);
1088
1089 inta = priv->inta;
1090
1091#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1092 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA
1093 /* just for debug */
1094 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1095 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1096 inta, inta_mask);
1097 }
1098#endif
2f301227
ZY
1099
1100 spin_unlock_irqrestore(&priv->lock, flags);
1101
ef850d7c
MA
1102 /* saved interrupt in inta variable now we can reset priv->inta */
1103 priv->inta = 0;
1104
1105 /* Now service all interrupt bits discovered above. */
1106 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1107 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
1108
1109 /* Tell the device to stop sending interrupts */
1110 iwl_disable_interrupts(priv);
1111
1112 priv->isr_stats.hw++;
1113 iwl_irq_handle_error(priv);
1114
1115 handled |= CSR_INT_BIT_HW_ERR;
1116
ef850d7c
MA
1117 return;
1118 }
1119
1120#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1121 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA
1122 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1123 if (inta & CSR_INT_BIT_SCD) {
1124 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1125 "the frame/frames.\n");
1126 priv->isr_stats.sch++;
1127 }
1128
1129 /* Alive notification via Rx interrupt will do the real work */
1130 if (inta & CSR_INT_BIT_ALIVE) {
1131 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1132 priv->isr_stats.alive++;
1133 }
1134 }
1135#endif
1136 /* Safely ignore these bits for debug checks below */
1137 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1138
1139 /* HW RF KILL switch toggled */
1140 if (inta & CSR_INT_BIT_RF_KILL) {
1141 int hw_rf_kill = 0;
1142 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1143 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1144 hw_rf_kill = 1;
1145
4c423a2b 1146 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
1147 hw_rf_kill ? "disable radio" : "enable radio");
1148
1149 priv->isr_stats.rfkill++;
1150
1151 /* driver only loads ucode once setting the interface up.
1152 * the driver allows loading the ucode even if the radio
1153 * is killed. Hence update the killswitch state here. The
1154 * rfkill handler will care about restarting if needed.
1155 */
1156 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1157 if (hw_rf_kill)
1158 set_bit(STATUS_RF_KILL_HW, &priv->status);
1159 else
1160 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1161 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
1162 }
1163
1164 handled |= CSR_INT_BIT_RF_KILL;
1165 }
1166
1167 /* Chip got too hot and stopped itself */
1168 if (inta & CSR_INT_BIT_CT_KILL) {
1169 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1170 priv->isr_stats.ctkill++;
1171 handled |= CSR_INT_BIT_CT_KILL;
1172 }
1173
1174 /* Error detected by uCode */
1175 if (inta & CSR_INT_BIT_SW_ERR) {
1176 IWL_ERR(priv, "Microcode SW error detected. "
1177 " Restarting 0x%X.\n", inta);
1178 priv->isr_stats.sw++;
1179 priv->isr_stats.sw_err = inta;
1180 iwl_irq_handle_error(priv);
1181 handled |= CSR_INT_BIT_SW_ERR;
1182 }
1183
1184 /* uCode wakes up after power-down sleep */
1185 if (inta & CSR_INT_BIT_WAKEUP) {
1186 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1187 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1188 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1189 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1190 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1191 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1192 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1193 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
1194
1195 priv->isr_stats.wakeup++;
1196
1197 handled |= CSR_INT_BIT_WAKEUP;
1198 }
1199
1200 /* All uCode command responses, including Tx command responses,
1201 * Rx "responses" (frame-received notification), and other
1202 * notifications from uCode come through here*/
40cefda9
MA
1203 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1204 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1205 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1206 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1207 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1208 iwl_write32(priv, CSR_FH_INT_STATUS,
1209 CSR49_FH_INT_RX_MASK);
1210 }
1211 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1212 handled |= CSR_INT_BIT_RX_PERIODIC;
1213 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1214 }
1215 /* Sending RX interrupt require many steps to be done in the
1216 * the device:
1217 * 1- write interrupt to current index in ICT table.
1218 * 2- dma RX frame.
1219 * 3- update RX shared data to indicate last write index.
1220 * 4- send interrupt.
1221 * This could lead to RX race, driver could receive RX interrupt
1222 * but the shared data changes does not reflect this.
1223 * this could lead to RX race, RX periodic will solve this race
1224 */
1225 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1226 CSR_INT_PERIODIC_DIS);
ef850d7c 1227 iwl_rx_handle(priv);
40cefda9
MA
1228 /* Only set RX periodic if real RX is received. */
1229 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1230 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1231 CSR_INT_PERIODIC_ENA);
1232
ef850d7c 1233 priv->isr_stats.rx++;
1ed2a3d2 1234 iwl_leds_background(priv);
ef850d7c
MA
1235 }
1236
1237 if (inta & CSR_INT_BIT_FH_TX) {
1238 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1239 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
1240 priv->isr_stats.tx++;
1241 handled |= CSR_INT_BIT_FH_TX;
1242 /* FH finished to write, send event */
1243 priv->ucode_write_complete = 1;
1244 wake_up_interruptible(&priv->wait_command_queue);
1245 }
1246
1247 if (inta & ~handled) {
1248 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1249 priv->isr_stats.unhandled++;
1250 }
1251
40cefda9 1252 if (inta & ~(priv->inta_mask)) {
ef850d7c 1253 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1254 inta & ~priv->inta_mask);
ef850d7c
MA
1255 }
1256
ef850d7c
MA
1257 /* Re-enable all interrupts */
1258 /* only Re-enable if diabled by irq */
1259 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1260 iwl_enable_interrupts(priv);
ef850d7c
MA
1261}
1262
a83b9141 1263
b481de9c
ZY
1264/******************************************************************************
1265 *
1266 * uCode download functions
1267 *
1268 ******************************************************************************/
1269
5b9f8cd3 1270static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1271{
98c92211
TW
1272 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1273 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1274 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1275 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1276 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1277 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1278}
1279
5b9f8cd3 1280static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1281{
1282 /* Remove all resets to allow NIC to operate */
1283 iwl_write32(priv, CSR_RESET, 0);
1284}
1285
1286
b481de9c 1287/**
5b9f8cd3 1288 * iwl_read_ucode - Read uCode images from disk file.
b481de9c
ZY
1289 *
1290 * Copy into buffers for card to fetch via bus-mastering
1291 */
5b9f8cd3 1292static int iwl_read_ucode(struct iwl_priv *priv)
b481de9c 1293{
cc0f555d 1294 struct iwl_ucode_header *ucode;
a0987a8d 1295 int ret = -EINVAL, index;
b481de9c 1296 const struct firmware *ucode_raw;
a0987a8d
RC
1297 const char *name_pre = priv->cfg->fw_name_pre;
1298 const unsigned int api_max = priv->cfg->ucode_api_max;
1299 const unsigned int api_min = priv->cfg->ucode_api_min;
1300 char buf[25];
b481de9c
ZY
1301 u8 *src;
1302 size_t len;
cc0f555d
JS
1303 u32 api_ver, build;
1304 u32 inst_size, data_size, init_size, init_data_size, boot_size;
abdc2d62 1305 u16 eeprom_ver;
b481de9c
ZY
1306
1307 /* Ask kernel firmware_class module to get the boot firmware off disk.
1308 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
1309 for (index = api_max; index >= api_min; index--) {
1310 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1311 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1312 if (ret < 0) {
15b1687c 1313 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
1314 buf, ret);
1315 if (ret == -ENOENT)
1316 continue;
1317 else
1318 goto error;
1319 } else {
1320 if (index < api_max)
15b1687c
WT
1321 IWL_ERR(priv, "Loaded firmware %s, "
1322 "which is deprecated. "
1323 "Please use API v%u instead.\n",
a0987a8d 1324 buf, api_max);
15b1687c 1325
e1623446 1326 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
a0987a8d
RC
1327 buf, ucode_raw->size);
1328 break;
1329 }
b481de9c
ZY
1330 }
1331
a0987a8d
RC
1332 if (ret < 0)
1333 goto error;
b481de9c 1334
cc0f555d
JS
1335 /* Make sure that we got at least the v1 header! */
1336 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 1337 IWL_ERR(priv, "File size way too small!\n");
90e759d1 1338 ret = -EINVAL;
b481de9c
ZY
1339 goto err_release;
1340 }
1341
1342 /* Data from ucode file: header followed by uCode images */
cc0f555d 1343 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1344
c02b3acd 1345 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1346 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
1347 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1348 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1349 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1350 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1351 init_data_size =
1352 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1353 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1354 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 1355
a0987a8d
RC
1356 /* api_ver should match the api version forming part of the
1357 * firmware filename ... but we don't check for that and only rely
877d0310 1358 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1359
1360 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1361 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1362 "Driver supports v%u, firmware is v%u.\n",
1363 api_max, api_ver);
1364 priv->ucode_ver = 0;
1365 ret = -EINVAL;
1366 goto err_release;
1367 }
1368 if (api_ver != api_max)
978785a3 1369 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1370 "got v%u. New firmware can be obtained "
1371 "from http://www.intellinuxwireless.org.\n",
1372 api_max, api_ver);
1373
978785a3
TW
1374 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1375 IWL_UCODE_MAJOR(priv->ucode_ver),
1376 IWL_UCODE_MINOR(priv->ucode_ver),
1377 IWL_UCODE_API(priv->ucode_ver),
1378 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1379
5ebeb5a6
RC
1380 snprintf(priv->hw->wiphy->fw_version,
1381 sizeof(priv->hw->wiphy->fw_version),
1382 "%u.%u.%u.%u",
1383 IWL_UCODE_MAJOR(priv->ucode_ver),
1384 IWL_UCODE_MINOR(priv->ucode_ver),
1385 IWL_UCODE_API(priv->ucode_ver),
1386 IWL_UCODE_SERIAL(priv->ucode_ver));
1387
cc0f555d
JS
1388 if (build)
1389 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1390
abdc2d62
JS
1391 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1392 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1393 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1394 ? "OTP" : "EEPROM", eeprom_ver);
1395
e1623446 1396 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1397 priv->ucode_ver);
e1623446 1398 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1399 inst_size);
e1623446 1400 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1401 data_size);
e1623446 1402 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1403 init_size);
e1623446 1404 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1405 init_data_size);
e1623446 1406 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1407 boot_size);
1408
1409 /* Verify size of file vs. image size info in file's header */
cc0f555d
JS
1410 if (ucode_raw->size !=
1411 priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
1412 inst_size + data_size + init_size +
1413 init_data_size + boot_size) {
1414
cc0f555d
JS
1415 IWL_DEBUG_INFO(priv,
1416 "uCode file size %d does not match expected size\n",
1417 (int)ucode_raw->size);
90e759d1 1418 ret = -EINVAL;
b481de9c
ZY
1419 goto err_release;
1420 }
1421
1422 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1423 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1424 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
1425 inst_size);
1426 ret = -EINVAL;
b481de9c
ZY
1427 goto err_release;
1428 }
1429
099b40b7 1430 if (data_size > priv->hw_params.max_data_size) {
e1623446 1431 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
1432 data_size);
1433 ret = -EINVAL;
b481de9c
ZY
1434 goto err_release;
1435 }
099b40b7 1436 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1437 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1438 init_size);
90e759d1 1439 ret = -EINVAL;
b481de9c
ZY
1440 goto err_release;
1441 }
099b40b7 1442 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1443 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1
TW
1444 init_data_size);
1445 ret = -EINVAL;
b481de9c
ZY
1446 goto err_release;
1447 }
099b40b7 1448 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1449 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1450 boot_size);
90e759d1 1451 ret = -EINVAL;
b481de9c
ZY
1452 goto err_release;
1453 }
1454
1455 /* Allocate ucode buffers for card's bus-master loading ... */
1456
1457 /* Runtime instructions and 2 copies of data:
1458 * 1) unmodified from disk
1459 * 2) backup cache for save/restore during power-downs */
1460 priv->ucode_code.len = inst_size;
98c92211 1461 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1462
1463 priv->ucode_data.len = data_size;
98c92211 1464 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1465
1466 priv->ucode_data_backup.len = data_size;
98c92211 1467 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1468
1f304e4e
ZY
1469 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1470 !priv->ucode_data_backup.v_addr)
1471 goto err_pci_alloc;
1472
b481de9c 1473 /* Initialization instructions and data */
90e759d1
TW
1474 if (init_size && init_data_size) {
1475 priv->ucode_init.len = init_size;
98c92211 1476 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1477
1478 priv->ucode_init_data.len = init_data_size;
98c92211 1479 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1480
1481 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1482 goto err_pci_alloc;
1483 }
b481de9c
ZY
1484
1485 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1486 if (boot_size) {
1487 priv->ucode_boot.len = boot_size;
98c92211 1488 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1489
90e759d1
TW
1490 if (!priv->ucode_boot.v_addr)
1491 goto err_pci_alloc;
1492 }
b481de9c
ZY
1493
1494 /* Copy images into buffers for card's bus-master reads ... */
1495
1496 /* Runtime instructions (first block of data in file) */
cc0f555d 1497 len = inst_size;
e1623446 1498 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1499 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
1500 src += len;
1501
e1623446 1502 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1503 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1504
1505 /* Runtime data (2nd block)
5b9f8cd3 1506 * NOTE: Copy into backup buffer will be done in iwl_up() */
cc0f555d 1507 len = data_size;
e1623446 1508 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1509 memcpy(priv->ucode_data.v_addr, src, len);
1510 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 1511 src += len;
b481de9c
ZY
1512
1513 /* Initialization instructions (3rd block) */
1514 if (init_size) {
cc0f555d 1515 len = init_size;
e1623446 1516 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1517 len);
b481de9c 1518 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 1519 src += len;
b481de9c
ZY
1520 }
1521
1522 /* Initialization data (4th block) */
1523 if (init_data_size) {
cc0f555d 1524 len = init_data_size;
e1623446 1525 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1526 len);
b481de9c 1527 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 1528 src += len;
b481de9c
ZY
1529 }
1530
1531 /* Bootstrap instructions (5th block) */
cc0f555d 1532 len = boot_size;
e1623446 1533 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1534 memcpy(priv->ucode_boot.v_addr, src, len);
1535
1536 /* We have our copies now, allow OS release its copies */
1537 release_firmware(ucode_raw);
1538 return 0;
1539
1540 err_pci_alloc:
15b1687c 1541 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 1542 ret = -ENOMEM;
5b9f8cd3 1543 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
1544
1545 err_release:
1546 release_firmware(ucode_raw);
1547
1548 error:
90e759d1 1549 return ret;
b481de9c
ZY
1550}
1551
b7a79404
RC
1552#ifdef CONFIG_IWLWIFI_DEBUG
1553static const char *desc_lookup_text[] = {
1554 "OK",
1555 "FAIL",
1556 "BAD_PARAM",
1557 "BAD_CHECKSUM",
1558 "NMI_INTERRUPT_WDG",
1559 "SYSASSERT",
1560 "FATAL_ERROR",
1561 "BAD_COMMAND",
1562 "HW_ERROR_TUNE_LOCK",
1563 "HW_ERROR_TEMPERATURE",
1564 "ILLEGAL_CHAN_FREQ",
1565 "VCC_NOT_STABLE",
1566 "FH_ERROR",
1567 "NMI_INTERRUPT_HOST",
1568 "NMI_INTERRUPT_ACTION_PT",
1569 "NMI_INTERRUPT_UNKNOWN",
1570 "UCODE_VERSION_MISMATCH",
1571 "HW_ERROR_ABS_LOCK",
1572 "HW_ERROR_CAL_LOCK_FAIL",
1573 "NMI_INTERRUPT_INST_ACTION_PT",
1574 "NMI_INTERRUPT_DATA_ACTION_PT",
1575 "NMI_TRM_HW_ER",
1576 "NMI_INTERRUPT_TRM",
1577 "NMI_INTERRUPT_BREAK_POINT"
1578 "DEBUG_0",
1579 "DEBUG_1",
1580 "DEBUG_2",
1581 "DEBUG_3",
1582 "UNKNOWN"
1583};
1584
1585static const char *desc_lookup(int i)
1586{
1587 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1588
1589 if (i < 0 || i > max)
1590 i = max;
1591
1592 return desc_lookup_text[i];
1593}
1594
1595#define ERROR_START_OFFSET (1 * sizeof(u32))
1596#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1597
1598void iwl_dump_nic_error_log(struct iwl_priv *priv)
1599{
1600 u32 data2, line;
1601 u32 desc, time, count, base, data1;
1602 u32 blink1, blink2, ilink1, ilink2;
1603
1604 if (priv->ucode_type == UCODE_INIT)
1605 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1606 else
1607 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1608
1609 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1610 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
1611 return;
1612 }
1613
1614 count = iwl_read_targ_mem(priv, base);
1615
1616 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1617 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1618 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1619 priv->status, count);
1620 }
1621
1622 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1623 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1624 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1625 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1626 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1627 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1628 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1629 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1630 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1631
be1a71a1
JB
1632 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1633 blink1, blink2, ilink1, ilink2);
1634
b7a79404
RC
1635 IWL_ERR(priv, "Desc Time "
1636 "data1 data2 line\n");
1637 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1638 desc_lookup(desc), desc, time, data1, data2, line);
1639 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1640 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1641 ilink1, ilink2);
1642
1643}
1644
1645#define EVENT_START_OFFSET (4 * sizeof(u32))
1646
1647/**
1648 * iwl_print_event_log - Dump error event log to syslog
1649 *
1650 */
1651static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1652 u32 num_events, u32 mode)
1653{
1654 u32 i;
1655 u32 base; /* SRAM byte address of event log header */
1656 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1657 u32 ptr; /* SRAM byte address of log data */
1658 u32 ev, time, data; /* event log data */
1659
1660 if (num_events == 0)
1661 return;
1662 if (priv->ucode_type == UCODE_INIT)
1663 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1664 else
1665 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1666
1667 if (mode == 0)
1668 event_size = 2 * sizeof(u32);
1669 else
1670 event_size = 3 * sizeof(u32);
1671
1672 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1673
1674 /* "time" is actually "data" for mode 0 (no timestamp).
1675 * place event id # at far right for easier visual parsing. */
1676 for (i = 0; i < num_events; i++) {
1677 ev = iwl_read_targ_mem(priv, ptr);
1678 ptr += sizeof(u32);
1679 time = iwl_read_targ_mem(priv, ptr);
1680 ptr += sizeof(u32);
1681 if (mode == 0) {
1682 /* data, ev */
be1a71a1 1683 trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
b7a79404
RC
1684 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
1685 } else {
1686 data = iwl_read_targ_mem(priv, ptr);
1687 ptr += sizeof(u32);
1688 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1689 time, data, ev);
be1a71a1 1690 trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
b7a79404
RC
1691 }
1692 }
1693}
1694
1695void iwl_dump_nic_event_log(struct iwl_priv *priv)
1696{
1697 u32 base; /* SRAM byte address of event log header */
1698 u32 capacity; /* event log capacity in # entries */
1699 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1700 u32 num_wraps; /* # times uCode wrapped to top of log */
1701 u32 next_entry; /* index of next entry to be written by uCode */
1702 u32 size; /* # entries that we'll print */
1703
1704 if (priv->ucode_type == UCODE_INIT)
1705 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1706 else
1707 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1708
1709 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1710 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
1711 return;
1712 }
1713
1714 /* event log header */
1715 capacity = iwl_read_targ_mem(priv, base);
1716 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1717 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1718 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1719
1720 size = num_wraps ? capacity : next_entry;
1721
1722 /* bail out if nothing in log */
1723 if (size == 0) {
1724 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1725 return;
1726 }
1727
1728 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
1729 size, num_wraps);
1730
1731 /* if uCode has wrapped back to top of log, start at the oldest entry,
1732 * i.e the next one that uCode would fill. */
1733 if (num_wraps)
1734 iwl_print_event_log(priv, next_entry,
1735 capacity - next_entry, mode);
1736 /* (then/else) start at top of log */
1737 iwl_print_event_log(priv, 0, next_entry, mode);
1738
1739}
1740#endif
1741
b481de9c 1742/**
4a4a9e81 1743 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1744 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1745 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1746 */
4a4a9e81 1747static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 1748{
57aab75a 1749 int ret = 0;
b481de9c 1750
e1623446 1751 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
1752
1753 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1754 /* We had an error bringing up the hardware, so take it
1755 * all the way back down so we can try again */
e1623446 1756 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
1757 goto restart;
1758 }
1759
1760 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1761 * This is a paranoid check, because we would not have gotten the
1762 * "runtime" alive if code weren't properly loaded. */
b0692f2f 1763 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
1764 /* Runtime instruction load was bad;
1765 * take it all the way back down so we can try again */
e1623446 1766 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
1767 goto restart;
1768 }
1769
c587de0b 1770 iwl_clear_stations_table(priv);
57aab75a
TW
1771 ret = priv->cfg->ops->lib->alive_notify(priv);
1772 if (ret) {
39aadf8c
WT
1773 IWL_WARN(priv,
1774 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
1775 goto restart;
1776 }
1777
5b9f8cd3 1778 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
1779 set_bit(STATUS_ALIVE, &priv->status);
1780
fee1247a 1781 if (iwl_is_rfkill(priv))
b481de9c
ZY
1782 return;
1783
36d6825b 1784 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
1785
1786 priv->active_rate = priv->rates_mask;
1787 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1788
2f748dec
WYG
1789 /* Configure Tx antenna selection based on H/W config */
1790 if (priv->cfg->ops->hcmd->set_tx_ant)
1791 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
1792
3109ece1 1793 if (iwl_is_associated(priv)) {
c1adf9fb
GG
1794 struct iwl_rxon_cmd *active_rxon =
1795 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
1796 /* apply any changes in staging */
1797 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
1798 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1799 } else {
1800 /* Initialize our rx_config data */
5b9f8cd3 1801 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
1802
1803 if (priv->cfg->ops->hcmd->set_rxon_chain)
1804 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1805
b481de9c
ZY
1806 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1807 }
1808
9fbab516 1809 /* Configure Bluetooth device coexistence support */
5b9f8cd3 1810 iwl_send_bt_config(priv);
b481de9c 1811
4a4a9e81
TW
1812 iwl_reset_run_time_calib(priv);
1813
b481de9c 1814 /* Configure the adapter for unassociated operation */
e0158e61 1815 iwlcore_commit_rxon(priv);
b481de9c
ZY
1816
1817 /* At this point, the NIC is initialized and operational */
47f4a587 1818 iwl_rf_kill_ct_config(priv);
5a66926a 1819
e932a609 1820 iwl_leds_init(priv);
fe00b5a5 1821
e1623446 1822 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 1823 set_bit(STATUS_READY, &priv->status);
5a66926a 1824 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 1825
e312c24c 1826 iwl_power_update_mode(priv, true);
c46fbefa 1827
ada17513
MA
1828 /* reassociate for ADHOC mode */
1829 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1830 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1831 priv->vif);
1832 if (beacon)
1833 iwl_mac_beacon_update(priv->hw, beacon);
1834 }
1835
1836
c46fbefa 1837 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 1838 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 1839
b481de9c
ZY
1840 return;
1841
1842 restart:
1843 queue_work(priv->workqueue, &priv->restart);
1844}
1845
4e39317d 1846static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 1847
5b9f8cd3 1848static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1849{
1850 unsigned long flags;
1851 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 1852
e1623446 1853 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 1854
b481de9c
ZY
1855 if (!exit_pending)
1856 set_bit(STATUS_EXIT_PENDING, &priv->status);
1857
c587de0b 1858 iwl_clear_stations_table(priv);
b481de9c
ZY
1859
1860 /* Unblock any waiting calls */
1861 wake_up_interruptible_all(&priv->wait_command_queue);
1862
b481de9c
ZY
1863 /* Wipe out the EXIT_PENDING status bit if we are not actually
1864 * exiting the module */
1865 if (!exit_pending)
1866 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1867
1868 /* stop and reset the on-board processor */
3395f6e9 1869 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
1870
1871 /* tell the device to stop sending interrupts */
0359facc 1872 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 1873 iwl_disable_interrupts(priv);
0359facc
MA
1874 spin_unlock_irqrestore(&priv->lock, flags);
1875 iwl_synchronize_irq(priv);
b481de9c
ZY
1876
1877 if (priv->mac80211_registered)
1878 ieee80211_stop_queues(priv->hw);
1879
5b9f8cd3 1880 /* If we have not previously called iwl_init() then
a60e77e5 1881 * clear all bits but the RF Kill bit and return */
fee1247a 1882 if (!iwl_is_init(priv)) {
b481de9c
ZY
1883 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1884 STATUS_RF_KILL_HW |
9788864e
RC
1885 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1886 STATUS_GEO_CONFIGURED |
052ec3f1
MA
1887 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1888 STATUS_EXIT_PENDING;
b481de9c
ZY
1889 goto exit;
1890 }
1891
6da3a13e 1892 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 1893 * bit and continue taking the NIC down. */
b481de9c
ZY
1894 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1895 STATUS_RF_KILL_HW |
9788864e
RC
1896 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1897 STATUS_GEO_CONFIGURED |
b481de9c 1898 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
1899 STATUS_FW_ERROR |
1900 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1901 STATUS_EXIT_PENDING;
b481de9c 1902
ef850d7c
MA
1903 /* device going down, Stop using ICT table */
1904 iwl_disable_ict(priv);
b481de9c 1905 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 1906 iwl_clear_bit(priv, CSR_GP_CNTRL,
9fbab516 1907 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
1908 spin_unlock_irqrestore(&priv->lock, flags);
1909
da1bc453 1910 iwl_txq_ctx_stop(priv);
b3bbacb7 1911 iwl_rxq_stop(priv);
b481de9c 1912
a8b50a0a
MA
1913 iwl_write_prph(priv, APMG_CLK_DIS_REG,
1914 APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
1915
1916 udelay(5);
1917
4d2ccdb9
BC
1918 /* Stop the device, and put it in low power state */
1919 priv->cfg->ops->lib->apm_ops.stop(priv);
1920
b481de9c 1921 exit:
885ba202 1922 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
1923
1924 if (priv->ibss_beacon)
1925 dev_kfree_skb(priv->ibss_beacon);
1926 priv->ibss_beacon = NULL;
1927
1928 /* clear out any free frames */
fcab423d 1929 iwl_clear_free_frames(priv);
b481de9c
ZY
1930}
1931
5b9f8cd3 1932static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1933{
1934 mutex_lock(&priv->mutex);
5b9f8cd3 1935 __iwl_down(priv);
b481de9c 1936 mutex_unlock(&priv->mutex);
b24d22b1 1937
4e39317d 1938 iwl_cancel_deferred_work(priv);
b481de9c
ZY
1939}
1940
086ed117
MA
1941#define HW_READY_TIMEOUT (50)
1942
1943static int iwl_set_hw_ready(struct iwl_priv *priv)
1944{
1945 int ret = 0;
1946
1947 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1948 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
1949
1950 /* See if we got it */
1951 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1952 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1953 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1954 HW_READY_TIMEOUT);
1955 if (ret != -ETIMEDOUT)
1956 priv->hw_ready = true;
1957 else
1958 priv->hw_ready = false;
1959
1960 IWL_DEBUG_INFO(priv, "hardware %s\n",
1961 (priv->hw_ready == 1) ? "ready" : "not ready");
1962 return ret;
1963}
1964
1965static int iwl_prepare_card_hw(struct iwl_priv *priv)
1966{
1967 int ret = 0;
1968
1969 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
1970
3354a0f6
MA
1971 ret = iwl_set_hw_ready(priv);
1972 if (priv->hw_ready)
1973 return ret;
1974
1975 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
1976 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1977 CSR_HW_IF_CONFIG_REG_PREPARE);
1978
1979 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1980 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
1981 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
1982
3354a0f6 1983 /* HW should be ready by now, check again. */
086ed117
MA
1984 if (ret != -ETIMEDOUT)
1985 iwl_set_hw_ready(priv);
1986
1987 return ret;
1988}
1989
b481de9c
ZY
1990#define MAX_HW_RESTARTS 5
1991
5b9f8cd3 1992static int __iwl_up(struct iwl_priv *priv)
b481de9c 1993{
57aab75a
TW
1994 int i;
1995 int ret;
b481de9c
ZY
1996
1997 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 1998 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
1999 return -EIO;
2000 }
2001
e903fbd4 2002 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2003 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
2004 return -EIO;
2005 }
2006
086ed117
MA
2007 iwl_prepare_card_hw(priv);
2008
2009 if (!priv->hw_ready) {
2010 IWL_WARN(priv, "Exit HW not ready\n");
2011 return -EIO;
2012 }
2013
e655b9f0 2014 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2015 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2016 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2017 else
e655b9f0 2018 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2019
c1842d61 2020 if (iwl_is_rfkill(priv)) {
a60e77e5
JB
2021 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2022
5b9f8cd3 2023 iwl_enable_interrupts(priv);
a60e77e5 2024 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2025 return 0;
b481de9c
ZY
2026 }
2027
3395f6e9 2028 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2029
1053d35f 2030 ret = iwl_hw_nic_init(priv);
57aab75a 2031 if (ret) {
15b1687c 2032 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2033 return ret;
b481de9c
ZY
2034 }
2035
2036 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
2037 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2038 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2039 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2040
2041 /* clear (again), then enable host interrupts */
3395f6e9 2042 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2043 iwl_enable_interrupts(priv);
b481de9c
ZY
2044
2045 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
2046 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2047 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2048
2049 /* Copy original ucode data image from disk into backup cache.
2050 * This will be used to initialize the on-board processor's
2051 * data SRAM for a clean start when the runtime program first loads. */
2052 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2053 priv->ucode_data.len);
b481de9c 2054
b481de9c
ZY
2055 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2056
c587de0b 2057 iwl_clear_stations_table(priv);
b481de9c
ZY
2058
2059 /* load bootstrap state machine,
2060 * load bootstrap program into processor's memory,
2061 * prepare to load the "initialize" uCode */
57aab75a 2062 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2063
57aab75a 2064 if (ret) {
15b1687c
WT
2065 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2066 ret);
b481de9c
ZY
2067 continue;
2068 }
2069
2070 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2071 iwl_nic_start(priv);
b481de9c 2072
e1623446 2073 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2074
2075 return 0;
2076 }
2077
2078 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2079 __iwl_down(priv);
64e72c3e 2080 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2081
2082 /* tried to restart and config the device for as long as our
2083 * patience could withstand */
15b1687c 2084 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2085 return -EIO;
2086}
2087
2088
2089/*****************************************************************************
2090 *
2091 * Workqueue callbacks
2092 *
2093 *****************************************************************************/
2094
4a4a9e81 2095static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2096{
c79dd5b5
TW
2097 struct iwl_priv *priv =
2098 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2099
2100 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2101 return;
2102
2103 mutex_lock(&priv->mutex);
f3ccc08c 2104 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
2105 mutex_unlock(&priv->mutex);
2106}
2107
4a4a9e81 2108static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2109{
c79dd5b5
TW
2110 struct iwl_priv *priv =
2111 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2112
2113 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2114 return;
2115
258c44a0
MA
2116 /* enable dram interrupt */
2117 iwl_reset_ict(priv);
2118
b481de9c 2119 mutex_lock(&priv->mutex);
4a4a9e81 2120 iwl_alive_start(priv);
b481de9c
ZY
2121 mutex_unlock(&priv->mutex);
2122}
2123
16e727e8
EG
2124static void iwl_bg_run_time_calib_work(struct work_struct *work)
2125{
2126 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2127 run_time_calib_work);
2128
2129 mutex_lock(&priv->mutex);
2130
2131 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2132 test_bit(STATUS_SCANNING, &priv->status)) {
2133 mutex_unlock(&priv->mutex);
2134 return;
2135 }
2136
2137 if (priv->start_calib) {
2138 iwl_chain_noise_calibration(priv, &priv->statistics);
2139
2140 iwl_sensitivity_calibration(priv, &priv->statistics);
2141 }
2142
2143 mutex_unlock(&priv->mutex);
2144 return;
2145}
2146
5b9f8cd3 2147static void iwl_bg_up(struct work_struct *data)
b481de9c 2148{
c79dd5b5 2149 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
2150
2151 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2152 return;
2153
2154 mutex_lock(&priv->mutex);
5b9f8cd3 2155 __iwl_up(priv);
b481de9c
ZY
2156 mutex_unlock(&priv->mutex);
2157}
2158
5b9f8cd3 2159static void iwl_bg_restart(struct work_struct *data)
b481de9c 2160{
c79dd5b5 2161 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2162
2163 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2164 return;
2165
19cc1087
JB
2166 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2167 mutex_lock(&priv->mutex);
2168 priv->vif = NULL;
2169 priv->is_open = 0;
2170 mutex_unlock(&priv->mutex);
2171 iwl_down(priv);
2172 ieee80211_restart_hw(priv->hw);
2173 } else {
2174 iwl_down(priv);
2175 queue_work(priv->workqueue, &priv->up);
2176 }
b481de9c
ZY
2177}
2178
5b9f8cd3 2179static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2180{
c79dd5b5
TW
2181 struct iwl_priv *priv =
2182 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2183
2184 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2185 return;
2186
2187 mutex_lock(&priv->mutex);
a55360e4 2188 iwl_rx_replenish(priv);
b481de9c
ZY
2189 mutex_unlock(&priv->mutex);
2190}
2191
7878a5a4
MA
2192#define IWL_DELAY_NEXT_SCAN (HZ*2)
2193
5bbe233b 2194void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2195{
b481de9c 2196 struct ieee80211_conf *conf = NULL;
857485c0 2197 int ret = 0;
1ff50bda 2198 unsigned long flags;
b481de9c 2199
05c914fe 2200 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2201 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2202 return;
2203 }
2204
e1623446 2205 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 2206 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
2207
2208
2209 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2210 return;
2211
b481de9c 2212
508e32e1 2213 if (!priv->vif || !priv->is_open)
948c171c 2214 return;
508e32e1 2215
2a421b91 2216 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2217
b481de9c
ZY
2218 conf = ieee80211_get_hw_conf(priv->hw);
2219
2220 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2221 iwlcore_commit_rxon(priv);
b481de9c 2222
3195c1f3 2223 iwl_setup_rxon_timing(priv);
857485c0 2224 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2225 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2226 if (ret)
39aadf8c 2227 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2228 "Attempting to continue.\n");
2229
2230 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2231
42eb7c64 2232 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2233
45823531
AK
2234 if (priv->cfg->ops->hcmd->set_rxon_chain)
2235 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2236
b481de9c
ZY
2237 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2238
e1623446 2239 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2240 priv->assoc_id, priv->beacon_int);
2241
2242 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2243 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2244 else
2245 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2246
2247 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2248 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2249 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2250 else
2251 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2252
05c914fe 2253 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2254 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2255
2256 }
2257
e0158e61 2258 iwlcore_commit_rxon(priv);
b481de9c
ZY
2259
2260 switch (priv->iw_mode) {
05c914fe 2261 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2262 break;
2263
05c914fe 2264 case NL80211_IFTYPE_ADHOC:
b481de9c 2265
c46fbefa
AK
2266 /* assume default assoc id */
2267 priv->assoc_id = 1;
b481de9c 2268
4f40e4d9 2269 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 2270 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2271
2272 break;
2273
2274 default:
15b1687c 2275 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2276 __func__, priv->iw_mode);
b481de9c
ZY
2277 break;
2278 }
2279
05c914fe 2280 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2281 priv->assoc_station_added = 1;
2282
1ff50bda
EG
2283 spin_lock_irqsave(&priv->lock, flags);
2284 iwl_activate_qos(priv, 0);
2285 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 2286
04816448
GE
2287 /* the chain noise calibration will enabled PM upon completion
2288 * If chain noise has already been run, then we need to enable
2289 * power management here */
2290 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 2291 iwl_power_update_mode(priv, false);
c90a74ba
EG
2292
2293 /* Enable Rx differential gain and sensitivity calibrations */
2294 iwl_chain_noise_reset(priv);
2295 priv->start_calib = 1;
2296
508e32e1
RC
2297}
2298
b481de9c
ZY
2299/*****************************************************************************
2300 *
2301 * mac80211 entry point functions
2302 *
2303 *****************************************************************************/
2304
154b25ce 2305#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2306
f0b6e2e8
RC
2307/*
2308 * Not a mac80211 entry point function, but it fits in with all the
2309 * other mac80211 functions grouped here.
2310 */
2311static int iwl_setup_mac(struct iwl_priv *priv)
2312{
2313 int ret;
2314 struct ieee80211_hw *hw = priv->hw;
2315 hw->rate_control_algorithm = "iwl-agn-rs";
2316
2317 /* Tell mac80211 our characteristics */
2318 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2319 IEEE80211_HW_NOISE_DBM |
2320 IEEE80211_HW_AMPDU_AGGREGATION |
2321 IEEE80211_HW_SPECTRUM_MGMT;
2322
2323 if (!priv->cfg->broken_powersave)
2324 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2325 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2326
8d9698b3 2327 hw->sta_data_size = sizeof(struct iwl_station_priv);
f0b6e2e8
RC
2328 hw->wiphy->interface_modes =
2329 BIT(NL80211_IFTYPE_STATION) |
2330 BIT(NL80211_IFTYPE_ADHOC);
2331
2332 hw->wiphy->custom_regulatory = true;
2333
2334 /* Firmware does not support this */
2335 hw->wiphy->disable_beacon_hints = true;
2336
2337 /*
2338 * For now, disable PS by default because it affects
2339 * RX performance significantly.
2340 */
2341 hw->wiphy->ps_default = false;
2342
2343 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2344 /* we create the 802.11 header and a zero-length SSID element */
2345 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2346
2347 /* Default value; 4 EDCA QOS priorities */
2348 hw->queues = 4;
2349
2350 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2351
2352 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2353 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2354 &priv->bands[IEEE80211_BAND_2GHZ];
2355 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2356 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2357 &priv->bands[IEEE80211_BAND_5GHZ];
2358
2359 ret = ieee80211_register_hw(priv->hw);
2360 if (ret) {
2361 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2362 return ret;
2363 }
2364 priv->mac80211_registered = 1;
2365
2366 return 0;
2367}
2368
2369
5b9f8cd3 2370static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2371{
c79dd5b5 2372 struct iwl_priv *priv = hw->priv;
5a66926a 2373 int ret;
b481de9c 2374
e1623446 2375 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2376
2377 /* we should be verifying the device is ready to be opened */
2378 mutex_lock(&priv->mutex);
2379
5a66926a
ZY
2380 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2381 * ucode filename and max sizes are card-specific. */
b481de9c 2382
5a66926a 2383 if (!priv->ucode_code.len) {
5b9f8cd3 2384 ret = iwl_read_ucode(priv);
5a66926a 2385 if (ret) {
15b1687c 2386 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a 2387 mutex_unlock(&priv->mutex);
6cd0b1cb 2388 return ret;
5a66926a
ZY
2389 }
2390 }
b481de9c 2391
5b9f8cd3 2392 ret = __iwl_up(priv);
5a66926a 2393
b481de9c 2394 mutex_unlock(&priv->mutex);
5a66926a 2395
e655b9f0 2396 if (ret)
6cd0b1cb 2397 return ret;
e655b9f0 2398
c1842d61
TW
2399 if (iwl_is_rfkill(priv))
2400 goto out;
2401
e1623446 2402 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2403
fe9b6b72 2404 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2405 * mac80211 will not be run successfully. */
154b25ce
EG
2406 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2407 test_bit(STATUS_READY, &priv->status),
2408 UCODE_READY_TIMEOUT);
2409 if (!ret) {
2410 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2411 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2412 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2413 return -ETIMEDOUT;
5a66926a 2414 }
fe9b6b72 2415 }
0a078ffa 2416
e932a609
JB
2417 iwl_led_start(priv);
2418
c1842d61 2419out:
0a078ffa 2420 priv->is_open = 1;
e1623446 2421 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2422 return 0;
2423}
2424
5b9f8cd3 2425static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2426{
c79dd5b5 2427 struct iwl_priv *priv = hw->priv;
b481de9c 2428
e1623446 2429 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2430
19cc1087 2431 if (!priv->is_open)
e655b9f0 2432 return;
e655b9f0 2433
b481de9c 2434 priv->is_open = 0;
5a66926a 2435
5bddf549 2436 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY
2437 /* stop mac, cancel any scan request and clear
2438 * RXON_FILTER_ASSOC_MSK BIT
2439 */
5a66926a 2440 mutex_lock(&priv->mutex);
2a421b91 2441 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2442 mutex_unlock(&priv->mutex);
fde3571f
MA
2443 }
2444
5b9f8cd3 2445 iwl_down(priv);
5a66926a
ZY
2446
2447 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2448
2449 /* enable interrupts again in order to receive rfkill changes */
2450 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2451 iwl_enable_interrupts(priv);
948c171c 2452
e1623446 2453 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2454}
2455
5b9f8cd3 2456static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2457{
c79dd5b5 2458 struct iwl_priv *priv = hw->priv;
b481de9c 2459
e1623446 2460 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2461
e1623446 2462 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2463 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2464
e039fa4a 2465 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2466 dev_kfree_skb_any(skb);
2467
e1623446 2468 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2469 return NETDEV_TX_OK;
b481de9c
ZY
2470}
2471
60690a6a 2472void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2473{
857485c0 2474 int ret = 0;
1ff50bda 2475 unsigned long flags;
b481de9c 2476
d986bcd1 2477 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2478 return;
2479
2480 /* The following should be done only at AP bring up */
3195c1f3 2481 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2482
2483 /* RXON - unassoc (to set timing command) */
2484 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2485 iwlcore_commit_rxon(priv);
b481de9c
ZY
2486
2487 /* RXON Timing */
3195c1f3 2488 iwl_setup_rxon_timing(priv);
857485c0 2489 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2490 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2491 if (ret)
39aadf8c 2492 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2493 "Attempting to continue.\n");
2494
45823531
AK
2495 if (priv->cfg->ops->hcmd->set_rxon_chain)
2496 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2497
2498 /* FIXME: what should be the assoc_id for AP? */
2499 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2500 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2501 priv->staging_rxon.flags |=
2502 RXON_FLG_SHORT_PREAMBLE_MSK;
2503 else
2504 priv->staging_rxon.flags &=
2505 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2506
2507 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2508 if (priv->assoc_capability &
2509 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2510 priv->staging_rxon.flags |=
2511 RXON_FLG_SHORT_SLOT_MSK;
2512 else
2513 priv->staging_rxon.flags &=
2514 ~RXON_FLG_SHORT_SLOT_MSK;
2515
05c914fe 2516 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2517 priv->staging_rxon.flags &=
2518 ~RXON_FLG_SHORT_SLOT_MSK;
2519 }
2520 /* restore RXON assoc */
2521 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2522 iwlcore_commit_rxon(priv);
1ff50bda
EG
2523 spin_lock_irqsave(&priv->lock, flags);
2524 iwl_activate_qos(priv, 1);
2525 spin_unlock_irqrestore(&priv->lock, flags);
4f40e4d9 2526 iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
e1493deb 2527 }
5b9f8cd3 2528 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2529
2530 /* FIXME - we need to add code here to detect a totally new
2531 * configuration, reset the AP, unassoc, rxon timing, assoc,
2532 * clear sta table, add BCAST sta... */
2533}
2534
5b9f8cd3 2535static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
ab885f8c
EG
2536 struct ieee80211_key_conf *keyconf, const u8 *addr,
2537 u32 iv32, u16 *phase1key)
2538{
ab885f8c 2539
9f58671e 2540 struct iwl_priv *priv = hw->priv;
e1623446 2541 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2542
9f58671e 2543 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
ab885f8c 2544
e1623446 2545 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2546}
2547
5b9f8cd3 2548static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2549 struct ieee80211_vif *vif,
2550 struct ieee80211_sta *sta,
b481de9c
ZY
2551 struct ieee80211_key_conf *key)
2552{
c79dd5b5 2553 struct iwl_priv *priv = hw->priv;
42986796
WT
2554 const u8 *addr;
2555 int ret;
2556 u8 sta_id;
2557 bool is_default_wep_key = false;
b481de9c 2558
e1623446 2559 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2560
90e8e424 2561 if (priv->cfg->mod_params->sw_crypto) {
e1623446 2562 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2563 return -EOPNOTSUPP;
2564 }
42986796 2565 addr = sta ? sta->addr : iwl_bcast_addr;
c587de0b 2566 sta_id = iwl_find_station(priv, addr);
6974e363 2567 if (sta_id == IWL_INVALID_STATION) {
e1623446 2568 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2569 addr);
6974e363 2570 return -EINVAL;
b481de9c 2571
deb09c43 2572 }
b481de9c 2573
6974e363 2574 mutex_lock(&priv->mutex);
2a421b91 2575 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2576 mutex_unlock(&priv->mutex);
2577
2578 /* If we are getting WEP group key and we didn't receive any key mapping
2579 * so far, we are in legacy wep mode (group key only), otherwise we are
2580 * in 1X mode.
2581 * In legacy wep mode, we use another host command to the uCode */
5425e490 2582 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2583 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2584 if (cmd == SET_KEY)
2585 is_default_wep_key = !priv->key_mapping_key;
2586 else
ccc038ab
EG
2587 is_default_wep_key =
2588 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2589 }
052c4b9f 2590
b481de9c 2591 switch (cmd) {
deb09c43 2592 case SET_KEY:
6974e363
EG
2593 if (is_default_wep_key)
2594 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2595 else
7480513f 2596 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2597
e1623446 2598 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2599 break;
2600 case DISABLE_KEY:
6974e363
EG
2601 if (is_default_wep_key)
2602 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2603 else
3ec47732 2604 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2605
e1623446 2606 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2607 break;
2608 default:
deb09c43 2609 ret = -EINVAL;
b481de9c
ZY
2610 }
2611
e1623446 2612 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2613
deb09c43 2614 return ret;
b481de9c
ZY
2615}
2616
5b9f8cd3 2617static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
d783b061 2618 enum ieee80211_ampdu_mlme_action action,
17741cdc 2619 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2620{
2621 struct iwl_priv *priv = hw->priv;
5c2207c6 2622 int ret;
d783b061 2623
e1623446 2624 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2625 sta->addr, tid);
d783b061
TW
2626
2627 if (!(priv->cfg->sku & IWL_SKU_N))
2628 return -EACCES;
2629
2630 switch (action) {
2631 case IEEE80211_AMPDU_RX_START:
e1623446 2632 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2633 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2634 case IEEE80211_AMPDU_RX_STOP:
e1623446 2635 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2636 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2637 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2638 return 0;
2639 else
2640 return ret;
d783b061 2641 case IEEE80211_AMPDU_TX_START:
e1623446 2642 IWL_DEBUG_HT(priv, "start Tx\n");
17741cdc 2643 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2644 case IEEE80211_AMPDU_TX_STOP:
e1623446 2645 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2646 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2647 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2648 return 0;
2649 else
2650 return ret;
d783b061 2651 default:
e1623446 2652 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2653 return -EINVAL;
2654 break;
2655 }
2656 return 0;
2657}
9f58671e 2658
5b9f8cd3 2659static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2660 struct ieee80211_low_level_stats *stats)
2661{
bf403db8
EK
2662 struct iwl_priv *priv = hw->priv;
2663
2664 priv = hw->priv;
e1623446
TW
2665 IWL_DEBUG_MAC80211(priv, "enter\n");
2666 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2667
2668 return 0;
2669}
2670
b481de9c
ZY
2671/*****************************************************************************
2672 *
2673 * sysfs attributes
2674 *
2675 *****************************************************************************/
2676
0a6857e7 2677#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2678
2679/*
2680 * The following adds a new attribute to the sysfs representation
c3a739fa 2681 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
2682 * used for controlling the debug level.
2683 *
2684 * See the level definitions in iwl for details.
a562a9dd 2685 *
3d816c77
RC
2686 * The debug_level being managed using sysfs below is a per device debug
2687 * level that is used instead of the global debug level if it (the per
2688 * device debug level) is set.
b481de9c 2689 */
8cf769c6
EK
2690static ssize_t show_debug_level(struct device *d,
2691 struct device_attribute *attr, char *buf)
b481de9c 2692{
3d816c77
RC
2693 struct iwl_priv *priv = dev_get_drvdata(d);
2694 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 2695}
8cf769c6
EK
2696static ssize_t store_debug_level(struct device *d,
2697 struct device_attribute *attr,
b481de9c
ZY
2698 const char *buf, size_t count)
2699{
928841b1 2700 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2701 unsigned long val;
2702 int ret;
b481de9c 2703
9257746f
TW
2704 ret = strict_strtoul(buf, 0, &val);
2705 if (ret)
978785a3 2706 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 2707 else {
3d816c77 2708 priv->debug_level = val;
20594eb0
WYG
2709 if (iwl_alloc_traffic_mem(priv))
2710 IWL_ERR(priv,
2711 "Not enough memory to generate traffic log\n");
2712 }
b481de9c
ZY
2713 return strnlen(buf, count);
2714}
2715
8cf769c6
EK
2716static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2717 show_debug_level, store_debug_level);
2718
b481de9c 2719
0a6857e7 2720#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 2721
b481de9c
ZY
2722
2723static ssize_t show_temperature(struct device *d,
2724 struct device_attribute *attr, char *buf)
2725{
928841b1 2726 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 2727
fee1247a 2728 if (!iwl_is_alive(priv))
b481de9c
ZY
2729 return -EAGAIN;
2730
91dbc5bd 2731 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
2732}
2733
2734static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2735
b481de9c
ZY
2736static ssize_t show_tx_power(struct device *d,
2737 struct device_attribute *attr, char *buf)
2738{
928841b1 2739 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
2740
2741 if (!iwl_is_ready_rf(priv))
2742 return sprintf(buf, "off\n");
2743 else
2744 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
2745}
2746
2747static ssize_t store_tx_power(struct device *d,
2748 struct device_attribute *attr,
2749 const char *buf, size_t count)
2750{
928841b1 2751 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2752 unsigned long val;
2753 int ret;
b481de9c 2754
9257746f
TW
2755 ret = strict_strtoul(buf, 10, &val);
2756 if (ret)
978785a3 2757 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
5eadd94b
WYG
2758 else {
2759 ret = iwl_set_tx_power(priv, val, false);
2760 if (ret)
2761 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
2762 ret);
2763 else
2764 ret = count;
2765 }
2766 return ret;
b481de9c
ZY
2767}
2768
2769static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2770
2771static ssize_t show_flags(struct device *d,
2772 struct device_attribute *attr, char *buf)
2773{
928841b1 2774 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2775
2776 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2777}
2778
2779static ssize_t store_flags(struct device *d,
2780 struct device_attribute *attr,
2781 const char *buf, size_t count)
2782{
928841b1 2783 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2784 unsigned long val;
2785 u32 flags;
2786 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2787 if (ret)
9257746f
TW
2788 return ret;
2789 flags = (u32)val;
b481de9c
ZY
2790
2791 mutex_lock(&priv->mutex);
2792 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2793 /* Cancel any currently running scans... */
2a421b91 2794 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2795 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2796 else {
e1623446 2797 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 2798 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 2799 iwlcore_commit_rxon(priv);
b481de9c
ZY
2800 }
2801 }
2802 mutex_unlock(&priv->mutex);
2803
2804 return count;
2805}
2806
2807static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2808
2809static ssize_t show_filter_flags(struct device *d,
2810 struct device_attribute *attr, char *buf)
2811{
928841b1 2812 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2813
2814 return sprintf(buf, "0x%04X\n",
2815 le32_to_cpu(priv->active_rxon.filter_flags));
2816}
2817
2818static ssize_t store_filter_flags(struct device *d,
2819 struct device_attribute *attr,
2820 const char *buf, size_t count)
2821{
928841b1 2822 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2823 unsigned long val;
2824 u32 filter_flags;
2825 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2826 if (ret)
9257746f
TW
2827 return ret;
2828 filter_flags = (u32)val;
b481de9c
ZY
2829
2830 mutex_lock(&priv->mutex);
2831 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2832 /* Cancel any currently running scans... */
2a421b91 2833 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2834 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2835 else {
e1623446 2836 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY
2837 "0x%04X\n", filter_flags);
2838 priv->staging_rxon.filter_flags =
2839 cpu_to_le32(filter_flags);
e0158e61 2840 iwlcore_commit_rxon(priv);
b481de9c
ZY
2841 }
2842 }
2843 mutex_unlock(&priv->mutex);
2844
2845 return count;
2846}
2847
2848static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2849 store_filter_flags);
2850
b481de9c
ZY
2851
2852static ssize_t show_statistics(struct device *d,
2853 struct device_attribute *attr, char *buf)
2854{
c79dd5b5 2855 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 2856 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 2857 u32 len = 0, ofs = 0;
3ac7f146 2858 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
2859 int rc = 0;
2860
fee1247a 2861 if (!iwl_is_alive(priv))
b481de9c
ZY
2862 return -EAGAIN;
2863
2864 mutex_lock(&priv->mutex);
49ea8596 2865 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
2866 mutex_unlock(&priv->mutex);
2867
2868 if (rc) {
2869 len = sprintf(buf,
2870 "Error sending statistics request: 0x%08X\n", rc);
2871 return len;
2872 }
2873
2874 while (size && (PAGE_SIZE - len)) {
2875 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2876 PAGE_SIZE - len, 1);
2877 len = strlen(buf);
2878 if (PAGE_SIZE - len)
2879 buf[len++] = '\n';
2880
2881 ofs += 16;
2882 size -= min(size, 16U);
2883 }
2884
2885 return len;
2886}
2887
2888static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
2889
01abfbb2
WYG
2890static ssize_t show_rts_ht_protection(struct device *d,
2891 struct device_attribute *attr, char *buf)
2892{
2893 struct iwl_priv *priv = dev_get_drvdata(d);
2894
2895 return sprintf(buf, "%s\n",
2896 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
2897}
2898
2899static ssize_t store_rts_ht_protection(struct device *d,
2900 struct device_attribute *attr,
2901 const char *buf, size_t count)
2902{
2903 struct iwl_priv *priv = dev_get_drvdata(d);
2904 unsigned long val;
2905 int ret;
2906
2907 ret = strict_strtoul(buf, 10, &val);
2908 if (ret)
2909 IWL_INFO(priv, "Input is not in decimal form.\n");
2910 else {
2911 if (!iwl_is_associated(priv))
2912 priv->cfg->use_rts_for_ht = val ? true : false;
2913 else
2914 IWL_ERR(priv, "Sta associated with AP - "
2915 "Change protection mechanism is not allowed\n");
2916 ret = count;
2917 }
2918 return ret;
2919}
2920
2921static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
2922 show_rts_ht_protection, store_rts_ht_protection);
2923
b481de9c 2924
b481de9c
ZY
2925/*****************************************************************************
2926 *
2927 * driver setup and teardown
2928 *
2929 *****************************************************************************/
2930
4e39317d 2931static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2932{
d21050c7 2933 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
2934
2935 init_waitqueue_head(&priv->wait_command_queue);
2936
5b9f8cd3
EG
2937 INIT_WORK(&priv->up, iwl_bg_up);
2938 INIT_WORK(&priv->restart, iwl_bg_restart);
2939 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 2940 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 2941 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
2942 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
2943 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 2944
2a421b91 2945 iwl_setup_scan_deferred_work(priv);
bb8c093b 2946
4e39317d
EG
2947 if (priv->cfg->ops->lib->setup_deferred_work)
2948 priv->cfg->ops->lib->setup_deferred_work(priv);
2949
2950 init_timer(&priv->statistics_periodic);
2951 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 2952 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 2953
ef850d7c
MA
2954 if (!priv->cfg->use_isr_legacy)
2955 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2956 iwl_irq_tasklet, (unsigned long)priv);
2957 else
2958 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2959 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
2960}
2961
4e39317d 2962static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2963{
4e39317d
EG
2964 if (priv->cfg->ops->lib->cancel_deferred_work)
2965 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 2966
3ae6a054 2967 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
2968 cancel_delayed_work(&priv->scan_check);
2969 cancel_delayed_work(&priv->alive_start);
b481de9c 2970 cancel_work_sync(&priv->beacon_update);
4e39317d 2971 del_timer_sync(&priv->statistics_periodic);
b481de9c
ZY
2972}
2973
5b9f8cd3 2974static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY
2975 &dev_attr_flags.attr,
2976 &dev_attr_filter_flags.attr,
b481de9c 2977 &dev_attr_statistics.attr,
b481de9c 2978 &dev_attr_temperature.attr,
b481de9c 2979 &dev_attr_tx_power.attr,
01abfbb2 2980 &dev_attr_rts_ht_protection.attr,
8cf769c6
EK
2981#ifdef CONFIG_IWLWIFI_DEBUG
2982 &dev_attr_debug_level.attr,
2983#endif
b481de9c
ZY
2984 NULL
2985};
2986
5b9f8cd3 2987static struct attribute_group iwl_attribute_group = {
b481de9c 2988 .name = NULL, /* put in device directory */
5b9f8cd3 2989 .attrs = iwl_sysfs_entries,
b481de9c
ZY
2990};
2991
5b9f8cd3
EG
2992static struct ieee80211_ops iwl_hw_ops = {
2993 .tx = iwl_mac_tx,
2994 .start = iwl_mac_start,
2995 .stop = iwl_mac_stop,
2996 .add_interface = iwl_mac_add_interface,
2997 .remove_interface = iwl_mac_remove_interface,
2998 .config = iwl_mac_config,
5b9f8cd3
EG
2999 .configure_filter = iwl_configure_filter,
3000 .set_key = iwl_mac_set_key,
3001 .update_tkip_key = iwl_mac_update_tkip_key,
3002 .get_stats = iwl_mac_get_stats,
3003 .get_tx_stats = iwl_mac_get_tx_stats,
3004 .conf_tx = iwl_mac_conf_tx,
3005 .reset_tsf = iwl_mac_reset_tsf,
3006 .bss_info_changed = iwl_bss_info_changed,
3007 .ampdu_action = iwl_mac_ampdu_action,
cb43dc25 3008 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
3009};
3010
5b9f8cd3 3011static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3012{
3013 int err = 0;
c79dd5b5 3014 struct iwl_priv *priv;
b481de9c 3015 struct ieee80211_hw *hw;
82b9a121 3016 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3017 unsigned long flags;
6cd0b1cb 3018 u16 pci_cmd;
b481de9c 3019
316c30d9
AK
3020 /************************
3021 * 1. Allocating HW data
3022 ************************/
3023
6440adb5
CB
3024 /* Disabling hardware scan means that mac80211 will perform scans
3025 * "the hard way", rather than using device's scan. */
1ea87396 3026 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3027 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK
3028 dev_printk(KERN_DEBUG, &(pdev->dev),
3029 "Disabling hw_scan\n");
5b9f8cd3 3030 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
3031 }
3032
5b9f8cd3 3033 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3034 if (!hw) {
b481de9c
ZY
3035 err = -ENOMEM;
3036 goto out;
3037 }
1d0a082d
AK
3038 priv = hw->priv;
3039 /* At this point both hw and priv are allocated. */
3040
b481de9c
ZY
3041 SET_IEEE80211_DEV(hw, &pdev->dev);
3042
e1623446 3043 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3044 priv->cfg = cfg;
b481de9c 3045 priv->pci_dev = pdev;
40cefda9 3046 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3047
0a6857e7 3048#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3049 atomic_set(&priv->restrict_refcnt, 0);
3050#endif
20594eb0
WYG
3051 if (iwl_alloc_traffic_mem(priv))
3052 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3053
316c30d9
AK
3054 /**************************
3055 * 2. Initializing PCI bus
3056 **************************/
3057 if (pci_enable_device(pdev)) {
3058 err = -ENODEV;
3059 goto out_ieee80211_free_hw;
3060 }
3061
3062 pci_set_master(pdev);
3063
093d874c 3064 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3065 if (!err)
093d874c 3066 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3067 if (err) {
093d874c 3068 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3069 if (!err)
093d874c 3070 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3071 /* both attempts failed: */
316c30d9 3072 if (err) {
978785a3 3073 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3074 goto out_pci_disable_device;
cc2a8ea8 3075 }
316c30d9
AK
3076 }
3077
3078 err = pci_request_regions(pdev, DRV_NAME);
3079 if (err)
3080 goto out_pci_disable_device;
3081
3082 pci_set_drvdata(pdev, priv);
3083
316c30d9
AK
3084
3085 /***********************
3086 * 3. Read REV register
3087 ***********************/
3088 priv->hw_base = pci_iomap(pdev, 0, 0);
3089 if (!priv->hw_base) {
3090 err = -ENODEV;
3091 goto out_pci_release_regions;
3092 }
3093
e1623446 3094 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3095 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3096 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3097
a8b50a0a
MA
3098 /* this spin lock will be used in apm_ops.init and EEPROM access
3099 * we should init now
3100 */
3101 spin_lock_init(&priv->reg_lock);
b661c819 3102 iwl_hw_detect(priv);
978785a3 3103 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 3104 priv->cfg->name, priv->hw_rev);
316c30d9 3105
e7b63581
TW
3106 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3107 * PCI Tx retries from interfering with C3 CPU state */
3108 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3109
086ed117
MA
3110 iwl_prepare_card_hw(priv);
3111 if (!priv->hw_ready) {
3112 IWL_WARN(priv, "Failed, HW not ready\n");
3113 goto out_iounmap;
3114 }
3115
91238714
TW
3116 /*****************
3117 * 4. Read EEPROM
3118 *****************/
316c30d9
AK
3119 /* Read the EEPROM */
3120 err = iwl_eeprom_init(priv);
3121 if (err) {
15b1687c 3122 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
3123 goto out_iounmap;
3124 }
8614f360
TW
3125 err = iwl_eeprom_check_version(priv);
3126 if (err)
c8f16138 3127 goto out_free_eeprom;
8614f360 3128
02883017 3129 /* extract MAC Address */
316c30d9 3130 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3131 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
3132 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3133
3134 /************************
3135 * 5. Setup HW constants
3136 ************************/
da154e30 3137 if (iwl_set_hw_params(priv)) {
15b1687c 3138 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3139 goto out_free_eeprom;
316c30d9
AK
3140 }
3141
3142 /*******************
6ba87956 3143 * 6. Setup priv
316c30d9 3144 *******************/
b481de9c 3145
6ba87956 3146 err = iwl_init_drv(priv);
bf85ea4f 3147 if (err)
399f4900 3148 goto out_free_eeprom;
bf85ea4f 3149 /* At this point both hw and priv are initialized. */
316c30d9 3150
316c30d9 3151 /********************
09f9bf79 3152 * 7. Setup services
316c30d9 3153 ********************/
0359facc 3154 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3155 iwl_disable_interrupts(priv);
0359facc 3156 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3157
6cd0b1cb
HS
3158 pci_enable_msi(priv->pci_dev);
3159
ef850d7c
MA
3160 iwl_alloc_isr_ict(priv);
3161 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3162 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
3163 if (err) {
3164 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3165 goto out_disable_msi;
3166 }
5b9f8cd3 3167 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3168 if (err) {
15b1687c 3169 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3170 goto out_free_irq;
316c30d9
AK
3171 }
3172
4e39317d 3173 iwl_setup_deferred_work(priv);
653fa4a0 3174 iwl_setup_rx_handlers(priv);
316c30d9 3175
6ba87956 3176 /**********************************
09f9bf79 3177 * 8. Setup and register mac80211
6ba87956
TW
3178 **********************************/
3179
6cd0b1cb
HS
3180 /* enable interrupts if needed: hw bug w/a */
3181 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3182 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3183 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3184 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3185 }
3186
3187 iwl_enable_interrupts(priv);
3188
6ba87956
TW
3189 err = iwl_setup_mac(priv);
3190 if (err)
3191 goto out_remove_sysfs;
3192
3193 err = iwl_dbgfs_register(priv, DRV_NAME);
3194 if (err)
a75fbe8d 3195 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
6ba87956 3196
6cd0b1cb
HS
3197 /* If platform's RF_KILL switch is NOT set to KILL */
3198 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3199 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3200 else
3201 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3202
a60e77e5
JB
3203 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3204 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3205
58d0f361 3206 iwl_power_initialize(priv);
39b73fb1 3207 iwl_tt_initialize(priv);
b481de9c
ZY
3208 return 0;
3209
316c30d9 3210 out_remove_sysfs:
c8f16138
RC
3211 destroy_workqueue(priv->workqueue);
3212 priv->workqueue = NULL;
5b9f8cd3 3213 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3214 out_free_irq:
3215 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3216 iwl_free_isr_ict(priv);
6cd0b1cb
HS
3217 out_disable_msi:
3218 pci_disable_msi(priv->pci_dev);
6ba87956 3219 iwl_uninit_drv(priv);
073d3f5f
TW
3220 out_free_eeprom:
3221 iwl_eeprom_free(priv);
b481de9c
ZY
3222 out_iounmap:
3223 pci_iounmap(pdev, priv->hw_base);
3224 out_pci_release_regions:
316c30d9 3225 pci_set_drvdata(pdev, NULL);
623d563e 3226 pci_release_regions(pdev);
b481de9c
ZY
3227 out_pci_disable_device:
3228 pci_disable_device(pdev);
b481de9c 3229 out_ieee80211_free_hw:
20594eb0 3230 iwl_free_traffic_mem(priv);
d7c76f4c 3231 ieee80211_free_hw(priv->hw);
b481de9c
ZY
3232 out:
3233 return err;
3234}
3235
5b9f8cd3 3236static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3237{
c79dd5b5 3238 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3239 unsigned long flags;
b481de9c
ZY
3240
3241 if (!priv)
3242 return;
3243
e1623446 3244 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3245
67249625 3246 iwl_dbgfs_unregister(priv);
5b9f8cd3 3247 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3248
5b9f8cd3
EG
3249 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3250 * to be called and iwl_down since we are removing the device
0b124c31
GG
3251 * we need to set STATUS_EXIT_PENDING bit.
3252 */
3253 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3254 if (priv->mac80211_registered) {
3255 ieee80211_unregister_hw(priv->hw);
3256 priv->mac80211_registered = 0;
0b124c31 3257 } else {
5b9f8cd3 3258 iwl_down(priv);
c4f55232
RR
3259 }
3260
c166b25a
BC
3261 /*
3262 * Make sure device is reset to low power before unloading driver.
3263 * This may be redundant with iwl_down(), but there are paths to
3264 * run iwl_down() without calling apm_ops.stop(), and there are
3265 * paths to avoid running iwl_down() at all before leaving driver.
3266 * This (inexpensive) call *makes sure* device is reset.
3267 */
3268 priv->cfg->ops->lib->apm_ops.stop(priv);
3269
39b73fb1
WYG
3270 iwl_tt_exit(priv);
3271
0359facc
MA
3272 /* make sure we flush any pending irq or
3273 * tasklet for the driver
3274 */
3275 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3276 iwl_disable_interrupts(priv);
0359facc
MA
3277 spin_unlock_irqrestore(&priv->lock, flags);
3278
3279 iwl_synchronize_irq(priv);
3280
5b9f8cd3 3281 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3282
3283 if (priv->rxq.bd)
a55360e4 3284 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3285 iwl_hw_txq_ctx_free(priv);
b481de9c 3286
c587de0b 3287 iwl_clear_stations_table(priv);
073d3f5f 3288 iwl_eeprom_free(priv);
b481de9c 3289
b481de9c 3290
948c171c
MA
3291 /*netif_stop_queue(dev); */
3292 flush_workqueue(priv->workqueue);
3293
5b9f8cd3 3294 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3295 * priv->workqueue... so we can't take down the workqueue
3296 * until now... */
3297 destroy_workqueue(priv->workqueue);
3298 priv->workqueue = NULL;
20594eb0 3299 iwl_free_traffic_mem(priv);
b481de9c 3300
6cd0b1cb
HS
3301 free_irq(priv->pci_dev->irq, priv);
3302 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3303 pci_iounmap(pdev, priv->hw_base);
3304 pci_release_regions(pdev);
3305 pci_disable_device(pdev);
3306 pci_set_drvdata(pdev, NULL);
3307
6ba87956 3308 iwl_uninit_drv(priv);
b481de9c 3309
ef850d7c
MA
3310 iwl_free_isr_ict(priv);
3311
b481de9c
ZY
3312 if (priv->ibss_beacon)
3313 dev_kfree_skb(priv->ibss_beacon);
3314
3315 ieee80211_free_hw(priv->hw);
3316}
3317
b481de9c
ZY
3318
3319/*****************************************************************************
3320 *
3321 * driver and module entry point
3322 *
3323 *****************************************************************************/
3324
fed9017e
RR
3325/* Hardware specific file defines the PCI IDs table for that hardware module */
3326static struct pci_device_id iwl_hw_card_ids[] = {
4fc22b21 3327#ifdef CONFIG_IWL4965
fed9017e
RR
3328 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3329 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3330#endif /* CONFIG_IWL4965 */
5a6a256e 3331#ifdef CONFIG_IWL5000
47408639
EK
3332 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3333 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3334 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3335 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3336 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3337 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
5a6a256e 3338 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
47408639
EK
3339 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3340 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3341 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
e96a8495
TW
3342/* 5350 WiFi/WiMax */
3343 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3344 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3345 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
7100e924
TW
3346/* 5150 Wifi/WiMax */
3347 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3348 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
5953a62e
WYG
3349
3350/* 6x00 Series */
3351 {IWL_PCI_DEVICE(0x008D, 0x1301, iwl6000h_2agn_cfg)},
3352 {IWL_PCI_DEVICE(0x008D, 0x1321, iwl6000h_2agn_cfg)},
3353 {IWL_PCI_DEVICE(0x008D, 0x1326, iwl6000h_2abg_cfg)},
3354 {IWL_PCI_DEVICE(0x008D, 0x1306, iwl6000h_2abg_cfg)},
3355 {IWL_PCI_DEVICE(0x008D, 0x1307, iwl6000h_2bg_cfg)},
3356 {IWL_PCI_DEVICE(0x008E, 0x1311, iwl6000h_2agn_cfg)},
3357 {IWL_PCI_DEVICE(0x008E, 0x1316, iwl6000h_2abg_cfg)},
3358
3359 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3360 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3361 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3362 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3363 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3364 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3365 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3366 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3367 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3368 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3369
3370/* 6x50 WiFi/WiMax Series */
3371 {IWL_PCI_DEVICE(0x0086, 0x1101, iwl6050_3agn_cfg)},
3372 {IWL_PCI_DEVICE(0x0086, 0x1121, iwl6050_3agn_cfg)},
3373 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3374 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3375 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3376 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
3377 {IWL_PCI_DEVICE(0x0088, 0x1111, iwl6050_3agn_cfg)},
3378 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3379 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3380
77dcb6a9 3381/* 1000 Series WiFi */
4bd0914f
WYG
3382 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3383 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3384 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3385 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3386 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3387 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3388 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3389 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3390 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3391 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3392 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3393 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 3394#endif /* CONFIG_IWL5000 */
7100e924 3395
fed9017e
RR
3396 {0}
3397};
3398MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3399
3400static struct pci_driver iwl_driver = {
b481de9c 3401 .name = DRV_NAME,
fed9017e 3402 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3403 .probe = iwl_pci_probe,
3404 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3405#ifdef CONFIG_PM
5b9f8cd3
EG
3406 .suspend = iwl_pci_suspend,
3407 .resume = iwl_pci_resume,
b481de9c
ZY
3408#endif
3409};
3410
5b9f8cd3 3411static int __init iwl_init(void)
b481de9c
ZY
3412{
3413
3414 int ret;
3415 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3416 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3417
e227ceac 3418 ret = iwlagn_rate_control_register();
897e1cf2 3419 if (ret) {
a3139c59
SO
3420 printk(KERN_ERR DRV_NAME
3421 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3422 return ret;
3423 }
3424
fed9017e 3425 ret = pci_register_driver(&iwl_driver);
b481de9c 3426 if (ret) {
a3139c59 3427 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3428 goto error_register;
b481de9c 3429 }
b481de9c
ZY
3430
3431 return ret;
897e1cf2 3432
897e1cf2 3433error_register:
e227ceac 3434 iwlagn_rate_control_unregister();
897e1cf2 3435 return ret;
b481de9c
ZY
3436}
3437
5b9f8cd3 3438static void __exit iwl_exit(void)
b481de9c 3439{
fed9017e 3440 pci_unregister_driver(&iwl_driver);
e227ceac 3441 iwlagn_rate_control_unregister();
b481de9c
ZY
3442}
3443
5b9f8cd3
EG
3444module_exit(iwl_exit);
3445module_init(iwl_init);
a562a9dd
RC
3446
3447#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 3448module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 3449MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 3450module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC
3451MODULE_PARM_DESC(debug, "debug output mask");
3452#endif
3453
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