Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/wireless.h> | |
39 | #include <linux/firmware.h> | |
b481de9c ZY |
40 | #include <linux/etherdevice.h> |
41 | #include <linux/if_arp.h> | |
42 | ||
b481de9c ZY |
43 | #include <net/mac80211.h> |
44 | ||
45 | #include <asm/div64.h> | |
46 | ||
a3139c59 SO |
47 | #define DRV_NAME "iwlagn" |
48 | ||
6bc913bd | 49 | #include "iwl-eeprom.h" |
3e0d4cb1 | 50 | #include "iwl-dev.h" |
fee1247a | 51 | #include "iwl-core.h" |
3395f6e9 | 52 | #include "iwl-io.h" |
b481de9c | 53 | #include "iwl-helpers.h" |
6974e363 | 54 | #include "iwl-sta.h" |
f0832f13 | 55 | #include "iwl-calib.h" |
b481de9c | 56 | |
416e1438 | 57 | |
b481de9c ZY |
58 | /****************************************************************************** |
59 | * | |
60 | * module boiler plate | |
61 | * | |
62 | ******************************************************************************/ | |
63 | ||
b481de9c ZY |
64 | /* |
65 | * module name, copyright, version, etc. | |
b481de9c | 66 | */ |
d783b061 | 67 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 68 | |
0a6857e7 | 69 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
70 | #define VD "d" |
71 | #else | |
72 | #define VD | |
73 | #endif | |
74 | ||
80bc5393 | 75 | #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT |
b481de9c ZY |
76 | #define VS "s" |
77 | #else | |
78 | #define VS | |
79 | #endif | |
80 | ||
df48c323 | 81 | #define DRV_VERSION IWLWIFI_VERSION VD VS |
b481de9c | 82 | |
b481de9c ZY |
83 | |
84 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
85 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 86 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c | 87 | MODULE_LICENSE("GPL"); |
4fc22b21 | 88 | MODULE_ALIAS("iwl4965"); |
b481de9c | 89 | |
b481de9c | 90 | /*************** STATION TABLE MANAGEMENT **** |
9fbab516 | 91 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
92 | * the functionality provided here |
93 | */ | |
94 | ||
95 | /**************************************************************/ | |
96 | ||
b481de9c | 97 | /** |
5b9f8cd3 | 98 | * iwl_commit_rxon - commit staging_rxon to hardware |
b481de9c | 99 | * |
01ebd063 | 100 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
101 | * the active_rxon structure is updated with the new data. This |
102 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
103 | * a HW tune is required based on the RXON structure changes. | |
104 | */ | |
e0158e61 | 105 | int iwl_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
106 | { |
107 | /* cast away the const for active_rxon in this function */ | |
c1adf9fb | 108 | struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
43d59b32 EG |
109 | int ret; |
110 | bool new_assoc = | |
111 | !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK); | |
b481de9c | 112 | |
fee1247a | 113 | if (!iwl_is_alive(priv)) |
43d59b32 | 114 | return -EBUSY; |
b481de9c ZY |
115 | |
116 | /* always get timestamp with Rx frame */ | |
117 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
a326a5d0 EG |
118 | /* allow CTS-to-self if possible. this is relevant only for |
119 | * 5000, but will not damage 4965 */ | |
120 | priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN; | |
b481de9c | 121 | |
8ccde88a | 122 | ret = iwl_check_rxon_cmd(priv); |
43d59b32 | 123 | if (ret) { |
15b1687c | 124 | IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); |
b481de9c ZY |
125 | return -EINVAL; |
126 | } | |
127 | ||
128 | /* If we don't need to send a full RXON, we can use | |
5b9f8cd3 | 129 | * iwl_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 130 | * and other flags for the current radio configuration. */ |
54559703 | 131 | if (!iwl_full_rxon_required(priv)) { |
43d59b32 EG |
132 | ret = iwl_send_rxon_assoc(priv); |
133 | if (ret) { | |
15b1687c | 134 | IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret); |
43d59b32 | 135 | return ret; |
b481de9c ZY |
136 | } |
137 | ||
138 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
139 | return 0; |
140 | } | |
141 | ||
142 | /* station table will be cleared */ | |
143 | priv->assoc_station_added = 0; | |
144 | ||
b481de9c ZY |
145 | /* If we are currently associated and the new config requires |
146 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
147 | * we must clear the associated from the active configuration | |
148 | * before we apply the new config */ | |
43d59b32 | 149 | if (iwl_is_associated(priv) && new_assoc) { |
e1623446 | 150 | IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n"); |
b481de9c ZY |
151 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
152 | ||
43d59b32 | 153 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, |
c1adf9fb | 154 | sizeof(struct iwl_rxon_cmd), |
b481de9c ZY |
155 | &priv->active_rxon); |
156 | ||
157 | /* If the mask clearing failed then we set | |
158 | * active_rxon back to what it was previously */ | |
43d59b32 | 159 | if (ret) { |
b481de9c | 160 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; |
15b1687c | 161 | IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret); |
43d59b32 | 162 | return ret; |
b481de9c | 163 | } |
b481de9c ZY |
164 | } |
165 | ||
e1623446 | 166 | IWL_DEBUG_INFO(priv, "Sending RXON\n" |
b481de9c ZY |
167 | "* with%s RXON_FILTER_ASSOC_MSK\n" |
168 | "* channel = %d\n" | |
e174961c | 169 | "* bssid = %pM\n", |
43d59b32 | 170 | (new_assoc ? "" : "out"), |
b481de9c | 171 | le16_to_cpu(priv->staging_rxon.channel), |
e174961c | 172 | priv->staging_rxon.bssid_addr); |
b481de9c | 173 | |
90e8e424 | 174 | iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto); |
43d59b32 EG |
175 | |
176 | /* Apply the new configuration | |
177 | * RXON unassoc clears the station table in uCode, send it before | |
178 | * we add the bcast station. If assoc bit is set, we will send RXON | |
179 | * after having added the bcast and bssid station. | |
180 | */ | |
181 | if (!new_assoc) { | |
182 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
c1adf9fb | 183 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); |
43d59b32 | 184 | if (ret) { |
15b1687c | 185 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
186 | return ret; |
187 | } | |
188 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
189 | } |
190 | ||
c587de0b | 191 | iwl_clear_stations_table(priv); |
556f8db7 | 192 | |
19cc1087 | 193 | priv->start_calib = 0; |
b481de9c | 194 | |
b481de9c | 195 | /* Add the broadcast address so we can send broadcast frames */ |
4f40e4d9 | 196 | if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) == |
43d59b32 | 197 | IWL_INVALID_STATION) { |
15b1687c | 198 | IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n"); |
b481de9c ZY |
199 | return -EIO; |
200 | } | |
201 | ||
202 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
203 | * add the IWL_AP_ID to the station rate table */ | |
9185159d | 204 | if (new_assoc) { |
05c914fe | 205 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
9185159d TW |
206 | ret = iwl_rxon_add_station(priv, |
207 | priv->active_rxon.bssid_addr, 1); | |
208 | if (ret == IWL_INVALID_STATION) { | |
15b1687c WT |
209 | IWL_ERR(priv, |
210 | "Error adding AP address for TX.\n"); | |
9185159d TW |
211 | return -EIO; |
212 | } | |
213 | priv->assoc_station_added = 1; | |
214 | if (priv->default_wep_key && | |
215 | iwl_send_static_wepkey_cmd(priv, 0)) | |
15b1687c WT |
216 | IWL_ERR(priv, |
217 | "Could not send WEP static key.\n"); | |
b481de9c | 218 | } |
43d59b32 EG |
219 | |
220 | /* Apply the new configuration | |
221 | * RXON assoc doesn't clear the station table in uCode, | |
222 | */ | |
223 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
224 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); | |
225 | if (ret) { | |
15b1687c | 226 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
227 | return ret; |
228 | } | |
229 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
230 | } |
231 | ||
36da7d70 ZY |
232 | iwl_init_sensitivity(priv); |
233 | ||
234 | /* If we issue a new RXON command which required a tune then we must | |
235 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
236 | ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true); | |
237 | if (ret) { | |
15b1687c | 238 | IWL_ERR(priv, "Error sending TX power (%d)\n", ret); |
36da7d70 ZY |
239 | return ret; |
240 | } | |
241 | ||
b481de9c ZY |
242 | return 0; |
243 | } | |
244 | ||
5b9f8cd3 | 245 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f MA |
246 | { |
247 | ||
45823531 AK |
248 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
249 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
e0158e61 | 250 | iwlcore_commit_rxon(priv); |
5da4b55f MA |
251 | } |
252 | ||
fcab423d | 253 | static void iwl_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
254 | { |
255 | struct list_head *element; | |
256 | ||
e1623446 | 257 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
258 | priv->frames_count); |
259 | ||
260 | while (!list_empty(&priv->free_frames)) { | |
261 | element = priv->free_frames.next; | |
262 | list_del(element); | |
fcab423d | 263 | kfree(list_entry(element, struct iwl_frame, list)); |
b481de9c ZY |
264 | priv->frames_count--; |
265 | } | |
266 | ||
267 | if (priv->frames_count) { | |
39aadf8c | 268 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
269 | priv->frames_count); |
270 | priv->frames_count = 0; | |
271 | } | |
272 | } | |
273 | ||
fcab423d | 274 | static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv) |
b481de9c | 275 | { |
fcab423d | 276 | struct iwl_frame *frame; |
b481de9c ZY |
277 | struct list_head *element; |
278 | if (list_empty(&priv->free_frames)) { | |
279 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
280 | if (!frame) { | |
15b1687c | 281 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
282 | return NULL; |
283 | } | |
284 | ||
285 | priv->frames_count++; | |
286 | return frame; | |
287 | } | |
288 | ||
289 | element = priv->free_frames.next; | |
290 | list_del(element); | |
fcab423d | 291 | return list_entry(element, struct iwl_frame, list); |
b481de9c ZY |
292 | } |
293 | ||
fcab423d | 294 | static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) |
b481de9c ZY |
295 | { |
296 | memset(frame, 0, sizeof(*frame)); | |
297 | list_add(&frame->list, &priv->free_frames); | |
298 | } | |
299 | ||
4bf64efd TW |
300 | static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv, |
301 | struct ieee80211_hdr *hdr, | |
73ec1cc2 | 302 | int left) |
b481de9c | 303 | { |
3109ece1 | 304 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
305 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
306 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
307 | return 0; |
308 | ||
309 | if (priv->ibss_beacon->len > left) | |
310 | return 0; | |
311 | ||
312 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
313 | ||
314 | return priv->ibss_beacon->len; | |
315 | } | |
316 | ||
5b9f8cd3 | 317 | static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, |
4bf64efd TW |
318 | struct iwl_frame *frame, u8 rate) |
319 | { | |
320 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
321 | unsigned int frame_size; | |
322 | ||
323 | tx_beacon_cmd = &frame->u.beacon; | |
324 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
325 | ||
326 | tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id; | |
327 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
328 | ||
329 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, | |
4bf64efd TW |
330 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
331 | ||
332 | BUG_ON(frame_size > MAX_MPDU_SIZE); | |
333 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); | |
334 | ||
335 | if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP)) | |
336 | tx_beacon_cmd->tx.rate_n_flags = | |
337 | iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK); | |
338 | else | |
339 | tx_beacon_cmd->tx.rate_n_flags = | |
340 | iwl_hw_set_rate_n_flags(rate, 0); | |
341 | ||
342 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
343 | TX_CMD_FLG_TSF_MSK | | |
344 | TX_CMD_FLG_STA_RATE_MSK; | |
345 | ||
346 | return sizeof(*tx_beacon_cmd) + frame_size; | |
347 | } | |
5b9f8cd3 | 348 | static int iwl_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 349 | { |
fcab423d | 350 | struct iwl_frame *frame; |
b481de9c ZY |
351 | unsigned int frame_size; |
352 | int rc; | |
353 | u8 rate; | |
354 | ||
fcab423d | 355 | frame = iwl_get_free_frame(priv); |
b481de9c ZY |
356 | |
357 | if (!frame) { | |
15b1687c | 358 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
359 | "command.\n"); |
360 | return -ENOMEM; | |
361 | } | |
362 | ||
5b9f8cd3 | 363 | rate = iwl_rate_get_lowest_plcp(priv); |
b481de9c | 364 | |
5b9f8cd3 | 365 | frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 366 | |
857485c0 | 367 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
368 | &frame->u.cmd[0]); |
369 | ||
fcab423d | 370 | iwl_free_frame(priv, frame); |
b481de9c ZY |
371 | |
372 | return rc; | |
373 | } | |
374 | ||
7aaa1d79 SO |
375 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
376 | { | |
377 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
378 | ||
379 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
380 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
381 | addr |= | |
382 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
383 | ||
384 | return addr; | |
385 | } | |
386 | ||
387 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
388 | { | |
389 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
390 | ||
391 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
392 | } | |
393 | ||
394 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
395 | dma_addr_t addr, u16 len) | |
396 | { | |
397 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
398 | u16 hi_n_len = len << 4; | |
399 | ||
400 | put_unaligned_le32(addr, &tb->lo); | |
401 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
402 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
403 | ||
404 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
405 | ||
406 | tfd->num_tbs = idx + 1; | |
407 | } | |
408 | ||
409 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
410 | { | |
411 | return tfd->num_tbs & 0x1f; | |
412 | } | |
413 | ||
414 | /** | |
415 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
416 | * @priv - driver private data | |
417 | * @txq - tx queue | |
418 | * | |
419 | * Does NOT advance any TFD circular buffer read/write indexes | |
420 | * Does NOT free the TFD itself (which is within circular buffer) | |
421 | */ | |
422 | void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
423 | { | |
59606ffa | 424 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; |
7aaa1d79 SO |
425 | struct iwl_tfd *tfd; |
426 | struct pci_dev *dev = priv->pci_dev; | |
427 | int index = txq->q.read_ptr; | |
428 | int i; | |
429 | int num_tbs; | |
430 | ||
431 | tfd = &tfd_tmp[index]; | |
432 | ||
433 | /* Sanity check on number of chunks */ | |
434 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
435 | ||
436 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
437 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
438 | /* @todo issue fatal error, it is quite serious situation */ | |
439 | return; | |
440 | } | |
441 | ||
442 | /* Unmap tx_cmd */ | |
443 | if (num_tbs) | |
444 | pci_unmap_single(dev, | |
c2acea8e JB |
445 | pci_unmap_addr(&txq->meta[index], mapping), |
446 | pci_unmap_len(&txq->meta[index], len), | |
96891cee | 447 | PCI_DMA_BIDIRECTIONAL); |
7aaa1d79 SO |
448 | |
449 | /* Unmap chunks, if any. */ | |
450 | for (i = 1; i < num_tbs; i++) { | |
451 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), | |
452 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
453 | ||
454 | if (txq->txb) { | |
455 | dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]); | |
456 | txq->txb[txq->q.read_ptr].skb[i - 1] = NULL; | |
457 | } | |
458 | } | |
459 | } | |
460 | ||
461 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
462 | struct iwl_tx_queue *txq, | |
463 | dma_addr_t addr, u16 len, | |
464 | u8 reset, u8 pad) | |
465 | { | |
466 | struct iwl_queue *q; | |
59606ffa | 467 | struct iwl_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
468 | u32 num_tbs; |
469 | ||
470 | q = &txq->q; | |
59606ffa SO |
471 | tfd_tmp = (struct iwl_tfd *)txq->tfds; |
472 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
473 | |
474 | if (reset) | |
475 | memset(tfd, 0, sizeof(*tfd)); | |
476 | ||
477 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
478 | ||
479 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
480 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
481 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
482 | IWL_NUM_OF_TBS); | |
483 | return -EINVAL; | |
484 | } | |
485 | ||
486 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
487 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
488 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
489 | (unsigned long long)addr); | |
490 | ||
491 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
492 | ||
493 | return 0; | |
494 | } | |
495 | ||
a8e74e27 SO |
496 | /* |
497 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
498 | * given Tx queue, and enable the DMA channel used for that queue. | |
499 | * | |
500 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
501 | * channels supported in hardware. | |
502 | */ | |
503 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
504 | struct iwl_tx_queue *txq) | |
505 | { | |
a8e74e27 SO |
506 | int txq_id = txq->q.id; |
507 | ||
a8e74e27 SO |
508 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
509 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
510 | txq->q.dma_addr >> 8); | |
511 | ||
a8e74e27 SO |
512 | return 0; |
513 | } | |
514 | ||
b481de9c ZY |
515 | /****************************************************************************** |
516 | * | |
517 | * Generic RX handler implementations | |
518 | * | |
519 | ******************************************************************************/ | |
885ba202 TW |
520 | static void iwl_rx_reply_alive(struct iwl_priv *priv, |
521 | struct iwl_rx_mem_buffer *rxb) | |
b481de9c | 522 | { |
db11d634 | 523 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
885ba202 | 524 | struct iwl_alive_resp *palive; |
b481de9c ZY |
525 | struct delayed_work *pwork; |
526 | ||
527 | palive = &pkt->u.alive_frame; | |
528 | ||
e1623446 | 529 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
530 | "0x%01X 0x%01X\n", |
531 | palive->is_valid, palive->ver_type, | |
532 | palive->ver_subtype); | |
533 | ||
534 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 535 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
b481de9c ZY |
536 | memcpy(&priv->card_alive_init, |
537 | &pkt->u.alive_frame, | |
885ba202 | 538 | sizeof(struct iwl_init_alive_resp)); |
b481de9c ZY |
539 | pwork = &priv->init_alive_start; |
540 | } else { | |
e1623446 | 541 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 542 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
885ba202 | 543 | sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
544 | pwork = &priv->alive_start; |
545 | } | |
546 | ||
547 | /* We delay the ALIVE response by 5ms to | |
548 | * give the HW RF Kill time to activate... */ | |
549 | if (palive->is_valid == UCODE_VALID_OK) | |
550 | queue_delayed_work(priv->workqueue, pwork, | |
551 | msecs_to_jiffies(5)); | |
552 | else | |
39aadf8c | 553 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
554 | } |
555 | ||
5b9f8cd3 | 556 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 557 | { |
c79dd5b5 TW |
558 | struct iwl_priv *priv = |
559 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
560 | struct sk_buff *beacon; |
561 | ||
562 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 563 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
564 | |
565 | if (!beacon) { | |
15b1687c | 566 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
567 | return; |
568 | } | |
569 | ||
570 | mutex_lock(&priv->mutex); | |
571 | /* new beacon skb is allocated every time; dispose previous.*/ | |
572 | if (priv->ibss_beacon) | |
573 | dev_kfree_skb(priv->ibss_beacon); | |
574 | ||
575 | priv->ibss_beacon = beacon; | |
576 | mutex_unlock(&priv->mutex); | |
577 | ||
5b9f8cd3 | 578 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
579 | } |
580 | ||
4e39317d | 581 | /** |
5b9f8cd3 | 582 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
583 | * |
584 | * This callback is provided in order to send a statistics request. | |
585 | * | |
586 | * This timer function is continually reset to execute within | |
587 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
588 | * was received. We need to ensure we receive the statistics in order | |
589 | * to update the temperature used for calibrating the TXPOWER. | |
590 | */ | |
5b9f8cd3 | 591 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
592 | { |
593 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
594 | ||
595 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
596 | return; | |
597 | ||
61780ee3 MA |
598 | /* dont send host command if rf-kill is on */ |
599 | if (!iwl_is_ready_rf(priv)) | |
600 | return; | |
601 | ||
4e39317d EG |
602 | iwl_send_statistics_request(priv, CMD_ASYNC); |
603 | } | |
604 | ||
5b9f8cd3 | 605 | static void iwl_rx_beacon_notif(struct iwl_priv *priv, |
a55360e4 | 606 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 607 | { |
0a6857e7 | 608 | #ifdef CONFIG_IWLWIFI_DEBUG |
db11d634 | 609 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
2aa6ab86 TW |
610 | struct iwl4965_beacon_notif *beacon = |
611 | (struct iwl4965_beacon_notif *)pkt->u.raw; | |
e7d326ac | 612 | u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
b481de9c | 613 | |
e1623446 | 614 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c | 615 | "tsf %d %d rate %d\n", |
25a6572c | 616 | le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, |
b481de9c ZY |
617 | beacon->beacon_notify_hdr.failure_frame, |
618 | le32_to_cpu(beacon->ibss_mgr_status), | |
619 | le32_to_cpu(beacon->high_tsf), | |
620 | le32_to_cpu(beacon->low_tsf), rate); | |
621 | #endif | |
622 | ||
05c914fe | 623 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
624 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
625 | queue_work(priv->workqueue, &priv->beacon_update); | |
626 | } | |
627 | ||
b481de9c ZY |
628 | /* Handle notification from uCode that card's power state is changing |
629 | * due to software, hardware, or critical temperature RFKILL */ | |
5b9f8cd3 | 630 | static void iwl_rx_card_state_notif(struct iwl_priv *priv, |
a55360e4 | 631 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 632 | { |
db11d634 | 633 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
634 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
635 | unsigned long status = priv->status; | |
636 | ||
e1623446 | 637 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n", |
b481de9c ZY |
638 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
639 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
640 | ||
641 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
642 | RF_CARD_DISABLED)) { | |
643 | ||
3395f6e9 | 644 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
645 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
646 | ||
a8b50a0a MA |
647 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
648 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
b481de9c ZY |
649 | |
650 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 651 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 652 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
a8b50a0a | 653 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
b481de9c | 654 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
b481de9c | 655 | } |
39b73fb1 WYG |
656 | if (flags & RF_CARD_DISABLED) |
657 | iwl_tt_enter_ct_kill(priv); | |
b481de9c | 658 | } |
39b73fb1 WYG |
659 | if (!(flags & RF_CARD_DISABLED)) |
660 | iwl_tt_exit_ct_kill(priv); | |
b481de9c ZY |
661 | |
662 | if (flags & HW_CARD_DISABLED) | |
663 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
664 | else | |
665 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
666 | ||
667 | ||
b481de9c | 668 | if (!(flags & RXON_CARD_DISABLED)) |
2a421b91 | 669 | iwl_scan_cancel(priv); |
b481de9c ZY |
670 | |
671 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
672 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
673 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
674 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
675 | else |
676 | wake_up_interruptible(&priv->wait_command_queue); | |
677 | } | |
678 | ||
5b9f8cd3 | 679 | int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) |
e2e3c57b | 680 | { |
e2e3c57b | 681 | if (src == IWL_PWR_SRC_VAUX) { |
3fdb68de | 682 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) |
e2e3c57b TW |
683 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
684 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
685 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
686 | } else { | |
687 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
688 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
689 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
690 | } | |
691 | ||
a8b50a0a | 692 | return 0; |
e2e3c57b TW |
693 | } |
694 | ||
b481de9c | 695 | /** |
5b9f8cd3 | 696 | * iwl_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
697 | * |
698 | * Setup the RX handlers for each of the reply types sent from the uCode | |
699 | * to the host. | |
700 | * | |
701 | * This function chains into the hardware specific files for them to setup | |
702 | * any hardware specific handlers as well. | |
703 | */ | |
653fa4a0 | 704 | static void iwl_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 705 | { |
885ba202 | 706 | priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive; |
5b9f8cd3 EG |
707 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
708 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; | |
5b9f8cd3 | 709 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 710 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
5b9f8cd3 EG |
711 | iwl_rx_pm_debug_statistics_notif; |
712 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif; | |
b481de9c | 713 | |
9fbab516 BC |
714 | /* |
715 | * The same handler is used for both the REPLY to a discrete | |
716 | * statistics request from the host as well as for the periodic | |
717 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 718 | */ |
8f91aecb EG |
719 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics; |
720 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics; | |
2a421b91 | 721 | |
21c339bf | 722 | iwl_setup_spectrum_handlers(priv); |
2a421b91 TW |
723 | iwl_setup_rx_scan_handlers(priv); |
724 | ||
37a44211 | 725 | /* status change handler */ |
5b9f8cd3 | 726 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif; |
b481de9c | 727 | |
c1354754 TW |
728 | priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] = |
729 | iwl_rx_missed_beacon_notif; | |
37a44211 | 730 | /* Rx handlers */ |
1781a07f EG |
731 | priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy; |
732 | priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx; | |
653fa4a0 EG |
733 | /* block ack */ |
734 | priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba; | |
9fbab516 | 735 | /* Set up hardware specific Rx handlers */ |
d4789efe | 736 | priv->cfg->ops->lib->rx_handler_setup(priv); |
b481de9c ZY |
737 | } |
738 | ||
b481de9c | 739 | /** |
a55360e4 | 740 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
741 | * |
742 | * Uses the priv->rx_handlers callback function array to invoke | |
743 | * the appropriate handlers, including command responses, | |
744 | * frame-received notifications, and other notifications. | |
745 | */ | |
a55360e4 | 746 | void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 747 | { |
a55360e4 | 748 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 749 | struct iwl_rx_packet *pkt; |
a55360e4 | 750 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
751 | u32 r, i; |
752 | int reclaim; | |
753 | unsigned long flags; | |
5c0eef96 | 754 | u8 fill_rx = 0; |
d68ab680 | 755 | u32 count = 8; |
4752c93c | 756 | int total_empty; |
b481de9c | 757 | |
6440adb5 CB |
758 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
759 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 760 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
761 | i = rxq->read; |
762 | ||
763 | /* Rx interrupt, but nothing sent from uCode */ | |
764 | if (i == r) | |
e1623446 | 765 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c | 766 | |
4752c93c MA |
767 | /* calculate total frames need to be restock after handling RX */ |
768 | total_empty = r - priv->rxq.write_actual; | |
769 | if (total_empty < 0) | |
770 | total_empty += RX_QUEUE_SIZE; | |
771 | ||
772 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 MA |
773 | fill_rx = 1; |
774 | ||
b481de9c ZY |
775 | while (i != r) { |
776 | rxb = rxq->queue[i]; | |
777 | ||
9fbab516 | 778 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
779 | * then a bug has been introduced in the queue refilling |
780 | * routines -- catch it here */ | |
781 | BUG_ON(rxb == NULL); | |
782 | ||
783 | rxq->queue[i] = NULL; | |
784 | ||
df833b1d RC |
785 | pci_unmap_single(priv->pci_dev, rxb->real_dma_addr, |
786 | priv->hw_params.rx_buf_size + 256, | |
787 | PCI_DMA_FROMDEVICE); | |
db11d634 | 788 | pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
789 | |
790 | /* Reclaim a command buffer only if this packet is a response | |
791 | * to a (driver-originated) command. | |
792 | * If the packet (e.g. Rx frame) originated from uCode, | |
793 | * there is no command buffer to reclaim. | |
794 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
795 | * but apparently a few don't get set; catch them here. */ | |
796 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
797 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 798 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 799 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 800 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
801 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
802 | (pkt->hdr.cmd != REPLY_TX); | |
803 | ||
804 | /* Based on type of command response or notification, | |
805 | * handle those that need handling via function in | |
5b9f8cd3 | 806 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 807 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 808 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, |
f3d67999 | 809 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
b481de9c | 810 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
a83b9141 | 811 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
b481de9c ZY |
812 | } else { |
813 | /* No handling needed */ | |
e1623446 | 814 | IWL_DEBUG_RX(priv, |
b481de9c ZY |
815 | "r %d i %d No handler needed for %s, 0x%02x\n", |
816 | r, i, get_cmd_string(pkt->hdr.cmd), | |
817 | pkt->hdr.cmd); | |
818 | } | |
819 | ||
820 | if (reclaim) { | |
9fbab516 | 821 | /* Invoke any callbacks, transfer the skb to caller, and |
857485c0 | 822 | * fire off the (possibly) blocking iwl_send_cmd() |
b481de9c ZY |
823 | * as we reclaim the driver command queue */ |
824 | if (rxb && rxb->skb) | |
17b88929 | 825 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 826 | else |
39aadf8c | 827 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
828 | } |
829 | ||
830 | /* For now we just don't re-use anything. We can tweak this | |
831 | * later to try and re-use notification packets and SKBs that | |
832 | * fail to Rx correctly */ | |
833 | if (rxb->skb != NULL) { | |
834 | priv->alloc_rxb_skb--; | |
835 | dev_kfree_skb_any(rxb->skb); | |
836 | rxb->skb = NULL; | |
837 | } | |
838 | ||
b481de9c ZY |
839 | spin_lock_irqsave(&rxq->lock, flags); |
840 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
841 | spin_unlock_irqrestore(&rxq->lock, flags); | |
842 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
843 | /* If there are a lot of unused frames, |
844 | * restock the Rx queue so ucode wont assert. */ | |
845 | if (fill_rx) { | |
846 | count++; | |
847 | if (count >= 8) { | |
848 | priv->rxq.read = i; | |
4752c93c | 849 | iwl_rx_replenish_now(priv); |
5c0eef96 MA |
850 | count = 0; |
851 | } | |
852 | } | |
b481de9c ZY |
853 | } |
854 | ||
855 | /* Backtrack one entry */ | |
856 | priv->rxq.read = i; | |
4752c93c MA |
857 | if (fill_rx) |
858 | iwl_rx_replenish_now(priv); | |
859 | else | |
860 | iwl_rx_queue_restock(priv); | |
a55360e4 | 861 | } |
a55360e4 | 862 | |
0359facc MA |
863 | /* call this function to flush any scheduled tasklet */ |
864 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
865 | { | |
a96a27f9 | 866 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
867 | synchronize_irq(priv->pci_dev->irq); |
868 | tasklet_kill(&priv->irq_tasklet); | |
869 | } | |
870 | ||
ef850d7c | 871 | static void iwl_irq_tasklet_legacy(struct iwl_priv *priv) |
b481de9c ZY |
872 | { |
873 | u32 inta, handled = 0; | |
874 | u32 inta_fh; | |
875 | unsigned long flags; | |
0a6857e7 | 876 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
877 | u32 inta_mask; |
878 | #endif | |
879 | ||
880 | spin_lock_irqsave(&priv->lock, flags); | |
881 | ||
882 | /* Ack/clear/reset pending uCode interrupts. | |
883 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
884 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
885 | inta = iwl_read32(priv, CSR_INT); |
886 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
887 | |
888 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
889 | * Any new interrupts that happen after this, either while we're | |
890 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
891 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
892 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 893 | |
0a6857e7 | 894 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 895 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
9fbab516 | 896 | /* just for debug */ |
3395f6e9 | 897 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 898 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
899 | inta, inta_mask, inta_fh); |
900 | } | |
901 | #endif | |
902 | ||
903 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
904 | * atomic, make sure that inta covers all the interrupts that | |
905 | * we've discovered, even if FH interrupt came in just after | |
906 | * reading CSR_INT. */ | |
6f83eaa1 | 907 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 908 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 909 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
910 | inta |= CSR_INT_BIT_FH_TX; |
911 | ||
912 | /* Now service all interrupt bits discovered above. */ | |
913 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 914 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
b481de9c ZY |
915 | |
916 | /* Tell the device to stop sending interrupts */ | |
5b9f8cd3 | 917 | iwl_disable_interrupts(priv); |
b481de9c | 918 | |
a83b9141 | 919 | priv->isr_stats.hw++; |
5b9f8cd3 | 920 | iwl_irq_handle_error(priv); |
b481de9c ZY |
921 | |
922 | handled |= CSR_INT_BIT_HW_ERR; | |
923 | ||
924 | spin_unlock_irqrestore(&priv->lock, flags); | |
925 | ||
926 | return; | |
927 | } | |
928 | ||
0a6857e7 | 929 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 930 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
b481de9c | 931 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
a83b9141 | 932 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 933 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 934 | "the frame/frames.\n"); |
a83b9141 WYG |
935 | priv->isr_stats.sch++; |
936 | } | |
b481de9c ZY |
937 | |
938 | /* Alive notification via Rx interrupt will do the real work */ | |
a83b9141 | 939 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 940 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
a83b9141 WYG |
941 | priv->isr_stats.alive++; |
942 | } | |
b481de9c ZY |
943 | } |
944 | #endif | |
945 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 946 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 947 | |
9fbab516 | 948 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
949 | if (inta & CSR_INT_BIT_RF_KILL) { |
950 | int hw_rf_kill = 0; | |
3395f6e9 | 951 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
952 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
953 | hw_rf_kill = 1; | |
954 | ||
4c423a2b | 955 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
c3056065 | 956 | hw_rf_kill ? "disable radio" : "enable radio"); |
b481de9c | 957 | |
a83b9141 WYG |
958 | priv->isr_stats.rfkill++; |
959 | ||
a9efa652 | 960 | /* driver only loads ucode once setting the interface up. |
6cd0b1cb HS |
961 | * the driver allows loading the ucode even if the radio |
962 | * is killed. Hence update the killswitch state here. The | |
963 | * rfkill handler will care about restarting if needed. | |
a9efa652 | 964 | */ |
6cd0b1cb HS |
965 | if (!test_bit(STATUS_ALIVE, &priv->status)) { |
966 | if (hw_rf_kill) | |
967 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
968 | else | |
969 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 970 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
edb34228 | 971 | } |
b481de9c ZY |
972 | |
973 | handled |= CSR_INT_BIT_RF_KILL; | |
974 | } | |
975 | ||
9fbab516 | 976 | /* Chip got too hot and stopped itself */ |
b481de9c | 977 | if (inta & CSR_INT_BIT_CT_KILL) { |
15b1687c | 978 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); |
a83b9141 | 979 | priv->isr_stats.ctkill++; |
b481de9c ZY |
980 | handled |= CSR_INT_BIT_CT_KILL; |
981 | } | |
982 | ||
983 | /* Error detected by uCode */ | |
984 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
985 | IWL_ERR(priv, "Microcode SW error detected. " |
986 | " Restarting 0x%X.\n", inta); | |
a83b9141 WYG |
987 | priv->isr_stats.sw++; |
988 | priv->isr_stats.sw_err = inta; | |
5b9f8cd3 | 989 | iwl_irq_handle_error(priv); |
b481de9c ZY |
990 | handled |= CSR_INT_BIT_SW_ERR; |
991 | } | |
992 | ||
993 | /* uCode wakes up after power-down sleep */ | |
994 | if (inta & CSR_INT_BIT_WAKEUP) { | |
e1623446 | 995 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
a55360e4 | 996 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
babcebfa TW |
997 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); |
998 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
999 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1000 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1001 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1002 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c | 1003 | |
a83b9141 WYG |
1004 | priv->isr_stats.wakeup++; |
1005 | ||
b481de9c ZY |
1006 | handled |= CSR_INT_BIT_WAKEUP; |
1007 | } | |
1008 | ||
1009 | /* All uCode command responses, including Tx command responses, | |
1010 | * Rx "responses" (frame-received notification), and other | |
1011 | * notifications from uCode come through here*/ | |
1012 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
a55360e4 | 1013 | iwl_rx_handle(priv); |
a83b9141 | 1014 | priv->isr_stats.rx++; |
b481de9c ZY |
1015 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1016 | } | |
1017 | ||
1018 | if (inta & CSR_INT_BIT_FH_TX) { | |
e1623446 | 1019 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); |
a83b9141 | 1020 | priv->isr_stats.tx++; |
b481de9c | 1021 | handled |= CSR_INT_BIT_FH_TX; |
dbb983b7 RR |
1022 | /* FH finished to write, send event */ |
1023 | priv->ucode_write_complete = 1; | |
1024 | wake_up_interruptible(&priv->wait_command_queue); | |
b481de9c ZY |
1025 | } |
1026 | ||
a83b9141 | 1027 | if (inta & ~handled) { |
15b1687c | 1028 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
a83b9141 WYG |
1029 | priv->isr_stats.unhandled++; |
1030 | } | |
b481de9c | 1031 | |
40cefda9 | 1032 | if (inta & ~(priv->inta_mask)) { |
39aadf8c | 1033 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1034 | inta & ~priv->inta_mask); |
39aadf8c | 1035 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1036 | } |
1037 | ||
1038 | /* Re-enable all interrupts */ | |
0359facc MA |
1039 | /* only Re-enable if diabled by irq */ |
1040 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
5b9f8cd3 | 1041 | iwl_enable_interrupts(priv); |
b481de9c | 1042 | |
0a6857e7 | 1043 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1044 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
3395f6e9 TW |
1045 | inta = iwl_read32(priv, CSR_INT); |
1046 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1047 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1048 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1049 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1050 | } | |
1051 | #endif | |
1052 | spin_unlock_irqrestore(&priv->lock, flags); | |
1053 | } | |
1054 | ||
ef850d7c MA |
1055 | /* tasklet for iwlagn interrupt */ |
1056 | static void iwl_irq_tasklet(struct iwl_priv *priv) | |
1057 | { | |
1058 | u32 inta = 0; | |
1059 | u32 handled = 0; | |
1060 | unsigned long flags; | |
1061 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1062 | u32 inta_mask; | |
1063 | #endif | |
1064 | ||
1065 | spin_lock_irqsave(&priv->lock, flags); | |
1066 | ||
1067 | /* Ack/clear/reset pending uCode interrupts. | |
1068 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1069 | */ | |
1070 | iwl_write32(priv, CSR_INT, priv->inta); | |
1071 | ||
1072 | inta = priv->inta; | |
1073 | ||
1074 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1075 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
ef850d7c MA |
1076 | /* just for debug */ |
1077 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1078 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
1079 | inta, inta_mask); | |
1080 | } | |
1081 | #endif | |
1082 | /* saved interrupt in inta variable now we can reset priv->inta */ | |
1083 | priv->inta = 0; | |
1084 | ||
1085 | /* Now service all interrupt bits discovered above. */ | |
1086 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1087 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
ef850d7c MA |
1088 | |
1089 | /* Tell the device to stop sending interrupts */ | |
1090 | iwl_disable_interrupts(priv); | |
1091 | ||
1092 | priv->isr_stats.hw++; | |
1093 | iwl_irq_handle_error(priv); | |
1094 | ||
1095 | handled |= CSR_INT_BIT_HW_ERR; | |
1096 | ||
1097 | spin_unlock_irqrestore(&priv->lock, flags); | |
1098 | ||
1099 | return; | |
1100 | } | |
1101 | ||
1102 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1103 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
ef850d7c MA |
1104 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
1105 | if (inta & CSR_INT_BIT_SCD) { | |
1106 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
1107 | "the frame/frames.\n"); | |
1108 | priv->isr_stats.sch++; | |
1109 | } | |
1110 | ||
1111 | /* Alive notification via Rx interrupt will do the real work */ | |
1112 | if (inta & CSR_INT_BIT_ALIVE) { | |
1113 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
1114 | priv->isr_stats.alive++; | |
1115 | } | |
1116 | } | |
1117 | #endif | |
1118 | /* Safely ignore these bits for debug checks below */ | |
1119 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
1120 | ||
1121 | /* HW RF KILL switch toggled */ | |
1122 | if (inta & CSR_INT_BIT_RF_KILL) { | |
1123 | int hw_rf_kill = 0; | |
1124 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
1125 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
1126 | hw_rf_kill = 1; | |
1127 | ||
4c423a2b | 1128 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
ef850d7c MA |
1129 | hw_rf_kill ? "disable radio" : "enable radio"); |
1130 | ||
1131 | priv->isr_stats.rfkill++; | |
1132 | ||
1133 | /* driver only loads ucode once setting the interface up. | |
1134 | * the driver allows loading the ucode even if the radio | |
1135 | * is killed. Hence update the killswitch state here. The | |
1136 | * rfkill handler will care about restarting if needed. | |
1137 | */ | |
1138 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | |
1139 | if (hw_rf_kill) | |
1140 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1141 | else | |
1142 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1143 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
ef850d7c MA |
1144 | } |
1145 | ||
1146 | handled |= CSR_INT_BIT_RF_KILL; | |
1147 | } | |
1148 | ||
1149 | /* Chip got too hot and stopped itself */ | |
1150 | if (inta & CSR_INT_BIT_CT_KILL) { | |
1151 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
1152 | priv->isr_stats.ctkill++; | |
1153 | handled |= CSR_INT_BIT_CT_KILL; | |
1154 | } | |
1155 | ||
1156 | /* Error detected by uCode */ | |
1157 | if (inta & CSR_INT_BIT_SW_ERR) { | |
1158 | IWL_ERR(priv, "Microcode SW error detected. " | |
1159 | " Restarting 0x%X.\n", inta); | |
1160 | priv->isr_stats.sw++; | |
1161 | priv->isr_stats.sw_err = inta; | |
1162 | iwl_irq_handle_error(priv); | |
1163 | handled |= CSR_INT_BIT_SW_ERR; | |
1164 | } | |
1165 | ||
1166 | /* uCode wakes up after power-down sleep */ | |
1167 | if (inta & CSR_INT_BIT_WAKEUP) { | |
1168 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | |
1169 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | |
1170 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); | |
1171 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1172 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1173 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1174 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1175 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
1176 | ||
1177 | priv->isr_stats.wakeup++; | |
1178 | ||
1179 | handled |= CSR_INT_BIT_WAKEUP; | |
1180 | } | |
1181 | ||
1182 | /* All uCode command responses, including Tx command responses, | |
1183 | * Rx "responses" (frame-received notification), and other | |
1184 | * notifications from uCode come through here*/ | |
40cefda9 MA |
1185 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | |
1186 | CSR_INT_BIT_RX_PERIODIC)) { | |
ef850d7c | 1187 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); |
40cefda9 MA |
1188 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1189 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1190 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
1191 | CSR49_FH_INT_RX_MASK); | |
1192 | } | |
1193 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
1194 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1195 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
1196 | } | |
1197 | /* Sending RX interrupt require many steps to be done in the | |
1198 | * the device: | |
1199 | * 1- write interrupt to current index in ICT table. | |
1200 | * 2- dma RX frame. | |
1201 | * 3- update RX shared data to indicate last write index. | |
1202 | * 4- send interrupt. | |
1203 | * This could lead to RX race, driver could receive RX interrupt | |
1204 | * but the shared data changes does not reflect this. | |
1205 | * this could lead to RX race, RX periodic will solve this race | |
1206 | */ | |
1207 | iwl_write32(priv, CSR_INT_PERIODIC_REG, | |
1208 | CSR_INT_PERIODIC_DIS); | |
ef850d7c | 1209 | iwl_rx_handle(priv); |
40cefda9 MA |
1210 | /* Only set RX periodic if real RX is received. */ |
1211 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) | |
1212 | iwl_write32(priv, CSR_INT_PERIODIC_REG, | |
1213 | CSR_INT_PERIODIC_ENA); | |
1214 | ||
ef850d7c | 1215 | priv->isr_stats.rx++; |
ef850d7c MA |
1216 | } |
1217 | ||
1218 | if (inta & CSR_INT_BIT_FH_TX) { | |
1219 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); | |
1220 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); | |
1221 | priv->isr_stats.tx++; | |
1222 | handled |= CSR_INT_BIT_FH_TX; | |
1223 | /* FH finished to write, send event */ | |
1224 | priv->ucode_write_complete = 1; | |
1225 | wake_up_interruptible(&priv->wait_command_queue); | |
1226 | } | |
1227 | ||
1228 | if (inta & ~handled) { | |
1229 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
1230 | priv->isr_stats.unhandled++; | |
1231 | } | |
1232 | ||
40cefda9 | 1233 | if (inta & ~(priv->inta_mask)) { |
ef850d7c | 1234 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1235 | inta & ~priv->inta_mask); |
ef850d7c MA |
1236 | } |
1237 | ||
1238 | ||
1239 | /* Re-enable all interrupts */ | |
1240 | /* only Re-enable if diabled by irq */ | |
1241 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
1242 | iwl_enable_interrupts(priv); | |
1243 | ||
1244 | spin_unlock_irqrestore(&priv->lock, flags); | |
1245 | ||
1246 | } | |
1247 | ||
a83b9141 | 1248 | |
b481de9c ZY |
1249 | /****************************************************************************** |
1250 | * | |
1251 | * uCode download functions | |
1252 | * | |
1253 | ******************************************************************************/ | |
1254 | ||
5b9f8cd3 | 1255 | static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1256 | { |
98c92211 TW |
1257 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1258 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1259 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1260 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1261 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1262 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1263 | } |
1264 | ||
5b9f8cd3 | 1265 | static void iwl_nic_start(struct iwl_priv *priv) |
edcdf8b2 RR |
1266 | { |
1267 | /* Remove all resets to allow NIC to operate */ | |
1268 | iwl_write32(priv, CSR_RESET, 0); | |
1269 | } | |
1270 | ||
1271 | ||
b481de9c | 1272 | /** |
5b9f8cd3 | 1273 | * iwl_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
1274 | * |
1275 | * Copy into buffers for card to fetch via bus-mastering | |
1276 | */ | |
5b9f8cd3 | 1277 | static int iwl_read_ucode(struct iwl_priv *priv) |
b481de9c | 1278 | { |
cc0f555d | 1279 | struct iwl_ucode_header *ucode; |
a0987a8d | 1280 | int ret = -EINVAL, index; |
b481de9c | 1281 | const struct firmware *ucode_raw; |
a0987a8d RC |
1282 | const char *name_pre = priv->cfg->fw_name_pre; |
1283 | const unsigned int api_max = priv->cfg->ucode_api_max; | |
1284 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
1285 | char buf[25]; | |
b481de9c ZY |
1286 | u8 *src; |
1287 | size_t len; | |
cc0f555d JS |
1288 | u32 api_ver, build; |
1289 | u32 inst_size, data_size, init_size, init_data_size, boot_size; | |
abdc2d62 | 1290 | u16 eeprom_ver; |
b481de9c ZY |
1291 | |
1292 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
1293 | * request_firmware() is synchronous, file is in memory on return. */ | |
a0987a8d RC |
1294 | for (index = api_max; index >= api_min; index--) { |
1295 | sprintf(buf, "%s%d%s", name_pre, index, ".ucode"); | |
1296 | ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); | |
1297 | if (ret < 0) { | |
15b1687c | 1298 | IWL_ERR(priv, "%s firmware file req failed: %d\n", |
a0987a8d RC |
1299 | buf, ret); |
1300 | if (ret == -ENOENT) | |
1301 | continue; | |
1302 | else | |
1303 | goto error; | |
1304 | } else { | |
1305 | if (index < api_max) | |
15b1687c WT |
1306 | IWL_ERR(priv, "Loaded firmware %s, " |
1307 | "which is deprecated. " | |
1308 | "Please use API v%u instead.\n", | |
a0987a8d | 1309 | buf, api_max); |
15b1687c | 1310 | |
e1623446 | 1311 | IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n", |
a0987a8d RC |
1312 | buf, ucode_raw->size); |
1313 | break; | |
1314 | } | |
b481de9c ZY |
1315 | } |
1316 | ||
a0987a8d RC |
1317 | if (ret < 0) |
1318 | goto error; | |
b481de9c | 1319 | |
cc0f555d JS |
1320 | /* Make sure that we got at least the v1 header! */ |
1321 | if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) { | |
15b1687c | 1322 | IWL_ERR(priv, "File size way too small!\n"); |
90e759d1 | 1323 | ret = -EINVAL; |
b481de9c ZY |
1324 | goto err_release; |
1325 | } | |
1326 | ||
1327 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 1328 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 1329 | |
c02b3acd | 1330 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 1331 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
cc0f555d JS |
1332 | build = priv->cfg->ops->ucode->get_build(ucode, api_ver); |
1333 | inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver); | |
1334 | data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver); | |
1335 | init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver); | |
1336 | init_data_size = | |
1337 | priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver); | |
1338 | boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver); | |
1339 | src = priv->cfg->ops->ucode->get_data(ucode, api_ver); | |
b481de9c | 1340 | |
a0987a8d RC |
1341 | /* api_ver should match the api version forming part of the |
1342 | * firmware filename ... but we don't check for that and only rely | |
877d0310 | 1343 | * on the API version read from firmware header from here on forward */ |
a0987a8d RC |
1344 | |
1345 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 1346 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
1347 | "Driver supports v%u, firmware is v%u.\n", |
1348 | api_max, api_ver); | |
1349 | priv->ucode_ver = 0; | |
1350 | ret = -EINVAL; | |
1351 | goto err_release; | |
1352 | } | |
1353 | if (api_ver != api_max) | |
978785a3 | 1354 | IWL_ERR(priv, "Firmware has old API version. Expected v%u, " |
a0987a8d RC |
1355 | "got v%u. New firmware can be obtained " |
1356 | "from http://www.intellinuxwireless.org.\n", | |
1357 | api_max, api_ver); | |
1358 | ||
978785a3 TW |
1359 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
1360 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
1361 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1362 | IWL_UCODE_API(priv->ucode_ver), | |
1363 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
a0987a8d | 1364 | |
cc0f555d JS |
1365 | if (build) |
1366 | IWL_DEBUG_INFO(priv, "Build %u\n", build); | |
1367 | ||
abdc2d62 JS |
1368 | eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION); |
1369 | IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n", | |
1370 | (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) | |
1371 | ? "OTP" : "EEPROM", eeprom_ver); | |
1372 | ||
e1623446 | 1373 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
a0987a8d | 1374 | priv->ucode_ver); |
e1623446 | 1375 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n", |
b481de9c | 1376 | inst_size); |
e1623446 | 1377 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n", |
b481de9c | 1378 | data_size); |
e1623446 | 1379 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n", |
b481de9c | 1380 | init_size); |
e1623446 | 1381 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n", |
b481de9c | 1382 | init_data_size); |
e1623446 | 1383 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n", |
b481de9c ZY |
1384 | boot_size); |
1385 | ||
1386 | /* Verify size of file vs. image size info in file's header */ | |
cc0f555d JS |
1387 | if (ucode_raw->size != |
1388 | priv->cfg->ops->ucode->get_header_size(api_ver) + | |
b481de9c ZY |
1389 | inst_size + data_size + init_size + |
1390 | init_data_size + boot_size) { | |
1391 | ||
cc0f555d JS |
1392 | IWL_DEBUG_INFO(priv, |
1393 | "uCode file size %d does not match expected size\n", | |
1394 | (int)ucode_raw->size); | |
90e759d1 | 1395 | ret = -EINVAL; |
b481de9c ZY |
1396 | goto err_release; |
1397 | } | |
1398 | ||
1399 | /* Verify that uCode images will fit in card's SRAM */ | |
099b40b7 | 1400 | if (inst_size > priv->hw_params.max_inst_size) { |
e1623446 | 1401 | IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n", |
90e759d1 TW |
1402 | inst_size); |
1403 | ret = -EINVAL; | |
b481de9c ZY |
1404 | goto err_release; |
1405 | } | |
1406 | ||
099b40b7 | 1407 | if (data_size > priv->hw_params.max_data_size) { |
e1623446 | 1408 | IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n", |
90e759d1 TW |
1409 | data_size); |
1410 | ret = -EINVAL; | |
b481de9c ZY |
1411 | goto err_release; |
1412 | } | |
099b40b7 | 1413 | if (init_size > priv->hw_params.max_inst_size) { |
e1623446 TW |
1414 | IWL_INFO(priv, "uCode init instr len %d too large to fit in\n", |
1415 | init_size); | |
90e759d1 | 1416 | ret = -EINVAL; |
b481de9c ZY |
1417 | goto err_release; |
1418 | } | |
099b40b7 | 1419 | if (init_data_size > priv->hw_params.max_data_size) { |
e1623446 | 1420 | IWL_INFO(priv, "uCode init data len %d too large to fit in\n", |
90e759d1 TW |
1421 | init_data_size); |
1422 | ret = -EINVAL; | |
b481de9c ZY |
1423 | goto err_release; |
1424 | } | |
099b40b7 | 1425 | if (boot_size > priv->hw_params.max_bsm_size) { |
e1623446 TW |
1426 | IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n", |
1427 | boot_size); | |
90e759d1 | 1428 | ret = -EINVAL; |
b481de9c ZY |
1429 | goto err_release; |
1430 | } | |
1431 | ||
1432 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
1433 | ||
1434 | /* Runtime instructions and 2 copies of data: | |
1435 | * 1) unmodified from disk | |
1436 | * 2) backup cache for save/restore during power-downs */ | |
1437 | priv->ucode_code.len = inst_size; | |
98c92211 | 1438 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
1439 | |
1440 | priv->ucode_data.len = data_size; | |
98c92211 | 1441 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
1442 | |
1443 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 1444 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 1445 | |
1f304e4e ZY |
1446 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
1447 | !priv->ucode_data_backup.v_addr) | |
1448 | goto err_pci_alloc; | |
1449 | ||
b481de9c | 1450 | /* Initialization instructions and data */ |
90e759d1 TW |
1451 | if (init_size && init_data_size) { |
1452 | priv->ucode_init.len = init_size; | |
98c92211 | 1453 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
1454 | |
1455 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 1456 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
1457 | |
1458 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
1459 | goto err_pci_alloc; | |
1460 | } | |
b481de9c ZY |
1461 | |
1462 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
1463 | if (boot_size) { |
1464 | priv->ucode_boot.len = boot_size; | |
98c92211 | 1465 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 1466 | |
90e759d1 TW |
1467 | if (!priv->ucode_boot.v_addr) |
1468 | goto err_pci_alloc; | |
1469 | } | |
b481de9c ZY |
1470 | |
1471 | /* Copy images into buffers for card's bus-master reads ... */ | |
1472 | ||
1473 | /* Runtime instructions (first block of data in file) */ | |
cc0f555d | 1474 | len = inst_size; |
e1623446 | 1475 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c | 1476 | memcpy(priv->ucode_code.v_addr, src, len); |
cc0f555d JS |
1477 | src += len; |
1478 | ||
e1623446 | 1479 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
1480 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
1481 | ||
1482 | /* Runtime data (2nd block) | |
5b9f8cd3 | 1483 | * NOTE: Copy into backup buffer will be done in iwl_up() */ |
cc0f555d | 1484 | len = data_size; |
e1623446 | 1485 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
1486 | memcpy(priv->ucode_data.v_addr, src, len); |
1487 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
cc0f555d | 1488 | src += len; |
b481de9c ZY |
1489 | |
1490 | /* Initialization instructions (3rd block) */ | |
1491 | if (init_size) { | |
cc0f555d | 1492 | len = init_size; |
e1623446 | 1493 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n", |
90e759d1 | 1494 | len); |
b481de9c | 1495 | memcpy(priv->ucode_init.v_addr, src, len); |
cc0f555d | 1496 | src += len; |
b481de9c ZY |
1497 | } |
1498 | ||
1499 | /* Initialization data (4th block) */ | |
1500 | if (init_data_size) { | |
cc0f555d | 1501 | len = init_data_size; |
e1623446 | 1502 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n", |
90e759d1 | 1503 | len); |
b481de9c | 1504 | memcpy(priv->ucode_init_data.v_addr, src, len); |
cc0f555d | 1505 | src += len; |
b481de9c ZY |
1506 | } |
1507 | ||
1508 | /* Bootstrap instructions (5th block) */ | |
cc0f555d | 1509 | len = boot_size; |
e1623446 | 1510 | IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len); |
b481de9c ZY |
1511 | memcpy(priv->ucode_boot.v_addr, src, len); |
1512 | ||
1513 | /* We have our copies now, allow OS release its copies */ | |
1514 | release_firmware(ucode_raw); | |
1515 | return 0; | |
1516 | ||
1517 | err_pci_alloc: | |
15b1687c | 1518 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
90e759d1 | 1519 | ret = -ENOMEM; |
5b9f8cd3 | 1520 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
1521 | |
1522 | err_release: | |
1523 | release_firmware(ucode_raw); | |
1524 | ||
1525 | error: | |
90e759d1 | 1526 | return ret; |
b481de9c ZY |
1527 | } |
1528 | ||
b481de9c | 1529 | /** |
4a4a9e81 | 1530 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 1531 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 1532 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 1533 | */ |
4a4a9e81 | 1534 | static void iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 1535 | { |
57aab75a | 1536 | int ret = 0; |
b481de9c | 1537 | |
e1623446 | 1538 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
1539 | |
1540 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
1541 | /* We had an error bringing up the hardware, so take it | |
1542 | * all the way back down so we can try again */ | |
e1623446 | 1543 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
1544 | goto restart; |
1545 | } | |
1546 | ||
1547 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
1548 | * This is a paranoid check, because we would not have gotten the | |
1549 | * "runtime" alive if code weren't properly loaded. */ | |
b0692f2f | 1550 | if (iwl_verify_ucode(priv)) { |
b481de9c ZY |
1551 | /* Runtime instruction load was bad; |
1552 | * take it all the way back down so we can try again */ | |
e1623446 | 1553 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
1554 | goto restart; |
1555 | } | |
1556 | ||
c587de0b | 1557 | iwl_clear_stations_table(priv); |
57aab75a TW |
1558 | ret = priv->cfg->ops->lib->alive_notify(priv); |
1559 | if (ret) { | |
39aadf8c WT |
1560 | IWL_WARN(priv, |
1561 | "Could not complete ALIVE transition [ntf]: %d\n", ret); | |
b481de9c ZY |
1562 | goto restart; |
1563 | } | |
1564 | ||
5b9f8cd3 | 1565 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
1566 | set_bit(STATUS_ALIVE, &priv->status); |
1567 | ||
fee1247a | 1568 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
1569 | return; |
1570 | ||
36d6825b | 1571 | ieee80211_wake_queues(priv->hw); |
b481de9c ZY |
1572 | |
1573 | priv->active_rate = priv->rates_mask; | |
1574 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
1575 | ||
3109ece1 | 1576 | if (iwl_is_associated(priv)) { |
c1adf9fb GG |
1577 | struct iwl_rxon_cmd *active_rxon = |
1578 | (struct iwl_rxon_cmd *)&priv->active_rxon; | |
019fb97d MA |
1579 | /* apply any changes in staging */ |
1580 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
b481de9c ZY |
1581 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
1582 | } else { | |
1583 | /* Initialize our rx_config data */ | |
5b9f8cd3 | 1584 | iwl_connection_init_rx_config(priv, priv->iw_mode); |
45823531 AK |
1585 | |
1586 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
1587 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
1588 | ||
b481de9c ZY |
1589 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
1590 | } | |
1591 | ||
9fbab516 | 1592 | /* Configure Bluetooth device coexistence support */ |
5b9f8cd3 | 1593 | iwl_send_bt_config(priv); |
b481de9c | 1594 | |
4a4a9e81 TW |
1595 | iwl_reset_run_time_calib(priv); |
1596 | ||
b481de9c | 1597 | /* Configure the adapter for unassociated operation */ |
e0158e61 | 1598 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
1599 | |
1600 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 1601 | iwl_rf_kill_ct_config(priv); |
5a66926a | 1602 | |
fe00b5a5 RC |
1603 | iwl_leds_register(priv); |
1604 | ||
e1623446 | 1605 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 1606 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 1607 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 1608 | |
58d0f361 | 1609 | iwl_power_update_mode(priv, 1); |
c46fbefa | 1610 | |
ada17513 MA |
1611 | /* reassociate for ADHOC mode */ |
1612 | if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) { | |
1613 | struct sk_buff *beacon = ieee80211_beacon_get(priv->hw, | |
1614 | priv->vif); | |
1615 | if (beacon) | |
1616 | iwl_mac_beacon_update(priv->hw, beacon); | |
1617 | } | |
1618 | ||
1619 | ||
c46fbefa | 1620 | if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status)) |
5b9f8cd3 | 1621 | iwl_set_mode(priv, priv->iw_mode); |
c46fbefa | 1622 | |
b481de9c ZY |
1623 | return; |
1624 | ||
1625 | restart: | |
1626 | queue_work(priv->workqueue, &priv->restart); | |
1627 | } | |
1628 | ||
4e39317d | 1629 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 1630 | |
5b9f8cd3 | 1631 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
1632 | { |
1633 | unsigned long flags; | |
1634 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 1635 | |
e1623446 | 1636 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 1637 | |
b481de9c ZY |
1638 | if (!exit_pending) |
1639 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
1640 | ||
ab53d8af MA |
1641 | iwl_leds_unregister(priv); |
1642 | ||
c587de0b | 1643 | iwl_clear_stations_table(priv); |
b481de9c ZY |
1644 | |
1645 | /* Unblock any waiting calls */ | |
1646 | wake_up_interruptible_all(&priv->wait_command_queue); | |
1647 | ||
b481de9c ZY |
1648 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
1649 | * exiting the module */ | |
1650 | if (!exit_pending) | |
1651 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
1652 | ||
1653 | /* stop and reset the on-board processor */ | |
3395f6e9 | 1654 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
1655 | |
1656 | /* tell the device to stop sending interrupts */ | |
0359facc | 1657 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 1658 | iwl_disable_interrupts(priv); |
0359facc MA |
1659 | spin_unlock_irqrestore(&priv->lock, flags); |
1660 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
1661 | |
1662 | if (priv->mac80211_registered) | |
1663 | ieee80211_stop_queues(priv->hw); | |
1664 | ||
5b9f8cd3 | 1665 | /* If we have not previously called iwl_init() then |
a60e77e5 | 1666 | * clear all bits but the RF Kill bit and return */ |
fee1247a | 1667 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
1668 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
1669 | STATUS_RF_KILL_HW | | |
9788864e RC |
1670 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
1671 | STATUS_GEO_CONFIGURED | | |
052ec3f1 MA |
1672 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
1673 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
1674 | goto exit; |
1675 | } | |
1676 | ||
6da3a13e | 1677 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 1678 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
1679 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
1680 | STATUS_RF_KILL_HW | | |
9788864e RC |
1681 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
1682 | STATUS_GEO_CONFIGURED | | |
b481de9c | 1683 | test_bit(STATUS_FW_ERROR, &priv->status) << |
052ec3f1 MA |
1684 | STATUS_FW_ERROR | |
1685 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
1686 | STATUS_EXIT_PENDING; | |
b481de9c | 1687 | |
ef850d7c MA |
1688 | /* device going down, Stop using ICT table */ |
1689 | iwl_disable_ict(priv); | |
b481de9c | 1690 | spin_lock_irqsave(&priv->lock, flags); |
3395f6e9 | 1691 | iwl_clear_bit(priv, CSR_GP_CNTRL, |
9fbab516 | 1692 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
1693 | spin_unlock_irqrestore(&priv->lock, flags); |
1694 | ||
da1bc453 | 1695 | iwl_txq_ctx_stop(priv); |
b3bbacb7 | 1696 | iwl_rxq_stop(priv); |
b481de9c | 1697 | |
a8b50a0a MA |
1698 | iwl_write_prph(priv, APMG_CLK_DIS_REG, |
1699 | APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
1700 | |
1701 | udelay(5); | |
1702 | ||
7f066108 | 1703 | /* FIXME: apm_ops.suspend(priv) */ |
6da3a13e | 1704 | if (exit_pending) |
d535311e GG |
1705 | priv->cfg->ops->lib->apm_ops.stop(priv); |
1706 | else | |
1707 | priv->cfg->ops->lib->apm_ops.reset(priv); | |
b481de9c | 1708 | exit: |
885ba202 | 1709 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
1710 | |
1711 | if (priv->ibss_beacon) | |
1712 | dev_kfree_skb(priv->ibss_beacon); | |
1713 | priv->ibss_beacon = NULL; | |
1714 | ||
1715 | /* clear out any free frames */ | |
fcab423d | 1716 | iwl_clear_free_frames(priv); |
b481de9c ZY |
1717 | } |
1718 | ||
5b9f8cd3 | 1719 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
1720 | { |
1721 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 1722 | __iwl_down(priv); |
b481de9c | 1723 | mutex_unlock(&priv->mutex); |
b24d22b1 | 1724 | |
4e39317d | 1725 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
1726 | } |
1727 | ||
086ed117 MA |
1728 | #define HW_READY_TIMEOUT (50) |
1729 | ||
1730 | static int iwl_set_hw_ready(struct iwl_priv *priv) | |
1731 | { | |
1732 | int ret = 0; | |
1733 | ||
1734 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
1735 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
1736 | ||
1737 | /* See if we got it */ | |
1738 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
1739 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
1740 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
1741 | HW_READY_TIMEOUT); | |
1742 | if (ret != -ETIMEDOUT) | |
1743 | priv->hw_ready = true; | |
1744 | else | |
1745 | priv->hw_ready = false; | |
1746 | ||
1747 | IWL_DEBUG_INFO(priv, "hardware %s\n", | |
1748 | (priv->hw_ready == 1) ? "ready" : "not ready"); | |
1749 | return ret; | |
1750 | } | |
1751 | ||
1752 | static int iwl_prepare_card_hw(struct iwl_priv *priv) | |
1753 | { | |
1754 | int ret = 0; | |
1755 | ||
1756 | IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n"); | |
1757 | ||
3354a0f6 MA |
1758 | ret = iwl_set_hw_ready(priv); |
1759 | if (priv->hw_ready) | |
1760 | return ret; | |
1761 | ||
1762 | /* If HW is not ready, prepare the conditions to check again */ | |
086ed117 MA |
1763 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
1764 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
1765 | ||
1766 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
1767 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
1768 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
1769 | ||
3354a0f6 | 1770 | /* HW should be ready by now, check again. */ |
086ed117 MA |
1771 | if (ret != -ETIMEDOUT) |
1772 | iwl_set_hw_ready(priv); | |
1773 | ||
1774 | return ret; | |
1775 | } | |
1776 | ||
b481de9c ZY |
1777 | #define MAX_HW_RESTARTS 5 |
1778 | ||
5b9f8cd3 | 1779 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 1780 | { |
57aab75a TW |
1781 | int i; |
1782 | int ret; | |
b481de9c ZY |
1783 | |
1784 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 1785 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
1786 | return -EIO; |
1787 | } | |
1788 | ||
e903fbd4 | 1789 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 1790 | IWL_ERR(priv, "ucode not available for device bringup\n"); |
e903fbd4 RC |
1791 | return -EIO; |
1792 | } | |
1793 | ||
086ed117 MA |
1794 | iwl_prepare_card_hw(priv); |
1795 | ||
1796 | if (!priv->hw_ready) { | |
1797 | IWL_WARN(priv, "Exit HW not ready\n"); | |
1798 | return -EIO; | |
1799 | } | |
1800 | ||
e655b9f0 | 1801 | /* If platform's RF_KILL switch is NOT set to KILL */ |
c1842d61 | 1802 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
e655b9f0 | 1803 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 1804 | else |
e655b9f0 | 1805 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 1806 | |
c1842d61 | 1807 | if (iwl_is_rfkill(priv)) { |
a60e77e5 JB |
1808 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, true); |
1809 | ||
5b9f8cd3 | 1810 | iwl_enable_interrupts(priv); |
a60e77e5 | 1811 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
c1842d61 | 1812 | return 0; |
b481de9c ZY |
1813 | } |
1814 | ||
3395f6e9 | 1815 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 1816 | |
1053d35f | 1817 | ret = iwl_hw_nic_init(priv); |
57aab75a | 1818 | if (ret) { |
15b1687c | 1819 | IWL_ERR(priv, "Unable to init nic\n"); |
57aab75a | 1820 | return ret; |
b481de9c ZY |
1821 | } |
1822 | ||
1823 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
1824 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1825 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
1826 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
1827 | ||
1828 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 1829 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
5b9f8cd3 | 1830 | iwl_enable_interrupts(priv); |
b481de9c ZY |
1831 | |
1832 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
1833 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1834 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
1835 | |
1836 | /* Copy original ucode data image from disk into backup cache. | |
1837 | * This will be used to initialize the on-board processor's | |
1838 | * data SRAM for a clean start when the runtime program first loads. */ | |
1839 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 1840 | priv->ucode_data.len); |
b481de9c | 1841 | |
b481de9c ZY |
1842 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
1843 | ||
c587de0b | 1844 | iwl_clear_stations_table(priv); |
b481de9c ZY |
1845 | |
1846 | /* load bootstrap state machine, | |
1847 | * load bootstrap program into processor's memory, | |
1848 | * prepare to load the "initialize" uCode */ | |
57aab75a | 1849 | ret = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c | 1850 | |
57aab75a | 1851 | if (ret) { |
15b1687c WT |
1852 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", |
1853 | ret); | |
b481de9c ZY |
1854 | continue; |
1855 | } | |
1856 | ||
1857 | /* start card; "initialize" will load runtime ucode */ | |
5b9f8cd3 | 1858 | iwl_nic_start(priv); |
b481de9c | 1859 | |
e1623446 | 1860 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
1861 | |
1862 | return 0; | |
1863 | } | |
1864 | ||
1865 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5b9f8cd3 | 1866 | __iwl_down(priv); |
64e72c3e | 1867 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
1868 | |
1869 | /* tried to restart and config the device for as long as our | |
1870 | * patience could withstand */ | |
15b1687c | 1871 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
1872 | return -EIO; |
1873 | } | |
1874 | ||
1875 | ||
1876 | /***************************************************************************** | |
1877 | * | |
1878 | * Workqueue callbacks | |
1879 | * | |
1880 | *****************************************************************************/ | |
1881 | ||
4a4a9e81 | 1882 | static void iwl_bg_init_alive_start(struct work_struct *data) |
b481de9c | 1883 | { |
c79dd5b5 TW |
1884 | struct iwl_priv *priv = |
1885 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
1886 | |
1887 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1888 | return; | |
1889 | ||
1890 | mutex_lock(&priv->mutex); | |
f3ccc08c | 1891 | priv->cfg->ops->lib->init_alive_start(priv); |
b481de9c ZY |
1892 | mutex_unlock(&priv->mutex); |
1893 | } | |
1894 | ||
4a4a9e81 | 1895 | static void iwl_bg_alive_start(struct work_struct *data) |
b481de9c | 1896 | { |
c79dd5b5 TW |
1897 | struct iwl_priv *priv = |
1898 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
1899 | |
1900 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1901 | return; | |
1902 | ||
258c44a0 MA |
1903 | /* enable dram interrupt */ |
1904 | iwl_reset_ict(priv); | |
1905 | ||
b481de9c | 1906 | mutex_lock(&priv->mutex); |
4a4a9e81 | 1907 | iwl_alive_start(priv); |
b481de9c ZY |
1908 | mutex_unlock(&priv->mutex); |
1909 | } | |
1910 | ||
16e727e8 EG |
1911 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
1912 | { | |
1913 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
1914 | run_time_calib_work); | |
1915 | ||
1916 | mutex_lock(&priv->mutex); | |
1917 | ||
1918 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
1919 | test_bit(STATUS_SCANNING, &priv->status)) { | |
1920 | mutex_unlock(&priv->mutex); | |
1921 | return; | |
1922 | } | |
1923 | ||
1924 | if (priv->start_calib) { | |
1925 | iwl_chain_noise_calibration(priv, &priv->statistics); | |
1926 | ||
1927 | iwl_sensitivity_calibration(priv, &priv->statistics); | |
1928 | } | |
1929 | ||
1930 | mutex_unlock(&priv->mutex); | |
1931 | return; | |
1932 | } | |
1933 | ||
5b9f8cd3 | 1934 | static void iwl_bg_up(struct work_struct *data) |
b481de9c | 1935 | { |
c79dd5b5 | 1936 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
1937 | |
1938 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1939 | return; | |
1940 | ||
1941 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 1942 | __iwl_up(priv); |
b481de9c ZY |
1943 | mutex_unlock(&priv->mutex); |
1944 | } | |
1945 | ||
5b9f8cd3 | 1946 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 1947 | { |
c79dd5b5 | 1948 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
1949 | |
1950 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1951 | return; | |
1952 | ||
19cc1087 JB |
1953 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
1954 | mutex_lock(&priv->mutex); | |
1955 | priv->vif = NULL; | |
1956 | priv->is_open = 0; | |
1957 | mutex_unlock(&priv->mutex); | |
1958 | iwl_down(priv); | |
1959 | ieee80211_restart_hw(priv->hw); | |
1960 | } else { | |
1961 | iwl_down(priv); | |
1962 | queue_work(priv->workqueue, &priv->up); | |
1963 | } | |
b481de9c ZY |
1964 | } |
1965 | ||
5b9f8cd3 | 1966 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 1967 | { |
c79dd5b5 TW |
1968 | struct iwl_priv *priv = |
1969 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
1970 | |
1971 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1972 | return; | |
1973 | ||
1974 | mutex_lock(&priv->mutex); | |
a55360e4 | 1975 | iwl_rx_replenish(priv); |
b481de9c ZY |
1976 | mutex_unlock(&priv->mutex); |
1977 | } | |
1978 | ||
7878a5a4 MA |
1979 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
1980 | ||
5bbe233b | 1981 | void iwl_post_associate(struct iwl_priv *priv) |
b481de9c | 1982 | { |
b481de9c | 1983 | struct ieee80211_conf *conf = NULL; |
857485c0 | 1984 | int ret = 0; |
1ff50bda | 1985 | unsigned long flags; |
b481de9c | 1986 | |
05c914fe | 1987 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
15b1687c | 1988 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
1989 | return; |
1990 | } | |
1991 | ||
e1623446 | 1992 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
e174961c | 1993 | priv->assoc_id, priv->active_rxon.bssid_addr); |
b481de9c ZY |
1994 | |
1995 | ||
1996 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1997 | return; | |
1998 | ||
b481de9c | 1999 | |
508e32e1 | 2000 | if (!priv->vif || !priv->is_open) |
948c171c | 2001 | return; |
508e32e1 | 2002 | |
2a421b91 | 2003 | iwl_scan_cancel_timeout(priv, 200); |
052c4b9f | 2004 | |
b481de9c ZY |
2005 | conf = ieee80211_get_hw_conf(priv->hw); |
2006 | ||
2007 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2008 | iwlcore_commit_rxon(priv); |
b481de9c | 2009 | |
3195c1f3 | 2010 | iwl_setup_rxon_timing(priv); |
857485c0 | 2011 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2012 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2013 | if (ret) |
39aadf8c | 2014 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2015 | "Attempting to continue.\n"); |
2016 | ||
2017 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
2018 | ||
42eb7c64 | 2019 | iwl_set_rxon_ht(priv, &priv->current_ht_config); |
4f85f5b3 | 2020 | |
45823531 AK |
2021 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
2022 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
2023 | ||
b481de9c ZY |
2024 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
2025 | ||
e1623446 | 2026 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
b481de9c ZY |
2027 | priv->assoc_id, priv->beacon_int); |
2028 | ||
2029 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2030 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2031 | else | |
2032 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2033 | ||
2034 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2035 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2036 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2037 | else | |
2038 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2039 | ||
05c914fe | 2040 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2041 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
2042 | ||
2043 | } | |
2044 | ||
e0158e61 | 2045 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2046 | |
2047 | switch (priv->iw_mode) { | |
05c914fe | 2048 | case NL80211_IFTYPE_STATION: |
b481de9c ZY |
2049 | break; |
2050 | ||
05c914fe | 2051 | case NL80211_IFTYPE_ADHOC: |
b481de9c | 2052 | |
c46fbefa AK |
2053 | /* assume default assoc id */ |
2054 | priv->assoc_id = 1; | |
b481de9c | 2055 | |
4f40e4d9 | 2056 | iwl_rxon_add_station(priv, priv->bssid, 0); |
5b9f8cd3 | 2057 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2058 | |
2059 | break; | |
2060 | ||
2061 | default: | |
15b1687c | 2062 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3ac7f146 | 2063 | __func__, priv->iw_mode); |
b481de9c ZY |
2064 | break; |
2065 | } | |
2066 | ||
05c914fe | 2067 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2068 | priv->assoc_station_added = 1; |
2069 | ||
1ff50bda EG |
2070 | spin_lock_irqsave(&priv->lock, flags); |
2071 | iwl_activate_qos(priv, 0); | |
2072 | spin_unlock_irqrestore(&priv->lock, flags); | |
292ae174 | 2073 | |
04816448 GE |
2074 | /* the chain noise calibration will enabled PM upon completion |
2075 | * If chain noise has already been run, then we need to enable | |
2076 | * power management here */ | |
2077 | if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE) | |
7af2c460 | 2078 | iwl_power_update_mode(priv, 0); |
c90a74ba EG |
2079 | |
2080 | /* Enable Rx differential gain and sensitivity calibrations */ | |
2081 | iwl_chain_noise_reset(priv); | |
2082 | priv->start_calib = 1; | |
2083 | ||
508e32e1 RC |
2084 | } |
2085 | ||
b481de9c ZY |
2086 | /***************************************************************************** |
2087 | * | |
2088 | * mac80211 entry point functions | |
2089 | * | |
2090 | *****************************************************************************/ | |
2091 | ||
154b25ce | 2092 | #define UCODE_READY_TIMEOUT (4 * HZ) |
5a66926a | 2093 | |
5b9f8cd3 | 2094 | static int iwl_mac_start(struct ieee80211_hw *hw) |
b481de9c | 2095 | { |
c79dd5b5 | 2096 | struct iwl_priv *priv = hw->priv; |
5a66926a | 2097 | int ret; |
b481de9c | 2098 | |
e1623446 | 2099 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
2100 | |
2101 | /* we should be verifying the device is ready to be opened */ | |
2102 | mutex_lock(&priv->mutex); | |
2103 | ||
5a66926a ZY |
2104 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... |
2105 | * ucode filename and max sizes are card-specific. */ | |
b481de9c | 2106 | |
5a66926a | 2107 | if (!priv->ucode_code.len) { |
5b9f8cd3 | 2108 | ret = iwl_read_ucode(priv); |
5a66926a | 2109 | if (ret) { |
15b1687c | 2110 | IWL_ERR(priv, "Could not read microcode: %d\n", ret); |
5a66926a | 2111 | mutex_unlock(&priv->mutex); |
6cd0b1cb | 2112 | return ret; |
5a66926a ZY |
2113 | } |
2114 | } | |
b481de9c | 2115 | |
5b9f8cd3 | 2116 | ret = __iwl_up(priv); |
5a66926a | 2117 | |
b481de9c | 2118 | mutex_unlock(&priv->mutex); |
5a66926a | 2119 | |
e655b9f0 | 2120 | if (ret) |
6cd0b1cb | 2121 | return ret; |
e655b9f0 | 2122 | |
c1842d61 TW |
2123 | if (iwl_is_rfkill(priv)) |
2124 | goto out; | |
2125 | ||
e1623446 | 2126 | IWL_DEBUG_INFO(priv, "Start UP work done.\n"); |
e655b9f0 | 2127 | |
fe9b6b72 | 2128 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from |
5a66926a | 2129 | * mac80211 will not be run successfully. */ |
154b25ce EG |
2130 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
2131 | test_bit(STATUS_READY, &priv->status), | |
2132 | UCODE_READY_TIMEOUT); | |
2133 | if (!ret) { | |
2134 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c | 2135 | IWL_ERR(priv, "START_ALIVE timeout after %dms.\n", |
154b25ce | 2136 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
6cd0b1cb | 2137 | return -ETIMEDOUT; |
5a66926a | 2138 | } |
fe9b6b72 | 2139 | } |
0a078ffa | 2140 | |
c1842d61 | 2141 | out: |
0a078ffa | 2142 | priv->is_open = 1; |
e1623446 | 2143 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2144 | return 0; |
2145 | } | |
2146 | ||
5b9f8cd3 | 2147 | static void iwl_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 2148 | { |
c79dd5b5 | 2149 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2150 | |
e1623446 | 2151 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
948c171c | 2152 | |
19cc1087 | 2153 | if (!priv->is_open) |
e655b9f0 | 2154 | return; |
e655b9f0 | 2155 | |
b481de9c | 2156 | priv->is_open = 0; |
5a66926a | 2157 | |
fee1247a | 2158 | if (iwl_is_ready_rf(priv)) { |
e655b9f0 ZY |
2159 | /* stop mac, cancel any scan request and clear |
2160 | * RXON_FILTER_ASSOC_MSK BIT | |
2161 | */ | |
5a66926a | 2162 | mutex_lock(&priv->mutex); |
2a421b91 | 2163 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 2164 | mutex_unlock(&priv->mutex); |
fde3571f MA |
2165 | } |
2166 | ||
5b9f8cd3 | 2167 | iwl_down(priv); |
5a66926a ZY |
2168 | |
2169 | flush_workqueue(priv->workqueue); | |
6cd0b1cb HS |
2170 | |
2171 | /* enable interrupts again in order to receive rfkill changes */ | |
2172 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | |
2173 | iwl_enable_interrupts(priv); | |
948c171c | 2174 | |
e1623446 | 2175 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2176 | } |
2177 | ||
5b9f8cd3 | 2178 | static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 2179 | { |
c79dd5b5 | 2180 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2181 | |
e1623446 | 2182 | IWL_DEBUG_MACDUMP(priv, "enter\n"); |
b481de9c | 2183 | |
e1623446 | 2184 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 2185 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 2186 | |
e039fa4a | 2187 | if (iwl_tx_skb(priv, skb)) |
b481de9c ZY |
2188 | dev_kfree_skb_any(skb); |
2189 | ||
e1623446 | 2190 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
637f8837 | 2191 | return NETDEV_TX_OK; |
b481de9c ZY |
2192 | } |
2193 | ||
60690a6a | 2194 | void iwl_config_ap(struct iwl_priv *priv) |
b481de9c | 2195 | { |
857485c0 | 2196 | int ret = 0; |
1ff50bda | 2197 | unsigned long flags; |
b481de9c | 2198 | |
d986bcd1 | 2199 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
2200 | return; |
2201 | ||
2202 | /* The following should be done only at AP bring up */ | |
3195c1f3 | 2203 | if (!iwl_is_associated(priv)) { |
b481de9c ZY |
2204 | |
2205 | /* RXON - unassoc (to set timing command) */ | |
2206 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2207 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2208 | |
2209 | /* RXON Timing */ | |
3195c1f3 | 2210 | iwl_setup_rxon_timing(priv); |
857485c0 | 2211 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2212 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2213 | if (ret) |
39aadf8c | 2214 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2215 | "Attempting to continue.\n"); |
2216 | ||
45823531 AK |
2217 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
2218 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
b481de9c ZY |
2219 | |
2220 | /* FIXME: what should be the assoc_id for AP? */ | |
2221 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
2222 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2223 | priv->staging_rxon.flags |= | |
2224 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
2225 | else | |
2226 | priv->staging_rxon.flags &= | |
2227 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2228 | ||
2229 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2230 | if (priv->assoc_capability & | |
2231 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2232 | priv->staging_rxon.flags |= | |
2233 | RXON_FLG_SHORT_SLOT_MSK; | |
2234 | else | |
2235 | priv->staging_rxon.flags &= | |
2236 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2237 | ||
05c914fe | 2238 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2239 | priv->staging_rxon.flags &= |
2240 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2241 | } | |
2242 | /* restore RXON assoc */ | |
2243 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2244 | iwlcore_commit_rxon(priv); |
1ff50bda EG |
2245 | spin_lock_irqsave(&priv->lock, flags); |
2246 | iwl_activate_qos(priv, 1); | |
2247 | spin_unlock_irqrestore(&priv->lock, flags); | |
4f40e4d9 | 2248 | iwl_rxon_add_station(priv, iwl_bcast_addr, 0); |
e1493deb | 2249 | } |
5b9f8cd3 | 2250 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2251 | |
2252 | /* FIXME - we need to add code here to detect a totally new | |
2253 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
2254 | * clear sta table, add BCAST sta... */ | |
2255 | } | |
2256 | ||
5b9f8cd3 | 2257 | static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw, |
ab885f8c EG |
2258 | struct ieee80211_key_conf *keyconf, const u8 *addr, |
2259 | u32 iv32, u16 *phase1key) | |
2260 | { | |
ab885f8c | 2261 | |
9f58671e | 2262 | struct iwl_priv *priv = hw->priv; |
e1623446 | 2263 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
ab885f8c | 2264 | |
9f58671e | 2265 | iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key); |
ab885f8c | 2266 | |
e1623446 | 2267 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
ab885f8c EG |
2268 | } |
2269 | ||
5b9f8cd3 | 2270 | static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
2271 | struct ieee80211_vif *vif, |
2272 | struct ieee80211_sta *sta, | |
b481de9c ZY |
2273 | struct ieee80211_key_conf *key) |
2274 | { | |
c79dd5b5 | 2275 | struct iwl_priv *priv = hw->priv; |
42986796 WT |
2276 | const u8 *addr; |
2277 | int ret; | |
2278 | u8 sta_id; | |
2279 | bool is_default_wep_key = false; | |
b481de9c | 2280 | |
e1623446 | 2281 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 2282 | |
90e8e424 | 2283 | if (priv->cfg->mod_params->sw_crypto) { |
e1623446 | 2284 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
2285 | return -EOPNOTSUPP; |
2286 | } | |
42986796 | 2287 | addr = sta ? sta->addr : iwl_bcast_addr; |
c587de0b | 2288 | sta_id = iwl_find_station(priv, addr); |
6974e363 | 2289 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 2290 | IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n", |
e174961c | 2291 | addr); |
6974e363 | 2292 | return -EINVAL; |
b481de9c | 2293 | |
deb09c43 | 2294 | } |
b481de9c | 2295 | |
6974e363 | 2296 | mutex_lock(&priv->mutex); |
2a421b91 | 2297 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 EG |
2298 | mutex_unlock(&priv->mutex); |
2299 | ||
2300 | /* If we are getting WEP group key and we didn't receive any key mapping | |
2301 | * so far, we are in legacy wep mode (group key only), otherwise we are | |
2302 | * in 1X mode. | |
2303 | * In legacy wep mode, we use another host command to the uCode */ | |
5425e490 | 2304 | if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id && |
05c914fe | 2305 | priv->iw_mode != NL80211_IFTYPE_AP) { |
6974e363 EG |
2306 | if (cmd == SET_KEY) |
2307 | is_default_wep_key = !priv->key_mapping_key; | |
2308 | else | |
ccc038ab EG |
2309 | is_default_wep_key = |
2310 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 2311 | } |
052c4b9f | 2312 | |
b481de9c | 2313 | switch (cmd) { |
deb09c43 | 2314 | case SET_KEY: |
6974e363 EG |
2315 | if (is_default_wep_key) |
2316 | ret = iwl_set_default_wep_key(priv, key); | |
deb09c43 | 2317 | else |
7480513f | 2318 | ret = iwl_set_dynamic_key(priv, key, sta_id); |
deb09c43 | 2319 | |
e1623446 | 2320 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); |
b481de9c ZY |
2321 | break; |
2322 | case DISABLE_KEY: | |
6974e363 EG |
2323 | if (is_default_wep_key) |
2324 | ret = iwl_remove_default_wep_key(priv, key); | |
deb09c43 | 2325 | else |
3ec47732 | 2326 | ret = iwl_remove_dynamic_key(priv, key, sta_id); |
deb09c43 | 2327 | |
e1623446 | 2328 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); |
b481de9c ZY |
2329 | break; |
2330 | default: | |
deb09c43 | 2331 | ret = -EINVAL; |
b481de9c ZY |
2332 | } |
2333 | ||
e1623446 | 2334 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 2335 | |
deb09c43 | 2336 | return ret; |
b481de9c ZY |
2337 | } |
2338 | ||
5b9f8cd3 | 2339 | static int iwl_mac_ampdu_action(struct ieee80211_hw *hw, |
d783b061 | 2340 | enum ieee80211_ampdu_mlme_action action, |
17741cdc | 2341 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) |
d783b061 TW |
2342 | { |
2343 | struct iwl_priv *priv = hw->priv; | |
5c2207c6 | 2344 | int ret; |
d783b061 | 2345 | |
e1623446 | 2346 | IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", |
e174961c | 2347 | sta->addr, tid); |
d783b061 TW |
2348 | |
2349 | if (!(priv->cfg->sku & IWL_SKU_N)) | |
2350 | return -EACCES; | |
2351 | ||
2352 | switch (action) { | |
2353 | case IEEE80211_AMPDU_RX_START: | |
e1623446 | 2354 | IWL_DEBUG_HT(priv, "start Rx\n"); |
9f58671e | 2355 | return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn); |
d783b061 | 2356 | case IEEE80211_AMPDU_RX_STOP: |
e1623446 | 2357 | IWL_DEBUG_HT(priv, "stop Rx\n"); |
5c2207c6 WYG |
2358 | ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid); |
2359 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2360 | return 0; | |
2361 | else | |
2362 | return ret; | |
d783b061 | 2363 | case IEEE80211_AMPDU_TX_START: |
e1623446 | 2364 | IWL_DEBUG_HT(priv, "start Tx\n"); |
17741cdc | 2365 | return iwl_tx_agg_start(priv, sta->addr, tid, ssn); |
d783b061 | 2366 | case IEEE80211_AMPDU_TX_STOP: |
e1623446 | 2367 | IWL_DEBUG_HT(priv, "stop Tx\n"); |
5c2207c6 WYG |
2368 | ret = iwl_tx_agg_stop(priv, sta->addr, tid); |
2369 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2370 | return 0; | |
2371 | else | |
2372 | return ret; | |
d783b061 | 2373 | default: |
e1623446 | 2374 | IWL_DEBUG_HT(priv, "unknown\n"); |
d783b061 TW |
2375 | return -EINVAL; |
2376 | break; | |
2377 | } | |
2378 | return 0; | |
2379 | } | |
9f58671e | 2380 | |
5b9f8cd3 | 2381 | static int iwl_mac_get_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
2382 | struct ieee80211_low_level_stats *stats) |
2383 | { | |
bf403db8 EK |
2384 | struct iwl_priv *priv = hw->priv; |
2385 | ||
2386 | priv = hw->priv; | |
e1623446 TW |
2387 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
2388 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
b481de9c ZY |
2389 | |
2390 | return 0; | |
2391 | } | |
2392 | ||
b481de9c ZY |
2393 | /***************************************************************************** |
2394 | * | |
2395 | * sysfs attributes | |
2396 | * | |
2397 | *****************************************************************************/ | |
2398 | ||
0a6857e7 | 2399 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
2400 | |
2401 | /* | |
2402 | * The following adds a new attribute to the sysfs representation | |
c3a739fa | 2403 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) |
b481de9c ZY |
2404 | * used for controlling the debug level. |
2405 | * | |
2406 | * See the level definitions in iwl for details. | |
a562a9dd | 2407 | * |
3d816c77 RC |
2408 | * The debug_level being managed using sysfs below is a per device debug |
2409 | * level that is used instead of the global debug level if it (the per | |
2410 | * device debug level) is set. | |
b481de9c | 2411 | */ |
8cf769c6 EK |
2412 | static ssize_t show_debug_level(struct device *d, |
2413 | struct device_attribute *attr, char *buf) | |
b481de9c | 2414 | { |
3d816c77 RC |
2415 | struct iwl_priv *priv = dev_get_drvdata(d); |
2416 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
b481de9c | 2417 | } |
8cf769c6 EK |
2418 | static ssize_t store_debug_level(struct device *d, |
2419 | struct device_attribute *attr, | |
b481de9c ZY |
2420 | const char *buf, size_t count) |
2421 | { | |
928841b1 | 2422 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2423 | unsigned long val; |
2424 | int ret; | |
b481de9c | 2425 | |
9257746f TW |
2426 | ret = strict_strtoul(buf, 0, &val); |
2427 | if (ret) | |
978785a3 | 2428 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); |
20594eb0 | 2429 | else { |
3d816c77 | 2430 | priv->debug_level = val; |
20594eb0 WYG |
2431 | if (iwl_alloc_traffic_mem(priv)) |
2432 | IWL_ERR(priv, | |
2433 | "Not enough memory to generate traffic log\n"); | |
2434 | } | |
b481de9c ZY |
2435 | return strnlen(buf, count); |
2436 | } | |
2437 | ||
8cf769c6 EK |
2438 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
2439 | show_debug_level, store_debug_level); | |
2440 | ||
b481de9c | 2441 | |
0a6857e7 | 2442 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 2443 | |
b481de9c ZY |
2444 | |
2445 | static ssize_t show_temperature(struct device *d, | |
2446 | struct device_attribute *attr, char *buf) | |
2447 | { | |
928841b1 | 2448 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 2449 | |
fee1247a | 2450 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
2451 | return -EAGAIN; |
2452 | ||
91dbc5bd | 2453 | return sprintf(buf, "%d\n", priv->temperature); |
b481de9c ZY |
2454 | } |
2455 | ||
2456 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
2457 | ||
b481de9c ZY |
2458 | static ssize_t show_tx_power(struct device *d, |
2459 | struct device_attribute *attr, char *buf) | |
2460 | { | |
928841b1 | 2461 | struct iwl_priv *priv = dev_get_drvdata(d); |
91f39e8e JS |
2462 | |
2463 | if (!iwl_is_ready_rf(priv)) | |
2464 | return sprintf(buf, "off\n"); | |
2465 | else | |
2466 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
b481de9c ZY |
2467 | } |
2468 | ||
2469 | static ssize_t store_tx_power(struct device *d, | |
2470 | struct device_attribute *attr, | |
2471 | const char *buf, size_t count) | |
2472 | { | |
928841b1 | 2473 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2474 | unsigned long val; |
2475 | int ret; | |
b481de9c | 2476 | |
9257746f TW |
2477 | ret = strict_strtoul(buf, 10, &val); |
2478 | if (ret) | |
978785a3 | 2479 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); |
b481de9c | 2480 | else |
630fe9b6 | 2481 | iwl_set_tx_power(priv, val, false); |
b481de9c ZY |
2482 | |
2483 | return count; | |
2484 | } | |
2485 | ||
2486 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
2487 | ||
2488 | static ssize_t show_flags(struct device *d, | |
2489 | struct device_attribute *attr, char *buf) | |
2490 | { | |
928841b1 | 2491 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
2492 | |
2493 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); | |
2494 | } | |
2495 | ||
2496 | static ssize_t store_flags(struct device *d, | |
2497 | struct device_attribute *attr, | |
2498 | const char *buf, size_t count) | |
2499 | { | |
928841b1 | 2500 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2501 | unsigned long val; |
2502 | u32 flags; | |
2503 | int ret = strict_strtoul(buf, 0, &val); | |
926f0b2e | 2504 | if (ret) |
9257746f TW |
2505 | return ret; |
2506 | flags = (u32)val; | |
b481de9c ZY |
2507 | |
2508 | mutex_lock(&priv->mutex); | |
2509 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { | |
2510 | /* Cancel any currently running scans... */ | |
2a421b91 | 2511 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 2512 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 2513 | else { |
e1623446 | 2514 | IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags); |
b481de9c | 2515 | priv->staging_rxon.flags = cpu_to_le32(flags); |
e0158e61 | 2516 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2517 | } |
2518 | } | |
2519 | mutex_unlock(&priv->mutex); | |
2520 | ||
2521 | return count; | |
2522 | } | |
2523 | ||
2524 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
2525 | ||
2526 | static ssize_t show_filter_flags(struct device *d, | |
2527 | struct device_attribute *attr, char *buf) | |
2528 | { | |
928841b1 | 2529 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
2530 | |
2531 | return sprintf(buf, "0x%04X\n", | |
2532 | le32_to_cpu(priv->active_rxon.filter_flags)); | |
2533 | } | |
2534 | ||
2535 | static ssize_t store_filter_flags(struct device *d, | |
2536 | struct device_attribute *attr, | |
2537 | const char *buf, size_t count) | |
2538 | { | |
928841b1 | 2539 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2540 | unsigned long val; |
2541 | u32 filter_flags; | |
2542 | int ret = strict_strtoul(buf, 0, &val); | |
926f0b2e | 2543 | if (ret) |
9257746f TW |
2544 | return ret; |
2545 | filter_flags = (u32)val; | |
b481de9c ZY |
2546 | |
2547 | mutex_lock(&priv->mutex); | |
2548 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { | |
2549 | /* Cancel any currently running scans... */ | |
2a421b91 | 2550 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 2551 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 2552 | else { |
e1623446 | 2553 | IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = " |
b481de9c ZY |
2554 | "0x%04X\n", filter_flags); |
2555 | priv->staging_rxon.filter_flags = | |
2556 | cpu_to_le32(filter_flags); | |
e0158e61 | 2557 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2558 | } |
2559 | } | |
2560 | mutex_unlock(&priv->mutex); | |
2561 | ||
2562 | return count; | |
2563 | } | |
2564 | ||
2565 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
2566 | store_filter_flags); | |
2567 | ||
b481de9c ZY |
2568 | static ssize_t store_power_level(struct device *d, |
2569 | struct device_attribute *attr, | |
2570 | const char *buf, size_t count) | |
2571 | { | |
c79dd5b5 | 2572 | struct iwl_priv *priv = dev_get_drvdata(d); |
298df1f6 | 2573 | int ret; |
9257746f TW |
2574 | unsigned long mode; |
2575 | ||
b481de9c | 2576 | |
b481de9c ZY |
2577 | mutex_lock(&priv->mutex); |
2578 | ||
9257746f | 2579 | ret = strict_strtoul(buf, 10, &mode); |
926f0b2e | 2580 | if (ret) |
9257746f TW |
2581 | goto out; |
2582 | ||
298df1f6 EK |
2583 | ret = iwl_power_set_user_mode(priv, mode); |
2584 | if (ret) { | |
e1623446 | 2585 | IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n"); |
5da4b55f | 2586 | goto out; |
b481de9c | 2587 | } |
298df1f6 | 2588 | ret = count; |
b481de9c ZY |
2589 | |
2590 | out: | |
2591 | mutex_unlock(&priv->mutex); | |
298df1f6 | 2592 | return ret; |
b481de9c ZY |
2593 | } |
2594 | ||
b481de9c ZY |
2595 | static ssize_t show_power_level(struct device *d, |
2596 | struct device_attribute *attr, char *buf) | |
2597 | { | |
c79dd5b5 | 2598 | struct iwl_priv *priv = dev_get_drvdata(d); |
5da4b55f | 2599 | int level = priv->power_data.power_mode; |
b481de9c ZY |
2600 | char *p = buf; |
2601 | ||
872ed190 | 2602 | p += sprintf(p, "%d\n", level); |
3ac7f146 | 2603 | return p - buf + 1; |
b481de9c ZY |
2604 | } |
2605 | ||
2606 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, | |
2607 | store_power_level); | |
2608 | ||
b481de9c ZY |
2609 | |
2610 | static ssize_t show_statistics(struct device *d, | |
2611 | struct device_attribute *attr, char *buf) | |
2612 | { | |
c79dd5b5 | 2613 | struct iwl_priv *priv = dev_get_drvdata(d); |
8f91aecb | 2614 | u32 size = sizeof(struct iwl_notif_statistics); |
b481de9c | 2615 | u32 len = 0, ofs = 0; |
3ac7f146 | 2616 | u8 *data = (u8 *)&priv->statistics; |
b481de9c ZY |
2617 | int rc = 0; |
2618 | ||
fee1247a | 2619 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
2620 | return -EAGAIN; |
2621 | ||
2622 | mutex_lock(&priv->mutex); | |
49ea8596 | 2623 | rc = iwl_send_statistics_request(priv, 0); |
b481de9c ZY |
2624 | mutex_unlock(&priv->mutex); |
2625 | ||
2626 | if (rc) { | |
2627 | len = sprintf(buf, | |
2628 | "Error sending statistics request: 0x%08X\n", rc); | |
2629 | return len; | |
2630 | } | |
2631 | ||
2632 | while (size && (PAGE_SIZE - len)) { | |
2633 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
2634 | PAGE_SIZE - len, 1); | |
2635 | len = strlen(buf); | |
2636 | if (PAGE_SIZE - len) | |
2637 | buf[len++] = '\n'; | |
2638 | ||
2639 | ofs += 16; | |
2640 | size -= min(size, 16U); | |
2641 | } | |
2642 | ||
2643 | return len; | |
2644 | } | |
2645 | ||
2646 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
2647 | ||
b481de9c | 2648 | |
b481de9c ZY |
2649 | /***************************************************************************** |
2650 | * | |
2651 | * driver setup and teardown | |
2652 | * | |
2653 | *****************************************************************************/ | |
2654 | ||
4e39317d | 2655 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 2656 | { |
d21050c7 | 2657 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
2658 | |
2659 | init_waitqueue_head(&priv->wait_command_queue); | |
2660 | ||
5b9f8cd3 EG |
2661 | INIT_WORK(&priv->up, iwl_bg_up); |
2662 | INIT_WORK(&priv->restart, iwl_bg_restart); | |
2663 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
5b9f8cd3 | 2664 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); |
16e727e8 | 2665 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
4a4a9e81 TW |
2666 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start); |
2667 | INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start); | |
2a421b91 | 2668 | |
2a421b91 | 2669 | iwl_setup_scan_deferred_work(priv); |
bb8c093b | 2670 | |
4e39317d EG |
2671 | if (priv->cfg->ops->lib->setup_deferred_work) |
2672 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
2673 | ||
2674 | init_timer(&priv->statistics_periodic); | |
2675 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 2676 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c | 2677 | |
ef850d7c MA |
2678 | if (!priv->cfg->use_isr_legacy) |
2679 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
2680 | iwl_irq_tasklet, (unsigned long)priv); | |
2681 | else | |
2682 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
2683 | iwl_irq_tasklet_legacy, (unsigned long)priv); | |
b481de9c ZY |
2684 | } |
2685 | ||
4e39317d | 2686 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 2687 | { |
4e39317d EG |
2688 | if (priv->cfg->ops->lib->cancel_deferred_work) |
2689 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 2690 | |
3ae6a054 | 2691 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
2692 | cancel_delayed_work(&priv->scan_check); |
2693 | cancel_delayed_work(&priv->alive_start); | |
b481de9c | 2694 | cancel_work_sync(&priv->beacon_update); |
4e39317d | 2695 | del_timer_sync(&priv->statistics_periodic); |
b481de9c ZY |
2696 | } |
2697 | ||
5b9f8cd3 | 2698 | static struct attribute *iwl_sysfs_entries[] = { |
b481de9c ZY |
2699 | &dev_attr_flags.attr, |
2700 | &dev_attr_filter_flags.attr, | |
b481de9c | 2701 | &dev_attr_power_level.attr, |
b481de9c | 2702 | &dev_attr_statistics.attr, |
b481de9c | 2703 | &dev_attr_temperature.attr, |
b481de9c | 2704 | &dev_attr_tx_power.attr, |
8cf769c6 EK |
2705 | #ifdef CONFIG_IWLWIFI_DEBUG |
2706 | &dev_attr_debug_level.attr, | |
2707 | #endif | |
b481de9c ZY |
2708 | NULL |
2709 | }; | |
2710 | ||
5b9f8cd3 | 2711 | static struct attribute_group iwl_attribute_group = { |
b481de9c | 2712 | .name = NULL, /* put in device directory */ |
5b9f8cd3 | 2713 | .attrs = iwl_sysfs_entries, |
b481de9c ZY |
2714 | }; |
2715 | ||
5b9f8cd3 EG |
2716 | static struct ieee80211_ops iwl_hw_ops = { |
2717 | .tx = iwl_mac_tx, | |
2718 | .start = iwl_mac_start, | |
2719 | .stop = iwl_mac_stop, | |
2720 | .add_interface = iwl_mac_add_interface, | |
2721 | .remove_interface = iwl_mac_remove_interface, | |
2722 | .config = iwl_mac_config, | |
5b9f8cd3 EG |
2723 | .configure_filter = iwl_configure_filter, |
2724 | .set_key = iwl_mac_set_key, | |
2725 | .update_tkip_key = iwl_mac_update_tkip_key, | |
2726 | .get_stats = iwl_mac_get_stats, | |
2727 | .get_tx_stats = iwl_mac_get_tx_stats, | |
2728 | .conf_tx = iwl_mac_conf_tx, | |
2729 | .reset_tsf = iwl_mac_reset_tsf, | |
2730 | .bss_info_changed = iwl_bss_info_changed, | |
2731 | .ampdu_action = iwl_mac_ampdu_action, | |
cb43dc25 | 2732 | .hw_scan = iwl_mac_hw_scan |
b481de9c ZY |
2733 | }; |
2734 | ||
5b9f8cd3 | 2735 | static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
2736 | { |
2737 | int err = 0; | |
c79dd5b5 | 2738 | struct iwl_priv *priv; |
b481de9c | 2739 | struct ieee80211_hw *hw; |
82b9a121 | 2740 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 2741 | unsigned long flags; |
6cd0b1cb | 2742 | u16 pci_cmd; |
b481de9c | 2743 | |
316c30d9 AK |
2744 | /************************ |
2745 | * 1. Allocating HW data | |
2746 | ************************/ | |
2747 | ||
6440adb5 CB |
2748 | /* Disabling hardware scan means that mac80211 will perform scans |
2749 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 2750 | if (cfg->mod_params->disable_hw_scan) { |
a562a9dd | 2751 | if (iwl_debug_level & IWL_DL_INFO) |
bf403db8 EK |
2752 | dev_printk(KERN_DEBUG, &(pdev->dev), |
2753 | "Disabling hw_scan\n"); | |
5b9f8cd3 | 2754 | iwl_hw_ops.hw_scan = NULL; |
b481de9c ZY |
2755 | } |
2756 | ||
5b9f8cd3 | 2757 | hw = iwl_alloc_all(cfg, &iwl_hw_ops); |
1d0a082d | 2758 | if (!hw) { |
b481de9c ZY |
2759 | err = -ENOMEM; |
2760 | goto out; | |
2761 | } | |
1d0a082d AK |
2762 | priv = hw->priv; |
2763 | /* At this point both hw and priv are allocated. */ | |
2764 | ||
b481de9c ZY |
2765 | SET_IEEE80211_DEV(hw, &pdev->dev); |
2766 | ||
e1623446 | 2767 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
82b9a121 | 2768 | priv->cfg = cfg; |
b481de9c | 2769 | priv->pci_dev = pdev; |
40cefda9 | 2770 | priv->inta_mask = CSR_INI_SET_MASK; |
316c30d9 | 2771 | |
0a6857e7 | 2772 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
2773 | atomic_set(&priv->restrict_refcnt, 0); |
2774 | #endif | |
20594eb0 WYG |
2775 | if (iwl_alloc_traffic_mem(priv)) |
2776 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 2777 | |
316c30d9 AK |
2778 | /************************** |
2779 | * 2. Initializing PCI bus | |
2780 | **************************/ | |
2781 | if (pci_enable_device(pdev)) { | |
2782 | err = -ENODEV; | |
2783 | goto out_ieee80211_free_hw; | |
2784 | } | |
2785 | ||
2786 | pci_set_master(pdev); | |
2787 | ||
093d874c | 2788 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); |
316c30d9 | 2789 | if (!err) |
093d874c | 2790 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); |
cc2a8ea8 | 2791 | if (err) { |
093d874c | 2792 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 2793 | if (!err) |
093d874c | 2794 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 2795 | /* both attempts failed: */ |
316c30d9 | 2796 | if (err) { |
978785a3 | 2797 | IWL_WARN(priv, "No suitable DMA available.\n"); |
316c30d9 | 2798 | goto out_pci_disable_device; |
cc2a8ea8 | 2799 | } |
316c30d9 AK |
2800 | } |
2801 | ||
2802 | err = pci_request_regions(pdev, DRV_NAME); | |
2803 | if (err) | |
2804 | goto out_pci_disable_device; | |
2805 | ||
2806 | pci_set_drvdata(pdev, priv); | |
2807 | ||
316c30d9 AK |
2808 | |
2809 | /*********************** | |
2810 | * 3. Read REV register | |
2811 | ***********************/ | |
2812 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
2813 | if (!priv->hw_base) { | |
2814 | err = -ENODEV; | |
2815 | goto out_pci_release_regions; | |
2816 | } | |
2817 | ||
e1623446 | 2818 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
316c30d9 | 2819 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 2820 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
316c30d9 | 2821 | |
a8b50a0a MA |
2822 | /* this spin lock will be used in apm_ops.init and EEPROM access |
2823 | * we should init now | |
2824 | */ | |
2825 | spin_lock_init(&priv->reg_lock); | |
b661c819 | 2826 | iwl_hw_detect(priv); |
978785a3 | 2827 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n", |
b661c819 | 2828 | priv->cfg->name, priv->hw_rev); |
316c30d9 | 2829 | |
e7b63581 TW |
2830 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
2831 | * PCI Tx retries from interfering with C3 CPU state */ | |
2832 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
2833 | ||
086ed117 MA |
2834 | iwl_prepare_card_hw(priv); |
2835 | if (!priv->hw_ready) { | |
2836 | IWL_WARN(priv, "Failed, HW not ready\n"); | |
2837 | goto out_iounmap; | |
2838 | } | |
2839 | ||
91238714 TW |
2840 | /* amp init */ |
2841 | err = priv->cfg->ops->lib->apm_ops.init(priv); | |
316c30d9 | 2842 | if (err < 0) { |
808ff697 | 2843 | IWL_ERR(priv, "Failed to init APMG\n"); |
316c30d9 AK |
2844 | goto out_iounmap; |
2845 | } | |
91238714 TW |
2846 | /***************** |
2847 | * 4. Read EEPROM | |
2848 | *****************/ | |
316c30d9 AK |
2849 | /* Read the EEPROM */ |
2850 | err = iwl_eeprom_init(priv); | |
2851 | if (err) { | |
15b1687c | 2852 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
316c30d9 AK |
2853 | goto out_iounmap; |
2854 | } | |
8614f360 TW |
2855 | err = iwl_eeprom_check_version(priv); |
2856 | if (err) | |
c8f16138 | 2857 | goto out_free_eeprom; |
8614f360 | 2858 | |
02883017 | 2859 | /* extract MAC Address */ |
316c30d9 | 2860 | iwl_eeprom_get_mac(priv, priv->mac_addr); |
e1623446 | 2861 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr); |
316c30d9 AK |
2862 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); |
2863 | ||
2864 | /************************ | |
2865 | * 5. Setup HW constants | |
2866 | ************************/ | |
da154e30 | 2867 | if (iwl_set_hw_params(priv)) { |
15b1687c | 2868 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 2869 | goto out_free_eeprom; |
316c30d9 AK |
2870 | } |
2871 | ||
2872 | /******************* | |
6ba87956 | 2873 | * 6. Setup priv |
316c30d9 | 2874 | *******************/ |
b481de9c | 2875 | |
6ba87956 | 2876 | err = iwl_init_drv(priv); |
bf85ea4f | 2877 | if (err) |
399f4900 | 2878 | goto out_free_eeprom; |
bf85ea4f | 2879 | /* At this point both hw and priv are initialized. */ |
316c30d9 | 2880 | |
316c30d9 | 2881 | /******************** |
09f9bf79 | 2882 | * 7. Setup services |
316c30d9 | 2883 | ********************/ |
0359facc | 2884 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 2885 | iwl_disable_interrupts(priv); |
0359facc | 2886 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 | 2887 | |
6cd0b1cb HS |
2888 | pci_enable_msi(priv->pci_dev); |
2889 | ||
ef850d7c MA |
2890 | iwl_alloc_isr_ict(priv); |
2891 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr, | |
2892 | IRQF_SHARED, DRV_NAME, priv); | |
6cd0b1cb HS |
2893 | if (err) { |
2894 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
2895 | goto out_disable_msi; | |
2896 | } | |
5b9f8cd3 | 2897 | err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group); |
316c30d9 | 2898 | if (err) { |
15b1687c | 2899 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
795cc0ad | 2900 | goto out_free_irq; |
316c30d9 AK |
2901 | } |
2902 | ||
4e39317d | 2903 | iwl_setup_deferred_work(priv); |
653fa4a0 | 2904 | iwl_setup_rx_handlers(priv); |
316c30d9 | 2905 | |
6ba87956 | 2906 | /********************************** |
09f9bf79 | 2907 | * 8. Setup and register mac80211 |
6ba87956 TW |
2908 | **********************************/ |
2909 | ||
6cd0b1cb HS |
2910 | /* enable interrupts if needed: hw bug w/a */ |
2911 | pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd); | |
2912 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
2913 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
2914 | pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd); | |
2915 | } | |
2916 | ||
2917 | iwl_enable_interrupts(priv); | |
2918 | ||
6ba87956 TW |
2919 | err = iwl_setup_mac(priv); |
2920 | if (err) | |
2921 | goto out_remove_sysfs; | |
2922 | ||
2923 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
2924 | if (err) | |
a75fbe8d | 2925 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); |
6ba87956 | 2926 | |
6cd0b1cb HS |
2927 | /* If platform's RF_KILL switch is NOT set to KILL */ |
2928 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
2929 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2930 | else | |
2931 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 2932 | |
a60e77e5 JB |
2933 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
2934 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
6cd0b1cb | 2935 | |
58d0f361 | 2936 | iwl_power_initialize(priv); |
39b73fb1 | 2937 | iwl_tt_initialize(priv); |
b481de9c ZY |
2938 | return 0; |
2939 | ||
316c30d9 | 2940 | out_remove_sysfs: |
c8f16138 RC |
2941 | destroy_workqueue(priv->workqueue); |
2942 | priv->workqueue = NULL; | |
5b9f8cd3 | 2943 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
795cc0ad HS |
2944 | out_free_irq: |
2945 | free_irq(priv->pci_dev->irq, priv); | |
ef850d7c | 2946 | iwl_free_isr_ict(priv); |
6cd0b1cb HS |
2947 | out_disable_msi: |
2948 | pci_disable_msi(priv->pci_dev); | |
6ba87956 | 2949 | iwl_uninit_drv(priv); |
073d3f5f TW |
2950 | out_free_eeprom: |
2951 | iwl_eeprom_free(priv); | |
b481de9c ZY |
2952 | out_iounmap: |
2953 | pci_iounmap(pdev, priv->hw_base); | |
2954 | out_pci_release_regions: | |
316c30d9 | 2955 | pci_set_drvdata(pdev, NULL); |
623d563e | 2956 | pci_release_regions(pdev); |
b481de9c ZY |
2957 | out_pci_disable_device: |
2958 | pci_disable_device(pdev); | |
b481de9c ZY |
2959 | out_ieee80211_free_hw: |
2960 | ieee80211_free_hw(priv->hw); | |
20594eb0 | 2961 | iwl_free_traffic_mem(priv); |
b481de9c ZY |
2962 | out: |
2963 | return err; | |
2964 | } | |
2965 | ||
5b9f8cd3 | 2966 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
b481de9c | 2967 | { |
c79dd5b5 | 2968 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 2969 | unsigned long flags; |
b481de9c ZY |
2970 | |
2971 | if (!priv) | |
2972 | return; | |
2973 | ||
e1623446 | 2974 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 2975 | |
67249625 | 2976 | iwl_dbgfs_unregister(priv); |
5b9f8cd3 | 2977 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
67249625 | 2978 | |
5b9f8cd3 EG |
2979 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
2980 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
2981 | * we need to set STATUS_EXIT_PENDING bit. |
2982 | */ | |
2983 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
c4f55232 RR |
2984 | if (priv->mac80211_registered) { |
2985 | ieee80211_unregister_hw(priv->hw); | |
2986 | priv->mac80211_registered = 0; | |
0b124c31 | 2987 | } else { |
5b9f8cd3 | 2988 | iwl_down(priv); |
c4f55232 RR |
2989 | } |
2990 | ||
39b73fb1 WYG |
2991 | iwl_tt_exit(priv); |
2992 | ||
0359facc MA |
2993 | /* make sure we flush any pending irq or |
2994 | * tasklet for the driver | |
2995 | */ | |
2996 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 2997 | iwl_disable_interrupts(priv); |
0359facc MA |
2998 | spin_unlock_irqrestore(&priv->lock, flags); |
2999 | ||
3000 | iwl_synchronize_irq(priv); | |
3001 | ||
5b9f8cd3 | 3002 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
3003 | |
3004 | if (priv->rxq.bd) | |
a55360e4 | 3005 | iwl_rx_queue_free(priv, &priv->rxq); |
1053d35f | 3006 | iwl_hw_txq_ctx_free(priv); |
b481de9c | 3007 | |
c587de0b | 3008 | iwl_clear_stations_table(priv); |
073d3f5f | 3009 | iwl_eeprom_free(priv); |
b481de9c | 3010 | |
b481de9c | 3011 | |
948c171c MA |
3012 | /*netif_stop_queue(dev); */ |
3013 | flush_workqueue(priv->workqueue); | |
3014 | ||
5b9f8cd3 | 3015 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
3016 | * priv->workqueue... so we can't take down the workqueue |
3017 | * until now... */ | |
3018 | destroy_workqueue(priv->workqueue); | |
3019 | priv->workqueue = NULL; | |
20594eb0 | 3020 | iwl_free_traffic_mem(priv); |
b481de9c | 3021 | |
6cd0b1cb HS |
3022 | free_irq(priv->pci_dev->irq, priv); |
3023 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
3024 | pci_iounmap(pdev, priv->hw_base); |
3025 | pci_release_regions(pdev); | |
3026 | pci_disable_device(pdev); | |
3027 | pci_set_drvdata(pdev, NULL); | |
3028 | ||
6ba87956 | 3029 | iwl_uninit_drv(priv); |
b481de9c | 3030 | |
ef850d7c MA |
3031 | iwl_free_isr_ict(priv); |
3032 | ||
b481de9c ZY |
3033 | if (priv->ibss_beacon) |
3034 | dev_kfree_skb(priv->ibss_beacon); | |
3035 | ||
3036 | ieee80211_free_hw(priv->hw); | |
3037 | } | |
3038 | ||
b481de9c ZY |
3039 | |
3040 | /***************************************************************************** | |
3041 | * | |
3042 | * driver and module entry point | |
3043 | * | |
3044 | *****************************************************************************/ | |
3045 | ||
fed9017e RR |
3046 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
3047 | static struct pci_device_id iwl_hw_card_ids[] = { | |
4fc22b21 | 3048 | #ifdef CONFIG_IWL4965 |
fed9017e RR |
3049 | {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, |
3050 | {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, | |
4fc22b21 | 3051 | #endif /* CONFIG_IWL4965 */ |
5a6a256e | 3052 | #ifdef CONFIG_IWL5000 |
47408639 EK |
3053 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)}, |
3054 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)}, | |
3055 | {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, | |
3056 | {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, | |
3057 | {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, | |
3058 | {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, | |
5a6a256e | 3059 | {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)}, |
47408639 EK |
3060 | {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)}, |
3061 | {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)}, | |
3062 | {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)}, | |
e96a8495 TW |
3063 | /* 5350 WiFi/WiMax */ |
3064 | {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, | |
3065 | {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, | |
3066 | {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, | |
7100e924 TW |
3067 | /* 5150 Wifi/WiMax */ |
3068 | {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)}, | |
3069 | {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)}, | |
e1228374 | 3070 | /* 6000/6050 Series */ |
65b7998a WYG |
3071 | {IWL_PCI_DEVICE(0x008D, PCI_ANY_ID, iwl6000h_2agn_cfg)}, |
3072 | {IWL_PCI_DEVICE(0x008E, PCI_ANY_ID, iwl6000h_2agn_cfg)}, | |
e1228374 | 3073 | {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)}, |
65b7998a | 3074 | {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000i_2agn_cfg)}, |
e1228374 | 3075 | {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)}, |
65b7998a | 3076 | {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000i_2agn_cfg)}, |
e1228374 JS |
3077 | {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)}, |
3078 | {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)}, | |
3079 | {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)}, | |
3080 | {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)}, | |
77dcb6a9 JS |
3081 | /* 1000 Series WiFi */ |
3082 | {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)}, | |
3083 | {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)}, | |
5a6a256e | 3084 | #endif /* CONFIG_IWL5000 */ |
7100e924 | 3085 | |
fed9017e RR |
3086 | {0} |
3087 | }; | |
3088 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | |
3089 | ||
3090 | static struct pci_driver iwl_driver = { | |
b481de9c | 3091 | .name = DRV_NAME, |
fed9017e | 3092 | .id_table = iwl_hw_card_ids, |
5b9f8cd3 EG |
3093 | .probe = iwl_pci_probe, |
3094 | .remove = __devexit_p(iwl_pci_remove), | |
b481de9c | 3095 | #ifdef CONFIG_PM |
5b9f8cd3 EG |
3096 | .suspend = iwl_pci_suspend, |
3097 | .resume = iwl_pci_resume, | |
b481de9c ZY |
3098 | #endif |
3099 | }; | |
3100 | ||
5b9f8cd3 | 3101 | static int __init iwl_init(void) |
b481de9c ZY |
3102 | { |
3103 | ||
3104 | int ret; | |
3105 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
3106 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 | 3107 | |
e227ceac | 3108 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 3109 | if (ret) { |
a3139c59 SO |
3110 | printk(KERN_ERR DRV_NAME |
3111 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
3112 | return ret; |
3113 | } | |
3114 | ||
fed9017e | 3115 | ret = pci_register_driver(&iwl_driver); |
b481de9c | 3116 | if (ret) { |
a3139c59 | 3117 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 3118 | goto error_register; |
b481de9c | 3119 | } |
b481de9c ZY |
3120 | |
3121 | return ret; | |
897e1cf2 | 3122 | |
897e1cf2 | 3123 | error_register: |
e227ceac | 3124 | iwlagn_rate_control_unregister(); |
897e1cf2 | 3125 | return ret; |
b481de9c ZY |
3126 | } |
3127 | ||
5b9f8cd3 | 3128 | static void __exit iwl_exit(void) |
b481de9c | 3129 | { |
fed9017e | 3130 | pci_unregister_driver(&iwl_driver); |
e227ceac | 3131 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
3132 | } |
3133 | ||
5b9f8cd3 EG |
3134 | module_exit(iwl_exit); |
3135 | module_init(iwl_init); | |
a562a9dd RC |
3136 | |
3137 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3138 | module_param_named(debug50, iwl_debug_level, uint, 0444); | |
3139 | MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)"); | |
3140 | module_param_named(debug, iwl_debug_level, uint, 0644); | |
3141 | MODULE_PARM_DESC(debug, "debug output mask"); | |
3142 | #endif | |
3143 |