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iwlwifi: issue ct_kill host command based on device config
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
01f8162a 5 * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
df48c323
TW		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
df48c323
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
8ccde88a 31#include <linux/etherdevice.h>
1d0a082d 32#include <net/mac80211.h>
df48c323 33
6bc913bd 34#include "iwl-eeprom.h"
3e0d4cb1 35#include "iwl-dev.h" /* FIXME: remove */
19335774 36#include "iwl-debug.h"
df48c323 37#include "iwl-core.h"
b661c819 38#include "iwl-io.h"
5da4b55f 39#include "iwl-power.h"
83dde8c9 40#include "iwl-sta.h"
ef850d7c 41#include "iwl-helpers.h"
df48c323 42
1d0a082d 43
df48c323
TW		 44MODULE_DESCRIPTION("iwl core");
45MODULE_VERSION(IWLWIFI_VERSION);
a7b75207 46MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
712b6cf5 47MODULE_LICENSE("GPL");
df48c323 48
c7de35cd
RR		 49#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
61
a562a9dd
RC		 62u32 iwl_debug_level;
63EXPORT_SYMBOL(iwl_debug_level);
64
ef850d7c
MA		 65static irqreturn_t iwl_isr(int irq, void *data);
66
c7de35cd
RR		 67/*
68 * Parameter order:
69 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
70 *
71 * If there isn't a valid next or previous rate then INV is used which
72 * maps to IWL_RATE_INVALID
73 *
74 */
1826dcc0 75const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 76 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
77 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
78 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
79 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
80 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
81 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
82 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
83 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
84 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
85 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
86 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
87 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
88 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
89 /* FIXME:RS: ^^ should be INV (legacy) */
90};
1826dcc0 91EXPORT_SYMBOL(iwl_rates);
c7de35cd 92
e7d326ac
TW		 93/**
94 * translate ucode response to mac80211 tx status control values
95 */
96void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 97 struct ieee80211_tx_info *info)
e7d326ac 98{
e6a9854b 99 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 100
e6a9854b 101 info->antenna_sel_tx =
e7d326ac
TW		 102 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
103 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 104 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 105 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 106 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
7aafef1c 107 if (rate_n_flags & RATE_MCS_HT40_MSK)
e6a9854b 108 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 109 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 110 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 111 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 112 r->flags |= IEEE80211_TX_RC_SHORT_GI;
31513be8 113 r->idx = iwl_hwrate_to_mac80211_idx(rate_n_flags, info->band);
e7d326ac
TW		 114}
115EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
116
117int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
118{
119 int idx = 0;
120
121 /* HT rate format */
122 if (rate_n_flags & RATE_MCS_HT_MSK) {
123 idx = (rate_n_flags & 0xff);
124
60d32215
DH		 125 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
126 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
127 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 128 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
129
130 idx += IWL_FIRST_OFDM_RATE;
131 /* skip 9M not supported in ht*/
132 if (idx >= IWL_RATE_9M_INDEX)
133 idx += 1;
134 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
135 return idx;
136
137 /* legacy rate format, search for match in table */
138 } else {
139 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
140 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
141 return idx;
142 }
143
144 return -1;
145}
146EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
147
31513be8
DH		 148int iwl_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
149{
150 int idx = 0;
151 int band_offset = 0;
152
153 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
154 if (rate_n_flags & RATE_MCS_HT_MSK) {
155 idx = (rate_n_flags & 0xff);
156 return idx;
157 /* Legacy rate format, search for match in table */
158 } else {
159 if (band == IEEE80211_BAND_5GHZ)
160 band_offset = IWL_FIRST_OFDM_RATE;
161 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
162 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
163 return idx - band_offset;
164 }
165
166 return -1;
167}
168
76eff18b
TW		 169u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
170{
171 int i;
172 u8 ind = ant;
173 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
174 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
175 if (priv->hw_params.valid_tx_ant & BIT(ind))
176 return ind;
177 }
178 return ant;
179}
57bd1bea
TW		 180
181const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
182EXPORT_SYMBOL(iwl_bcast_addr);
183
184
1d0a082d
AK		 185/* This function both allocates and initializes hw and priv. */
186struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
187 struct ieee80211_ops *hw_ops)
188{
189 struct iwl_priv *priv;
190
191 /* mac80211 allocates memory for this device instance, including
192 * space for this driver's private structure */
193 struct ieee80211_hw *hw =
194 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
195 if (hw == NULL) {
a3139c59
SO		 196 printk(KERN_ERR "%s: Can not allocate network device\n",
197 cfg->name);
1d0a082d
AK		 198 goto out;
199 }
200
201 priv = hw->priv;
202 priv->hw = hw;
203
204out:
205 return hw;
206}
207EXPORT_SYMBOL(iwl_alloc_all);
208
b661c819
TW		 209void iwl_hw_detect(struct iwl_priv *priv)
210{
211 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
212 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
213 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
214}
215EXPORT_SYMBOL(iwl_hw_detect);
216
1053d35f
RR		 217int iwl_hw_nic_init(struct iwl_priv *priv)
218{
219 unsigned long flags;
220 struct iwl_rx_queue *rxq = &priv->rxq;
221 int ret;
222
223 /* nic_init */
1053d35f 224 spin_lock_irqsave(&priv->lock, flags);
1b73af82 225 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 226 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
227 spin_unlock_irqrestore(&priv->lock, flags);
228
229 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
230
231 priv->cfg->ops->lib->apm_ops.config(priv);
232
233 /* Allocate the RX queue, or reset if it is already allocated */
234 if (!rxq->bd) {
235 ret = iwl_rx_queue_alloc(priv);
236 if (ret) {
15b1687c 237 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1053d35f
RR		 238 return -ENOMEM;
239 }
240 } else
241 iwl_rx_queue_reset(priv, rxq);
242
243 iwl_rx_replenish(priv);
244
245 iwl_rx_init(priv, rxq);
246
247 spin_lock_irqsave(&priv->lock, flags);
248
249 rxq->need_update = 1;
250 iwl_rx_queue_update_write_ptr(priv, rxq);
251
252 spin_unlock_irqrestore(&priv->lock, flags);
253
254 /* Allocate and init all Tx and Command queues */
255 ret = iwl_txq_ctx_reset(priv);
256 if (ret)
257 return ret;
258
259 set_bit(STATUS_INIT, &priv->status);
260
261 return 0;
262}
263EXPORT_SYMBOL(iwl_hw_nic_init);
264
14d2aac5
AK		 265/*
266 * QoS support
267*/
268void iwl_activate_qos(struct iwl_priv *priv, u8 force)
269{
270 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
271 return;
272
273 priv->qos_data.def_qos_parm.qos_flags = 0;
274
275 if (priv->qos_data.qos_cap.q_AP.queue_request &&
276 !priv->qos_data.qos_cap.q_AP.txop_request)
277 priv->qos_data.def_qos_parm.qos_flags |=
278 QOS_PARAM_FLG_TXOP_TYPE_MSK;
279 if (priv->qos_data.qos_active)
280 priv->qos_data.def_qos_parm.qos_flags |=
281 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
282
283 if (priv->current_ht_config.is_ht)
284 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
285
286 if (force || iwl_is_associated(priv)) {
287 IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
288 priv->qos_data.qos_active,
289 priv->qos_data.def_qos_parm.qos_flags);
290
291 iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
292 sizeof(struct iwl_qosparam_cmd),
293 &priv->qos_data.def_qos_parm, NULL);
294 }
295}
296EXPORT_SYMBOL(iwl_activate_qos);
297
f2c95b04
WYG		 298/*
299 * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
300 * (802.11b) (802.11a/g)
301 * AC_BK 15 1023 7 0 0
302 * AC_BE 15 1023 3 0 0
303 * AC_VI 7 15 2 6.016ms 3.008ms
304 * AC_VO 3 7 2 3.264ms 1.504ms
305 */
c7de35cd 306void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 307{
308 u16 cw_min = 15;
309 u16 cw_max = 1023;
310 u8 aifs = 2;
30dab79e 311 bool is_legacy = false;
bf85ea4f
AK		 312 unsigned long flags;
313 int i;
314
315 spin_lock_irqsave(&priv->lock, flags);
30dab79e
WT		 316 /* QoS always active in AP and ADHOC mode
317 * In STA mode wait for association
318 */
319 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
320 priv->iw_mode == NL80211_IFTYPE_AP)
321 priv->qos_data.qos_active = 1;
322 else
323 priv->qos_data.qos_active = 0;
bf85ea4f 324
30dab79e
WT		 325 /* check for legacy mode */
326 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
327 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
328 (priv->iw_mode == NL80211_IFTYPE_STATION &&
329 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
bf85ea4f
AK		 330 cw_min = 31;
331 is_legacy = 1;
332 }
333
334 if (priv->qos_data.qos_active)
335 aifs = 3;
336
f2c95b04 337 /* AC_BE */
bf85ea4f
AK		 338 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
339 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
340 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
341 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
342 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
343
344 if (priv->qos_data.qos_active) {
f2c95b04 345 /* AC_BK */
bf85ea4f
AK		 346 i = 1;
347 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
348 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
349 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
350 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
351 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
352
f2c95b04 353 /* AC_VI */
bf85ea4f
AK		 354 i = 2;
355 priv->qos_data.def_qos_parm.ac[i].cw_min =
356 cpu_to_le16((cw_min + 1) / 2 - 1);
357 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 358 cpu_to_le16(cw_min);
bf85ea4f
AK		 359 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
360 if (is_legacy)
361 priv->qos_data.def_qos_parm.ac[i].edca_txop =
362 cpu_to_le16(6016);
363 else
364 priv->qos_data.def_qos_parm.ac[i].edca_txop =
365 cpu_to_le16(3008);
366 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
367
f2c95b04 368 /* AC_VO */
bf85ea4f
AK		 369 i = 3;
370 priv->qos_data.def_qos_parm.ac[i].cw_min =
371 cpu_to_le16((cw_min + 1) / 4 - 1);
372 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 373 cpu_to_le16((cw_min + 1) / 2 - 1);
bf85ea4f
AK		 374 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
375 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
376 if (is_legacy)
377 priv->qos_data.def_qos_parm.ac[i].edca_txop =
378 cpu_to_le16(3264);
379 else
380 priv->qos_data.def_qos_parm.ac[i].edca_txop =
381 cpu_to_le16(1504);
382 } else {
383 for (i = 1; i < 4; i++) {
384 priv->qos_data.def_qos_parm.ac[i].cw_min =
385 cpu_to_le16(cw_min);
386 priv->qos_data.def_qos_parm.ac[i].cw_max =
387 cpu_to_le16(cw_max);
388 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
389 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
390 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
391 }
392 }
e1623446 393 IWL_DEBUG_QOS(priv, "set QoS to default \n");
bf85ea4f
AK		 394
395 spin_unlock_irqrestore(&priv->lock, flags);
396}
c7de35cd
RR		 397EXPORT_SYMBOL(iwl_reset_qos);
398
d9fe60de
JB		 399#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
400#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 401static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 402 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 403 enum ieee80211_band band)
404{
39130df3
RR		 405 u16 max_bit_rate = 0;
406 u8 rx_chains_num = priv->hw_params.rx_chains_num;
407 u8 tx_chains_num = priv->hw_params.tx_chains_num;
408
c7de35cd 409 ht_info->cap = 0;
d9fe60de 410 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 411
d9fe60de 412 ht_info->ht_supported = true;
c7de35cd 413
b261793d
DH		 414 if (priv->cfg->ht_greenfield_support)
415 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
d9fe60de
JB		 416 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
417 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
00c5ae2f 418 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
39130df3
RR		 419
420 max_bit_rate = MAX_BIT_RATE_20_MHZ;
7aafef1c 421 if (priv->hw_params.ht40_channel & BIT(band)) {
d9fe60de
JB		 422 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
423 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
424 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 425 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 426 }
c7de35cd
RR		 427
428 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 429 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 430
431 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
432 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
433
d9fe60de 434 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 435 if (rx_chains_num >= 2)
d9fe60de 436 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 437 if (rx_chains_num >= 3)
d9fe60de 438 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 439
440 /* Highest supported Rx data rate */
441 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 442 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
443 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 444
445 /* Tx MCS capabilities */
d9fe60de 446 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 447 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 448 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
449 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
450 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 451 }
c7de35cd 452}
c7de35cd
RR		 453
454static void iwlcore_init_hw_rates(struct iwl_priv *priv,
455 struct ieee80211_rate *rates)
456{
457 int i;
458
5027309b 459 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
1826dcc0 460 rates[i].bitrate = iwl_rates[i].ieee * 5;
c7de35cd
RR		 461 rates[i].hw_value = i; /* Rate scaling will work on indexes */
462 rates[i].hw_value_short = i;
463 rates[i].flags = 0;
5027309b 464 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
c7de35cd
RR		 465 /*
466 * If CCK != 1M then set short preamble rate flag.
467 */
468 rates[i].flags |=
1826dcc0 469 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
c7de35cd
RR		 470 0 : IEEE80211_RATE_SHORT_PREAMBLE;
471 }
472 }
473}
474
8ccde88a 475
c7de35cd
RR		 476/**
477 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
478 */
534166de 479int iwlcore_init_geos(struct iwl_priv *priv)
c7de35cd
RR		 480{
481 struct iwl_channel_info *ch;
482 struct ieee80211_supported_band *sband;
483 struct ieee80211_channel *channels;
484 struct ieee80211_channel *geo_ch;
485 struct ieee80211_rate *rates;
486 int i = 0;
487
488 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
489 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
e1623446 490 IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
c7de35cd
RR		 491 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
492 return 0;
493 }
494
495 channels = kzalloc(sizeof(struct ieee80211_channel) *
496 priv->channel_count, GFP_KERNEL);
497 if (!channels)
498 return -ENOMEM;
499
5027309b 500 rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY),
c7de35cd
RR		 501 GFP_KERNEL);
502 if (!rates) {
503 kfree(channels);
504 return -ENOMEM;
505 }
506
507 /* 5.2GHz channels start after the 2.4GHz channels */
508 sband = &priv->bands[IEEE80211_BAND_5GHZ];
509 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
510 /* just OFDM */
511 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
5027309b 512 sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
c7de35cd 513
49779293 514 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 515 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 516 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 517
518 sband = &priv->bands[IEEE80211_BAND_2GHZ];
519 sband->channels = channels;
520 /* OFDM & CCK */
521 sband->bitrates = rates;
5027309b 522 sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
c7de35cd 523
49779293 524 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 525 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 526 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 527
528 priv->ieee_channels = channels;
529 priv->ieee_rates = rates;
530
c7de35cd
RR		 531 for (i = 0; i < priv->channel_count; i++) {
532 ch = &priv->channel_info[i];
533
534 /* FIXME: might be removed if scan is OK */
535 if (!is_channel_valid(ch))
536 continue;
537
538 if (is_channel_a_band(ch))
539 sband = &priv->bands[IEEE80211_BAND_5GHZ];
540 else
541 sband = &priv->bands[IEEE80211_BAND_2GHZ];
542
543 geo_ch = &sband->channels[sband->n_channels++];
544
545 geo_ch->center_freq =
546 ieee80211_channel_to_frequency(ch->channel);
547 geo_ch->max_power = ch->max_power_avg;
548 geo_ch->max_antenna_gain = 0xff;
549 geo_ch->hw_value = ch->channel;
550
551 if (is_channel_valid(ch)) {
552 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
553 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
554
555 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
556 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
557
558 if (ch->flags & EEPROM_CHANNEL_RADAR)
559 geo_ch->flags |= IEEE80211_CHAN_RADAR;
560
7aafef1c 561 geo_ch->flags |= ch->ht40_extension_channel;
4d38c2e8 562
dc1b0973
WYG		 563 if (ch->max_power_avg > priv->tx_power_device_lmt)
564 priv->tx_power_device_lmt = ch->max_power_avg;
c7de35cd
RR		 565 } else {
566 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
567 }
568
e1623446 569 IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 570 ch->channel, geo_ch->center_freq,
571 is_channel_a_band(ch) ? "5.2" : "2.4",
572 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
573 "restricted" : "valid",
574 geo_ch->flags);
575 }
576
577 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
578 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW		 579 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
580 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
a3139c59
SO		 581 priv->pci_dev->device,
582 priv->pci_dev->subsystem_device);
c7de35cd
RR		 583 priv->cfg->sku &= ~IWL_SKU_A;
584 }
585
978785a3 586 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
a3139c59
SO		 587 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
588 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
c7de35cd
RR		 589
590 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
591
592 return 0;
593}
534166de 594EXPORT_SYMBOL(iwlcore_init_geos);
c7de35cd
RR		 595
596/*
597 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
598 */
534166de 599void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 600{
601 kfree(priv->ieee_channels);
602 kfree(priv->ieee_rates);
603 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
604}
534166de 605EXPORT_SYMBOL(iwlcore_free_geos);
c7de35cd 606
37dc70fe
AK		 607/*
608 * iwlcore_rts_tx_cmd_flag: Set rts/cts. 3945 and 4965 only share this
609 * function.
610 */
611void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
612 __le32 *tx_flags)
613{
614 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
615 *tx_flags |= TX_CMD_FLG_RTS_MSK;
616 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
617 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
618 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
619 *tx_flags |= TX_CMD_FLG_CTS_MSK;
620 }
621}
622EXPORT_SYMBOL(iwlcore_rts_tx_cmd_flag);
623
28a6b07a 624static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 625{
626 return !priv->current_ht_config.is_ht ||
02bb1bea 627 priv->current_ht_config.single_chain_sufficient;
c7de35cd 628}
963f5517 629
47c5196e
TW		 630static u8 iwl_is_channel_extension(struct iwl_priv *priv,
631 enum ieee80211_band band,
632 u16 channel, u8 extension_chan_offset)
633{
634 const struct iwl_channel_info *ch_info;
635
636 ch_info = iwl_get_channel_info(priv, band, channel);
637 if (!is_channel_valid(ch_info))
638 return 0;
639
d9fe60de 640 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
7aafef1c 641 return !(ch_info->ht40_extension_channel &
689da1b3 642 IEEE80211_CHAN_NO_HT40PLUS);
d9fe60de 643 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
7aafef1c 644 return !(ch_info->ht40_extension_channel &
689da1b3 645 IEEE80211_CHAN_NO_HT40MINUS);
47c5196e
TW		 646
647 return 0;
648}
649
7aafef1c 650u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
d9fe60de 651 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e 652{
fad95bf5 653 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
47c5196e 654
fad95bf5 655 if (!ht_conf->is_ht || !ht_conf->is_40mhz)
47c5196e
TW		 656 return 0;
657
a2b0f02e
WYG		 658 /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
659 * the bit will not set if it is pure 40MHz case
660 */
47c5196e 661 if (sta_ht_inf) {
a2b0f02e 662 if (!sta_ht_inf->ht_supported)
47c5196e
TW		 663 return 0;
664 }
1e4247d4
WYG		 665#ifdef CONFIG_IWLWIFI_DEBUG
666 if (priv->disable_ht40)
667 return 0;
668#endif
611d3eb7
WYG		 669 return iwl_is_channel_extension(priv, priv->band,
670 le16_to_cpu(priv->staging_rxon.channel),
fad95bf5 671 ht_conf->extension_chan_offset);
47c5196e 672}
7aafef1c 673EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
47c5196e 674
2c2f3b33
TW		 675static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
676{
677 u16 new_val = 0;
678 u16 beacon_factor = 0;
679
680 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
681 new_val = beacon_val / beacon_factor;
682
683 if (!new_val)
684 new_val = max_beacon_val;
685
686 return new_val;
687}
688
689void iwl_setup_rxon_timing(struct iwl_priv *priv)
690{
691 u64 tsf;
692 s32 interval_tm, rem;
693 unsigned long flags;
694 struct ieee80211_conf *conf = NULL;
695 u16 beacon_int;
696
697 conf = ieee80211_get_hw_conf(priv->hw);
698
699 spin_lock_irqsave(&priv->lock, flags);
700 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
701 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
702
703 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
704 beacon_int = priv->beacon_int;
705 priv->rxon_timing.atim_window = 0;
706 } else {
707 beacon_int = priv->vif->bss_conf.beacon_int;
708
709 /* TODO: we need to get atim_window from upper stack
710 * for now we set to 0 */
711 priv->rxon_timing.atim_window = 0;
712 }
713
714 beacon_int = iwl_adjust_beacon_interval(beacon_int,
715 priv->hw_params.max_beacon_itrvl * 1024);
716 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
717
718 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
719 interval_tm = beacon_int * 1024;
720 rem = do_div(tsf, interval_tm);
721 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
722
723 spin_unlock_irqrestore(&priv->lock, flags);
724 IWL_DEBUG_ASSOC(priv,
725 "beacon interval %d beacon timer %d beacon tim %d\n",
726 le16_to_cpu(priv->rxon_timing.beacon_interval),
727 le32_to_cpu(priv->rxon_timing.beacon_init_val),
728 le16_to_cpu(priv->rxon_timing.atim_window));
729}
730EXPORT_SYMBOL(iwl_setup_rxon_timing);
731
8ccde88a
SO		 732void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
733{
734 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
735
736 if (hw_decrypt)
737 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
738 else
739 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
740
741}
742EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
743
744/**
745 * iwl_check_rxon_cmd - validate RXON structure is valid
746 *
747 * NOTE: This is really only useful during development and can eventually
748 * be #ifdef'd out once the driver is stable and folks aren't actively
749 * making changes
750 */
751int iwl_check_rxon_cmd(struct iwl_priv *priv)
752{
753 int error = 0;
754 int counter = 1;
755 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
756
757 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
758 error |= le32_to_cpu(rxon->flags &
759 (RXON_FLG_TGJ_NARROW_BAND_MSK |
760 RXON_FLG_RADAR_DETECT_MSK));
761 if (error)
762 IWL_WARN(priv, "check 24G fields %d | %d\n",
763 counter++, error);
764 } else {
765 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
766 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
767 if (error)
768 IWL_WARN(priv, "check 52 fields %d | %d\n",
769 counter++, error);
770 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
771 if (error)
772 IWL_WARN(priv, "check 52 CCK %d | %d\n",
773 counter++, error);
774 }
775 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
776 if (error)
777 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
778
779 /* make sure basic rates 6Mbps and 1Mbps are supported */
780 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
781 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
782 if (error)
783 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
784
785 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
786 if (error)
787 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
788
789 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
790 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
791 if (error)
792 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
793 counter++, error);
794
795 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
796 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
797 if (error)
798 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
799 counter++, error);
800
801 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
802 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
803 if (error)
804 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
805 counter++, error);
806
807 if (error)
808 IWL_WARN(priv, "Tuning to channel %d\n",
809 le16_to_cpu(rxon->channel));
810
811 if (error) {
812 IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
813 return -1;
814 }
815 return 0;
816}
817EXPORT_SYMBOL(iwl_check_rxon_cmd);
818
819/**
820 * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
821 * @priv: staging_rxon is compared to active_rxon
822 *
823 * If the RXON structure is changing enough to require a new tune,
824 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
825 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
826 */
827int iwl_full_rxon_required(struct iwl_priv *priv)
828{
829
830 /* These items are only settable from the full RXON command */
831 if (!(iwl_is_associated(priv)) ||
832 compare_ether_addr(priv->staging_rxon.bssid_addr,
833 priv->active_rxon.bssid_addr) ||
834 compare_ether_addr(priv->staging_rxon.node_addr,
835 priv->active_rxon.node_addr) ||
836 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
837 priv->active_rxon.wlap_bssid_addr) ||
838 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
839 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
840 (priv->staging_rxon.air_propagation !=
841 priv->active_rxon.air_propagation) ||
842 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
843 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
844 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
845 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
c2105fa7
DH		 846 (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
847 priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
8ccde88a
SO		 848 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
849 return 1;
850
851 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
852 * be updated with the RXON_ASSOC command -- however only some
853 * flag transitions are allowed using RXON_ASSOC */
854
855 /* Check if we are not switching bands */
856 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
857 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
858 return 1;
859
860 /* Check if we are switching association toggle */
861 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
862 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
863 return 1;
864
865 return 0;
866}
867EXPORT_SYMBOL(iwl_full_rxon_required);
868
869u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
870{
871 int i;
872 int rate_mask;
873
874 /* Set rate mask*/
875 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
876 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
877 else
878 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
879
880 /* Find lowest valid rate */
881 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
882 i = iwl_rates[i].next_ieee) {
883 if (rate_mask & (1 << i))
884 return iwl_rates[i].plcp;
885 }
886
887 /* No valid rate was found. Assign the lowest one */
888 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
889 return IWL_RATE_1M_PLCP;
890 else
891 return IWL_RATE_6M_PLCP;
892}
893EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
894
fad95bf5 895void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf)
47c5196e 896{
c1adf9fb 897 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e 898
fad95bf5 899 if (!ht_conf->is_ht) {
a2b0f02e 900 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
42eb7c64 901 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
7aafef1c 902 RXON_FLG_HT40_PROT_MSK |
42eb7c64 903 RXON_FLG_HT_PROT_MSK);
47c5196e 904 return;
42eb7c64 905 }
47c5196e 906
a2b0f02e
WYG		 907 /* FIXME: if the definition of ht_protection changed, the "translation"
908 * will be needed for rxon->flags
909 */
fad95bf5 910 rxon->flags |= cpu_to_le32(ht_conf->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
a2b0f02e
WYG		 911
912 /* Set up channel bandwidth:
7aafef1c 913 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
a2b0f02e
WYG		 914 /* clear the HT channel mode before set the mode */
915 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
916 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
7aafef1c
WYG		 917 if (iwl_is_ht40_tx_allowed(priv, NULL)) {
918 /* pure ht40 */
fad95bf5 919 if (ht_conf->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
a2b0f02e 920 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
508b08e7 921 /* Note: control channel is opposite of extension channel */
fad95bf5 922 switch (ht_conf->extension_chan_offset) {
508b08e7
WYG		 923 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
924 rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
925 break;
926 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
927 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
928 break;
929 }
930 } else {
a2b0f02e 931 /* Note: control channel is opposite of extension channel */
fad95bf5 932 switch (ht_conf->extension_chan_offset) {
a2b0f02e
WYG		 933 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
934 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
935 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
936 break;
937 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
938 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
939 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
940 break;
941 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
942 default:
943 /* channel location only valid if in Mixed mode */
944 IWL_ERR(priv, "invalid extension channel offset\n");
945 break;
946 }
947 }
948 } else {
949 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
47c5196e
TW		 950 }
951
45823531
AK		 952 if (priv->cfg->ops->hcmd->set_rxon_chain)
953 priv->cfg->ops->hcmd->set_rxon_chain(priv);
47c5196e 954
02bb1bea 955 IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
ae5eb026 956 "extension channel offset 0x%x\n",
fad95bf5
JB		 957 le32_to_cpu(rxon->flags), ht_conf->ht_protection,
958 ht_conf->extension_chan_offset);
47c5196e
TW		 959 return;
960}
961EXPORT_SYMBOL(iwl_set_rxon_ht);
962
9e5e6c32
TW		 963#define IWL_NUM_RX_CHAINS_MULTIPLE 3
964#define IWL_NUM_RX_CHAINS_SINGLE 2
965#define IWL_NUM_IDLE_CHAINS_DUAL 2
966#define IWL_NUM_IDLE_CHAINS_SINGLE 1
967
2b396a12
JB		 968/*
969 * Determine how many receiver/antenna chains to use.
970 *
971 * More provides better reception via diversity. Fewer saves power
972 * at the expense of throughput, but only when not in powersave to
973 * start with.
974 *
c7de35cd
RR		 975 * MIMO (dual stream) requires at least 2, but works better with 3.
976 * This does not determine *which* chains to use, just how many.
977 */
28a6b07a 978static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 979{
c7de35cd 980 /* # of Rx chains to use when expecting MIMO. */
02bb1bea 981 if (is_single_rx_stream(priv))
9e5e6c32 982 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 983 else
9e5e6c32 984 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 985}
c7de35cd 986
2b396a12
JB		 987/*
988 * When we are in power saving, there's no difference between
989 * using multiple chains or just a single chain, but due to the
990 * lack of SM PS we lose a lot of throughput if we use just a
991 * single chain.
992 *
993 * Therefore, use the active count here (which will use multiple
994 * chains unless connected to a legacy AP).
995 */
28a6b07a
TW		 996static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
997{
2b396a12 998 return active_cnt;
c7de35cd
RR		 999}
1000
04816448
GE		 1001/* up to 4 chains */
1002static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
1003{
1004 u8 res;
1005 res = (chain_bitmap & BIT(0)) >> 0;
1006 res += (chain_bitmap & BIT(1)) >> 1;
1007 res += (chain_bitmap & BIT(2)) >> 2;
9bddbab3 1008 res += (chain_bitmap & BIT(3)) >> 3;
04816448
GE		 1009 return res;
1010}
1011
4c4df78f
CR		 1012/**
1013 * iwl_is_monitor_mode - Determine if interface in monitor mode
1014 *
1015 * priv->iw_mode is set in add_interface, but add_interface is
1016 * never called for monitor mode. The only way mac80211 informs us about
1017 * monitor mode is through configuring filters (call to configure_filter).
1018 */
279b05d4 1019bool iwl_is_monitor_mode(struct iwl_priv *priv)
4c4df78f
CR		 1020{
1021 return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
1022}
279b05d4 1023EXPORT_SYMBOL(iwl_is_monitor_mode);
4c4df78f 1024
c7de35cd
RR		 1025/**
1026 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1027 *
1028 * Selects how many and which Rx receivers/antennas/chains to use.
1029 * This should not be used for scan command ... it puts data in wrong place.
1030 */
1031void iwl_set_rxon_chain(struct iwl_priv *priv)
1032{
28a6b07a
TW		 1033 bool is_single = is_single_rx_stream(priv);
1034 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 1035 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1036 u32 active_chains;
28a6b07a 1037 u16 rx_chain;
c7de35cd
RR		 1038
1039 /* Tell uCode which antennas are actually connected.
1040 * Before first association, we assume all antennas are connected.
1041 * Just after first association, iwl_chain_noise_calibration()
1042 * checks which antennas actually *are* connected. */
04816448
GE		 1043 if (priv->chain_noise_data.active_chains)
1044 active_chains = priv->chain_noise_data.active_chains;
1045 else
1046 active_chains = priv->hw_params.valid_rx_ant;
1047
1048 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 1049
1050 /* How many receivers should we use? */
28a6b07a
TW		 1051 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
1052 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
1053
28a6b07a 1054
04816448
GE		 1055 /* correct rx chain count according hw settings
1056 * and chain noise calibration
1057 */
1058 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
1059 if (valid_rx_cnt < active_rx_cnt)
1060 active_rx_cnt = valid_rx_cnt;
1061
1062 if (valid_rx_cnt < idle_rx_cnt)
1063 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 1064
1065 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1066 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1067
7b841727
RF		 1068 /* copied from 'iwl_bg_request_scan()' */
1069 /* Force use of chains B and C (0x6) for Rx for 4965
1070 * Avoid A (0x1) because of its off-channel reception on A-band.
1071 * MIMO is not used here, but value is required */
1072 if (iwl_is_monitor_mode(priv) &&
1073 !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
1074 ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
fff7a434
WYG		 1075 rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
1076 rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
1077 rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1078 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
7b841727
RF		 1079 }
1080
28a6b07a
TW		 1081 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
1082
9e5e6c32 1083 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 1084 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1085 else
1086 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1087
e1623446 1088 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 1089 priv->staging_rxon.rx_chain,
1090 active_rx_cnt, idle_rx_cnt);
1091
1092 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1093 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 1094}
1095EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 1096
1097/**
17e72782 1098 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 1099 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
1100 * @channel: Any channel valid for the requested phymode
1101
1102 * In addition to setting the staging RXON, priv->phymode is also set.
1103 *
1104 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
1105 * in the staging RXON flag structure based on the phymode
1106 */
17e72782 1107int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 1108{
17e72782
TW		 1109 enum ieee80211_band band = ch->band;
1110 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
1111
8622e705 1112 if (!iwl_get_channel_info(priv, band, channel)) {
e1623446 1113 IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
bf85ea4f
AK		 1114 channel, band);
1115 return -EINVAL;
1116 }
1117
1118 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
1119 (priv->band == band))
1120 return 0;
1121
1122 priv->staging_rxon.channel = cpu_to_le16(channel);
1123 if (band == IEEE80211_BAND_5GHZ)
1124 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
1125 else
1126 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1127
1128 priv->band = band;
1129
e1623446 1130 IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
bf85ea4f
AK		 1131
1132 return 0;
1133}
c7de35cd 1134EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 1135
8ccde88a
SO		 1136void iwl_set_flags_for_band(struct iwl_priv *priv,
1137 enum ieee80211_band band)
1138{
1139 if (band == IEEE80211_BAND_5GHZ) {
1140 priv->staging_rxon.flags &=
1141 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1142 | RXON_FLG_CCK_MSK);
1143 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1144 } else {
1145 /* Copied from iwl_post_associate() */
1146 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
1147 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1148 else
1149 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1150
1151 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
1152 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1153
1154 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1155 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1156 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
1157 }
1158}
8ccde88a
SO		 1159
1160/*
1161 * initialize rxon structure with default values from eeprom
1162 */
1163void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
1164{
1165 const struct iwl_channel_info *ch_info;
1166
1167 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
1168
1169 switch (mode) {
1170 case NL80211_IFTYPE_AP:
1171 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
1172 break;
1173
1174 case NL80211_IFTYPE_STATION:
1175 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
1176 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
1177 break;
1178
1179 case NL80211_IFTYPE_ADHOC:
1180 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1181 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1182 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
1183 RXON_FILTER_ACCEPT_GRP_MSK;
1184 break;
1185
8ccde88a
SO		 1186 default:
1187 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
1188 break;
1189 }
1190
1191#if 0
1192 /* TODO: Figure out when short_preamble would be set and cache from
1193 * that */
1194 if (!hw_to_local(priv->hw)->short_preamble)
1195 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1196 else
1197 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1198#endif
1199
1200 ch_info = iwl_get_channel_info(priv, priv->band,
1201 le16_to_cpu(priv->active_rxon.channel));
1202
1203 if (!ch_info)
1204 ch_info = &priv->channel_info[0];
1205
1206 /*
1207 * in some case A channels are all non IBSS
1208 * in this case force B/G channel
1209 */
1210 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
1211 !(is_channel_ibss(ch_info)))
1212 ch_info = &priv->channel_info[0];
1213
1214 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
1215 priv->band = ch_info->band;
1216
1217 iwl_set_flags_for_band(priv, priv->band);
1218
1219 priv->staging_rxon.ofdm_basic_rates =
1220 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1221 priv->staging_rxon.cck_basic_rates =
1222 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1223
a2b0f02e
WYG		 1224 /* clear both MIX and PURE40 mode flag */
1225 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
1226 RXON_FLG_CHANNEL_MODE_PURE_40);
8ccde88a
SO		 1227 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1228 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
1229 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
1230 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
11397a65 1231 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
8ccde88a
SO		 1232}
1233EXPORT_SYMBOL(iwl_connection_init_rx_config);
1234
782571f4 1235static void iwl_set_rate(struct iwl_priv *priv)
8ccde88a
SO		 1236{
1237 const struct ieee80211_supported_band *hw = NULL;
1238 struct ieee80211_rate *rate;
1239 int i;
1240
1241 hw = iwl_get_hw_mode(priv, priv->band);
1242 if (!hw) {
1243 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
1244 return;
1245 }
1246
1247 priv->active_rate = 0;
1248 priv->active_rate_basic = 0;
1249
1250 for (i = 0; i < hw->n_bitrates; i++) {
1251 rate = &(hw->bitrates[i]);
5027309b 1252 if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
8ccde88a
SO		 1253 priv->active_rate |= (1 << rate->hw_value);
1254 }
1255
e1623446 1256 IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
8ccde88a
SO		 1257 priv->active_rate, priv->active_rate_basic);
1258
1259 /*
1260 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
1261 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
1262 * OFDM
1263 */
1264 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
1265 priv->staging_rxon.cck_basic_rates =
1266 ((priv->active_rate_basic &
1267 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
1268 else
1269 priv->staging_rxon.cck_basic_rates =
1270 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1271
1272 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
1273 priv->staging_rxon.ofdm_basic_rates =
1274 ((priv->active_rate_basic &
1275 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
1276 IWL_FIRST_OFDM_RATE) & 0xFF;
1277 else
1278 priv->staging_rxon.ofdm_basic_rates =
1279 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1280}
8ccde88a
SO		 1281
1282void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1283{
2f301227 1284 struct iwl_rx_packet *pkt = rxb_addr(rxb);
8ccde88a
SO		 1285 struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
1286 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
e1623446 1287 IWL_DEBUG_11H(priv, "CSA notif: channel %d, status %d\n",
8ccde88a
SO		 1288 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
1289 rxon->channel = csa->channel;
1290 priv->staging_rxon.channel = csa->channel;
1291}
1292EXPORT_SYMBOL(iwl_rx_csa);
1293
1294#ifdef CONFIG_IWLWIFI_DEBUG
1295static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
1296{
1297 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
1298
e1623446 1299 IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
3d816c77 1300 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e1623446
TW		 1301 IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
1302 IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
1303 IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
8ccde88a 1304 le32_to_cpu(rxon->filter_flags));
e1623446
TW		 1305 IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
1306 IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
8ccde88a 1307 rxon->ofdm_basic_rates);
e1623446
TW		 1308 IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
1309 IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
1310 IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
1311 IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
8ccde88a 1312}
6686d17e 1313#endif
8ccde88a
SO		 1314/**
1315 * iwl_irq_handle_error - called for HW or SW error interrupt from card
1316 */
1317void iwl_irq_handle_error(struct iwl_priv *priv)
1318{
1319 /* Set the FW error flag -- cleared on iwl_down */
1320 set_bit(STATUS_FW_ERROR, &priv->status);
1321
1322 /* Cancel currently queued command. */
1323 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1324
1325#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1326 if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) {
b7a79404
RC		 1327 priv->cfg->ops->lib->dump_nic_error_log(priv);
1328 priv->cfg->ops->lib->dump_nic_event_log(priv);
8ccde88a
SO		 1329 iwl_print_rx_config_cmd(priv);
1330 }
1331#endif
1332
1333 wake_up_interruptible(&priv->wait_command_queue);
1334
1335 /* Keep the restart process from trying to send host
1336 * commands by clearing the INIT status bit */
1337 clear_bit(STATUS_READY, &priv->status);
1338
1339 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 1340 IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
8ccde88a
SO		 1341 "Restarting adapter due to uCode error.\n");
1342
8ccde88a
SO		 1343 if (priv->cfg->mod_params->restart_fw)
1344 queue_work(priv->workqueue, &priv->restart);
1345 }
1346}
1347EXPORT_SYMBOL(iwl_irq_handle_error);
1348
d68b603c
AK		 1349int iwl_apm_stop_master(struct iwl_priv *priv)
1350{
1351 unsigned long flags;
1352
1353 spin_lock_irqsave(&priv->lock, flags);
1354
1355 /* set stop master bit */
1356 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1357
1739d332 1358 iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
d68b603c
AK		 1359 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1360
1361 spin_unlock_irqrestore(&priv->lock, flags);
1362 IWL_DEBUG_INFO(priv, "stop master\n");
1363
1364 return 0;
1365}
1366EXPORT_SYMBOL(iwl_apm_stop_master);
1367
1368void iwl_apm_stop(struct iwl_priv *priv)
1369{
1370 unsigned long flags;
1371
fadb3582
BC		 1372 IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
1373
d68b603c
AK		 1374 iwl_apm_stop_master(priv);
1375
1376 spin_lock_irqsave(&priv->lock, flags);
1377
1378 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1379
1380 udelay(10);
1381 /* clear "init complete" move adapter D0A* --> D0U state */
1382 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1383 spin_unlock_irqrestore(&priv->lock, flags);
1384}
1385EXPORT_SYMBOL(iwl_apm_stop);
1386
fadb3582
BC		 1387
1388/*
1389 * Start up NIC's basic functionality after it has been reset
1390 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1391 * NOTE: This does not load uCode nor start the embedded processor
1392 */
1393int iwl_apm_init(struct iwl_priv *priv)
1394{
1395 int ret = 0;
1396 u16 lctl;
1397
1398 IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
1399
1400 /*
1401 * Use "set_bit" below rather than "write", to preserve any hardware
1402 * bits already set by default after reset.
1403 */
1404
1405 /* Disable L0S exit timer (platform NMI Work/Around) */
1406 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1407 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1408
1409 /*
1410 * Disable L0s without affecting L1;
1411 * don't wait for ICH L0s (ICH bug W/A)
1412 */
1413 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1414 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1415
1416 /* Set FH wait threshold to maximum (HW error during stress W/A) */
1417 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
1418
1419 /*
1420 * Enable HAP INTA (interrupt from management bus) to
1421 * wake device's PCI Express link L1a -> L0s
1422 * NOTE: This is no-op for 3945 (non-existant bit)
1423 */
1424 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1425 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
1426
1427 /*
1428 * HW bug W/A - costs negligible power consumption ...
1429 * Check if BIOS (or OS) enabled L1-ASPM on this device
1430 */
1431 if (priv->cfg->set_l0s) {
1432 lctl = iwl_pcie_link_ctl(priv);
1433 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
1434 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
1435 /* L1-ASPM enabled; disable(!) L0S */
1436 iwl_set_bit(priv, CSR_GIO_REG,
1437 CSR_GIO_REG_VAL_L0S_ENABLED);
1438 IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
1439 } else {
1440 /* L1-ASPM disabled; enable(!) L0S */
1441 iwl_clear_bit(priv, CSR_GIO_REG,
1442 CSR_GIO_REG_VAL_L0S_ENABLED);
1443 IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
1444 }
1445 }
1446
1447 /* Configure analog phase-lock-loop before activating to D0A */
1448 if (priv->cfg->pll_cfg_val)
1449 iwl_set_bit(priv, CSR_ANA_PLL_CFG, priv->cfg->pll_cfg_val);
1450
1451 /*
1452 * Set "initialization complete" bit to move adapter from
1453 * D0U* --> D0A* (powered-up active) state.
1454 */
1455 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1456
1457 /*
1458 * Wait for clock stabilization; once stabilized, access to
1459 * device-internal resources is supported, e.g. iwl_write_prph()
1460 * and accesses to uCode SRAM.
1461 */
1462 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
1463 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1464 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1465 if (ret < 0) {
1466 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1467 goto out;
1468 }
1469
1470 /*
1471 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
1472 * BSM (Boostrap State Machine) is only in 3945 and 4965;
1473 * later devices (i.e. 5000 and later) have non-volatile SRAM,
1474 * and don't need BSM to restore data after power-saving sleep.
1475 *
1476 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
1477 * do not disable clocks. This preserves any hardware bits already
1478 * set by default in "CLK_CTRL_REG" after reset.
1479 */
1480 if (priv->cfg->use_bsm)
1481 iwl_write_prph(priv, APMG_CLK_EN_REG,
1482 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
1483 else
1484 iwl_write_prph(priv, APMG_CLK_EN_REG,
1485 APMG_CLK_VAL_DMA_CLK_RQT);
1486 udelay(20);
1487
1488 /* Disable L1-Active */
1489 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1490 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1491
1492out:
1493 return ret;
1494}
1495EXPORT_SYMBOL(iwl_apm_init);
1496
1497
1498
8ccde88a
SO		 1499void iwl_configure_filter(struct ieee80211_hw *hw,
1500 unsigned int changed_flags,
1501 unsigned int *total_flags,
3ac64bee 1502 u64 multicast)
8ccde88a
SO		 1503{
1504 struct iwl_priv *priv = hw->priv;
1505 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
1506
e1623446 1507 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
8ccde88a
SO		 1508 changed_flags, *total_flags);
1509
1510 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
1511 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
1512 *filter_flags |= RXON_FILTER_PROMISC_MSK;
1513 else
1514 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
1515 }
1516 if (changed_flags & FIF_ALLMULTI) {
1517 if (*total_flags & FIF_ALLMULTI)
1518 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
1519 else
1520 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
1521 }
1522 if (changed_flags & FIF_CONTROL) {
1523 if (*total_flags & FIF_CONTROL)
1524 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
1525 else
1526 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
1527 }
1528 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1529 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1530 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
1531 else
1532 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
1533 }
1534
1535 /* We avoid iwl_commit_rxon here to commit the new filter flags
1536 * since mac80211 will call ieee80211_hw_config immediately.
1537 * (mc_list is not supported at this time). Otherwise, we need to
1538 * queue a background iwl_commit_rxon work.
1539 */
1540
1541 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
1542 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
1543}
1544EXPORT_SYMBOL(iwl_configure_filter);
1545
da154e30
RR		 1546int iwl_set_hw_params(struct iwl_priv *priv)
1547{
da154e30
RR		 1548 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1549 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1550 if (priv->cfg->mod_params->amsdu_size_8K)
2f301227 1551 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
da154e30 1552 else
2f301227 1553 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
da154e30 1554
2c2f3b33
TW		 1555 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
1556
49779293
RR		 1557 if (priv->cfg->mod_params->disable_11n)
1558 priv->cfg->sku &= ~IWL_SKU_N;
1559
da154e30
RR		 1560 /* Device-specific setup */
1561 return priv->cfg->ops->lib->set_hw_params(priv);
1562}
1563EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956
TW		 1564
1565int iwl_init_drv(struct iwl_priv *priv)
c7de35cd
RR		 1566{
1567 int ret;
c7de35cd 1568
c7de35cd
RR		 1569 priv->ibss_beacon = NULL;
1570
1571 spin_lock_init(&priv->lock);
c7de35cd
RR		 1572 spin_lock_init(&priv->sta_lock);
1573 spin_lock_init(&priv->hcmd_lock);
c7de35cd 1574
c7de35cd
RR		 1575 INIT_LIST_HEAD(&priv->free_frames);
1576
1577 mutex_init(&priv->mutex);
1578
1579 /* Clear the driver's (not device's) station table */
c587de0b 1580 iwl_clear_stations_table(priv);
c7de35cd 1581
c7de35cd
RR		 1582 priv->ieee_channels = NULL;
1583 priv->ieee_rates = NULL;
1584 priv->band = IEEE80211_BAND_2GHZ;
1585
05c914fe 1586 priv->iw_mode = NL80211_IFTYPE_STATION;
c7de35cd 1587
c7de35cd 1588 /* Choose which receivers/antennas to use */
45823531
AK		 1589 if (priv->cfg->ops->hcmd->set_rxon_chain)
1590 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1591
f53696de 1592 iwl_init_scan_params(priv);
c7de35cd
RR		 1593
1594 iwl_reset_qos(priv);
1595
1596 priv->qos_data.qos_active = 0;
1597 priv->qos_data.qos_cap.val = 0;
1598
c7de35cd 1599 priv->rates_mask = IWL_RATES_MASK;
02eec9c5
WYG		 1600 /* Set the tx_power_user_lmt to the lowest power level
1601 * this value will get overwritten by channel max power avg
1602 * from eeprom */
1603 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
c7de35cd
RR		 1604
1605 ret = iwl_init_channel_map(priv);
1606 if (ret) {
15b1687c 1607 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
c7de35cd
RR		 1608 goto err;
1609 }
1610
1611 ret = iwlcore_init_geos(priv);
1612 if (ret) {
15b1687c 1613 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
c7de35cd
RR		 1614 goto err_free_channel_map;
1615 }
534166de 1616 iwlcore_init_hw_rates(priv, priv->ieee_rates);
c7de35cd 1617
c7de35cd
RR		 1618 return 0;
1619
c7de35cd
RR		 1620err_free_channel_map:
1621 iwl_free_channel_map(priv);
1622err:
1623 return ret;
1624}
6ba87956 1625EXPORT_SYMBOL(iwl_init_drv);
c7de35cd 1626
630fe9b6
TW		 1627int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1628{
1629 int ret = 0;
5eadd94b
WYG		 1630 s8 prev_tx_power = priv->tx_power_user_lmt;
1631
630fe9b6 1632 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
daf518de
WF		 1633 IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
1634 tx_power,
1635 IWL_TX_POWER_TARGET_POWER_MIN);
630fe9b6
TW		 1636 return -EINVAL;
1637 }
1638
dc1b0973 1639 if (tx_power > priv->tx_power_device_lmt) {
08f2d58d
WYG		 1640 IWL_WARN(priv,
1641 "Requested user TXPOWER %d above upper limit %d.\n",
dc1b0973 1642 tx_power, priv->tx_power_device_lmt);
630fe9b6
TW		 1643 return -EINVAL;
1644 }
1645
1646 if (priv->tx_power_user_lmt != tx_power)
1647 force = true;
1648
019fb97d 1649 /* if nic is not up don't send command */
5eadd94b
WYG		 1650 if (iwl_is_ready_rf(priv)) {
1651 priv->tx_power_user_lmt = tx_power;
1652 if (force && priv->cfg->ops->lib->send_tx_power)
1653 ret = priv->cfg->ops->lib->send_tx_power(priv);
1654 else if (!priv->cfg->ops->lib->send_tx_power)
1655 ret = -EOPNOTSUPP;
1656 /*
1657 * if fail to set tx_power, restore the orig. tx power
1658 */
1659 if (ret)
1660 priv->tx_power_user_lmt = prev_tx_power;
1661 }
630fe9b6 1662
5eadd94b
WYG		 1663 /*
1664 * Even this is an async host command, the command
1665 * will always report success from uCode
1666 * So once driver can placing the command into the queue
1667 * successfully, driver can use priv->tx_power_user_lmt
1668 * to reflect the current tx power
1669 */
630fe9b6
TW		 1670 return ret;
1671}
1672EXPORT_SYMBOL(iwl_set_tx_power);
1673
6ba87956 1674void iwl_uninit_drv(struct iwl_priv *priv)
bf85ea4f 1675{
6e21f2c1 1676 iwl_calib_free_results(priv);
6ba87956
TW		 1677 iwlcore_free_geos(priv);
1678 iwl_free_channel_map(priv);
261415f7 1679 kfree(priv->scan);
bf85ea4f 1680}
6ba87956 1681EXPORT_SYMBOL(iwl_uninit_drv);
bf85ea4f 1682
ef850d7c
MA		 1683#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1684
1685/* Free dram table */
1686void iwl_free_isr_ict(struct iwl_priv *priv)
1687{
1688 if (priv->ict_tbl_vir) {
1689 pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
1690 PAGE_SIZE, priv->ict_tbl_vir,
1691 priv->ict_tbl_dma);
1692 priv->ict_tbl_vir = NULL;
1693 }
1694}
1695EXPORT_SYMBOL(iwl_free_isr_ict);
1696
1697
1698/* allocate dram shared table it is a PAGE_SIZE aligned
1699 * also reset all data related to ICT table interrupt.
1700 */
1701int iwl_alloc_isr_ict(struct iwl_priv *priv)
1702{
1703
1704 if (priv->cfg->use_isr_legacy)
1705 return 0;
1706 /* allocate shrared data table */
1707 priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
1708 ICT_COUNT) + PAGE_SIZE,
1709 &priv->ict_tbl_dma);
1710 if (!priv->ict_tbl_vir)
1711 return -ENOMEM;
1712
1713 /* align table to PAGE_SIZE boundry */
1714 priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
1715
1716 IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1717 (unsigned long long)priv->ict_tbl_dma,
1718 (unsigned long long)priv->aligned_ict_tbl_dma,
1719 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1720
1721 priv->ict_tbl = priv->ict_tbl_vir +
1722 (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
1723
1724 IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
1725 priv->ict_tbl, priv->ict_tbl_vir,
1726 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1727
1728 /* reset table and index to all 0 */
1729 memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1730 priv->ict_index = 0;
1731
40cefda9
MA		 1732 /* add periodic RX interrupt */
1733 priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
ef850d7c
MA		 1734 return 0;
1735}
1736EXPORT_SYMBOL(iwl_alloc_isr_ict);
1737
1738/* Device is going up inform it about using ICT interrupt table,
1739 * also we need to tell the driver to start using ICT interrupt.
1740 */
1741int iwl_reset_ict(struct iwl_priv *priv)
1742{
1743 u32 val;
1744 unsigned long flags;
1745
1746 if (!priv->ict_tbl_vir)
1747 return 0;
1748
1749 spin_lock_irqsave(&priv->lock, flags);
1750 iwl_disable_interrupts(priv);
1751
1303dcfd 1752 memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
ef850d7c
MA		 1753
1754 val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
1755
1756 val |= CSR_DRAM_INT_TBL_ENABLE;
1757 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1758
1759 IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
1760 "aligned dma address %Lx\n",
1761 val, (unsigned long long)priv->aligned_ict_tbl_dma);
1762
1763 iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
1764 priv->use_ict = true;
1765 priv->ict_index = 0;
40cefda9 1766 iwl_write32(priv, CSR_INT, priv->inta_mask);
ef850d7c
MA		 1767 iwl_enable_interrupts(priv);
1768 spin_unlock_irqrestore(&priv->lock, flags);
1769
1770 return 0;
1771}
1772EXPORT_SYMBOL(iwl_reset_ict);
1773
1774/* Device is going down disable ict interrupt usage */
1775void iwl_disable_ict(struct iwl_priv *priv)
1776{
1777 unsigned long flags;
1778
1779 spin_lock_irqsave(&priv->lock, flags);
1780 priv->use_ict = false;
1781 spin_unlock_irqrestore(&priv->lock, flags);
1782}
1783EXPORT_SYMBOL(iwl_disable_ict);
1784
1785/* interrupt handler using ict table, with this interrupt driver will
1786 * stop using INTA register to get device's interrupt, reading this register
1787 * is expensive, device will write interrupts in ICT dram table, increment
1788 * index then will fire interrupt to driver, driver will OR all ICT table
1789 * entries from current index up to table entry with 0 value. the result is
1790 * the interrupt we need to service, driver will set the entries back to 0 and
1791 * set index.
1792 */
1793irqreturn_t iwl_isr_ict(int irq, void *data)
1794{
1795 struct iwl_priv *priv = data;
1796 u32 inta, inta_mask;
1797 u32 val = 0;
1798
1799 if (!priv)
1800 return IRQ_NONE;
1801
1802 /* dram interrupt table not set yet,
1803 * use legacy interrupt.
1804 */
1805 if (!priv->use_ict)
1806 return iwl_isr(irq, data);
1807
1808 spin_lock(&priv->lock);
1809
1810 /* Disable (but don't clear!) interrupts here to avoid
1811 * back-to-back ISRs and sporadic interrupts from our NIC.
1812 * If we have something to service, the tasklet will re-enable ints.
1813 * If we *don't* have something, we'll re-enable before leaving here.
1814 */
1815 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1816 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1817
1818
1819 /* Ignore interrupt if there's nothing in NIC to service.
1820 * This may be due to IRQ shared with another device,
1821 * or due to sporadic interrupts thrown from our NIC. */
1822 if (!priv->ict_tbl[priv->ict_index]) {
1823 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1824 goto none;
1825 }
1826
1827 /* read all entries that not 0 start with ict_index */
1828 while (priv->ict_tbl[priv->ict_index]) {
1829
1303dcfd 1830 val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
ef850d7c 1831 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
1303dcfd
JB		 1832 priv->ict_index,
1833 le32_to_cpu(priv->ict_tbl[priv->ict_index]));
ef850d7c
MA		 1834 priv->ict_tbl[priv->ict_index] = 0;
1835 priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
1303dcfd 1836 ICT_COUNT);
ef850d7c
MA		 1837
1838 }
1839
1840 /* We should not get this value, just ignore it. */
1841 if (val == 0xffffffff)
1842 val = 0;
1843
1844 inta = (0xff & val) | ((0xff00 & val) << 16);
1845 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1846 inta, inta_mask, val);
1847
40cefda9 1848 inta &= priv->inta_mask;
ef850d7c
MA		 1849 priv->inta |= inta;
1850
1851 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1852 if (likely(inta))
1853 tasklet_schedule(&priv->irq_tasklet);
1854 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
1855 /* Allow interrupt if was disabled by this handler and
1856 * no tasklet was schedules, We should not enable interrupt,
1857 * tasklet will enable it.
1858 */
1859 iwl_enable_interrupts(priv);
1860 }
1861
1862 spin_unlock(&priv->lock);
1863 return IRQ_HANDLED;
1864
1865 none:
1866 /* re-enable interrupts here since we don't have anything to service.
1867 * only Re-enable if disabled by irq.
1868 */
1869 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1870 iwl_enable_interrupts(priv);
1871
1872 spin_unlock(&priv->lock);
1873 return IRQ_NONE;
1874}
1875EXPORT_SYMBOL(iwl_isr_ict);
1876
1877
1878static irqreturn_t iwl_isr(int irq, void *data)
1879{
1880 struct iwl_priv *priv = data;
1881 u32 inta, inta_mask;
d651ae32 1882#ifdef CONFIG_IWLWIFI_DEBUG
ef850d7c 1883 u32 inta_fh;
d651ae32 1884#endif
ef850d7c
MA		 1885 if (!priv)
1886 return IRQ_NONE;
1887
1888 spin_lock(&priv->lock);
1889
1890 /* Disable (but don't clear!) interrupts here to avoid
1891 * back-to-back ISRs and sporadic interrupts from our NIC.
1892 * If we have something to service, the tasklet will re-enable ints.
1893 * If we *don't* have something, we'll re-enable before leaving here. */
1894 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1895 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1896
1897 /* Discover which interrupts are active/pending */
1898 inta = iwl_read32(priv, CSR_INT);
1899
1900 /* Ignore interrupt if there's nothing in NIC to service.
1901 * This may be due to IRQ shared with another device,
1902 * or due to sporadic interrupts thrown from our NIC. */
1903 if (!inta) {
1904 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1905 goto none;
1906 }
1907
1908 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1909 /* Hardware disappeared. It might have already raised
1910 * an interrupt */
1911 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1912 goto unplugged;
1913 }
1914
1915#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1916 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1917 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1918 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
1919 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1920 }
1921#endif
1922
1923 priv->inta |= inta;
1924 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1925 if (likely(inta))
1926 tasklet_schedule(&priv->irq_tasklet);
1927 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1928 iwl_enable_interrupts(priv);
1929
1930 unplugged:
1931 spin_unlock(&priv->lock);
1932 return IRQ_HANDLED;
1933
1934 none:
1935 /* re-enable interrupts here since we don't have anything to service. */
1936 /* only Re-enable if diabled by irq and no schedules tasklet. */
1937 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1938 iwl_enable_interrupts(priv);
1939
1940 spin_unlock(&priv->lock);
1941 return IRQ_NONE;
1942}
1943
1944irqreturn_t iwl_isr_legacy(int irq, void *data)
f17d08a6
AK		 1945{
1946 struct iwl_priv *priv = data;
1947 u32 inta, inta_mask;
1948 u32 inta_fh;
1949 if (!priv)
1950 return IRQ_NONE;
1951
1952 spin_lock(&priv->lock);
1953
1954 /* Disable (but don't clear!) interrupts here to avoid
1955 * back-to-back ISRs and sporadic interrupts from our NIC.
1956 * If we have something to service, the tasklet will re-enable ints.
1957 * If we *don't* have something, we'll re-enable before leaving here. */
1958 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1959 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1960
1961 /* Discover which interrupts are active/pending */
1962 inta = iwl_read32(priv, CSR_INT);
1963 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1964
1965 /* Ignore interrupt if there's nothing in NIC to service.
1966 * This may be due to IRQ shared with another device,
1967 * or due to sporadic interrupts thrown from our NIC. */
1968 if (!inta && !inta_fh) {
1969 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
1970 goto none;
1971 }
1972
1973 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1974 /* Hardware disappeared. It might have already raised
1975 * an interrupt */
1976 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1977 goto unplugged;
1978 }
1979
1980 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1981 inta, inta_mask, inta_fh);
1982
1983 inta &= ~CSR_INT_BIT_SCD;
1984
1985 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1986 if (likely(inta || inta_fh))
1987 tasklet_schedule(&priv->irq_tasklet);
1988
1989 unplugged:
1990 spin_unlock(&priv->lock);
1991 return IRQ_HANDLED;
1992
1993 none:
1994 /* re-enable interrupts here since we don't have anything to service. */
1995 /* only Re-enable if diabled by irq */
1996 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1997 iwl_enable_interrupts(priv);
1998 spin_unlock(&priv->lock);
1999 return IRQ_NONE;
2000}
ef850d7c 2001EXPORT_SYMBOL(iwl_isr_legacy);
f17d08a6 2002
17f841cd
SO		 2003int iwl_send_bt_config(struct iwl_priv *priv)
2004{
2005 struct iwl_bt_cmd bt_cmd = {
456d0f76
WYG		 2006 .flags = BT_COEX_MODE_4W,
2007 .lead_time = BT_LEAD_TIME_DEF,
2008 .max_kill = BT_MAX_KILL_DEF,
17f841cd
SO		 2009 .kill_ack_mask = 0,
2010 .kill_cts_mask = 0,
2011 };
2012
2013 return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
2014 sizeof(struct iwl_bt_cmd), &bt_cmd);
2015}
2016EXPORT_SYMBOL(iwl_send_bt_config);
2017
49ea8596
EG		 2018int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
2019{
2020 u32 stat_flags = 0;
2021 struct iwl_host_cmd cmd = {
2022 .id = REPLY_STATISTICS_CMD,
c2acea8e 2023 .flags = flags,
49ea8596
EG		 2024 .len = sizeof(stat_flags),
2025 .data = (u8 *) &stat_flags,
2026 };
2027 return iwl_send_cmd(priv, &cmd);
2028}
2029EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 2030
b0692f2f
EG		 2031/**
2032 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
2033 * using sample data 100 bytes apart. If these sample points are good,
2034 * it's a pretty good bet that everything between them is good, too.
2035 */
2036static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
2037{
2038 u32 val;
2039 int ret = 0;
2040 u32 errcnt = 0;
2041 u32 i;
2042
e1623446 2043 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2044
b0692f2f
EG		 2045 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2046 /* read data comes through single port, auto-incr addr */
2047 /* NOTE: Use the debugless read so we don't flood kernel log
2048 * if IWL_DL_IO is set */
2049 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2050 i + IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2051 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2052 if (val != le32_to_cpu(*image)) {
2053 ret = -EIO;
2054 errcnt++;
2055 if (errcnt >= 3)
2056 break;
2057 }
2058 }
2059
b0692f2f
EG		 2060 return ret;
2061}
2062
2063/**
2064 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
2065 * looking at all data.
2066 */
2067static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
2068 u32 len)
2069{
2070 u32 val;
2071 u32 save_len = len;
2072 int ret = 0;
2073 u32 errcnt;
2074
e1623446 2075 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2076
250bdd21
SO		 2077 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
2078 IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2079
2080 errcnt = 0;
2081 for (; len > 0; len -= sizeof(u32), image++) {
2082 /* read data comes through single port, auto-incr addr */
2083 /* NOTE: Use the debugless read so we don't flood kernel log
2084 * if IWL_DL_IO is set */
2085 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2086 if (val != le32_to_cpu(*image)) {
15b1687c 2087 IWL_ERR(priv, "uCode INST section is invalid at "
b0692f2f
EG		 2088 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2089 save_len - len, val, le32_to_cpu(*image));
2090 ret = -EIO;
2091 errcnt++;
2092 if (errcnt >= 20)
2093 break;
2094 }
2095 }
2096
b0692f2f 2097 if (!errcnt)
e1623446
TW		 2098 IWL_DEBUG_INFO(priv,
2099 "ucode image in INSTRUCTION memory is good\n");
b0692f2f
EG		 2100
2101 return ret;
2102}
2103
2104/**
2105 * iwl_verify_ucode - determine which instruction image is in SRAM,
2106 * and verify its contents
2107 */
2108int iwl_verify_ucode(struct iwl_priv *priv)
2109{
2110 __le32 *image;
2111 u32 len;
2112 int ret;
2113
2114 /* Try bootstrap */
2115 image = (__le32 *)priv->ucode_boot.v_addr;
2116 len = priv->ucode_boot.len;
2117 ret = iwlcore_verify_inst_sparse(priv, image, len);
2118 if (!ret) {
e1623446 2119 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b0692f2f
EG		 2120 return 0;
2121 }
2122
2123 /* Try initialize */
2124 image = (__le32 *)priv->ucode_init.v_addr;
2125 len = priv->ucode_init.len;
2126 ret = iwlcore_verify_inst_sparse(priv, image, len);
2127 if (!ret) {
e1623446 2128 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b0692f2f
EG		 2129 return 0;
2130 }
2131
2132 /* Try runtime/protocol */
2133 image = (__le32 *)priv->ucode_code.v_addr;
2134 len = priv->ucode_code.len;
2135 ret = iwlcore_verify_inst_sparse(priv, image, len);
2136 if (!ret) {
e1623446 2137 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b0692f2f
EG		 2138 return 0;
2139 }
2140
15b1687c 2141 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b0692f2f
EG		 2142
2143 /* Since nothing seems to match, show first several data entries in
2144 * instruction SRAM, so maybe visual inspection will give a clue.
2145 * Selection of bootstrap image (vs. other images) is arbitrary. */
2146 image = (__le32 *)priv->ucode_boot.v_addr;
2147 len = priv->ucode_boot.len;
2148 ret = iwl_verify_inst_full(priv, image, len);
2149
2150 return ret;
2151}
2152EXPORT_SYMBOL(iwl_verify_ucode);
2153
56e12615 2154
47f4a587
EG		 2155void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2156{
2157 struct iwl_ct_kill_config cmd;
672639de 2158 struct iwl_ct_kill_throttling_config adv_cmd;
47f4a587
EG		 2159 unsigned long flags;
2160 int ret = 0;
2161
2162 spin_lock_irqsave(&priv->lock, flags);
2163 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2164 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2165 spin_unlock_irqrestore(&priv->lock, flags);
3ad3b92a 2166 priv->thermal_throttle.ct_kill_toggle = false;
47f4a587 2167
480e8407 2168 if (priv->cfg->support_ct_kill_exit) {
672639de
WYG		 2169 adv_cmd.critical_temperature_enter =
2170 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2171 adv_cmd.critical_temperature_exit =
2172 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2173
2174 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2175 sizeof(adv_cmd), &adv_cmd);
d91b1ba3
WYG		 2176 if (ret)
2177 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2178 else
2179 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2180 "succeeded, "
2181 "critical temperature enter is %d,"
2182 "exit is %d\n",
2183 priv->hw_params.ct_kill_threshold,
2184 priv->hw_params.ct_kill_exit_threshold);
480e8407 2185 } else {
672639de
WYG		 2186 cmd.critical_temperature_R =
2187 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 2188
672639de
WYG		 2189 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2190 sizeof(cmd), &cmd);
d91b1ba3
WYG		 2191 if (ret)
2192 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2193 else
2194 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2195 "succeeded, "
2196 "critical temperature is %d\n",
2197 priv->hw_params.ct_kill_threshold);
672639de 2198 }
47f4a587
EG		 2199}
2200EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f 2201
0ad91a35 2202
14a08a7f
EG		 2203/*
2204 * CARD_STATE_CMD
2205 *
2206 * Use: Sets the device's internal card state to enable, disable, or halt
2207 *
2208 * When in the 'enable' state the card operates as normal.
2209 * When in the 'disable' state, the card enters into a low power mode.
2210 * When in the 'halt' state, the card is shut down and must be fully
2211 * restarted to come back on.
2212 */
c496294e 2213int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
14a08a7f
EG		 2214{
2215 struct iwl_host_cmd cmd = {
2216 .id = REPLY_CARD_STATE_CMD,
2217 .len = sizeof(u32),
2218 .data = &flags,
c2acea8e 2219 .flags = meta_flag,
14a08a7f
EG		 2220 };
2221
2222 return iwl_send_cmd(priv, &cmd);
2223}
2224
030f05ed
AK		 2225void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
2226 struct iwl_rx_mem_buffer *rxb)
2227{
2228#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 2229 struct iwl_rx_packet *pkt = rxb_addr(rxb);
030f05ed
AK		 2230 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
2231 IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
2232 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2233#endif
2234}
2235EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
2236
2237void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
2238 struct iwl_rx_mem_buffer *rxb)
2239{
2f301227 2240 struct iwl_rx_packet *pkt = rxb_addr(rxb);
396887a2 2241 u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
030f05ed 2242 IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
396887a2
DH		 2243 "notification for %s:\n", len,
2244 get_cmd_string(pkt->hdr.cmd));
2245 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len);
030f05ed
AK		 2246}
2247EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
261b9c33
AK		 2248
2249void iwl_rx_reply_error(struct iwl_priv *priv,
2250 struct iwl_rx_mem_buffer *rxb)
2251{
2f301227 2252 struct iwl_rx_packet *pkt = rxb_addr(rxb);
261b9c33
AK		 2253
2254 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
2255 "seq 0x%04X ser 0x%08X\n",
2256 le32_to_cpu(pkt->u.err_resp.error_type),
2257 get_cmd_string(pkt->u.err_resp.cmd_id),
2258 pkt->u.err_resp.cmd_id,
2259 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2260 le32_to_cpu(pkt->u.err_resp.error_info));
2261}
2262EXPORT_SYMBOL(iwl_rx_reply_error);
2263
a83b9141
WYG		 2264void iwl_clear_isr_stats(struct iwl_priv *priv)
2265{
2266 memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
2267}
a83b9141 2268
488829f1
AK		 2269int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
2270 const struct ieee80211_tx_queue_params *params)
2271{
2272 struct iwl_priv *priv = hw->priv;
2273 unsigned long flags;
2274 int q;
2275
2276 IWL_DEBUG_MAC80211(priv, "enter\n");
2277
2278 if (!iwl_is_ready_rf(priv)) {
2279 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2280 return -EIO;
2281 }
2282
2283 if (queue >= AC_NUM) {
2284 IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
2285 return 0;
2286 }
2287
2288 q = AC_NUM - 1 - queue;
2289
2290 spin_lock_irqsave(&priv->lock, flags);
2291
2292 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
2293 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
2294 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
2295 priv->qos_data.def_qos_parm.ac[q].edca_txop =
2296 cpu_to_le16((params->txop * 32));
2297
2298 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
2299 priv->qos_data.qos_active = 1;
2300
2301 if (priv->iw_mode == NL80211_IFTYPE_AP)
2302 iwl_activate_qos(priv, 1);
2303 else if (priv->assoc_id && iwl_is_associated(priv))
2304 iwl_activate_qos(priv, 0);
2305
2306 spin_unlock_irqrestore(&priv->lock, flags);
2307
2308 IWL_DEBUG_MAC80211(priv, "leave\n");
2309 return 0;
2310}
2311EXPORT_SYMBOL(iwl_mac_conf_tx);
5bbe233b
AK		 2312
2313static void iwl_ht_conf(struct iwl_priv *priv,
02bb1bea 2314 struct ieee80211_bss_conf *bss_conf)
5bbe233b 2315{
fad95bf5 2316 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
5bbe233b
AK		 2317 struct ieee80211_sta *sta;
2318
2319 IWL_DEBUG_MAC80211(priv, "enter: \n");
2320
fad95bf5 2321 if (!ht_conf->is_ht)
5bbe233b
AK		 2322 return;
2323
fad95bf5 2324 ht_conf->ht_protection =
9ed6bcce 2325 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
fad95bf5 2326 ht_conf->non_GF_STA_present =
9ed6bcce 2327 !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
5bbe233b 2328
02bb1bea
JB		 2329 ht_conf->single_chain_sufficient = false;
2330
2331 switch (priv->iw_mode) {
2332 case NL80211_IFTYPE_STATION:
2333 rcu_read_lock();
2334 sta = ieee80211_find_sta(priv->hw, priv->bssid);
2335 if (sta) {
2336 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
2337 int maxstreams;
2338
2339 maxstreams = (ht_cap->mcs.tx_params &
2340 IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
2341 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2342 maxstreams += 1;
2343
2344 if ((ht_cap->mcs.rx_mask[1] == 0) &&
2345 (ht_cap->mcs.rx_mask[2] == 0))
2346 ht_conf->single_chain_sufficient = true;
2347 if (maxstreams <= 1)
2348 ht_conf->single_chain_sufficient = true;
2349 } else {
2350 /*
2351 * If at all, this can only happen through a race
2352 * when the AP disconnects us while we're still
2353 * setting up the connection, in that case mac80211
2354 * will soon tell us about that.
2355 */
2356 ht_conf->single_chain_sufficient = true;
2357 }
2358 rcu_read_unlock();
2359 break;
2360 case NL80211_IFTYPE_ADHOC:
2361 ht_conf->single_chain_sufficient = true;
2362 break;
2363 default:
2364 break;
2365 }
5bbe233b
AK		 2366
2367 IWL_DEBUG_MAC80211(priv, "leave\n");
2368}
2369
2370#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
2371void iwl_bss_info_changed(struct ieee80211_hw *hw,
2d0ddec5
JB		 2372 struct ieee80211_vif *vif,
2373 struct ieee80211_bss_conf *bss_conf,
2374 u32 changes)
5bbe233b
AK		 2375{
2376 struct iwl_priv *priv = hw->priv;
3a650292 2377 int ret;
5bbe233b
AK		 2378
2379 IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
2380
2d0ddec5
JB		 2381 if (!iwl_is_alive(priv))
2382 return;
2383
2384 mutex_lock(&priv->mutex);
2385
2386 if (changes & BSS_CHANGED_BEACON &&
2387 priv->iw_mode == NL80211_IFTYPE_AP) {
2388 dev_kfree_skb(priv->ibss_beacon);
2389 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
2390 }
2391
d7129e19
JB		 2392 if (changes & BSS_CHANGED_BEACON_INT) {
2393 priv->beacon_int = bss_conf->beacon_int;
2394 /* TODO: in AP mode, do something to make this take effect */
2395 }
2396
2397 if (changes & BSS_CHANGED_BSSID) {
2398 IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
2399
2400 /*
2401 * If there is currently a HW scan going on in the
2402 * background then we need to cancel it else the RXON
2403 * below/in post_associate will fail.
2404 */
2d0ddec5 2405 if (iwl_scan_cancel_timeout(priv, 100)) {
d7129e19 2406 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
2d0ddec5
JB		 2407 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
2408 mutex_unlock(&priv->mutex);
2409 return;
2410 }
2d0ddec5 2411
d7129e19
JB		 2412 /* mac80211 only sets assoc when in STATION mode */
2413 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
2414 bss_conf->assoc) {
2415 memcpy(priv->staging_rxon.bssid_addr,
2416 bss_conf->bssid, ETH_ALEN);
2d0ddec5 2417
d7129e19
JB		 2418 /* currently needed in a few places */
2419 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2420 } else {
2421 priv->staging_rxon.filter_flags &=
2422 ~RXON_FILTER_ASSOC_MSK;
2d0ddec5 2423 }
d7129e19 2424
2d0ddec5
JB		 2425 }
2426
d7129e19
JB		 2427 /*
2428 * This needs to be after setting the BSSID in case
2429 * mac80211 decides to do both changes at once because
2430 * it will invoke post_associate.
2431 */
2d0ddec5
JB		 2432 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2433 changes & BSS_CHANGED_BEACON) {
2434 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2435
2436 if (beacon)
2437 iwl_mac_beacon_update(hw, beacon);
2438 }
2439
5bbe233b
AK		 2440 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
2441 IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
2442 bss_conf->use_short_preamble);
2443 if (bss_conf->use_short_preamble)
2444 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2445 else
2446 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2447 }
2448
2449 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
2450 IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
2451 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
2452 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
2453 else
2454 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
2455 }
2456
d7129e19
JB		 2457 if (changes & BSS_CHANGED_BASIC_RATES) {
2458 /* XXX use this information
2459 *
2460 * To do that, remove code from iwl_set_rate() and put something
2461 * like this here:
2462 *
2463 if (A-band)
2464 priv->staging_rxon.ofdm_basic_rates =
2465 bss_conf->basic_rates;
2466 else
2467 priv->staging_rxon.ofdm_basic_rates =
2468 bss_conf->basic_rates >> 4;
2469 priv->staging_rxon.cck_basic_rates =
2470 bss_conf->basic_rates & 0xF;
2471 */
2472 }
2473
5bbe233b
AK		 2474 if (changes & BSS_CHANGED_HT) {
2475 iwl_ht_conf(priv, bss_conf);
45823531
AK		 2476
2477 if (priv->cfg->ops->hcmd->set_rxon_chain)
2478 priv->cfg->ops->hcmd->set_rxon_chain(priv);
5bbe233b
AK		 2479 }
2480
2481 if (changes & BSS_CHANGED_ASSOC) {
2482 IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
5bbe233b
AK		 2483 if (bss_conf->assoc) {
2484 priv->assoc_id = bss_conf->aid;
2485 priv->beacon_int = bss_conf->beacon_int;
5bbe233b
AK		 2486 priv->timestamp = bss_conf->timestamp;
2487 priv->assoc_capability = bss_conf->assoc_capability;
2488
e932a609
JB		 2489 iwl_led_associate(priv);
2490
d7129e19
JB		 2491 /*
2492 * We have just associated, don't start scan too early
2493 * leave time for EAPOL exchange to complete.
2494 *
2495 * XXX: do this in mac80211
5bbe233b
AK		 2496 */
2497 priv->next_scan_jiffies = jiffies +
2498 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
d7129e19
JB		 2499 if (!iwl_is_rfkill(priv))
2500 priv->cfg->ops->lib->post_associate(priv);
e932a609 2501 } else {
5bbe233b 2502 priv->assoc_id = 0;
e932a609
JB		 2503 iwl_led_disassociate(priv);
2504 }
d7129e19
JB		 2505 }
2506
2507 if (changes && iwl_is_associated(priv) && priv->assoc_id) {
2508 IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
2509 changes);
2510 ret = iwl_send_rxon_assoc(priv);
2511 if (!ret) {
2512 /* Sync active_rxon with latest change. */
2513 memcpy((void *)&priv->active_rxon,
2514 &priv->staging_rxon,
2515 sizeof(struct iwl_rxon_cmd));
5bbe233b 2516 }
5bbe233b 2517 }
d7129e19
JB		 2518
2519 mutex_unlock(&priv->mutex);
2520
2d0ddec5 2521 IWL_DEBUG_MAC80211(priv, "leave\n");
5bbe233b
AK		 2522}
2523EXPORT_SYMBOL(iwl_bss_info_changed);
2524
9944b938
AK		 2525int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
2526{
2527 struct iwl_priv *priv = hw->priv;
2528 unsigned long flags;
2529 __le64 timestamp;
2530
2531 IWL_DEBUG_MAC80211(priv, "enter\n");
2532
2533 if (!iwl_is_ready_rf(priv)) {
2534 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2535 return -EIO;
2536 }
2537
2538 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2539 IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
2540 return -EIO;
2541 }
2542
2543 spin_lock_irqsave(&priv->lock, flags);
2544
2545 if (priv->ibss_beacon)
2546 dev_kfree_skb(priv->ibss_beacon);
2547
2548 priv->ibss_beacon = skb;
2549
2550 priv->assoc_id = 0;
2551 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
2552 priv->timestamp = le64_to_cpu(timestamp);
2553
2554 IWL_DEBUG_MAC80211(priv, "leave\n");
2555 spin_unlock_irqrestore(&priv->lock, flags);
2556
2557 iwl_reset_qos(priv);
2558
2559 priv->cfg->ops->lib->post_associate(priv);
2560
2561
2562 return 0;
2563}
2564EXPORT_SYMBOL(iwl_mac_beacon_update);
2565
727882d6
AK		 2566int iwl_set_mode(struct iwl_priv *priv, int mode)
2567{
2568 if (mode == NL80211_IFTYPE_ADHOC) {
2569 const struct iwl_channel_info *ch_info;
2570
2571 ch_info = iwl_get_channel_info(priv,
2572 priv->band,
2573 le16_to_cpu(priv->staging_rxon.channel));
2574
2575 if (!ch_info || !is_channel_ibss(ch_info)) {
2576 IWL_ERR(priv, "channel %d not IBSS channel\n",
2577 le16_to_cpu(priv->staging_rxon.channel));
2578 return -EINVAL;
2579 }
2580 }
2581
2582 iwl_connection_init_rx_config(priv, mode);
2583
2584 if (priv->cfg->ops->hcmd->set_rxon_chain)
2585 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2586
2587 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2588
c587de0b 2589 iwl_clear_stations_table(priv);
727882d6
AK		 2590
2591 /* dont commit rxon if rf-kill is on*/
2592 if (!iwl_is_ready_rf(priv))
2593 return -EAGAIN;
2594
727882d6
AK		 2595 iwlcore_commit_rxon(priv);
2596
2597 return 0;
2598}
2599EXPORT_SYMBOL(iwl_set_mode);
2600
cbb6ab94
AK		 2601int iwl_mac_add_interface(struct ieee80211_hw *hw,
2602 struct ieee80211_if_init_conf *conf)
2603{
2604 struct iwl_priv *priv = hw->priv;
2605 unsigned long flags;
2606
2607 IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
2608
2609 if (priv->vif) {
2610 IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
2611 return -EOPNOTSUPP;
2612 }
2613
2614 spin_lock_irqsave(&priv->lock, flags);
2615 priv->vif = conf->vif;
2616 priv->iw_mode = conf->type;
2617
2618 spin_unlock_irqrestore(&priv->lock, flags);
2619
2620 mutex_lock(&priv->mutex);
2621
2622 if (conf->mac_addr) {
2623 IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
2624 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
2625 }
2626
2627 if (iwl_set_mode(priv, conf->type) == -EAGAIN)
2628 /* we are not ready, will run again when ready */
2629 set_bit(STATUS_MODE_PENDING, &priv->status);
2630
2631 mutex_unlock(&priv->mutex);
2632
2633 IWL_DEBUG_MAC80211(priv, "leave\n");
2634 return 0;
2635}
2636EXPORT_SYMBOL(iwl_mac_add_interface);
2637
d8052319
AK		 2638void iwl_mac_remove_interface(struct ieee80211_hw *hw,
2639 struct ieee80211_if_init_conf *conf)
2640{
2641 struct iwl_priv *priv = hw->priv;
2642
2643 IWL_DEBUG_MAC80211(priv, "enter\n");
2644
2645 mutex_lock(&priv->mutex);
2646
2647 if (iwl_is_ready_rf(priv)) {
2648 iwl_scan_cancel_timeout(priv, 100);
2649 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2650 iwlcore_commit_rxon(priv);
2651 }
2652 if (priv->vif == conf->vif) {
2653 priv->vif = NULL;
2654 memset(priv->bssid, 0, ETH_ALEN);
2655 }
2656 mutex_unlock(&priv->mutex);
2657
2658 IWL_DEBUG_MAC80211(priv, "leave\n");
2659
2660}
2661EXPORT_SYMBOL(iwl_mac_remove_interface);
2662
4808368d
AK		 2663/**
2664 * iwl_mac_config - mac80211 config callback
2665 *
2666 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
2667 * be set inappropriately and the driver currently sets the hardware up to
2668 * use it whenever needed.
2669 */
2670int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
2671{
2672 struct iwl_priv *priv = hw->priv;
2673 const struct iwl_channel_info *ch_info;
2674 struct ieee80211_conf *conf = &hw->conf;
fad95bf5 2675 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
4808368d
AK		 2676 unsigned long flags = 0;
2677 int ret = 0;
2678 u16 ch;
2679 int scan_active = 0;
2680
2681 mutex_lock(&priv->mutex);
2682
4808368d
AK		 2683 IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
2684 conf->channel->hw_value, changed);
2685
2686 if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
2687 test_bit(STATUS_SCANNING, &priv->status))) {
2688 scan_active = 1;
2689 IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
2690 }
2691
2692
2693 /* during scanning mac80211 will delay channel setting until
2694 * scan finish with changed = 0
2695 */
2696 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
2697 if (scan_active)
2698 goto set_ch_out;
2699
2700 ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
2701 ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
2702 if (!is_channel_valid(ch_info)) {
2703 IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
2704 ret = -EINVAL;
2705 goto set_ch_out;
2706 }
2707
2708 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2709 !is_channel_ibss(ch_info)) {
2710 IWL_ERR(priv, "channel %d in band %d not "
2711 "IBSS channel\n",
2712 conf->channel->hw_value, conf->channel->band);
2713 ret = -EINVAL;
2714 goto set_ch_out;
2715 }
2716
4808368d
AK		 2717 spin_lock_irqsave(&priv->lock, flags);
2718
28bd723b
DH		 2719 /* Configure HT40 channels */
2720 ht_conf->is_ht = conf_is_ht(conf);
2721 if (ht_conf->is_ht) {
2722 if (conf_is_ht40_minus(conf)) {
2723 ht_conf->extension_chan_offset =
2724 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
c812ee24 2725 ht_conf->is_40mhz = true;
28bd723b
DH		 2726 } else if (conf_is_ht40_plus(conf)) {
2727 ht_conf->extension_chan_offset =
2728 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
c812ee24 2729 ht_conf->is_40mhz = true;
28bd723b
DH		 2730 } else {
2731 ht_conf->extension_chan_offset =
2732 IEEE80211_HT_PARAM_CHA_SEC_NONE;
c812ee24 2733 ht_conf->is_40mhz = false;
28bd723b
DH		 2734 }
2735 } else
c812ee24 2736 ht_conf->is_40mhz = false;
28bd723b
DH		 2737 /* Default to no protection. Protection mode will later be set
2738 * from BSS config in iwl_ht_conf */
2739 ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
4808368d
AK		 2740
2741 /* if we are switching from ht to 2.4 clear flags
2742 * from any ht related info since 2.4 does not
2743 * support ht */
2744 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
2745 priv->staging_rxon.flags = 0;
2746
2747 iwl_set_rxon_channel(priv, conf->channel);
2748
2749 iwl_set_flags_for_band(priv, conf->channel->band);
2750 spin_unlock_irqrestore(&priv->lock, flags);
2751 set_ch_out:
2752 /* The list of supported rates and rate mask can be different
2753 * for each band; since the band may have changed, reset
2754 * the rate mask to what mac80211 lists */
2755 iwl_set_rate(priv);
2756 }
2757
78f5fb7f
JB		 2758 if (changed & (IEEE80211_CONF_CHANGE_PS |
2759 IEEE80211_CONF_CHANGE_IDLE)) {
e312c24c 2760 ret = iwl_power_update_mode(priv, false);
4808368d 2761 if (ret)
e312c24c 2762 IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
4808368d
AK		 2763 }
2764
2765 if (changed & IEEE80211_CONF_CHANGE_POWER) {
2766 IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
2767 priv->tx_power_user_lmt, conf->power_level);
2768
2769 iwl_set_tx_power(priv, conf->power_level, false);
2770 }
2771
2772 /* call to ensure that 4965 rx_chain is set properly in monitor mode */
2773 if (priv->cfg->ops->hcmd->set_rxon_chain)
2774 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2775
0cf4c01e
MA		 2776 if (!iwl_is_ready(priv)) {
2777 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2778 goto out;
2779 }
2780
4808368d
AK		 2781 if (scan_active)
2782 goto out;
2783
2784 if (memcmp(&priv->active_rxon,
2785 &priv->staging_rxon, sizeof(priv->staging_rxon)))
2786 iwlcore_commit_rxon(priv);
2787 else
2788 IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
2789
2790
2791out:
2792 IWL_DEBUG_MAC80211(priv, "leave\n");
2793 mutex_unlock(&priv->mutex);
2794 return ret;
2795}
2796EXPORT_SYMBOL(iwl_mac_config);
2797
aa89f31e
AK		 2798int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
2799 struct ieee80211_tx_queue_stats *stats)
2800{
2801 struct iwl_priv *priv = hw->priv;
2802 int i, avail;
2803 struct iwl_tx_queue *txq;
2804 struct iwl_queue *q;
2805 unsigned long flags;
2806
2807 IWL_DEBUG_MAC80211(priv, "enter\n");
2808
2809 if (!iwl_is_ready_rf(priv)) {
2810 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2811 return -EIO;
2812 }
2813
2814 spin_lock_irqsave(&priv->lock, flags);
2815
2816 for (i = 0; i < AC_NUM; i++) {
2817 txq = &priv->txq[i];
2818 q = &txq->q;
2819 avail = iwl_queue_space(q);
2820
2821 stats[i].len = q->n_window - avail;
2822 stats[i].limit = q->n_window - q->high_mark;
2823 stats[i].count = q->n_window;
2824
2825 }
2826 spin_unlock_irqrestore(&priv->lock, flags);
2827
2828 IWL_DEBUG_MAC80211(priv, "leave\n");
2829
2830 return 0;
2831}
2832EXPORT_SYMBOL(iwl_mac_get_tx_stats);
2833
bd564261
AK		 2834void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
2835{
2836 struct iwl_priv *priv = hw->priv;
2837 unsigned long flags;
2838
2839 mutex_lock(&priv->mutex);
2840 IWL_DEBUG_MAC80211(priv, "enter\n");
2841
2842 spin_lock_irqsave(&priv->lock, flags);
fad95bf5 2843 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
bd564261
AK		 2844 spin_unlock_irqrestore(&priv->lock, flags);
2845
2846 iwl_reset_qos(priv);
2847
2848 spin_lock_irqsave(&priv->lock, flags);
2849 priv->assoc_id = 0;
2850 priv->assoc_capability = 0;
2851 priv->assoc_station_added = 0;
2852
2853 /* new association get rid of ibss beacon skb */
2854 if (priv->ibss_beacon)
2855 dev_kfree_skb(priv->ibss_beacon);
2856
2857 priv->ibss_beacon = NULL;
2858
57c4d7b4 2859 priv->beacon_int = priv->vif->bss_conf.beacon_int;
bd564261
AK		 2860 priv->timestamp = 0;
2861 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
2862 priv->beacon_int = 0;
2863
2864 spin_unlock_irqrestore(&priv->lock, flags);
2865
2866 if (!iwl_is_ready_rf(priv)) {
2867 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2868 mutex_unlock(&priv->mutex);
2869 return;
2870 }
2871
2872 /* we are restarting association process
2873 * clear RXON_FILTER_ASSOC_MSK bit
2874 */
2875 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2876 iwl_scan_cancel_timeout(priv, 100);
2877 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2878 iwlcore_commit_rxon(priv);
2879 }
2880
bd564261 2881 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
bd564261
AK		 2882 IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
2883 mutex_unlock(&priv->mutex);
2884 return;
2885 }
2886
2887 iwl_set_rate(priv);
2888
2889 mutex_unlock(&priv->mutex);
2890
2891 IWL_DEBUG_MAC80211(priv, "leave\n");
2892}
2893EXPORT_SYMBOL(iwl_mac_reset_tsf);
2894
88804e2b
WYG		 2895int iwl_alloc_txq_mem(struct iwl_priv *priv)
2896{
2897 if (!priv->txq)
2898 priv->txq = kzalloc(
2899 sizeof(struct iwl_tx_queue) * priv->cfg->num_of_queues,
2900 GFP_KERNEL);
2901 if (!priv->txq) {
2902 IWL_ERR(priv, "Not enough memory for txq \n");
2903 return -ENOMEM;
2904 }
2905 return 0;
2906}
2907EXPORT_SYMBOL(iwl_alloc_txq_mem);
2908
2909void iwl_free_txq_mem(struct iwl_priv *priv)
2910{
2911 kfree(priv->txq);
2912 priv->txq = NULL;
2913}
2914EXPORT_SYMBOL(iwl_free_txq_mem);
2915
20594eb0
WYG		 2916#ifdef CONFIG_IWLWIFI_DEBUGFS
2917
2918#define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
2919
2920void iwl_reset_traffic_log(struct iwl_priv *priv)
2921{
2922 priv->tx_traffic_idx = 0;
2923 priv->rx_traffic_idx = 0;
2924 if (priv->tx_traffic)
2925 memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2926 if (priv->rx_traffic)
2927 memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2928}
2929
2930int iwl_alloc_traffic_mem(struct iwl_priv *priv)
2931{
2932 u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
2933
2934 if (iwl_debug_level & IWL_DL_TX) {
2935 if (!priv->tx_traffic) {
2936 priv->tx_traffic =
2937 kzalloc(traffic_size, GFP_KERNEL);
2938 if (!priv->tx_traffic)
2939 return -ENOMEM;
2940 }
2941 }
2942 if (iwl_debug_level & IWL_DL_RX) {
2943 if (!priv->rx_traffic) {
2944 priv->rx_traffic =
2945 kzalloc(traffic_size, GFP_KERNEL);
2946 if (!priv->rx_traffic)
2947 return -ENOMEM;
2948 }
2949 }
2950 iwl_reset_traffic_log(priv);
2951 return 0;
2952}
2953EXPORT_SYMBOL(iwl_alloc_traffic_mem);
2954
2955void iwl_free_traffic_mem(struct iwl_priv *priv)
2956{
2957 kfree(priv->tx_traffic);
2958 priv->tx_traffic = NULL;
2959
2960 kfree(priv->rx_traffic);
2961 priv->rx_traffic = NULL;
2962}
2963EXPORT_SYMBOL(iwl_free_traffic_mem);
2964
2965void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
2966 u16 length, struct ieee80211_hdr *header)
2967{
2968 __le16 fc;
2969 u16 len;
2970
2971 if (likely(!(iwl_debug_level & IWL_DL_TX)))
2972 return;
2973
2974 if (!priv->tx_traffic)
2975 return;
2976
2977 fc = header->frame_control;
2978 if (ieee80211_is_data(fc)) {
2979 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
2980 ? IWL_TRAFFIC_ENTRY_SIZE : length;
2981 memcpy((priv->tx_traffic +
2982 (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
2983 header, len);
2984 priv->tx_traffic_idx =
2985 (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
2986 }
2987}
2988EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
2989
2990void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
2991 u16 length, struct ieee80211_hdr *header)
2992{
2993 __le16 fc;
2994 u16 len;
2995
2996 if (likely(!(iwl_debug_level & IWL_DL_RX)))
2997 return;
2998
2999 if (!priv->rx_traffic)
3000 return;
3001
3002 fc = header->frame_control;
3003 if (ieee80211_is_data(fc)) {
3004 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
3005 ? IWL_TRAFFIC_ENTRY_SIZE : length;
3006 memcpy((priv->rx_traffic +
3007 (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3008 header, len);
3009 priv->rx_traffic_idx =
3010 (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3011 }
3012}
3013EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
22fdf3c9
WYG		 3014
3015const char *get_mgmt_string(int cmd)
3016{
3017 switch (cmd) {
3018 IWL_CMD(MANAGEMENT_ASSOC_REQ);
3019 IWL_CMD(MANAGEMENT_ASSOC_RESP);
3020 IWL_CMD(MANAGEMENT_REASSOC_REQ);
3021 IWL_CMD(MANAGEMENT_REASSOC_RESP);
3022 IWL_CMD(MANAGEMENT_PROBE_REQ);
3023 IWL_CMD(MANAGEMENT_PROBE_RESP);
3024 IWL_CMD(MANAGEMENT_BEACON);
3025 IWL_CMD(MANAGEMENT_ATIM);
3026 IWL_CMD(MANAGEMENT_DISASSOC);
3027 IWL_CMD(MANAGEMENT_AUTH);
3028 IWL_CMD(MANAGEMENT_DEAUTH);
3029 IWL_CMD(MANAGEMENT_ACTION);
3030 default:
3031 return "UNKNOWN";
3032
3033 }
3034}
3035
3036const char *get_ctrl_string(int cmd)
3037{
3038 switch (cmd) {
3039 IWL_CMD(CONTROL_BACK_REQ);
3040 IWL_CMD(CONTROL_BACK);
3041 IWL_CMD(CONTROL_PSPOLL);
3042 IWL_CMD(CONTROL_RTS);
3043 IWL_CMD(CONTROL_CTS);
3044 IWL_CMD(CONTROL_ACK);
3045 IWL_CMD(CONTROL_CFEND);
3046 IWL_CMD(CONTROL_CFENDACK);
3047 default:
3048 return "UNKNOWN";
3049
3050 }
3051}
3052
3053void iwl_clear_tx_stats(struct iwl_priv *priv)
3054{
3055 memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
3056
3057}
3058
3059void iwl_clear_rx_stats(struct iwl_priv *priv)
3060{
3061 memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
3062}
3063
3064/*
3065 * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
3066 * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
3067 * Use debugFs to display the rx/rx_statistics
3068 * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
3069 * information will be recorded, but DATA pkt still will be recorded
3070 * for the reason of iwl_led.c need to control the led blinking based on
3071 * number of tx and rx data.
3072 *
3073 */
3074void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
3075{
3076 struct traffic_stats *stats;
3077
3078 if (is_tx)
3079 stats = &priv->tx_stats;
3080 else
3081 stats = &priv->rx_stats;
3082
3083 if (ieee80211_is_mgmt(fc)) {
3084 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3085 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
3086 stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
3087 break;
3088 case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
3089 stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
3090 break;
3091 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
3092 stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
3093 break;
3094 case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
3095 stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
3096 break;
3097 case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
3098 stats->mgmt[MANAGEMENT_PROBE_REQ]++;
3099 break;
3100 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
3101 stats->mgmt[MANAGEMENT_PROBE_RESP]++;
3102 break;
3103 case cpu_to_le16(IEEE80211_STYPE_BEACON):
3104 stats->mgmt[MANAGEMENT_BEACON]++;
3105 break;
3106 case cpu_to_le16(IEEE80211_STYPE_ATIM):
3107 stats->mgmt[MANAGEMENT_ATIM]++;
3108 break;
3109 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
3110 stats->mgmt[MANAGEMENT_DISASSOC]++;
3111 break;
3112 case cpu_to_le16(IEEE80211_STYPE_AUTH):
3113 stats->mgmt[MANAGEMENT_AUTH]++;
3114 break;
3115 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
3116 stats->mgmt[MANAGEMENT_DEAUTH]++;
3117 break;
3118 case cpu_to_le16(IEEE80211_STYPE_ACTION):
3119 stats->mgmt[MANAGEMENT_ACTION]++;
3120 break;
3121 }
3122 } else if (ieee80211_is_ctl(fc)) {
3123 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3124 case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
3125 stats->ctrl[CONTROL_BACK_REQ]++;
3126 break;
3127 case cpu_to_le16(IEEE80211_STYPE_BACK):
3128 stats->ctrl[CONTROL_BACK]++;
3129 break;
3130 case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
3131 stats->ctrl[CONTROL_PSPOLL]++;
3132 break;
3133 case cpu_to_le16(IEEE80211_STYPE_RTS):
3134 stats->ctrl[CONTROL_RTS]++;
3135 break;
3136 case cpu_to_le16(IEEE80211_STYPE_CTS):
3137 stats->ctrl[CONTROL_CTS]++;
3138 break;
3139 case cpu_to_le16(IEEE80211_STYPE_ACK):
3140 stats->ctrl[CONTROL_ACK]++;
3141 break;
3142 case cpu_to_le16(IEEE80211_STYPE_CFEND):
3143 stats->ctrl[CONTROL_CFEND]++;
3144 break;
3145 case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
3146 stats->ctrl[CONTROL_CFENDACK]++;
3147 break;
3148 }
3149 } else {
3150 /* data */
3151 stats->data_cnt++;
3152 stats->data_bytes += len;
3153 }
3154}
3155EXPORT_SYMBOL(iwl_update_stats);
20594eb0
WYG		 3156#endif
3157
6da3a13e
WYG		 3158#ifdef CONFIG_PM
3159
3160int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
3161{
3162 struct iwl_priv *priv = pci_get_drvdata(pdev);
3163
3164 /*
3165 * This function is called when system goes into suspend state
3166 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
3167 * first but since iwl_mac_stop() has no knowledge of who the caller is,
3168 * it will not call apm_ops.stop() to stop the DMA operation.
3169 * Calling apm_ops.stop here to make sure we stop the DMA.
3170 */
3171 priv->cfg->ops->lib->apm_ops.stop(priv);
3172
3173 pci_save_state(pdev);
3174 pci_disable_device(pdev);
3175 pci_set_power_state(pdev, PCI_D3hot);
3176
3177 return 0;
3178}
3179EXPORT_SYMBOL(iwl_pci_suspend);
3180
3181int iwl_pci_resume(struct pci_dev *pdev)
3182{
3183 struct iwl_priv *priv = pci_get_drvdata(pdev);
3184 int ret;
3185
3186 pci_set_power_state(pdev, PCI_D0);
3187 ret = pci_enable_device(pdev);
3188 if (ret)
3189 return ret;
3190 pci_restore_state(pdev);
3191 iwl_enable_interrupts(priv);
3192
3193 return 0;
3194}
3195EXPORT_SYMBOL(iwl_pci_resume);
3196
3197#endif /* CONFIG_PM */
Linux kernel - Deliverables
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