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iwl3945: fix resume for ADHOC network
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
1d0a082d 31#include <net/mac80211.h>
df48c323 32
712b6cf5 33struct iwl_priv; /* FIXME: remove */
0a6857e7 34#include "iwl-debug.h"
6bc913bd 35#include "iwl-eeprom.h"
3e0d4cb1 36#include "iwl-dev.h" /* FIXME: remove */
df48c323 37#include "iwl-core.h"
b661c819 38#include "iwl-io.h"
ad97edd2 39#include "iwl-rfkill.h"
5da4b55f 40#include "iwl-power.h"
df48c323 41
1d0a082d 42
df48c323
TW		 43MODULE_DESCRIPTION("iwl core");
44MODULE_VERSION(IWLWIFI_VERSION);
45MODULE_AUTHOR(DRV_COPYRIGHT);
712b6cf5 46MODULE_LICENSE("GPL");
df48c323 47
c7de35cd
RR		 48#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
49 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
50 IWL_RATE_SISO_##s##M_PLCP, \
51 IWL_RATE_MIMO2_##s##M_PLCP,\
52 IWL_RATE_MIMO3_##s##M_PLCP,\
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
59 IWL_RATE_##np##M_INDEX }
60
61/*
62 * Parameter order:
63 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
64 *
65 * If there isn't a valid next or previous rate then INV is used which
66 * maps to IWL_RATE_INVALID
67 *
68 */
1826dcc0 69const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 70 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
71 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
72 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
73 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
74 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
75 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
76 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
77 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
78 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
79 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
80 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
81 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
82 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
83 /* FIXME:RS: ^^ should be INV (legacy) */
84};
1826dcc0 85EXPORT_SYMBOL(iwl_rates);
c7de35cd 86
e7d326ac
TW		 87/**
88 * translate ucode response to mac80211 tx status control values
89 */
90void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 91 struct ieee80211_tx_info *info)
e7d326ac
TW		 92{
93 int rate_index;
e6a9854b 94 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 95
e6a9854b 96 info->antenna_sel_tx =
e7d326ac
TW		 97 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
98 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 99 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 100 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 101 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
e7d326ac 102 if (rate_n_flags & RATE_MCS_FAT_MSK)
e6a9854b 103 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 104 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 105 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 106 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 107 r->flags |= IEEE80211_TX_RC_SHORT_GI;
e7d326ac 108 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
e6a9854b 109 if (info->band == IEEE80211_BAND_5GHZ)
e7d326ac 110 rate_index -= IWL_FIRST_OFDM_RATE;
e6a9854b 111 r->idx = rate_index;
e7d326ac
TW		 112}
113EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
114
115int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
116{
117 int idx = 0;
118
119 /* HT rate format */
120 if (rate_n_flags & RATE_MCS_HT_MSK) {
121 idx = (rate_n_flags & 0xff);
122
60d32215
DH		 123 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
124 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
125 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 126 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
127
128 idx += IWL_FIRST_OFDM_RATE;
129 /* skip 9M not supported in ht*/
130 if (idx >= IWL_RATE_9M_INDEX)
131 idx += 1;
132 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
133 return idx;
134
135 /* legacy rate format, search for match in table */
136 } else {
137 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
138 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
139 return idx;
140 }
141
142 return -1;
143}
144EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
145
76eff18b
TW		 146u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
147{
148 int i;
149 u8 ind = ant;
150 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
151 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
152 if (priv->hw_params.valid_tx_ant & BIT(ind))
153 return ind;
154 }
155 return ant;
156}
57bd1bea
TW		 157
158const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
159EXPORT_SYMBOL(iwl_bcast_addr);
160
161
1d0a082d
AK		 162/* This function both allocates and initializes hw and priv. */
163struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
164 struct ieee80211_ops *hw_ops)
165{
166 struct iwl_priv *priv;
167
168 /* mac80211 allocates memory for this device instance, including
169 * space for this driver's private structure */
170 struct ieee80211_hw *hw =
171 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
172 if (hw == NULL) {
173 IWL_ERROR("Can not allocate network device\n");
174 goto out;
175 }
176
177 priv = hw->priv;
178 priv->hw = hw;
179
180out:
181 return hw;
182}
183EXPORT_SYMBOL(iwl_alloc_all);
184
b661c819
TW		 185void iwl_hw_detect(struct iwl_priv *priv)
186{
187 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
188 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
189 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
190}
191EXPORT_SYMBOL(iwl_hw_detect);
192
1053d35f
RR		 193/* Tell nic where to find the "keep warm" buffer */
194int iwl_kw_init(struct iwl_priv *priv)
195{
196 unsigned long flags;
197 int ret;
198
199 spin_lock_irqsave(&priv->lock, flags);
200 ret = iwl_grab_nic_access(priv);
201 if (ret)
202 goto out;
203
204 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
205 priv->kw.dma_addr >> 4);
206 iwl_release_nic_access(priv);
207out:
208 spin_unlock_irqrestore(&priv->lock, flags);
209 return ret;
210}
211
212int iwl_kw_alloc(struct iwl_priv *priv)
213{
214 struct pci_dev *dev = priv->pci_dev;
16466903 215 struct iwl_kw *kw = &priv->kw;
1053d35f 216
16466903 217 kw->size = IWL_KW_SIZE;
1053d35f
RR		 218 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
219 if (!kw->v_addr)
220 return -ENOMEM;
221
222 return 0;
223}
224
225/**
226 * iwl_kw_free - Free the "keep warm" buffer
227 */
228void iwl_kw_free(struct iwl_priv *priv)
229{
230 struct pci_dev *dev = priv->pci_dev;
16466903 231 struct iwl_kw *kw = &priv->kw;
1053d35f
RR		 232
233 if (kw->v_addr) {
234 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
235 memset(kw, 0, sizeof(*kw));
236 }
237}
238
239int iwl_hw_nic_init(struct iwl_priv *priv)
240{
241 unsigned long flags;
242 struct iwl_rx_queue *rxq = &priv->rxq;
243 int ret;
244
245 /* nic_init */
1053d35f 246 spin_lock_irqsave(&priv->lock, flags);
1b73af82 247 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 248 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
249 spin_unlock_irqrestore(&priv->lock, flags);
250
251 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
252
253 priv->cfg->ops->lib->apm_ops.config(priv);
254
255 /* Allocate the RX queue, or reset if it is already allocated */
256 if (!rxq->bd) {
257 ret = iwl_rx_queue_alloc(priv);
258 if (ret) {
259 IWL_ERROR("Unable to initialize Rx queue\n");
260 return -ENOMEM;
261 }
262 } else
263 iwl_rx_queue_reset(priv, rxq);
264
265 iwl_rx_replenish(priv);
266
267 iwl_rx_init(priv, rxq);
268
269 spin_lock_irqsave(&priv->lock, flags);
270
271 rxq->need_update = 1;
272 iwl_rx_queue_update_write_ptr(priv, rxq);
273
274 spin_unlock_irqrestore(&priv->lock, flags);
275
276 /* Allocate and init all Tx and Command queues */
277 ret = iwl_txq_ctx_reset(priv);
278 if (ret)
279 return ret;
280
281 set_bit(STATUS_INIT, &priv->status);
282
283 return 0;
284}
285EXPORT_SYMBOL(iwl_hw_nic_init);
286
bf85ea4f 287/**
37deb2a0 288 * iwl_clear_stations_table - Clear the driver's station table
bf85ea4f
AK		 289 *
290 * NOTE: This does not clear or otherwise alter the device's station table.
291 */
37deb2a0 292void iwl_clear_stations_table(struct iwl_priv *priv)
bf85ea4f
AK		 293{
294 unsigned long flags;
295
296 spin_lock_irqsave(&priv->sta_lock, flags);
297
24e5c401 298 if (iwl_is_alive(priv) &&
37deb2a0
EG		 299 !test_bit(STATUS_EXIT_PENDING, &priv->status) &&
300 iwl_send_cmd_pdu_async(priv, REPLY_REMOVE_ALL_STA, 0, NULL, NULL))
24e5c401
EG		 301 IWL_ERROR("Couldn't clear the station table\n");
302
37deb2a0 303 priv->num_stations = 0;
bf85ea4f
AK		 304 memset(priv->stations, 0, sizeof(priv->stations));
305
306 spin_unlock_irqrestore(&priv->sta_lock, flags);
307}
37deb2a0 308EXPORT_SYMBOL(iwl_clear_stations_table);
bf85ea4f 309
c7de35cd 310void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 311{
312 u16 cw_min = 15;
313 u16 cw_max = 1023;
314 u8 aifs = 2;
315 u8 is_legacy = 0;
316 unsigned long flags;
317 int i;
318
319 spin_lock_irqsave(&priv->lock, flags);
320 priv->qos_data.qos_active = 0;
321
05c914fe 322 if (priv->iw_mode == NL80211_IFTYPE_ADHOC) {
bf85ea4f
AK		 323 if (priv->qos_data.qos_enable)
324 priv->qos_data.qos_active = 1;
325 if (!(priv->active_rate & 0xfff0)) {
326 cw_min = 31;
327 is_legacy = 1;
328 }
05c914fe 329 } else if (priv->iw_mode == NL80211_IFTYPE_AP) {
bf85ea4f
AK		 330 if (priv->qos_data.qos_enable)
331 priv->qos_data.qos_active = 1;
332 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
333 cw_min = 31;
334 is_legacy = 1;
335 }
336
337 if (priv->qos_data.qos_active)
338 aifs = 3;
339
340 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
341 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
342 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
343 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
344 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
345
346 if (priv->qos_data.qos_active) {
347 i = 1;
348 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
349 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
350 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
351 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
352 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
353
354 i = 2;
355 priv->qos_data.def_qos_parm.ac[i].cw_min =
356 cpu_to_le16((cw_min + 1) / 2 - 1);
357 priv->qos_data.def_qos_parm.ac[i].cw_max =
358 cpu_to_le16(cw_max);
359 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
360 if (is_legacy)
361 priv->qos_data.def_qos_parm.ac[i].edca_txop =
362 cpu_to_le16(6016);
363 else
364 priv->qos_data.def_qos_parm.ac[i].edca_txop =
365 cpu_to_le16(3008);
366 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
367
368 i = 3;
369 priv->qos_data.def_qos_parm.ac[i].cw_min =
370 cpu_to_le16((cw_min + 1) / 4 - 1);
371 priv->qos_data.def_qos_parm.ac[i].cw_max =
372 cpu_to_le16((cw_max + 1) / 2 - 1);
373 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
374 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
375 if (is_legacy)
376 priv->qos_data.def_qos_parm.ac[i].edca_txop =
377 cpu_to_le16(3264);
378 else
379 priv->qos_data.def_qos_parm.ac[i].edca_txop =
380 cpu_to_le16(1504);
381 } else {
382 for (i = 1; i < 4; i++) {
383 priv->qos_data.def_qos_parm.ac[i].cw_min =
384 cpu_to_le16(cw_min);
385 priv->qos_data.def_qos_parm.ac[i].cw_max =
386 cpu_to_le16(cw_max);
387 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
388 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
389 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
390 }
391 }
392 IWL_DEBUG_QOS("set QoS to default \n");
393
394 spin_unlock_irqrestore(&priv->lock, flags);
395}
c7de35cd
RR		 396EXPORT_SYMBOL(iwl_reset_qos);
397
d9fe60de
JB		 398#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
399#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 400static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 401 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 402 enum ieee80211_band band)
403{
39130df3
RR		 404 u16 max_bit_rate = 0;
405 u8 rx_chains_num = priv->hw_params.rx_chains_num;
406 u8 tx_chains_num = priv->hw_params.tx_chains_num;
407
c7de35cd 408 ht_info->cap = 0;
d9fe60de 409 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 410
d9fe60de 411 ht_info->ht_supported = true;
c7de35cd 412
d9fe60de
JB		 413 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
414 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
415 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
00c5ae2f 416 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
39130df3
RR		 417
418 max_bit_rate = MAX_BIT_RATE_20_MHZ;
c7de35cd 419 if (priv->hw_params.fat_channel & BIT(band)) {
d9fe60de
JB		 420 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
421 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
422 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 423 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 424 }
c7de35cd
RR		 425
426 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 427 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 428
429 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
430 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
431
d9fe60de 432 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 433 if (rx_chains_num >= 2)
d9fe60de 434 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 435 if (rx_chains_num >= 3)
d9fe60de 436 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 437
438 /* Highest supported Rx data rate */
439 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 440 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
441 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 442
443 /* Tx MCS capabilities */
d9fe60de 444 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 445 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 446 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
447 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
448 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 449 }
c7de35cd 450}
c7de35cd
RR		 451
452static void iwlcore_init_hw_rates(struct iwl_priv *priv,
453 struct ieee80211_rate *rates)
454{
455 int i;
456
457 for (i = 0; i < IWL_RATE_COUNT; i++) {
1826dcc0 458 rates[i].bitrate = iwl_rates[i].ieee * 5;
c7de35cd
RR		 459 rates[i].hw_value = i; /* Rate scaling will work on indexes */
460 rates[i].hw_value_short = i;
461 rates[i].flags = 0;
462 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
463 /*
464 * If CCK != 1M then set short preamble rate flag.
465 */
466 rates[i].flags |=
1826dcc0 467 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
c7de35cd
RR		 468 0 : IEEE80211_RATE_SHORT_PREAMBLE;
469 }
470 }
471}
472
473/**
474 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
475 */
476static int iwlcore_init_geos(struct iwl_priv *priv)
477{
478 struct iwl_channel_info *ch;
479 struct ieee80211_supported_band *sband;
480 struct ieee80211_channel *channels;
481 struct ieee80211_channel *geo_ch;
482 struct ieee80211_rate *rates;
483 int i = 0;
484
485 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
486 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
487 IWL_DEBUG_INFO("Geography modes already initialized.\n");
488 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
489 return 0;
490 }
491
492 channels = kzalloc(sizeof(struct ieee80211_channel) *
493 priv->channel_count, GFP_KERNEL);
494 if (!channels)
495 return -ENOMEM;
496
497 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
498 GFP_KERNEL);
499 if (!rates) {
500 kfree(channels);
501 return -ENOMEM;
502 }
503
504 /* 5.2GHz channels start after the 2.4GHz channels */
505 sband = &priv->bands[IEEE80211_BAND_5GHZ];
506 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
507 /* just OFDM */
508 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
509 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
510
49779293 511 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 512 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 513 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 514
515 sband = &priv->bands[IEEE80211_BAND_2GHZ];
516 sband->channels = channels;
517 /* OFDM & CCK */
518 sband->bitrates = rates;
519 sband->n_bitrates = IWL_RATE_COUNT;
520
49779293 521 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 522 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 523 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 524
525 priv->ieee_channels = channels;
526 priv->ieee_rates = rates;
527
528 iwlcore_init_hw_rates(priv, rates);
529
530 for (i = 0; i < priv->channel_count; i++) {
531 ch = &priv->channel_info[i];
532
533 /* FIXME: might be removed if scan is OK */
534 if (!is_channel_valid(ch))
535 continue;
536
537 if (is_channel_a_band(ch))
538 sband = &priv->bands[IEEE80211_BAND_5GHZ];
539 else
540 sband = &priv->bands[IEEE80211_BAND_2GHZ];
541
542 geo_ch = &sband->channels[sband->n_channels++];
543
544 geo_ch->center_freq =
545 ieee80211_channel_to_frequency(ch->channel);
546 geo_ch->max_power = ch->max_power_avg;
547 geo_ch->max_antenna_gain = 0xff;
548 geo_ch->hw_value = ch->channel;
549
550 if (is_channel_valid(ch)) {
551 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
552 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
553
554 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
555 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
556
557 if (ch->flags & EEPROM_CHANNEL_RADAR)
558 geo_ch->flags |= IEEE80211_CHAN_RADAR;
559
963f5517 560 geo_ch->flags |= ch->fat_extension_channel;
4d38c2e8 561
630fe9b6
TW		 562 if (ch->max_power_avg > priv->tx_power_channel_lmt)
563 priv->tx_power_channel_lmt = ch->max_power_avg;
c7de35cd
RR		 564 } else {
565 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
566 }
567
568 /* Save flags for reg domain usage */
569 geo_ch->orig_flags = geo_ch->flags;
570
963f5517 571 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 572 ch->channel, geo_ch->center_freq,
573 is_channel_a_band(ch) ? "5.2" : "2.4",
574 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
575 "restricted" : "valid",
576 geo_ch->flags);
577 }
578
579 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
580 priv->cfg->sku & IWL_SKU_A) {
581 printk(KERN_INFO DRV_NAME
582 ": Incorrectly detected BG card as ABG. Please send "
583 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
584 priv->pci_dev->device, priv->pci_dev->subsystem_device);
585 priv->cfg->sku &= ~IWL_SKU_A;
586 }
587
588 printk(KERN_INFO DRV_NAME
589 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
590 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
591 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
592
c7de35cd
RR		 593
594 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
595
596 return 0;
597}
598
599/*
600 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
601 */
6ba87956 602static void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 603{
604 kfree(priv->ieee_channels);
605 kfree(priv->ieee_rates);
606 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
607}
c7de35cd 608
28a6b07a 609static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 610{
611 return !priv->current_ht_config.is_ht ||
d9fe60de
JB		 612 ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
613 (priv->current_ht_config.mcs.rx_mask[2] == 0));
c7de35cd 614}
963f5517 615
47c5196e
TW		 616static u8 iwl_is_channel_extension(struct iwl_priv *priv,
617 enum ieee80211_band band,
618 u16 channel, u8 extension_chan_offset)
619{
620 const struct iwl_channel_info *ch_info;
621
622 ch_info = iwl_get_channel_info(priv, band, channel);
623 if (!is_channel_valid(ch_info))
624 return 0;
625
d9fe60de 626 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
963f5517
EG		 627 return !(ch_info->fat_extension_channel &
628 IEEE80211_CHAN_NO_FAT_ABOVE);
d9fe60de 629 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
963f5517
EG		 630 return !(ch_info->fat_extension_channel &
631 IEEE80211_CHAN_NO_FAT_BELOW);
47c5196e
TW		 632
633 return 0;
634}
635
636u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
d9fe60de 637 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e
TW		 638{
639 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
640
641 if ((!iwl_ht_conf->is_ht) ||
642 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
d9fe60de 643 (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE))
47c5196e
TW		 644 return 0;
645
646 if (sta_ht_inf) {
647 if ((!sta_ht_inf->ht_supported) ||
d9fe60de 648 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)))
47c5196e
TW		 649 return 0;
650 }
651
652 return iwl_is_channel_extension(priv, priv->band,
ae5eb026
JB		 653 le16_to_cpu(priv->staging_rxon.channel),
654 iwl_ht_conf->extension_chan_offset);
47c5196e
TW		 655}
656EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
657
658void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
659{
c1adf9fb 660 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e
TW		 661 u32 val;
662
42eb7c64
EG		 663 if (!ht_info->is_ht) {
664 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
665 RXON_FLG_CHANNEL_MODE_PURE_40_MSK |
666 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
667 RXON_FLG_FAT_PROT_MSK |
668 RXON_FLG_HT_PROT_MSK);
47c5196e 669 return;
42eb7c64 670 }
47c5196e
TW		 671
672 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
673 if (iwl_is_fat_tx_allowed(priv, NULL))
674 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
675 else
676 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
677 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
678
47c5196e
TW		 679 /* Note: control channel is opposite of extension channel */
680 switch (ht_info->extension_chan_offset) {
d9fe60de 681 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
47c5196e
TW		 682 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
683 break;
d9fe60de 684 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
47c5196e
TW		 685 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
686 break;
d9fe60de 687 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
47c5196e
TW		 688 default:
689 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
690 break;
691 }
692
693 val = ht_info->ht_protection;
694
695 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
696
697 iwl_set_rxon_chain(priv);
698
699 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
700 "rxon flags 0x%X operation mode :0x%X "
ae5eb026 701 "extension channel offset 0x%x\n",
d9fe60de
JB		 702 ht_info->mcs.rx_mask[0],
703 ht_info->mcs.rx_mask[1],
704 ht_info->mcs.rx_mask[2],
47c5196e 705 le32_to_cpu(rxon->flags), ht_info->ht_protection,
ae5eb026 706 ht_info->extension_chan_offset);
47c5196e
TW		 707 return;
708}
709EXPORT_SYMBOL(iwl_set_rxon_ht);
710
9e5e6c32
TW		 711#define IWL_NUM_RX_CHAINS_MULTIPLE 3
712#define IWL_NUM_RX_CHAINS_SINGLE 2
713#define IWL_NUM_IDLE_CHAINS_DUAL 2
714#define IWL_NUM_IDLE_CHAINS_SINGLE 1
715
716/* Determine how many receiver/antenna chains to use.
c7de35cd
RR		 717 * More provides better reception via diversity. Fewer saves power.
718 * MIMO (dual stream) requires at least 2, but works better with 3.
719 * This does not determine *which* chains to use, just how many.
720 */
28a6b07a 721static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 722{
28a6b07a
TW		 723 bool is_single = is_single_rx_stream(priv);
724 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd
RR		 725
726 /* # of Rx chains to use when expecting MIMO. */
12837be1
RR		 727 if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
728 WLAN_HT_CAP_SM_PS_STATIC)))
9e5e6c32 729 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 730 else
9e5e6c32 731 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 732}
c7de35cd 733
28a6b07a
TW		 734static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
735{
736 int idle_cnt;
737 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd 738 /* # Rx chains when idling and maybe trying to save power */
12837be1 739 switch (priv->current_ht_config.sm_ps) {
00c5ae2f
TW		 740 case WLAN_HT_CAP_SM_PS_STATIC:
741 case WLAN_HT_CAP_SM_PS_DYNAMIC:
9e5e6c32
TW		 742 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
743 IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 744 break;
00c5ae2f 745 case WLAN_HT_CAP_SM_PS_DISABLED:
9e5e6c32 746 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 747 break;
00c5ae2f 748 case WLAN_HT_CAP_SM_PS_INVALID:
c7de35cd 749 default:
a96a27f9 750 IWL_ERROR("invalid mimo ps mode %d\n",
12837be1 751 priv->current_ht_config.sm_ps);
28a6b07a
TW		 752 WARN_ON(1);
753 idle_cnt = -1;
c7de35cd
RR		 754 break;
755 }
28a6b07a 756 return idle_cnt;
c7de35cd
RR		 757}
758
04816448
GE		 759/* up to 4 chains */
760static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
761{
762 u8 res;
763 res = (chain_bitmap & BIT(0)) >> 0;
764 res += (chain_bitmap & BIT(1)) >> 1;
765 res += (chain_bitmap & BIT(2)) >> 2;
766 res += (chain_bitmap & BIT(4)) >> 4;
767 return res;
768}
769
c7de35cd
RR		 770/**
771 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
772 *
773 * Selects how many and which Rx receivers/antennas/chains to use.
774 * This should not be used for scan command ... it puts data in wrong place.
775 */
776void iwl_set_rxon_chain(struct iwl_priv *priv)
777{
28a6b07a
TW		 778 bool is_single = is_single_rx_stream(priv);
779 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 780 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
781 u32 active_chains;
28a6b07a 782 u16 rx_chain;
c7de35cd
RR		 783
784 /* Tell uCode which antennas are actually connected.
785 * Before first association, we assume all antennas are connected.
786 * Just after first association, iwl_chain_noise_calibration()
787 * checks which antennas actually *are* connected. */
04816448
GE		 788 if (priv->chain_noise_data.active_chains)
789 active_chains = priv->chain_noise_data.active_chains;
790 else
791 active_chains = priv->hw_params.valid_rx_ant;
792
793 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 794
795 /* How many receivers should we use? */
28a6b07a
TW		 796 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
797 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
798
28a6b07a 799
04816448
GE		 800 /* correct rx chain count according hw settings
801 * and chain noise calibration
802 */
803 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
804 if (valid_rx_cnt < active_rx_cnt)
805 active_rx_cnt = valid_rx_cnt;
806
807 if (valid_rx_cnt < idle_rx_cnt)
808 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 809
810 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
811 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
812
813 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
814
9e5e6c32 815 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 816 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
817 else
818 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
819
a33c2f47 820 IWL_DEBUG_ASSOC("rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 821 priv->staging_rxon.rx_chain,
822 active_rx_cnt, idle_rx_cnt);
823
824 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
825 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 826}
827EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 828
829/**
17e72782 830 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 831 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
832 * @channel: Any channel valid for the requested phymode
833
834 * In addition to setting the staging RXON, priv->phymode is also set.
835 *
836 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
837 * in the staging RXON flag structure based on the phymode
838 */
17e72782 839int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 840{
17e72782
TW		 841 enum ieee80211_band band = ch->band;
842 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
843
8622e705 844 if (!iwl_get_channel_info(priv, band, channel)) {
bf85ea4f
AK		 845 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
846 channel, band);
847 return -EINVAL;
848 }
849
850 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
851 (priv->band == band))
852 return 0;
853
854 priv->staging_rxon.channel = cpu_to_le16(channel);
855 if (band == IEEE80211_BAND_5GHZ)
856 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
857 else
858 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
859
860 priv->band = band;
861
862 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
863
864 return 0;
865}
c7de35cd 866EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 867
6ba87956 868int iwl_setup_mac(struct iwl_priv *priv)
bf85ea4f 869{
6ba87956 870 int ret;
bf85ea4f 871 struct ieee80211_hw *hw = priv->hw;
e227ceac 872 hw->rate_control_algorithm = "iwl-agn-rs";
bf85ea4f 873
566bfe5a 874 /* Tell mac80211 our characteristics */
605a0bd6 875 hw->flags = IEEE80211_HW_SIGNAL_DBM |
8b30b1fe
S		 876 IEEE80211_HW_NOISE_DBM |
877 IEEE80211_HW_AMPDU_AGGREGATION;
f59ac048
LR		 878 hw->wiphy->interface_modes =
879 BIT(NL80211_IFTYPE_AP) |
880 BIT(NL80211_IFTYPE_STATION) |
881 BIT(NL80211_IFTYPE_ADHOC);
bf85ea4f
AK		 882 /* Default value; 4 EDCA QOS priorities */
883 hw->queues = 4;
49779293
RR		 884 /* queues to support 11n aggregation */
885 if (priv->cfg->sku & IWL_SKU_N)
9f17b318 886 hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues;
6ba87956
TW		 887
888 hw->conf.beacon_int = 100;
b5d7be5e 889 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
6ba87956
TW		 890
891 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
892 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
893 &priv->bands[IEEE80211_BAND_2GHZ];
894 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
895 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
896 &priv->bands[IEEE80211_BAND_5GHZ];
897
898 ret = ieee80211_register_hw(priv->hw);
899 if (ret) {
900 IWL_ERROR("Failed to register hw (error %d)\n", ret);
901 return ret;
902 }
903 priv->mac80211_registered = 1;
904
905 return 0;
bf85ea4f 906}
6ba87956 907EXPORT_SYMBOL(iwl_setup_mac);
bf85ea4f 908
da154e30
RR		 909int iwl_set_hw_params(struct iwl_priv *priv)
910{
911 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
912 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
913 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
914 if (priv->cfg->mod_params->amsdu_size_8K)
915 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
916 else
917 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
918 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
919
49779293
RR		 920 if (priv->cfg->mod_params->disable_11n)
921 priv->cfg->sku &= ~IWL_SKU_N;
922
da154e30
RR		 923 /* Device-specific setup */
924 return priv->cfg->ops->lib->set_hw_params(priv);
925}
926EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956
TW		 927
928int iwl_init_drv(struct iwl_priv *priv)
c7de35cd
RR		 929{
930 int ret;
c7de35cd
RR		 931
932 priv->retry_rate = 1;
933 priv->ibss_beacon = NULL;
934
935 spin_lock_init(&priv->lock);
936 spin_lock_init(&priv->power_data.lock);
937 spin_lock_init(&priv->sta_lock);
938 spin_lock_init(&priv->hcmd_lock);
c7de35cd 939
c7de35cd
RR		 940 INIT_LIST_HEAD(&priv->free_frames);
941
942 mutex_init(&priv->mutex);
943
944 /* Clear the driver's (not device's) station table */
37deb2a0 945 iwl_clear_stations_table(priv);
c7de35cd
RR		 946
947 priv->data_retry_limit = -1;
948 priv->ieee_channels = NULL;
949 priv->ieee_rates = NULL;
950 priv->band = IEEE80211_BAND_2GHZ;
951
05c914fe 952 priv->iw_mode = NL80211_IFTYPE_STATION;
c7de35cd 953
12837be1 954 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
c7de35cd
RR		 955
956 /* Choose which receivers/antennas to use */
957 iwl_set_rxon_chain(priv);
f53696de 958 iwl_init_scan_params(priv);
c7de35cd 959
6ba87956
TW		 960 if (priv->cfg->mod_params->enable_qos)
961 priv->qos_data.qos_enable = 1;
962
c7de35cd
RR		 963 iwl_reset_qos(priv);
964
965 priv->qos_data.qos_active = 0;
966 priv->qos_data.qos_cap.val = 0;
967
c7de35cd
RR		 968 priv->rates_mask = IWL_RATES_MASK;
969 /* If power management is turned on, default to AC mode */
970 priv->power_mode = IWL_POWER_AC;
630fe9b6 971 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
c7de35cd
RR		 972
973 ret = iwl_init_channel_map(priv);
974 if (ret) {
975 IWL_ERROR("initializing regulatory failed: %d\n", ret);
976 goto err;
977 }
978
979 ret = iwlcore_init_geos(priv);
980 if (ret) {
981 IWL_ERROR("initializing geos failed: %d\n", ret);
982 goto err_free_channel_map;
983 }
984
c7de35cd
RR		 985 return 0;
986
c7de35cd
RR		 987err_free_channel_map:
988 iwl_free_channel_map(priv);
989err:
990 return ret;
991}
6ba87956 992EXPORT_SYMBOL(iwl_init_drv);
c7de35cd 993
630fe9b6
TW		 994int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
995{
996 int ret = 0;
997 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
998 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
999 priv->tx_power_user_lmt);
1000 return -EINVAL;
1001 }
1002
1003 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
1004 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1005 priv->tx_power_user_lmt);
1006 return -EINVAL;
1007 }
1008
1009 if (priv->tx_power_user_lmt != tx_power)
1010 force = true;
1011
1012 priv->tx_power_user_lmt = tx_power;
1013
1014 if (force && priv->cfg->ops->lib->send_tx_power)
1015 ret = priv->cfg->ops->lib->send_tx_power(priv);
1016
1017 return ret;
1018}
1019EXPORT_SYMBOL(iwl_set_tx_power);
1020
6ba87956 1021void iwl_uninit_drv(struct iwl_priv *priv)
bf85ea4f 1022{
6e21f2c1 1023 iwl_calib_free_results(priv);
6ba87956
TW		 1024 iwlcore_free_geos(priv);
1025 iwl_free_channel_map(priv);
261415f7 1026 kfree(priv->scan);
bf85ea4f 1027}
6ba87956 1028EXPORT_SYMBOL(iwl_uninit_drv);
bf85ea4f 1029
49ea8596
EG		 1030int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
1031{
1032 u32 stat_flags = 0;
1033 struct iwl_host_cmd cmd = {
1034 .id = REPLY_STATISTICS_CMD,
1035 .meta.flags = flags,
1036 .len = sizeof(stat_flags),
1037 .data = (u8 *) &stat_flags,
1038 };
1039 return iwl_send_cmd(priv, &cmd);
1040}
1041EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 1042
b0692f2f
EG		 1043/**
1044 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1045 * using sample data 100 bytes apart. If these sample points are good,
1046 * it's a pretty good bet that everything between them is good, too.
1047 */
1048static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1049{
1050 u32 val;
1051 int ret = 0;
1052 u32 errcnt = 0;
1053 u32 i;
1054
1055 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1056
1057 ret = iwl_grab_nic_access(priv);
1058 if (ret)
1059 return ret;
1060
1061 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1062 /* read data comes through single port, auto-incr addr */
1063 /* NOTE: Use the debugless read so we don't flood kernel log
1064 * if IWL_DL_IO is set */
1065 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1066 i + RTC_INST_LOWER_BOUND);
1067 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1068 if (val != le32_to_cpu(*image)) {
1069 ret = -EIO;
1070 errcnt++;
1071 if (errcnt >= 3)
1072 break;
1073 }
1074 }
1075
1076 iwl_release_nic_access(priv);
1077
1078 return ret;
1079}
1080
1081/**
1082 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1083 * looking at all data.
1084 */
1085static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1086 u32 len)
1087{
1088 u32 val;
1089 u32 save_len = len;
1090 int ret = 0;
1091 u32 errcnt;
1092
1093 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1094
1095 ret = iwl_grab_nic_access(priv);
1096 if (ret)
1097 return ret;
1098
1099 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1100
1101 errcnt = 0;
1102 for (; len > 0; len -= sizeof(u32), image++) {
1103 /* read data comes through single port, auto-incr addr */
1104 /* NOTE: Use the debugless read so we don't flood kernel log
1105 * if IWL_DL_IO is set */
1106 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1107 if (val != le32_to_cpu(*image)) {
1108 IWL_ERROR("uCode INST section is invalid at "
1109 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1110 save_len - len, val, le32_to_cpu(*image));
1111 ret = -EIO;
1112 errcnt++;
1113 if (errcnt >= 20)
1114 break;
1115 }
1116 }
1117
1118 iwl_release_nic_access(priv);
1119
1120 if (!errcnt)
1121 IWL_DEBUG_INFO
1122 ("ucode image in INSTRUCTION memory is good\n");
1123
1124 return ret;
1125}
1126
1127/**
1128 * iwl_verify_ucode - determine which instruction image is in SRAM,
1129 * and verify its contents
1130 */
1131int iwl_verify_ucode(struct iwl_priv *priv)
1132{
1133 __le32 *image;
1134 u32 len;
1135 int ret;
1136
1137 /* Try bootstrap */
1138 image = (__le32 *)priv->ucode_boot.v_addr;
1139 len = priv->ucode_boot.len;
1140 ret = iwlcore_verify_inst_sparse(priv, image, len);
1141 if (!ret) {
1142 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1143 return 0;
1144 }
1145
1146 /* Try initialize */
1147 image = (__le32 *)priv->ucode_init.v_addr;
1148 len = priv->ucode_init.len;
1149 ret = iwlcore_verify_inst_sparse(priv, image, len);
1150 if (!ret) {
1151 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1152 return 0;
1153 }
1154
1155 /* Try runtime/protocol */
1156 image = (__le32 *)priv->ucode_code.v_addr;
1157 len = priv->ucode_code.len;
1158 ret = iwlcore_verify_inst_sparse(priv, image, len);
1159 if (!ret) {
1160 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1161 return 0;
1162 }
1163
1164 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1165
1166 /* Since nothing seems to match, show first several data entries in
1167 * instruction SRAM, so maybe visual inspection will give a clue.
1168 * Selection of bootstrap image (vs. other images) is arbitrary. */
1169 image = (__le32 *)priv->ucode_boot.v_addr;
1170 len = priv->ucode_boot.len;
1171 ret = iwl_verify_inst_full(priv, image, len);
1172
1173 return ret;
1174}
1175EXPORT_SYMBOL(iwl_verify_ucode);
1176
56e12615
JS		 1177
1178static const char *desc_lookup_text[] = {
1179 "OK",
1180 "FAIL",
1181 "BAD_PARAM",
1182 "BAD_CHECKSUM",
1183 "NMI_INTERRUPT_WDG",
1184 "SYSASSERT",
1185 "FATAL_ERROR",
1186 "BAD_COMMAND",
1187 "HW_ERROR_TUNE_LOCK",
1188 "HW_ERROR_TEMPERATURE",
1189 "ILLEGAL_CHAN_FREQ",
1190 "VCC_NOT_STABLE",
1191 "FH_ERROR",
1192 "NMI_INTERRUPT_HOST",
1193 "NMI_INTERRUPT_ACTION_PT",
1194 "NMI_INTERRUPT_UNKNOWN",
1195 "UCODE_VERSION_MISMATCH",
1196 "HW_ERROR_ABS_LOCK",
1197 "HW_ERROR_CAL_LOCK_FAIL",
1198 "NMI_INTERRUPT_INST_ACTION_PT",
1199 "NMI_INTERRUPT_DATA_ACTION_PT",
1200 "NMI_TRM_HW_ER",
1201 "NMI_INTERRUPT_TRM",
1202 "NMI_INTERRUPT_BREAK_POINT"
1203 "DEBUG_0",
1204 "DEBUG_1",
1205 "DEBUG_2",
1206 "DEBUG_3",
1207 "UNKNOWN"
1208};
1209
ede0cba4
EK		 1210static const char *desc_lookup(int i)
1211{
56e12615
JS		 1212 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1213
1214 if (i < 0 || i > max)
1215 i = max;
ede0cba4 1216
56e12615 1217 return desc_lookup_text[i];
ede0cba4
EK		 1218}
1219
1220#define ERROR_START_OFFSET (1 * sizeof(u32))
1221#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1222
1223void iwl_dump_nic_error_log(struct iwl_priv *priv)
1224{
1225 u32 data2, line;
1226 u32 desc, time, count, base, data1;
1227 u32 blink1, blink2, ilink1, ilink2;
e1dfc085 1228 int ret;
ede0cba4 1229
e1dfc085
GG		 1230 if (priv->ucode_type == UCODE_INIT)
1231 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1232 else
1233 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
ede0cba4
EK		 1234
1235 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1236 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1237 return;
1238 }
1239
e1dfc085
GG		 1240 ret = iwl_grab_nic_access(priv);
1241 if (ret) {
ede0cba4
EK		 1242 IWL_WARNING("Can not read from adapter at this time.\n");
1243 return;
1244 }
1245
1246 count = iwl_read_targ_mem(priv, base);
1247
1248 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1249 IWL_ERROR("Start IWL Error Log Dump:\n");
1250 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1251 }
1252
1253 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1254 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1255 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1256 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1257 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1258 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1259 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1260 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1261 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1262
56e12615 1263 IWL_ERROR("Desc Time "
ede0cba4 1264 "data1 data2 line\n");
56e12615 1265 IWL_ERROR("%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
ede0cba4
EK		 1266 desc_lookup(desc), desc, time, data1, data2, line);
1267 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1268 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1269 ilink1, ilink2);
1270
1271 iwl_release_nic_access(priv);
1272}
1273EXPORT_SYMBOL(iwl_dump_nic_error_log);
1274
189a2b59
EK		 1275#define EVENT_START_OFFSET (4 * sizeof(u32))
1276
1277/**
1278 * iwl_print_event_log - Dump error event log to syslog
1279 *
a33c2f47 1280 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
189a2b59 1281 */
a33c2f47 1282static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
189a2b59
EK		 1283 u32 num_events, u32 mode)
1284{
1285 u32 i;
1286 u32 base; /* SRAM byte address of event log header */
1287 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1288 u32 ptr; /* SRAM byte address of log data */
1289 u32 ev, time, data; /* event log data */
1290
1291 if (num_events == 0)
1292 return;
e1dfc085
GG		 1293 if (priv->ucode_type == UCODE_INIT)
1294 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1295 else
1296 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
189a2b59
EK		 1297
1298 if (mode == 0)
1299 event_size = 2 * sizeof(u32);
1300 else
1301 event_size = 3 * sizeof(u32);
1302
1303 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1304
1305 /* "time" is actually "data" for mode 0 (no timestamp).
1306 * place event id # at far right for easier visual parsing. */
1307 for (i = 0; i < num_events; i++) {
1308 ev = iwl_read_targ_mem(priv, ptr);
1309 ptr += sizeof(u32);
1310 time = iwl_read_targ_mem(priv, ptr);
1311 ptr += sizeof(u32);
77c5d08e
TW		 1312 if (mode == 0) {
1313 /* data, ev */
1314 IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1315 } else {
189a2b59
EK		 1316 data = iwl_read_targ_mem(priv, ptr);
1317 ptr += sizeof(u32);
77c5d08e
TW		 1318 IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1319 time, data, ev);
189a2b59
EK		 1320 }
1321 }
1322}
189a2b59
EK		 1323
1324void iwl_dump_nic_event_log(struct iwl_priv *priv)
1325{
e1dfc085 1326 int ret;
189a2b59
EK		 1327 u32 base; /* SRAM byte address of event log header */
1328 u32 capacity; /* event log capacity in # entries */
1329 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1330 u32 num_wraps; /* # times uCode wrapped to top of log */
1331 u32 next_entry; /* index of next entry to be written by uCode */
1332 u32 size; /* # entries that we'll print */
1333
e1dfc085
GG		 1334 if (priv->ucode_type == UCODE_INIT)
1335 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1336 else
1337 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1338
189a2b59
EK		 1339 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1340 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1341 return;
1342 }
1343
e1dfc085
GG		 1344 ret = iwl_grab_nic_access(priv);
1345 if (ret) {
189a2b59
EK		 1346 IWL_WARNING("Can not read from adapter at this time.\n");
1347 return;
1348 }
1349
1350 /* event log header */
1351 capacity = iwl_read_targ_mem(priv, base);
1352 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1353 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1354 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1355
1356 size = num_wraps ? capacity : next_entry;
1357
1358 /* bail out if nothing in log */
1359 if (size == 0) {
1360 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1361 iwl_release_nic_access(priv);
1362 return;
1363 }
1364
1365 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1366 size, num_wraps);
1367
1368 /* if uCode has wrapped back to top of log, start at the oldest entry,
1369 * i.e the next one that uCode would fill. */
1370 if (num_wraps)
1371 iwl_print_event_log(priv, next_entry,
1372 capacity - next_entry, mode);
1373 /* (then/else) start at top of log */
1374 iwl_print_event_log(priv, 0, next_entry, mode);
1375
1376 iwl_release_nic_access(priv);
1377}
1378EXPORT_SYMBOL(iwl_dump_nic_event_log);
1379
47f4a587
EG		 1380void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1381{
1382 struct iwl_ct_kill_config cmd;
1383 unsigned long flags;
1384 int ret = 0;
1385
1386 spin_lock_irqsave(&priv->lock, flags);
1387 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1388 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1389 spin_unlock_irqrestore(&priv->lock, flags);
1390
1391 cmd.critical_temperature_R =
1392 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 1393
47f4a587
EG		 1394 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1395 sizeof(cmd), &cmd);
1396 if (ret)
1397 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1398 else
1399 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1400 "critical temperature is %d\n",
1401 cmd.critical_temperature_R);
1402}
1403EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f
EG		 1404
1405/*
1406 * CARD_STATE_CMD
1407 *
1408 * Use: Sets the device's internal card state to enable, disable, or halt
1409 *
1410 * When in the 'enable' state the card operates as normal.
1411 * When in the 'disable' state, the card enters into a low power mode.
1412 * When in the 'halt' state, the card is shut down and must be fully
1413 * restarted to come back on.
1414 */
1415static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
1416{
1417 struct iwl_host_cmd cmd = {
1418 .id = REPLY_CARD_STATE_CMD,
1419 .len = sizeof(u32),
1420 .data = &flags,
1421 .meta.flags = meta_flag,
1422 };
1423
1424 return iwl_send_cmd(priv, &cmd);
1425}
1426
1427void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1428{
1429 unsigned long flags;
1430
1431 if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1432 return;
1433
1434 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1435
1436 iwl_scan_cancel(priv);
1437 /* FIXME: This is a workaround for AP */
05c914fe 1438 if (priv->iw_mode != NL80211_IFTYPE_AP) {
14a08a7f
EG		 1439 spin_lock_irqsave(&priv->lock, flags);
1440 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1441 CSR_UCODE_SW_BIT_RFKILL);
1442 spin_unlock_irqrestore(&priv->lock, flags);
1443 /* call the host command only if no hw rf-kill set */
1444 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1445 iwl_is_ready(priv))
1446 iwl_send_card_state(priv,
1447 CARD_STATE_CMD_DISABLE, 0);
1448 set_bit(STATUS_RF_KILL_SW, &priv->status);
1449 /* make sure mac80211 stop sending Tx frame */
1450 if (priv->mac80211_registered)
1451 ieee80211_stop_queues(priv->hw);
1452 }
1453}
1454EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1455
1456int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1457{
1458 unsigned long flags;
1459
1460 if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1461 return 0;
1462
1463 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1464
1465 spin_lock_irqsave(&priv->lock, flags);
1466 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1467
a9efa652
EG		 1468 /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1469 * notification where it will clear SW rfkill status.
1470 * Setting it here would break the handler. Only if the
1471 * interface is down we can set here since we don't
1472 * receive any further notification.
1473 */
1474 if (!priv->is_open)
1475 clear_bit(STATUS_RF_KILL_SW, &priv->status);
14a08a7f
EG		 1476 spin_unlock_irqrestore(&priv->lock, flags);
1477
1478 /* wake up ucode */
1479 msleep(10);
1480
1481 spin_lock_irqsave(&priv->lock, flags);
1482 iwl_read32(priv, CSR_UCODE_DRV_GP1);
1483 if (!iwl_grab_nic_access(priv))
1484 iwl_release_nic_access(priv);
1485 spin_unlock_irqrestore(&priv->lock, flags);
1486
1487 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
1488 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1489 "disabled by HW switch\n");
1490 return 0;
1491 }
1492
a9efa652
EG		 1493 /* If the driver is already loaded, it will receive
1494 * CARD_STATE_NOTIFICATION notifications and the handler will
1495 * call restart to reload the driver.
1496 */
14a08a7f
EG		 1497 return 1;
1498}
1499EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);
Linux kernel - Deliverables
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