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mac80211: add might_sleep to hw_config
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
1d0a082d 31#include <net/mac80211.h>
df48c323 32
712b6cf5 33struct iwl_priv; /* FIXME: remove */
0a6857e7 34#include "iwl-debug.h"
6bc913bd 35#include "iwl-eeprom.h"
3e0d4cb1 36#include "iwl-dev.h" /* FIXME: remove */
df48c323 37#include "iwl-core.h"
b661c819 38#include "iwl-io.h"
ad97edd2 39#include "iwl-rfkill.h"
5da4b55f 40#include "iwl-power.h"
df48c323 41
1d0a082d 42
df48c323
TW		 43MODULE_DESCRIPTION("iwl core");
44MODULE_VERSION(IWLWIFI_VERSION);
45MODULE_AUTHOR(DRV_COPYRIGHT);
712b6cf5 46MODULE_LICENSE("GPL");
df48c323 47
c7de35cd
RR		 48#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
49 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
50 IWL_RATE_SISO_##s##M_PLCP, \
51 IWL_RATE_MIMO2_##s##M_PLCP,\
52 IWL_RATE_MIMO3_##s##M_PLCP,\
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
59 IWL_RATE_##np##M_INDEX }
60
61/*
62 * Parameter order:
63 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
64 *
65 * If there isn't a valid next or previous rate then INV is used which
66 * maps to IWL_RATE_INVALID
67 *
68 */
1826dcc0 69const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 70 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
71 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
72 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
73 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
74 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
75 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
76 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
77 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
78 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
79 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
80 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
81 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
82 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
83 /* FIXME:RS: ^^ should be INV (legacy) */
84};
1826dcc0 85EXPORT_SYMBOL(iwl_rates);
c7de35cd 86
e7d326ac
TW		 87/**
88 * translate ucode response to mac80211 tx status control values
89 */
90void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
91 struct ieee80211_tx_info *control)
92{
93 int rate_index;
94
95 control->antenna_sel_tx =
96 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
97 if (rate_n_flags & RATE_MCS_HT_MSK)
98 control->flags |= IEEE80211_TX_CTL_OFDM_HT;
99 if (rate_n_flags & RATE_MCS_GF_MSK)
100 control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
101 if (rate_n_flags & RATE_MCS_FAT_MSK)
102 control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
103 if (rate_n_flags & RATE_MCS_DUP_MSK)
104 control->flags |= IEEE80211_TX_CTL_DUP_DATA;
105 if (rate_n_flags & RATE_MCS_SGI_MSK)
106 control->flags |= IEEE80211_TX_CTL_SHORT_GI;
107 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
108 if (control->band == IEEE80211_BAND_5GHZ)
109 rate_index -= IWL_FIRST_OFDM_RATE;
110 control->tx_rate_idx = rate_index;
111}
112EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
113
114int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
115{
116 int idx = 0;
117
118 /* HT rate format */
119 if (rate_n_flags & RATE_MCS_HT_MSK) {
120 idx = (rate_n_flags & 0xff);
121
122 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
123 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
124
125 idx += IWL_FIRST_OFDM_RATE;
126 /* skip 9M not supported in ht*/
127 if (idx >= IWL_RATE_9M_INDEX)
128 idx += 1;
129 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
130 return idx;
131
132 /* legacy rate format, search for match in table */
133 } else {
134 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
135 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
136 return idx;
137 }
138
139 return -1;
140}
141EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
142
143
57bd1bea
TW		 144
145const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
146EXPORT_SYMBOL(iwl_bcast_addr);
147
148
1d0a082d
AK		 149/* This function both allocates and initializes hw and priv. */
150struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
151 struct ieee80211_ops *hw_ops)
152{
153 struct iwl_priv *priv;
154
155 /* mac80211 allocates memory for this device instance, including
156 * space for this driver's private structure */
157 struct ieee80211_hw *hw =
158 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
159 if (hw == NULL) {
160 IWL_ERROR("Can not allocate network device\n");
161 goto out;
162 }
163
164 priv = hw->priv;
165 priv->hw = hw;
166
167out:
168 return hw;
169}
170EXPORT_SYMBOL(iwl_alloc_all);
171
b661c819
TW		 172void iwl_hw_detect(struct iwl_priv *priv)
173{
174 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
175 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
176 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
177}
178EXPORT_SYMBOL(iwl_hw_detect);
179
1053d35f
RR		 180/* Tell nic where to find the "keep warm" buffer */
181int iwl_kw_init(struct iwl_priv *priv)
182{
183 unsigned long flags;
184 int ret;
185
186 spin_lock_irqsave(&priv->lock, flags);
187 ret = iwl_grab_nic_access(priv);
188 if (ret)
189 goto out;
190
191 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
192 priv->kw.dma_addr >> 4);
193 iwl_release_nic_access(priv);
194out:
195 spin_unlock_irqrestore(&priv->lock, flags);
196 return ret;
197}
198
199int iwl_kw_alloc(struct iwl_priv *priv)
200{
201 struct pci_dev *dev = priv->pci_dev;
16466903 202 struct iwl_kw *kw = &priv->kw;
1053d35f 203
16466903 204 kw->size = IWL_KW_SIZE;
1053d35f
RR		 205 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
206 if (!kw->v_addr)
207 return -ENOMEM;
208
209 return 0;
210}
211
212/**
213 * iwl_kw_free - Free the "keep warm" buffer
214 */
215void iwl_kw_free(struct iwl_priv *priv)
216{
217 struct pci_dev *dev = priv->pci_dev;
16466903 218 struct iwl_kw *kw = &priv->kw;
1053d35f
RR		 219
220 if (kw->v_addr) {
221 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
222 memset(kw, 0, sizeof(*kw));
223 }
224}
225
226int iwl_hw_nic_init(struct iwl_priv *priv)
227{
228 unsigned long flags;
229 struct iwl_rx_queue *rxq = &priv->rxq;
230 int ret;
231
232 /* nic_init */
1053d35f 233 spin_lock_irqsave(&priv->lock, flags);
1b73af82 234 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 235 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
236 spin_unlock_irqrestore(&priv->lock, flags);
237
238 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
239
240 priv->cfg->ops->lib->apm_ops.config(priv);
241
242 /* Allocate the RX queue, or reset if it is already allocated */
243 if (!rxq->bd) {
244 ret = iwl_rx_queue_alloc(priv);
245 if (ret) {
246 IWL_ERROR("Unable to initialize Rx queue\n");
247 return -ENOMEM;
248 }
249 } else
250 iwl_rx_queue_reset(priv, rxq);
251
252 iwl_rx_replenish(priv);
253
254 iwl_rx_init(priv, rxq);
255
256 spin_lock_irqsave(&priv->lock, flags);
257
258 rxq->need_update = 1;
259 iwl_rx_queue_update_write_ptr(priv, rxq);
260
261 spin_unlock_irqrestore(&priv->lock, flags);
262
263 /* Allocate and init all Tx and Command queues */
264 ret = iwl_txq_ctx_reset(priv);
265 if (ret)
266 return ret;
267
268 set_bit(STATUS_INIT, &priv->status);
269
270 return 0;
271}
272EXPORT_SYMBOL(iwl_hw_nic_init);
273
bf85ea4f 274/**
37deb2a0 275 * iwl_clear_stations_table - Clear the driver's station table
bf85ea4f
AK		 276 *
277 * NOTE: This does not clear or otherwise alter the device's station table.
278 */
37deb2a0 279void iwl_clear_stations_table(struct iwl_priv *priv)
bf85ea4f
AK		 280{
281 unsigned long flags;
282
283 spin_lock_irqsave(&priv->sta_lock, flags);
284
24e5c401 285 if (iwl_is_alive(priv) &&
37deb2a0
EG		 286 !test_bit(STATUS_EXIT_PENDING, &priv->status) &&
287 iwl_send_cmd_pdu_async(priv, REPLY_REMOVE_ALL_STA, 0, NULL, NULL))
24e5c401
EG		 288 IWL_ERROR("Couldn't clear the station table\n");
289
37deb2a0 290 priv->num_stations = 0;
bf85ea4f
AK		 291 memset(priv->stations, 0, sizeof(priv->stations));
292
293 spin_unlock_irqrestore(&priv->sta_lock, flags);
294}
37deb2a0 295EXPORT_SYMBOL(iwl_clear_stations_table);
bf85ea4f 296
c7de35cd 297void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 298{
299 u16 cw_min = 15;
300 u16 cw_max = 1023;
301 u8 aifs = 2;
302 u8 is_legacy = 0;
303 unsigned long flags;
304 int i;
305
306 spin_lock_irqsave(&priv->lock, flags);
307 priv->qos_data.qos_active = 0;
308
05c914fe 309 if (priv->iw_mode == NL80211_IFTYPE_ADHOC) {
bf85ea4f
AK		 310 if (priv->qos_data.qos_enable)
311 priv->qos_data.qos_active = 1;
312 if (!(priv->active_rate & 0xfff0)) {
313 cw_min = 31;
314 is_legacy = 1;
315 }
05c914fe 316 } else if (priv->iw_mode == NL80211_IFTYPE_AP) {
bf85ea4f
AK		 317 if (priv->qos_data.qos_enable)
318 priv->qos_data.qos_active = 1;
319 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
320 cw_min = 31;
321 is_legacy = 1;
322 }
323
324 if (priv->qos_data.qos_active)
325 aifs = 3;
326
327 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
328 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
329 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
330 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
331 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
332
333 if (priv->qos_data.qos_active) {
334 i = 1;
335 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
336 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
337 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
338 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
339 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
340
341 i = 2;
342 priv->qos_data.def_qos_parm.ac[i].cw_min =
343 cpu_to_le16((cw_min + 1) / 2 - 1);
344 priv->qos_data.def_qos_parm.ac[i].cw_max =
345 cpu_to_le16(cw_max);
346 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
347 if (is_legacy)
348 priv->qos_data.def_qos_parm.ac[i].edca_txop =
349 cpu_to_le16(6016);
350 else
351 priv->qos_data.def_qos_parm.ac[i].edca_txop =
352 cpu_to_le16(3008);
353 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
354
355 i = 3;
356 priv->qos_data.def_qos_parm.ac[i].cw_min =
357 cpu_to_le16((cw_min + 1) / 4 - 1);
358 priv->qos_data.def_qos_parm.ac[i].cw_max =
359 cpu_to_le16((cw_max + 1) / 2 - 1);
360 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
361 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
362 if (is_legacy)
363 priv->qos_data.def_qos_parm.ac[i].edca_txop =
364 cpu_to_le16(3264);
365 else
366 priv->qos_data.def_qos_parm.ac[i].edca_txop =
367 cpu_to_le16(1504);
368 } else {
369 for (i = 1; i < 4; i++) {
370 priv->qos_data.def_qos_parm.ac[i].cw_min =
371 cpu_to_le16(cw_min);
372 priv->qos_data.def_qos_parm.ac[i].cw_max =
373 cpu_to_le16(cw_max);
374 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
375 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
376 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
377 }
378 }
379 IWL_DEBUG_QOS("set QoS to default \n");
380
381 spin_unlock_irqrestore(&priv->lock, flags);
382}
c7de35cd
RR		 383EXPORT_SYMBOL(iwl_reset_qos);
384
d9fe60de
JB		 385#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
386#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 387static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 388 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 389 enum ieee80211_band band)
390{
39130df3
RR		 391 u16 max_bit_rate = 0;
392 u8 rx_chains_num = priv->hw_params.rx_chains_num;
393 u8 tx_chains_num = priv->hw_params.tx_chains_num;
394
c7de35cd 395 ht_info->cap = 0;
d9fe60de 396 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 397
d9fe60de 398 ht_info->ht_supported = true;
c7de35cd 399
d9fe60de
JB		 400 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
401 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
402 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
00c5ae2f 403 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
39130df3
RR		 404
405 max_bit_rate = MAX_BIT_RATE_20_MHZ;
c7de35cd 406 if (priv->hw_params.fat_channel & BIT(band)) {
d9fe60de
JB		 407 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
408 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
409 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 410 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 411 }
c7de35cd
RR		 412
413 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 414 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 415
416 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
417 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
418
d9fe60de 419 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 420 if (rx_chains_num >= 2)
d9fe60de 421 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 422 if (rx_chains_num >= 3)
d9fe60de 423 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 424
425 /* Highest supported Rx data rate */
426 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 427 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
428 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 429
430 /* Tx MCS capabilities */
d9fe60de 431 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 432 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 433 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
434 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
435 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 436 }
c7de35cd 437}
c7de35cd
RR		 438
439static void iwlcore_init_hw_rates(struct iwl_priv *priv,
440 struct ieee80211_rate *rates)
441{
442 int i;
443
444 for (i = 0; i < IWL_RATE_COUNT; i++) {
1826dcc0 445 rates[i].bitrate = iwl_rates[i].ieee * 5;
c7de35cd
RR		 446 rates[i].hw_value = i; /* Rate scaling will work on indexes */
447 rates[i].hw_value_short = i;
448 rates[i].flags = 0;
449 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
450 /*
451 * If CCK != 1M then set short preamble rate flag.
452 */
453 rates[i].flags |=
1826dcc0 454 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
c7de35cd
RR		 455 0 : IEEE80211_RATE_SHORT_PREAMBLE;
456 }
457 }
458}
459
460/**
461 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
462 */
463static int iwlcore_init_geos(struct iwl_priv *priv)
464{
465 struct iwl_channel_info *ch;
466 struct ieee80211_supported_band *sband;
467 struct ieee80211_channel *channels;
468 struct ieee80211_channel *geo_ch;
469 struct ieee80211_rate *rates;
470 int i = 0;
471
472 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
473 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
474 IWL_DEBUG_INFO("Geography modes already initialized.\n");
475 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
476 return 0;
477 }
478
479 channels = kzalloc(sizeof(struct ieee80211_channel) *
480 priv->channel_count, GFP_KERNEL);
481 if (!channels)
482 return -ENOMEM;
483
484 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
485 GFP_KERNEL);
486 if (!rates) {
487 kfree(channels);
488 return -ENOMEM;
489 }
490
491 /* 5.2GHz channels start after the 2.4GHz channels */
492 sband = &priv->bands[IEEE80211_BAND_5GHZ];
493 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
494 /* just OFDM */
495 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
496 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
497
49779293 498 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 499 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 500 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 501
502 sband = &priv->bands[IEEE80211_BAND_2GHZ];
503 sband->channels = channels;
504 /* OFDM & CCK */
505 sband->bitrates = rates;
506 sband->n_bitrates = IWL_RATE_COUNT;
507
49779293 508 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 509 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 510 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 511
512 priv->ieee_channels = channels;
513 priv->ieee_rates = rates;
514
515 iwlcore_init_hw_rates(priv, rates);
516
517 for (i = 0; i < priv->channel_count; i++) {
518 ch = &priv->channel_info[i];
519
520 /* FIXME: might be removed if scan is OK */
521 if (!is_channel_valid(ch))
522 continue;
523
524 if (is_channel_a_band(ch))
525 sband = &priv->bands[IEEE80211_BAND_5GHZ];
526 else
527 sband = &priv->bands[IEEE80211_BAND_2GHZ];
528
529 geo_ch = &sband->channels[sband->n_channels++];
530
531 geo_ch->center_freq =
532 ieee80211_channel_to_frequency(ch->channel);
533 geo_ch->max_power = ch->max_power_avg;
534 geo_ch->max_antenna_gain = 0xff;
535 geo_ch->hw_value = ch->channel;
536
537 if (is_channel_valid(ch)) {
538 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
539 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
540
541 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
542 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
543
544 if (ch->flags & EEPROM_CHANNEL_RADAR)
545 geo_ch->flags |= IEEE80211_CHAN_RADAR;
546
963f5517 547 geo_ch->flags |= ch->fat_extension_channel;
4d38c2e8 548
630fe9b6
TW		 549 if (ch->max_power_avg > priv->tx_power_channel_lmt)
550 priv->tx_power_channel_lmt = ch->max_power_avg;
c7de35cd
RR		 551 } else {
552 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
553 }
554
555 /* Save flags for reg domain usage */
556 geo_ch->orig_flags = geo_ch->flags;
557
963f5517 558 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 559 ch->channel, geo_ch->center_freq,
560 is_channel_a_band(ch) ? "5.2" : "2.4",
561 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
562 "restricted" : "valid",
563 geo_ch->flags);
564 }
565
566 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
567 priv->cfg->sku & IWL_SKU_A) {
568 printk(KERN_INFO DRV_NAME
569 ": Incorrectly detected BG card as ABG. Please send "
570 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
571 priv->pci_dev->device, priv->pci_dev->subsystem_device);
572 priv->cfg->sku &= ~IWL_SKU_A;
573 }
574
575 printk(KERN_INFO DRV_NAME
576 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
577 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
578 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
579
c7de35cd
RR		 580
581 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
582
583 return 0;
584}
585
586/*
587 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
588 */
6ba87956 589static void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 590{
591 kfree(priv->ieee_channels);
592 kfree(priv->ieee_rates);
593 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
594}
c7de35cd 595
28a6b07a 596static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 597{
598 return !priv->current_ht_config.is_ht ||
d9fe60de
JB		 599 ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
600 (priv->current_ht_config.mcs.rx_mask[2] == 0));
c7de35cd 601}
963f5517 602
47c5196e
TW		 603static u8 iwl_is_channel_extension(struct iwl_priv *priv,
604 enum ieee80211_band band,
605 u16 channel, u8 extension_chan_offset)
606{
607 const struct iwl_channel_info *ch_info;
608
609 ch_info = iwl_get_channel_info(priv, band, channel);
610 if (!is_channel_valid(ch_info))
611 return 0;
612
d9fe60de 613 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
963f5517
EG		 614 return !(ch_info->fat_extension_channel &
615 IEEE80211_CHAN_NO_FAT_ABOVE);
d9fe60de 616 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
963f5517
EG		 617 return !(ch_info->fat_extension_channel &
618 IEEE80211_CHAN_NO_FAT_BELOW);
47c5196e
TW		 619
620 return 0;
621}
622
623u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
d9fe60de 624 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e
TW		 625{
626 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
627
628 if ((!iwl_ht_conf->is_ht) ||
629 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
d9fe60de 630 (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE))
47c5196e
TW		 631 return 0;
632
633 if (sta_ht_inf) {
634 if ((!sta_ht_inf->ht_supported) ||
d9fe60de 635 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)))
47c5196e
TW		 636 return 0;
637 }
638
639 return iwl_is_channel_extension(priv, priv->band,
ae5eb026
JB		 640 le16_to_cpu(priv->staging_rxon.channel),
641 iwl_ht_conf->extension_chan_offset);
47c5196e
TW		 642}
643EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
644
645void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
646{
c1adf9fb 647 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e
TW		 648 u32 val;
649
42eb7c64
EG		 650 if (!ht_info->is_ht) {
651 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
652 RXON_FLG_CHANNEL_MODE_PURE_40_MSK |
653 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
654 RXON_FLG_FAT_PROT_MSK |
655 RXON_FLG_HT_PROT_MSK);
47c5196e 656 return;
42eb7c64 657 }
47c5196e
TW		 658
659 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
660 if (iwl_is_fat_tx_allowed(priv, NULL))
661 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
662 else
663 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
664 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
665
47c5196e
TW		 666 /* Note: control channel is opposite of extension channel */
667 switch (ht_info->extension_chan_offset) {
d9fe60de 668 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
47c5196e
TW		 669 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
670 break;
d9fe60de 671 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
47c5196e
TW		 672 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
673 break;
d9fe60de 674 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
47c5196e
TW		 675 default:
676 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
677 break;
678 }
679
680 val = ht_info->ht_protection;
681
682 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
683
684 iwl_set_rxon_chain(priv);
685
686 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
687 "rxon flags 0x%X operation mode :0x%X "
ae5eb026 688 "extension channel offset 0x%x\n",
d9fe60de
JB		 689 ht_info->mcs.rx_mask[0],
690 ht_info->mcs.rx_mask[1],
691 ht_info->mcs.rx_mask[2],
47c5196e 692 le32_to_cpu(rxon->flags), ht_info->ht_protection,
ae5eb026 693 ht_info->extension_chan_offset);
47c5196e
TW		 694 return;
695}
696EXPORT_SYMBOL(iwl_set_rxon_ht);
697
9e5e6c32
TW		 698#define IWL_NUM_RX_CHAINS_MULTIPLE 3
699#define IWL_NUM_RX_CHAINS_SINGLE 2
700#define IWL_NUM_IDLE_CHAINS_DUAL 2
701#define IWL_NUM_IDLE_CHAINS_SINGLE 1
702
703/* Determine how many receiver/antenna chains to use.
c7de35cd
RR		 704 * More provides better reception via diversity. Fewer saves power.
705 * MIMO (dual stream) requires at least 2, but works better with 3.
706 * This does not determine *which* chains to use, just how many.
707 */
28a6b07a 708static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 709{
28a6b07a
TW		 710 bool is_single = is_single_rx_stream(priv);
711 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd
RR		 712
713 /* # of Rx chains to use when expecting MIMO. */
12837be1
RR		 714 if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
715 WLAN_HT_CAP_SM_PS_STATIC)))
9e5e6c32 716 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 717 else
9e5e6c32 718 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 719}
c7de35cd 720
28a6b07a
TW		 721static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
722{
723 int idle_cnt;
724 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd 725 /* # Rx chains when idling and maybe trying to save power */
12837be1 726 switch (priv->current_ht_config.sm_ps) {
00c5ae2f
TW		 727 case WLAN_HT_CAP_SM_PS_STATIC:
728 case WLAN_HT_CAP_SM_PS_DYNAMIC:
9e5e6c32
TW		 729 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
730 IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 731 break;
00c5ae2f 732 case WLAN_HT_CAP_SM_PS_DISABLED:
9e5e6c32 733 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 734 break;
00c5ae2f 735 case WLAN_HT_CAP_SM_PS_INVALID:
c7de35cd 736 default:
12837be1
RR		 737 IWL_ERROR("invalide mimo ps mode %d\n",
738 priv->current_ht_config.sm_ps);
28a6b07a
TW		 739 WARN_ON(1);
740 idle_cnt = -1;
c7de35cd
RR		 741 break;
742 }
28a6b07a 743 return idle_cnt;
c7de35cd
RR		 744}
745
04816448
GE		 746/* up to 4 chains */
747static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
748{
749 u8 res;
750 res = (chain_bitmap & BIT(0)) >> 0;
751 res += (chain_bitmap & BIT(1)) >> 1;
752 res += (chain_bitmap & BIT(2)) >> 2;
753 res += (chain_bitmap & BIT(4)) >> 4;
754 return res;
755}
756
c7de35cd
RR		 757/**
758 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
759 *
760 * Selects how many and which Rx receivers/antennas/chains to use.
761 * This should not be used for scan command ... it puts data in wrong place.
762 */
763void iwl_set_rxon_chain(struct iwl_priv *priv)
764{
28a6b07a
TW		 765 bool is_single = is_single_rx_stream(priv);
766 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 767 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
768 u32 active_chains;
28a6b07a 769 u16 rx_chain;
c7de35cd
RR		 770
771 /* Tell uCode which antennas are actually connected.
772 * Before first association, we assume all antennas are connected.
773 * Just after first association, iwl_chain_noise_calibration()
774 * checks which antennas actually *are* connected. */
04816448
GE		 775 if (priv->chain_noise_data.active_chains)
776 active_chains = priv->chain_noise_data.active_chains;
777 else
778 active_chains = priv->hw_params.valid_rx_ant;
779
780 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 781
782 /* How many receivers should we use? */
28a6b07a
TW		 783 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
784 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
785
28a6b07a 786
04816448
GE		 787 /* correct rx chain count according hw settings
788 * and chain noise calibration
789 */
790 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
791 if (valid_rx_cnt < active_rx_cnt)
792 active_rx_cnt = valid_rx_cnt;
793
794 if (valid_rx_cnt < idle_rx_cnt)
795 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 796
797 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
798 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
799
800 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
801
9e5e6c32 802 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 803 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
804 else
805 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
806
a33c2f47 807 IWL_DEBUG_ASSOC("rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 808 priv->staging_rxon.rx_chain,
809 active_rx_cnt, idle_rx_cnt);
810
811 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
812 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 813}
814EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 815
816/**
17e72782 817 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 818 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
819 * @channel: Any channel valid for the requested phymode
820
821 * In addition to setting the staging RXON, priv->phymode is also set.
822 *
823 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
824 * in the staging RXON flag structure based on the phymode
825 */
17e72782 826int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 827{
17e72782
TW		 828 enum ieee80211_band band = ch->band;
829 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
830
8622e705 831 if (!iwl_get_channel_info(priv, band, channel)) {
bf85ea4f
AK		 832 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
833 channel, band);
834 return -EINVAL;
835 }
836
837 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
838 (priv->band == band))
839 return 0;
840
841 priv->staging_rxon.channel = cpu_to_le16(channel);
842 if (band == IEEE80211_BAND_5GHZ)
843 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
844 else
845 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
846
847 priv->band = band;
848
849 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
850
851 return 0;
852}
c7de35cd 853EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 854
6ba87956 855int iwl_setup_mac(struct iwl_priv *priv)
bf85ea4f 856{
6ba87956 857 int ret;
bf85ea4f 858 struct ieee80211_hw *hw = priv->hw;
e227ceac 859 hw->rate_control_algorithm = "iwl-agn-rs";
bf85ea4f 860
566bfe5a 861 /* Tell mac80211 our characteristics */
605a0bd6 862 hw->flags = IEEE80211_HW_SIGNAL_DBM |
566bfe5a 863 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 864 hw->wiphy->interface_modes =
865 BIT(NL80211_IFTYPE_AP) |
866 BIT(NL80211_IFTYPE_STATION) |
867 BIT(NL80211_IFTYPE_ADHOC);
bf85ea4f
AK		 868 /* Default value; 4 EDCA QOS priorities */
869 hw->queues = 4;
49779293
RR		 870 /* queues to support 11n aggregation */
871 if (priv->cfg->sku & IWL_SKU_N)
9f17b318 872 hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues;
6ba87956
TW		 873
874 hw->conf.beacon_int = 100;
b5d7be5e 875 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
6ba87956
TW		 876
877 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
878 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
879 &priv->bands[IEEE80211_BAND_2GHZ];
880 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
881 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
882 &priv->bands[IEEE80211_BAND_5GHZ];
883
884 ret = ieee80211_register_hw(priv->hw);
885 if (ret) {
886 IWL_ERROR("Failed to register hw (error %d)\n", ret);
887 return ret;
888 }
889 priv->mac80211_registered = 1;
890
891 return 0;
bf85ea4f 892}
6ba87956 893EXPORT_SYMBOL(iwl_setup_mac);
bf85ea4f 894
da154e30
RR		 895int iwl_set_hw_params(struct iwl_priv *priv)
896{
897 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
898 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
899 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
900 if (priv->cfg->mod_params->amsdu_size_8K)
901 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
902 else
903 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
904 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
905
49779293
RR		 906 if (priv->cfg->mod_params->disable_11n)
907 priv->cfg->sku &= ~IWL_SKU_N;
908
da154e30
RR		 909 /* Device-specific setup */
910 return priv->cfg->ops->lib->set_hw_params(priv);
911}
912EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956
TW		 913
914int iwl_init_drv(struct iwl_priv *priv)
c7de35cd
RR		 915{
916 int ret;
c7de35cd
RR		 917
918 priv->retry_rate = 1;
919 priv->ibss_beacon = NULL;
920
921 spin_lock_init(&priv->lock);
922 spin_lock_init(&priv->power_data.lock);
923 spin_lock_init(&priv->sta_lock);
924 spin_lock_init(&priv->hcmd_lock);
c7de35cd 925
c7de35cd
RR		 926 INIT_LIST_HEAD(&priv->free_frames);
927
928 mutex_init(&priv->mutex);
929
930 /* Clear the driver's (not device's) station table */
37deb2a0 931 iwl_clear_stations_table(priv);
c7de35cd
RR		 932
933 priv->data_retry_limit = -1;
934 priv->ieee_channels = NULL;
935 priv->ieee_rates = NULL;
936 priv->band = IEEE80211_BAND_2GHZ;
937
05c914fe 938 priv->iw_mode = NL80211_IFTYPE_STATION;
c7de35cd
RR		 939
940 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
12837be1 941 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
c7de35cd
RR		 942
943 /* Choose which receivers/antennas to use */
944 iwl_set_rxon_chain(priv);
f53696de 945 iwl_init_scan_params(priv);
c7de35cd 946
6ba87956
TW		 947 if (priv->cfg->mod_params->enable_qos)
948 priv->qos_data.qos_enable = 1;
949
c7de35cd
RR		 950 iwl_reset_qos(priv);
951
952 priv->qos_data.qos_active = 0;
953 priv->qos_data.qos_cap.val = 0;
954
c7de35cd
RR		 955 priv->rates_mask = IWL_RATES_MASK;
956 /* If power management is turned on, default to AC mode */
957 priv->power_mode = IWL_POWER_AC;
630fe9b6 958 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
c7de35cd
RR		 959
960 ret = iwl_init_channel_map(priv);
961 if (ret) {
962 IWL_ERROR("initializing regulatory failed: %d\n", ret);
963 goto err;
964 }
965
966 ret = iwlcore_init_geos(priv);
967 if (ret) {
968 IWL_ERROR("initializing geos failed: %d\n", ret);
969 goto err_free_channel_map;
970 }
971
c7de35cd
RR		 972 return 0;
973
c7de35cd
RR		 974err_free_channel_map:
975 iwl_free_channel_map(priv);
976err:
977 return ret;
978}
6ba87956 979EXPORT_SYMBOL(iwl_init_drv);
c7de35cd 980
630fe9b6
TW		 981int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
982{
983 int ret = 0;
984 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
985 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
986 priv->tx_power_user_lmt);
987 return -EINVAL;
988 }
989
990 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
991 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
992 priv->tx_power_user_lmt);
993 return -EINVAL;
994 }
995
996 if (priv->tx_power_user_lmt != tx_power)
997 force = true;
998
999 priv->tx_power_user_lmt = tx_power;
1000
1001 if (force && priv->cfg->ops->lib->send_tx_power)
1002 ret = priv->cfg->ops->lib->send_tx_power(priv);
1003
1004 return ret;
1005}
1006EXPORT_SYMBOL(iwl_set_tx_power);
1007
6ba87956 1008void iwl_uninit_drv(struct iwl_priv *priv)
bf85ea4f 1009{
6e21f2c1 1010 iwl_calib_free_results(priv);
6ba87956
TW		 1011 iwlcore_free_geos(priv);
1012 iwl_free_channel_map(priv);
261415f7 1013 kfree(priv->scan);
bf85ea4f 1014}
6ba87956 1015EXPORT_SYMBOL(iwl_uninit_drv);
bf85ea4f 1016
49ea8596
EG		 1017int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
1018{
1019 u32 stat_flags = 0;
1020 struct iwl_host_cmd cmd = {
1021 .id = REPLY_STATISTICS_CMD,
1022 .meta.flags = flags,
1023 .len = sizeof(stat_flags),
1024 .data = (u8 *) &stat_flags,
1025 };
1026 return iwl_send_cmd(priv, &cmd);
1027}
1028EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 1029
b0692f2f
EG		 1030/**
1031 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1032 * using sample data 100 bytes apart. If these sample points are good,
1033 * it's a pretty good bet that everything between them is good, too.
1034 */
1035static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1036{
1037 u32 val;
1038 int ret = 0;
1039 u32 errcnt = 0;
1040 u32 i;
1041
1042 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1043
1044 ret = iwl_grab_nic_access(priv);
1045 if (ret)
1046 return ret;
1047
1048 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1049 /* read data comes through single port, auto-incr addr */
1050 /* NOTE: Use the debugless read so we don't flood kernel log
1051 * if IWL_DL_IO is set */
1052 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1053 i + RTC_INST_LOWER_BOUND);
1054 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1055 if (val != le32_to_cpu(*image)) {
1056 ret = -EIO;
1057 errcnt++;
1058 if (errcnt >= 3)
1059 break;
1060 }
1061 }
1062
1063 iwl_release_nic_access(priv);
1064
1065 return ret;
1066}
1067
1068/**
1069 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1070 * looking at all data.
1071 */
1072static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1073 u32 len)
1074{
1075 u32 val;
1076 u32 save_len = len;
1077 int ret = 0;
1078 u32 errcnt;
1079
1080 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1081
1082 ret = iwl_grab_nic_access(priv);
1083 if (ret)
1084 return ret;
1085
1086 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1087
1088 errcnt = 0;
1089 for (; len > 0; len -= sizeof(u32), image++) {
1090 /* read data comes through single port, auto-incr addr */
1091 /* NOTE: Use the debugless read so we don't flood kernel log
1092 * if IWL_DL_IO is set */
1093 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1094 if (val != le32_to_cpu(*image)) {
1095 IWL_ERROR("uCode INST section is invalid at "
1096 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1097 save_len - len, val, le32_to_cpu(*image));
1098 ret = -EIO;
1099 errcnt++;
1100 if (errcnt >= 20)
1101 break;
1102 }
1103 }
1104
1105 iwl_release_nic_access(priv);
1106
1107 if (!errcnt)
1108 IWL_DEBUG_INFO
1109 ("ucode image in INSTRUCTION memory is good\n");
1110
1111 return ret;
1112}
1113
1114/**
1115 * iwl_verify_ucode - determine which instruction image is in SRAM,
1116 * and verify its contents
1117 */
1118int iwl_verify_ucode(struct iwl_priv *priv)
1119{
1120 __le32 *image;
1121 u32 len;
1122 int ret;
1123
1124 /* Try bootstrap */
1125 image = (__le32 *)priv->ucode_boot.v_addr;
1126 len = priv->ucode_boot.len;
1127 ret = iwlcore_verify_inst_sparse(priv, image, len);
1128 if (!ret) {
1129 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1130 return 0;
1131 }
1132
1133 /* Try initialize */
1134 image = (__le32 *)priv->ucode_init.v_addr;
1135 len = priv->ucode_init.len;
1136 ret = iwlcore_verify_inst_sparse(priv, image, len);
1137 if (!ret) {
1138 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1139 return 0;
1140 }
1141
1142 /* Try runtime/protocol */
1143 image = (__le32 *)priv->ucode_code.v_addr;
1144 len = priv->ucode_code.len;
1145 ret = iwlcore_verify_inst_sparse(priv, image, len);
1146 if (!ret) {
1147 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1148 return 0;
1149 }
1150
1151 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1152
1153 /* Since nothing seems to match, show first several data entries in
1154 * instruction SRAM, so maybe visual inspection will give a clue.
1155 * Selection of bootstrap image (vs. other images) is arbitrary. */
1156 image = (__le32 *)priv->ucode_boot.v_addr;
1157 len = priv->ucode_boot.len;
1158 ret = iwl_verify_inst_full(priv, image, len);
1159
1160 return ret;
1161}
1162EXPORT_SYMBOL(iwl_verify_ucode);
1163
ede0cba4
EK		 1164static const char *desc_lookup(int i)
1165{
1166 switch (i) {
1167 case 1:
1168 return "FAIL";
1169 case 2:
1170 return "BAD_PARAM";
1171 case 3:
1172 return "BAD_CHECKSUM";
1173 case 4:
1174 return "NMI_INTERRUPT";
1175 case 5:
1176 return "SYSASSERT";
1177 case 6:
1178 return "FATAL_ERROR";
1179 }
1180
1181 return "UNKNOWN";
1182}
1183
1184#define ERROR_START_OFFSET (1 * sizeof(u32))
1185#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1186
1187void iwl_dump_nic_error_log(struct iwl_priv *priv)
1188{
1189 u32 data2, line;
1190 u32 desc, time, count, base, data1;
1191 u32 blink1, blink2, ilink1, ilink2;
e1dfc085 1192 int ret;
ede0cba4 1193
e1dfc085
GG		 1194 if (priv->ucode_type == UCODE_INIT)
1195 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1196 else
1197 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
ede0cba4
EK		 1198
1199 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1200 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1201 return;
1202 }
1203
e1dfc085
GG		 1204 ret = iwl_grab_nic_access(priv);
1205 if (ret) {
ede0cba4
EK		 1206 IWL_WARNING("Can not read from adapter at this time.\n");
1207 return;
1208 }
1209
1210 count = iwl_read_targ_mem(priv, base);
1211
1212 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1213 IWL_ERROR("Start IWL Error Log Dump:\n");
1214 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1215 }
1216
1217 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1218 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1219 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1220 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1221 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1222 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1223 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1224 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1225 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1226
1227 IWL_ERROR("Desc Time "
1228 "data1 data2 line\n");
1229 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1230 desc_lookup(desc), desc, time, data1, data2, line);
1231 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1232 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1233 ilink1, ilink2);
1234
1235 iwl_release_nic_access(priv);
1236}
1237EXPORT_SYMBOL(iwl_dump_nic_error_log);
1238
189a2b59
EK		 1239#define EVENT_START_OFFSET (4 * sizeof(u32))
1240
1241/**
1242 * iwl_print_event_log - Dump error event log to syslog
1243 *
a33c2f47 1244 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
189a2b59 1245 */
a33c2f47 1246static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
189a2b59
EK		 1247 u32 num_events, u32 mode)
1248{
1249 u32 i;
1250 u32 base; /* SRAM byte address of event log header */
1251 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1252 u32 ptr; /* SRAM byte address of log data */
1253 u32 ev, time, data; /* event log data */
1254
1255 if (num_events == 0)
1256 return;
e1dfc085
GG		 1257 if (priv->ucode_type == UCODE_INIT)
1258 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1259 else
1260 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
189a2b59
EK		 1261
1262 if (mode == 0)
1263 event_size = 2 * sizeof(u32);
1264 else
1265 event_size = 3 * sizeof(u32);
1266
1267 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1268
1269 /* "time" is actually "data" for mode 0 (no timestamp).
1270 * place event id # at far right for easier visual parsing. */
1271 for (i = 0; i < num_events; i++) {
1272 ev = iwl_read_targ_mem(priv, ptr);
1273 ptr += sizeof(u32);
1274 time = iwl_read_targ_mem(priv, ptr);
1275 ptr += sizeof(u32);
77c5d08e
TW		 1276 if (mode == 0) {
1277 /* data, ev */
1278 IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1279 } else {
189a2b59
EK		 1280 data = iwl_read_targ_mem(priv, ptr);
1281 ptr += sizeof(u32);
77c5d08e
TW		 1282 IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1283 time, data, ev);
189a2b59
EK		 1284 }
1285 }
1286}
189a2b59
EK		 1287
1288void iwl_dump_nic_event_log(struct iwl_priv *priv)
1289{
e1dfc085 1290 int ret;
189a2b59
EK		 1291 u32 base; /* SRAM byte address of event log header */
1292 u32 capacity; /* event log capacity in # entries */
1293 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1294 u32 num_wraps; /* # times uCode wrapped to top of log */
1295 u32 next_entry; /* index of next entry to be written by uCode */
1296 u32 size; /* # entries that we'll print */
1297
e1dfc085
GG		 1298 if (priv->ucode_type == UCODE_INIT)
1299 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1300 else
1301 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1302
189a2b59
EK		 1303 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1304 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1305 return;
1306 }
1307
e1dfc085
GG		 1308 ret = iwl_grab_nic_access(priv);
1309 if (ret) {
189a2b59
EK		 1310 IWL_WARNING("Can not read from adapter at this time.\n");
1311 return;
1312 }
1313
1314 /* event log header */
1315 capacity = iwl_read_targ_mem(priv, base);
1316 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1317 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1318 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1319
1320 size = num_wraps ? capacity : next_entry;
1321
1322 /* bail out if nothing in log */
1323 if (size == 0) {
1324 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1325 iwl_release_nic_access(priv);
1326 return;
1327 }
1328
1329 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1330 size, num_wraps);
1331
1332 /* if uCode has wrapped back to top of log, start at the oldest entry,
1333 * i.e the next one that uCode would fill. */
1334 if (num_wraps)
1335 iwl_print_event_log(priv, next_entry,
1336 capacity - next_entry, mode);
1337 /* (then/else) start at top of log */
1338 iwl_print_event_log(priv, 0, next_entry, mode);
1339
1340 iwl_release_nic_access(priv);
1341}
1342EXPORT_SYMBOL(iwl_dump_nic_event_log);
1343
47f4a587
EG		 1344void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1345{
1346 struct iwl_ct_kill_config cmd;
1347 unsigned long flags;
1348 int ret = 0;
1349
1350 spin_lock_irqsave(&priv->lock, flags);
1351 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1352 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1353 spin_unlock_irqrestore(&priv->lock, flags);
1354
1355 cmd.critical_temperature_R =
1356 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 1357
47f4a587
EG		 1358 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1359 sizeof(cmd), &cmd);
1360 if (ret)
1361 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1362 else
1363 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1364 "critical temperature is %d\n",
1365 cmd.critical_temperature_R);
1366}
1367EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f
EG		 1368
1369/*
1370 * CARD_STATE_CMD
1371 *
1372 * Use: Sets the device's internal card state to enable, disable, or halt
1373 *
1374 * When in the 'enable' state the card operates as normal.
1375 * When in the 'disable' state, the card enters into a low power mode.
1376 * When in the 'halt' state, the card is shut down and must be fully
1377 * restarted to come back on.
1378 */
1379static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
1380{
1381 struct iwl_host_cmd cmd = {
1382 .id = REPLY_CARD_STATE_CMD,
1383 .len = sizeof(u32),
1384 .data = &flags,
1385 .meta.flags = meta_flag,
1386 };
1387
1388 return iwl_send_cmd(priv, &cmd);
1389}
1390
1391void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1392{
1393 unsigned long flags;
1394
1395 if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1396 return;
1397
1398 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1399
1400 iwl_scan_cancel(priv);
1401 /* FIXME: This is a workaround for AP */
05c914fe 1402 if (priv->iw_mode != NL80211_IFTYPE_AP) {
14a08a7f
EG		 1403 spin_lock_irqsave(&priv->lock, flags);
1404 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1405 CSR_UCODE_SW_BIT_RFKILL);
1406 spin_unlock_irqrestore(&priv->lock, flags);
1407 /* call the host command only if no hw rf-kill set */
1408 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1409 iwl_is_ready(priv))
1410 iwl_send_card_state(priv,
1411 CARD_STATE_CMD_DISABLE, 0);
1412 set_bit(STATUS_RF_KILL_SW, &priv->status);
1413 /* make sure mac80211 stop sending Tx frame */
1414 if (priv->mac80211_registered)
1415 ieee80211_stop_queues(priv->hw);
1416 }
1417}
1418EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1419
1420int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1421{
1422 unsigned long flags;
1423
1424 if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1425 return 0;
1426
1427 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1428
1429 spin_lock_irqsave(&priv->lock, flags);
1430 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1431
a9efa652
EG		 1432 /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1433 * notification where it will clear SW rfkill status.
1434 * Setting it here would break the handler. Only if the
1435 * interface is down we can set here since we don't
1436 * receive any further notification.
1437 */
1438 if (!priv->is_open)
1439 clear_bit(STATUS_RF_KILL_SW, &priv->status);
14a08a7f
EG		 1440 spin_unlock_irqrestore(&priv->lock, flags);
1441
1442 /* wake up ucode */
1443 msleep(10);
1444
1445 spin_lock_irqsave(&priv->lock, flags);
1446 iwl_read32(priv, CSR_UCODE_DRV_GP1);
1447 if (!iwl_grab_nic_access(priv))
1448 iwl_release_nic_access(priv);
1449 spin_unlock_irqrestore(&priv->lock, flags);
1450
1451 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
1452 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1453 "disabled by HW switch\n");
1454 return 0;
1455 }
1456
a9efa652
EG		 1457 /* If the driver is already loaded, it will receive
1458 * CARD_STATE_NOTIFICATION notifications and the handler will
1459 * call restart to reload the driver.
1460 */
14a08a7f
EG		 1461 return 1;
1462}
1463EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);
Linux kernel - Deliverables
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