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df48c323 | 1 | /****************************************************************************** |
df48c323 TW |
2 | * |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
01f8162a | 5 | * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved. |
df48c323 TW |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
df48c323 TW |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | *****************************************************************************/ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
8ccde88a | 31 | #include <linux/etherdevice.h> |
1d0a082d | 32 | #include <net/mac80211.h> |
df48c323 | 33 | |
6bc913bd | 34 | #include "iwl-eeprom.h" |
3e0d4cb1 | 35 | #include "iwl-dev.h" /* FIXME: remove */ |
19335774 | 36 | #include "iwl-debug.h" |
df48c323 | 37 | #include "iwl-core.h" |
b661c819 | 38 | #include "iwl-io.h" |
ad97edd2 | 39 | #include "iwl-rfkill.h" |
5da4b55f | 40 | #include "iwl-power.h" |
83dde8c9 | 41 | #include "iwl-sta.h" |
ef850d7c | 42 | #include "iwl-helpers.h" |
df48c323 | 43 | |
1d0a082d | 44 | |
df48c323 TW |
45 | MODULE_DESCRIPTION("iwl core"); |
46 | MODULE_VERSION(IWLWIFI_VERSION); | |
a7b75207 | 47 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
712b6cf5 | 48 | MODULE_LICENSE("GPL"); |
df48c323 | 49 | |
c7de35cd RR |
50 | #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \ |
51 | [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \ | |
52 | IWL_RATE_SISO_##s##M_PLCP, \ | |
53 | IWL_RATE_MIMO2_##s##M_PLCP,\ | |
54 | IWL_RATE_MIMO3_##s##M_PLCP,\ | |
55 | IWL_RATE_##r##M_IEEE, \ | |
56 | IWL_RATE_##ip##M_INDEX, \ | |
57 | IWL_RATE_##in##M_INDEX, \ | |
58 | IWL_RATE_##rp##M_INDEX, \ | |
59 | IWL_RATE_##rn##M_INDEX, \ | |
60 | IWL_RATE_##pp##M_INDEX, \ | |
61 | IWL_RATE_##np##M_INDEX } | |
62 | ||
ef850d7c MA |
63 | static irqreturn_t iwl_isr(int irq, void *data); |
64 | ||
c7de35cd RR |
65 | /* |
66 | * Parameter order: | |
67 | * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate | |
68 | * | |
69 | * If there isn't a valid next or previous rate then INV is used which | |
70 | * maps to IWL_RATE_INVALID | |
71 | * | |
72 | */ | |
1826dcc0 | 73 | const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = { |
c7de35cd RR |
74 | IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */ |
75 | IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */ | |
76 | IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */ | |
77 | IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */ | |
78 | IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */ | |
79 | IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */ | |
80 | IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */ | |
81 | IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */ | |
82 | IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */ | |
83 | IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */ | |
84 | IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */ | |
85 | IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */ | |
86 | IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */ | |
87 | /* FIXME:RS: ^^ should be INV (legacy) */ | |
88 | }; | |
1826dcc0 | 89 | EXPORT_SYMBOL(iwl_rates); |
c7de35cd | 90 | |
e7d326ac TW |
91 | /** |
92 | * translate ucode response to mac80211 tx status control values | |
93 | */ | |
94 | void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags, | |
e6a9854b | 95 | struct ieee80211_tx_info *info) |
e7d326ac TW |
96 | { |
97 | int rate_index; | |
e6a9854b | 98 | struct ieee80211_tx_rate *r = &info->control.rates[0]; |
e7d326ac | 99 | |
e6a9854b | 100 | info->antenna_sel_tx = |
e7d326ac TW |
101 | ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS); |
102 | if (rate_n_flags & RATE_MCS_HT_MSK) | |
e6a9854b | 103 | r->flags |= IEEE80211_TX_RC_MCS; |
e7d326ac | 104 | if (rate_n_flags & RATE_MCS_GF_MSK) |
e6a9854b | 105 | r->flags |= IEEE80211_TX_RC_GREEN_FIELD; |
e7d326ac | 106 | if (rate_n_flags & RATE_MCS_FAT_MSK) |
e6a9854b | 107 | r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; |
e7d326ac | 108 | if (rate_n_flags & RATE_MCS_DUP_MSK) |
e6a9854b | 109 | r->flags |= IEEE80211_TX_RC_DUP_DATA; |
e7d326ac | 110 | if (rate_n_flags & RATE_MCS_SGI_MSK) |
e6a9854b | 111 | r->flags |= IEEE80211_TX_RC_SHORT_GI; |
e7d326ac | 112 | rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags); |
e6a9854b | 113 | if (info->band == IEEE80211_BAND_5GHZ) |
e7d326ac | 114 | rate_index -= IWL_FIRST_OFDM_RATE; |
e6a9854b | 115 | r->idx = rate_index; |
e7d326ac TW |
116 | } |
117 | EXPORT_SYMBOL(iwl_hwrate_to_tx_control); | |
118 | ||
119 | int iwl_hwrate_to_plcp_idx(u32 rate_n_flags) | |
120 | { | |
121 | int idx = 0; | |
122 | ||
123 | /* HT rate format */ | |
124 | if (rate_n_flags & RATE_MCS_HT_MSK) { | |
125 | idx = (rate_n_flags & 0xff); | |
126 | ||
60d32215 DH |
127 | if (idx >= IWL_RATE_MIMO3_6M_PLCP) |
128 | idx = idx - IWL_RATE_MIMO3_6M_PLCP; | |
129 | else if (idx >= IWL_RATE_MIMO2_6M_PLCP) | |
e7d326ac TW |
130 | idx = idx - IWL_RATE_MIMO2_6M_PLCP; |
131 | ||
132 | idx += IWL_FIRST_OFDM_RATE; | |
133 | /* skip 9M not supported in ht*/ | |
134 | if (idx >= IWL_RATE_9M_INDEX) | |
135 | idx += 1; | |
136 | if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE)) | |
137 | return idx; | |
138 | ||
139 | /* legacy rate format, search for match in table */ | |
140 | } else { | |
141 | for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++) | |
142 | if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF)) | |
143 | return idx; | |
144 | } | |
145 | ||
146 | return -1; | |
147 | } | |
148 | EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx); | |
149 | ||
76eff18b TW |
150 | u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant) |
151 | { | |
152 | int i; | |
153 | u8 ind = ant; | |
154 | for (i = 0; i < RATE_ANT_NUM - 1; i++) { | |
155 | ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0; | |
156 | if (priv->hw_params.valid_tx_ant & BIT(ind)) | |
157 | return ind; | |
158 | } | |
159 | return ant; | |
160 | } | |
57bd1bea TW |
161 | |
162 | const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; | |
163 | EXPORT_SYMBOL(iwl_bcast_addr); | |
164 | ||
165 | ||
1d0a082d AK |
166 | /* This function both allocates and initializes hw and priv. */ |
167 | struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg, | |
168 | struct ieee80211_ops *hw_ops) | |
169 | { | |
170 | struct iwl_priv *priv; | |
171 | ||
172 | /* mac80211 allocates memory for this device instance, including | |
173 | * space for this driver's private structure */ | |
174 | struct ieee80211_hw *hw = | |
175 | ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops); | |
176 | if (hw == NULL) { | |
a3139c59 SO |
177 | printk(KERN_ERR "%s: Can not allocate network device\n", |
178 | cfg->name); | |
1d0a082d AK |
179 | goto out; |
180 | } | |
181 | ||
182 | priv = hw->priv; | |
183 | priv->hw = hw; | |
184 | ||
185 | out: | |
186 | return hw; | |
187 | } | |
188 | EXPORT_SYMBOL(iwl_alloc_all); | |
189 | ||
b661c819 TW |
190 | void iwl_hw_detect(struct iwl_priv *priv) |
191 | { | |
192 | priv->hw_rev = _iwl_read32(priv, CSR_HW_REV); | |
193 | priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG); | |
194 | pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id); | |
195 | } | |
196 | EXPORT_SYMBOL(iwl_hw_detect); | |
197 | ||
1053d35f RR |
198 | int iwl_hw_nic_init(struct iwl_priv *priv) |
199 | { | |
200 | unsigned long flags; | |
201 | struct iwl_rx_queue *rxq = &priv->rxq; | |
202 | int ret; | |
203 | ||
204 | /* nic_init */ | |
1053d35f | 205 | spin_lock_irqsave(&priv->lock, flags); |
1b73af82 | 206 | priv->cfg->ops->lib->apm_ops.init(priv); |
1053d35f RR |
207 | iwl_write32(priv, CSR_INT_COALESCING, 512 / 32); |
208 | spin_unlock_irqrestore(&priv->lock, flags); | |
209 | ||
210 | ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN); | |
211 | ||
212 | priv->cfg->ops->lib->apm_ops.config(priv); | |
213 | ||
214 | /* Allocate the RX queue, or reset if it is already allocated */ | |
215 | if (!rxq->bd) { | |
216 | ret = iwl_rx_queue_alloc(priv); | |
217 | if (ret) { | |
15b1687c | 218 | IWL_ERR(priv, "Unable to initialize Rx queue\n"); |
1053d35f RR |
219 | return -ENOMEM; |
220 | } | |
221 | } else | |
222 | iwl_rx_queue_reset(priv, rxq); | |
223 | ||
224 | iwl_rx_replenish(priv); | |
225 | ||
226 | iwl_rx_init(priv, rxq); | |
227 | ||
228 | spin_lock_irqsave(&priv->lock, flags); | |
229 | ||
230 | rxq->need_update = 1; | |
231 | iwl_rx_queue_update_write_ptr(priv, rxq); | |
232 | ||
233 | spin_unlock_irqrestore(&priv->lock, flags); | |
234 | ||
235 | /* Allocate and init all Tx and Command queues */ | |
236 | ret = iwl_txq_ctx_reset(priv); | |
237 | if (ret) | |
238 | return ret; | |
239 | ||
240 | set_bit(STATUS_INIT, &priv->status); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | EXPORT_SYMBOL(iwl_hw_nic_init); | |
245 | ||
14d2aac5 AK |
246 | /* |
247 | * QoS support | |
248 | */ | |
249 | void iwl_activate_qos(struct iwl_priv *priv, u8 force) | |
250 | { | |
251 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
252 | return; | |
253 | ||
254 | priv->qos_data.def_qos_parm.qos_flags = 0; | |
255 | ||
256 | if (priv->qos_data.qos_cap.q_AP.queue_request && | |
257 | !priv->qos_data.qos_cap.q_AP.txop_request) | |
258 | priv->qos_data.def_qos_parm.qos_flags |= | |
259 | QOS_PARAM_FLG_TXOP_TYPE_MSK; | |
260 | if (priv->qos_data.qos_active) | |
261 | priv->qos_data.def_qos_parm.qos_flags |= | |
262 | QOS_PARAM_FLG_UPDATE_EDCA_MSK; | |
263 | ||
264 | if (priv->current_ht_config.is_ht) | |
265 | priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK; | |
266 | ||
267 | if (force || iwl_is_associated(priv)) { | |
268 | IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n", | |
269 | priv->qos_data.qos_active, | |
270 | priv->qos_data.def_qos_parm.qos_flags); | |
271 | ||
272 | iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM, | |
273 | sizeof(struct iwl_qosparam_cmd), | |
274 | &priv->qos_data.def_qos_parm, NULL); | |
275 | } | |
276 | } | |
277 | EXPORT_SYMBOL(iwl_activate_qos); | |
278 | ||
f2c95b04 WYG |
279 | /* |
280 | * AC CWmin CW max AIFSN TXOP Limit TXOP Limit | |
281 | * (802.11b) (802.11a/g) | |
282 | * AC_BK 15 1023 7 0 0 | |
283 | * AC_BE 15 1023 3 0 0 | |
284 | * AC_VI 7 15 2 6.016ms 3.008ms | |
285 | * AC_VO 3 7 2 3.264ms 1.504ms | |
286 | */ | |
c7de35cd | 287 | void iwl_reset_qos(struct iwl_priv *priv) |
bf85ea4f AK |
288 | { |
289 | u16 cw_min = 15; | |
290 | u16 cw_max = 1023; | |
291 | u8 aifs = 2; | |
30dab79e | 292 | bool is_legacy = false; |
bf85ea4f AK |
293 | unsigned long flags; |
294 | int i; | |
295 | ||
296 | spin_lock_irqsave(&priv->lock, flags); | |
30dab79e WT |
297 | /* QoS always active in AP and ADHOC mode |
298 | * In STA mode wait for association | |
299 | */ | |
300 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC || | |
301 | priv->iw_mode == NL80211_IFTYPE_AP) | |
302 | priv->qos_data.qos_active = 1; | |
303 | else | |
304 | priv->qos_data.qos_active = 0; | |
bf85ea4f | 305 | |
30dab79e WT |
306 | /* check for legacy mode */ |
307 | if ((priv->iw_mode == NL80211_IFTYPE_ADHOC && | |
308 | (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) || | |
309 | (priv->iw_mode == NL80211_IFTYPE_STATION && | |
310 | (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) { | |
bf85ea4f AK |
311 | cw_min = 31; |
312 | is_legacy = 1; | |
313 | } | |
314 | ||
315 | if (priv->qos_data.qos_active) | |
316 | aifs = 3; | |
317 | ||
f2c95b04 | 318 | /* AC_BE */ |
bf85ea4f AK |
319 | priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min); |
320 | priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max); | |
321 | priv->qos_data.def_qos_parm.ac[0].aifsn = aifs; | |
322 | priv->qos_data.def_qos_parm.ac[0].edca_txop = 0; | |
323 | priv->qos_data.def_qos_parm.ac[0].reserved1 = 0; | |
324 | ||
325 | if (priv->qos_data.qos_active) { | |
f2c95b04 | 326 | /* AC_BK */ |
bf85ea4f AK |
327 | i = 1; |
328 | priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min); | |
329 | priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max); | |
330 | priv->qos_data.def_qos_parm.ac[i].aifsn = 7; | |
331 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
332 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
333 | ||
f2c95b04 | 334 | /* AC_VI */ |
bf85ea4f AK |
335 | i = 2; |
336 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
337 | cpu_to_le16((cw_min + 1) / 2 - 1); | |
338 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
f2c95b04 | 339 | cpu_to_le16(cw_min); |
bf85ea4f AK |
340 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; |
341 | if (is_legacy) | |
342 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
343 | cpu_to_le16(6016); | |
344 | else | |
345 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
346 | cpu_to_le16(3008); | |
347 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
348 | ||
f2c95b04 | 349 | /* AC_VO */ |
bf85ea4f AK |
350 | i = 3; |
351 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
352 | cpu_to_le16((cw_min + 1) / 4 - 1); | |
353 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
f2c95b04 | 354 | cpu_to_le16((cw_min + 1) / 2 - 1); |
bf85ea4f AK |
355 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; |
356 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
357 | if (is_legacy) | |
358 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
359 | cpu_to_le16(3264); | |
360 | else | |
361 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
362 | cpu_to_le16(1504); | |
363 | } else { | |
364 | for (i = 1; i < 4; i++) { | |
365 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
366 | cpu_to_le16(cw_min); | |
367 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
368 | cpu_to_le16(cw_max); | |
369 | priv->qos_data.def_qos_parm.ac[i].aifsn = aifs; | |
370 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
371 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
372 | } | |
373 | } | |
e1623446 | 374 | IWL_DEBUG_QOS(priv, "set QoS to default \n"); |
bf85ea4f AK |
375 | |
376 | spin_unlock_irqrestore(&priv->lock, flags); | |
377 | } | |
c7de35cd RR |
378 | EXPORT_SYMBOL(iwl_reset_qos); |
379 | ||
d9fe60de JB |
380 | #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */ |
381 | #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */ | |
c7de35cd | 382 | static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv, |
d9fe60de | 383 | struct ieee80211_sta_ht_cap *ht_info, |
c7de35cd RR |
384 | enum ieee80211_band band) |
385 | { | |
39130df3 RR |
386 | u16 max_bit_rate = 0; |
387 | u8 rx_chains_num = priv->hw_params.rx_chains_num; | |
388 | u8 tx_chains_num = priv->hw_params.tx_chains_num; | |
389 | ||
c7de35cd | 390 | ht_info->cap = 0; |
d9fe60de | 391 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); |
c7de35cd | 392 | |
d9fe60de | 393 | ht_info->ht_supported = true; |
c7de35cd | 394 | |
d9fe60de JB |
395 | ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD; |
396 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
397 | ht_info->cap |= (IEEE80211_HT_CAP_SM_PS & | |
00c5ae2f | 398 | (WLAN_HT_CAP_SM_PS_DISABLED << 2)); |
39130df3 RR |
399 | |
400 | max_bit_rate = MAX_BIT_RATE_20_MHZ; | |
c7de35cd | 401 | if (priv->hw_params.fat_channel & BIT(band)) { |
d9fe60de JB |
402 | ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; |
403 | ht_info->cap |= IEEE80211_HT_CAP_SGI_40; | |
404 | ht_info->mcs.rx_mask[4] = 0x01; | |
39130df3 | 405 | max_bit_rate = MAX_BIT_RATE_40_MHZ; |
c7de35cd | 406 | } |
c7de35cd RR |
407 | |
408 | if (priv->cfg->mod_params->amsdu_size_8K) | |
d9fe60de | 409 | ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU; |
c7de35cd RR |
410 | |
411 | ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF; | |
412 | ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF; | |
413 | ||
d9fe60de | 414 | ht_info->mcs.rx_mask[0] = 0xFF; |
39130df3 | 415 | if (rx_chains_num >= 2) |
d9fe60de | 416 | ht_info->mcs.rx_mask[1] = 0xFF; |
39130df3 | 417 | if (rx_chains_num >= 3) |
d9fe60de | 418 | ht_info->mcs.rx_mask[2] = 0xFF; |
39130df3 RR |
419 | |
420 | /* Highest supported Rx data rate */ | |
421 | max_bit_rate *= rx_chains_num; | |
d9fe60de JB |
422 | WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK); |
423 | ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate); | |
39130df3 RR |
424 | |
425 | /* Tx MCS capabilities */ | |
d9fe60de | 426 | ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; |
39130df3 | 427 | if (tx_chains_num != rx_chains_num) { |
d9fe60de JB |
428 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
429 | ht_info->mcs.tx_params |= ((tx_chains_num - 1) << | |
430 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
39130df3 | 431 | } |
c7de35cd | 432 | } |
c7de35cd RR |
433 | |
434 | static void iwlcore_init_hw_rates(struct iwl_priv *priv, | |
435 | struct ieee80211_rate *rates) | |
436 | { | |
437 | int i; | |
438 | ||
439 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
1826dcc0 | 440 | rates[i].bitrate = iwl_rates[i].ieee * 5; |
c7de35cd RR |
441 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ |
442 | rates[i].hw_value_short = i; | |
443 | rates[i].flags = 0; | |
444 | if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { | |
445 | /* | |
446 | * If CCK != 1M then set short preamble rate flag. | |
447 | */ | |
448 | rates[i].flags |= | |
1826dcc0 | 449 | (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ? |
c7de35cd RR |
450 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
451 | } | |
452 | } | |
453 | } | |
454 | ||
8ccde88a | 455 | |
c7de35cd RR |
456 | /** |
457 | * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom | |
458 | */ | |
534166de | 459 | int iwlcore_init_geos(struct iwl_priv *priv) |
c7de35cd RR |
460 | { |
461 | struct iwl_channel_info *ch; | |
462 | struct ieee80211_supported_band *sband; | |
463 | struct ieee80211_channel *channels; | |
464 | struct ieee80211_channel *geo_ch; | |
465 | struct ieee80211_rate *rates; | |
466 | int i = 0; | |
467 | ||
468 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || | |
469 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
e1623446 | 470 | IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n"); |
c7de35cd RR |
471 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
472 | return 0; | |
473 | } | |
474 | ||
475 | channels = kzalloc(sizeof(struct ieee80211_channel) * | |
476 | priv->channel_count, GFP_KERNEL); | |
477 | if (!channels) | |
478 | return -ENOMEM; | |
479 | ||
480 | rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)), | |
481 | GFP_KERNEL); | |
482 | if (!rates) { | |
483 | kfree(channels); | |
484 | return -ENOMEM; | |
485 | } | |
486 | ||
487 | /* 5.2GHz channels start after the 2.4GHz channels */ | |
488 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
489 | sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)]; | |
490 | /* just OFDM */ | |
491 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
492 | sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE; | |
493 | ||
49779293 | 494 | if (priv->cfg->sku & IWL_SKU_N) |
d9fe60de | 495 | iwlcore_init_ht_hw_capab(priv, &sband->ht_cap, |
49779293 | 496 | IEEE80211_BAND_5GHZ); |
c7de35cd RR |
497 | |
498 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
499 | sband->channels = channels; | |
500 | /* OFDM & CCK */ | |
501 | sband->bitrates = rates; | |
502 | sband->n_bitrates = IWL_RATE_COUNT; | |
503 | ||
49779293 | 504 | if (priv->cfg->sku & IWL_SKU_N) |
d9fe60de | 505 | iwlcore_init_ht_hw_capab(priv, &sband->ht_cap, |
49779293 | 506 | IEEE80211_BAND_2GHZ); |
c7de35cd RR |
507 | |
508 | priv->ieee_channels = channels; | |
509 | priv->ieee_rates = rates; | |
510 | ||
c7de35cd RR |
511 | for (i = 0; i < priv->channel_count; i++) { |
512 | ch = &priv->channel_info[i]; | |
513 | ||
514 | /* FIXME: might be removed if scan is OK */ | |
515 | if (!is_channel_valid(ch)) | |
516 | continue; | |
517 | ||
518 | if (is_channel_a_band(ch)) | |
519 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
520 | else | |
521 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
522 | ||
523 | geo_ch = &sband->channels[sband->n_channels++]; | |
524 | ||
525 | geo_ch->center_freq = | |
526 | ieee80211_channel_to_frequency(ch->channel); | |
527 | geo_ch->max_power = ch->max_power_avg; | |
528 | geo_ch->max_antenna_gain = 0xff; | |
529 | geo_ch->hw_value = ch->channel; | |
530 | ||
531 | if (is_channel_valid(ch)) { | |
532 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) | |
533 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
534 | ||
535 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) | |
536 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
537 | ||
538 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
539 | geo_ch->flags |= IEEE80211_CHAN_RADAR; | |
540 | ||
963f5517 | 541 | geo_ch->flags |= ch->fat_extension_channel; |
4d38c2e8 | 542 | |
630fe9b6 TW |
543 | if (ch->max_power_avg > priv->tx_power_channel_lmt) |
544 | priv->tx_power_channel_lmt = ch->max_power_avg; | |
c7de35cd RR |
545 | } else { |
546 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; | |
547 | } | |
548 | ||
549 | /* Save flags for reg domain usage */ | |
550 | geo_ch->orig_flags = geo_ch->flags; | |
551 | ||
e1623446 | 552 | IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", |
c7de35cd RR |
553 | ch->channel, geo_ch->center_freq, |
554 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
555 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
556 | "restricted" : "valid", | |
557 | geo_ch->flags); | |
558 | } | |
559 | ||
560 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && | |
561 | priv->cfg->sku & IWL_SKU_A) { | |
978785a3 TW |
562 | IWL_INFO(priv, "Incorrectly detected BG card as ABG. " |
563 | "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n", | |
a3139c59 SO |
564 | priv->pci_dev->device, |
565 | priv->pci_dev->subsystem_device); | |
c7de35cd RR |
566 | priv->cfg->sku &= ~IWL_SKU_A; |
567 | } | |
568 | ||
978785a3 | 569 | IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n", |
a3139c59 SO |
570 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
571 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
c7de35cd RR |
572 | |
573 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
574 | ||
575 | return 0; | |
576 | } | |
534166de | 577 | EXPORT_SYMBOL(iwlcore_init_geos); |
c7de35cd RR |
578 | |
579 | /* | |
580 | * iwlcore_free_geos - undo allocations in iwlcore_init_geos | |
581 | */ | |
534166de | 582 | void iwlcore_free_geos(struct iwl_priv *priv) |
c7de35cd RR |
583 | { |
584 | kfree(priv->ieee_channels); | |
585 | kfree(priv->ieee_rates); | |
586 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
587 | } | |
534166de | 588 | EXPORT_SYMBOL(iwlcore_free_geos); |
c7de35cd | 589 | |
28a6b07a | 590 | static bool is_single_rx_stream(struct iwl_priv *priv) |
c7de35cd RR |
591 | { |
592 | return !priv->current_ht_config.is_ht || | |
d9fe60de JB |
593 | ((priv->current_ht_config.mcs.rx_mask[1] == 0) && |
594 | (priv->current_ht_config.mcs.rx_mask[2] == 0)); | |
c7de35cd | 595 | } |
963f5517 | 596 | |
47c5196e TW |
597 | static u8 iwl_is_channel_extension(struct iwl_priv *priv, |
598 | enum ieee80211_band band, | |
599 | u16 channel, u8 extension_chan_offset) | |
600 | { | |
601 | const struct iwl_channel_info *ch_info; | |
602 | ||
603 | ch_info = iwl_get_channel_info(priv, band, channel); | |
604 | if (!is_channel_valid(ch_info)) | |
605 | return 0; | |
606 | ||
d9fe60de | 607 | if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) |
963f5517 | 608 | return !(ch_info->fat_extension_channel & |
689da1b3 | 609 | IEEE80211_CHAN_NO_HT40PLUS); |
d9fe60de | 610 | else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) |
963f5517 | 611 | return !(ch_info->fat_extension_channel & |
689da1b3 | 612 | IEEE80211_CHAN_NO_HT40MINUS); |
47c5196e TW |
613 | |
614 | return 0; | |
615 | } | |
616 | ||
617 | u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv, | |
d9fe60de | 618 | struct ieee80211_sta_ht_cap *sta_ht_inf) |
47c5196e TW |
619 | { |
620 | struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config; | |
621 | ||
622 | if ((!iwl_ht_conf->is_ht) || | |
a2b0f02e | 623 | (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ)) |
47c5196e TW |
624 | return 0; |
625 | ||
a2b0f02e WYG |
626 | /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
627 | * the bit will not set if it is pure 40MHz case | |
628 | */ | |
47c5196e | 629 | if (sta_ht_inf) { |
a2b0f02e | 630 | if (!sta_ht_inf->ht_supported) |
47c5196e TW |
631 | return 0; |
632 | } | |
633 | ||
a2b0f02e WYG |
634 | if (iwl_ht_conf->ht_protection & IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) |
635 | return 1; | |
636 | else | |
637 | return iwl_is_channel_extension(priv, priv->band, | |
638 | le16_to_cpu(priv->staging_rxon.channel), | |
639 | iwl_ht_conf->extension_chan_offset); | |
47c5196e TW |
640 | } |
641 | EXPORT_SYMBOL(iwl_is_fat_tx_allowed); | |
642 | ||
8ccde88a SO |
643 | void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt) |
644 | { | |
645 | struct iwl_rxon_cmd *rxon = &priv->staging_rxon; | |
646 | ||
647 | if (hw_decrypt) | |
648 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
649 | else | |
650 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
651 | ||
652 | } | |
653 | EXPORT_SYMBOL(iwl_set_rxon_hwcrypto); | |
654 | ||
655 | /** | |
656 | * iwl_check_rxon_cmd - validate RXON structure is valid | |
657 | * | |
658 | * NOTE: This is really only useful during development and can eventually | |
659 | * be #ifdef'd out once the driver is stable and folks aren't actively | |
660 | * making changes | |
661 | */ | |
662 | int iwl_check_rxon_cmd(struct iwl_priv *priv) | |
663 | { | |
664 | int error = 0; | |
665 | int counter = 1; | |
666 | struct iwl_rxon_cmd *rxon = &priv->staging_rxon; | |
667 | ||
668 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
669 | error |= le32_to_cpu(rxon->flags & | |
670 | (RXON_FLG_TGJ_NARROW_BAND_MSK | | |
671 | RXON_FLG_RADAR_DETECT_MSK)); | |
672 | if (error) | |
673 | IWL_WARN(priv, "check 24G fields %d | %d\n", | |
674 | counter++, error); | |
675 | } else { | |
676 | error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ? | |
677 | 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK); | |
678 | if (error) | |
679 | IWL_WARN(priv, "check 52 fields %d | %d\n", | |
680 | counter++, error); | |
681 | error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK); | |
682 | if (error) | |
683 | IWL_WARN(priv, "check 52 CCK %d | %d\n", | |
684 | counter++, error); | |
685 | } | |
686 | error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1; | |
687 | if (error) | |
688 | IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error); | |
689 | ||
690 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
691 | error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) && | |
692 | ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0)); | |
693 | if (error) | |
694 | IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error); | |
695 | ||
696 | error |= (le16_to_cpu(rxon->assoc_id) > 2007); | |
697 | if (error) | |
698 | IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error); | |
699 | ||
700 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) | |
701 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)); | |
702 | if (error) | |
703 | IWL_WARN(priv, "check CCK and short slot %d | %d\n", | |
704 | counter++, error); | |
705 | ||
706 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) | |
707 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)); | |
708 | if (error) | |
709 | IWL_WARN(priv, "check CCK & auto detect %d | %d\n", | |
710 | counter++, error); | |
711 | ||
712 | error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | | |
713 | RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK); | |
714 | if (error) | |
715 | IWL_WARN(priv, "check TGG and auto detect %d | %d\n", | |
716 | counter++, error); | |
717 | ||
718 | if (error) | |
719 | IWL_WARN(priv, "Tuning to channel %d\n", | |
720 | le16_to_cpu(rxon->channel)); | |
721 | ||
722 | if (error) { | |
723 | IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n"); | |
724 | return -1; | |
725 | } | |
726 | return 0; | |
727 | } | |
728 | EXPORT_SYMBOL(iwl_check_rxon_cmd); | |
729 | ||
730 | /** | |
731 | * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed | |
732 | * @priv: staging_rxon is compared to active_rxon | |
733 | * | |
734 | * If the RXON structure is changing enough to require a new tune, | |
735 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
736 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
737 | */ | |
738 | int iwl_full_rxon_required(struct iwl_priv *priv) | |
739 | { | |
740 | ||
741 | /* These items are only settable from the full RXON command */ | |
742 | if (!(iwl_is_associated(priv)) || | |
743 | compare_ether_addr(priv->staging_rxon.bssid_addr, | |
744 | priv->active_rxon.bssid_addr) || | |
745 | compare_ether_addr(priv->staging_rxon.node_addr, | |
746 | priv->active_rxon.node_addr) || | |
747 | compare_ether_addr(priv->staging_rxon.wlap_bssid_addr, | |
748 | priv->active_rxon.wlap_bssid_addr) || | |
749 | (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) || | |
750 | (priv->staging_rxon.channel != priv->active_rxon.channel) || | |
751 | (priv->staging_rxon.air_propagation != | |
752 | priv->active_rxon.air_propagation) || | |
753 | (priv->staging_rxon.ofdm_ht_single_stream_basic_rates != | |
754 | priv->active_rxon.ofdm_ht_single_stream_basic_rates) || | |
755 | (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates != | |
756 | priv->active_rxon.ofdm_ht_dual_stream_basic_rates) || | |
c2105fa7 DH |
757 | (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates != |
758 | priv->active_rxon.ofdm_ht_triple_stream_basic_rates) || | |
8ccde88a SO |
759 | (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id)) |
760 | return 1; | |
761 | ||
762 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
763 | * be updated with the RXON_ASSOC command -- however only some | |
764 | * flag transitions are allowed using RXON_ASSOC */ | |
765 | ||
766 | /* Check if we are not switching bands */ | |
767 | if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) != | |
768 | (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)) | |
769 | return 1; | |
770 | ||
771 | /* Check if we are switching association toggle */ | |
772 | if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) != | |
773 | (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) | |
774 | return 1; | |
775 | ||
776 | return 0; | |
777 | } | |
778 | EXPORT_SYMBOL(iwl_full_rxon_required); | |
779 | ||
780 | u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv) | |
781 | { | |
782 | int i; | |
783 | int rate_mask; | |
784 | ||
785 | /* Set rate mask*/ | |
786 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) | |
787 | rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK; | |
788 | else | |
789 | rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK; | |
790 | ||
791 | /* Find lowest valid rate */ | |
792 | for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID; | |
793 | i = iwl_rates[i].next_ieee) { | |
794 | if (rate_mask & (1 << i)) | |
795 | return iwl_rates[i].plcp; | |
796 | } | |
797 | ||
798 | /* No valid rate was found. Assign the lowest one */ | |
799 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) | |
800 | return IWL_RATE_1M_PLCP; | |
801 | else | |
802 | return IWL_RATE_6M_PLCP; | |
803 | } | |
804 | EXPORT_SYMBOL(iwl_rate_get_lowest_plcp); | |
805 | ||
47c5196e TW |
806 | void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info) |
807 | { | |
c1adf9fb | 808 | struct iwl_rxon_cmd *rxon = &priv->staging_rxon; |
47c5196e | 809 | |
42eb7c64 | 810 | if (!ht_info->is_ht) { |
a2b0f02e | 811 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | |
42eb7c64 EG |
812 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | |
813 | RXON_FLG_FAT_PROT_MSK | | |
814 | RXON_FLG_HT_PROT_MSK); | |
47c5196e | 815 | return; |
42eb7c64 | 816 | } |
47c5196e | 817 | |
a2b0f02e WYG |
818 | /* FIXME: if the definition of ht_protection changed, the "translation" |
819 | * will be needed for rxon->flags | |
820 | */ | |
821 | rxon->flags |= cpu_to_le32(ht_info->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS); | |
822 | ||
823 | /* Set up channel bandwidth: | |
824 | * 20 MHz only, 20/40 mixed or pure 40 if fat ok */ | |
825 | /* clear the HT channel mode before set the mode */ | |
826 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | | |
827 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
828 | if (iwl_is_fat_tx_allowed(priv, NULL)) { | |
829 | /* pure 40 fat */ | |
830 | if (rxon->flags & RXON_FLG_FAT_PROT_MSK) | |
831 | rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40; | |
832 | else { | |
833 | /* Note: control channel is opposite of extension channel */ | |
834 | switch (ht_info->extension_chan_offset) { | |
835 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: | |
836 | rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
837 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
838 | break; | |
839 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
840 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
841 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
842 | break; | |
843 | case IEEE80211_HT_PARAM_CHA_SEC_NONE: | |
844 | default: | |
845 | /* channel location only valid if in Mixed mode */ | |
846 | IWL_ERR(priv, "invalid extension channel offset\n"); | |
847 | break; | |
848 | } | |
849 | } | |
850 | } else { | |
851 | rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY; | |
47c5196e TW |
852 | } |
853 | ||
45823531 AK |
854 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
855 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
47c5196e | 856 | |
e1623446 | 857 | IWL_DEBUG_ASSOC(priv, "supported HT rate 0x%X 0x%X 0x%X " |
47c5196e | 858 | "rxon flags 0x%X operation mode :0x%X " |
ae5eb026 | 859 | "extension channel offset 0x%x\n", |
d9fe60de JB |
860 | ht_info->mcs.rx_mask[0], |
861 | ht_info->mcs.rx_mask[1], | |
862 | ht_info->mcs.rx_mask[2], | |
47c5196e | 863 | le32_to_cpu(rxon->flags), ht_info->ht_protection, |
ae5eb026 | 864 | ht_info->extension_chan_offset); |
47c5196e TW |
865 | return; |
866 | } | |
867 | EXPORT_SYMBOL(iwl_set_rxon_ht); | |
868 | ||
9e5e6c32 TW |
869 | #define IWL_NUM_RX_CHAINS_MULTIPLE 3 |
870 | #define IWL_NUM_RX_CHAINS_SINGLE 2 | |
871 | #define IWL_NUM_IDLE_CHAINS_DUAL 2 | |
872 | #define IWL_NUM_IDLE_CHAINS_SINGLE 1 | |
873 | ||
874 | /* Determine how many receiver/antenna chains to use. | |
c7de35cd RR |
875 | * More provides better reception via diversity. Fewer saves power. |
876 | * MIMO (dual stream) requires at least 2, but works better with 3. | |
877 | * This does not determine *which* chains to use, just how many. | |
878 | */ | |
28a6b07a | 879 | static int iwl_get_active_rx_chain_count(struct iwl_priv *priv) |
c7de35cd | 880 | { |
28a6b07a TW |
881 | bool is_single = is_single_rx_stream(priv); |
882 | bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status); | |
c7de35cd RR |
883 | |
884 | /* # of Rx chains to use when expecting MIMO. */ | |
12837be1 RR |
885 | if (is_single || (!is_cam && (priv->current_ht_config.sm_ps == |
886 | WLAN_HT_CAP_SM_PS_STATIC))) | |
9e5e6c32 | 887 | return IWL_NUM_RX_CHAINS_SINGLE; |
c7de35cd | 888 | else |
9e5e6c32 | 889 | return IWL_NUM_RX_CHAINS_MULTIPLE; |
28a6b07a | 890 | } |
c7de35cd | 891 | |
28a6b07a TW |
892 | static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt) |
893 | { | |
894 | int idle_cnt; | |
895 | bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status); | |
c7de35cd | 896 | /* # Rx chains when idling and maybe trying to save power */ |
12837be1 | 897 | switch (priv->current_ht_config.sm_ps) { |
00c5ae2f TW |
898 | case WLAN_HT_CAP_SM_PS_STATIC: |
899 | case WLAN_HT_CAP_SM_PS_DYNAMIC: | |
9e5e6c32 TW |
900 | idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL : |
901 | IWL_NUM_IDLE_CHAINS_SINGLE; | |
c7de35cd | 902 | break; |
00c5ae2f | 903 | case WLAN_HT_CAP_SM_PS_DISABLED: |
9e5e6c32 | 904 | idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE; |
c7de35cd | 905 | break; |
00c5ae2f | 906 | case WLAN_HT_CAP_SM_PS_INVALID: |
c7de35cd | 907 | default: |
15b1687c | 908 | IWL_ERR(priv, "invalid mimo ps mode %d\n", |
12837be1 | 909 | priv->current_ht_config.sm_ps); |
28a6b07a TW |
910 | WARN_ON(1); |
911 | idle_cnt = -1; | |
c7de35cd RR |
912 | break; |
913 | } | |
28a6b07a | 914 | return idle_cnt; |
c7de35cd RR |
915 | } |
916 | ||
04816448 GE |
917 | /* up to 4 chains */ |
918 | static u8 iwl_count_chain_bitmap(u32 chain_bitmap) | |
919 | { | |
920 | u8 res; | |
921 | res = (chain_bitmap & BIT(0)) >> 0; | |
922 | res += (chain_bitmap & BIT(1)) >> 1; | |
923 | res += (chain_bitmap & BIT(2)) >> 2; | |
924 | res += (chain_bitmap & BIT(4)) >> 4; | |
925 | return res; | |
926 | } | |
927 | ||
4c4df78f CR |
928 | /** |
929 | * iwl_is_monitor_mode - Determine if interface in monitor mode | |
930 | * | |
931 | * priv->iw_mode is set in add_interface, but add_interface is | |
932 | * never called for monitor mode. The only way mac80211 informs us about | |
933 | * monitor mode is through configuring filters (call to configure_filter). | |
934 | */ | |
279b05d4 | 935 | bool iwl_is_monitor_mode(struct iwl_priv *priv) |
4c4df78f CR |
936 | { |
937 | return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK); | |
938 | } | |
279b05d4 | 939 | EXPORT_SYMBOL(iwl_is_monitor_mode); |
4c4df78f | 940 | |
c7de35cd RR |
941 | /** |
942 | * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image | |
943 | * | |
944 | * Selects how many and which Rx receivers/antennas/chains to use. | |
945 | * This should not be used for scan command ... it puts data in wrong place. | |
946 | */ | |
947 | void iwl_set_rxon_chain(struct iwl_priv *priv) | |
948 | { | |
28a6b07a TW |
949 | bool is_single = is_single_rx_stream(priv); |
950 | bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status); | |
04816448 GE |
951 | u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt; |
952 | u32 active_chains; | |
28a6b07a | 953 | u16 rx_chain; |
c7de35cd RR |
954 | |
955 | /* Tell uCode which antennas are actually connected. | |
956 | * Before first association, we assume all antennas are connected. | |
957 | * Just after first association, iwl_chain_noise_calibration() | |
958 | * checks which antennas actually *are* connected. */ | |
04816448 GE |
959 | if (priv->chain_noise_data.active_chains) |
960 | active_chains = priv->chain_noise_data.active_chains; | |
961 | else | |
962 | active_chains = priv->hw_params.valid_rx_ant; | |
963 | ||
964 | rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS; | |
c7de35cd RR |
965 | |
966 | /* How many receivers should we use? */ | |
28a6b07a TW |
967 | active_rx_cnt = iwl_get_active_rx_chain_count(priv); |
968 | idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt); | |
969 | ||
28a6b07a | 970 | |
04816448 GE |
971 | /* correct rx chain count according hw settings |
972 | * and chain noise calibration | |
973 | */ | |
974 | valid_rx_cnt = iwl_count_chain_bitmap(active_chains); | |
975 | if (valid_rx_cnt < active_rx_cnt) | |
976 | active_rx_cnt = valid_rx_cnt; | |
977 | ||
978 | if (valid_rx_cnt < idle_rx_cnt) | |
979 | idle_rx_cnt = valid_rx_cnt; | |
28a6b07a TW |
980 | |
981 | rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS; | |
982 | rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS; | |
983 | ||
7b841727 RF |
984 | /* copied from 'iwl_bg_request_scan()' */ |
985 | /* Force use of chains B and C (0x6) for Rx for 4965 | |
986 | * Avoid A (0x1) because of its off-channel reception on A-band. | |
987 | * MIMO is not used here, but value is required */ | |
988 | if (iwl_is_monitor_mode(priv) && | |
989 | !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) && | |
990 | ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) { | |
fff7a434 WYG |
991 | rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS; |
992 | rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS; | |
993 | rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS; | |
994 | rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS; | |
7b841727 RF |
995 | } |
996 | ||
28a6b07a TW |
997 | priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain); |
998 | ||
9e5e6c32 | 999 | if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam) |
c7de35cd RR |
1000 | priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK; |
1001 | else | |
1002 | priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK; | |
1003 | ||
e1623446 | 1004 | IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n", |
28a6b07a TW |
1005 | priv->staging_rxon.rx_chain, |
1006 | active_rx_cnt, idle_rx_cnt); | |
1007 | ||
1008 | WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 || | |
1009 | active_rx_cnt < idle_rx_cnt); | |
c7de35cd RR |
1010 | } |
1011 | EXPORT_SYMBOL(iwl_set_rxon_chain); | |
bf85ea4f AK |
1012 | |
1013 | /** | |
17e72782 | 1014 | * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON |
bf85ea4f AK |
1015 | * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz |
1016 | * @channel: Any channel valid for the requested phymode | |
1017 | ||
1018 | * In addition to setting the staging RXON, priv->phymode is also set. | |
1019 | * | |
1020 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields | |
1021 | * in the staging RXON flag structure based on the phymode | |
1022 | */ | |
17e72782 | 1023 | int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch) |
bf85ea4f | 1024 | { |
17e72782 TW |
1025 | enum ieee80211_band band = ch->band; |
1026 | u16 channel = ieee80211_frequency_to_channel(ch->center_freq); | |
1027 | ||
8622e705 | 1028 | if (!iwl_get_channel_info(priv, band, channel)) { |
e1623446 | 1029 | IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n", |
bf85ea4f AK |
1030 | channel, band); |
1031 | return -EINVAL; | |
1032 | } | |
1033 | ||
1034 | if ((le16_to_cpu(priv->staging_rxon.channel) == channel) && | |
1035 | (priv->band == band)) | |
1036 | return 0; | |
1037 | ||
1038 | priv->staging_rxon.channel = cpu_to_le16(channel); | |
1039 | if (band == IEEE80211_BAND_5GHZ) | |
1040 | priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK; | |
1041 | else | |
1042 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
1043 | ||
1044 | priv->band = band; | |
1045 | ||
e1623446 | 1046 | IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band); |
bf85ea4f AK |
1047 | |
1048 | return 0; | |
1049 | } | |
c7de35cd | 1050 | EXPORT_SYMBOL(iwl_set_rxon_channel); |
bf85ea4f | 1051 | |
8ccde88a SO |
1052 | void iwl_set_flags_for_band(struct iwl_priv *priv, |
1053 | enum ieee80211_band band) | |
1054 | { | |
1055 | if (band == IEEE80211_BAND_5GHZ) { | |
1056 | priv->staging_rxon.flags &= | |
1057 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK | |
1058 | | RXON_FLG_CCK_MSK); | |
1059 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
1060 | } else { | |
1061 | /* Copied from iwl_post_associate() */ | |
1062 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
1063 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
1064 | else | |
1065 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
1066 | ||
1067 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) | |
1068 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
1069 | ||
1070 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
1071 | priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
1072 | priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK; | |
1073 | } | |
1074 | } | |
1075 | EXPORT_SYMBOL(iwl_set_flags_for_band); | |
1076 | ||
1077 | /* | |
1078 | * initialize rxon structure with default values from eeprom | |
1079 | */ | |
1080 | void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode) | |
1081 | { | |
1082 | const struct iwl_channel_info *ch_info; | |
1083 | ||
1084 | memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon)); | |
1085 | ||
1086 | switch (mode) { | |
1087 | case NL80211_IFTYPE_AP: | |
1088 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP; | |
1089 | break; | |
1090 | ||
1091 | case NL80211_IFTYPE_STATION: | |
1092 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS; | |
1093 | priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; | |
1094 | break; | |
1095 | ||
1096 | case NL80211_IFTYPE_ADHOC: | |
1097 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS; | |
1098 | priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK; | |
1099 | priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
1100 | RXON_FILTER_ACCEPT_GRP_MSK; | |
1101 | break; | |
1102 | ||
8ccde88a SO |
1103 | default: |
1104 | IWL_ERR(priv, "Unsupported interface type %d\n", mode); | |
1105 | break; | |
1106 | } | |
1107 | ||
1108 | #if 0 | |
1109 | /* TODO: Figure out when short_preamble would be set and cache from | |
1110 | * that */ | |
1111 | if (!hw_to_local(priv->hw)->short_preamble) | |
1112 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
1113 | else | |
1114 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
1115 | #endif | |
1116 | ||
1117 | ch_info = iwl_get_channel_info(priv, priv->band, | |
1118 | le16_to_cpu(priv->active_rxon.channel)); | |
1119 | ||
1120 | if (!ch_info) | |
1121 | ch_info = &priv->channel_info[0]; | |
1122 | ||
1123 | /* | |
1124 | * in some case A channels are all non IBSS | |
1125 | * in this case force B/G channel | |
1126 | */ | |
1127 | if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) && | |
1128 | !(is_channel_ibss(ch_info))) | |
1129 | ch_info = &priv->channel_info[0]; | |
1130 | ||
1131 | priv->staging_rxon.channel = cpu_to_le16(ch_info->channel); | |
1132 | priv->band = ch_info->band; | |
1133 | ||
1134 | iwl_set_flags_for_band(priv, priv->band); | |
1135 | ||
1136 | priv->staging_rxon.ofdm_basic_rates = | |
1137 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
1138 | priv->staging_rxon.cck_basic_rates = | |
1139 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
1140 | ||
a2b0f02e WYG |
1141 | /* clear both MIX and PURE40 mode flag */ |
1142 | priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED | | |
1143 | RXON_FLG_CHANNEL_MODE_PURE_40); | |
8ccde88a SO |
1144 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
1145 | memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN); | |
1146 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff; | |
1147 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff; | |
11397a65 | 1148 | priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff; |
8ccde88a SO |
1149 | } |
1150 | EXPORT_SYMBOL(iwl_connection_init_rx_config); | |
1151 | ||
782571f4 | 1152 | static void iwl_set_rate(struct iwl_priv *priv) |
8ccde88a SO |
1153 | { |
1154 | const struct ieee80211_supported_band *hw = NULL; | |
1155 | struct ieee80211_rate *rate; | |
1156 | int i; | |
1157 | ||
1158 | hw = iwl_get_hw_mode(priv, priv->band); | |
1159 | if (!hw) { | |
1160 | IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n"); | |
1161 | return; | |
1162 | } | |
1163 | ||
1164 | priv->active_rate = 0; | |
1165 | priv->active_rate_basic = 0; | |
1166 | ||
1167 | for (i = 0; i < hw->n_bitrates; i++) { | |
1168 | rate = &(hw->bitrates[i]); | |
1169 | if (rate->hw_value < IWL_RATE_COUNT) | |
1170 | priv->active_rate |= (1 << rate->hw_value); | |
1171 | } | |
1172 | ||
e1623446 | 1173 | IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n", |
8ccde88a SO |
1174 | priv->active_rate, priv->active_rate_basic); |
1175 | ||
1176 | /* | |
1177 | * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK) | |
1178 | * otherwise set it to the default of all CCK rates and 6, 12, 24 for | |
1179 | * OFDM | |
1180 | */ | |
1181 | if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK) | |
1182 | priv->staging_rxon.cck_basic_rates = | |
1183 | ((priv->active_rate_basic & | |
1184 | IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF; | |
1185 | else | |
1186 | priv->staging_rxon.cck_basic_rates = | |
1187 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
1188 | ||
1189 | if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK) | |
1190 | priv->staging_rxon.ofdm_basic_rates = | |
1191 | ((priv->active_rate_basic & | |
1192 | (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >> | |
1193 | IWL_FIRST_OFDM_RATE) & 0xFF; | |
1194 | else | |
1195 | priv->staging_rxon.ofdm_basic_rates = | |
1196 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
1197 | } | |
8ccde88a SO |
1198 | |
1199 | void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
1200 | { | |
1201 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1202 | struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon; | |
1203 | struct iwl_csa_notification *csa = &(pkt->u.csa_notif); | |
e1623446 | 1204 | IWL_DEBUG_11H(priv, "CSA notif: channel %d, status %d\n", |
8ccde88a SO |
1205 | le16_to_cpu(csa->channel), le32_to_cpu(csa->status)); |
1206 | rxon->channel = csa->channel; | |
1207 | priv->staging_rxon.channel = csa->channel; | |
1208 | } | |
1209 | EXPORT_SYMBOL(iwl_rx_csa); | |
1210 | ||
1211 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1212 | static void iwl_print_rx_config_cmd(struct iwl_priv *priv) | |
1213 | { | |
1214 | struct iwl_rxon_cmd *rxon = &priv->staging_rxon; | |
1215 | ||
e1623446 | 1216 | IWL_DEBUG_RADIO(priv, "RX CONFIG:\n"); |
8ccde88a | 1217 | iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
e1623446 TW |
1218 | IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
1219 | IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
1220 | IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n", | |
8ccde88a | 1221 | le32_to_cpu(rxon->filter_flags)); |
e1623446 TW |
1222 | IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type); |
1223 | IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n", | |
8ccde88a | 1224 | rxon->ofdm_basic_rates); |
e1623446 TW |
1225 | IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); |
1226 | IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr); | |
1227 | IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr); | |
1228 | IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); | |
8ccde88a SO |
1229 | } |
1230 | #endif | |
1231 | ||
1232 | /** | |
1233 | * iwl_irq_handle_error - called for HW or SW error interrupt from card | |
1234 | */ | |
1235 | void iwl_irq_handle_error(struct iwl_priv *priv) | |
1236 | { | |
1237 | /* Set the FW error flag -- cleared on iwl_down */ | |
1238 | set_bit(STATUS_FW_ERROR, &priv->status); | |
1239 | ||
1240 | /* Cancel currently queued command. */ | |
1241 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
1242 | ||
1243 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1244 | if (priv->debug_level & IWL_DL_FW_ERRORS) { | |
1245 | iwl_dump_nic_error_log(priv); | |
1246 | iwl_dump_nic_event_log(priv); | |
1247 | iwl_print_rx_config_cmd(priv); | |
1248 | } | |
1249 | #endif | |
1250 | ||
1251 | wake_up_interruptible(&priv->wait_command_queue); | |
1252 | ||
1253 | /* Keep the restart process from trying to send host | |
1254 | * commands by clearing the INIT status bit */ | |
1255 | clear_bit(STATUS_READY, &priv->status); | |
1256 | ||
1257 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
e1623446 | 1258 | IWL_DEBUG(priv, IWL_DL_FW_ERRORS, |
8ccde88a SO |
1259 | "Restarting adapter due to uCode error.\n"); |
1260 | ||
8ccde88a SO |
1261 | if (priv->cfg->mod_params->restart_fw) |
1262 | queue_work(priv->workqueue, &priv->restart); | |
1263 | } | |
1264 | } | |
1265 | EXPORT_SYMBOL(iwl_irq_handle_error); | |
1266 | ||
1267 | void iwl_configure_filter(struct ieee80211_hw *hw, | |
1268 | unsigned int changed_flags, | |
1269 | unsigned int *total_flags, | |
1270 | int mc_count, struct dev_addr_list *mc_list) | |
1271 | { | |
1272 | struct iwl_priv *priv = hw->priv; | |
1273 | __le32 *filter_flags = &priv->staging_rxon.filter_flags; | |
1274 | ||
e1623446 | 1275 | IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n", |
8ccde88a SO |
1276 | changed_flags, *total_flags); |
1277 | ||
1278 | if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) { | |
1279 | if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) | |
1280 | *filter_flags |= RXON_FILTER_PROMISC_MSK; | |
1281 | else | |
1282 | *filter_flags &= ~RXON_FILTER_PROMISC_MSK; | |
1283 | } | |
1284 | if (changed_flags & FIF_ALLMULTI) { | |
1285 | if (*total_flags & FIF_ALLMULTI) | |
1286 | *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK; | |
1287 | else | |
1288 | *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK; | |
1289 | } | |
1290 | if (changed_flags & FIF_CONTROL) { | |
1291 | if (*total_flags & FIF_CONTROL) | |
1292 | *filter_flags |= RXON_FILTER_CTL2HOST_MSK; | |
1293 | else | |
1294 | *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK; | |
1295 | } | |
1296 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { | |
1297 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) | |
1298 | *filter_flags |= RXON_FILTER_BCON_AWARE_MSK; | |
1299 | else | |
1300 | *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK; | |
1301 | } | |
1302 | ||
1303 | /* We avoid iwl_commit_rxon here to commit the new filter flags | |
1304 | * since mac80211 will call ieee80211_hw_config immediately. | |
1305 | * (mc_list is not supported at this time). Otherwise, we need to | |
1306 | * queue a background iwl_commit_rxon work. | |
1307 | */ | |
1308 | ||
1309 | *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | | |
1310 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; | |
1311 | } | |
1312 | EXPORT_SYMBOL(iwl_configure_filter); | |
1313 | ||
6ba87956 | 1314 | int iwl_setup_mac(struct iwl_priv *priv) |
bf85ea4f | 1315 | { |
6ba87956 | 1316 | int ret; |
bf85ea4f | 1317 | struct ieee80211_hw *hw = priv->hw; |
e227ceac | 1318 | hw->rate_control_algorithm = "iwl-agn-rs"; |
bf85ea4f | 1319 | |
566bfe5a | 1320 | /* Tell mac80211 our characteristics */ |
605a0bd6 | 1321 | hw->flags = IEEE80211_HW_SIGNAL_DBM | |
8b30b1fe | 1322 | IEEE80211_HW_NOISE_DBM | |
4be8c387 | 1323 | IEEE80211_HW_AMPDU_AGGREGATION | |
286d9490 | 1324 | IEEE80211_HW_SPECTRUM_MGMT; |
f59ac048 | 1325 | hw->wiphy->interface_modes = |
f59ac048 LR |
1326 | BIT(NL80211_IFTYPE_STATION) | |
1327 | BIT(NL80211_IFTYPE_ADHOC); | |
ea4a82dc | 1328 | |
2a44f911 | 1329 | hw->wiphy->custom_regulatory = true; |
1ecf9fc1 JB |
1330 | |
1331 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; | |
1332 | /* we create the 802.11 header and a zero-length SSID element */ | |
1333 | hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2; | |
ea4a82dc | 1334 | |
bf85ea4f AK |
1335 | /* Default value; 4 EDCA QOS priorities */ |
1336 | hw->queues = 4; | |
6ba87956 | 1337 | |
b5d7be5e | 1338 | hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL; |
6ba87956 TW |
1339 | |
1340 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) | |
1341 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
1342 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
1343 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
1344 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
1345 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
1346 | ||
1347 | ret = ieee80211_register_hw(priv->hw); | |
1348 | if (ret) { | |
15b1687c | 1349 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); |
6ba87956 TW |
1350 | return ret; |
1351 | } | |
1352 | priv->mac80211_registered = 1; | |
1353 | ||
1354 | return 0; | |
bf85ea4f | 1355 | } |
6ba87956 | 1356 | EXPORT_SYMBOL(iwl_setup_mac); |
bf85ea4f | 1357 | |
da154e30 RR |
1358 | int iwl_set_hw_params(struct iwl_priv *priv) |
1359 | { | |
1360 | priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto; | |
1361 | priv->hw_params.max_rxq_size = RX_QUEUE_SIZE; | |
1362 | priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; | |
1363 | if (priv->cfg->mod_params->amsdu_size_8K) | |
1364 | priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K; | |
1365 | else | |
1366 | priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K; | |
1367 | priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256; | |
1368 | ||
49779293 RR |
1369 | if (priv->cfg->mod_params->disable_11n) |
1370 | priv->cfg->sku &= ~IWL_SKU_N; | |
1371 | ||
da154e30 RR |
1372 | /* Device-specific setup */ |
1373 | return priv->cfg->ops->lib->set_hw_params(priv); | |
1374 | } | |
1375 | EXPORT_SYMBOL(iwl_set_hw_params); | |
6ba87956 TW |
1376 | |
1377 | int iwl_init_drv(struct iwl_priv *priv) | |
c7de35cd RR |
1378 | { |
1379 | int ret; | |
c7de35cd | 1380 | |
c7de35cd RR |
1381 | priv->ibss_beacon = NULL; |
1382 | ||
1383 | spin_lock_init(&priv->lock); | |
c7de35cd RR |
1384 | spin_lock_init(&priv->sta_lock); |
1385 | spin_lock_init(&priv->hcmd_lock); | |
c7de35cd | 1386 | |
c7de35cd RR |
1387 | INIT_LIST_HEAD(&priv->free_frames); |
1388 | ||
1389 | mutex_init(&priv->mutex); | |
1390 | ||
1391 | /* Clear the driver's (not device's) station table */ | |
e11bc028 | 1392 | priv->cfg->ops->smgmt->clear_station_table(priv); |
c7de35cd RR |
1393 | |
1394 | priv->data_retry_limit = -1; | |
1395 | priv->ieee_channels = NULL; | |
1396 | priv->ieee_rates = NULL; | |
1397 | priv->band = IEEE80211_BAND_2GHZ; | |
1398 | ||
05c914fe | 1399 | priv->iw_mode = NL80211_IFTYPE_STATION; |
c7de35cd | 1400 | |
12837be1 | 1401 | priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED; |
c7de35cd RR |
1402 | |
1403 | /* Choose which receivers/antennas to use */ | |
45823531 AK |
1404 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
1405 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
1406 | ||
f53696de | 1407 | iwl_init_scan_params(priv); |
c7de35cd RR |
1408 | |
1409 | iwl_reset_qos(priv); | |
1410 | ||
1411 | priv->qos_data.qos_active = 0; | |
1412 | priv->qos_data.qos_cap.val = 0; | |
1413 | ||
c7de35cd | 1414 | priv->rates_mask = IWL_RATES_MASK; |
d25aabb0 WT |
1415 | /* If power management is turned on, default to CAM mode */ |
1416 | priv->power_mode = IWL_POWER_MODE_CAM; | |
630fe9b6 | 1417 | priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX; |
c7de35cd RR |
1418 | |
1419 | ret = iwl_init_channel_map(priv); | |
1420 | if (ret) { | |
15b1687c | 1421 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); |
c7de35cd RR |
1422 | goto err; |
1423 | } | |
1424 | ||
1425 | ret = iwlcore_init_geos(priv); | |
1426 | if (ret) { | |
15b1687c | 1427 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); |
c7de35cd RR |
1428 | goto err_free_channel_map; |
1429 | } | |
534166de | 1430 | iwlcore_init_hw_rates(priv, priv->ieee_rates); |
c7de35cd | 1431 | |
c7de35cd RR |
1432 | return 0; |
1433 | ||
c7de35cd RR |
1434 | err_free_channel_map: |
1435 | iwl_free_channel_map(priv); | |
1436 | err: | |
1437 | return ret; | |
1438 | } | |
6ba87956 | 1439 | EXPORT_SYMBOL(iwl_init_drv); |
c7de35cd | 1440 | |
630fe9b6 TW |
1441 | int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force) |
1442 | { | |
1443 | int ret = 0; | |
1444 | if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) { | |
daf518de WF |
1445 | IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n", |
1446 | tx_power, | |
1447 | IWL_TX_POWER_TARGET_POWER_MIN); | |
630fe9b6 TW |
1448 | return -EINVAL; |
1449 | } | |
1450 | ||
1451 | if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) { | |
daf518de WF |
1452 | IWL_WARN(priv, "Requested user TXPOWER %d above upper limit %d.\n", |
1453 | tx_power, | |
1454 | IWL_TX_POWER_TARGET_POWER_MAX); | |
630fe9b6 TW |
1455 | return -EINVAL; |
1456 | } | |
1457 | ||
1458 | if (priv->tx_power_user_lmt != tx_power) | |
1459 | force = true; | |
1460 | ||
1461 | priv->tx_power_user_lmt = tx_power; | |
1462 | ||
019fb97d MA |
1463 | /* if nic is not up don't send command */ |
1464 | if (!iwl_is_ready_rf(priv)) | |
1465 | return ret; | |
1466 | ||
630fe9b6 TW |
1467 | if (force && priv->cfg->ops->lib->send_tx_power) |
1468 | ret = priv->cfg->ops->lib->send_tx_power(priv); | |
1469 | ||
1470 | return ret; | |
1471 | } | |
1472 | EXPORT_SYMBOL(iwl_set_tx_power); | |
1473 | ||
6ba87956 | 1474 | void iwl_uninit_drv(struct iwl_priv *priv) |
bf85ea4f | 1475 | { |
6e21f2c1 | 1476 | iwl_calib_free_results(priv); |
6ba87956 TW |
1477 | iwlcore_free_geos(priv); |
1478 | iwl_free_channel_map(priv); | |
261415f7 | 1479 | kfree(priv->scan); |
bf85ea4f | 1480 | } |
6ba87956 | 1481 | EXPORT_SYMBOL(iwl_uninit_drv); |
bf85ea4f | 1482 | |
0ad91a35 WT |
1483 | |
1484 | void iwl_disable_interrupts(struct iwl_priv *priv) | |
1485 | { | |
1486 | clear_bit(STATUS_INT_ENABLED, &priv->status); | |
1487 | ||
1488 | /* disable interrupts from uCode/NIC to host */ | |
1489 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
1490 | ||
1491 | /* acknowledge/clear/reset any interrupts still pending | |
1492 | * from uCode or flow handler (Rx/Tx DMA) */ | |
1493 | iwl_write32(priv, CSR_INT, 0xffffffff); | |
1494 | iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff); | |
e1623446 | 1495 | IWL_DEBUG_ISR(priv, "Disabled interrupts\n"); |
0ad91a35 WT |
1496 | } |
1497 | EXPORT_SYMBOL(iwl_disable_interrupts); | |
1498 | ||
1499 | void iwl_enable_interrupts(struct iwl_priv *priv) | |
1500 | { | |
e1623446 | 1501 | IWL_DEBUG_ISR(priv, "Enabling interrupts\n"); |
0ad91a35 | 1502 | set_bit(STATUS_INT_ENABLED, &priv->status); |
40cefda9 | 1503 | iwl_write32(priv, CSR_INT_MASK, priv->inta_mask); |
0ad91a35 WT |
1504 | } |
1505 | EXPORT_SYMBOL(iwl_enable_interrupts); | |
1506 | ||
ef850d7c MA |
1507 | |
1508 | #define ICT_COUNT (PAGE_SIZE/sizeof(u32)) | |
1509 | ||
1510 | /* Free dram table */ | |
1511 | void iwl_free_isr_ict(struct iwl_priv *priv) | |
1512 | { | |
1513 | if (priv->ict_tbl_vir) { | |
1514 | pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) + | |
1515 | PAGE_SIZE, priv->ict_tbl_vir, | |
1516 | priv->ict_tbl_dma); | |
1517 | priv->ict_tbl_vir = NULL; | |
1518 | } | |
1519 | } | |
1520 | EXPORT_SYMBOL(iwl_free_isr_ict); | |
1521 | ||
1522 | ||
1523 | /* allocate dram shared table it is a PAGE_SIZE aligned | |
1524 | * also reset all data related to ICT table interrupt. | |
1525 | */ | |
1526 | int iwl_alloc_isr_ict(struct iwl_priv *priv) | |
1527 | { | |
1528 | ||
1529 | if (priv->cfg->use_isr_legacy) | |
1530 | return 0; | |
1531 | /* allocate shrared data table */ | |
1532 | priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) * | |
1533 | ICT_COUNT) + PAGE_SIZE, | |
1534 | &priv->ict_tbl_dma); | |
1535 | if (!priv->ict_tbl_vir) | |
1536 | return -ENOMEM; | |
1537 | ||
1538 | /* align table to PAGE_SIZE boundry */ | |
1539 | priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE); | |
1540 | ||
1541 | IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n", | |
1542 | (unsigned long long)priv->ict_tbl_dma, | |
1543 | (unsigned long long)priv->aligned_ict_tbl_dma, | |
1544 | (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma)); | |
1545 | ||
1546 | priv->ict_tbl = priv->ict_tbl_vir + | |
1547 | (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma); | |
1548 | ||
1549 | IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n", | |
1550 | priv->ict_tbl, priv->ict_tbl_vir, | |
1551 | (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma)); | |
1552 | ||
1553 | /* reset table and index to all 0 */ | |
1554 | memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE); | |
1555 | priv->ict_index = 0; | |
1556 | ||
40cefda9 MA |
1557 | /* add periodic RX interrupt */ |
1558 | priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC; | |
ef850d7c MA |
1559 | return 0; |
1560 | } | |
1561 | EXPORT_SYMBOL(iwl_alloc_isr_ict); | |
1562 | ||
1563 | /* Device is going up inform it about using ICT interrupt table, | |
1564 | * also we need to tell the driver to start using ICT interrupt. | |
1565 | */ | |
1566 | int iwl_reset_ict(struct iwl_priv *priv) | |
1567 | { | |
1568 | u32 val; | |
1569 | unsigned long flags; | |
1570 | ||
1571 | if (!priv->ict_tbl_vir) | |
1572 | return 0; | |
1573 | ||
1574 | spin_lock_irqsave(&priv->lock, flags); | |
1575 | iwl_disable_interrupts(priv); | |
1576 | ||
1577 | memset(&priv->ict_tbl[0],0, sizeof(u32) * ICT_COUNT); | |
1578 | ||
1579 | val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT; | |
1580 | ||
1581 | val |= CSR_DRAM_INT_TBL_ENABLE; | |
1582 | val |= CSR_DRAM_INIT_TBL_WRAP_CHECK; | |
1583 | ||
1584 | IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X " | |
1585 | "aligned dma address %Lx\n", | |
1586 | val, (unsigned long long)priv->aligned_ict_tbl_dma); | |
1587 | ||
1588 | iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val); | |
1589 | priv->use_ict = true; | |
1590 | priv->ict_index = 0; | |
40cefda9 | 1591 | iwl_write32(priv, CSR_INT, priv->inta_mask); |
ef850d7c MA |
1592 | iwl_enable_interrupts(priv); |
1593 | spin_unlock_irqrestore(&priv->lock, flags); | |
1594 | ||
1595 | return 0; | |
1596 | } | |
1597 | EXPORT_SYMBOL(iwl_reset_ict); | |
1598 | ||
1599 | /* Device is going down disable ict interrupt usage */ | |
1600 | void iwl_disable_ict(struct iwl_priv *priv) | |
1601 | { | |
1602 | unsigned long flags; | |
1603 | ||
1604 | spin_lock_irqsave(&priv->lock, flags); | |
1605 | priv->use_ict = false; | |
1606 | spin_unlock_irqrestore(&priv->lock, flags); | |
1607 | } | |
1608 | EXPORT_SYMBOL(iwl_disable_ict); | |
1609 | ||
1610 | /* interrupt handler using ict table, with this interrupt driver will | |
1611 | * stop using INTA register to get device's interrupt, reading this register | |
1612 | * is expensive, device will write interrupts in ICT dram table, increment | |
1613 | * index then will fire interrupt to driver, driver will OR all ICT table | |
1614 | * entries from current index up to table entry with 0 value. the result is | |
1615 | * the interrupt we need to service, driver will set the entries back to 0 and | |
1616 | * set index. | |
1617 | */ | |
1618 | irqreturn_t iwl_isr_ict(int irq, void *data) | |
1619 | { | |
1620 | struct iwl_priv *priv = data; | |
1621 | u32 inta, inta_mask; | |
1622 | u32 val = 0; | |
1623 | ||
1624 | if (!priv) | |
1625 | return IRQ_NONE; | |
1626 | ||
1627 | /* dram interrupt table not set yet, | |
1628 | * use legacy interrupt. | |
1629 | */ | |
1630 | if (!priv->use_ict) | |
1631 | return iwl_isr(irq, data); | |
1632 | ||
1633 | spin_lock(&priv->lock); | |
1634 | ||
1635 | /* Disable (but don't clear!) interrupts here to avoid | |
1636 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
1637 | * If we have something to service, the tasklet will re-enable ints. | |
1638 | * If we *don't* have something, we'll re-enable before leaving here. | |
1639 | */ | |
1640 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ | |
1641 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
1642 | ||
1643 | ||
1644 | /* Ignore interrupt if there's nothing in NIC to service. | |
1645 | * This may be due to IRQ shared with another device, | |
1646 | * or due to sporadic interrupts thrown from our NIC. */ | |
1647 | if (!priv->ict_tbl[priv->ict_index]) { | |
1648 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n"); | |
1649 | goto none; | |
1650 | } | |
1651 | ||
1652 | /* read all entries that not 0 start with ict_index */ | |
1653 | while (priv->ict_tbl[priv->ict_index]) { | |
1654 | ||
1655 | val |= priv->ict_tbl[priv->ict_index]; | |
1656 | IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n", | |
1657 | priv->ict_index, | |
1658 | priv->ict_tbl[priv->ict_index]); | |
1659 | priv->ict_tbl[priv->ict_index] = 0; | |
1660 | priv->ict_index = iwl_queue_inc_wrap(priv->ict_index, | |
1661 | ICT_COUNT); | |
1662 | ||
1663 | } | |
1664 | ||
1665 | /* We should not get this value, just ignore it. */ | |
1666 | if (val == 0xffffffff) | |
1667 | val = 0; | |
1668 | ||
1669 | inta = (0xff & val) | ((0xff00 & val) << 16); | |
1670 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n", | |
1671 | inta, inta_mask, val); | |
1672 | ||
40cefda9 | 1673 | inta &= priv->inta_mask; |
ef850d7c MA |
1674 | priv->inta |= inta; |
1675 | ||
1676 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ | |
1677 | if (likely(inta)) | |
1678 | tasklet_schedule(&priv->irq_tasklet); | |
1679 | else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) { | |
1680 | /* Allow interrupt if was disabled by this handler and | |
1681 | * no tasklet was schedules, We should not enable interrupt, | |
1682 | * tasklet will enable it. | |
1683 | */ | |
1684 | iwl_enable_interrupts(priv); | |
1685 | } | |
1686 | ||
1687 | spin_unlock(&priv->lock); | |
1688 | return IRQ_HANDLED; | |
1689 | ||
1690 | none: | |
1691 | /* re-enable interrupts here since we don't have anything to service. | |
1692 | * only Re-enable if disabled by irq. | |
1693 | */ | |
1694 | if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) | |
1695 | iwl_enable_interrupts(priv); | |
1696 | ||
1697 | spin_unlock(&priv->lock); | |
1698 | return IRQ_NONE; | |
1699 | } | |
1700 | EXPORT_SYMBOL(iwl_isr_ict); | |
1701 | ||
1702 | ||
1703 | static irqreturn_t iwl_isr(int irq, void *data) | |
1704 | { | |
1705 | struct iwl_priv *priv = data; | |
1706 | u32 inta, inta_mask; | |
d651ae32 | 1707 | #ifdef CONFIG_IWLWIFI_DEBUG |
ef850d7c | 1708 | u32 inta_fh; |
d651ae32 | 1709 | #endif |
ef850d7c MA |
1710 | if (!priv) |
1711 | return IRQ_NONE; | |
1712 | ||
1713 | spin_lock(&priv->lock); | |
1714 | ||
1715 | /* Disable (but don't clear!) interrupts here to avoid | |
1716 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
1717 | * If we have something to service, the tasklet will re-enable ints. | |
1718 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
1719 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ | |
1720 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
1721 | ||
1722 | /* Discover which interrupts are active/pending */ | |
1723 | inta = iwl_read32(priv, CSR_INT); | |
1724 | ||
1725 | /* Ignore interrupt if there's nothing in NIC to service. | |
1726 | * This may be due to IRQ shared with another device, | |
1727 | * or due to sporadic interrupts thrown from our NIC. */ | |
1728 | if (!inta) { | |
1729 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n"); | |
1730 | goto none; | |
1731 | } | |
1732 | ||
1733 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
1734 | /* Hardware disappeared. It might have already raised | |
1735 | * an interrupt */ | |
1736 | IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta); | |
1737 | goto unplugged; | |
1738 | } | |
1739 | ||
1740 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1741 | if (priv->debug_level & (IWL_DL_ISR)) { | |
1742 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
1743 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, " | |
1744 | "fh 0x%08x\n", inta, inta_mask, inta_fh); | |
1745 | } | |
1746 | #endif | |
1747 | ||
1748 | priv->inta |= inta; | |
1749 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ | |
1750 | if (likely(inta)) | |
1751 | tasklet_schedule(&priv->irq_tasklet); | |
1752 | else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) | |
1753 | iwl_enable_interrupts(priv); | |
1754 | ||
1755 | unplugged: | |
1756 | spin_unlock(&priv->lock); | |
1757 | return IRQ_HANDLED; | |
1758 | ||
1759 | none: | |
1760 | /* re-enable interrupts here since we don't have anything to service. */ | |
1761 | /* only Re-enable if diabled by irq and no schedules tasklet. */ | |
1762 | if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) | |
1763 | iwl_enable_interrupts(priv); | |
1764 | ||
1765 | spin_unlock(&priv->lock); | |
1766 | return IRQ_NONE; | |
1767 | } | |
1768 | ||
1769 | irqreturn_t iwl_isr_legacy(int irq, void *data) | |
f17d08a6 AK |
1770 | { |
1771 | struct iwl_priv *priv = data; | |
1772 | u32 inta, inta_mask; | |
1773 | u32 inta_fh; | |
1774 | if (!priv) | |
1775 | return IRQ_NONE; | |
1776 | ||
1777 | spin_lock(&priv->lock); | |
1778 | ||
1779 | /* Disable (but don't clear!) interrupts here to avoid | |
1780 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
1781 | * If we have something to service, the tasklet will re-enable ints. | |
1782 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
1783 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ | |
1784 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
1785 | ||
1786 | /* Discover which interrupts are active/pending */ | |
1787 | inta = iwl_read32(priv, CSR_INT); | |
1788 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
1789 | ||
1790 | /* Ignore interrupt if there's nothing in NIC to service. | |
1791 | * This may be due to IRQ shared with another device, | |
1792 | * or due to sporadic interrupts thrown from our NIC. */ | |
1793 | if (!inta && !inta_fh) { | |
1794 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n"); | |
1795 | goto none; | |
1796 | } | |
1797 | ||
1798 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
1799 | /* Hardware disappeared. It might have already raised | |
1800 | * an interrupt */ | |
1801 | IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta); | |
1802 | goto unplugged; | |
1803 | } | |
1804 | ||
1805 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | |
1806 | inta, inta_mask, inta_fh); | |
1807 | ||
1808 | inta &= ~CSR_INT_BIT_SCD; | |
1809 | ||
1810 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ | |
1811 | if (likely(inta || inta_fh)) | |
1812 | tasklet_schedule(&priv->irq_tasklet); | |
1813 | ||
1814 | unplugged: | |
1815 | spin_unlock(&priv->lock); | |
1816 | return IRQ_HANDLED; | |
1817 | ||
1818 | none: | |
1819 | /* re-enable interrupts here since we don't have anything to service. */ | |
1820 | /* only Re-enable if diabled by irq */ | |
1821 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
1822 | iwl_enable_interrupts(priv); | |
1823 | spin_unlock(&priv->lock); | |
1824 | return IRQ_NONE; | |
1825 | } | |
ef850d7c | 1826 | EXPORT_SYMBOL(iwl_isr_legacy); |
f17d08a6 | 1827 | |
17f841cd SO |
1828 | int iwl_send_bt_config(struct iwl_priv *priv) |
1829 | { | |
1830 | struct iwl_bt_cmd bt_cmd = { | |
1831 | .flags = 3, | |
1832 | .lead_time = 0xAA, | |
1833 | .max_kill = 1, | |
1834 | .kill_ack_mask = 0, | |
1835 | .kill_cts_mask = 0, | |
1836 | }; | |
1837 | ||
1838 | return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, | |
1839 | sizeof(struct iwl_bt_cmd), &bt_cmd); | |
1840 | } | |
1841 | EXPORT_SYMBOL(iwl_send_bt_config); | |
1842 | ||
49ea8596 EG |
1843 | int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags) |
1844 | { | |
1845 | u32 stat_flags = 0; | |
1846 | struct iwl_host_cmd cmd = { | |
1847 | .id = REPLY_STATISTICS_CMD, | |
1848 | .meta.flags = flags, | |
1849 | .len = sizeof(stat_flags), | |
1850 | .data = (u8 *) &stat_flags, | |
1851 | }; | |
1852 | return iwl_send_cmd(priv, &cmd); | |
1853 | } | |
1854 | EXPORT_SYMBOL(iwl_send_statistics_request); | |
7e8c519e | 1855 | |
b0692f2f EG |
1856 | /** |
1857 | * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host, | |
1858 | * using sample data 100 bytes apart. If these sample points are good, | |
1859 | * it's a pretty good bet that everything between them is good, too. | |
1860 | */ | |
1861 | static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) | |
1862 | { | |
1863 | u32 val; | |
1864 | int ret = 0; | |
1865 | u32 errcnt = 0; | |
1866 | u32 i; | |
1867 | ||
e1623446 | 1868 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b0692f2f | 1869 | |
b0692f2f EG |
1870 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { |
1871 | /* read data comes through single port, auto-incr addr */ | |
1872 | /* NOTE: Use the debugless read so we don't flood kernel log | |
1873 | * if IWL_DL_IO is set */ | |
1874 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, | |
250bdd21 | 1875 | i + IWL49_RTC_INST_LOWER_BOUND); |
b0692f2f EG |
1876 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
1877 | if (val != le32_to_cpu(*image)) { | |
1878 | ret = -EIO; | |
1879 | errcnt++; | |
1880 | if (errcnt >= 3) | |
1881 | break; | |
1882 | } | |
1883 | } | |
1884 | ||
b0692f2f EG |
1885 | return ret; |
1886 | } | |
1887 | ||
1888 | /** | |
1889 | * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host, | |
1890 | * looking at all data. | |
1891 | */ | |
1892 | static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image, | |
1893 | u32 len) | |
1894 | { | |
1895 | u32 val; | |
1896 | u32 save_len = len; | |
1897 | int ret = 0; | |
1898 | u32 errcnt; | |
1899 | ||
e1623446 | 1900 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b0692f2f | 1901 | |
250bdd21 SO |
1902 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
1903 | IWL49_RTC_INST_LOWER_BOUND); | |
b0692f2f EG |
1904 | |
1905 | errcnt = 0; | |
1906 | for (; len > 0; len -= sizeof(u32), image++) { | |
1907 | /* read data comes through single port, auto-incr addr */ | |
1908 | /* NOTE: Use the debugless read so we don't flood kernel log | |
1909 | * if IWL_DL_IO is set */ | |
1910 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
1911 | if (val != le32_to_cpu(*image)) { | |
15b1687c | 1912 | IWL_ERR(priv, "uCode INST section is invalid at " |
b0692f2f EG |
1913 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
1914 | save_len - len, val, le32_to_cpu(*image)); | |
1915 | ret = -EIO; | |
1916 | errcnt++; | |
1917 | if (errcnt >= 20) | |
1918 | break; | |
1919 | } | |
1920 | } | |
1921 | ||
b0692f2f | 1922 | if (!errcnt) |
e1623446 TW |
1923 | IWL_DEBUG_INFO(priv, |
1924 | "ucode image in INSTRUCTION memory is good\n"); | |
b0692f2f EG |
1925 | |
1926 | return ret; | |
1927 | } | |
1928 | ||
1929 | /** | |
1930 | * iwl_verify_ucode - determine which instruction image is in SRAM, | |
1931 | * and verify its contents | |
1932 | */ | |
1933 | int iwl_verify_ucode(struct iwl_priv *priv) | |
1934 | { | |
1935 | __le32 *image; | |
1936 | u32 len; | |
1937 | int ret; | |
1938 | ||
1939 | /* Try bootstrap */ | |
1940 | image = (__le32 *)priv->ucode_boot.v_addr; | |
1941 | len = priv->ucode_boot.len; | |
1942 | ret = iwlcore_verify_inst_sparse(priv, image, len); | |
1943 | if (!ret) { | |
e1623446 | 1944 | IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n"); |
b0692f2f EG |
1945 | return 0; |
1946 | } | |
1947 | ||
1948 | /* Try initialize */ | |
1949 | image = (__le32 *)priv->ucode_init.v_addr; | |
1950 | len = priv->ucode_init.len; | |
1951 | ret = iwlcore_verify_inst_sparse(priv, image, len); | |
1952 | if (!ret) { | |
e1623446 | 1953 | IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n"); |
b0692f2f EG |
1954 | return 0; |
1955 | } | |
1956 | ||
1957 | /* Try runtime/protocol */ | |
1958 | image = (__le32 *)priv->ucode_code.v_addr; | |
1959 | len = priv->ucode_code.len; | |
1960 | ret = iwlcore_verify_inst_sparse(priv, image, len); | |
1961 | if (!ret) { | |
e1623446 | 1962 | IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n"); |
b0692f2f EG |
1963 | return 0; |
1964 | } | |
1965 | ||
15b1687c | 1966 | IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); |
b0692f2f EG |
1967 | |
1968 | /* Since nothing seems to match, show first several data entries in | |
1969 | * instruction SRAM, so maybe visual inspection will give a clue. | |
1970 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
1971 | image = (__le32 *)priv->ucode_boot.v_addr; | |
1972 | len = priv->ucode_boot.len; | |
1973 | ret = iwl_verify_inst_full(priv, image, len); | |
1974 | ||
1975 | return ret; | |
1976 | } | |
1977 | EXPORT_SYMBOL(iwl_verify_ucode); | |
1978 | ||
56e12615 JS |
1979 | |
1980 | static const char *desc_lookup_text[] = { | |
1981 | "OK", | |
1982 | "FAIL", | |
1983 | "BAD_PARAM", | |
1984 | "BAD_CHECKSUM", | |
1985 | "NMI_INTERRUPT_WDG", | |
1986 | "SYSASSERT", | |
1987 | "FATAL_ERROR", | |
1988 | "BAD_COMMAND", | |
1989 | "HW_ERROR_TUNE_LOCK", | |
1990 | "HW_ERROR_TEMPERATURE", | |
1991 | "ILLEGAL_CHAN_FREQ", | |
1992 | "VCC_NOT_STABLE", | |
1993 | "FH_ERROR", | |
1994 | "NMI_INTERRUPT_HOST", | |
1995 | "NMI_INTERRUPT_ACTION_PT", | |
1996 | "NMI_INTERRUPT_UNKNOWN", | |
1997 | "UCODE_VERSION_MISMATCH", | |
1998 | "HW_ERROR_ABS_LOCK", | |
1999 | "HW_ERROR_CAL_LOCK_FAIL", | |
2000 | "NMI_INTERRUPT_INST_ACTION_PT", | |
2001 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
2002 | "NMI_TRM_HW_ER", | |
2003 | "NMI_INTERRUPT_TRM", | |
2004 | "NMI_INTERRUPT_BREAK_POINT" | |
2005 | "DEBUG_0", | |
2006 | "DEBUG_1", | |
2007 | "DEBUG_2", | |
2008 | "DEBUG_3", | |
2009 | "UNKNOWN" | |
2010 | }; | |
2011 | ||
ede0cba4 EK |
2012 | static const char *desc_lookup(int i) |
2013 | { | |
56e12615 JS |
2014 | int max = ARRAY_SIZE(desc_lookup_text) - 1; |
2015 | ||
2016 | if (i < 0 || i > max) | |
2017 | i = max; | |
ede0cba4 | 2018 | |
56e12615 | 2019 | return desc_lookup_text[i]; |
ede0cba4 EK |
2020 | } |
2021 | ||
2022 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
2023 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
2024 | ||
2025 | void iwl_dump_nic_error_log(struct iwl_priv *priv) | |
2026 | { | |
2027 | u32 data2, line; | |
2028 | u32 desc, time, count, base, data1; | |
2029 | u32 blink1, blink2, ilink1, ilink2; | |
ede0cba4 | 2030 | |
e1dfc085 GG |
2031 | if (priv->ucode_type == UCODE_INIT) |
2032 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | |
2033 | else | |
2034 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
ede0cba4 EK |
2035 | |
2036 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
15b1687c | 2037 | IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base); |
ede0cba4 EK |
2038 | return; |
2039 | } | |
2040 | ||
ede0cba4 EK |
2041 | count = iwl_read_targ_mem(priv, base); |
2042 | ||
2043 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
15b1687c WT |
2044 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); |
2045 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
2046 | priv->status, count); | |
ede0cba4 EK |
2047 | } |
2048 | ||
2049 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); | |
2050 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); | |
2051 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
2052 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
2053 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
2054 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
2055 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
2056 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
2057 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
2058 | ||
15b1687c | 2059 | IWL_ERR(priv, "Desc Time " |
ede0cba4 | 2060 | "data1 data2 line\n"); |
15b1687c | 2061 | IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n", |
ede0cba4 | 2062 | desc_lookup(desc), desc, time, data1, data2, line); |
15b1687c WT |
2063 | IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n"); |
2064 | IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, | |
ede0cba4 EK |
2065 | ilink1, ilink2); |
2066 | ||
ede0cba4 EK |
2067 | } |
2068 | EXPORT_SYMBOL(iwl_dump_nic_error_log); | |
2069 | ||
189a2b59 EK |
2070 | #define EVENT_START_OFFSET (4 * sizeof(u32)) |
2071 | ||
2072 | /** | |
2073 | * iwl_print_event_log - Dump error event log to syslog | |
2074 | * | |
189a2b59 | 2075 | */ |
a33c2f47 | 2076 | static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, |
189a2b59 EK |
2077 | u32 num_events, u32 mode) |
2078 | { | |
2079 | u32 i; | |
2080 | u32 base; /* SRAM byte address of event log header */ | |
2081 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
2082 | u32 ptr; /* SRAM byte address of log data */ | |
2083 | u32 ev, time, data; /* event log data */ | |
2084 | ||
2085 | if (num_events == 0) | |
2086 | return; | |
e1dfc085 GG |
2087 | if (priv->ucode_type == UCODE_INIT) |
2088 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | |
2089 | else | |
2090 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
189a2b59 EK |
2091 | |
2092 | if (mode == 0) | |
2093 | event_size = 2 * sizeof(u32); | |
2094 | else | |
2095 | event_size = 3 * sizeof(u32); | |
2096 | ||
2097 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
2098 | ||
2099 | /* "time" is actually "data" for mode 0 (no timestamp). | |
2100 | * place event id # at far right for easier visual parsing. */ | |
2101 | for (i = 0; i < num_events; i++) { | |
2102 | ev = iwl_read_targ_mem(priv, ptr); | |
2103 | ptr += sizeof(u32); | |
2104 | time = iwl_read_targ_mem(priv, ptr); | |
2105 | ptr += sizeof(u32); | |
77c5d08e TW |
2106 | if (mode == 0) { |
2107 | /* data, ev */ | |
15b1687c | 2108 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev); |
77c5d08e | 2109 | } else { |
189a2b59 EK |
2110 | data = iwl_read_targ_mem(priv, ptr); |
2111 | ptr += sizeof(u32); | |
15b1687c | 2112 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", |
77c5d08e | 2113 | time, data, ev); |
189a2b59 EK |
2114 | } |
2115 | } | |
2116 | } | |
189a2b59 EK |
2117 | |
2118 | void iwl_dump_nic_event_log(struct iwl_priv *priv) | |
2119 | { | |
189a2b59 EK |
2120 | u32 base; /* SRAM byte address of event log header */ |
2121 | u32 capacity; /* event log capacity in # entries */ | |
2122 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
2123 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
2124 | u32 next_entry; /* index of next entry to be written by uCode */ | |
2125 | u32 size; /* # entries that we'll print */ | |
2126 | ||
e1dfc085 GG |
2127 | if (priv->ucode_type == UCODE_INIT) |
2128 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | |
2129 | else | |
2130 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
2131 | ||
189a2b59 | 2132 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { |
15b1687c | 2133 | IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); |
189a2b59 EK |
2134 | return; |
2135 | } | |
2136 | ||
189a2b59 EK |
2137 | /* event log header */ |
2138 | capacity = iwl_read_targ_mem(priv, base); | |
2139 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
2140 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
2141 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
2142 | ||
2143 | size = num_wraps ? capacity : next_entry; | |
2144 | ||
2145 | /* bail out if nothing in log */ | |
2146 | if (size == 0) { | |
15b1687c | 2147 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); |
189a2b59 EK |
2148 | return; |
2149 | } | |
2150 | ||
15b1687c | 2151 | IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n", |
189a2b59 EK |
2152 | size, num_wraps); |
2153 | ||
2154 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
2155 | * i.e the next one that uCode would fill. */ | |
2156 | if (num_wraps) | |
2157 | iwl_print_event_log(priv, next_entry, | |
2158 | capacity - next_entry, mode); | |
2159 | /* (then/else) start at top of log */ | |
2160 | iwl_print_event_log(priv, 0, next_entry, mode); | |
2161 | ||
189a2b59 EK |
2162 | } |
2163 | EXPORT_SYMBOL(iwl_dump_nic_event_log); | |
2164 | ||
47f4a587 EG |
2165 | void iwl_rf_kill_ct_config(struct iwl_priv *priv) |
2166 | { | |
2167 | struct iwl_ct_kill_config cmd; | |
2168 | unsigned long flags; | |
2169 | int ret = 0; | |
2170 | ||
2171 | spin_lock_irqsave(&priv->lock, flags); | |
2172 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
2173 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); | |
2174 | spin_unlock_irqrestore(&priv->lock, flags); | |
2175 | ||
2176 | cmd.critical_temperature_R = | |
2177 | cpu_to_le32(priv->hw_params.ct_kill_threshold); | |
189a2b59 | 2178 | |
47f4a587 EG |
2179 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, |
2180 | sizeof(cmd), &cmd); | |
2181 | if (ret) | |
15b1687c | 2182 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); |
47f4a587 | 2183 | else |
e1623446 | 2184 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD succeeded, " |
47f4a587 EG |
2185 | "critical temperature is %d\n", |
2186 | cmd.critical_temperature_R); | |
2187 | } | |
2188 | EXPORT_SYMBOL(iwl_rf_kill_ct_config); | |
14a08a7f | 2189 | |
0ad91a35 | 2190 | |
14a08a7f EG |
2191 | /* |
2192 | * CARD_STATE_CMD | |
2193 | * | |
2194 | * Use: Sets the device's internal card state to enable, disable, or halt | |
2195 | * | |
2196 | * When in the 'enable' state the card operates as normal. | |
2197 | * When in the 'disable' state, the card enters into a low power mode. | |
2198 | * When in the 'halt' state, the card is shut down and must be fully | |
2199 | * restarted to come back on. | |
2200 | */ | |
c496294e | 2201 | int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag) |
14a08a7f EG |
2202 | { |
2203 | struct iwl_host_cmd cmd = { | |
2204 | .id = REPLY_CARD_STATE_CMD, | |
2205 | .len = sizeof(u32), | |
2206 | .data = &flags, | |
2207 | .meta.flags = meta_flag, | |
2208 | }; | |
2209 | ||
2210 | return iwl_send_cmd(priv, &cmd); | |
2211 | } | |
c496294e | 2212 | EXPORT_SYMBOL(iwl_send_card_state); |
14a08a7f EG |
2213 | |
2214 | void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv) | |
2215 | { | |
2216 | unsigned long flags; | |
2217 | ||
2218 | if (test_bit(STATUS_RF_KILL_SW, &priv->status)) | |
2219 | return; | |
2220 | ||
e1623446 | 2221 | IWL_DEBUG_RF_KILL(priv, "Manual SW RF KILL set to: RADIO OFF\n"); |
14a08a7f EG |
2222 | |
2223 | iwl_scan_cancel(priv); | |
2224 | /* FIXME: This is a workaround for AP */ | |
05c914fe | 2225 | if (priv->iw_mode != NL80211_IFTYPE_AP) { |
14a08a7f EG |
2226 | spin_lock_irqsave(&priv->lock, flags); |
2227 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, | |
2228 | CSR_UCODE_SW_BIT_RFKILL); | |
2229 | spin_unlock_irqrestore(&priv->lock, flags); | |
2230 | /* call the host command only if no hw rf-kill set */ | |
2231 | if (!test_bit(STATUS_RF_KILL_HW, &priv->status) && | |
2232 | iwl_is_ready(priv)) | |
2233 | iwl_send_card_state(priv, | |
2234 | CARD_STATE_CMD_DISABLE, 0); | |
2235 | set_bit(STATUS_RF_KILL_SW, &priv->status); | |
2236 | /* make sure mac80211 stop sending Tx frame */ | |
2237 | if (priv->mac80211_registered) | |
2238 | ieee80211_stop_queues(priv->hw); | |
2239 | } | |
2240 | } | |
2241 | EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio); | |
2242 | ||
2243 | int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv) | |
2244 | { | |
2245 | unsigned long flags; | |
2246 | ||
2247 | if (!test_bit(STATUS_RF_KILL_SW, &priv->status)) | |
2248 | return 0; | |
2249 | ||
e1623446 | 2250 | IWL_DEBUG_RF_KILL(priv, "Manual SW RF KILL set to: RADIO ON\n"); |
14a08a7f EG |
2251 | |
2252 | spin_lock_irqsave(&priv->lock, flags); | |
2253 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
2254 | ||
a9efa652 EG |
2255 | /* If the driver is up it will receive CARD_STATE_NOTIFICATION |
2256 | * notification where it will clear SW rfkill status. | |
2257 | * Setting it here would break the handler. Only if the | |
2258 | * interface is down we can set here since we don't | |
2259 | * receive any further notification. | |
2260 | */ | |
2261 | if (!priv->is_open) | |
2262 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
14a08a7f EG |
2263 | spin_unlock_irqrestore(&priv->lock, flags); |
2264 | ||
2265 | /* wake up ucode */ | |
2266 | msleep(10); | |
2267 | ||
14a08a7f | 2268 | iwl_read32(priv, CSR_UCODE_DRV_GP1); |
a8b50a0a | 2269 | spin_lock_irqsave(&priv->reg_lock, flags); |
14a08a7f EG |
2270 | if (!iwl_grab_nic_access(priv)) |
2271 | iwl_release_nic_access(priv); | |
a8b50a0a | 2272 | spin_unlock_irqrestore(&priv->reg_lock, flags); |
14a08a7f EG |
2273 | |
2274 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
e1623446 | 2275 | IWL_DEBUG_RF_KILL(priv, "Can not turn radio back on - " |
14a08a7f EG |
2276 | "disabled by HW switch\n"); |
2277 | return 0; | |
2278 | } | |
2279 | ||
edb34228 MA |
2280 | /* when driver is up while rfkill is on, it wont receive |
2281 | * any CARD_STATE_NOTIFICATION notifications so we have to | |
2282 | * restart it in here | |
2283 | */ | |
2284 | if (priv->is_open && !test_bit(STATUS_ALIVE, &priv->status)) { | |
2285 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
2286 | if (!iwl_is_rfkill(priv)) | |
2287 | queue_work(priv->workqueue, &priv->up); | |
2288 | } | |
2289 | ||
a9efa652 EG |
2290 | /* If the driver is already loaded, it will receive |
2291 | * CARD_STATE_NOTIFICATION notifications and the handler will | |
2292 | * call restart to reload the driver. | |
2293 | */ | |
14a08a7f EG |
2294 | return 1; |
2295 | } | |
2296 | EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio); | |
c0af96a6 SO |
2297 | |
2298 | void iwl_bg_rf_kill(struct work_struct *work) | |
2299 | { | |
2300 | struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill); | |
2301 | ||
2302 | wake_up_interruptible(&priv->wait_command_queue); | |
2303 | ||
2304 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2305 | return; | |
2306 | ||
2307 | mutex_lock(&priv->mutex); | |
2308 | ||
2309 | if (!iwl_is_rfkill(priv)) { | |
e1623446 | 2310 | IWL_DEBUG_RF_KILL(priv, |
c0af96a6 SO |
2311 | "HW and/or SW RF Kill no longer active, restarting " |
2312 | "device\n"); | |
2313 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status) && | |
55a3757a | 2314 | priv->is_open) |
c0af96a6 SO |
2315 | queue_work(priv->workqueue, &priv->restart); |
2316 | } else { | |
2317 | /* make sure mac80211 stop sending Tx frame */ | |
2318 | if (priv->mac80211_registered) | |
2319 | ieee80211_stop_queues(priv->hw); | |
2320 | ||
2321 | if (!test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
e1623446 | 2322 | IWL_DEBUG_RF_KILL(priv, "Can not turn radio back on - " |
c0af96a6 SO |
2323 | "disabled by SW switch\n"); |
2324 | else | |
2325 | IWL_WARN(priv, "Radio Frequency Kill Switch is On:\n" | |
2326 | "Kill switch must be turned off for " | |
2327 | "wireless networking to work.\n"); | |
2328 | } | |
2329 | mutex_unlock(&priv->mutex); | |
2330 | iwl_rfkill_set_hw_state(priv); | |
2331 | } | |
2332 | EXPORT_SYMBOL(iwl_bg_rf_kill); | |
030f05ed AK |
2333 | |
2334 | void iwl_rx_pm_sleep_notif(struct iwl_priv *priv, | |
2335 | struct iwl_rx_mem_buffer *rxb) | |
2336 | { | |
2337 | #ifdef CONFIG_IWLWIFI_DEBUG | |
2338 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
2339 | struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif); | |
2340 | IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n", | |
2341 | sleep->pm_sleep_mode, sleep->pm_wakeup_src); | |
2342 | #endif | |
2343 | } | |
2344 | EXPORT_SYMBOL(iwl_rx_pm_sleep_notif); | |
2345 | ||
2346 | void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv, | |
2347 | struct iwl_rx_mem_buffer *rxb) | |
2348 | { | |
2349 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
2350 | IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled " | |
2351 | "notification for %s:\n", | |
2352 | le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd)); | |
2353 | iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len)); | |
2354 | } | |
2355 | EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif); | |
261b9c33 AK |
2356 | |
2357 | void iwl_rx_reply_error(struct iwl_priv *priv, | |
2358 | struct iwl_rx_mem_buffer *rxb) | |
2359 | { | |
2360 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
2361 | ||
2362 | IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) " | |
2363 | "seq 0x%04X ser 0x%08X\n", | |
2364 | le32_to_cpu(pkt->u.err_resp.error_type), | |
2365 | get_cmd_string(pkt->u.err_resp.cmd_id), | |
2366 | pkt->u.err_resp.cmd_id, | |
2367 | le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num), | |
2368 | le32_to_cpu(pkt->u.err_resp.error_info)); | |
2369 | } | |
2370 | EXPORT_SYMBOL(iwl_rx_reply_error); | |
2371 | ||
a83b9141 WYG |
2372 | void iwl_clear_isr_stats(struct iwl_priv *priv) |
2373 | { | |
2374 | memset(&priv->isr_stats, 0, sizeof(priv->isr_stats)); | |
2375 | } | |
2376 | EXPORT_SYMBOL(iwl_clear_isr_stats); | |
2377 | ||
488829f1 AK |
2378 | int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue, |
2379 | const struct ieee80211_tx_queue_params *params) | |
2380 | { | |
2381 | struct iwl_priv *priv = hw->priv; | |
2382 | unsigned long flags; | |
2383 | int q; | |
2384 | ||
2385 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
2386 | ||
2387 | if (!iwl_is_ready_rf(priv)) { | |
2388 | IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n"); | |
2389 | return -EIO; | |
2390 | } | |
2391 | ||
2392 | if (queue >= AC_NUM) { | |
2393 | IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue); | |
2394 | return 0; | |
2395 | } | |
2396 | ||
2397 | q = AC_NUM - 1 - queue; | |
2398 | ||
2399 | spin_lock_irqsave(&priv->lock, flags); | |
2400 | ||
2401 | priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min); | |
2402 | priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max); | |
2403 | priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; | |
2404 | priv->qos_data.def_qos_parm.ac[q].edca_txop = | |
2405 | cpu_to_le16((params->txop * 32)); | |
2406 | ||
2407 | priv->qos_data.def_qos_parm.ac[q].reserved1 = 0; | |
2408 | priv->qos_data.qos_active = 1; | |
2409 | ||
2410 | if (priv->iw_mode == NL80211_IFTYPE_AP) | |
2411 | iwl_activate_qos(priv, 1); | |
2412 | else if (priv->assoc_id && iwl_is_associated(priv)) | |
2413 | iwl_activate_qos(priv, 0); | |
2414 | ||
2415 | spin_unlock_irqrestore(&priv->lock, flags); | |
2416 | ||
2417 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2418 | return 0; | |
2419 | } | |
2420 | EXPORT_SYMBOL(iwl_mac_conf_tx); | |
5bbe233b AK |
2421 | |
2422 | static void iwl_ht_conf(struct iwl_priv *priv, | |
2423 | struct ieee80211_bss_conf *bss_conf) | |
2424 | { | |
2425 | struct ieee80211_sta_ht_cap *ht_conf; | |
2426 | struct iwl_ht_info *iwl_conf = &priv->current_ht_config; | |
2427 | struct ieee80211_sta *sta; | |
2428 | ||
2429 | IWL_DEBUG_MAC80211(priv, "enter: \n"); | |
2430 | ||
2431 | if (!iwl_conf->is_ht) | |
2432 | return; | |
2433 | ||
2434 | ||
2435 | /* | |
2436 | * It is totally wrong to base global information on something | |
2437 | * that is valid only when associated, alas, this driver works | |
2438 | * that way and I don't know how to fix it. | |
2439 | */ | |
2440 | ||
2441 | rcu_read_lock(); | |
2442 | sta = ieee80211_find_sta(priv->hw, priv->bssid); | |
2443 | if (!sta) { | |
2444 | rcu_read_unlock(); | |
2445 | return; | |
2446 | } | |
2447 | ht_conf = &sta->ht_cap; | |
2448 | ||
2449 | if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20) | |
2450 | iwl_conf->sgf |= HT_SHORT_GI_20MHZ; | |
2451 | if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40) | |
2452 | iwl_conf->sgf |= HT_SHORT_GI_40MHZ; | |
2453 | ||
2454 | iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD); | |
2455 | iwl_conf->max_amsdu_size = | |
2456 | !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU); | |
2457 | ||
2458 | iwl_conf->supported_chan_width = | |
2459 | !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40); | |
2460 | ||
2461 | /* | |
2462 | * XXX: The HT configuration needs to be moved into iwl_mac_config() | |
2463 | * to be done there correctly. | |
2464 | */ | |
2465 | ||
2466 | iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_NONE; | |
2467 | if (conf_is_ht40_minus(&priv->hw->conf)) | |
2468 | iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_BELOW; | |
2469 | else if (conf_is_ht40_plus(&priv->hw->conf)) | |
2470 | iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_ABOVE; | |
2471 | ||
2472 | /* If no above or below channel supplied disable FAT channel */ | |
2473 | if (iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_ABOVE && | |
2474 | iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_BELOW) | |
2475 | iwl_conf->supported_chan_width = 0; | |
2476 | ||
2477 | iwl_conf->sm_ps = (u8)((ht_conf->cap & IEEE80211_HT_CAP_SM_PS) >> 2); | |
2478 | ||
2479 | memcpy(&iwl_conf->mcs, &ht_conf->mcs, 16); | |
2480 | ||
2481 | iwl_conf->tx_chan_width = iwl_conf->supported_chan_width != 0; | |
2482 | iwl_conf->ht_protection = | |
9ed6bcce | 2483 | bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION; |
5bbe233b | 2484 | iwl_conf->non_GF_STA_present = |
9ed6bcce | 2485 | !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); |
5bbe233b AK |
2486 | |
2487 | rcu_read_unlock(); | |
2488 | ||
2489 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2490 | } | |
2491 | ||
2492 | #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) | |
2493 | void iwl_bss_info_changed(struct ieee80211_hw *hw, | |
2d0ddec5 JB |
2494 | struct ieee80211_vif *vif, |
2495 | struct ieee80211_bss_conf *bss_conf, | |
2496 | u32 changes) | |
5bbe233b AK |
2497 | { |
2498 | struct iwl_priv *priv = hw->priv; | |
3a650292 | 2499 | int ret; |
5bbe233b AK |
2500 | |
2501 | IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes); | |
2502 | ||
2d0ddec5 JB |
2503 | if (!iwl_is_alive(priv)) |
2504 | return; | |
2505 | ||
2506 | mutex_lock(&priv->mutex); | |
2507 | ||
2508 | if (changes & BSS_CHANGED_BEACON && | |
2509 | priv->iw_mode == NL80211_IFTYPE_AP) { | |
2510 | dev_kfree_skb(priv->ibss_beacon); | |
2511 | priv->ibss_beacon = ieee80211_beacon_get(hw, vif); | |
2512 | } | |
2513 | ||
2514 | if ((changes & BSS_CHANGED_BSSID) && !iwl_is_rfkill(priv)) { | |
2515 | /* If there is currently a HW scan going on in the background | |
2516 | * then we need to cancel it else the RXON below will fail. */ | |
2517 | if (iwl_scan_cancel_timeout(priv, 100)) { | |
2518 | IWL_WARN(priv, "Aborted scan still in progress " | |
2519 | "after 100ms\n"); | |
2520 | IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n"); | |
2521 | mutex_unlock(&priv->mutex); | |
2522 | return; | |
2523 | } | |
2524 | memcpy(priv->staging_rxon.bssid_addr, | |
2525 | bss_conf->bssid, ETH_ALEN); | |
2526 | ||
2527 | /* TODO: Audit driver for usage of these members and see | |
2528 | * if mac80211 deprecates them (priv->bssid looks like it | |
2529 | * shouldn't be there, but I haven't scanned the IBSS code | |
2530 | * to verify) - jpk */ | |
2531 | memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN); | |
2532 | ||
2533 | if (priv->iw_mode == NL80211_IFTYPE_AP) | |
2534 | iwlcore_config_ap(priv); | |
2535 | else { | |
2536 | int rc = iwlcore_commit_rxon(priv); | |
2537 | if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc) | |
2538 | iwl_rxon_add_station( | |
2539 | priv, priv->active_rxon.bssid_addr, 1); | |
2540 | } | |
2541 | } else if (!iwl_is_rfkill(priv)) { | |
2542 | iwl_scan_cancel_timeout(priv, 100); | |
2543 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
2544 | iwlcore_commit_rxon(priv); | |
2545 | } | |
2546 | ||
2547 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC && | |
2548 | changes & BSS_CHANGED_BEACON) { | |
2549 | struct sk_buff *beacon = ieee80211_beacon_get(hw, vif); | |
2550 | ||
2551 | if (beacon) | |
2552 | iwl_mac_beacon_update(hw, beacon); | |
2553 | } | |
2554 | ||
2555 | mutex_unlock(&priv->mutex); | |
2556 | ||
5bbe233b AK |
2557 | if (changes & BSS_CHANGED_ERP_PREAMBLE) { |
2558 | IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n", | |
2559 | bss_conf->use_short_preamble); | |
2560 | if (bss_conf->use_short_preamble) | |
2561 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2562 | else | |
2563 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2564 | } | |
2565 | ||
2566 | if (changes & BSS_CHANGED_ERP_CTS_PROT) { | |
2567 | IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot); | |
2568 | if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ)) | |
2569 | priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK; | |
2570 | else | |
2571 | priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK; | |
2572 | } | |
2573 | ||
2574 | if (changes & BSS_CHANGED_HT) { | |
2575 | iwl_ht_conf(priv, bss_conf); | |
45823531 AK |
2576 | |
2577 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
2578 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
5bbe233b AK |
2579 | } |
2580 | ||
2581 | if (changes & BSS_CHANGED_ASSOC) { | |
2582 | IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc); | |
2583 | /* This should never happen as this function should | |
2584 | * never be called from interrupt context. */ | |
2585 | if (WARN_ON_ONCE(in_interrupt())) | |
2586 | return; | |
2587 | if (bss_conf->assoc) { | |
2588 | priv->assoc_id = bss_conf->aid; | |
2589 | priv->beacon_int = bss_conf->beacon_int; | |
2590 | priv->power_data.dtim_period = bss_conf->dtim_period; | |
2591 | priv->timestamp = bss_conf->timestamp; | |
2592 | priv->assoc_capability = bss_conf->assoc_capability; | |
2593 | ||
2594 | /* we have just associated, don't start scan too early | |
2595 | * leave time for EAPOL exchange to complete | |
2596 | */ | |
2597 | priv->next_scan_jiffies = jiffies + | |
2598 | IWL_DELAY_NEXT_SCAN_AFTER_ASSOC; | |
2599 | mutex_lock(&priv->mutex); | |
2600 | priv->cfg->ops->lib->post_associate(priv); | |
2601 | mutex_unlock(&priv->mutex); | |
2602 | } else { | |
2603 | priv->assoc_id = 0; | |
2604 | IWL_DEBUG_MAC80211(priv, "DISASSOC %d\n", bss_conf->assoc); | |
2605 | } | |
2606 | } else if (changes && iwl_is_associated(priv) && priv->assoc_id) { | |
2607 | IWL_DEBUG_MAC80211(priv, "Associated Changes %d\n", changes); | |
3a650292 MA |
2608 | ret = iwl_send_rxon_assoc(priv); |
2609 | if (!ret) | |
2610 | /* Sync active_rxon with latest change. */ | |
2611 | memcpy((void *)&priv->active_rxon, | |
2612 | &priv->staging_rxon, | |
2613 | sizeof(struct iwl_rxon_cmd)); | |
5bbe233b | 2614 | } |
2d0ddec5 | 2615 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
5bbe233b AK |
2616 | } |
2617 | EXPORT_SYMBOL(iwl_bss_info_changed); | |
2618 | ||
9944b938 AK |
2619 | int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb) |
2620 | { | |
2621 | struct iwl_priv *priv = hw->priv; | |
2622 | unsigned long flags; | |
2623 | __le64 timestamp; | |
2624 | ||
2625 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
2626 | ||
2627 | if (!iwl_is_ready_rf(priv)) { | |
2628 | IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n"); | |
2629 | return -EIO; | |
2630 | } | |
2631 | ||
2632 | if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { | |
2633 | IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n"); | |
2634 | return -EIO; | |
2635 | } | |
2636 | ||
2637 | spin_lock_irqsave(&priv->lock, flags); | |
2638 | ||
2639 | if (priv->ibss_beacon) | |
2640 | dev_kfree_skb(priv->ibss_beacon); | |
2641 | ||
2642 | priv->ibss_beacon = skb; | |
2643 | ||
2644 | priv->assoc_id = 0; | |
2645 | timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp; | |
2646 | priv->timestamp = le64_to_cpu(timestamp); | |
2647 | ||
2648 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2649 | spin_unlock_irqrestore(&priv->lock, flags); | |
2650 | ||
2651 | iwl_reset_qos(priv); | |
2652 | ||
2653 | priv->cfg->ops->lib->post_associate(priv); | |
2654 | ||
2655 | ||
2656 | return 0; | |
2657 | } | |
2658 | EXPORT_SYMBOL(iwl_mac_beacon_update); | |
2659 | ||
727882d6 AK |
2660 | int iwl_set_mode(struct iwl_priv *priv, int mode) |
2661 | { | |
2662 | if (mode == NL80211_IFTYPE_ADHOC) { | |
2663 | const struct iwl_channel_info *ch_info; | |
2664 | ||
2665 | ch_info = iwl_get_channel_info(priv, | |
2666 | priv->band, | |
2667 | le16_to_cpu(priv->staging_rxon.channel)); | |
2668 | ||
2669 | if (!ch_info || !is_channel_ibss(ch_info)) { | |
2670 | IWL_ERR(priv, "channel %d not IBSS channel\n", | |
2671 | le16_to_cpu(priv->staging_rxon.channel)); | |
2672 | return -EINVAL; | |
2673 | } | |
2674 | } | |
2675 | ||
2676 | iwl_connection_init_rx_config(priv, mode); | |
2677 | ||
2678 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
2679 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
2680 | ||
2681 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); | |
2682 | ||
2683 | priv->cfg->ops->smgmt->clear_station_table(priv); | |
2684 | ||
2685 | /* dont commit rxon if rf-kill is on*/ | |
2686 | if (!iwl_is_ready_rf(priv)) | |
2687 | return -EAGAIN; | |
2688 | ||
727882d6 AK |
2689 | iwlcore_commit_rxon(priv); |
2690 | ||
2691 | return 0; | |
2692 | } | |
2693 | EXPORT_SYMBOL(iwl_set_mode); | |
2694 | ||
cbb6ab94 AK |
2695 | int iwl_mac_add_interface(struct ieee80211_hw *hw, |
2696 | struct ieee80211_if_init_conf *conf) | |
2697 | { | |
2698 | struct iwl_priv *priv = hw->priv; | |
2699 | unsigned long flags; | |
2700 | ||
2701 | IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type); | |
2702 | ||
2703 | if (priv->vif) { | |
2704 | IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n"); | |
2705 | return -EOPNOTSUPP; | |
2706 | } | |
2707 | ||
2708 | spin_lock_irqsave(&priv->lock, flags); | |
2709 | priv->vif = conf->vif; | |
2710 | priv->iw_mode = conf->type; | |
2711 | ||
2712 | spin_unlock_irqrestore(&priv->lock, flags); | |
2713 | ||
2714 | mutex_lock(&priv->mutex); | |
2715 | ||
2716 | if (conf->mac_addr) { | |
2717 | IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr); | |
2718 | memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); | |
2719 | } | |
2720 | ||
2721 | if (iwl_set_mode(priv, conf->type) == -EAGAIN) | |
2722 | /* we are not ready, will run again when ready */ | |
2723 | set_bit(STATUS_MODE_PENDING, &priv->status); | |
2724 | ||
2725 | mutex_unlock(&priv->mutex); | |
2726 | ||
2727 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2728 | return 0; | |
2729 | } | |
2730 | EXPORT_SYMBOL(iwl_mac_add_interface); | |
2731 | ||
d8052319 AK |
2732 | void iwl_mac_remove_interface(struct ieee80211_hw *hw, |
2733 | struct ieee80211_if_init_conf *conf) | |
2734 | { | |
2735 | struct iwl_priv *priv = hw->priv; | |
2736 | ||
2737 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
2738 | ||
2739 | mutex_lock(&priv->mutex); | |
2740 | ||
2741 | if (iwl_is_ready_rf(priv)) { | |
2742 | iwl_scan_cancel_timeout(priv, 100); | |
2743 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
2744 | iwlcore_commit_rxon(priv); | |
2745 | } | |
2746 | if (priv->vif == conf->vif) { | |
2747 | priv->vif = NULL; | |
2748 | memset(priv->bssid, 0, ETH_ALEN); | |
2749 | } | |
2750 | mutex_unlock(&priv->mutex); | |
2751 | ||
2752 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2753 | ||
2754 | } | |
2755 | EXPORT_SYMBOL(iwl_mac_remove_interface); | |
2756 | ||
4808368d AK |
2757 | /** |
2758 | * iwl_mac_config - mac80211 config callback | |
2759 | * | |
2760 | * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to | |
2761 | * be set inappropriately and the driver currently sets the hardware up to | |
2762 | * use it whenever needed. | |
2763 | */ | |
2764 | int iwl_mac_config(struct ieee80211_hw *hw, u32 changed) | |
2765 | { | |
2766 | struct iwl_priv *priv = hw->priv; | |
2767 | const struct iwl_channel_info *ch_info; | |
2768 | struct ieee80211_conf *conf = &hw->conf; | |
2769 | unsigned long flags = 0; | |
2770 | int ret = 0; | |
2771 | u16 ch; | |
2772 | int scan_active = 0; | |
2773 | ||
2774 | mutex_lock(&priv->mutex); | |
2775 | ||
4808368d AK |
2776 | IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n", |
2777 | conf->channel->hw_value, changed); | |
2778 | ||
2779 | if (unlikely(!priv->cfg->mod_params->disable_hw_scan && | |
2780 | test_bit(STATUS_SCANNING, &priv->status))) { | |
2781 | scan_active = 1; | |
2782 | IWL_DEBUG_MAC80211(priv, "leave - scanning\n"); | |
2783 | } | |
2784 | ||
2785 | ||
2786 | /* during scanning mac80211 will delay channel setting until | |
2787 | * scan finish with changed = 0 | |
2788 | */ | |
2789 | if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { | |
2790 | if (scan_active) | |
2791 | goto set_ch_out; | |
2792 | ||
2793 | ch = ieee80211_frequency_to_channel(conf->channel->center_freq); | |
2794 | ch_info = iwl_get_channel_info(priv, conf->channel->band, ch); | |
2795 | if (!is_channel_valid(ch_info)) { | |
2796 | IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n"); | |
2797 | ret = -EINVAL; | |
2798 | goto set_ch_out; | |
2799 | } | |
2800 | ||
2801 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC && | |
2802 | !is_channel_ibss(ch_info)) { | |
2803 | IWL_ERR(priv, "channel %d in band %d not " | |
2804 | "IBSS channel\n", | |
2805 | conf->channel->hw_value, conf->channel->band); | |
2806 | ret = -EINVAL; | |
2807 | goto set_ch_out; | |
2808 | } | |
2809 | ||
2810 | priv->current_ht_config.is_ht = conf_is_ht(conf); | |
2811 | ||
2812 | spin_lock_irqsave(&priv->lock, flags); | |
2813 | ||
2814 | ||
2815 | /* if we are switching from ht to 2.4 clear flags | |
2816 | * from any ht related info since 2.4 does not | |
2817 | * support ht */ | |
2818 | if ((le16_to_cpu(priv->staging_rxon.channel) != ch)) | |
2819 | priv->staging_rxon.flags = 0; | |
2820 | ||
2821 | iwl_set_rxon_channel(priv, conf->channel); | |
2822 | ||
2823 | iwl_set_flags_for_band(priv, conf->channel->band); | |
2824 | spin_unlock_irqrestore(&priv->lock, flags); | |
2825 | set_ch_out: | |
2826 | /* The list of supported rates and rate mask can be different | |
2827 | * for each band; since the band may have changed, reset | |
2828 | * the rate mask to what mac80211 lists */ | |
2829 | iwl_set_rate(priv); | |
2830 | } | |
2831 | ||
7af2c460 JB |
2832 | if (changed & IEEE80211_CONF_CHANGE_PS && |
2833 | priv->iw_mode == NL80211_IFTYPE_STATION) { | |
2834 | priv->power_data.power_disabled = | |
2835 | !(conf->flags & IEEE80211_CONF_PS); | |
2836 | ret = iwl_power_update_mode(priv, 0); | |
4808368d AK |
2837 | if (ret) |
2838 | IWL_DEBUG_MAC80211(priv, "Error setting power level\n"); | |
4808368d AK |
2839 | } |
2840 | ||
2841 | if (changed & IEEE80211_CONF_CHANGE_POWER) { | |
2842 | IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n", | |
2843 | priv->tx_power_user_lmt, conf->power_level); | |
2844 | ||
2845 | iwl_set_tx_power(priv, conf->power_level, false); | |
2846 | } | |
2847 | ||
2848 | /* call to ensure that 4965 rx_chain is set properly in monitor mode */ | |
2849 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
2850 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
2851 | ||
2852 | if (changed & IEEE80211_CONF_CHANGE_RADIO_ENABLED) { | |
2853 | if (conf->radio_enabled && | |
2854 | iwl_radio_kill_sw_enable_radio(priv)) { | |
2855 | IWL_DEBUG_MAC80211(priv, "leave - RF-KILL - " | |
2856 | "waiting for uCode\n"); | |
2857 | goto out; | |
2858 | } | |
2859 | ||
2860 | if (!conf->radio_enabled) | |
2861 | iwl_radio_kill_sw_disable_radio(priv); | |
2862 | } | |
2863 | ||
2864 | if (!conf->radio_enabled) { | |
2865 | IWL_DEBUG_MAC80211(priv, "leave - radio disabled\n"); | |
2866 | goto out; | |
2867 | } | |
2868 | ||
0cf4c01e MA |
2869 | if (!iwl_is_ready(priv)) { |
2870 | IWL_DEBUG_MAC80211(priv, "leave - not ready\n"); | |
2871 | goto out; | |
2872 | } | |
2873 | ||
4808368d AK |
2874 | if (scan_active) |
2875 | goto out; | |
2876 | ||
2877 | if (memcmp(&priv->active_rxon, | |
2878 | &priv->staging_rxon, sizeof(priv->staging_rxon))) | |
2879 | iwlcore_commit_rxon(priv); | |
2880 | else | |
2881 | IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n"); | |
2882 | ||
2883 | ||
2884 | out: | |
2885 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2886 | mutex_unlock(&priv->mutex); | |
2887 | return ret; | |
2888 | } | |
2889 | EXPORT_SYMBOL(iwl_mac_config); | |
2890 | ||
aa89f31e AK |
2891 | int iwl_mac_get_tx_stats(struct ieee80211_hw *hw, |
2892 | struct ieee80211_tx_queue_stats *stats) | |
2893 | { | |
2894 | struct iwl_priv *priv = hw->priv; | |
2895 | int i, avail; | |
2896 | struct iwl_tx_queue *txq; | |
2897 | struct iwl_queue *q; | |
2898 | unsigned long flags; | |
2899 | ||
2900 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
2901 | ||
2902 | if (!iwl_is_ready_rf(priv)) { | |
2903 | IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n"); | |
2904 | return -EIO; | |
2905 | } | |
2906 | ||
2907 | spin_lock_irqsave(&priv->lock, flags); | |
2908 | ||
2909 | for (i = 0; i < AC_NUM; i++) { | |
2910 | txq = &priv->txq[i]; | |
2911 | q = &txq->q; | |
2912 | avail = iwl_queue_space(q); | |
2913 | ||
2914 | stats[i].len = q->n_window - avail; | |
2915 | stats[i].limit = q->n_window - q->high_mark; | |
2916 | stats[i].count = q->n_window; | |
2917 | ||
2918 | } | |
2919 | spin_unlock_irqrestore(&priv->lock, flags); | |
2920 | ||
2921 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2922 | ||
2923 | return 0; | |
2924 | } | |
2925 | EXPORT_SYMBOL(iwl_mac_get_tx_stats); | |
2926 | ||
bd564261 AK |
2927 | void iwl_mac_reset_tsf(struct ieee80211_hw *hw) |
2928 | { | |
2929 | struct iwl_priv *priv = hw->priv; | |
2930 | unsigned long flags; | |
2931 | ||
2932 | mutex_lock(&priv->mutex); | |
2933 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
2934 | ||
2935 | spin_lock_irqsave(&priv->lock, flags); | |
2936 | memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info)); | |
2937 | spin_unlock_irqrestore(&priv->lock, flags); | |
2938 | ||
2939 | iwl_reset_qos(priv); | |
2940 | ||
2941 | spin_lock_irqsave(&priv->lock, flags); | |
2942 | priv->assoc_id = 0; | |
2943 | priv->assoc_capability = 0; | |
2944 | priv->assoc_station_added = 0; | |
2945 | ||
2946 | /* new association get rid of ibss beacon skb */ | |
2947 | if (priv->ibss_beacon) | |
2948 | dev_kfree_skb(priv->ibss_beacon); | |
2949 | ||
2950 | priv->ibss_beacon = NULL; | |
2951 | ||
57c4d7b4 | 2952 | priv->beacon_int = priv->vif->bss_conf.beacon_int; |
bd564261 AK |
2953 | priv->timestamp = 0; |
2954 | if ((priv->iw_mode == NL80211_IFTYPE_STATION)) | |
2955 | priv->beacon_int = 0; | |
2956 | ||
2957 | spin_unlock_irqrestore(&priv->lock, flags); | |
2958 | ||
2959 | if (!iwl_is_ready_rf(priv)) { | |
2960 | IWL_DEBUG_MAC80211(priv, "leave - not ready\n"); | |
2961 | mutex_unlock(&priv->mutex); | |
2962 | return; | |
2963 | } | |
2964 | ||
2965 | /* we are restarting association process | |
2966 | * clear RXON_FILTER_ASSOC_MSK bit | |
2967 | */ | |
2968 | if (priv->iw_mode != NL80211_IFTYPE_AP) { | |
2969 | iwl_scan_cancel_timeout(priv, 100); | |
2970 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
2971 | iwlcore_commit_rxon(priv); | |
2972 | } | |
2973 | ||
bd564261 | 2974 | if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { |
bd564261 AK |
2975 | IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n"); |
2976 | mutex_unlock(&priv->mutex); | |
2977 | return; | |
2978 | } | |
2979 | ||
2980 | iwl_set_rate(priv); | |
2981 | ||
2982 | mutex_unlock(&priv->mutex); | |
2983 | ||
2984 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2985 | } | |
2986 | EXPORT_SYMBOL(iwl_mac_reset_tsf); | |
2987 | ||
6da3a13e WYG |
2988 | #ifdef CONFIG_PM |
2989 | ||
2990 | int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
2991 | { | |
2992 | struct iwl_priv *priv = pci_get_drvdata(pdev); | |
2993 | ||
2994 | /* | |
2995 | * This function is called when system goes into suspend state | |
2996 | * mac80211 will call iwl_mac_stop() from the mac80211 suspend function | |
2997 | * first but since iwl_mac_stop() has no knowledge of who the caller is, | |
2998 | * it will not call apm_ops.stop() to stop the DMA operation. | |
2999 | * Calling apm_ops.stop here to make sure we stop the DMA. | |
3000 | */ | |
3001 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
3002 | ||
3003 | pci_save_state(pdev); | |
3004 | pci_disable_device(pdev); | |
3005 | pci_set_power_state(pdev, PCI_D3hot); | |
3006 | ||
3007 | return 0; | |
3008 | } | |
3009 | EXPORT_SYMBOL(iwl_pci_suspend); | |
3010 | ||
3011 | int iwl_pci_resume(struct pci_dev *pdev) | |
3012 | { | |
3013 | struct iwl_priv *priv = pci_get_drvdata(pdev); | |
3014 | int ret; | |
3015 | ||
3016 | pci_set_power_state(pdev, PCI_D0); | |
3017 | ret = pci_enable_device(pdev); | |
3018 | if (ret) | |
3019 | return ret; | |
3020 | pci_restore_state(pdev); | |
3021 | iwl_enable_interrupts(priv); | |
3022 | ||
3023 | return 0; | |
3024 | } | |
3025 | EXPORT_SYMBOL(iwl_pci_resume); | |
3026 | ||
3027 | #endif /* CONFIG_PM */ |