Commit | Line | Data |
---|---|---|
df48c323 | 1 | /****************************************************************************** |
df48c323 TW |
2 | * |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
01f8162a | 5 | * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved. |
df48c323 TW |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
df48c323 TW |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | *****************************************************************************/ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
8ccde88a | 31 | #include <linux/etherdevice.h> |
1d0a082d | 32 | #include <net/mac80211.h> |
df48c323 | 33 | |
6bc913bd | 34 | #include "iwl-eeprom.h" |
3e0d4cb1 | 35 | #include "iwl-dev.h" /* FIXME: remove */ |
19335774 | 36 | #include "iwl-debug.h" |
df48c323 | 37 | #include "iwl-core.h" |
b661c819 | 38 | #include "iwl-io.h" |
5da4b55f | 39 | #include "iwl-power.h" |
83dde8c9 | 40 | #include "iwl-sta.h" |
ef850d7c | 41 | #include "iwl-helpers.h" |
df48c323 | 42 | |
1d0a082d | 43 | |
df48c323 TW |
44 | MODULE_DESCRIPTION("iwl core"); |
45 | MODULE_VERSION(IWLWIFI_VERSION); | |
a7b75207 | 46 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
712b6cf5 | 47 | MODULE_LICENSE("GPL"); |
df48c323 | 48 | |
c7de35cd RR |
49 | #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \ |
50 | [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \ | |
51 | IWL_RATE_SISO_##s##M_PLCP, \ | |
52 | IWL_RATE_MIMO2_##s##M_PLCP,\ | |
53 | IWL_RATE_MIMO3_##s##M_PLCP,\ | |
54 | IWL_RATE_##r##M_IEEE, \ | |
55 | IWL_RATE_##ip##M_INDEX, \ | |
56 | IWL_RATE_##in##M_INDEX, \ | |
57 | IWL_RATE_##rp##M_INDEX, \ | |
58 | IWL_RATE_##rn##M_INDEX, \ | |
59 | IWL_RATE_##pp##M_INDEX, \ | |
60 | IWL_RATE_##np##M_INDEX } | |
61 | ||
a562a9dd RC |
62 | u32 iwl_debug_level; |
63 | EXPORT_SYMBOL(iwl_debug_level); | |
64 | ||
ef850d7c MA |
65 | static irqreturn_t iwl_isr(int irq, void *data); |
66 | ||
c7de35cd RR |
67 | /* |
68 | * Parameter order: | |
69 | * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate | |
70 | * | |
71 | * If there isn't a valid next or previous rate then INV is used which | |
72 | * maps to IWL_RATE_INVALID | |
73 | * | |
74 | */ | |
1826dcc0 | 75 | const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = { |
c7de35cd RR |
76 | IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */ |
77 | IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */ | |
78 | IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */ | |
79 | IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */ | |
80 | IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */ | |
81 | IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */ | |
82 | IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */ | |
83 | IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */ | |
84 | IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */ | |
85 | IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */ | |
86 | IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */ | |
87 | IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */ | |
88 | IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */ | |
89 | /* FIXME:RS: ^^ should be INV (legacy) */ | |
90 | }; | |
1826dcc0 | 91 | EXPORT_SYMBOL(iwl_rates); |
c7de35cd | 92 | |
e7d326ac TW |
93 | /** |
94 | * translate ucode response to mac80211 tx status control values | |
95 | */ | |
96 | void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags, | |
e6a9854b | 97 | struct ieee80211_tx_info *info) |
e7d326ac TW |
98 | { |
99 | int rate_index; | |
e6a9854b | 100 | struct ieee80211_tx_rate *r = &info->control.rates[0]; |
e7d326ac | 101 | |
e6a9854b | 102 | info->antenna_sel_tx = |
e7d326ac TW |
103 | ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS); |
104 | if (rate_n_flags & RATE_MCS_HT_MSK) | |
e6a9854b | 105 | r->flags |= IEEE80211_TX_RC_MCS; |
e7d326ac | 106 | if (rate_n_flags & RATE_MCS_GF_MSK) |
e6a9854b | 107 | r->flags |= IEEE80211_TX_RC_GREEN_FIELD; |
7aafef1c | 108 | if (rate_n_flags & RATE_MCS_HT40_MSK) |
e6a9854b | 109 | r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; |
e7d326ac | 110 | if (rate_n_flags & RATE_MCS_DUP_MSK) |
e6a9854b | 111 | r->flags |= IEEE80211_TX_RC_DUP_DATA; |
e7d326ac | 112 | if (rate_n_flags & RATE_MCS_SGI_MSK) |
e6a9854b | 113 | r->flags |= IEEE80211_TX_RC_SHORT_GI; |
e7d326ac | 114 | rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags); |
e6a9854b | 115 | if (info->band == IEEE80211_BAND_5GHZ) |
e7d326ac | 116 | rate_index -= IWL_FIRST_OFDM_RATE; |
e6a9854b | 117 | r->idx = rate_index; |
e7d326ac TW |
118 | } |
119 | EXPORT_SYMBOL(iwl_hwrate_to_tx_control); | |
120 | ||
121 | int iwl_hwrate_to_plcp_idx(u32 rate_n_flags) | |
122 | { | |
123 | int idx = 0; | |
124 | ||
125 | /* HT rate format */ | |
126 | if (rate_n_flags & RATE_MCS_HT_MSK) { | |
127 | idx = (rate_n_flags & 0xff); | |
128 | ||
60d32215 DH |
129 | if (idx >= IWL_RATE_MIMO3_6M_PLCP) |
130 | idx = idx - IWL_RATE_MIMO3_6M_PLCP; | |
131 | else if (idx >= IWL_RATE_MIMO2_6M_PLCP) | |
e7d326ac TW |
132 | idx = idx - IWL_RATE_MIMO2_6M_PLCP; |
133 | ||
134 | idx += IWL_FIRST_OFDM_RATE; | |
135 | /* skip 9M not supported in ht*/ | |
136 | if (idx >= IWL_RATE_9M_INDEX) | |
137 | idx += 1; | |
138 | if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE)) | |
139 | return idx; | |
140 | ||
141 | /* legacy rate format, search for match in table */ | |
142 | } else { | |
143 | for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++) | |
144 | if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF)) | |
145 | return idx; | |
146 | } | |
147 | ||
148 | return -1; | |
149 | } | |
150 | EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx); | |
151 | ||
76eff18b TW |
152 | u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant) |
153 | { | |
154 | int i; | |
155 | u8 ind = ant; | |
156 | for (i = 0; i < RATE_ANT_NUM - 1; i++) { | |
157 | ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0; | |
158 | if (priv->hw_params.valid_tx_ant & BIT(ind)) | |
159 | return ind; | |
160 | } | |
161 | return ant; | |
162 | } | |
57bd1bea TW |
163 | |
164 | const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; | |
165 | EXPORT_SYMBOL(iwl_bcast_addr); | |
166 | ||
167 | ||
1d0a082d AK |
168 | /* This function both allocates and initializes hw and priv. */ |
169 | struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg, | |
170 | struct ieee80211_ops *hw_ops) | |
171 | { | |
172 | struct iwl_priv *priv; | |
173 | ||
174 | /* mac80211 allocates memory for this device instance, including | |
175 | * space for this driver's private structure */ | |
176 | struct ieee80211_hw *hw = | |
177 | ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops); | |
178 | if (hw == NULL) { | |
a3139c59 SO |
179 | printk(KERN_ERR "%s: Can not allocate network device\n", |
180 | cfg->name); | |
1d0a082d AK |
181 | goto out; |
182 | } | |
183 | ||
184 | priv = hw->priv; | |
185 | priv->hw = hw; | |
186 | ||
187 | out: | |
188 | return hw; | |
189 | } | |
190 | EXPORT_SYMBOL(iwl_alloc_all); | |
191 | ||
b661c819 TW |
192 | void iwl_hw_detect(struct iwl_priv *priv) |
193 | { | |
194 | priv->hw_rev = _iwl_read32(priv, CSR_HW_REV); | |
195 | priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG); | |
196 | pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id); | |
197 | } | |
198 | EXPORT_SYMBOL(iwl_hw_detect); | |
199 | ||
1053d35f RR |
200 | int iwl_hw_nic_init(struct iwl_priv *priv) |
201 | { | |
202 | unsigned long flags; | |
203 | struct iwl_rx_queue *rxq = &priv->rxq; | |
204 | int ret; | |
205 | ||
206 | /* nic_init */ | |
1053d35f | 207 | spin_lock_irqsave(&priv->lock, flags); |
1b73af82 | 208 | priv->cfg->ops->lib->apm_ops.init(priv); |
1053d35f RR |
209 | iwl_write32(priv, CSR_INT_COALESCING, 512 / 32); |
210 | spin_unlock_irqrestore(&priv->lock, flags); | |
211 | ||
212 | ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN); | |
213 | ||
214 | priv->cfg->ops->lib->apm_ops.config(priv); | |
215 | ||
216 | /* Allocate the RX queue, or reset if it is already allocated */ | |
217 | if (!rxq->bd) { | |
218 | ret = iwl_rx_queue_alloc(priv); | |
219 | if (ret) { | |
15b1687c | 220 | IWL_ERR(priv, "Unable to initialize Rx queue\n"); |
1053d35f RR |
221 | return -ENOMEM; |
222 | } | |
223 | } else | |
224 | iwl_rx_queue_reset(priv, rxq); | |
225 | ||
226 | iwl_rx_replenish(priv); | |
227 | ||
228 | iwl_rx_init(priv, rxq); | |
229 | ||
230 | spin_lock_irqsave(&priv->lock, flags); | |
231 | ||
232 | rxq->need_update = 1; | |
233 | iwl_rx_queue_update_write_ptr(priv, rxq); | |
234 | ||
235 | spin_unlock_irqrestore(&priv->lock, flags); | |
236 | ||
237 | /* Allocate and init all Tx and Command queues */ | |
238 | ret = iwl_txq_ctx_reset(priv); | |
239 | if (ret) | |
240 | return ret; | |
241 | ||
242 | set_bit(STATUS_INIT, &priv->status); | |
243 | ||
244 | return 0; | |
245 | } | |
246 | EXPORT_SYMBOL(iwl_hw_nic_init); | |
247 | ||
14d2aac5 AK |
248 | /* |
249 | * QoS support | |
250 | */ | |
251 | void iwl_activate_qos(struct iwl_priv *priv, u8 force) | |
252 | { | |
253 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
254 | return; | |
255 | ||
256 | priv->qos_data.def_qos_parm.qos_flags = 0; | |
257 | ||
258 | if (priv->qos_data.qos_cap.q_AP.queue_request && | |
259 | !priv->qos_data.qos_cap.q_AP.txop_request) | |
260 | priv->qos_data.def_qos_parm.qos_flags |= | |
261 | QOS_PARAM_FLG_TXOP_TYPE_MSK; | |
262 | if (priv->qos_data.qos_active) | |
263 | priv->qos_data.def_qos_parm.qos_flags |= | |
264 | QOS_PARAM_FLG_UPDATE_EDCA_MSK; | |
265 | ||
266 | if (priv->current_ht_config.is_ht) | |
267 | priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK; | |
268 | ||
269 | if (force || iwl_is_associated(priv)) { | |
270 | IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n", | |
271 | priv->qos_data.qos_active, | |
272 | priv->qos_data.def_qos_parm.qos_flags); | |
273 | ||
274 | iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM, | |
275 | sizeof(struct iwl_qosparam_cmd), | |
276 | &priv->qos_data.def_qos_parm, NULL); | |
277 | } | |
278 | } | |
279 | EXPORT_SYMBOL(iwl_activate_qos); | |
280 | ||
f2c95b04 WYG |
281 | /* |
282 | * AC CWmin CW max AIFSN TXOP Limit TXOP Limit | |
283 | * (802.11b) (802.11a/g) | |
284 | * AC_BK 15 1023 7 0 0 | |
285 | * AC_BE 15 1023 3 0 0 | |
286 | * AC_VI 7 15 2 6.016ms 3.008ms | |
287 | * AC_VO 3 7 2 3.264ms 1.504ms | |
288 | */ | |
c7de35cd | 289 | void iwl_reset_qos(struct iwl_priv *priv) |
bf85ea4f AK |
290 | { |
291 | u16 cw_min = 15; | |
292 | u16 cw_max = 1023; | |
293 | u8 aifs = 2; | |
30dab79e | 294 | bool is_legacy = false; |
bf85ea4f AK |
295 | unsigned long flags; |
296 | int i; | |
297 | ||
298 | spin_lock_irqsave(&priv->lock, flags); | |
30dab79e WT |
299 | /* QoS always active in AP and ADHOC mode |
300 | * In STA mode wait for association | |
301 | */ | |
302 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC || | |
303 | priv->iw_mode == NL80211_IFTYPE_AP) | |
304 | priv->qos_data.qos_active = 1; | |
305 | else | |
306 | priv->qos_data.qos_active = 0; | |
bf85ea4f | 307 | |
30dab79e WT |
308 | /* check for legacy mode */ |
309 | if ((priv->iw_mode == NL80211_IFTYPE_ADHOC && | |
310 | (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) || | |
311 | (priv->iw_mode == NL80211_IFTYPE_STATION && | |
312 | (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) { | |
bf85ea4f AK |
313 | cw_min = 31; |
314 | is_legacy = 1; | |
315 | } | |
316 | ||
317 | if (priv->qos_data.qos_active) | |
318 | aifs = 3; | |
319 | ||
f2c95b04 | 320 | /* AC_BE */ |
bf85ea4f AK |
321 | priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min); |
322 | priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max); | |
323 | priv->qos_data.def_qos_parm.ac[0].aifsn = aifs; | |
324 | priv->qos_data.def_qos_parm.ac[0].edca_txop = 0; | |
325 | priv->qos_data.def_qos_parm.ac[0].reserved1 = 0; | |
326 | ||
327 | if (priv->qos_data.qos_active) { | |
f2c95b04 | 328 | /* AC_BK */ |
bf85ea4f AK |
329 | i = 1; |
330 | priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min); | |
331 | priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max); | |
332 | priv->qos_data.def_qos_parm.ac[i].aifsn = 7; | |
333 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
334 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
335 | ||
f2c95b04 | 336 | /* AC_VI */ |
bf85ea4f AK |
337 | i = 2; |
338 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
339 | cpu_to_le16((cw_min + 1) / 2 - 1); | |
340 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
f2c95b04 | 341 | cpu_to_le16(cw_min); |
bf85ea4f AK |
342 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; |
343 | if (is_legacy) | |
344 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
345 | cpu_to_le16(6016); | |
346 | else | |
347 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
348 | cpu_to_le16(3008); | |
349 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
350 | ||
f2c95b04 | 351 | /* AC_VO */ |
bf85ea4f AK |
352 | i = 3; |
353 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
354 | cpu_to_le16((cw_min + 1) / 4 - 1); | |
355 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
f2c95b04 | 356 | cpu_to_le16((cw_min + 1) / 2 - 1); |
bf85ea4f AK |
357 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; |
358 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
359 | if (is_legacy) | |
360 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
361 | cpu_to_le16(3264); | |
362 | else | |
363 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
364 | cpu_to_le16(1504); | |
365 | } else { | |
366 | for (i = 1; i < 4; i++) { | |
367 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
368 | cpu_to_le16(cw_min); | |
369 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
370 | cpu_to_le16(cw_max); | |
371 | priv->qos_data.def_qos_parm.ac[i].aifsn = aifs; | |
372 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
373 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
374 | } | |
375 | } | |
e1623446 | 376 | IWL_DEBUG_QOS(priv, "set QoS to default \n"); |
bf85ea4f AK |
377 | |
378 | spin_unlock_irqrestore(&priv->lock, flags); | |
379 | } | |
c7de35cd RR |
380 | EXPORT_SYMBOL(iwl_reset_qos); |
381 | ||
d9fe60de JB |
382 | #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */ |
383 | #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */ | |
c7de35cd | 384 | static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv, |
d9fe60de | 385 | struct ieee80211_sta_ht_cap *ht_info, |
c7de35cd RR |
386 | enum ieee80211_band band) |
387 | { | |
39130df3 RR |
388 | u16 max_bit_rate = 0; |
389 | u8 rx_chains_num = priv->hw_params.rx_chains_num; | |
390 | u8 tx_chains_num = priv->hw_params.tx_chains_num; | |
391 | ||
c7de35cd | 392 | ht_info->cap = 0; |
d9fe60de | 393 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); |
c7de35cd | 394 | |
d9fe60de | 395 | ht_info->ht_supported = true; |
c7de35cd | 396 | |
b261793d DH |
397 | if (priv->cfg->ht_greenfield_support) |
398 | ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD; | |
d9fe60de JB |
399 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; |
400 | ht_info->cap |= (IEEE80211_HT_CAP_SM_PS & | |
00c5ae2f | 401 | (WLAN_HT_CAP_SM_PS_DISABLED << 2)); |
39130df3 RR |
402 | |
403 | max_bit_rate = MAX_BIT_RATE_20_MHZ; | |
7aafef1c | 404 | if (priv->hw_params.ht40_channel & BIT(band)) { |
d9fe60de JB |
405 | ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; |
406 | ht_info->cap |= IEEE80211_HT_CAP_SGI_40; | |
407 | ht_info->mcs.rx_mask[4] = 0x01; | |
39130df3 | 408 | max_bit_rate = MAX_BIT_RATE_40_MHZ; |
c7de35cd | 409 | } |
c7de35cd RR |
410 | |
411 | if (priv->cfg->mod_params->amsdu_size_8K) | |
d9fe60de | 412 | ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU; |
c7de35cd RR |
413 | |
414 | ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF; | |
415 | ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF; | |
416 | ||
d9fe60de | 417 | ht_info->mcs.rx_mask[0] = 0xFF; |
39130df3 | 418 | if (rx_chains_num >= 2) |
d9fe60de | 419 | ht_info->mcs.rx_mask[1] = 0xFF; |
39130df3 | 420 | if (rx_chains_num >= 3) |
d9fe60de | 421 | ht_info->mcs.rx_mask[2] = 0xFF; |
39130df3 RR |
422 | |
423 | /* Highest supported Rx data rate */ | |
424 | max_bit_rate *= rx_chains_num; | |
d9fe60de JB |
425 | WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK); |
426 | ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate); | |
39130df3 RR |
427 | |
428 | /* Tx MCS capabilities */ | |
d9fe60de | 429 | ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; |
39130df3 | 430 | if (tx_chains_num != rx_chains_num) { |
d9fe60de JB |
431 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
432 | ht_info->mcs.tx_params |= ((tx_chains_num - 1) << | |
433 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
39130df3 | 434 | } |
c7de35cd | 435 | } |
c7de35cd RR |
436 | |
437 | static void iwlcore_init_hw_rates(struct iwl_priv *priv, | |
438 | struct ieee80211_rate *rates) | |
439 | { | |
440 | int i; | |
441 | ||
442 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
1826dcc0 | 443 | rates[i].bitrate = iwl_rates[i].ieee * 5; |
c7de35cd RR |
444 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ |
445 | rates[i].hw_value_short = i; | |
446 | rates[i].flags = 0; | |
447 | if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { | |
448 | /* | |
449 | * If CCK != 1M then set short preamble rate flag. | |
450 | */ | |
451 | rates[i].flags |= | |
1826dcc0 | 452 | (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ? |
c7de35cd RR |
453 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
454 | } | |
455 | } | |
456 | } | |
457 | ||
8ccde88a | 458 | |
c7de35cd RR |
459 | /** |
460 | * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom | |
461 | */ | |
534166de | 462 | int iwlcore_init_geos(struct iwl_priv *priv) |
c7de35cd RR |
463 | { |
464 | struct iwl_channel_info *ch; | |
465 | struct ieee80211_supported_band *sband; | |
466 | struct ieee80211_channel *channels; | |
467 | struct ieee80211_channel *geo_ch; | |
468 | struct ieee80211_rate *rates; | |
469 | int i = 0; | |
470 | ||
471 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || | |
472 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
e1623446 | 473 | IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n"); |
c7de35cd RR |
474 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
475 | return 0; | |
476 | } | |
477 | ||
478 | channels = kzalloc(sizeof(struct ieee80211_channel) * | |
479 | priv->channel_count, GFP_KERNEL); | |
480 | if (!channels) | |
481 | return -ENOMEM; | |
482 | ||
483 | rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)), | |
484 | GFP_KERNEL); | |
485 | if (!rates) { | |
486 | kfree(channels); | |
487 | return -ENOMEM; | |
488 | } | |
489 | ||
490 | /* 5.2GHz channels start after the 2.4GHz channels */ | |
491 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
492 | sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)]; | |
493 | /* just OFDM */ | |
494 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
495 | sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE; | |
496 | ||
49779293 | 497 | if (priv->cfg->sku & IWL_SKU_N) |
d9fe60de | 498 | iwlcore_init_ht_hw_capab(priv, &sband->ht_cap, |
49779293 | 499 | IEEE80211_BAND_5GHZ); |
c7de35cd RR |
500 | |
501 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
502 | sband->channels = channels; | |
503 | /* OFDM & CCK */ | |
504 | sband->bitrates = rates; | |
505 | sband->n_bitrates = IWL_RATE_COUNT; | |
506 | ||
49779293 | 507 | if (priv->cfg->sku & IWL_SKU_N) |
d9fe60de | 508 | iwlcore_init_ht_hw_capab(priv, &sband->ht_cap, |
49779293 | 509 | IEEE80211_BAND_2GHZ); |
c7de35cd RR |
510 | |
511 | priv->ieee_channels = channels; | |
512 | priv->ieee_rates = rates; | |
513 | ||
c7de35cd RR |
514 | for (i = 0; i < priv->channel_count; i++) { |
515 | ch = &priv->channel_info[i]; | |
516 | ||
517 | /* FIXME: might be removed if scan is OK */ | |
518 | if (!is_channel_valid(ch)) | |
519 | continue; | |
520 | ||
521 | if (is_channel_a_band(ch)) | |
522 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
523 | else | |
524 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
525 | ||
526 | geo_ch = &sband->channels[sband->n_channels++]; | |
527 | ||
528 | geo_ch->center_freq = | |
529 | ieee80211_channel_to_frequency(ch->channel); | |
530 | geo_ch->max_power = ch->max_power_avg; | |
531 | geo_ch->max_antenna_gain = 0xff; | |
532 | geo_ch->hw_value = ch->channel; | |
533 | ||
534 | if (is_channel_valid(ch)) { | |
535 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) | |
536 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
537 | ||
538 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) | |
539 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
540 | ||
541 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
542 | geo_ch->flags |= IEEE80211_CHAN_RADAR; | |
543 | ||
7aafef1c | 544 | geo_ch->flags |= ch->ht40_extension_channel; |
4d38c2e8 | 545 | |
dc1b0973 WYG |
546 | if (ch->max_power_avg > priv->tx_power_device_lmt) |
547 | priv->tx_power_device_lmt = ch->max_power_avg; | |
c7de35cd RR |
548 | } else { |
549 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; | |
550 | } | |
551 | ||
e1623446 | 552 | IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", |
c7de35cd RR |
553 | ch->channel, geo_ch->center_freq, |
554 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
555 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
556 | "restricted" : "valid", | |
557 | geo_ch->flags); | |
558 | } | |
559 | ||
560 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && | |
561 | priv->cfg->sku & IWL_SKU_A) { | |
978785a3 TW |
562 | IWL_INFO(priv, "Incorrectly detected BG card as ABG. " |
563 | "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n", | |
a3139c59 SO |
564 | priv->pci_dev->device, |
565 | priv->pci_dev->subsystem_device); | |
c7de35cd RR |
566 | priv->cfg->sku &= ~IWL_SKU_A; |
567 | } | |
568 | ||
978785a3 | 569 | IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n", |
a3139c59 SO |
570 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
571 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
c7de35cd RR |
572 | |
573 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
574 | ||
575 | return 0; | |
576 | } | |
534166de | 577 | EXPORT_SYMBOL(iwlcore_init_geos); |
c7de35cd RR |
578 | |
579 | /* | |
580 | * iwlcore_free_geos - undo allocations in iwlcore_init_geos | |
581 | */ | |
534166de | 582 | void iwlcore_free_geos(struct iwl_priv *priv) |
c7de35cd RR |
583 | { |
584 | kfree(priv->ieee_channels); | |
585 | kfree(priv->ieee_rates); | |
586 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
587 | } | |
534166de | 588 | EXPORT_SYMBOL(iwlcore_free_geos); |
c7de35cd | 589 | |
28a6b07a | 590 | static bool is_single_rx_stream(struct iwl_priv *priv) |
c7de35cd RR |
591 | { |
592 | return !priv->current_ht_config.is_ht || | |
d9fe60de JB |
593 | ((priv->current_ht_config.mcs.rx_mask[1] == 0) && |
594 | (priv->current_ht_config.mcs.rx_mask[2] == 0)); | |
c7de35cd | 595 | } |
963f5517 | 596 | |
47c5196e TW |
597 | static u8 iwl_is_channel_extension(struct iwl_priv *priv, |
598 | enum ieee80211_band band, | |
599 | u16 channel, u8 extension_chan_offset) | |
600 | { | |
601 | const struct iwl_channel_info *ch_info; | |
602 | ||
603 | ch_info = iwl_get_channel_info(priv, band, channel); | |
604 | if (!is_channel_valid(ch_info)) | |
605 | return 0; | |
606 | ||
d9fe60de | 607 | if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) |
7aafef1c | 608 | return !(ch_info->ht40_extension_channel & |
689da1b3 | 609 | IEEE80211_CHAN_NO_HT40PLUS); |
d9fe60de | 610 | else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) |
7aafef1c | 611 | return !(ch_info->ht40_extension_channel & |
689da1b3 | 612 | IEEE80211_CHAN_NO_HT40MINUS); |
47c5196e TW |
613 | |
614 | return 0; | |
615 | } | |
616 | ||
7aafef1c | 617 | u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv, |
d9fe60de | 618 | struct ieee80211_sta_ht_cap *sta_ht_inf) |
47c5196e TW |
619 | { |
620 | struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config; | |
621 | ||
622 | if ((!iwl_ht_conf->is_ht) || | |
a2b0f02e | 623 | (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ)) |
47c5196e TW |
624 | return 0; |
625 | ||
a2b0f02e WYG |
626 | /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
627 | * the bit will not set if it is pure 40MHz case | |
628 | */ | |
47c5196e | 629 | if (sta_ht_inf) { |
a2b0f02e | 630 | if (!sta_ht_inf->ht_supported) |
47c5196e TW |
631 | return 0; |
632 | } | |
1e4247d4 WYG |
633 | #ifdef CONFIG_IWLWIFI_DEBUG |
634 | if (priv->disable_ht40) | |
635 | return 0; | |
636 | #endif | |
611d3eb7 WYG |
637 | return iwl_is_channel_extension(priv, priv->band, |
638 | le16_to_cpu(priv->staging_rxon.channel), | |
639 | iwl_ht_conf->extension_chan_offset); | |
47c5196e | 640 | } |
7aafef1c | 641 | EXPORT_SYMBOL(iwl_is_ht40_tx_allowed); |
47c5196e | 642 | |
2c2f3b33 TW |
643 | static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val) |
644 | { | |
645 | u16 new_val = 0; | |
646 | u16 beacon_factor = 0; | |
647 | ||
648 | beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val; | |
649 | new_val = beacon_val / beacon_factor; | |
650 | ||
651 | if (!new_val) | |
652 | new_val = max_beacon_val; | |
653 | ||
654 | return new_val; | |
655 | } | |
656 | ||
657 | void iwl_setup_rxon_timing(struct iwl_priv *priv) | |
658 | { | |
659 | u64 tsf; | |
660 | s32 interval_tm, rem; | |
661 | unsigned long flags; | |
662 | struct ieee80211_conf *conf = NULL; | |
663 | u16 beacon_int; | |
664 | ||
665 | conf = ieee80211_get_hw_conf(priv->hw); | |
666 | ||
667 | spin_lock_irqsave(&priv->lock, flags); | |
668 | priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp); | |
669 | priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval); | |
670 | ||
671 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { | |
672 | beacon_int = priv->beacon_int; | |
673 | priv->rxon_timing.atim_window = 0; | |
674 | } else { | |
675 | beacon_int = priv->vif->bss_conf.beacon_int; | |
676 | ||
677 | /* TODO: we need to get atim_window from upper stack | |
678 | * for now we set to 0 */ | |
679 | priv->rxon_timing.atim_window = 0; | |
680 | } | |
681 | ||
682 | beacon_int = iwl_adjust_beacon_interval(beacon_int, | |
683 | priv->hw_params.max_beacon_itrvl * 1024); | |
684 | priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int); | |
685 | ||
686 | tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */ | |
687 | interval_tm = beacon_int * 1024; | |
688 | rem = do_div(tsf, interval_tm); | |
689 | priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem); | |
690 | ||
691 | spin_unlock_irqrestore(&priv->lock, flags); | |
692 | IWL_DEBUG_ASSOC(priv, | |
693 | "beacon interval %d beacon timer %d beacon tim %d\n", | |
694 | le16_to_cpu(priv->rxon_timing.beacon_interval), | |
695 | le32_to_cpu(priv->rxon_timing.beacon_init_val), | |
696 | le16_to_cpu(priv->rxon_timing.atim_window)); | |
697 | } | |
698 | EXPORT_SYMBOL(iwl_setup_rxon_timing); | |
699 | ||
8ccde88a SO |
700 | void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt) |
701 | { | |
702 | struct iwl_rxon_cmd *rxon = &priv->staging_rxon; | |
703 | ||
704 | if (hw_decrypt) | |
705 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
706 | else | |
707 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
708 | ||
709 | } | |
710 | EXPORT_SYMBOL(iwl_set_rxon_hwcrypto); | |
711 | ||
712 | /** | |
713 | * iwl_check_rxon_cmd - validate RXON structure is valid | |
714 | * | |
715 | * NOTE: This is really only useful during development and can eventually | |
716 | * be #ifdef'd out once the driver is stable and folks aren't actively | |
717 | * making changes | |
718 | */ | |
719 | int iwl_check_rxon_cmd(struct iwl_priv *priv) | |
720 | { | |
721 | int error = 0; | |
722 | int counter = 1; | |
723 | struct iwl_rxon_cmd *rxon = &priv->staging_rxon; | |
724 | ||
725 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
726 | error |= le32_to_cpu(rxon->flags & | |
727 | (RXON_FLG_TGJ_NARROW_BAND_MSK | | |
728 | RXON_FLG_RADAR_DETECT_MSK)); | |
729 | if (error) | |
730 | IWL_WARN(priv, "check 24G fields %d | %d\n", | |
731 | counter++, error); | |
732 | } else { | |
733 | error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ? | |
734 | 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK); | |
735 | if (error) | |
736 | IWL_WARN(priv, "check 52 fields %d | %d\n", | |
737 | counter++, error); | |
738 | error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK); | |
739 | if (error) | |
740 | IWL_WARN(priv, "check 52 CCK %d | %d\n", | |
741 | counter++, error); | |
742 | } | |
743 | error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1; | |
744 | if (error) | |
745 | IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error); | |
746 | ||
747 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
748 | error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) && | |
749 | ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0)); | |
750 | if (error) | |
751 | IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error); | |
752 | ||
753 | error |= (le16_to_cpu(rxon->assoc_id) > 2007); | |
754 | if (error) | |
755 | IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error); | |
756 | ||
757 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) | |
758 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)); | |
759 | if (error) | |
760 | IWL_WARN(priv, "check CCK and short slot %d | %d\n", | |
761 | counter++, error); | |
762 | ||
763 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) | |
764 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)); | |
765 | if (error) | |
766 | IWL_WARN(priv, "check CCK & auto detect %d | %d\n", | |
767 | counter++, error); | |
768 | ||
769 | error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | | |
770 | RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK); | |
771 | if (error) | |
772 | IWL_WARN(priv, "check TGG and auto detect %d | %d\n", | |
773 | counter++, error); | |
774 | ||
775 | if (error) | |
776 | IWL_WARN(priv, "Tuning to channel %d\n", | |
777 | le16_to_cpu(rxon->channel)); | |
778 | ||
779 | if (error) { | |
780 | IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n"); | |
781 | return -1; | |
782 | } | |
783 | return 0; | |
784 | } | |
785 | EXPORT_SYMBOL(iwl_check_rxon_cmd); | |
786 | ||
787 | /** | |
788 | * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed | |
789 | * @priv: staging_rxon is compared to active_rxon | |
790 | * | |
791 | * If the RXON structure is changing enough to require a new tune, | |
792 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
793 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
794 | */ | |
795 | int iwl_full_rxon_required(struct iwl_priv *priv) | |
796 | { | |
797 | ||
798 | /* These items are only settable from the full RXON command */ | |
799 | if (!(iwl_is_associated(priv)) || | |
800 | compare_ether_addr(priv->staging_rxon.bssid_addr, | |
801 | priv->active_rxon.bssid_addr) || | |
802 | compare_ether_addr(priv->staging_rxon.node_addr, | |
803 | priv->active_rxon.node_addr) || | |
804 | compare_ether_addr(priv->staging_rxon.wlap_bssid_addr, | |
805 | priv->active_rxon.wlap_bssid_addr) || | |
806 | (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) || | |
807 | (priv->staging_rxon.channel != priv->active_rxon.channel) || | |
808 | (priv->staging_rxon.air_propagation != | |
809 | priv->active_rxon.air_propagation) || | |
810 | (priv->staging_rxon.ofdm_ht_single_stream_basic_rates != | |
811 | priv->active_rxon.ofdm_ht_single_stream_basic_rates) || | |
812 | (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates != | |
813 | priv->active_rxon.ofdm_ht_dual_stream_basic_rates) || | |
c2105fa7 DH |
814 | (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates != |
815 | priv->active_rxon.ofdm_ht_triple_stream_basic_rates) || | |
8ccde88a SO |
816 | (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id)) |
817 | return 1; | |
818 | ||
819 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
820 | * be updated with the RXON_ASSOC command -- however only some | |
821 | * flag transitions are allowed using RXON_ASSOC */ | |
822 | ||
823 | /* Check if we are not switching bands */ | |
824 | if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) != | |
825 | (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)) | |
826 | return 1; | |
827 | ||
828 | /* Check if we are switching association toggle */ | |
829 | if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) != | |
830 | (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) | |
831 | return 1; | |
832 | ||
833 | return 0; | |
834 | } | |
835 | EXPORT_SYMBOL(iwl_full_rxon_required); | |
836 | ||
837 | u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv) | |
838 | { | |
839 | int i; | |
840 | int rate_mask; | |
841 | ||
842 | /* Set rate mask*/ | |
843 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) | |
844 | rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK; | |
845 | else | |
846 | rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK; | |
847 | ||
848 | /* Find lowest valid rate */ | |
849 | for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID; | |
850 | i = iwl_rates[i].next_ieee) { | |
851 | if (rate_mask & (1 << i)) | |
852 | return iwl_rates[i].plcp; | |
853 | } | |
854 | ||
855 | /* No valid rate was found. Assign the lowest one */ | |
856 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) | |
857 | return IWL_RATE_1M_PLCP; | |
858 | else | |
859 | return IWL_RATE_6M_PLCP; | |
860 | } | |
861 | EXPORT_SYMBOL(iwl_rate_get_lowest_plcp); | |
862 | ||
47c5196e TW |
863 | void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info) |
864 | { | |
c1adf9fb | 865 | struct iwl_rxon_cmd *rxon = &priv->staging_rxon; |
47c5196e | 866 | |
42eb7c64 | 867 | if (!ht_info->is_ht) { |
a2b0f02e | 868 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | |
42eb7c64 | 869 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | |
7aafef1c | 870 | RXON_FLG_HT40_PROT_MSK | |
42eb7c64 | 871 | RXON_FLG_HT_PROT_MSK); |
47c5196e | 872 | return; |
42eb7c64 | 873 | } |
47c5196e | 874 | |
a2b0f02e WYG |
875 | /* FIXME: if the definition of ht_protection changed, the "translation" |
876 | * will be needed for rxon->flags | |
877 | */ | |
878 | rxon->flags |= cpu_to_le32(ht_info->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS); | |
879 | ||
880 | /* Set up channel bandwidth: | |
7aafef1c | 881 | * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */ |
a2b0f02e WYG |
882 | /* clear the HT channel mode before set the mode */ |
883 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | | |
884 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
7aafef1c WYG |
885 | if (iwl_is_ht40_tx_allowed(priv, NULL)) { |
886 | /* pure ht40 */ | |
508b08e7 | 887 | if (ht_info->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) { |
a2b0f02e | 888 | rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40; |
508b08e7 WYG |
889 | /* Note: control channel is opposite of extension channel */ |
890 | switch (ht_info->extension_chan_offset) { | |
891 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: | |
892 | rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
893 | break; | |
894 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
895 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
896 | break; | |
897 | } | |
898 | } else { | |
a2b0f02e WYG |
899 | /* Note: control channel is opposite of extension channel */ |
900 | switch (ht_info->extension_chan_offset) { | |
901 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: | |
902 | rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
903 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
904 | break; | |
905 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
906 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
907 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
908 | break; | |
909 | case IEEE80211_HT_PARAM_CHA_SEC_NONE: | |
910 | default: | |
911 | /* channel location only valid if in Mixed mode */ | |
912 | IWL_ERR(priv, "invalid extension channel offset\n"); | |
913 | break; | |
914 | } | |
915 | } | |
916 | } else { | |
917 | rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY; | |
47c5196e TW |
918 | } |
919 | ||
45823531 AK |
920 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
921 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
47c5196e | 922 | |
e1623446 | 923 | IWL_DEBUG_ASSOC(priv, "supported HT rate 0x%X 0x%X 0x%X " |
47c5196e | 924 | "rxon flags 0x%X operation mode :0x%X " |
ae5eb026 | 925 | "extension channel offset 0x%x\n", |
d9fe60de JB |
926 | ht_info->mcs.rx_mask[0], |
927 | ht_info->mcs.rx_mask[1], | |
928 | ht_info->mcs.rx_mask[2], | |
47c5196e | 929 | le32_to_cpu(rxon->flags), ht_info->ht_protection, |
ae5eb026 | 930 | ht_info->extension_chan_offset); |
47c5196e TW |
931 | return; |
932 | } | |
933 | EXPORT_SYMBOL(iwl_set_rxon_ht); | |
934 | ||
9e5e6c32 TW |
935 | #define IWL_NUM_RX_CHAINS_MULTIPLE 3 |
936 | #define IWL_NUM_RX_CHAINS_SINGLE 2 | |
937 | #define IWL_NUM_IDLE_CHAINS_DUAL 2 | |
938 | #define IWL_NUM_IDLE_CHAINS_SINGLE 1 | |
939 | ||
940 | /* Determine how many receiver/antenna chains to use. | |
c7de35cd RR |
941 | * More provides better reception via diversity. Fewer saves power. |
942 | * MIMO (dual stream) requires at least 2, but works better with 3. | |
943 | * This does not determine *which* chains to use, just how many. | |
944 | */ | |
28a6b07a | 945 | static int iwl_get_active_rx_chain_count(struct iwl_priv *priv) |
c7de35cd | 946 | { |
28a6b07a TW |
947 | bool is_single = is_single_rx_stream(priv); |
948 | bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status); | |
c7de35cd RR |
949 | |
950 | /* # of Rx chains to use when expecting MIMO. */ | |
12837be1 RR |
951 | if (is_single || (!is_cam && (priv->current_ht_config.sm_ps == |
952 | WLAN_HT_CAP_SM_PS_STATIC))) | |
9e5e6c32 | 953 | return IWL_NUM_RX_CHAINS_SINGLE; |
c7de35cd | 954 | else |
9e5e6c32 | 955 | return IWL_NUM_RX_CHAINS_MULTIPLE; |
28a6b07a | 956 | } |
c7de35cd | 957 | |
28a6b07a TW |
958 | static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt) |
959 | { | |
960 | int idle_cnt; | |
961 | bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status); | |
c7de35cd | 962 | /* # Rx chains when idling and maybe trying to save power */ |
12837be1 | 963 | switch (priv->current_ht_config.sm_ps) { |
00c5ae2f TW |
964 | case WLAN_HT_CAP_SM_PS_STATIC: |
965 | case WLAN_HT_CAP_SM_PS_DYNAMIC: | |
9e5e6c32 TW |
966 | idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL : |
967 | IWL_NUM_IDLE_CHAINS_SINGLE; | |
c7de35cd | 968 | break; |
00c5ae2f | 969 | case WLAN_HT_CAP_SM_PS_DISABLED: |
9e5e6c32 | 970 | idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE; |
c7de35cd | 971 | break; |
00c5ae2f | 972 | case WLAN_HT_CAP_SM_PS_INVALID: |
c7de35cd | 973 | default: |
15b1687c | 974 | IWL_ERR(priv, "invalid mimo ps mode %d\n", |
12837be1 | 975 | priv->current_ht_config.sm_ps); |
28a6b07a TW |
976 | WARN_ON(1); |
977 | idle_cnt = -1; | |
c7de35cd RR |
978 | break; |
979 | } | |
28a6b07a | 980 | return idle_cnt; |
c7de35cd RR |
981 | } |
982 | ||
04816448 GE |
983 | /* up to 4 chains */ |
984 | static u8 iwl_count_chain_bitmap(u32 chain_bitmap) | |
985 | { | |
986 | u8 res; | |
987 | res = (chain_bitmap & BIT(0)) >> 0; | |
988 | res += (chain_bitmap & BIT(1)) >> 1; | |
989 | res += (chain_bitmap & BIT(2)) >> 2; | |
990 | res += (chain_bitmap & BIT(4)) >> 4; | |
991 | return res; | |
992 | } | |
993 | ||
4c4df78f CR |
994 | /** |
995 | * iwl_is_monitor_mode - Determine if interface in monitor mode | |
996 | * | |
997 | * priv->iw_mode is set in add_interface, but add_interface is | |
998 | * never called for monitor mode. The only way mac80211 informs us about | |
999 | * monitor mode is through configuring filters (call to configure_filter). | |
1000 | */ | |
279b05d4 | 1001 | bool iwl_is_monitor_mode(struct iwl_priv *priv) |
4c4df78f CR |
1002 | { |
1003 | return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK); | |
1004 | } | |
279b05d4 | 1005 | EXPORT_SYMBOL(iwl_is_monitor_mode); |
4c4df78f | 1006 | |
c7de35cd RR |
1007 | /** |
1008 | * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image | |
1009 | * | |
1010 | * Selects how many and which Rx receivers/antennas/chains to use. | |
1011 | * This should not be used for scan command ... it puts data in wrong place. | |
1012 | */ | |
1013 | void iwl_set_rxon_chain(struct iwl_priv *priv) | |
1014 | { | |
28a6b07a TW |
1015 | bool is_single = is_single_rx_stream(priv); |
1016 | bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status); | |
04816448 GE |
1017 | u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt; |
1018 | u32 active_chains; | |
28a6b07a | 1019 | u16 rx_chain; |
c7de35cd RR |
1020 | |
1021 | /* Tell uCode which antennas are actually connected. | |
1022 | * Before first association, we assume all antennas are connected. | |
1023 | * Just after first association, iwl_chain_noise_calibration() | |
1024 | * checks which antennas actually *are* connected. */ | |
04816448 GE |
1025 | if (priv->chain_noise_data.active_chains) |
1026 | active_chains = priv->chain_noise_data.active_chains; | |
1027 | else | |
1028 | active_chains = priv->hw_params.valid_rx_ant; | |
1029 | ||
1030 | rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS; | |
c7de35cd RR |
1031 | |
1032 | /* How many receivers should we use? */ | |
28a6b07a TW |
1033 | active_rx_cnt = iwl_get_active_rx_chain_count(priv); |
1034 | idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt); | |
1035 | ||
28a6b07a | 1036 | |
04816448 GE |
1037 | /* correct rx chain count according hw settings |
1038 | * and chain noise calibration | |
1039 | */ | |
1040 | valid_rx_cnt = iwl_count_chain_bitmap(active_chains); | |
1041 | if (valid_rx_cnt < active_rx_cnt) | |
1042 | active_rx_cnt = valid_rx_cnt; | |
1043 | ||
1044 | if (valid_rx_cnt < idle_rx_cnt) | |
1045 | idle_rx_cnt = valid_rx_cnt; | |
28a6b07a TW |
1046 | |
1047 | rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS; | |
1048 | rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS; | |
1049 | ||
7b841727 RF |
1050 | /* copied from 'iwl_bg_request_scan()' */ |
1051 | /* Force use of chains B and C (0x6) for Rx for 4965 | |
1052 | * Avoid A (0x1) because of its off-channel reception on A-band. | |
1053 | * MIMO is not used here, but value is required */ | |
1054 | if (iwl_is_monitor_mode(priv) && | |
1055 | !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) && | |
1056 | ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) { | |
fff7a434 WYG |
1057 | rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS; |
1058 | rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS; | |
1059 | rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS; | |
1060 | rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS; | |
7b841727 RF |
1061 | } |
1062 | ||
28a6b07a TW |
1063 | priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain); |
1064 | ||
9e5e6c32 | 1065 | if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam) |
c7de35cd RR |
1066 | priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK; |
1067 | else | |
1068 | priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK; | |
1069 | ||
e1623446 | 1070 | IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n", |
28a6b07a TW |
1071 | priv->staging_rxon.rx_chain, |
1072 | active_rx_cnt, idle_rx_cnt); | |
1073 | ||
1074 | WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 || | |
1075 | active_rx_cnt < idle_rx_cnt); | |
c7de35cd RR |
1076 | } |
1077 | EXPORT_SYMBOL(iwl_set_rxon_chain); | |
bf85ea4f AK |
1078 | |
1079 | /** | |
17e72782 | 1080 | * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON |
bf85ea4f AK |
1081 | * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz |
1082 | * @channel: Any channel valid for the requested phymode | |
1083 | ||
1084 | * In addition to setting the staging RXON, priv->phymode is also set. | |
1085 | * | |
1086 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields | |
1087 | * in the staging RXON flag structure based on the phymode | |
1088 | */ | |
17e72782 | 1089 | int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch) |
bf85ea4f | 1090 | { |
17e72782 TW |
1091 | enum ieee80211_band band = ch->band; |
1092 | u16 channel = ieee80211_frequency_to_channel(ch->center_freq); | |
1093 | ||
8622e705 | 1094 | if (!iwl_get_channel_info(priv, band, channel)) { |
e1623446 | 1095 | IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n", |
bf85ea4f AK |
1096 | channel, band); |
1097 | return -EINVAL; | |
1098 | } | |
1099 | ||
1100 | if ((le16_to_cpu(priv->staging_rxon.channel) == channel) && | |
1101 | (priv->band == band)) | |
1102 | return 0; | |
1103 | ||
1104 | priv->staging_rxon.channel = cpu_to_le16(channel); | |
1105 | if (band == IEEE80211_BAND_5GHZ) | |
1106 | priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK; | |
1107 | else | |
1108 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
1109 | ||
1110 | priv->band = band; | |
1111 | ||
e1623446 | 1112 | IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band); |
bf85ea4f AK |
1113 | |
1114 | return 0; | |
1115 | } | |
c7de35cd | 1116 | EXPORT_SYMBOL(iwl_set_rxon_channel); |
bf85ea4f | 1117 | |
8ccde88a SO |
1118 | void iwl_set_flags_for_band(struct iwl_priv *priv, |
1119 | enum ieee80211_band band) | |
1120 | { | |
1121 | if (band == IEEE80211_BAND_5GHZ) { | |
1122 | priv->staging_rxon.flags &= | |
1123 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK | |
1124 | | RXON_FLG_CCK_MSK); | |
1125 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
1126 | } else { | |
1127 | /* Copied from iwl_post_associate() */ | |
1128 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
1129 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
1130 | else | |
1131 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
1132 | ||
1133 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) | |
1134 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
1135 | ||
1136 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
1137 | priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
1138 | priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK; | |
1139 | } | |
1140 | } | |
8ccde88a SO |
1141 | |
1142 | /* | |
1143 | * initialize rxon structure with default values from eeprom | |
1144 | */ | |
1145 | void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode) | |
1146 | { | |
1147 | const struct iwl_channel_info *ch_info; | |
1148 | ||
1149 | memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon)); | |
1150 | ||
1151 | switch (mode) { | |
1152 | case NL80211_IFTYPE_AP: | |
1153 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP; | |
1154 | break; | |
1155 | ||
1156 | case NL80211_IFTYPE_STATION: | |
1157 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS; | |
1158 | priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; | |
1159 | break; | |
1160 | ||
1161 | case NL80211_IFTYPE_ADHOC: | |
1162 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS; | |
1163 | priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK; | |
1164 | priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
1165 | RXON_FILTER_ACCEPT_GRP_MSK; | |
1166 | break; | |
1167 | ||
8ccde88a SO |
1168 | default: |
1169 | IWL_ERR(priv, "Unsupported interface type %d\n", mode); | |
1170 | break; | |
1171 | } | |
1172 | ||
1173 | #if 0 | |
1174 | /* TODO: Figure out when short_preamble would be set and cache from | |
1175 | * that */ | |
1176 | if (!hw_to_local(priv->hw)->short_preamble) | |
1177 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
1178 | else | |
1179 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
1180 | #endif | |
1181 | ||
1182 | ch_info = iwl_get_channel_info(priv, priv->band, | |
1183 | le16_to_cpu(priv->active_rxon.channel)); | |
1184 | ||
1185 | if (!ch_info) | |
1186 | ch_info = &priv->channel_info[0]; | |
1187 | ||
1188 | /* | |
1189 | * in some case A channels are all non IBSS | |
1190 | * in this case force B/G channel | |
1191 | */ | |
1192 | if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) && | |
1193 | !(is_channel_ibss(ch_info))) | |
1194 | ch_info = &priv->channel_info[0]; | |
1195 | ||
1196 | priv->staging_rxon.channel = cpu_to_le16(ch_info->channel); | |
1197 | priv->band = ch_info->band; | |
1198 | ||
1199 | iwl_set_flags_for_band(priv, priv->band); | |
1200 | ||
1201 | priv->staging_rxon.ofdm_basic_rates = | |
1202 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
1203 | priv->staging_rxon.cck_basic_rates = | |
1204 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
1205 | ||
a2b0f02e WYG |
1206 | /* clear both MIX and PURE40 mode flag */ |
1207 | priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED | | |
1208 | RXON_FLG_CHANNEL_MODE_PURE_40); | |
8ccde88a SO |
1209 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
1210 | memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN); | |
1211 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff; | |
1212 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff; | |
11397a65 | 1213 | priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff; |
8ccde88a SO |
1214 | } |
1215 | EXPORT_SYMBOL(iwl_connection_init_rx_config); | |
1216 | ||
782571f4 | 1217 | static void iwl_set_rate(struct iwl_priv *priv) |
8ccde88a SO |
1218 | { |
1219 | const struct ieee80211_supported_band *hw = NULL; | |
1220 | struct ieee80211_rate *rate; | |
1221 | int i; | |
1222 | ||
1223 | hw = iwl_get_hw_mode(priv, priv->band); | |
1224 | if (!hw) { | |
1225 | IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n"); | |
1226 | return; | |
1227 | } | |
1228 | ||
1229 | priv->active_rate = 0; | |
1230 | priv->active_rate_basic = 0; | |
1231 | ||
1232 | for (i = 0; i < hw->n_bitrates; i++) { | |
1233 | rate = &(hw->bitrates[i]); | |
1234 | if (rate->hw_value < IWL_RATE_COUNT) | |
1235 | priv->active_rate |= (1 << rate->hw_value); | |
1236 | } | |
1237 | ||
e1623446 | 1238 | IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n", |
8ccde88a SO |
1239 | priv->active_rate, priv->active_rate_basic); |
1240 | ||
1241 | /* | |
1242 | * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK) | |
1243 | * otherwise set it to the default of all CCK rates and 6, 12, 24 for | |
1244 | * OFDM | |
1245 | */ | |
1246 | if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK) | |
1247 | priv->staging_rxon.cck_basic_rates = | |
1248 | ((priv->active_rate_basic & | |
1249 | IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF; | |
1250 | else | |
1251 | priv->staging_rxon.cck_basic_rates = | |
1252 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
1253 | ||
1254 | if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK) | |
1255 | priv->staging_rxon.ofdm_basic_rates = | |
1256 | ((priv->active_rate_basic & | |
1257 | (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >> | |
1258 | IWL_FIRST_OFDM_RATE) & 0xFF; | |
1259 | else | |
1260 | priv->staging_rxon.ofdm_basic_rates = | |
1261 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
1262 | } | |
8ccde88a SO |
1263 | |
1264 | void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
1265 | { | |
1266 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1267 | struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon; | |
1268 | struct iwl_csa_notification *csa = &(pkt->u.csa_notif); | |
e1623446 | 1269 | IWL_DEBUG_11H(priv, "CSA notif: channel %d, status %d\n", |
8ccde88a SO |
1270 | le16_to_cpu(csa->channel), le32_to_cpu(csa->status)); |
1271 | rxon->channel = csa->channel; | |
1272 | priv->staging_rxon.channel = csa->channel; | |
1273 | } | |
1274 | EXPORT_SYMBOL(iwl_rx_csa); | |
1275 | ||
1276 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1277 | static void iwl_print_rx_config_cmd(struct iwl_priv *priv) | |
1278 | { | |
1279 | struct iwl_rxon_cmd *rxon = &priv->staging_rxon; | |
1280 | ||
e1623446 | 1281 | IWL_DEBUG_RADIO(priv, "RX CONFIG:\n"); |
3d816c77 | 1282 | iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
e1623446 TW |
1283 | IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
1284 | IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
1285 | IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n", | |
8ccde88a | 1286 | le32_to_cpu(rxon->filter_flags)); |
e1623446 TW |
1287 | IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type); |
1288 | IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n", | |
8ccde88a | 1289 | rxon->ofdm_basic_rates); |
e1623446 TW |
1290 | IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); |
1291 | IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr); | |
1292 | IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr); | |
1293 | IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); | |
8ccde88a | 1294 | } |
8ccde88a | 1295 | |
a94ca4e7 JB |
1296 | static const char *desc_lookup_text[] = { |
1297 | "OK", | |
1298 | "FAIL", | |
1299 | "BAD_PARAM", | |
1300 | "BAD_CHECKSUM", | |
1301 | "NMI_INTERRUPT_WDG", | |
1302 | "SYSASSERT", | |
1303 | "FATAL_ERROR", | |
1304 | "BAD_COMMAND", | |
1305 | "HW_ERROR_TUNE_LOCK", | |
1306 | "HW_ERROR_TEMPERATURE", | |
1307 | "ILLEGAL_CHAN_FREQ", | |
1308 | "VCC_NOT_STABLE", | |
1309 | "FH_ERROR", | |
1310 | "NMI_INTERRUPT_HOST", | |
1311 | "NMI_INTERRUPT_ACTION_PT", | |
1312 | "NMI_INTERRUPT_UNKNOWN", | |
1313 | "UCODE_VERSION_MISMATCH", | |
1314 | "HW_ERROR_ABS_LOCK", | |
1315 | "HW_ERROR_CAL_LOCK_FAIL", | |
1316 | "NMI_INTERRUPT_INST_ACTION_PT", | |
1317 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
1318 | "NMI_TRM_HW_ER", | |
1319 | "NMI_INTERRUPT_TRM", | |
1320 | "NMI_INTERRUPT_BREAK_POINT" | |
1321 | "DEBUG_0", | |
1322 | "DEBUG_1", | |
1323 | "DEBUG_2", | |
1324 | "DEBUG_3", | |
1325 | "UNKNOWN" | |
1326 | }; | |
1327 | ||
1328 | static const char *desc_lookup(int i) | |
1329 | { | |
1330 | int max = ARRAY_SIZE(desc_lookup_text) - 1; | |
1331 | ||
1332 | if (i < 0 || i > max) | |
1333 | i = max; | |
1334 | ||
1335 | return desc_lookup_text[i]; | |
1336 | } | |
1337 | ||
1338 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1339 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1340 | ||
1341 | static void iwl_dump_nic_error_log(struct iwl_priv *priv) | |
1342 | { | |
1343 | u32 data2, line; | |
1344 | u32 desc, time, count, base, data1; | |
1345 | u32 blink1, blink2, ilink1, ilink2; | |
1346 | ||
c03ea162 | 1347 | if (priv->ucode_type == UCODE_INIT) |
34a66de6 | 1348 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); |
c03ea162 RC |
1349 | else |
1350 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
a94ca4e7 JB |
1351 | |
1352 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
1353 | IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base); | |
1354 | return; | |
1355 | } | |
1356 | ||
1357 | count = iwl_read_targ_mem(priv, base); | |
1358 | ||
1359 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
1360 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); | |
1361 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
1362 | priv->status, count); | |
1363 | } | |
1364 | ||
1365 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); | |
1366 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); | |
1367 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
1368 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
1369 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
1370 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
1371 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
1372 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
1373 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
1374 | ||
1375 | IWL_ERR(priv, "Desc Time " | |
1376 | "data1 data2 line\n"); | |
1377 | IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n", | |
1378 | desc_lookup(desc), desc, time, data1, data2, line); | |
1379 | IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n"); | |
1380 | IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, | |
1381 | ilink1, ilink2); | |
1382 | ||
1383 | } | |
1384 | ||
1385 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
1386 | ||
1387 | /** | |
1388 | * iwl_print_event_log - Dump error event log to syslog | |
1389 | * | |
1390 | */ | |
1391 | static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, | |
1392 | u32 num_events, u32 mode) | |
1393 | { | |
1394 | u32 i; | |
1395 | u32 base; /* SRAM byte address of event log header */ | |
1396 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1397 | u32 ptr; /* SRAM byte address of log data */ | |
1398 | u32 ev, time, data; /* event log data */ | |
1399 | ||
1400 | if (num_events == 0) | |
1401 | return; | |
c03ea162 | 1402 | if (priv->ucode_type == UCODE_INIT) |
34a66de6 | 1403 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); |
c03ea162 RC |
1404 | else |
1405 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
a94ca4e7 JB |
1406 | |
1407 | if (mode == 0) | |
1408 | event_size = 2 * sizeof(u32); | |
1409 | else | |
1410 | event_size = 3 * sizeof(u32); | |
1411 | ||
1412 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1413 | ||
1414 | /* "time" is actually "data" for mode 0 (no timestamp). | |
1415 | * place event id # at far right for easier visual parsing. */ | |
1416 | for (i = 0; i < num_events; i++) { | |
1417 | ev = iwl_read_targ_mem(priv, ptr); | |
1418 | ptr += sizeof(u32); | |
1419 | time = iwl_read_targ_mem(priv, ptr); | |
1420 | ptr += sizeof(u32); | |
1421 | if (mode == 0) { | |
1422 | /* data, ev */ | |
1423 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev); | |
1424 | } else { | |
1425 | data = iwl_read_targ_mem(priv, ptr); | |
1426 | ptr += sizeof(u32); | |
1427 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", | |
1428 | time, data, ev); | |
1429 | } | |
1430 | } | |
1431 | } | |
1432 | ||
1433 | void iwl_dump_nic_event_log(struct iwl_priv *priv) | |
1434 | { | |
1435 | u32 base; /* SRAM byte address of event log header */ | |
1436 | u32 capacity; /* event log capacity in # entries */ | |
1437 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
1438 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
1439 | u32 next_entry; /* index of next entry to be written by uCode */ | |
1440 | u32 size; /* # entries that we'll print */ | |
1441 | ||
c03ea162 | 1442 | if (priv->ucode_type == UCODE_INIT) |
34a66de6 | 1443 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); |
c03ea162 RC |
1444 | else |
1445 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
a94ca4e7 JB |
1446 | |
1447 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
1448 | IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); | |
1449 | return; | |
1450 | } | |
1451 | ||
1452 | /* event log header */ | |
1453 | capacity = iwl_read_targ_mem(priv, base); | |
1454 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
1455 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
1456 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
1457 | ||
1458 | size = num_wraps ? capacity : next_entry; | |
1459 | ||
1460 | /* bail out if nothing in log */ | |
1461 | if (size == 0) { | |
1462 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); | |
1463 | return; | |
1464 | } | |
1465 | ||
1466 | IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n", | |
1467 | size, num_wraps); | |
1468 | ||
1469 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
1470 | * i.e the next one that uCode would fill. */ | |
1471 | if (num_wraps) | |
1472 | iwl_print_event_log(priv, next_entry, | |
1473 | capacity - next_entry, mode); | |
1474 | /* (then/else) start at top of log */ | |
1475 | iwl_print_event_log(priv, 0, next_entry, mode); | |
1476 | ||
1477 | } | |
6686d17e | 1478 | #endif |
8ccde88a SO |
1479 | /** |
1480 | * iwl_irq_handle_error - called for HW or SW error interrupt from card | |
1481 | */ | |
1482 | void iwl_irq_handle_error(struct iwl_priv *priv) | |
1483 | { | |
1484 | /* Set the FW error flag -- cleared on iwl_down */ | |
1485 | set_bit(STATUS_FW_ERROR, &priv->status); | |
1486 | ||
1487 | /* Cancel currently queued command. */ | |
1488 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
1489 | ||
1490 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1491 | if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) { |
8ccde88a SO |
1492 | iwl_dump_nic_error_log(priv); |
1493 | iwl_dump_nic_event_log(priv); | |
1494 | iwl_print_rx_config_cmd(priv); | |
1495 | } | |
1496 | #endif | |
1497 | ||
1498 | wake_up_interruptible(&priv->wait_command_queue); | |
1499 | ||
1500 | /* Keep the restart process from trying to send host | |
1501 | * commands by clearing the INIT status bit */ | |
1502 | clear_bit(STATUS_READY, &priv->status); | |
1503 | ||
1504 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
e1623446 | 1505 | IWL_DEBUG(priv, IWL_DL_FW_ERRORS, |
8ccde88a SO |
1506 | "Restarting adapter due to uCode error.\n"); |
1507 | ||
8ccde88a SO |
1508 | if (priv->cfg->mod_params->restart_fw) |
1509 | queue_work(priv->workqueue, &priv->restart); | |
1510 | } | |
1511 | } | |
1512 | EXPORT_SYMBOL(iwl_irq_handle_error); | |
1513 | ||
1514 | void iwl_configure_filter(struct ieee80211_hw *hw, | |
1515 | unsigned int changed_flags, | |
1516 | unsigned int *total_flags, | |
3ac64bee | 1517 | u64 multicast) |
8ccde88a SO |
1518 | { |
1519 | struct iwl_priv *priv = hw->priv; | |
1520 | __le32 *filter_flags = &priv->staging_rxon.filter_flags; | |
1521 | ||
e1623446 | 1522 | IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n", |
8ccde88a SO |
1523 | changed_flags, *total_flags); |
1524 | ||
1525 | if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) { | |
1526 | if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) | |
1527 | *filter_flags |= RXON_FILTER_PROMISC_MSK; | |
1528 | else | |
1529 | *filter_flags &= ~RXON_FILTER_PROMISC_MSK; | |
1530 | } | |
1531 | if (changed_flags & FIF_ALLMULTI) { | |
1532 | if (*total_flags & FIF_ALLMULTI) | |
1533 | *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK; | |
1534 | else | |
1535 | *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK; | |
1536 | } | |
1537 | if (changed_flags & FIF_CONTROL) { | |
1538 | if (*total_flags & FIF_CONTROL) | |
1539 | *filter_flags |= RXON_FILTER_CTL2HOST_MSK; | |
1540 | else | |
1541 | *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK; | |
1542 | } | |
1543 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { | |
1544 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) | |
1545 | *filter_flags |= RXON_FILTER_BCON_AWARE_MSK; | |
1546 | else | |
1547 | *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK; | |
1548 | } | |
1549 | ||
1550 | /* We avoid iwl_commit_rxon here to commit the new filter flags | |
1551 | * since mac80211 will call ieee80211_hw_config immediately. | |
1552 | * (mc_list is not supported at this time). Otherwise, we need to | |
1553 | * queue a background iwl_commit_rxon work. | |
1554 | */ | |
1555 | ||
1556 | *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | | |
1557 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; | |
1558 | } | |
1559 | EXPORT_SYMBOL(iwl_configure_filter); | |
1560 | ||
6ba87956 | 1561 | int iwl_setup_mac(struct iwl_priv *priv) |
bf85ea4f | 1562 | { |
6ba87956 | 1563 | int ret; |
bf85ea4f | 1564 | struct ieee80211_hw *hw = priv->hw; |
e227ceac | 1565 | hw->rate_control_algorithm = "iwl-agn-rs"; |
bf85ea4f | 1566 | |
566bfe5a | 1567 | /* Tell mac80211 our characteristics */ |
605a0bd6 | 1568 | hw->flags = IEEE80211_HW_SIGNAL_DBM | |
8b30b1fe | 1569 | IEEE80211_HW_NOISE_DBM | |
4be8c387 | 1570 | IEEE80211_HW_AMPDU_AGGREGATION | |
f55e668f | 1571 | IEEE80211_HW_SPECTRUM_MGMT | |
e312c24c JB |
1572 | IEEE80211_HW_SUPPORTS_PS | |
1573 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | |
f59ac048 | 1574 | hw->wiphy->interface_modes = |
f59ac048 LR |
1575 | BIT(NL80211_IFTYPE_STATION) | |
1576 | BIT(NL80211_IFTYPE_ADHOC); | |
ea4a82dc | 1577 | |
2a44f911 | 1578 | hw->wiphy->custom_regulatory = true; |
1ecf9fc1 | 1579 | |
37184244 LR |
1580 | /* Firmware does not support this */ |
1581 | hw->wiphy->disable_beacon_hints = true; | |
1582 | ||
b23da49e JB |
1583 | /* |
1584 | * For now, disable PS by default because it affects | |
1585 | * RX performance significantly. | |
1586 | */ | |
1587 | hw->wiphy->ps_default = false; | |
1588 | ||
1ecf9fc1 JB |
1589 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; |
1590 | /* we create the 802.11 header and a zero-length SSID element */ | |
1591 | hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2; | |
ea4a82dc | 1592 | |
bf85ea4f AK |
1593 | /* Default value; 4 EDCA QOS priorities */ |
1594 | hw->queues = 4; | |
6ba87956 | 1595 | |
b5d7be5e | 1596 | hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL; |
6ba87956 TW |
1597 | |
1598 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) | |
1599 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
1600 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
1601 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
1602 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
1603 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
1604 | ||
1605 | ret = ieee80211_register_hw(priv->hw); | |
1606 | if (ret) { | |
15b1687c | 1607 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); |
6ba87956 TW |
1608 | return ret; |
1609 | } | |
1610 | priv->mac80211_registered = 1; | |
1611 | ||
1612 | return 0; | |
bf85ea4f | 1613 | } |
6ba87956 | 1614 | EXPORT_SYMBOL(iwl_setup_mac); |
bf85ea4f | 1615 | |
da154e30 RR |
1616 | int iwl_set_hw_params(struct iwl_priv *priv) |
1617 | { | |
da154e30 RR |
1618 | priv->hw_params.max_rxq_size = RX_QUEUE_SIZE; |
1619 | priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; | |
1620 | if (priv->cfg->mod_params->amsdu_size_8K) | |
1621 | priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K; | |
1622 | else | |
1623 | priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K; | |
1624 | priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256; | |
1625 | ||
2c2f3b33 TW |
1626 | priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL; |
1627 | ||
49779293 RR |
1628 | if (priv->cfg->mod_params->disable_11n) |
1629 | priv->cfg->sku &= ~IWL_SKU_N; | |
1630 | ||
da154e30 RR |
1631 | /* Device-specific setup */ |
1632 | return priv->cfg->ops->lib->set_hw_params(priv); | |
1633 | } | |
1634 | EXPORT_SYMBOL(iwl_set_hw_params); | |
6ba87956 TW |
1635 | |
1636 | int iwl_init_drv(struct iwl_priv *priv) | |
c7de35cd RR |
1637 | { |
1638 | int ret; | |
c7de35cd | 1639 | |
c7de35cd RR |
1640 | priv->ibss_beacon = NULL; |
1641 | ||
1642 | spin_lock_init(&priv->lock); | |
c7de35cd RR |
1643 | spin_lock_init(&priv->sta_lock); |
1644 | spin_lock_init(&priv->hcmd_lock); | |
c7de35cd | 1645 | |
c7de35cd RR |
1646 | INIT_LIST_HEAD(&priv->free_frames); |
1647 | ||
1648 | mutex_init(&priv->mutex); | |
1649 | ||
1650 | /* Clear the driver's (not device's) station table */ | |
c587de0b | 1651 | iwl_clear_stations_table(priv); |
c7de35cd RR |
1652 | |
1653 | priv->data_retry_limit = -1; | |
1654 | priv->ieee_channels = NULL; | |
1655 | priv->ieee_rates = NULL; | |
1656 | priv->band = IEEE80211_BAND_2GHZ; | |
1657 | ||
05c914fe | 1658 | priv->iw_mode = NL80211_IFTYPE_STATION; |
c7de35cd | 1659 | |
12837be1 | 1660 | priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED; |
c7de35cd RR |
1661 | |
1662 | /* Choose which receivers/antennas to use */ | |
45823531 AK |
1663 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
1664 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
1665 | ||
f53696de | 1666 | iwl_init_scan_params(priv); |
c7de35cd RR |
1667 | |
1668 | iwl_reset_qos(priv); | |
1669 | ||
1670 | priv->qos_data.qos_active = 0; | |
1671 | priv->qos_data.qos_cap.val = 0; | |
1672 | ||
c7de35cd | 1673 | priv->rates_mask = IWL_RATES_MASK; |
02eec9c5 WYG |
1674 | /* Set the tx_power_user_lmt to the lowest power level |
1675 | * this value will get overwritten by channel max power avg | |
1676 | * from eeprom */ | |
1677 | priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN; | |
c7de35cd RR |
1678 | |
1679 | ret = iwl_init_channel_map(priv); | |
1680 | if (ret) { | |
15b1687c | 1681 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); |
c7de35cd RR |
1682 | goto err; |
1683 | } | |
1684 | ||
1685 | ret = iwlcore_init_geos(priv); | |
1686 | if (ret) { | |
15b1687c | 1687 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); |
c7de35cd RR |
1688 | goto err_free_channel_map; |
1689 | } | |
534166de | 1690 | iwlcore_init_hw_rates(priv, priv->ieee_rates); |
c7de35cd | 1691 | |
c7de35cd RR |
1692 | return 0; |
1693 | ||
c7de35cd RR |
1694 | err_free_channel_map: |
1695 | iwl_free_channel_map(priv); | |
1696 | err: | |
1697 | return ret; | |
1698 | } | |
6ba87956 | 1699 | EXPORT_SYMBOL(iwl_init_drv); |
c7de35cd | 1700 | |
630fe9b6 TW |
1701 | int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force) |
1702 | { | |
1703 | int ret = 0; | |
1704 | if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) { | |
daf518de WF |
1705 | IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n", |
1706 | tx_power, | |
1707 | IWL_TX_POWER_TARGET_POWER_MIN); | |
630fe9b6 TW |
1708 | return -EINVAL; |
1709 | } | |
1710 | ||
dc1b0973 | 1711 | if (tx_power > priv->tx_power_device_lmt) { |
08f2d58d WYG |
1712 | IWL_WARN(priv, |
1713 | "Requested user TXPOWER %d above upper limit %d.\n", | |
dc1b0973 | 1714 | tx_power, priv->tx_power_device_lmt); |
630fe9b6 TW |
1715 | return -EINVAL; |
1716 | } | |
1717 | ||
1718 | if (priv->tx_power_user_lmt != tx_power) | |
1719 | force = true; | |
1720 | ||
1721 | priv->tx_power_user_lmt = tx_power; | |
1722 | ||
019fb97d MA |
1723 | /* if nic is not up don't send command */ |
1724 | if (!iwl_is_ready_rf(priv)) | |
1725 | return ret; | |
1726 | ||
630fe9b6 TW |
1727 | if (force && priv->cfg->ops->lib->send_tx_power) |
1728 | ret = priv->cfg->ops->lib->send_tx_power(priv); | |
1729 | ||
1730 | return ret; | |
1731 | } | |
1732 | EXPORT_SYMBOL(iwl_set_tx_power); | |
1733 | ||
6ba87956 | 1734 | void iwl_uninit_drv(struct iwl_priv *priv) |
bf85ea4f | 1735 | { |
6e21f2c1 | 1736 | iwl_calib_free_results(priv); |
6ba87956 TW |
1737 | iwlcore_free_geos(priv); |
1738 | iwl_free_channel_map(priv); | |
261415f7 | 1739 | kfree(priv->scan); |
bf85ea4f | 1740 | } |
6ba87956 | 1741 | EXPORT_SYMBOL(iwl_uninit_drv); |
bf85ea4f | 1742 | |
ef850d7c MA |
1743 | #define ICT_COUNT (PAGE_SIZE/sizeof(u32)) |
1744 | ||
1745 | /* Free dram table */ | |
1746 | void iwl_free_isr_ict(struct iwl_priv *priv) | |
1747 | { | |
1748 | if (priv->ict_tbl_vir) { | |
1749 | pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) + | |
1750 | PAGE_SIZE, priv->ict_tbl_vir, | |
1751 | priv->ict_tbl_dma); | |
1752 | priv->ict_tbl_vir = NULL; | |
1753 | } | |
1754 | } | |
1755 | EXPORT_SYMBOL(iwl_free_isr_ict); | |
1756 | ||
1757 | ||
1758 | /* allocate dram shared table it is a PAGE_SIZE aligned | |
1759 | * also reset all data related to ICT table interrupt. | |
1760 | */ | |
1761 | int iwl_alloc_isr_ict(struct iwl_priv *priv) | |
1762 | { | |
1763 | ||
1764 | if (priv->cfg->use_isr_legacy) | |
1765 | return 0; | |
1766 | /* allocate shrared data table */ | |
1767 | priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) * | |
1768 | ICT_COUNT) + PAGE_SIZE, | |
1769 | &priv->ict_tbl_dma); | |
1770 | if (!priv->ict_tbl_vir) | |
1771 | return -ENOMEM; | |
1772 | ||
1773 | /* align table to PAGE_SIZE boundry */ | |
1774 | priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE); | |
1775 | ||
1776 | IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n", | |
1777 | (unsigned long long)priv->ict_tbl_dma, | |
1778 | (unsigned long long)priv->aligned_ict_tbl_dma, | |
1779 | (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma)); | |
1780 | ||
1781 | priv->ict_tbl = priv->ict_tbl_vir + | |
1782 | (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma); | |
1783 | ||
1784 | IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n", | |
1785 | priv->ict_tbl, priv->ict_tbl_vir, | |
1786 | (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma)); | |
1787 | ||
1788 | /* reset table and index to all 0 */ | |
1789 | memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE); | |
1790 | priv->ict_index = 0; | |
1791 | ||
40cefda9 MA |
1792 | /* add periodic RX interrupt */ |
1793 | priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC; | |
ef850d7c MA |
1794 | return 0; |
1795 | } | |
1796 | EXPORT_SYMBOL(iwl_alloc_isr_ict); | |
1797 | ||
1798 | /* Device is going up inform it about using ICT interrupt table, | |
1799 | * also we need to tell the driver to start using ICT interrupt. | |
1800 | */ | |
1801 | int iwl_reset_ict(struct iwl_priv *priv) | |
1802 | { | |
1803 | u32 val; | |
1804 | unsigned long flags; | |
1805 | ||
1806 | if (!priv->ict_tbl_vir) | |
1807 | return 0; | |
1808 | ||
1809 | spin_lock_irqsave(&priv->lock, flags); | |
1810 | iwl_disable_interrupts(priv); | |
1811 | ||
1812 | memset(&priv->ict_tbl[0],0, sizeof(u32) * ICT_COUNT); | |
1813 | ||
1814 | val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT; | |
1815 | ||
1816 | val |= CSR_DRAM_INT_TBL_ENABLE; | |
1817 | val |= CSR_DRAM_INIT_TBL_WRAP_CHECK; | |
1818 | ||
1819 | IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X " | |
1820 | "aligned dma address %Lx\n", | |
1821 | val, (unsigned long long)priv->aligned_ict_tbl_dma); | |
1822 | ||
1823 | iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val); | |
1824 | priv->use_ict = true; | |
1825 | priv->ict_index = 0; | |
40cefda9 | 1826 | iwl_write32(priv, CSR_INT, priv->inta_mask); |
ef850d7c MA |
1827 | iwl_enable_interrupts(priv); |
1828 | spin_unlock_irqrestore(&priv->lock, flags); | |
1829 | ||
1830 | return 0; | |
1831 | } | |
1832 | EXPORT_SYMBOL(iwl_reset_ict); | |
1833 | ||
1834 | /* Device is going down disable ict interrupt usage */ | |
1835 | void iwl_disable_ict(struct iwl_priv *priv) | |
1836 | { | |
1837 | unsigned long flags; | |
1838 | ||
1839 | spin_lock_irqsave(&priv->lock, flags); | |
1840 | priv->use_ict = false; | |
1841 | spin_unlock_irqrestore(&priv->lock, flags); | |
1842 | } | |
1843 | EXPORT_SYMBOL(iwl_disable_ict); | |
1844 | ||
1845 | /* interrupt handler using ict table, with this interrupt driver will | |
1846 | * stop using INTA register to get device's interrupt, reading this register | |
1847 | * is expensive, device will write interrupts in ICT dram table, increment | |
1848 | * index then will fire interrupt to driver, driver will OR all ICT table | |
1849 | * entries from current index up to table entry with 0 value. the result is | |
1850 | * the interrupt we need to service, driver will set the entries back to 0 and | |
1851 | * set index. | |
1852 | */ | |
1853 | irqreturn_t iwl_isr_ict(int irq, void *data) | |
1854 | { | |
1855 | struct iwl_priv *priv = data; | |
1856 | u32 inta, inta_mask; | |
1857 | u32 val = 0; | |
1858 | ||
1859 | if (!priv) | |
1860 | return IRQ_NONE; | |
1861 | ||
1862 | /* dram interrupt table not set yet, | |
1863 | * use legacy interrupt. | |
1864 | */ | |
1865 | if (!priv->use_ict) | |
1866 | return iwl_isr(irq, data); | |
1867 | ||
1868 | spin_lock(&priv->lock); | |
1869 | ||
1870 | /* Disable (but don't clear!) interrupts here to avoid | |
1871 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
1872 | * If we have something to service, the tasklet will re-enable ints. | |
1873 | * If we *don't* have something, we'll re-enable before leaving here. | |
1874 | */ | |
1875 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ | |
1876 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
1877 | ||
1878 | ||
1879 | /* Ignore interrupt if there's nothing in NIC to service. | |
1880 | * This may be due to IRQ shared with another device, | |
1881 | * or due to sporadic interrupts thrown from our NIC. */ | |
1882 | if (!priv->ict_tbl[priv->ict_index]) { | |
1883 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n"); | |
1884 | goto none; | |
1885 | } | |
1886 | ||
1887 | /* read all entries that not 0 start with ict_index */ | |
1888 | while (priv->ict_tbl[priv->ict_index]) { | |
1889 | ||
1890 | val |= priv->ict_tbl[priv->ict_index]; | |
1891 | IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n", | |
1892 | priv->ict_index, | |
1893 | priv->ict_tbl[priv->ict_index]); | |
1894 | priv->ict_tbl[priv->ict_index] = 0; | |
1895 | priv->ict_index = iwl_queue_inc_wrap(priv->ict_index, | |
1896 | ICT_COUNT); | |
1897 | ||
1898 | } | |
1899 | ||
1900 | /* We should not get this value, just ignore it. */ | |
1901 | if (val == 0xffffffff) | |
1902 | val = 0; | |
1903 | ||
1904 | inta = (0xff & val) | ((0xff00 & val) << 16); | |
1905 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n", | |
1906 | inta, inta_mask, val); | |
1907 | ||
40cefda9 | 1908 | inta &= priv->inta_mask; |
ef850d7c MA |
1909 | priv->inta |= inta; |
1910 | ||
1911 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ | |
1912 | if (likely(inta)) | |
1913 | tasklet_schedule(&priv->irq_tasklet); | |
1914 | else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) { | |
1915 | /* Allow interrupt if was disabled by this handler and | |
1916 | * no tasklet was schedules, We should not enable interrupt, | |
1917 | * tasklet will enable it. | |
1918 | */ | |
1919 | iwl_enable_interrupts(priv); | |
1920 | } | |
1921 | ||
1922 | spin_unlock(&priv->lock); | |
1923 | return IRQ_HANDLED; | |
1924 | ||
1925 | none: | |
1926 | /* re-enable interrupts here since we don't have anything to service. | |
1927 | * only Re-enable if disabled by irq. | |
1928 | */ | |
1929 | if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) | |
1930 | iwl_enable_interrupts(priv); | |
1931 | ||
1932 | spin_unlock(&priv->lock); | |
1933 | return IRQ_NONE; | |
1934 | } | |
1935 | EXPORT_SYMBOL(iwl_isr_ict); | |
1936 | ||
1937 | ||
1938 | static irqreturn_t iwl_isr(int irq, void *data) | |
1939 | { | |
1940 | struct iwl_priv *priv = data; | |
1941 | u32 inta, inta_mask; | |
d651ae32 | 1942 | #ifdef CONFIG_IWLWIFI_DEBUG |
ef850d7c | 1943 | u32 inta_fh; |
d651ae32 | 1944 | #endif |
ef850d7c MA |
1945 | if (!priv) |
1946 | return IRQ_NONE; | |
1947 | ||
1948 | spin_lock(&priv->lock); | |
1949 | ||
1950 | /* Disable (but don't clear!) interrupts here to avoid | |
1951 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
1952 | * If we have something to service, the tasklet will re-enable ints. | |
1953 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
1954 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ | |
1955 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
1956 | ||
1957 | /* Discover which interrupts are active/pending */ | |
1958 | inta = iwl_read32(priv, CSR_INT); | |
1959 | ||
1960 | /* Ignore interrupt if there's nothing in NIC to service. | |
1961 | * This may be due to IRQ shared with another device, | |
1962 | * or due to sporadic interrupts thrown from our NIC. */ | |
1963 | if (!inta) { | |
1964 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n"); | |
1965 | goto none; | |
1966 | } | |
1967 | ||
1968 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
1969 | /* Hardware disappeared. It might have already raised | |
1970 | * an interrupt */ | |
1971 | IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta); | |
1972 | goto unplugged; | |
1973 | } | |
1974 | ||
1975 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1976 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
ef850d7c MA |
1977 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1978 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, " | |
1979 | "fh 0x%08x\n", inta, inta_mask, inta_fh); | |
1980 | } | |
1981 | #endif | |
1982 | ||
1983 | priv->inta |= inta; | |
1984 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ | |
1985 | if (likely(inta)) | |
1986 | tasklet_schedule(&priv->irq_tasklet); | |
1987 | else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) | |
1988 | iwl_enable_interrupts(priv); | |
1989 | ||
1990 | unplugged: | |
1991 | spin_unlock(&priv->lock); | |
1992 | return IRQ_HANDLED; | |
1993 | ||
1994 | none: | |
1995 | /* re-enable interrupts here since we don't have anything to service. */ | |
1996 | /* only Re-enable if diabled by irq and no schedules tasklet. */ | |
1997 | if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) | |
1998 | iwl_enable_interrupts(priv); | |
1999 | ||
2000 | spin_unlock(&priv->lock); | |
2001 | return IRQ_NONE; | |
2002 | } | |
2003 | ||
2004 | irqreturn_t iwl_isr_legacy(int irq, void *data) | |
f17d08a6 AK |
2005 | { |
2006 | struct iwl_priv *priv = data; | |
2007 | u32 inta, inta_mask; | |
2008 | u32 inta_fh; | |
2009 | if (!priv) | |
2010 | return IRQ_NONE; | |
2011 | ||
2012 | spin_lock(&priv->lock); | |
2013 | ||
2014 | /* Disable (but don't clear!) interrupts here to avoid | |
2015 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
2016 | * If we have something to service, the tasklet will re-enable ints. | |
2017 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
2018 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ | |
2019 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
2020 | ||
2021 | /* Discover which interrupts are active/pending */ | |
2022 | inta = iwl_read32(priv, CSR_INT); | |
2023 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
2024 | ||
2025 | /* Ignore interrupt if there's nothing in NIC to service. | |
2026 | * This may be due to IRQ shared with another device, | |
2027 | * or due to sporadic interrupts thrown from our NIC. */ | |
2028 | if (!inta && !inta_fh) { | |
2029 | IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n"); | |
2030 | goto none; | |
2031 | } | |
2032 | ||
2033 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
2034 | /* Hardware disappeared. It might have already raised | |
2035 | * an interrupt */ | |
2036 | IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta); | |
2037 | goto unplugged; | |
2038 | } | |
2039 | ||
2040 | IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | |
2041 | inta, inta_mask, inta_fh); | |
2042 | ||
2043 | inta &= ~CSR_INT_BIT_SCD; | |
2044 | ||
2045 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ | |
2046 | if (likely(inta || inta_fh)) | |
2047 | tasklet_schedule(&priv->irq_tasklet); | |
2048 | ||
2049 | unplugged: | |
2050 | spin_unlock(&priv->lock); | |
2051 | return IRQ_HANDLED; | |
2052 | ||
2053 | none: | |
2054 | /* re-enable interrupts here since we don't have anything to service. */ | |
2055 | /* only Re-enable if diabled by irq */ | |
2056 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
2057 | iwl_enable_interrupts(priv); | |
2058 | spin_unlock(&priv->lock); | |
2059 | return IRQ_NONE; | |
2060 | } | |
ef850d7c | 2061 | EXPORT_SYMBOL(iwl_isr_legacy); |
f17d08a6 | 2062 | |
17f841cd SO |
2063 | int iwl_send_bt_config(struct iwl_priv *priv) |
2064 | { | |
2065 | struct iwl_bt_cmd bt_cmd = { | |
2066 | .flags = 3, | |
2067 | .lead_time = 0xAA, | |
2068 | .max_kill = 1, | |
2069 | .kill_ack_mask = 0, | |
2070 | .kill_cts_mask = 0, | |
2071 | }; | |
2072 | ||
2073 | return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, | |
2074 | sizeof(struct iwl_bt_cmd), &bt_cmd); | |
2075 | } | |
2076 | EXPORT_SYMBOL(iwl_send_bt_config); | |
2077 | ||
49ea8596 EG |
2078 | int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags) |
2079 | { | |
2080 | u32 stat_flags = 0; | |
2081 | struct iwl_host_cmd cmd = { | |
2082 | .id = REPLY_STATISTICS_CMD, | |
c2acea8e | 2083 | .flags = flags, |
49ea8596 EG |
2084 | .len = sizeof(stat_flags), |
2085 | .data = (u8 *) &stat_flags, | |
2086 | }; | |
2087 | return iwl_send_cmd(priv, &cmd); | |
2088 | } | |
2089 | EXPORT_SYMBOL(iwl_send_statistics_request); | |
7e8c519e | 2090 | |
b0692f2f EG |
2091 | /** |
2092 | * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host, | |
2093 | * using sample data 100 bytes apart. If these sample points are good, | |
2094 | * it's a pretty good bet that everything between them is good, too. | |
2095 | */ | |
2096 | static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) | |
2097 | { | |
2098 | u32 val; | |
2099 | int ret = 0; | |
2100 | u32 errcnt = 0; | |
2101 | u32 i; | |
2102 | ||
e1623446 | 2103 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b0692f2f | 2104 | |
b0692f2f EG |
2105 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { |
2106 | /* read data comes through single port, auto-incr addr */ | |
2107 | /* NOTE: Use the debugless read so we don't flood kernel log | |
2108 | * if IWL_DL_IO is set */ | |
2109 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, | |
250bdd21 | 2110 | i + IWL49_RTC_INST_LOWER_BOUND); |
b0692f2f EG |
2111 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
2112 | if (val != le32_to_cpu(*image)) { | |
2113 | ret = -EIO; | |
2114 | errcnt++; | |
2115 | if (errcnt >= 3) | |
2116 | break; | |
2117 | } | |
2118 | } | |
2119 | ||
b0692f2f EG |
2120 | return ret; |
2121 | } | |
2122 | ||
2123 | /** | |
2124 | * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host, | |
2125 | * looking at all data. | |
2126 | */ | |
2127 | static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image, | |
2128 | u32 len) | |
2129 | { | |
2130 | u32 val; | |
2131 | u32 save_len = len; | |
2132 | int ret = 0; | |
2133 | u32 errcnt; | |
2134 | ||
e1623446 | 2135 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b0692f2f | 2136 | |
250bdd21 SO |
2137 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
2138 | IWL49_RTC_INST_LOWER_BOUND); | |
b0692f2f EG |
2139 | |
2140 | errcnt = 0; | |
2141 | for (; len > 0; len -= sizeof(u32), image++) { | |
2142 | /* read data comes through single port, auto-incr addr */ | |
2143 | /* NOTE: Use the debugless read so we don't flood kernel log | |
2144 | * if IWL_DL_IO is set */ | |
2145 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
2146 | if (val != le32_to_cpu(*image)) { | |
15b1687c | 2147 | IWL_ERR(priv, "uCode INST section is invalid at " |
b0692f2f EG |
2148 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
2149 | save_len - len, val, le32_to_cpu(*image)); | |
2150 | ret = -EIO; | |
2151 | errcnt++; | |
2152 | if (errcnt >= 20) | |
2153 | break; | |
2154 | } | |
2155 | } | |
2156 | ||
b0692f2f | 2157 | if (!errcnt) |
e1623446 TW |
2158 | IWL_DEBUG_INFO(priv, |
2159 | "ucode image in INSTRUCTION memory is good\n"); | |
b0692f2f EG |
2160 | |
2161 | return ret; | |
2162 | } | |
2163 | ||
2164 | /** | |
2165 | * iwl_verify_ucode - determine which instruction image is in SRAM, | |
2166 | * and verify its contents | |
2167 | */ | |
2168 | int iwl_verify_ucode(struct iwl_priv *priv) | |
2169 | { | |
2170 | __le32 *image; | |
2171 | u32 len; | |
2172 | int ret; | |
2173 | ||
2174 | /* Try bootstrap */ | |
2175 | image = (__le32 *)priv->ucode_boot.v_addr; | |
2176 | len = priv->ucode_boot.len; | |
2177 | ret = iwlcore_verify_inst_sparse(priv, image, len); | |
2178 | if (!ret) { | |
e1623446 | 2179 | IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n"); |
b0692f2f EG |
2180 | return 0; |
2181 | } | |
2182 | ||
2183 | /* Try initialize */ | |
2184 | image = (__le32 *)priv->ucode_init.v_addr; | |
2185 | len = priv->ucode_init.len; | |
2186 | ret = iwlcore_verify_inst_sparse(priv, image, len); | |
2187 | if (!ret) { | |
e1623446 | 2188 | IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n"); |
b0692f2f EG |
2189 | return 0; |
2190 | } | |
2191 | ||
2192 | /* Try runtime/protocol */ | |
2193 | image = (__le32 *)priv->ucode_code.v_addr; | |
2194 | len = priv->ucode_code.len; | |
2195 | ret = iwlcore_verify_inst_sparse(priv, image, len); | |
2196 | if (!ret) { | |
e1623446 | 2197 | IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n"); |
b0692f2f EG |
2198 | return 0; |
2199 | } | |
2200 | ||
15b1687c | 2201 | IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); |
b0692f2f EG |
2202 | |
2203 | /* Since nothing seems to match, show first several data entries in | |
2204 | * instruction SRAM, so maybe visual inspection will give a clue. | |
2205 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
2206 | image = (__le32 *)priv->ucode_boot.v_addr; | |
2207 | len = priv->ucode_boot.len; | |
2208 | ret = iwl_verify_inst_full(priv, image, len); | |
2209 | ||
2210 | return ret; | |
2211 | } | |
2212 | EXPORT_SYMBOL(iwl_verify_ucode); | |
2213 | ||
56e12615 | 2214 | |
47f4a587 EG |
2215 | void iwl_rf_kill_ct_config(struct iwl_priv *priv) |
2216 | { | |
2217 | struct iwl_ct_kill_config cmd; | |
672639de | 2218 | struct iwl_ct_kill_throttling_config adv_cmd; |
47f4a587 EG |
2219 | unsigned long flags; |
2220 | int ret = 0; | |
2221 | ||
2222 | spin_lock_irqsave(&priv->lock, flags); | |
2223 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
2224 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); | |
2225 | spin_unlock_irqrestore(&priv->lock, flags); | |
3ad3b92a | 2226 | priv->thermal_throttle.ct_kill_toggle = false; |
47f4a587 | 2227 | |
672639de WYG |
2228 | switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { |
2229 | case CSR_HW_REV_TYPE_1000: | |
2230 | case CSR_HW_REV_TYPE_6x00: | |
2231 | case CSR_HW_REV_TYPE_6x50: | |
2232 | adv_cmd.critical_temperature_enter = | |
2233 | cpu_to_le32(priv->hw_params.ct_kill_threshold); | |
2234 | adv_cmd.critical_temperature_exit = | |
2235 | cpu_to_le32(priv->hw_params.ct_kill_exit_threshold); | |
2236 | ||
2237 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, | |
2238 | sizeof(adv_cmd), &adv_cmd); | |
d91b1ba3 WYG |
2239 | if (ret) |
2240 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); | |
2241 | else | |
2242 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD " | |
2243 | "succeeded, " | |
2244 | "critical temperature enter is %d," | |
2245 | "exit is %d\n", | |
2246 | priv->hw_params.ct_kill_threshold, | |
2247 | priv->hw_params.ct_kill_exit_threshold); | |
672639de WYG |
2248 | break; |
2249 | default: | |
2250 | cmd.critical_temperature_R = | |
2251 | cpu_to_le32(priv->hw_params.ct_kill_threshold); | |
189a2b59 | 2252 | |
672639de WYG |
2253 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, |
2254 | sizeof(cmd), &cmd); | |
d91b1ba3 WYG |
2255 | if (ret) |
2256 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); | |
2257 | else | |
2258 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD " | |
2259 | "succeeded, " | |
2260 | "critical temperature is %d\n", | |
2261 | priv->hw_params.ct_kill_threshold); | |
672639de WYG |
2262 | break; |
2263 | } | |
47f4a587 EG |
2264 | } |
2265 | EXPORT_SYMBOL(iwl_rf_kill_ct_config); | |
14a08a7f | 2266 | |
0ad91a35 | 2267 | |
14a08a7f EG |
2268 | /* |
2269 | * CARD_STATE_CMD | |
2270 | * | |
2271 | * Use: Sets the device's internal card state to enable, disable, or halt | |
2272 | * | |
2273 | * When in the 'enable' state the card operates as normal. | |
2274 | * When in the 'disable' state, the card enters into a low power mode. | |
2275 | * When in the 'halt' state, the card is shut down and must be fully | |
2276 | * restarted to come back on. | |
2277 | */ | |
c496294e | 2278 | int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag) |
14a08a7f EG |
2279 | { |
2280 | struct iwl_host_cmd cmd = { | |
2281 | .id = REPLY_CARD_STATE_CMD, | |
2282 | .len = sizeof(u32), | |
2283 | .data = &flags, | |
c2acea8e | 2284 | .flags = meta_flag, |
14a08a7f EG |
2285 | }; |
2286 | ||
2287 | return iwl_send_cmd(priv, &cmd); | |
2288 | } | |
2289 | ||
030f05ed AK |
2290 | void iwl_rx_pm_sleep_notif(struct iwl_priv *priv, |
2291 | struct iwl_rx_mem_buffer *rxb) | |
2292 | { | |
2293 | #ifdef CONFIG_IWLWIFI_DEBUG | |
2294 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
2295 | struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif); | |
2296 | IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n", | |
2297 | sleep->pm_sleep_mode, sleep->pm_wakeup_src); | |
2298 | #endif | |
2299 | } | |
2300 | EXPORT_SYMBOL(iwl_rx_pm_sleep_notif); | |
2301 | ||
2302 | void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv, | |
2303 | struct iwl_rx_mem_buffer *rxb) | |
2304 | { | |
2305 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
396887a2 | 2306 | u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; |
030f05ed | 2307 | IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled " |
396887a2 DH |
2308 | "notification for %s:\n", len, |
2309 | get_cmd_string(pkt->hdr.cmd)); | |
2310 | iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len); | |
030f05ed AK |
2311 | } |
2312 | EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif); | |
261b9c33 AK |
2313 | |
2314 | void iwl_rx_reply_error(struct iwl_priv *priv, | |
2315 | struct iwl_rx_mem_buffer *rxb) | |
2316 | { | |
2317 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
2318 | ||
2319 | IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) " | |
2320 | "seq 0x%04X ser 0x%08X\n", | |
2321 | le32_to_cpu(pkt->u.err_resp.error_type), | |
2322 | get_cmd_string(pkt->u.err_resp.cmd_id), | |
2323 | pkt->u.err_resp.cmd_id, | |
2324 | le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num), | |
2325 | le32_to_cpu(pkt->u.err_resp.error_info)); | |
2326 | } | |
2327 | EXPORT_SYMBOL(iwl_rx_reply_error); | |
2328 | ||
a83b9141 WYG |
2329 | void iwl_clear_isr_stats(struct iwl_priv *priv) |
2330 | { | |
2331 | memset(&priv->isr_stats, 0, sizeof(priv->isr_stats)); | |
2332 | } | |
a83b9141 | 2333 | |
488829f1 AK |
2334 | int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue, |
2335 | const struct ieee80211_tx_queue_params *params) | |
2336 | { | |
2337 | struct iwl_priv *priv = hw->priv; | |
2338 | unsigned long flags; | |
2339 | int q; | |
2340 | ||
2341 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
2342 | ||
2343 | if (!iwl_is_ready_rf(priv)) { | |
2344 | IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n"); | |
2345 | return -EIO; | |
2346 | } | |
2347 | ||
2348 | if (queue >= AC_NUM) { | |
2349 | IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue); | |
2350 | return 0; | |
2351 | } | |
2352 | ||
2353 | q = AC_NUM - 1 - queue; | |
2354 | ||
2355 | spin_lock_irqsave(&priv->lock, flags); | |
2356 | ||
2357 | priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min); | |
2358 | priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max); | |
2359 | priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; | |
2360 | priv->qos_data.def_qos_parm.ac[q].edca_txop = | |
2361 | cpu_to_le16((params->txop * 32)); | |
2362 | ||
2363 | priv->qos_data.def_qos_parm.ac[q].reserved1 = 0; | |
2364 | priv->qos_data.qos_active = 1; | |
2365 | ||
2366 | if (priv->iw_mode == NL80211_IFTYPE_AP) | |
2367 | iwl_activate_qos(priv, 1); | |
2368 | else if (priv->assoc_id && iwl_is_associated(priv)) | |
2369 | iwl_activate_qos(priv, 0); | |
2370 | ||
2371 | spin_unlock_irqrestore(&priv->lock, flags); | |
2372 | ||
2373 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2374 | return 0; | |
2375 | } | |
2376 | EXPORT_SYMBOL(iwl_mac_conf_tx); | |
5bbe233b AK |
2377 | |
2378 | static void iwl_ht_conf(struct iwl_priv *priv, | |
2379 | struct ieee80211_bss_conf *bss_conf) | |
2380 | { | |
2381 | struct ieee80211_sta_ht_cap *ht_conf; | |
2382 | struct iwl_ht_info *iwl_conf = &priv->current_ht_config; | |
2383 | struct ieee80211_sta *sta; | |
2384 | ||
2385 | IWL_DEBUG_MAC80211(priv, "enter: \n"); | |
2386 | ||
2387 | if (!iwl_conf->is_ht) | |
2388 | return; | |
2389 | ||
2390 | ||
2391 | /* | |
2392 | * It is totally wrong to base global information on something | |
2393 | * that is valid only when associated, alas, this driver works | |
2394 | * that way and I don't know how to fix it. | |
2395 | */ | |
2396 | ||
2397 | rcu_read_lock(); | |
2398 | sta = ieee80211_find_sta(priv->hw, priv->bssid); | |
2399 | if (!sta) { | |
2400 | rcu_read_unlock(); | |
2401 | return; | |
2402 | } | |
2403 | ht_conf = &sta->ht_cap; | |
2404 | ||
5bbe233b AK |
2405 | iwl_conf->sm_ps = (u8)((ht_conf->cap & IEEE80211_HT_CAP_SM_PS) >> 2); |
2406 | ||
2407 | memcpy(&iwl_conf->mcs, &ht_conf->mcs, 16); | |
2408 | ||
5bbe233b | 2409 | iwl_conf->ht_protection = |
9ed6bcce | 2410 | bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION; |
5bbe233b | 2411 | iwl_conf->non_GF_STA_present = |
9ed6bcce | 2412 | !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); |
5bbe233b AK |
2413 | |
2414 | rcu_read_unlock(); | |
2415 | ||
2416 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2417 | } | |
2418 | ||
2419 | #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) | |
2420 | void iwl_bss_info_changed(struct ieee80211_hw *hw, | |
2d0ddec5 JB |
2421 | struct ieee80211_vif *vif, |
2422 | struct ieee80211_bss_conf *bss_conf, | |
2423 | u32 changes) | |
5bbe233b AK |
2424 | { |
2425 | struct iwl_priv *priv = hw->priv; | |
3a650292 | 2426 | int ret; |
5bbe233b AK |
2427 | |
2428 | IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes); | |
2429 | ||
2d0ddec5 JB |
2430 | if (!iwl_is_alive(priv)) |
2431 | return; | |
2432 | ||
2433 | mutex_lock(&priv->mutex); | |
2434 | ||
2435 | if (changes & BSS_CHANGED_BEACON && | |
2436 | priv->iw_mode == NL80211_IFTYPE_AP) { | |
2437 | dev_kfree_skb(priv->ibss_beacon); | |
2438 | priv->ibss_beacon = ieee80211_beacon_get(hw, vif); | |
2439 | } | |
2440 | ||
d7129e19 JB |
2441 | if (changes & BSS_CHANGED_BEACON_INT) { |
2442 | priv->beacon_int = bss_conf->beacon_int; | |
2443 | /* TODO: in AP mode, do something to make this take effect */ | |
2444 | } | |
2445 | ||
2446 | if (changes & BSS_CHANGED_BSSID) { | |
2447 | IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid); | |
2448 | ||
2449 | /* | |
2450 | * If there is currently a HW scan going on in the | |
2451 | * background then we need to cancel it else the RXON | |
2452 | * below/in post_associate will fail. | |
2453 | */ | |
2d0ddec5 | 2454 | if (iwl_scan_cancel_timeout(priv, 100)) { |
d7129e19 | 2455 | IWL_WARN(priv, "Aborted scan still in progress after 100ms\n"); |
2d0ddec5 JB |
2456 | IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n"); |
2457 | mutex_unlock(&priv->mutex); | |
2458 | return; | |
2459 | } | |
2d0ddec5 | 2460 | |
d7129e19 JB |
2461 | /* mac80211 only sets assoc when in STATION mode */ |
2462 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC || | |
2463 | bss_conf->assoc) { | |
2464 | memcpy(priv->staging_rxon.bssid_addr, | |
2465 | bss_conf->bssid, ETH_ALEN); | |
2d0ddec5 | 2466 | |
d7129e19 JB |
2467 | /* currently needed in a few places */ |
2468 | memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN); | |
2469 | } else { | |
2470 | priv->staging_rxon.filter_flags &= | |
2471 | ~RXON_FILTER_ASSOC_MSK; | |
2d0ddec5 | 2472 | } |
d7129e19 | 2473 | |
2d0ddec5 JB |
2474 | } |
2475 | ||
d7129e19 JB |
2476 | /* |
2477 | * This needs to be after setting the BSSID in case | |
2478 | * mac80211 decides to do both changes at once because | |
2479 | * it will invoke post_associate. | |
2480 | */ | |
2d0ddec5 JB |
2481 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC && |
2482 | changes & BSS_CHANGED_BEACON) { | |
2483 | struct sk_buff *beacon = ieee80211_beacon_get(hw, vif); | |
2484 | ||
2485 | if (beacon) | |
2486 | iwl_mac_beacon_update(hw, beacon); | |
2487 | } | |
2488 | ||
5bbe233b AK |
2489 | if (changes & BSS_CHANGED_ERP_PREAMBLE) { |
2490 | IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n", | |
2491 | bss_conf->use_short_preamble); | |
2492 | if (bss_conf->use_short_preamble) | |
2493 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2494 | else | |
2495 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2496 | } | |
2497 | ||
2498 | if (changes & BSS_CHANGED_ERP_CTS_PROT) { | |
2499 | IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot); | |
2500 | if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ)) | |
2501 | priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK; | |
2502 | else | |
2503 | priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK; | |
2504 | } | |
2505 | ||
d7129e19 JB |
2506 | if (changes & BSS_CHANGED_BASIC_RATES) { |
2507 | /* XXX use this information | |
2508 | * | |
2509 | * To do that, remove code from iwl_set_rate() and put something | |
2510 | * like this here: | |
2511 | * | |
2512 | if (A-band) | |
2513 | priv->staging_rxon.ofdm_basic_rates = | |
2514 | bss_conf->basic_rates; | |
2515 | else | |
2516 | priv->staging_rxon.ofdm_basic_rates = | |
2517 | bss_conf->basic_rates >> 4; | |
2518 | priv->staging_rxon.cck_basic_rates = | |
2519 | bss_conf->basic_rates & 0xF; | |
2520 | */ | |
2521 | } | |
2522 | ||
5bbe233b AK |
2523 | if (changes & BSS_CHANGED_HT) { |
2524 | iwl_ht_conf(priv, bss_conf); | |
45823531 AK |
2525 | |
2526 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
2527 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
5bbe233b AK |
2528 | } |
2529 | ||
2530 | if (changes & BSS_CHANGED_ASSOC) { | |
2531 | IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc); | |
5bbe233b AK |
2532 | if (bss_conf->assoc) { |
2533 | priv->assoc_id = bss_conf->aid; | |
2534 | priv->beacon_int = bss_conf->beacon_int; | |
5bbe233b AK |
2535 | priv->timestamp = bss_conf->timestamp; |
2536 | priv->assoc_capability = bss_conf->assoc_capability; | |
2537 | ||
d7129e19 JB |
2538 | /* |
2539 | * We have just associated, don't start scan too early | |
2540 | * leave time for EAPOL exchange to complete. | |
2541 | * | |
2542 | * XXX: do this in mac80211 | |
5bbe233b AK |
2543 | */ |
2544 | priv->next_scan_jiffies = jiffies + | |
2545 | IWL_DELAY_NEXT_SCAN_AFTER_ASSOC; | |
d7129e19 JB |
2546 | if (!iwl_is_rfkill(priv)) |
2547 | priv->cfg->ops->lib->post_associate(priv); | |
2548 | } else | |
5bbe233b | 2549 | priv->assoc_id = 0; |
d7129e19 JB |
2550 | |
2551 | } | |
2552 | ||
2553 | if (changes && iwl_is_associated(priv) && priv->assoc_id) { | |
2554 | IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n", | |
2555 | changes); | |
2556 | ret = iwl_send_rxon_assoc(priv); | |
2557 | if (!ret) { | |
2558 | /* Sync active_rxon with latest change. */ | |
2559 | memcpy((void *)&priv->active_rxon, | |
2560 | &priv->staging_rxon, | |
2561 | sizeof(struct iwl_rxon_cmd)); | |
5bbe233b | 2562 | } |
5bbe233b | 2563 | } |
d7129e19 JB |
2564 | |
2565 | mutex_unlock(&priv->mutex); | |
2566 | ||
2d0ddec5 | 2567 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
5bbe233b AK |
2568 | } |
2569 | EXPORT_SYMBOL(iwl_bss_info_changed); | |
2570 | ||
9944b938 AK |
2571 | int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb) |
2572 | { | |
2573 | struct iwl_priv *priv = hw->priv; | |
2574 | unsigned long flags; | |
2575 | __le64 timestamp; | |
2576 | ||
2577 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
2578 | ||
2579 | if (!iwl_is_ready_rf(priv)) { | |
2580 | IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n"); | |
2581 | return -EIO; | |
2582 | } | |
2583 | ||
2584 | if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { | |
2585 | IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n"); | |
2586 | return -EIO; | |
2587 | } | |
2588 | ||
2589 | spin_lock_irqsave(&priv->lock, flags); | |
2590 | ||
2591 | if (priv->ibss_beacon) | |
2592 | dev_kfree_skb(priv->ibss_beacon); | |
2593 | ||
2594 | priv->ibss_beacon = skb; | |
2595 | ||
2596 | priv->assoc_id = 0; | |
2597 | timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp; | |
2598 | priv->timestamp = le64_to_cpu(timestamp); | |
2599 | ||
2600 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2601 | spin_unlock_irqrestore(&priv->lock, flags); | |
2602 | ||
2603 | iwl_reset_qos(priv); | |
2604 | ||
2605 | priv->cfg->ops->lib->post_associate(priv); | |
2606 | ||
2607 | ||
2608 | return 0; | |
2609 | } | |
2610 | EXPORT_SYMBOL(iwl_mac_beacon_update); | |
2611 | ||
727882d6 AK |
2612 | int iwl_set_mode(struct iwl_priv *priv, int mode) |
2613 | { | |
2614 | if (mode == NL80211_IFTYPE_ADHOC) { | |
2615 | const struct iwl_channel_info *ch_info; | |
2616 | ||
2617 | ch_info = iwl_get_channel_info(priv, | |
2618 | priv->band, | |
2619 | le16_to_cpu(priv->staging_rxon.channel)); | |
2620 | ||
2621 | if (!ch_info || !is_channel_ibss(ch_info)) { | |
2622 | IWL_ERR(priv, "channel %d not IBSS channel\n", | |
2623 | le16_to_cpu(priv->staging_rxon.channel)); | |
2624 | return -EINVAL; | |
2625 | } | |
2626 | } | |
2627 | ||
2628 | iwl_connection_init_rx_config(priv, mode); | |
2629 | ||
2630 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
2631 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
2632 | ||
2633 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); | |
2634 | ||
c587de0b | 2635 | iwl_clear_stations_table(priv); |
727882d6 AK |
2636 | |
2637 | /* dont commit rxon if rf-kill is on*/ | |
2638 | if (!iwl_is_ready_rf(priv)) | |
2639 | return -EAGAIN; | |
2640 | ||
727882d6 AK |
2641 | iwlcore_commit_rxon(priv); |
2642 | ||
2643 | return 0; | |
2644 | } | |
2645 | EXPORT_SYMBOL(iwl_set_mode); | |
2646 | ||
cbb6ab94 AK |
2647 | int iwl_mac_add_interface(struct ieee80211_hw *hw, |
2648 | struct ieee80211_if_init_conf *conf) | |
2649 | { | |
2650 | struct iwl_priv *priv = hw->priv; | |
2651 | unsigned long flags; | |
2652 | ||
2653 | IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type); | |
2654 | ||
2655 | if (priv->vif) { | |
2656 | IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n"); | |
2657 | return -EOPNOTSUPP; | |
2658 | } | |
2659 | ||
2660 | spin_lock_irqsave(&priv->lock, flags); | |
2661 | priv->vif = conf->vif; | |
2662 | priv->iw_mode = conf->type; | |
2663 | ||
2664 | spin_unlock_irqrestore(&priv->lock, flags); | |
2665 | ||
2666 | mutex_lock(&priv->mutex); | |
2667 | ||
2668 | if (conf->mac_addr) { | |
2669 | IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr); | |
2670 | memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); | |
2671 | } | |
2672 | ||
2673 | if (iwl_set_mode(priv, conf->type) == -EAGAIN) | |
2674 | /* we are not ready, will run again when ready */ | |
2675 | set_bit(STATUS_MODE_PENDING, &priv->status); | |
2676 | ||
2677 | mutex_unlock(&priv->mutex); | |
2678 | ||
2679 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2680 | return 0; | |
2681 | } | |
2682 | EXPORT_SYMBOL(iwl_mac_add_interface); | |
2683 | ||
d8052319 AK |
2684 | void iwl_mac_remove_interface(struct ieee80211_hw *hw, |
2685 | struct ieee80211_if_init_conf *conf) | |
2686 | { | |
2687 | struct iwl_priv *priv = hw->priv; | |
2688 | ||
2689 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
2690 | ||
2691 | mutex_lock(&priv->mutex); | |
2692 | ||
2693 | if (iwl_is_ready_rf(priv)) { | |
2694 | iwl_scan_cancel_timeout(priv, 100); | |
2695 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
2696 | iwlcore_commit_rxon(priv); | |
2697 | } | |
2698 | if (priv->vif == conf->vif) { | |
2699 | priv->vif = NULL; | |
2700 | memset(priv->bssid, 0, ETH_ALEN); | |
2701 | } | |
2702 | mutex_unlock(&priv->mutex); | |
2703 | ||
2704 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2705 | ||
2706 | } | |
2707 | EXPORT_SYMBOL(iwl_mac_remove_interface); | |
2708 | ||
4808368d AK |
2709 | /** |
2710 | * iwl_mac_config - mac80211 config callback | |
2711 | * | |
2712 | * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to | |
2713 | * be set inappropriately and the driver currently sets the hardware up to | |
2714 | * use it whenever needed. | |
2715 | */ | |
2716 | int iwl_mac_config(struct ieee80211_hw *hw, u32 changed) | |
2717 | { | |
2718 | struct iwl_priv *priv = hw->priv; | |
2719 | const struct iwl_channel_info *ch_info; | |
2720 | struct ieee80211_conf *conf = &hw->conf; | |
28bd723b | 2721 | struct iwl_ht_info *ht_conf = &priv->current_ht_config; |
4808368d AK |
2722 | unsigned long flags = 0; |
2723 | int ret = 0; | |
2724 | u16 ch; | |
2725 | int scan_active = 0; | |
2726 | ||
2727 | mutex_lock(&priv->mutex); | |
2728 | ||
4808368d AK |
2729 | IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n", |
2730 | conf->channel->hw_value, changed); | |
2731 | ||
2732 | if (unlikely(!priv->cfg->mod_params->disable_hw_scan && | |
2733 | test_bit(STATUS_SCANNING, &priv->status))) { | |
2734 | scan_active = 1; | |
2735 | IWL_DEBUG_MAC80211(priv, "leave - scanning\n"); | |
2736 | } | |
2737 | ||
2738 | ||
2739 | /* during scanning mac80211 will delay channel setting until | |
2740 | * scan finish with changed = 0 | |
2741 | */ | |
2742 | if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { | |
2743 | if (scan_active) | |
2744 | goto set_ch_out; | |
2745 | ||
2746 | ch = ieee80211_frequency_to_channel(conf->channel->center_freq); | |
2747 | ch_info = iwl_get_channel_info(priv, conf->channel->band, ch); | |
2748 | if (!is_channel_valid(ch_info)) { | |
2749 | IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n"); | |
2750 | ret = -EINVAL; | |
2751 | goto set_ch_out; | |
2752 | } | |
2753 | ||
2754 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC && | |
2755 | !is_channel_ibss(ch_info)) { | |
2756 | IWL_ERR(priv, "channel %d in band %d not " | |
2757 | "IBSS channel\n", | |
2758 | conf->channel->hw_value, conf->channel->band); | |
2759 | ret = -EINVAL; | |
2760 | goto set_ch_out; | |
2761 | } | |
2762 | ||
4808368d AK |
2763 | spin_lock_irqsave(&priv->lock, flags); |
2764 | ||
28bd723b DH |
2765 | /* Configure HT40 channels */ |
2766 | ht_conf->is_ht = conf_is_ht(conf); | |
2767 | if (ht_conf->is_ht) { | |
2768 | if (conf_is_ht40_minus(conf)) { | |
2769 | ht_conf->extension_chan_offset = | |
2770 | IEEE80211_HT_PARAM_CHA_SEC_BELOW; | |
2771 | ht_conf->supported_chan_width = | |
2772 | IWL_CHANNEL_WIDTH_40MHZ; | |
2773 | } else if (conf_is_ht40_plus(conf)) { | |
2774 | ht_conf->extension_chan_offset = | |
2775 | IEEE80211_HT_PARAM_CHA_SEC_ABOVE; | |
2776 | ht_conf->supported_chan_width = | |
2777 | IWL_CHANNEL_WIDTH_40MHZ; | |
2778 | } else { | |
2779 | ht_conf->extension_chan_offset = | |
2780 | IEEE80211_HT_PARAM_CHA_SEC_NONE; | |
2781 | ht_conf->supported_chan_width = | |
2782 | IWL_CHANNEL_WIDTH_20MHZ; | |
2783 | } | |
2784 | } else | |
2785 | ht_conf->supported_chan_width = IWL_CHANNEL_WIDTH_20MHZ; | |
2786 | /* Default to no protection. Protection mode will later be set | |
2787 | * from BSS config in iwl_ht_conf */ | |
2788 | ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE; | |
4808368d AK |
2789 | |
2790 | /* if we are switching from ht to 2.4 clear flags | |
2791 | * from any ht related info since 2.4 does not | |
2792 | * support ht */ | |
2793 | if ((le16_to_cpu(priv->staging_rxon.channel) != ch)) | |
2794 | priv->staging_rxon.flags = 0; | |
2795 | ||
2796 | iwl_set_rxon_channel(priv, conf->channel); | |
2797 | ||
2798 | iwl_set_flags_for_band(priv, conf->channel->band); | |
2799 | spin_unlock_irqrestore(&priv->lock, flags); | |
2800 | set_ch_out: | |
2801 | /* The list of supported rates and rate mask can be different | |
2802 | * for each band; since the band may have changed, reset | |
2803 | * the rate mask to what mac80211 lists */ | |
2804 | iwl_set_rate(priv); | |
2805 | } | |
2806 | ||
e312c24c JB |
2807 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
2808 | ret = iwl_power_update_mode(priv, false); | |
4808368d | 2809 | if (ret) |
e312c24c | 2810 | IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n"); |
4808368d AK |
2811 | } |
2812 | ||
2813 | if (changed & IEEE80211_CONF_CHANGE_POWER) { | |
2814 | IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n", | |
2815 | priv->tx_power_user_lmt, conf->power_level); | |
2816 | ||
2817 | iwl_set_tx_power(priv, conf->power_level, false); | |
2818 | } | |
2819 | ||
2820 | /* call to ensure that 4965 rx_chain is set properly in monitor mode */ | |
2821 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
2822 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
2823 | ||
0cf4c01e MA |
2824 | if (!iwl_is_ready(priv)) { |
2825 | IWL_DEBUG_MAC80211(priv, "leave - not ready\n"); | |
2826 | goto out; | |
2827 | } | |
2828 | ||
4808368d AK |
2829 | if (scan_active) |
2830 | goto out; | |
2831 | ||
2832 | if (memcmp(&priv->active_rxon, | |
2833 | &priv->staging_rxon, sizeof(priv->staging_rxon))) | |
2834 | iwlcore_commit_rxon(priv); | |
2835 | else | |
2836 | IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n"); | |
2837 | ||
2838 | ||
2839 | out: | |
2840 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2841 | mutex_unlock(&priv->mutex); | |
2842 | return ret; | |
2843 | } | |
2844 | EXPORT_SYMBOL(iwl_mac_config); | |
2845 | ||
aa89f31e AK |
2846 | int iwl_mac_get_tx_stats(struct ieee80211_hw *hw, |
2847 | struct ieee80211_tx_queue_stats *stats) | |
2848 | { | |
2849 | struct iwl_priv *priv = hw->priv; | |
2850 | int i, avail; | |
2851 | struct iwl_tx_queue *txq; | |
2852 | struct iwl_queue *q; | |
2853 | unsigned long flags; | |
2854 | ||
2855 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
2856 | ||
2857 | if (!iwl_is_ready_rf(priv)) { | |
2858 | IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n"); | |
2859 | return -EIO; | |
2860 | } | |
2861 | ||
2862 | spin_lock_irqsave(&priv->lock, flags); | |
2863 | ||
2864 | for (i = 0; i < AC_NUM; i++) { | |
2865 | txq = &priv->txq[i]; | |
2866 | q = &txq->q; | |
2867 | avail = iwl_queue_space(q); | |
2868 | ||
2869 | stats[i].len = q->n_window - avail; | |
2870 | stats[i].limit = q->n_window - q->high_mark; | |
2871 | stats[i].count = q->n_window; | |
2872 | ||
2873 | } | |
2874 | spin_unlock_irqrestore(&priv->lock, flags); | |
2875 | ||
2876 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2877 | ||
2878 | return 0; | |
2879 | } | |
2880 | EXPORT_SYMBOL(iwl_mac_get_tx_stats); | |
2881 | ||
bd564261 AK |
2882 | void iwl_mac_reset_tsf(struct ieee80211_hw *hw) |
2883 | { | |
2884 | struct iwl_priv *priv = hw->priv; | |
2885 | unsigned long flags; | |
2886 | ||
2887 | mutex_lock(&priv->mutex); | |
2888 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
2889 | ||
2890 | spin_lock_irqsave(&priv->lock, flags); | |
2891 | memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info)); | |
2892 | spin_unlock_irqrestore(&priv->lock, flags); | |
2893 | ||
2894 | iwl_reset_qos(priv); | |
2895 | ||
2896 | spin_lock_irqsave(&priv->lock, flags); | |
2897 | priv->assoc_id = 0; | |
2898 | priv->assoc_capability = 0; | |
2899 | priv->assoc_station_added = 0; | |
2900 | ||
2901 | /* new association get rid of ibss beacon skb */ | |
2902 | if (priv->ibss_beacon) | |
2903 | dev_kfree_skb(priv->ibss_beacon); | |
2904 | ||
2905 | priv->ibss_beacon = NULL; | |
2906 | ||
57c4d7b4 | 2907 | priv->beacon_int = priv->vif->bss_conf.beacon_int; |
bd564261 AK |
2908 | priv->timestamp = 0; |
2909 | if ((priv->iw_mode == NL80211_IFTYPE_STATION)) | |
2910 | priv->beacon_int = 0; | |
2911 | ||
2912 | spin_unlock_irqrestore(&priv->lock, flags); | |
2913 | ||
2914 | if (!iwl_is_ready_rf(priv)) { | |
2915 | IWL_DEBUG_MAC80211(priv, "leave - not ready\n"); | |
2916 | mutex_unlock(&priv->mutex); | |
2917 | return; | |
2918 | } | |
2919 | ||
2920 | /* we are restarting association process | |
2921 | * clear RXON_FILTER_ASSOC_MSK bit | |
2922 | */ | |
2923 | if (priv->iw_mode != NL80211_IFTYPE_AP) { | |
2924 | iwl_scan_cancel_timeout(priv, 100); | |
2925 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
2926 | iwlcore_commit_rxon(priv); | |
2927 | } | |
2928 | ||
bd564261 | 2929 | if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { |
bd564261 AK |
2930 | IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n"); |
2931 | mutex_unlock(&priv->mutex); | |
2932 | return; | |
2933 | } | |
2934 | ||
2935 | iwl_set_rate(priv); | |
2936 | ||
2937 | mutex_unlock(&priv->mutex); | |
2938 | ||
2939 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
2940 | } | |
2941 | EXPORT_SYMBOL(iwl_mac_reset_tsf); | |
2942 | ||
20594eb0 WYG |
2943 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
2944 | ||
2945 | #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES) | |
2946 | ||
2947 | void iwl_reset_traffic_log(struct iwl_priv *priv) | |
2948 | { | |
2949 | priv->tx_traffic_idx = 0; | |
2950 | priv->rx_traffic_idx = 0; | |
2951 | if (priv->tx_traffic) | |
2952 | memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); | |
2953 | if (priv->rx_traffic) | |
2954 | memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); | |
2955 | } | |
2956 | ||
2957 | int iwl_alloc_traffic_mem(struct iwl_priv *priv) | |
2958 | { | |
2959 | u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE; | |
2960 | ||
2961 | if (iwl_debug_level & IWL_DL_TX) { | |
2962 | if (!priv->tx_traffic) { | |
2963 | priv->tx_traffic = | |
2964 | kzalloc(traffic_size, GFP_KERNEL); | |
2965 | if (!priv->tx_traffic) | |
2966 | return -ENOMEM; | |
2967 | } | |
2968 | } | |
2969 | if (iwl_debug_level & IWL_DL_RX) { | |
2970 | if (!priv->rx_traffic) { | |
2971 | priv->rx_traffic = | |
2972 | kzalloc(traffic_size, GFP_KERNEL); | |
2973 | if (!priv->rx_traffic) | |
2974 | return -ENOMEM; | |
2975 | } | |
2976 | } | |
2977 | iwl_reset_traffic_log(priv); | |
2978 | return 0; | |
2979 | } | |
2980 | EXPORT_SYMBOL(iwl_alloc_traffic_mem); | |
2981 | ||
2982 | void iwl_free_traffic_mem(struct iwl_priv *priv) | |
2983 | { | |
2984 | kfree(priv->tx_traffic); | |
2985 | priv->tx_traffic = NULL; | |
2986 | ||
2987 | kfree(priv->rx_traffic); | |
2988 | priv->rx_traffic = NULL; | |
2989 | } | |
2990 | EXPORT_SYMBOL(iwl_free_traffic_mem); | |
2991 | ||
2992 | void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv, | |
2993 | u16 length, struct ieee80211_hdr *header) | |
2994 | { | |
2995 | __le16 fc; | |
2996 | u16 len; | |
2997 | ||
2998 | if (likely(!(iwl_debug_level & IWL_DL_TX))) | |
2999 | return; | |
3000 | ||
3001 | if (!priv->tx_traffic) | |
3002 | return; | |
3003 | ||
3004 | fc = header->frame_control; | |
3005 | if (ieee80211_is_data(fc)) { | |
3006 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) | |
3007 | ? IWL_TRAFFIC_ENTRY_SIZE : length; | |
3008 | memcpy((priv->tx_traffic + | |
3009 | (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), | |
3010 | header, len); | |
3011 | priv->tx_traffic_idx = | |
3012 | (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; | |
3013 | } | |
3014 | } | |
3015 | EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame); | |
3016 | ||
3017 | void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv, | |
3018 | u16 length, struct ieee80211_hdr *header) | |
3019 | { | |
3020 | __le16 fc; | |
3021 | u16 len; | |
3022 | ||
3023 | if (likely(!(iwl_debug_level & IWL_DL_RX))) | |
3024 | return; | |
3025 | ||
3026 | if (!priv->rx_traffic) | |
3027 | return; | |
3028 | ||
3029 | fc = header->frame_control; | |
3030 | if (ieee80211_is_data(fc)) { | |
3031 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) | |
3032 | ? IWL_TRAFFIC_ENTRY_SIZE : length; | |
3033 | memcpy((priv->rx_traffic + | |
3034 | (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), | |
3035 | header, len); | |
3036 | priv->rx_traffic_idx = | |
3037 | (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; | |
3038 | } | |
3039 | } | |
3040 | EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame); | |
22fdf3c9 WYG |
3041 | |
3042 | const char *get_mgmt_string(int cmd) | |
3043 | { | |
3044 | switch (cmd) { | |
3045 | IWL_CMD(MANAGEMENT_ASSOC_REQ); | |
3046 | IWL_CMD(MANAGEMENT_ASSOC_RESP); | |
3047 | IWL_CMD(MANAGEMENT_REASSOC_REQ); | |
3048 | IWL_CMD(MANAGEMENT_REASSOC_RESP); | |
3049 | IWL_CMD(MANAGEMENT_PROBE_REQ); | |
3050 | IWL_CMD(MANAGEMENT_PROBE_RESP); | |
3051 | IWL_CMD(MANAGEMENT_BEACON); | |
3052 | IWL_CMD(MANAGEMENT_ATIM); | |
3053 | IWL_CMD(MANAGEMENT_DISASSOC); | |
3054 | IWL_CMD(MANAGEMENT_AUTH); | |
3055 | IWL_CMD(MANAGEMENT_DEAUTH); | |
3056 | IWL_CMD(MANAGEMENT_ACTION); | |
3057 | default: | |
3058 | return "UNKNOWN"; | |
3059 | ||
3060 | } | |
3061 | } | |
3062 | ||
3063 | const char *get_ctrl_string(int cmd) | |
3064 | { | |
3065 | switch (cmd) { | |
3066 | IWL_CMD(CONTROL_BACK_REQ); | |
3067 | IWL_CMD(CONTROL_BACK); | |
3068 | IWL_CMD(CONTROL_PSPOLL); | |
3069 | IWL_CMD(CONTROL_RTS); | |
3070 | IWL_CMD(CONTROL_CTS); | |
3071 | IWL_CMD(CONTROL_ACK); | |
3072 | IWL_CMD(CONTROL_CFEND); | |
3073 | IWL_CMD(CONTROL_CFENDACK); | |
3074 | default: | |
3075 | return "UNKNOWN"; | |
3076 | ||
3077 | } | |
3078 | } | |
3079 | ||
3080 | void iwl_clear_tx_stats(struct iwl_priv *priv) | |
3081 | { | |
3082 | memset(&priv->tx_stats, 0, sizeof(struct traffic_stats)); | |
3083 | ||
3084 | } | |
3085 | ||
3086 | void iwl_clear_rx_stats(struct iwl_priv *priv) | |
3087 | { | |
3088 | memset(&priv->rx_stats, 0, sizeof(struct traffic_stats)); | |
3089 | } | |
3090 | ||
3091 | /* | |
3092 | * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will | |
3093 | * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass. | |
3094 | * Use debugFs to display the rx/rx_statistics | |
3095 | * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL | |
3096 | * information will be recorded, but DATA pkt still will be recorded | |
3097 | * for the reason of iwl_led.c need to control the led blinking based on | |
3098 | * number of tx and rx data. | |
3099 | * | |
3100 | */ | |
3101 | void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len) | |
3102 | { | |
3103 | struct traffic_stats *stats; | |
3104 | ||
3105 | if (is_tx) | |
3106 | stats = &priv->tx_stats; | |
3107 | else | |
3108 | stats = &priv->rx_stats; | |
3109 | ||
3110 | if (ieee80211_is_mgmt(fc)) { | |
3111 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
3112 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
3113 | stats->mgmt[MANAGEMENT_ASSOC_REQ]++; | |
3114 | break; | |
3115 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP): | |
3116 | stats->mgmt[MANAGEMENT_ASSOC_RESP]++; | |
3117 | break; | |
3118 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
3119 | stats->mgmt[MANAGEMENT_REASSOC_REQ]++; | |
3120 | break; | |
3121 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP): | |
3122 | stats->mgmt[MANAGEMENT_REASSOC_RESP]++; | |
3123 | break; | |
3124 | case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ): | |
3125 | stats->mgmt[MANAGEMENT_PROBE_REQ]++; | |
3126 | break; | |
3127 | case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP): | |
3128 | stats->mgmt[MANAGEMENT_PROBE_RESP]++; | |
3129 | break; | |
3130 | case cpu_to_le16(IEEE80211_STYPE_BEACON): | |
3131 | stats->mgmt[MANAGEMENT_BEACON]++; | |
3132 | break; | |
3133 | case cpu_to_le16(IEEE80211_STYPE_ATIM): | |
3134 | stats->mgmt[MANAGEMENT_ATIM]++; | |
3135 | break; | |
3136 | case cpu_to_le16(IEEE80211_STYPE_DISASSOC): | |
3137 | stats->mgmt[MANAGEMENT_DISASSOC]++; | |
3138 | break; | |
3139 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
3140 | stats->mgmt[MANAGEMENT_AUTH]++; | |
3141 | break; | |
3142 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
3143 | stats->mgmt[MANAGEMENT_DEAUTH]++; | |
3144 | break; | |
3145 | case cpu_to_le16(IEEE80211_STYPE_ACTION): | |
3146 | stats->mgmt[MANAGEMENT_ACTION]++; | |
3147 | break; | |
3148 | } | |
3149 | } else if (ieee80211_is_ctl(fc)) { | |
3150 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
3151 | case cpu_to_le16(IEEE80211_STYPE_BACK_REQ): | |
3152 | stats->ctrl[CONTROL_BACK_REQ]++; | |
3153 | break; | |
3154 | case cpu_to_le16(IEEE80211_STYPE_BACK): | |
3155 | stats->ctrl[CONTROL_BACK]++; | |
3156 | break; | |
3157 | case cpu_to_le16(IEEE80211_STYPE_PSPOLL): | |
3158 | stats->ctrl[CONTROL_PSPOLL]++; | |
3159 | break; | |
3160 | case cpu_to_le16(IEEE80211_STYPE_RTS): | |
3161 | stats->ctrl[CONTROL_RTS]++; | |
3162 | break; | |
3163 | case cpu_to_le16(IEEE80211_STYPE_CTS): | |
3164 | stats->ctrl[CONTROL_CTS]++; | |
3165 | break; | |
3166 | case cpu_to_le16(IEEE80211_STYPE_ACK): | |
3167 | stats->ctrl[CONTROL_ACK]++; | |
3168 | break; | |
3169 | case cpu_to_le16(IEEE80211_STYPE_CFEND): | |
3170 | stats->ctrl[CONTROL_CFEND]++; | |
3171 | break; | |
3172 | case cpu_to_le16(IEEE80211_STYPE_CFENDACK): | |
3173 | stats->ctrl[CONTROL_CFENDACK]++; | |
3174 | break; | |
3175 | } | |
3176 | } else { | |
3177 | /* data */ | |
3178 | stats->data_cnt++; | |
3179 | stats->data_bytes += len; | |
3180 | } | |
3181 | } | |
3182 | EXPORT_SYMBOL(iwl_update_stats); | |
20594eb0 WYG |
3183 | #endif |
3184 | ||
6da3a13e WYG |
3185 | #ifdef CONFIG_PM |
3186 | ||
3187 | int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
3188 | { | |
3189 | struct iwl_priv *priv = pci_get_drvdata(pdev); | |
3190 | ||
3191 | /* | |
3192 | * This function is called when system goes into suspend state | |
3193 | * mac80211 will call iwl_mac_stop() from the mac80211 suspend function | |
3194 | * first but since iwl_mac_stop() has no knowledge of who the caller is, | |
3195 | * it will not call apm_ops.stop() to stop the DMA operation. | |
3196 | * Calling apm_ops.stop here to make sure we stop the DMA. | |
3197 | */ | |
3198 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
3199 | ||
3200 | pci_save_state(pdev); | |
3201 | pci_disable_device(pdev); | |
3202 | pci_set_power_state(pdev, PCI_D3hot); | |
3203 | ||
3204 | return 0; | |
3205 | } | |
3206 | EXPORT_SYMBOL(iwl_pci_suspend); | |
3207 | ||
3208 | int iwl_pci_resume(struct pci_dev *pdev) | |
3209 | { | |
3210 | struct iwl_priv *priv = pci_get_drvdata(pdev); | |
3211 | int ret; | |
3212 | ||
3213 | pci_set_power_state(pdev, PCI_D0); | |
3214 | ret = pci_enable_device(pdev); | |
3215 | if (ret) | |
3216 | return ret; | |
3217 | pci_restore_state(pdev); | |
3218 | iwl_enable_interrupts(priv); | |
3219 | ||
3220 | return 0; | |
3221 | } | |
3222 | EXPORT_SYMBOL(iwl_pci_resume); | |
3223 | ||
3224 | #endif /* CONFIG_PM */ |