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df48c323 | 1 | /****************************************************************************** |
df48c323 TW |
2 | * |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
5 | * Copyright(c) 2008 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
25 | * Tomas Winkler <tomas.winkler@intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | *****************************************************************************/ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/version.h> | |
1d0a082d | 32 | #include <net/mac80211.h> |
df48c323 | 33 | |
712b6cf5 | 34 | struct iwl_priv; /* FIXME: remove */ |
0a6857e7 | 35 | #include "iwl-debug.h" |
6bc913bd | 36 | #include "iwl-eeprom.h" |
3e0d4cb1 | 37 | #include "iwl-dev.h" /* FIXME: remove */ |
df48c323 | 38 | #include "iwl-core.h" |
b661c819 | 39 | #include "iwl-io.h" |
ad97edd2 | 40 | #include "iwl-rfkill.h" |
5da4b55f | 41 | #include "iwl-power.h" |
df48c323 | 42 | |
1d0a082d | 43 | |
df48c323 TW |
44 | MODULE_DESCRIPTION("iwl core"); |
45 | MODULE_VERSION(IWLWIFI_VERSION); | |
46 | MODULE_AUTHOR(DRV_COPYRIGHT); | |
712b6cf5 | 47 | MODULE_LICENSE("GPL"); |
df48c323 | 48 | |
c7de35cd RR |
49 | #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \ |
50 | [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \ | |
51 | IWL_RATE_SISO_##s##M_PLCP, \ | |
52 | IWL_RATE_MIMO2_##s##M_PLCP,\ | |
53 | IWL_RATE_MIMO3_##s##M_PLCP,\ | |
54 | IWL_RATE_##r##M_IEEE, \ | |
55 | IWL_RATE_##ip##M_INDEX, \ | |
56 | IWL_RATE_##in##M_INDEX, \ | |
57 | IWL_RATE_##rp##M_INDEX, \ | |
58 | IWL_RATE_##rn##M_INDEX, \ | |
59 | IWL_RATE_##pp##M_INDEX, \ | |
60 | IWL_RATE_##np##M_INDEX } | |
61 | ||
62 | /* | |
63 | * Parameter order: | |
64 | * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate | |
65 | * | |
66 | * If there isn't a valid next or previous rate then INV is used which | |
67 | * maps to IWL_RATE_INVALID | |
68 | * | |
69 | */ | |
1826dcc0 | 70 | const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = { |
c7de35cd RR |
71 | IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */ |
72 | IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */ | |
73 | IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */ | |
74 | IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */ | |
75 | IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */ | |
76 | IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */ | |
77 | IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */ | |
78 | IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */ | |
79 | IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */ | |
80 | IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */ | |
81 | IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */ | |
82 | IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */ | |
83 | IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */ | |
84 | /* FIXME:RS: ^^ should be INV (legacy) */ | |
85 | }; | |
1826dcc0 | 86 | EXPORT_SYMBOL(iwl_rates); |
c7de35cd | 87 | |
e7d326ac TW |
88 | /** |
89 | * translate ucode response to mac80211 tx status control values | |
90 | */ | |
91 | void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags, | |
92 | struct ieee80211_tx_info *control) | |
93 | { | |
94 | int rate_index; | |
95 | ||
96 | control->antenna_sel_tx = | |
97 | ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS); | |
98 | if (rate_n_flags & RATE_MCS_HT_MSK) | |
99 | control->flags |= IEEE80211_TX_CTL_OFDM_HT; | |
100 | if (rate_n_flags & RATE_MCS_GF_MSK) | |
101 | control->flags |= IEEE80211_TX_CTL_GREEN_FIELD; | |
102 | if (rate_n_flags & RATE_MCS_FAT_MSK) | |
103 | control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH; | |
104 | if (rate_n_flags & RATE_MCS_DUP_MSK) | |
105 | control->flags |= IEEE80211_TX_CTL_DUP_DATA; | |
106 | if (rate_n_flags & RATE_MCS_SGI_MSK) | |
107 | control->flags |= IEEE80211_TX_CTL_SHORT_GI; | |
108 | rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags); | |
109 | if (control->band == IEEE80211_BAND_5GHZ) | |
110 | rate_index -= IWL_FIRST_OFDM_RATE; | |
111 | control->tx_rate_idx = rate_index; | |
112 | } | |
113 | EXPORT_SYMBOL(iwl_hwrate_to_tx_control); | |
114 | ||
115 | int iwl_hwrate_to_plcp_idx(u32 rate_n_flags) | |
116 | { | |
117 | int idx = 0; | |
118 | ||
119 | /* HT rate format */ | |
120 | if (rate_n_flags & RATE_MCS_HT_MSK) { | |
121 | idx = (rate_n_flags & 0xff); | |
122 | ||
123 | if (idx >= IWL_RATE_MIMO2_6M_PLCP) | |
124 | idx = idx - IWL_RATE_MIMO2_6M_PLCP; | |
125 | ||
126 | idx += IWL_FIRST_OFDM_RATE; | |
127 | /* skip 9M not supported in ht*/ | |
128 | if (idx >= IWL_RATE_9M_INDEX) | |
129 | idx += 1; | |
130 | if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE)) | |
131 | return idx; | |
132 | ||
133 | /* legacy rate format, search for match in table */ | |
134 | } else { | |
135 | for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++) | |
136 | if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF)) | |
137 | return idx; | |
138 | } | |
139 | ||
140 | return -1; | |
141 | } | |
142 | EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx); | |
143 | ||
144 | ||
57bd1bea TW |
145 | |
146 | const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; | |
147 | EXPORT_SYMBOL(iwl_bcast_addr); | |
148 | ||
149 | ||
1d0a082d AK |
150 | /* This function both allocates and initializes hw and priv. */ |
151 | struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg, | |
152 | struct ieee80211_ops *hw_ops) | |
153 | { | |
154 | struct iwl_priv *priv; | |
155 | ||
156 | /* mac80211 allocates memory for this device instance, including | |
157 | * space for this driver's private structure */ | |
158 | struct ieee80211_hw *hw = | |
159 | ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops); | |
160 | if (hw == NULL) { | |
161 | IWL_ERROR("Can not allocate network device\n"); | |
162 | goto out; | |
163 | } | |
164 | ||
165 | priv = hw->priv; | |
166 | priv->hw = hw; | |
167 | ||
168 | out: | |
169 | return hw; | |
170 | } | |
171 | EXPORT_SYMBOL(iwl_alloc_all); | |
172 | ||
b661c819 TW |
173 | void iwl_hw_detect(struct iwl_priv *priv) |
174 | { | |
175 | priv->hw_rev = _iwl_read32(priv, CSR_HW_REV); | |
176 | priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG); | |
177 | pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id); | |
178 | } | |
179 | EXPORT_SYMBOL(iwl_hw_detect); | |
180 | ||
1053d35f RR |
181 | /* Tell nic where to find the "keep warm" buffer */ |
182 | int iwl_kw_init(struct iwl_priv *priv) | |
183 | { | |
184 | unsigned long flags; | |
185 | int ret; | |
186 | ||
187 | spin_lock_irqsave(&priv->lock, flags); | |
188 | ret = iwl_grab_nic_access(priv); | |
189 | if (ret) | |
190 | goto out; | |
191 | ||
192 | iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, | |
193 | priv->kw.dma_addr >> 4); | |
194 | iwl_release_nic_access(priv); | |
195 | out: | |
196 | spin_unlock_irqrestore(&priv->lock, flags); | |
197 | return ret; | |
198 | } | |
199 | ||
200 | int iwl_kw_alloc(struct iwl_priv *priv) | |
201 | { | |
202 | struct pci_dev *dev = priv->pci_dev; | |
16466903 | 203 | struct iwl_kw *kw = &priv->kw; |
1053d35f | 204 | |
16466903 | 205 | kw->size = IWL_KW_SIZE; |
1053d35f RR |
206 | kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr); |
207 | if (!kw->v_addr) | |
208 | return -ENOMEM; | |
209 | ||
210 | return 0; | |
211 | } | |
212 | ||
213 | /** | |
214 | * iwl_kw_free - Free the "keep warm" buffer | |
215 | */ | |
216 | void iwl_kw_free(struct iwl_priv *priv) | |
217 | { | |
218 | struct pci_dev *dev = priv->pci_dev; | |
16466903 | 219 | struct iwl_kw *kw = &priv->kw; |
1053d35f RR |
220 | |
221 | if (kw->v_addr) { | |
222 | pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr); | |
223 | memset(kw, 0, sizeof(*kw)); | |
224 | } | |
225 | } | |
226 | ||
227 | int iwl_hw_nic_init(struct iwl_priv *priv) | |
228 | { | |
229 | unsigned long flags; | |
230 | struct iwl_rx_queue *rxq = &priv->rxq; | |
231 | int ret; | |
232 | ||
233 | /* nic_init */ | |
1053d35f | 234 | spin_lock_irqsave(&priv->lock, flags); |
1b73af82 | 235 | priv->cfg->ops->lib->apm_ops.init(priv); |
1053d35f RR |
236 | iwl_write32(priv, CSR_INT_COALESCING, 512 / 32); |
237 | spin_unlock_irqrestore(&priv->lock, flags); | |
238 | ||
239 | ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN); | |
240 | ||
241 | priv->cfg->ops->lib->apm_ops.config(priv); | |
242 | ||
243 | /* Allocate the RX queue, or reset if it is already allocated */ | |
244 | if (!rxq->bd) { | |
245 | ret = iwl_rx_queue_alloc(priv); | |
246 | if (ret) { | |
247 | IWL_ERROR("Unable to initialize Rx queue\n"); | |
248 | return -ENOMEM; | |
249 | } | |
250 | } else | |
251 | iwl_rx_queue_reset(priv, rxq); | |
252 | ||
253 | iwl_rx_replenish(priv); | |
254 | ||
255 | iwl_rx_init(priv, rxq); | |
256 | ||
257 | spin_lock_irqsave(&priv->lock, flags); | |
258 | ||
259 | rxq->need_update = 1; | |
260 | iwl_rx_queue_update_write_ptr(priv, rxq); | |
261 | ||
262 | spin_unlock_irqrestore(&priv->lock, flags); | |
263 | ||
264 | /* Allocate and init all Tx and Command queues */ | |
265 | ret = iwl_txq_ctx_reset(priv); | |
266 | if (ret) | |
267 | return ret; | |
268 | ||
269 | set_bit(STATUS_INIT, &priv->status); | |
270 | ||
271 | return 0; | |
272 | } | |
273 | EXPORT_SYMBOL(iwl_hw_nic_init); | |
274 | ||
bf85ea4f AK |
275 | /** |
276 | * iwlcore_clear_stations_table - Clear the driver's station table | |
277 | * | |
278 | * NOTE: This does not clear or otherwise alter the device's station table. | |
279 | */ | |
280 | void iwlcore_clear_stations_table(struct iwl_priv *priv) | |
281 | { | |
282 | unsigned long flags; | |
283 | ||
284 | spin_lock_irqsave(&priv->sta_lock, flags); | |
285 | ||
286 | priv->num_stations = 0; | |
287 | memset(priv->stations, 0, sizeof(priv->stations)); | |
288 | ||
289 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
290 | } | |
291 | EXPORT_SYMBOL(iwlcore_clear_stations_table); | |
292 | ||
c7de35cd | 293 | void iwl_reset_qos(struct iwl_priv *priv) |
bf85ea4f AK |
294 | { |
295 | u16 cw_min = 15; | |
296 | u16 cw_max = 1023; | |
297 | u8 aifs = 2; | |
298 | u8 is_legacy = 0; | |
299 | unsigned long flags; | |
300 | int i; | |
301 | ||
302 | spin_lock_irqsave(&priv->lock, flags); | |
303 | priv->qos_data.qos_active = 0; | |
304 | ||
305 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) { | |
306 | if (priv->qos_data.qos_enable) | |
307 | priv->qos_data.qos_active = 1; | |
308 | if (!(priv->active_rate & 0xfff0)) { | |
309 | cw_min = 31; | |
310 | is_legacy = 1; | |
311 | } | |
312 | } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
313 | if (priv->qos_data.qos_enable) | |
314 | priv->qos_data.qos_active = 1; | |
315 | } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) { | |
316 | cw_min = 31; | |
317 | is_legacy = 1; | |
318 | } | |
319 | ||
320 | if (priv->qos_data.qos_active) | |
321 | aifs = 3; | |
322 | ||
323 | priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min); | |
324 | priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max); | |
325 | priv->qos_data.def_qos_parm.ac[0].aifsn = aifs; | |
326 | priv->qos_data.def_qos_parm.ac[0].edca_txop = 0; | |
327 | priv->qos_data.def_qos_parm.ac[0].reserved1 = 0; | |
328 | ||
329 | if (priv->qos_data.qos_active) { | |
330 | i = 1; | |
331 | priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min); | |
332 | priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max); | |
333 | priv->qos_data.def_qos_parm.ac[i].aifsn = 7; | |
334 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
335 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
336 | ||
337 | i = 2; | |
338 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
339 | cpu_to_le16((cw_min + 1) / 2 - 1); | |
340 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
341 | cpu_to_le16(cw_max); | |
342 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; | |
343 | if (is_legacy) | |
344 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
345 | cpu_to_le16(6016); | |
346 | else | |
347 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
348 | cpu_to_le16(3008); | |
349 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
350 | ||
351 | i = 3; | |
352 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
353 | cpu_to_le16((cw_min + 1) / 4 - 1); | |
354 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
355 | cpu_to_le16((cw_max + 1) / 2 - 1); | |
356 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; | |
357 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
358 | if (is_legacy) | |
359 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
360 | cpu_to_le16(3264); | |
361 | else | |
362 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
363 | cpu_to_le16(1504); | |
364 | } else { | |
365 | for (i = 1; i < 4; i++) { | |
366 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
367 | cpu_to_le16(cw_min); | |
368 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
369 | cpu_to_le16(cw_max); | |
370 | priv->qos_data.def_qos_parm.ac[i].aifsn = aifs; | |
371 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
372 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
373 | } | |
374 | } | |
375 | IWL_DEBUG_QOS("set QoS to default \n"); | |
376 | ||
377 | spin_unlock_irqrestore(&priv->lock, flags); | |
378 | } | |
c7de35cd RR |
379 | EXPORT_SYMBOL(iwl_reset_qos); |
380 | ||
39130df3 RR |
381 | #define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */ |
382 | #define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */ | |
c7de35cd RR |
383 | static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv, |
384 | struct ieee80211_ht_info *ht_info, | |
385 | enum ieee80211_band band) | |
386 | { | |
39130df3 RR |
387 | u16 max_bit_rate = 0; |
388 | u8 rx_chains_num = priv->hw_params.rx_chains_num; | |
389 | u8 tx_chains_num = priv->hw_params.tx_chains_num; | |
390 | ||
c7de35cd RR |
391 | ht_info->cap = 0; |
392 | memset(ht_info->supp_mcs_set, 0, 16); | |
393 | ||
394 | ht_info->ht_supported = 1; | |
395 | ||
39130df3 RR |
396 | ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD; |
397 | ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20; | |
398 | ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS & | |
399 | (IWL_MIMO_PS_NONE << 2)); | |
400 | ||
401 | max_bit_rate = MAX_BIT_RATE_20_MHZ; | |
c7de35cd RR |
402 | if (priv->hw_params.fat_channel & BIT(band)) { |
403 | ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH; | |
404 | ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40; | |
405 | ht_info->supp_mcs_set[4] = 0x01; | |
39130df3 | 406 | max_bit_rate = MAX_BIT_RATE_40_MHZ; |
c7de35cd | 407 | } |
c7de35cd RR |
408 | |
409 | if (priv->cfg->mod_params->amsdu_size_8K) | |
410 | ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU; | |
411 | ||
412 | ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF; | |
413 | ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF; | |
414 | ||
415 | ht_info->supp_mcs_set[0] = 0xFF; | |
39130df3 | 416 | if (rx_chains_num >= 2) |
c7de35cd | 417 | ht_info->supp_mcs_set[1] = 0xFF; |
39130df3 | 418 | if (rx_chains_num >= 3) |
c7de35cd | 419 | ht_info->supp_mcs_set[2] = 0xFF; |
39130df3 RR |
420 | |
421 | /* Highest supported Rx data rate */ | |
422 | max_bit_rate *= rx_chains_num; | |
423 | ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF); | |
424 | ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8); | |
425 | ||
426 | /* Tx MCS capabilities */ | |
427 | ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED; | |
428 | if (tx_chains_num != rx_chains_num) { | |
429 | ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF; | |
430 | ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2); | |
431 | } | |
c7de35cd | 432 | } |
c7de35cd RR |
433 | |
434 | static void iwlcore_init_hw_rates(struct iwl_priv *priv, | |
435 | struct ieee80211_rate *rates) | |
436 | { | |
437 | int i; | |
438 | ||
439 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
1826dcc0 | 440 | rates[i].bitrate = iwl_rates[i].ieee * 5; |
c7de35cd RR |
441 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ |
442 | rates[i].hw_value_short = i; | |
443 | rates[i].flags = 0; | |
444 | if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { | |
445 | /* | |
446 | * If CCK != 1M then set short preamble rate flag. | |
447 | */ | |
448 | rates[i].flags |= | |
1826dcc0 | 449 | (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ? |
c7de35cd RR |
450 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
451 | } | |
452 | } | |
453 | } | |
454 | ||
455 | /** | |
456 | * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom | |
457 | */ | |
458 | static int iwlcore_init_geos(struct iwl_priv *priv) | |
459 | { | |
460 | struct iwl_channel_info *ch; | |
461 | struct ieee80211_supported_band *sband; | |
462 | struct ieee80211_channel *channels; | |
463 | struct ieee80211_channel *geo_ch; | |
464 | struct ieee80211_rate *rates; | |
465 | int i = 0; | |
466 | ||
467 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || | |
468 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
469 | IWL_DEBUG_INFO("Geography modes already initialized.\n"); | |
470 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
471 | return 0; | |
472 | } | |
473 | ||
474 | channels = kzalloc(sizeof(struct ieee80211_channel) * | |
475 | priv->channel_count, GFP_KERNEL); | |
476 | if (!channels) | |
477 | return -ENOMEM; | |
478 | ||
479 | rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)), | |
480 | GFP_KERNEL); | |
481 | if (!rates) { | |
482 | kfree(channels); | |
483 | return -ENOMEM; | |
484 | } | |
485 | ||
486 | /* 5.2GHz channels start after the 2.4GHz channels */ | |
487 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
488 | sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)]; | |
489 | /* just OFDM */ | |
490 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
491 | sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE; | |
492 | ||
493 | iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ); | |
494 | ||
495 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
496 | sband->channels = channels; | |
497 | /* OFDM & CCK */ | |
498 | sband->bitrates = rates; | |
499 | sband->n_bitrates = IWL_RATE_COUNT; | |
500 | ||
501 | iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ); | |
502 | ||
503 | priv->ieee_channels = channels; | |
504 | priv->ieee_rates = rates; | |
505 | ||
506 | iwlcore_init_hw_rates(priv, rates); | |
507 | ||
508 | for (i = 0; i < priv->channel_count; i++) { | |
509 | ch = &priv->channel_info[i]; | |
510 | ||
511 | /* FIXME: might be removed if scan is OK */ | |
512 | if (!is_channel_valid(ch)) | |
513 | continue; | |
514 | ||
515 | if (is_channel_a_band(ch)) | |
516 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; | |
517 | else | |
518 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
519 | ||
520 | geo_ch = &sband->channels[sband->n_channels++]; | |
521 | ||
522 | geo_ch->center_freq = | |
523 | ieee80211_channel_to_frequency(ch->channel); | |
524 | geo_ch->max_power = ch->max_power_avg; | |
525 | geo_ch->max_antenna_gain = 0xff; | |
526 | geo_ch->hw_value = ch->channel; | |
527 | ||
528 | if (is_channel_valid(ch)) { | |
529 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) | |
530 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
531 | ||
532 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) | |
533 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
534 | ||
535 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
536 | geo_ch->flags |= IEEE80211_CHAN_RADAR; | |
537 | ||
963f5517 | 538 | geo_ch->flags |= ch->fat_extension_channel; |
4d38c2e8 | 539 | |
630fe9b6 TW |
540 | if (ch->max_power_avg > priv->tx_power_channel_lmt) |
541 | priv->tx_power_channel_lmt = ch->max_power_avg; | |
c7de35cd RR |
542 | } else { |
543 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; | |
544 | } | |
545 | ||
546 | /* Save flags for reg domain usage */ | |
547 | geo_ch->orig_flags = geo_ch->flags; | |
548 | ||
963f5517 | 549 | IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", |
c7de35cd RR |
550 | ch->channel, geo_ch->center_freq, |
551 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
552 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
553 | "restricted" : "valid", | |
554 | geo_ch->flags); | |
555 | } | |
556 | ||
557 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && | |
558 | priv->cfg->sku & IWL_SKU_A) { | |
559 | printk(KERN_INFO DRV_NAME | |
560 | ": Incorrectly detected BG card as ABG. Please send " | |
561 | "your PCI ID 0x%04X:0x%04X to maintainer.\n", | |
562 | priv->pci_dev->device, priv->pci_dev->subsystem_device); | |
563 | priv->cfg->sku &= ~IWL_SKU_A; | |
564 | } | |
565 | ||
566 | printk(KERN_INFO DRV_NAME | |
567 | ": Tunable channels: %d 802.11bg, %d 802.11a channels\n", | |
568 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, | |
569 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
570 | ||
c7de35cd RR |
571 | |
572 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
573 | ||
574 | return 0; | |
575 | } | |
576 | ||
577 | /* | |
578 | * iwlcore_free_geos - undo allocations in iwlcore_init_geos | |
579 | */ | |
6ba87956 | 580 | static void iwlcore_free_geos(struct iwl_priv *priv) |
c7de35cd RR |
581 | { |
582 | kfree(priv->ieee_channels); | |
583 | kfree(priv->ieee_rates); | |
584 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
585 | } | |
c7de35cd | 586 | |
c7de35cd RR |
587 | static u8 is_single_rx_stream(struct iwl_priv *priv) |
588 | { | |
589 | return !priv->current_ht_config.is_ht || | |
590 | ((priv->current_ht_config.supp_mcs_set[1] == 0) && | |
591 | (priv->current_ht_config.supp_mcs_set[2] == 0)) || | |
592 | priv->ps_mode == IWL_MIMO_PS_STATIC; | |
593 | } | |
963f5517 | 594 | |
47c5196e TW |
595 | static u8 iwl_is_channel_extension(struct iwl_priv *priv, |
596 | enum ieee80211_band band, | |
597 | u16 channel, u8 extension_chan_offset) | |
598 | { | |
599 | const struct iwl_channel_info *ch_info; | |
600 | ||
601 | ch_info = iwl_get_channel_info(priv, band, channel); | |
602 | if (!is_channel_valid(ch_info)) | |
603 | return 0; | |
604 | ||
963f5517 EG |
605 | if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) |
606 | return !(ch_info->fat_extension_channel & | |
607 | IEEE80211_CHAN_NO_FAT_ABOVE); | |
608 | else if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) | |
609 | return !(ch_info->fat_extension_channel & | |
610 | IEEE80211_CHAN_NO_FAT_BELOW); | |
47c5196e TW |
611 | |
612 | return 0; | |
613 | } | |
614 | ||
615 | u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv, | |
616 | struct ieee80211_ht_info *sta_ht_inf) | |
617 | { | |
618 | struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config; | |
619 | ||
620 | if ((!iwl_ht_conf->is_ht) || | |
621 | (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) || | |
963f5517 | 622 | (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE)) |
47c5196e TW |
623 | return 0; |
624 | ||
625 | if (sta_ht_inf) { | |
626 | if ((!sta_ht_inf->ht_supported) || | |
627 | (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH))) | |
628 | return 0; | |
629 | } | |
630 | ||
631 | return iwl_is_channel_extension(priv, priv->band, | |
632 | iwl_ht_conf->control_channel, | |
633 | iwl_ht_conf->extension_chan_offset); | |
634 | } | |
635 | EXPORT_SYMBOL(iwl_is_fat_tx_allowed); | |
636 | ||
637 | void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info) | |
638 | { | |
c1adf9fb | 639 | struct iwl_rxon_cmd *rxon = &priv->staging_rxon; |
47c5196e TW |
640 | u32 val; |
641 | ||
642 | if (!ht_info->is_ht) | |
643 | return; | |
644 | ||
645 | /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */ | |
646 | if (iwl_is_fat_tx_allowed(priv, NULL)) | |
647 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK; | |
648 | else | |
649 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK | | |
650 | RXON_FLG_CHANNEL_MODE_PURE_40_MSK); | |
651 | ||
652 | if (le16_to_cpu(rxon->channel) != ht_info->control_channel) { | |
653 | IWL_DEBUG_ASSOC("control diff than current %d %d\n", | |
654 | le16_to_cpu(rxon->channel), | |
655 | ht_info->control_channel); | |
47c5196e TW |
656 | return; |
657 | } | |
658 | ||
659 | /* Note: control channel is opposite of extension channel */ | |
660 | switch (ht_info->extension_chan_offset) { | |
963f5517 | 661 | case IEEE80211_HT_IE_CHA_SEC_ABOVE: |
47c5196e TW |
662 | rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); |
663 | break; | |
963f5517 | 664 | case IEEE80211_HT_IE_CHA_SEC_BELOW: |
47c5196e TW |
665 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; |
666 | break; | |
963f5517 | 667 | case IEEE80211_HT_IE_CHA_SEC_NONE: |
47c5196e TW |
668 | default: |
669 | rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK; | |
670 | break; | |
671 | } | |
672 | ||
673 | val = ht_info->ht_protection; | |
674 | ||
675 | rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS); | |
676 | ||
677 | iwl_set_rxon_chain(priv); | |
678 | ||
679 | IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X " | |
680 | "rxon flags 0x%X operation mode :0x%X " | |
681 | "extension channel offset 0x%x " | |
682 | "control chan %d\n", | |
683 | ht_info->supp_mcs_set[0], | |
684 | ht_info->supp_mcs_set[1], | |
685 | ht_info->supp_mcs_set[2], | |
686 | le32_to_cpu(rxon->flags), ht_info->ht_protection, | |
687 | ht_info->extension_chan_offset, | |
688 | ht_info->control_channel); | |
689 | return; | |
690 | } | |
691 | EXPORT_SYMBOL(iwl_set_rxon_ht); | |
692 | ||
c7de35cd RR |
693 | /* |
694 | * Determine how many receiver/antenna chains to use. | |
695 | * More provides better reception via diversity. Fewer saves power. | |
696 | * MIMO (dual stream) requires at least 2, but works better with 3. | |
697 | * This does not determine *which* chains to use, just how many. | |
698 | */ | |
699 | static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv, | |
700 | u8 *idle_state, u8 *rx_state) | |
701 | { | |
702 | u8 is_single = is_single_rx_stream(priv); | |
703 | u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1; | |
704 | ||
705 | /* # of Rx chains to use when expecting MIMO. */ | |
706 | if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC))) | |
707 | *rx_state = 2; | |
708 | else | |
709 | *rx_state = 3; | |
710 | ||
711 | /* # Rx chains when idling and maybe trying to save power */ | |
712 | switch (priv->ps_mode) { | |
713 | case IWL_MIMO_PS_STATIC: | |
714 | case IWL_MIMO_PS_DYNAMIC: | |
715 | *idle_state = (is_cam) ? 2 : 1; | |
716 | break; | |
717 | case IWL_MIMO_PS_NONE: | |
718 | *idle_state = (is_cam) ? *rx_state : 1; | |
719 | break; | |
720 | default: | |
721 | *idle_state = 1; | |
722 | break; | |
723 | } | |
724 | ||
725 | return 0; | |
726 | } | |
727 | ||
728 | /** | |
729 | * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image | |
730 | * | |
731 | * Selects how many and which Rx receivers/antennas/chains to use. | |
732 | * This should not be used for scan command ... it puts data in wrong place. | |
733 | */ | |
734 | void iwl_set_rxon_chain(struct iwl_priv *priv) | |
735 | { | |
736 | u8 is_single = is_single_rx_stream(priv); | |
737 | u8 idle_state, rx_state; | |
738 | ||
739 | priv->staging_rxon.rx_chain = 0; | |
740 | rx_state = idle_state = 3; | |
741 | ||
742 | /* Tell uCode which antennas are actually connected. | |
743 | * Before first association, we assume all antennas are connected. | |
744 | * Just after first association, iwl_chain_noise_calibration() | |
745 | * checks which antennas actually *are* connected. */ | |
746 | priv->staging_rxon.rx_chain |= | |
747 | cpu_to_le16(priv->hw_params.valid_rx_ant << | |
748 | RXON_RX_CHAIN_VALID_POS); | |
749 | ||
750 | /* How many receivers should we use? */ | |
751 | iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state); | |
752 | priv->staging_rxon.rx_chain |= | |
753 | cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS); | |
754 | priv->staging_rxon.rx_chain |= | |
755 | cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS); | |
756 | ||
757 | if (!is_single && (rx_state >= 2) && | |
758 | !test_bit(STATUS_POWER_PMI, &priv->status)) | |
759 | priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK; | |
760 | else | |
761 | priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK; | |
762 | ||
763 | IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain); | |
764 | } | |
765 | EXPORT_SYMBOL(iwl_set_rxon_chain); | |
bf85ea4f AK |
766 | |
767 | /** | |
768 | * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON | |
769 | * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz | |
770 | * @channel: Any channel valid for the requested phymode | |
771 | ||
772 | * In addition to setting the staging RXON, priv->phymode is also set. | |
773 | * | |
774 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields | |
775 | * in the staging RXON flag structure based on the phymode | |
776 | */ | |
c7de35cd | 777 | int iwl_set_rxon_channel(struct iwl_priv *priv, |
bf85ea4f AK |
778 | enum ieee80211_band band, |
779 | u16 channel) | |
780 | { | |
8622e705 | 781 | if (!iwl_get_channel_info(priv, band, channel)) { |
bf85ea4f AK |
782 | IWL_DEBUG_INFO("Could not set channel to %d [%d]\n", |
783 | channel, band); | |
784 | return -EINVAL; | |
785 | } | |
786 | ||
787 | if ((le16_to_cpu(priv->staging_rxon.channel) == channel) && | |
788 | (priv->band == band)) | |
789 | return 0; | |
790 | ||
791 | priv->staging_rxon.channel = cpu_to_le16(channel); | |
792 | if (band == IEEE80211_BAND_5GHZ) | |
793 | priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK; | |
794 | else | |
795 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
796 | ||
797 | priv->band = band; | |
798 | ||
799 | IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band); | |
800 | ||
801 | return 0; | |
802 | } | |
c7de35cd | 803 | EXPORT_SYMBOL(iwl_set_rxon_channel); |
bf85ea4f | 804 | |
6ba87956 | 805 | int iwl_setup_mac(struct iwl_priv *priv) |
bf85ea4f | 806 | { |
6ba87956 | 807 | int ret; |
bf85ea4f AK |
808 | struct ieee80211_hw *hw = priv->hw; |
809 | hw->rate_control_algorithm = "iwl-4965-rs"; | |
810 | ||
566bfe5a BR |
811 | /* Tell mac80211 our characteristics */ |
812 | hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | | |
813 | IEEE80211_HW_SIGNAL_DBM | | |
814 | IEEE80211_HW_NOISE_DBM; | |
bf85ea4f AK |
815 | /* Default value; 4 EDCA QOS priorities */ |
816 | hw->queues = 4; | |
bf85ea4f | 817 | /* Enhanced value; more queues, to support 11n aggregation */ |
e100bb64 | 818 | hw->ampdu_queues = 12; |
6ba87956 TW |
819 | |
820 | hw->conf.beacon_int = 100; | |
821 | ||
822 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) | |
823 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
824 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
825 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
826 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
827 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
828 | ||
829 | ret = ieee80211_register_hw(priv->hw); | |
830 | if (ret) { | |
831 | IWL_ERROR("Failed to register hw (error %d)\n", ret); | |
832 | return ret; | |
833 | } | |
834 | priv->mac80211_registered = 1; | |
835 | ||
836 | return 0; | |
bf85ea4f | 837 | } |
6ba87956 | 838 | EXPORT_SYMBOL(iwl_setup_mac); |
bf85ea4f | 839 | |
6ba87956 TW |
840 | |
841 | int iwl_init_drv(struct iwl_priv *priv) | |
c7de35cd RR |
842 | { |
843 | int ret; | |
844 | int i; | |
845 | ||
846 | priv->retry_rate = 1; | |
847 | priv->ibss_beacon = NULL; | |
848 | ||
849 | spin_lock_init(&priv->lock); | |
850 | spin_lock_init(&priv->power_data.lock); | |
851 | spin_lock_init(&priv->sta_lock); | |
852 | spin_lock_init(&priv->hcmd_lock); | |
853 | spin_lock_init(&priv->lq_mngr.lock); | |
854 | ||
855 | for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) | |
856 | INIT_LIST_HEAD(&priv->ibss_mac_hash[i]); | |
857 | ||
858 | INIT_LIST_HEAD(&priv->free_frames); | |
859 | ||
860 | mutex_init(&priv->mutex); | |
861 | ||
862 | /* Clear the driver's (not device's) station table */ | |
863 | iwlcore_clear_stations_table(priv); | |
864 | ||
865 | priv->data_retry_limit = -1; | |
866 | priv->ieee_channels = NULL; | |
867 | priv->ieee_rates = NULL; | |
868 | priv->band = IEEE80211_BAND_2GHZ; | |
869 | ||
870 | priv->iw_mode = IEEE80211_IF_TYPE_STA; | |
871 | ||
872 | priv->use_ant_b_for_management_frame = 1; /* start with ant B */ | |
873 | priv->ps_mode = IWL_MIMO_PS_NONE; | |
874 | ||
875 | /* Choose which receivers/antennas to use */ | |
876 | iwl_set_rxon_chain(priv); | |
f53696de | 877 | iwl_init_scan_params(priv); |
c7de35cd | 878 | |
6ba87956 TW |
879 | if (priv->cfg->mod_params->enable_qos) |
880 | priv->qos_data.qos_enable = 1; | |
881 | ||
c7de35cd RR |
882 | iwl_reset_qos(priv); |
883 | ||
884 | priv->qos_data.qos_active = 0; | |
885 | priv->qos_data.qos_cap.val = 0; | |
886 | ||
887 | iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6); | |
888 | ||
889 | priv->rates_mask = IWL_RATES_MASK; | |
890 | /* If power management is turned on, default to AC mode */ | |
891 | priv->power_mode = IWL_POWER_AC; | |
630fe9b6 | 892 | priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX; |
c7de35cd RR |
893 | |
894 | ret = iwl_init_channel_map(priv); | |
895 | if (ret) { | |
896 | IWL_ERROR("initializing regulatory failed: %d\n", ret); | |
897 | goto err; | |
898 | } | |
899 | ||
900 | ret = iwlcore_init_geos(priv); | |
901 | if (ret) { | |
902 | IWL_ERROR("initializing geos failed: %d\n", ret); | |
903 | goto err_free_channel_map; | |
904 | } | |
905 | ||
c7de35cd RR |
906 | return 0; |
907 | ||
c7de35cd RR |
908 | err_free_channel_map: |
909 | iwl_free_channel_map(priv); | |
910 | err: | |
911 | return ret; | |
912 | } | |
6ba87956 | 913 | EXPORT_SYMBOL(iwl_init_drv); |
c7de35cd | 914 | |
7c616cba TW |
915 | void iwl_free_calib_results(struct iwl_priv *priv) |
916 | { | |
917 | kfree(priv->calib_results.lo_res); | |
918 | priv->calib_results.lo_res = NULL; | |
919 | priv->calib_results.lo_res_len = 0; | |
920 | ||
921 | kfree(priv->calib_results.tx_iq_res); | |
922 | priv->calib_results.tx_iq_res = NULL; | |
923 | priv->calib_results.tx_iq_res_len = 0; | |
924 | ||
925 | kfree(priv->calib_results.tx_iq_perd_res); | |
926 | priv->calib_results.tx_iq_perd_res = NULL; | |
927 | priv->calib_results.tx_iq_perd_res_len = 0; | |
928 | } | |
929 | EXPORT_SYMBOL(iwl_free_calib_results); | |
6ba87956 | 930 | |
630fe9b6 TW |
931 | int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force) |
932 | { | |
933 | int ret = 0; | |
934 | if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) { | |
935 | IWL_WARNING("Requested user TXPOWER %d below limit.\n", | |
936 | priv->tx_power_user_lmt); | |
937 | return -EINVAL; | |
938 | } | |
939 | ||
940 | if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) { | |
941 | IWL_WARNING("Requested user TXPOWER %d above limit.\n", | |
942 | priv->tx_power_user_lmt); | |
943 | return -EINVAL; | |
944 | } | |
945 | ||
946 | if (priv->tx_power_user_lmt != tx_power) | |
947 | force = true; | |
948 | ||
949 | priv->tx_power_user_lmt = tx_power; | |
950 | ||
951 | if (force && priv->cfg->ops->lib->send_tx_power) | |
952 | ret = priv->cfg->ops->lib->send_tx_power(priv); | |
953 | ||
954 | return ret; | |
955 | } | |
956 | EXPORT_SYMBOL(iwl_set_tx_power); | |
957 | ||
958 | ||
6ba87956 | 959 | void iwl_uninit_drv(struct iwl_priv *priv) |
bf85ea4f | 960 | { |
7c616cba | 961 | iwl_free_calib_results(priv); |
6ba87956 TW |
962 | iwlcore_free_geos(priv); |
963 | iwl_free_channel_map(priv); | |
261415f7 | 964 | kfree(priv->scan); |
bf85ea4f | 965 | } |
6ba87956 | 966 | EXPORT_SYMBOL(iwl_uninit_drv); |
bf85ea4f | 967 | |
49ea8596 EG |
968 | int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags) |
969 | { | |
970 | u32 stat_flags = 0; | |
971 | struct iwl_host_cmd cmd = { | |
972 | .id = REPLY_STATISTICS_CMD, | |
973 | .meta.flags = flags, | |
974 | .len = sizeof(stat_flags), | |
975 | .data = (u8 *) &stat_flags, | |
976 | }; | |
977 | return iwl_send_cmd(priv, &cmd); | |
978 | } | |
979 | EXPORT_SYMBOL(iwl_send_statistics_request); | |
7e8c519e | 980 | |
b0692f2f EG |
981 | /** |
982 | * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host, | |
983 | * using sample data 100 bytes apart. If these sample points are good, | |
984 | * it's a pretty good bet that everything between them is good, too. | |
985 | */ | |
986 | static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) | |
987 | { | |
988 | u32 val; | |
989 | int ret = 0; | |
990 | u32 errcnt = 0; | |
991 | u32 i; | |
992 | ||
993 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
994 | ||
995 | ret = iwl_grab_nic_access(priv); | |
996 | if (ret) | |
997 | return ret; | |
998 | ||
999 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
1000 | /* read data comes through single port, auto-incr addr */ | |
1001 | /* NOTE: Use the debugless read so we don't flood kernel log | |
1002 | * if IWL_DL_IO is set */ | |
1003 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, | |
1004 | i + RTC_INST_LOWER_BOUND); | |
1005 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
1006 | if (val != le32_to_cpu(*image)) { | |
1007 | ret = -EIO; | |
1008 | errcnt++; | |
1009 | if (errcnt >= 3) | |
1010 | break; | |
1011 | } | |
1012 | } | |
1013 | ||
1014 | iwl_release_nic_access(priv); | |
1015 | ||
1016 | return ret; | |
1017 | } | |
1018 | ||
1019 | /** | |
1020 | * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host, | |
1021 | * looking at all data. | |
1022 | */ | |
1023 | static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image, | |
1024 | u32 len) | |
1025 | { | |
1026 | u32 val; | |
1027 | u32 save_len = len; | |
1028 | int ret = 0; | |
1029 | u32 errcnt; | |
1030 | ||
1031 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
1032 | ||
1033 | ret = iwl_grab_nic_access(priv); | |
1034 | if (ret) | |
1035 | return ret; | |
1036 | ||
1037 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND); | |
1038 | ||
1039 | errcnt = 0; | |
1040 | for (; len > 0; len -= sizeof(u32), image++) { | |
1041 | /* read data comes through single port, auto-incr addr */ | |
1042 | /* NOTE: Use the debugless read so we don't flood kernel log | |
1043 | * if IWL_DL_IO is set */ | |
1044 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
1045 | if (val != le32_to_cpu(*image)) { | |
1046 | IWL_ERROR("uCode INST section is invalid at " | |
1047 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
1048 | save_len - len, val, le32_to_cpu(*image)); | |
1049 | ret = -EIO; | |
1050 | errcnt++; | |
1051 | if (errcnt >= 20) | |
1052 | break; | |
1053 | } | |
1054 | } | |
1055 | ||
1056 | iwl_release_nic_access(priv); | |
1057 | ||
1058 | if (!errcnt) | |
1059 | IWL_DEBUG_INFO | |
1060 | ("ucode image in INSTRUCTION memory is good\n"); | |
1061 | ||
1062 | return ret; | |
1063 | } | |
1064 | ||
1065 | /** | |
1066 | * iwl_verify_ucode - determine which instruction image is in SRAM, | |
1067 | * and verify its contents | |
1068 | */ | |
1069 | int iwl_verify_ucode(struct iwl_priv *priv) | |
1070 | { | |
1071 | __le32 *image; | |
1072 | u32 len; | |
1073 | int ret; | |
1074 | ||
1075 | /* Try bootstrap */ | |
1076 | image = (__le32 *)priv->ucode_boot.v_addr; | |
1077 | len = priv->ucode_boot.len; | |
1078 | ret = iwlcore_verify_inst_sparse(priv, image, len); | |
1079 | if (!ret) { | |
1080 | IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n"); | |
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | /* Try initialize */ | |
1085 | image = (__le32 *)priv->ucode_init.v_addr; | |
1086 | len = priv->ucode_init.len; | |
1087 | ret = iwlcore_verify_inst_sparse(priv, image, len); | |
1088 | if (!ret) { | |
1089 | IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n"); | |
1090 | return 0; | |
1091 | } | |
1092 | ||
1093 | /* Try runtime/protocol */ | |
1094 | image = (__le32 *)priv->ucode_code.v_addr; | |
1095 | len = priv->ucode_code.len; | |
1096 | ret = iwlcore_verify_inst_sparse(priv, image, len); | |
1097 | if (!ret) { | |
1098 | IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n"); | |
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); | |
1103 | ||
1104 | /* Since nothing seems to match, show first several data entries in | |
1105 | * instruction SRAM, so maybe visual inspection will give a clue. | |
1106 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
1107 | image = (__le32 *)priv->ucode_boot.v_addr; | |
1108 | len = priv->ucode_boot.len; | |
1109 | ret = iwl_verify_inst_full(priv, image, len); | |
1110 | ||
1111 | return ret; | |
1112 | } | |
1113 | EXPORT_SYMBOL(iwl_verify_ucode); | |
1114 | ||
189a2b59 | 1115 | |
ede0cba4 EK |
1116 | static const char *desc_lookup(int i) |
1117 | { | |
1118 | switch (i) { | |
1119 | case 1: | |
1120 | return "FAIL"; | |
1121 | case 2: | |
1122 | return "BAD_PARAM"; | |
1123 | case 3: | |
1124 | return "BAD_CHECKSUM"; | |
1125 | case 4: | |
1126 | return "NMI_INTERRUPT"; | |
1127 | case 5: | |
1128 | return "SYSASSERT"; | |
1129 | case 6: | |
1130 | return "FATAL_ERROR"; | |
1131 | } | |
1132 | ||
1133 | return "UNKNOWN"; | |
1134 | } | |
1135 | ||
1136 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1137 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1138 | ||
1139 | void iwl_dump_nic_error_log(struct iwl_priv *priv) | |
1140 | { | |
1141 | u32 data2, line; | |
1142 | u32 desc, time, count, base, data1; | |
1143 | u32 blink1, blink2, ilink1, ilink2; | |
e1dfc085 | 1144 | int ret; |
ede0cba4 | 1145 | |
e1dfc085 GG |
1146 | if (priv->ucode_type == UCODE_INIT) |
1147 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | |
1148 | else | |
1149 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
ede0cba4 EK |
1150 | |
1151 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
1152 | IWL_ERROR("Not valid error log pointer 0x%08X\n", base); | |
1153 | return; | |
1154 | } | |
1155 | ||
e1dfc085 GG |
1156 | ret = iwl_grab_nic_access(priv); |
1157 | if (ret) { | |
ede0cba4 EK |
1158 | IWL_WARNING("Can not read from adapter at this time.\n"); |
1159 | return; | |
1160 | } | |
1161 | ||
1162 | count = iwl_read_targ_mem(priv, base); | |
1163 | ||
1164 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
1165 | IWL_ERROR("Start IWL Error Log Dump:\n"); | |
1166 | IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count); | |
1167 | } | |
1168 | ||
1169 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); | |
1170 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); | |
1171 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
1172 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
1173 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
1174 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
1175 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
1176 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
1177 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
1178 | ||
1179 | IWL_ERROR("Desc Time " | |
1180 | "data1 data2 line\n"); | |
1181 | IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n", | |
1182 | desc_lookup(desc), desc, time, data1, data2, line); | |
1183 | IWL_ERROR("blink1 blink2 ilink1 ilink2\n"); | |
1184 | IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, | |
1185 | ilink1, ilink2); | |
1186 | ||
1187 | iwl_release_nic_access(priv); | |
1188 | } | |
1189 | EXPORT_SYMBOL(iwl_dump_nic_error_log); | |
1190 | ||
189a2b59 EK |
1191 | #define EVENT_START_OFFSET (4 * sizeof(u32)) |
1192 | ||
1193 | /** | |
1194 | * iwl_print_event_log - Dump error event log to syslog | |
1195 | * | |
1196 | * NOTE: Must be called with iwl4965_grab_nic_access() already obtained! | |
1197 | */ | |
1198 | void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, | |
1199 | u32 num_events, u32 mode) | |
1200 | { | |
1201 | u32 i; | |
1202 | u32 base; /* SRAM byte address of event log header */ | |
1203 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1204 | u32 ptr; /* SRAM byte address of log data */ | |
1205 | u32 ev, time, data; /* event log data */ | |
1206 | ||
1207 | if (num_events == 0) | |
1208 | return; | |
e1dfc085 GG |
1209 | if (priv->ucode_type == UCODE_INIT) |
1210 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | |
1211 | else | |
1212 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
189a2b59 EK |
1213 | |
1214 | if (mode == 0) | |
1215 | event_size = 2 * sizeof(u32); | |
1216 | else | |
1217 | event_size = 3 * sizeof(u32); | |
1218 | ||
1219 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1220 | ||
1221 | /* "time" is actually "data" for mode 0 (no timestamp). | |
1222 | * place event id # at far right for easier visual parsing. */ | |
1223 | for (i = 0; i < num_events; i++) { | |
1224 | ev = iwl_read_targ_mem(priv, ptr); | |
1225 | ptr += sizeof(u32); | |
1226 | time = iwl_read_targ_mem(priv, ptr); | |
1227 | ptr += sizeof(u32); | |
77c5d08e TW |
1228 | if (mode == 0) { |
1229 | /* data, ev */ | |
1230 | IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev); | |
1231 | } else { | |
189a2b59 EK |
1232 | data = iwl_read_targ_mem(priv, ptr); |
1233 | ptr += sizeof(u32); | |
77c5d08e TW |
1234 | IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n", |
1235 | time, data, ev); | |
189a2b59 EK |
1236 | } |
1237 | } | |
1238 | } | |
1239 | EXPORT_SYMBOL(iwl_print_event_log); | |
1240 | ||
1241 | ||
1242 | void iwl_dump_nic_event_log(struct iwl_priv *priv) | |
1243 | { | |
e1dfc085 | 1244 | int ret; |
189a2b59 EK |
1245 | u32 base; /* SRAM byte address of event log header */ |
1246 | u32 capacity; /* event log capacity in # entries */ | |
1247 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
1248 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
1249 | u32 next_entry; /* index of next entry to be written by uCode */ | |
1250 | u32 size; /* # entries that we'll print */ | |
1251 | ||
e1dfc085 GG |
1252 | if (priv->ucode_type == UCODE_INIT) |
1253 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | |
1254 | else | |
1255 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
1256 | ||
189a2b59 EK |
1257 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { |
1258 | IWL_ERROR("Invalid event log pointer 0x%08X\n", base); | |
1259 | return; | |
1260 | } | |
1261 | ||
e1dfc085 GG |
1262 | ret = iwl_grab_nic_access(priv); |
1263 | if (ret) { | |
189a2b59 EK |
1264 | IWL_WARNING("Can not read from adapter at this time.\n"); |
1265 | return; | |
1266 | } | |
1267 | ||
1268 | /* event log header */ | |
1269 | capacity = iwl_read_targ_mem(priv, base); | |
1270 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
1271 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
1272 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
1273 | ||
1274 | size = num_wraps ? capacity : next_entry; | |
1275 | ||
1276 | /* bail out if nothing in log */ | |
1277 | if (size == 0) { | |
1278 | IWL_ERROR("Start IWL Event Log Dump: nothing in log\n"); | |
1279 | iwl_release_nic_access(priv); | |
1280 | return; | |
1281 | } | |
1282 | ||
1283 | IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n", | |
1284 | size, num_wraps); | |
1285 | ||
1286 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
1287 | * i.e the next one that uCode would fill. */ | |
1288 | if (num_wraps) | |
1289 | iwl_print_event_log(priv, next_entry, | |
1290 | capacity - next_entry, mode); | |
1291 | /* (then/else) start at top of log */ | |
1292 | iwl_print_event_log(priv, 0, next_entry, mode); | |
1293 | ||
1294 | iwl_release_nic_access(priv); | |
1295 | } | |
1296 | EXPORT_SYMBOL(iwl_dump_nic_event_log); | |
1297 | ||
47f4a587 EG |
1298 | void iwl_rf_kill_ct_config(struct iwl_priv *priv) |
1299 | { | |
1300 | struct iwl_ct_kill_config cmd; | |
1301 | unsigned long flags; | |
1302 | int ret = 0; | |
1303 | ||
1304 | spin_lock_irqsave(&priv->lock, flags); | |
1305 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
1306 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); | |
1307 | spin_unlock_irqrestore(&priv->lock, flags); | |
1308 | ||
1309 | cmd.critical_temperature_R = | |
1310 | cpu_to_le32(priv->hw_params.ct_kill_threshold); | |
189a2b59 | 1311 | |
47f4a587 EG |
1312 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, |
1313 | sizeof(cmd), &cmd); | |
1314 | if (ret) | |
1315 | IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n"); | |
1316 | else | |
1317 | IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, " | |
1318 | "critical temperature is %d\n", | |
1319 | cmd.critical_temperature_R); | |
1320 | } | |
1321 | EXPORT_SYMBOL(iwl_rf_kill_ct_config); | |
14a08a7f EG |
1322 | |
1323 | /* | |
1324 | * CARD_STATE_CMD | |
1325 | * | |
1326 | * Use: Sets the device's internal card state to enable, disable, or halt | |
1327 | * | |
1328 | * When in the 'enable' state the card operates as normal. | |
1329 | * When in the 'disable' state, the card enters into a low power mode. | |
1330 | * When in the 'halt' state, the card is shut down and must be fully | |
1331 | * restarted to come back on. | |
1332 | */ | |
1333 | static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag) | |
1334 | { | |
1335 | struct iwl_host_cmd cmd = { | |
1336 | .id = REPLY_CARD_STATE_CMD, | |
1337 | .len = sizeof(u32), | |
1338 | .data = &flags, | |
1339 | .meta.flags = meta_flag, | |
1340 | }; | |
1341 | ||
1342 | return iwl_send_cmd(priv, &cmd); | |
1343 | } | |
1344 | ||
1345 | void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv) | |
1346 | { | |
1347 | unsigned long flags; | |
1348 | ||
1349 | if (test_bit(STATUS_RF_KILL_SW, &priv->status)) | |
1350 | return; | |
1351 | ||
1352 | IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n"); | |
1353 | ||
1354 | iwl_scan_cancel(priv); | |
1355 | /* FIXME: This is a workaround for AP */ | |
1356 | if (priv->iw_mode != IEEE80211_IF_TYPE_AP) { | |
1357 | spin_lock_irqsave(&priv->lock, flags); | |
1358 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, | |
1359 | CSR_UCODE_SW_BIT_RFKILL); | |
1360 | spin_unlock_irqrestore(&priv->lock, flags); | |
1361 | /* call the host command only if no hw rf-kill set */ | |
1362 | if (!test_bit(STATUS_RF_KILL_HW, &priv->status) && | |
1363 | iwl_is_ready(priv)) | |
1364 | iwl_send_card_state(priv, | |
1365 | CARD_STATE_CMD_DISABLE, 0); | |
1366 | set_bit(STATUS_RF_KILL_SW, &priv->status); | |
1367 | /* make sure mac80211 stop sending Tx frame */ | |
1368 | if (priv->mac80211_registered) | |
1369 | ieee80211_stop_queues(priv->hw); | |
1370 | } | |
1371 | } | |
1372 | EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio); | |
1373 | ||
1374 | int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv) | |
1375 | { | |
1376 | unsigned long flags; | |
1377 | ||
1378 | if (!test_bit(STATUS_RF_KILL_SW, &priv->status)) | |
1379 | return 0; | |
1380 | ||
1381 | IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n"); | |
1382 | ||
1383 | spin_lock_irqsave(&priv->lock, flags); | |
1384 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
1385 | ||
1386 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
1387 | spin_unlock_irqrestore(&priv->lock, flags); | |
1388 | ||
1389 | /* wake up ucode */ | |
1390 | msleep(10); | |
1391 | ||
1392 | spin_lock_irqsave(&priv->lock, flags); | |
1393 | iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
1394 | if (!iwl_grab_nic_access(priv)) | |
1395 | iwl_release_nic_access(priv); | |
1396 | spin_unlock_irqrestore(&priv->lock, flags); | |
1397 | ||
1398 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
1399 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
1400 | "disabled by HW switch\n"); | |
1401 | return 0; | |
1402 | } | |
1403 | ||
1404 | if (priv->is_open) | |
1405 | queue_work(priv->workqueue, &priv->restart); | |
1406 | return 1; | |
1407 | } | |
1408 | EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio); |