[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-csr.h

/******************************************************************************
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
 * in the file called LICENSE.GPL.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 * BSD LICENSE
 *
 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name Intel Corporation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/
#ifndef __iwl_csr_h__
#define __iwl_csr_h__
/*=== CSR (control and status registers) ===*/
#define CSR_BASE    (0x000)

#define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
#define CSR_INT_COALESCING     (CSR_BASE+0x004) /* accum ints, 32-usec units */
#define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
#define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
#define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
#define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
#define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
#define CSR_GP_CNTRL            (CSR_BASE+0x024)

/*
 * Hardware revision info
 * Bit fields:
 * 31-8:  Reserved
 *  7-4:  Type of device:  0x0 = 4965, 0xd = 3945
 *  3-2:  Revision step:  0 = A, 1 = B, 2 = C, 3 = D
 *  1-0:  "Dash" value, as in A-1, etc.
 *
 * NOTE:  Revision step affects calculation of CCK txpower for 4965.
 */
#define CSR_HW_REV              (CSR_BASE+0x028)

/* EEPROM reads */
#define CSR_EEPROM_REG          (CSR_BASE+0x02c)
#define CSR_EEPROM_GP           (CSR_BASE+0x030)
#define CSR_OTP_GP_REG   	(CSR_BASE+0x034)
#define CSR_GIO_REG		(CSR_BASE+0x03C)
#define CSR_GP_UCODE_REG	(CSR_BASE+0x048)
#define CSR_GP_DRIVER_REG	(CSR_BASE+0x050)
#define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
#define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
#define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
#define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)
#define CSR_LED_REG             (CSR_BASE+0x094)
#define CSR_DRAM_INT_TBL_REG	(CSR_BASE+0x0A0)
#define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)

#define CSR_INT_PERIODIC_REG	(CSR_BASE+0x005)
/* Analog phase-lock-loop configuration  */
#define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)
/*
 * Indicates hardware rev, to determine CCK backoff for txpower calculation.
 * Bit fields:
 *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
 */
#define CSR_HW_REV_WA_REG	(CSR_BASE+0x22C)
#define CSR_DBG_HPET_MEM_REG	(CSR_BASE+0x240)

/* Bits for CSR_HW_IF_CONFIG_REG */
#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R	(0x00000010)
#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER	(0x00000C00)
#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI 	(0x00000100)
#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI	(0x00000200)

#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB         (0x00000100)
#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM         (0x00000200)
#define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC            (0x00000400)
#define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE         (0x00000800)
#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A    (0x00000000)
#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B    (0x00001000)

#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A		(0x00080000)
#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM		(0x00200000)
#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY		(0x00400000)
#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE	(0x02000000)
#define CSR_HW_IF_CONFIG_REG_PREPARE			(0x08000000)

#define CSR_INT_PERIODIC_DIS			(0x00)
#define CSR_INT_PERIODIC_ENA			(0xFF)

/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
 * acknowledged (reset) by host writing "1" to flagged bits. */
#define CSR_INT_BIT_FH_RX        (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
#define CSR_INT_BIT_HW_ERR       (1 << 29) /* DMA hardware error FH_INT[31] */
#define CSR_INT_BIT_RX_PERIODIC	 (1 << 28) /* Rx periodic */
#define CSR_INT_BIT_FH_TX        (1 << 27) /* Tx DMA FH_INT[1:0] */
#define CSR_INT_BIT_SCD          (1 << 26) /* TXQ pointer advanced */
#define CSR_INT_BIT_SW_ERR       (1 << 25) /* uCode error */
#define CSR_INT_BIT_RF_KILL      (1 << 7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
#define CSR_INT_BIT_CT_KILL      (1 << 6)  /* Critical temp (chip too hot) rfkill */
#define CSR_INT_BIT_SW_RX        (1 << 3)  /* Rx, command responses, 3945 */
#define CSR_INT_BIT_WAKEUP       (1 << 1)  /* NIC controller waking up (pwr mgmt) */
#define CSR_INT_BIT_ALIVE        (1 << 0)  /* uCode interrupts once it initializes */

#define CSR_INI_SET_MASK	(CSR_INT_BIT_FH_RX   | \
				 CSR_INT_BIT_HW_ERR  | \
				 CSR_INT_BIT_FH_TX   | \
				 CSR_INT_BIT_SW_ERR  | \
				 CSR_INT_BIT_RF_KILL | \
				 CSR_INT_BIT_SW_RX   | \
				 CSR_INT_BIT_WAKEUP  | \
				 CSR_INT_BIT_ALIVE)

/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
#define CSR_FH_INT_BIT_ERR       (1 << 31) /* Error */
#define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30) /* High priority Rx, bypass coalescing */
#define CSR39_FH_INT_BIT_RX_CHNL2  (1 << 18) /* Rx channel 2 (3945 only) */
#define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17) /* Rx channel 1 */
#define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16) /* Rx channel 0 */
#define CSR39_FH_INT_BIT_TX_CHNL6  (1 << 6)  /* Tx channel 6 (3945 only) */
#define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)  /* Tx channel 1 */
#define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)  /* Tx channel 0 */

#define CSR39_FH_INT_RX_MASK	(CSR_FH_INT_BIT_HI_PRIOR | \
				 CSR39_FH_INT_BIT_RX_CHNL2 | \
				 CSR_FH_INT_BIT_RX_CHNL1 | \
				 CSR_FH_INT_BIT_RX_CHNL0)


#define CSR39_FH_INT_TX_MASK	(CSR39_FH_INT_BIT_TX_CHNL6 | \
				 CSR_FH_INT_BIT_TX_CHNL1 | \
				 CSR_FH_INT_BIT_TX_CHNL0)

#define CSR49_FH_INT_RX_MASK	(CSR_FH_INT_BIT_HI_PRIOR | \
				 CSR_FH_INT_BIT_RX_CHNL1 | \
				 CSR_FH_INT_BIT_RX_CHNL0)

#define CSR49_FH_INT_TX_MASK	(CSR_FH_INT_BIT_TX_CHNL1 | \
				 CSR_FH_INT_BIT_TX_CHNL0)

/* GPIO */
#define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC               (0x00000200)

/* RESET */
#define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
#define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
#define CSR_RESET_REG_FLAG_SW_RESET                  (0x00000080)
#define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
#define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)

/* GP (general purpose) CONTROL */
#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY        (0x00000001)
#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE              (0x00000004)
#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ         (0x00000008)
#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)

#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN           (0x00000001)

#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE         (0x04000000)
#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)


/* HW REV */
#define CSR_HW_REV_TYPE_MSK            (0x00000F0)
#define CSR_HW_REV_TYPE_3945           (0x00000D0)
#define CSR_HW_REV_TYPE_4965           (0x0000000)
#define CSR_HW_REV_TYPE_5300           (0x0000020)
#define CSR_HW_REV_TYPE_5350           (0x0000030)
#define CSR_HW_REV_TYPE_5100           (0x0000050)
#define CSR_HW_REV_TYPE_5150           (0x0000040)
#define CSR_HW_REV_TYPE_1000           (0x0000060)
#define CSR_HW_REV_TYPE_6x00           (0x0000070)
#define CSR_HW_REV_TYPE_6x50           (0x0000080)
#define CSR_HW_REV_TYPE_NONE           (0x00000F0)

/* EEPROM REG */
#define CSR_EEPROM_REG_READ_VALID_MSK	(0x00000001)
#define CSR_EEPROM_REG_BIT_CMD		(0x00000002)
#define CSR_EEPROM_REG_MSK_ADDR		(0x0000FFFC)
#define CSR_EEPROM_REG_MSK_DATA		(0xFFFF0000)

/* EEPROM GP */
#define CSR_EEPROM_GP_VALID_MSK		(0x00000007)
#define CSR_EEPROM_GP_IF_OWNER_MSK	(0x00000180)
#define CSR_OTP_GP_REG_DEVICE_SELECT	(0x00010000) /* 0 - EEPROM, 1 - OTP */
#define CSR_OTP_GP_REG_OTP_ACCESS_MODE	(0x00020000) /* 0 - absolute, 1 - relative */
#define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK          (0x00100000) /* bit 20 */
#define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK        (0x00200000) /* bit 21 */
#define CSR_GP_REG_POWER_SAVE_STATUS_MSK            (0x03000000) /* bit 24/25 */
#define CSR_GP_REG_NO_POWER_SAVE            (0x00000000)
#define CSR_GP_REG_MAC_POWER_SAVE           (0x01000000)
#define CSR_GP_REG_PHY_POWER_SAVE           (0x02000000)
#define CSR_GP_REG_POWER_SAVE_ERROR         (0x03000000)

/* EEPROM signature */
#define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP	(0x00000000)
#define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP		(0x00000001)
#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K		(0x00000002)
#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K		(0x00000004)

/* CSR GIO */
#define CSR_GIO_REG_VAL_L0S_ENABLED	(0x00000002)

/* UCODE DRV GP */
#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
#define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)

/* GP Driver */
#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK	    (0x00000003)
#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB	    (0x00000000)
#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB	    (0x00000001)
#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA	    (0x00000002)


/* GI Chicken Bits */
#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)

/* LED */
#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
#define CSR_LED_REG_TRUN_ON (0x78)
#define CSR_LED_REG_TRUN_OFF (0x38)

/* ANA_PLL */
#define CSR39_ANA_PLL_CFG_VAL        (0x01000000)
#define CSR50_ANA_PLL_CFG_VAL        (0x00880300)

/* HPET MEM debug */
#define CSR_DBG_HPET_MEM_REG_VAL	(0xFFFF0000)

/* DRAM INT TABLE */
#define CSR_DRAM_INT_TBL_ENABLE		(1 << 31)
#define CSR_DRAM_INIT_TBL_WRAP_CHECK	(1 << 27)

/*=== HBUS (Host-side Bus) ===*/
#define HBUS_BASE	(0x400)
/*
 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
 * structures, error log, event log, verifying uCode load).
 * First write to address register, then read from or write to data register
 * to complete the job.  Once the address register is set up, accesses to
 * data registers auto-increment the address by one dword.
 * Bit usage for address registers (read or write):
 *  0-31:  memory address within device
 */
#define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
#define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
#define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
#define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)

/*
 * Registers for accessing device's internal peripheral registers
 * (e.g. SCD, BSM, etc.).  First write to address register,
 * then read from or write to data register to complete the job.
 * Bit usage for address registers (read or write):
 *  0-15:  register address (offset) within device
 * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
 */
#define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
#define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
#define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
#define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)

/*
 * Per-Tx-queue write pointer (index, really!) (3945 and 4965).
 * Indicates index to next TFD that driver will fill (1 past latest filled).
 * Bit usage:
 *  0-7:  queue write index
 * 11-8:  queue selector
 */
#define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)
#define HBUS_TARG_MBX_C         (HBUS_BASE+0x030)

#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED         (0x00000004)


#endif /* !__iwl_csr_h__ */
Commit	Line	Data
6f83eaa1 TW	1	/******************************************************************************
	2	*
	3	* This file is provided under a dual BSD/GPLv2 license. When using or
	4	* redistributing this file, you may do so under either license.
	5	*
	6	* GPL LICENSE SUMMARY
	7	*
01f8162a	8	* Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
6f83eaa1 TW	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of version 2 of the GNU General Public License as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but
	15	* WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
	22	* USA
	23	*
	24	* The full GNU General Public License is included in this distribution
	25	* in the file called LICENSE.GPL.
	26	*
	27	* Contact Information:
759ef89f	28	* Intel Linux Wireless <ilw@linux.intel.com>
6f83eaa1 TW	29	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	30	*
	31	* BSD LICENSE
	32	*
01f8162a	33	* Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
6f83eaa1 TW	34	* All rights reserved.
	35	*
	36	* Redistribution and use in source and binary forms, with or without
	37	* modification, are permitted provided that the following conditions
	38	* are met:
	39	*
	40	* * Redistributions of source code must retain the above copyright
	41	* notice, this list of conditions and the following disclaimer.
	42	* * Redistributions in binary form must reproduce the above copyright
	43	* notice, this list of conditions and the following disclaimer in
	44	* the documentation and/or other materials provided with the
	45	* distribution.
	46	* * Neither the name Intel Corporation nor the names of its
	47	* contributors may be used to endorse or promote products derived
	48	* from this software without specific prior written permission.
	49	*
	50	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	51	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	52	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	53	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	54	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	55	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	56	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	57	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	58	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	59	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	60	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	61	*
	62	*****************************************************************************/
65a0667b TW	63	#ifndef __iwl_csr_h__
65a0667b TW	64	#define __iwl_csr_h__
6f83eaa1 TW	65	/=== CSR (control and status registers) ===/
	66	#define CSR_BASE (0x000)
	67
	68	#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
8cd519e8	69	#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
6f83eaa1 TW	70	#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
	71	#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
	72	#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
	73	#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
	74	#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
	75	#define CSR_GP_CNTRL (CSR_BASE+0x024)
	76
	77	/*
	78	* Hardware revision info
	79	* Bit fields:
	80	* 31-8: Reserved
	81	* 7-4: Type of device: 0x0 = 4965, 0xd = 3945
	82	* 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
	83	* 1-0: "Dash" value, as in A-1, etc.
	84	*
	85	* NOTE: Revision step affects calculation of CCK txpower for 4965.
	86	*/
	87	#define CSR_HW_REV (CSR_BASE+0x028)
	88
	89	/* EEPROM reads */
	90	#define CSR_EEPROM_REG (CSR_BASE+0x02c)
	91	#define CSR_EEPROM_GP (CSR_BASE+0x030)
0848e297	92	#define CSR_OTP_GP_REG (CSR_BASE+0x034)
8f061891	93	#define CSR_GIO_REG (CSR_BASE+0x03C)
65b7998a WYG	94	#define CSR_GP_UCODE_REG (CSR_BASE+0x048)
65b7998a WYG	95	#define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
6f83eaa1 TW	96	#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
	97	#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
	98	#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
	99	#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
ab53d8af	100	#define CSR_LED_REG (CSR_BASE+0x094)
ef850d7c	101	#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
8f061891	102	#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
6f83eaa1	103
40cefda9	104	#define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
a693f187	105	/* Analog phase-lock-loop configuration */
6f83eaa1 TW	106	#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
	107	/*
	108	* Indicates hardware rev, to determine CCK backoff for txpower calculation.
	109	* Bit fields:
	110	* 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
	111	*/
	112	#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
4c43e0d0	113	#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
6f83eaa1 TW	114
	115	/* Bits for CSR_HW_IF_CONFIG_REG */
	116	#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010)
a395b920 TW	117	#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
	118	#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
	119	#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
6f83eaa1 TW	120
	121	#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB (0x00000100)
	122	#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM (0x00000200)
	123	#define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
	124	#define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800)
	125	#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
	126	#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
	127
4c43e0d0 TW	128	#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
4c43e0d0 TW	129	#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
086ed117 MA	130	#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000)
	131	#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000)
	132	#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000)
4c43e0d0	133
40cefda9 MA	134	#define CSR_INT_PERIODIC_DIS (0x00)
40cefda9 MA	135	#define CSR_INT_PERIODIC_ENA (0xFF)
6f83eaa1 TW	136
	137	/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
	138	* acknowledged (reset) by host writing "1" to flagged bits. */
	139	#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
	140	#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
40cefda9	141	#define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
6f83eaa1 TW	142	#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
	143	#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
	144	#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
	145	#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
	146	#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
	147	#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */
	148	#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
	149	#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
	150
	151	#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX \| \
	152	CSR_INT_BIT_HW_ERR \| \
	153	CSR_INT_BIT_FH_TX \| \
	154	CSR_INT_BIT_SW_ERR \| \
	155	CSR_INT_BIT_RF_KILL \| \
	156	CSR_INT_BIT_SW_RX \| \
	157	CSR_INT_BIT_WAKEUP \| \
	158	CSR_INT_BIT_ALIVE)
	159
	160	/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
	161	#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
	162	#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
	163	#define CSR39_FH_INT_BIT_RX_CHNL2 (1 << 18) /* Rx channel 2 (3945 only) */
	164	#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
	165	#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
	166	#define CSR39_FH_INT_BIT_TX_CHNL6 (1 << 6) /* Tx channel 6 (3945 only) */
	167	#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
	168	#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
	169
	170	#define CSR39_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR \| \
	171	CSR39_FH_INT_BIT_RX_CHNL2 \| \
	172	CSR_FH_INT_BIT_RX_CHNL1 \| \
	173	CSR_FH_INT_BIT_RX_CHNL0)
	174
	175
	176	#define CSR39_FH_INT_TX_MASK (CSR39_FH_INT_BIT_TX_CHNL6 \| \
	177	CSR_FH_INT_BIT_TX_CHNL1 \| \
	178	CSR_FH_INT_BIT_TX_CHNL0)
	179
	180	#define CSR49_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR \| \
	181	CSR_FH_INT_BIT_RX_CHNL1 \| \
	182	CSR_FH_INT_BIT_RX_CHNL0)
	183
	184	#define CSR49_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 \| \
	185	CSR_FH_INT_BIT_TX_CHNL0)
	186
6f4083aa TW	187	/* GPIO */
	188	#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
	189	#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
	190	#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
6f83eaa1 TW	191
	192	/* RESET */
	193	#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
	194	#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
	195	#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
	196	#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
	197	#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
	198
	199	/* GP (general purpose) CONTROL */
	200	#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
	201	#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
	202	#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
	203	#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
	204
	205	#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
	206
	207	#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
	208	#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
	209	#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
	210
	211
b661c819 TW	212	/* HW REV */
	213	#define CSR_HW_REV_TYPE_MSK (0x00000F0)
	214	#define CSR_HW_REV_TYPE_3945 (0x00000D0)
	215	#define CSR_HW_REV_TYPE_4965 (0x0000000)
fcf623df TW	216	#define CSR_HW_REV_TYPE_5300 (0x0000020)
	217	#define CSR_HW_REV_TYPE_5350 (0x0000030)
	218	#define CSR_HW_REV_TYPE_5100 (0x0000050)
	219	#define CSR_HW_REV_TYPE_5150 (0x0000040)
77dcb6a9	220	#define CSR_HW_REV_TYPE_1000 (0x0000060)
2264596d JS	221	#define CSR_HW_REV_TYPE_6x00 (0x0000070)
2264596d JS	222	#define CSR_HW_REV_TYPE_6x50 (0x0000080)
fcf623df	223	#define CSR_HW_REV_TYPE_NONE (0x00000F0)
b661c819	224
6f83eaa1 TW	225	/* EEPROM REG */
	226	#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
	227	#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
3d5717ad ZY	228	#define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
3d5717ad ZY	229	#define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
6f83eaa1 TW	230
6f83eaa1 TW	231	/* EEPROM GP */
4b6f764e	232	#define CSR_EEPROM_GP_VALID_MSK (0x00000007)
6f83eaa1	233	#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
0848e297 WYG	234	#define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
	235	#define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
	236	#define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
	237	#define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
c09430ab WYG	238	#define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
	239	#define CSR_GP_REG_NO_POWER_SAVE (0x00000000)
	240	#define CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
	241	#define CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
	242	#define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
6f83eaa1	243
f41bb897 WYG	244	/* EEPROM signature */
	245	#define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
	246	#define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
	247	#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
	248	#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
	249
8f061891 TW	250	/* CSR GIO */
	251	#define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
	252
6f83eaa1 TW	253	/* UCODE DRV GP */
	254	#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
	255	#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
	256	#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
	257	#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
	258
65b7998a WYG	259	/* GP Driver */
	260	#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
	261	#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
	262	#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
	263	#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
	264
	265
6f83eaa1 TW	266	/* GI Chicken Bits */
	267	#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
	268	#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
	269
ab53d8af MA	270	/* LED */
	271	#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
	272	#define CSR_LED_REG_TRUN_ON (0x78)
	273	#define CSR_LED_REG_TRUN_OFF (0x38)
	274
a693f187 TW	275	/* ANA_PLL */
	276	#define CSR39_ANA_PLL_CFG_VAL (0x01000000)
	277	#define CSR50_ANA_PLL_CFG_VAL (0x00880300)
	278
4c43e0d0 TW	279	/* HPET MEM debug */
4c43e0d0 TW	280	#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
ef850d7c MA	281
	282	/* DRAM INT TABLE */
	283	#define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
	284	#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
	285
750fe639 TW	286	/=== HBUS (Host-side Bus) ===/
	287	#define HBUS_BASE (0x400)
	288	/*
	289	* Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
	290	* structures, error log, event log, verifying uCode load).
	291	* First write to address register, then read from or write to data register
	292	* to complete the job. Once the address register is set up, accesses to
	293	* data registers auto-increment the address by one dword.
	294	* Bit usage for address registers (read or write):
	295	* 0-31: memory address within device
	296	*/
	297	#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
	298	#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
	299	#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
	300	#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
	301
	302	/*
	303	* Registers for accessing device's internal peripheral registers
	304	* (e.g. SCD, BSM, etc.). First write to address register,
	305	* then read from or write to data register to complete the job.
	306	* Bit usage for address registers (read or write):
	307	* 0-15: register address (offset) within device
	308	* 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
	309	*/
	310	#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
	311	#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
	312	#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
	313	#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
	314
	315	/*
	316	* Per-Tx-queue write pointer (index, really!) (3945 and 4965).
	317	* Indicates index to next TFD that driver will fill (1 past latest filled).
	318	* Bit usage:
	319	* 0-7: queue write index
	320	* 11-8: queue selector
	321	*/
	322	#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
	323	#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
	324
	325	#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
	326
	327
65a0667b	328	#endif /* !__iwl_csr_h__ */