iwl3945: kill iwl3945_rx_queue_restock
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
b481de9c
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1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 * Please use iwl-4965-hw.h for hardware-related definitions.
30 */
31
be1f3ab6
EG
32#ifndef __iwl_dev_h__
33#define __iwl_dev_h__
b481de9c 34
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
37#include <net/ieee80211_radiotap.h>
38
6bc913bd 39#include "iwl-eeprom.h"
6f83eaa1 40#include "iwl-csr.h"
5d08cd1d 41#include "iwl-prph.h"
dbb6654c 42#include "iwl-fh.h"
0a6857e7 43#include "iwl-debug.h"
dbb6654c
WT
44#include "iwl-rfkill.h"
45#include "iwl-4965-hw.h"
46#include "iwl-3945-hw.h"
47#include "iwl-3945-led.h"
ab53d8af 48#include "iwl-led.h"
5da4b55f 49#include "iwl-power.h"
e227ceac 50#include "iwl-agn-rs.h"
5d08cd1d 51
fed9017e
RR
52/* configuration for the iwl4965 */
53extern struct iwl_cfg iwl4965_agn_cfg;
5a6a256e
TW
54extern struct iwl_cfg iwl5300_agn_cfg;
55extern struct iwl_cfg iwl5100_agn_cfg;
56extern struct iwl_cfg iwl5350_agn_cfg;
47408639
EK
57extern struct iwl_cfg iwl5100_bg_cfg;
58extern struct iwl_cfg iwl5100_abg_cfg;
7100e924 59extern struct iwl_cfg iwl5150_agn_cfg;
fed9017e 60
099b40b7
RR
61/* CT-KILL constants */
62#define CT_KILL_THRESHOLD 110 /* in Celsius */
4bf775cd 63
5d08cd1d
CH
64/* Default noise level to report when noise measurement is not available.
65 * This may be because we're:
66 * 1) Not associated (4965, no beacon statistics being sent to driver)
67 * 2) Scanning (noise measurement does not apply to associated channel)
68 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
69 * Use default noise value of -127 ... this is below the range of measurable
70 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
71 * Also, -127 works better than 0 when averaging frames with/without
72 * noise info (e.g. averaging might be done in app); measured dBm values are
73 * always negative ... using a negative value as the default keeps all
74 * averages within an s8's (used in some apps) range of negative values. */
75#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
76
5d08cd1d
CH
77/*
78 * RTS threshold here is total size [2347] minus 4 FCS bytes
79 * Per spec:
80 * a value of 0 means RTS on all data/management packets
81 * a value > max MSDU size means no RTS
82 * else RTS for data/management frames where MPDU is larger
83 * than RTS value.
84 */
85#define DEFAULT_RTS_THRESHOLD 2347U
86#define MIN_RTS_THRESHOLD 0U
87#define MAX_RTS_THRESHOLD 2347U
88#define MAX_MSDU_SIZE 2304U
89#define MAX_MPDU_SIZE 2346U
90#define DEFAULT_BEACON_INTERVAL 100U
91#define DEFAULT_SHORT_RETRY_LIMIT 7U
92#define DEFAULT_LONG_RETRY_LIMIT 4U
93
a55360e4 94struct iwl_rx_mem_buffer {
4018517a
JB
95 dma_addr_t real_dma_addr;
96 dma_addr_t aligned_dma_addr;
5d08cd1d
CH
97 struct sk_buff *skb;
98 struct list_head list;
99};
100
5d08cd1d
CH
101/*
102 * Generic queue structure
103 *
104 * Contains common data for Rx and Tx queues
105 */
443cfd45 106struct iwl_queue {
5d08cd1d
CH
107 int n_bd; /* number of BDs in this queue */
108 int write_ptr; /* 1-st empty entry (index) host_w*/
109 int read_ptr; /* last used entry (index) host_r*/
110 dma_addr_t dma_addr; /* physical addr for BD's */
111 int n_window; /* safe queue window */
112 u32 id;
113 int low_mark; /* low watermark, resume queue if free
114 * space more than this */
115 int high_mark; /* high watermark, stop queue if free
116 * space less than this */
117} __attribute__ ((packed));
118
bc47279f 119/* One for each TFD */
8567c63e 120struct iwl_tx_info {
499b1883 121 struct sk_buff *skb[IWL_NUM_OF_TBS - 1];
5d08cd1d
CH
122};
123
124/**
16466903 125 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
126 * @q: generic Rx/Tx queue descriptor
127 * @bd: base of circular buffer of TFDs
128 * @cmd: array of command/Tx buffers
129 * @dma_addr_cmd: physical address of cmd/tx buffer array
130 * @txb: array of per-TFD driver data
131 * @need_update: indicates need to update read/write index
132 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 133 *
bc47279f
BC
134 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
135 * descriptors) and required locking structures.
5d08cd1d 136 */
188cf6c7
SO
137#define TFD_TX_CMD_SLOTS 256
138#define TFD_CMD_SLOTS 32
139
16466903 140struct iwl_tx_queue {
443cfd45 141 struct iwl_queue q;
499b1883 142 struct iwl_tfd *tfds;
188cf6c7 143 struct iwl3945_tfd *tfds39;
da99c4b6 144 struct iwl_cmd *cmd[TFD_TX_CMD_SLOTS];
8567c63e 145 struct iwl_tx_info *txb;
3fd07a1e
TW
146 u8 need_update;
147 u8 sched_retry;
148 u8 active;
149 u8 swq_id;
5d08cd1d
CH
150};
151
152#define IWL_NUM_SCAN_RATES (2)
153
bb8c093b 154struct iwl4965_channel_tgd_info {
5d08cd1d
CH
155 u8 type;
156 s8 max_power;
157};
158
bb8c093b 159struct iwl4965_channel_tgh_info {
5d08cd1d
CH
160 s64 last_radar_time;
161};
162
d20b3c65
SO
163#define IWL4965_MAX_RATE (33)
164
85d41495
KA
165struct iwl3945_clip_group {
166 /* maximum power level to prevent clipping for each rate, derived by
167 * us from this band's saturation power in EEPROM */
168 const s8 clip_powers[IWL_MAX_RATES];
169};
170
d20b3c65
SO
171/* current Tx power values to use, one for each rate for each channel.
172 * requested power is limited by:
173 * -- regulatory EEPROM limits for this channel
174 * -- hardware capabilities (clip-powers)
175 * -- spectrum management
176 * -- user preference (e.g. iwconfig)
177 * when requested power is set, base power index must also be set. */
178struct iwl3945_channel_power_info {
179 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
180 s8 power_table_index; /* actual (compenst'd) index into gain table */
181 s8 base_power_index; /* gain index for power at factory temp. */
182 s8 requested_power; /* power (dBm) requested for this chnl/rate */
183};
184
185/* current scan Tx power values to use, one for each scan rate for each
186 * channel. */
187struct iwl3945_scan_power_info {
188 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
189 s8 power_table_index; /* actual (compenst'd) index into gain table */
190 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
191};
192
5d08cd1d
CH
193/*
194 * One for each channel, holds all channel setup data
195 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
196 * with one another!
197 */
bf85ea4f 198struct iwl_channel_info {
bb8c093b
CH
199 struct iwl4965_channel_tgd_info tgd;
200 struct iwl4965_channel_tgh_info tgh;
073d3f5f
TW
201 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
202 struct iwl_eeprom_channel fat_eeprom; /* EEPROM regulatory limit for
203 * FAT channel */
5d08cd1d
CH
204
205 u8 channel; /* channel number */
206 u8 flags; /* flags copied from EEPROM */
207 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 208 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
209 s8 min_power; /* always 0 */
210 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
211
212 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
213 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 214 enum ieee80211_band band;
5d08cd1d 215
5d08cd1d
CH
216 /* FAT channel info */
217 s8 fat_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
218 s8 fat_curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */
219 s8 fat_min_power; /* always 0 */
220 s8 fat_scan_power; /* (dBm) eeprom, direct scans, any rate */
221 u8 fat_flags; /* flags copied from EEPROM */
fcd427bb 222 u8 fat_extension_channel; /* HT_IE_EXT_CHANNEL_* */
d20b3c65
SO
223
224 /* Radio/DSP gain settings for each "normal" data Tx rate.
225 * These include, in addition to RF and DSP gain, a few fields for
226 * remembering/modifying gain settings (indexes). */
227 struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE];
228
229 /* Radio/DSP gain settings for each scan rate, for directed scans. */
230 struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
5d08cd1d
CH
231};
232
5d08cd1d
CH
233#define IWL_TX_FIFO_AC0 0
234#define IWL_TX_FIFO_AC1 1
235#define IWL_TX_FIFO_AC2 2
236#define IWL_TX_FIFO_AC3 3
237#define IWL_TX_FIFO_HCCA_1 5
238#define IWL_TX_FIFO_HCCA_2 6
239#define IWL_TX_FIFO_NONE 7
240
241/* Minimum number of queues. MAX_NUM is defined in hw specific files */
242#define IWL_MIN_NUM_QUEUES 4
243
244/* Power management (not Tx power) structures */
245
6f4083aa
TW
246enum iwl_pwr_src {
247 IWL_PWR_SRC_VMAIN,
248 IWL_PWR_SRC_VAUX,
249};
250
5d08cd1d
CH
251#define IEEE80211_DATA_LEN 2304
252#define IEEE80211_4ADDR_LEN 30
253#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
254#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
255
fcab423d 256struct iwl_frame {
5d08cd1d
CH
257 union {
258 struct ieee80211_hdr frame;
4bf64efd 259 struct iwl_tx_beacon_cmd beacon;
5d08cd1d
CH
260 u8 raw[IEEE80211_FRAME_LEN];
261 u8 cmd[360];
262 } u;
263 struct list_head list;
264};
265
5d08cd1d
CH
266#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
267#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
268#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
269
270enum {
271 /* CMD_SIZE_NORMAL = 0, */
272 CMD_SIZE_HUGE = (1 << 0),
273 /* CMD_SYNC = 0, */
274 CMD_ASYNC = (1 << 1),
275 /* CMD_NO_SKB = 0, */
276 CMD_WANT_SKB = (1 << 2),
277};
278
857485c0 279struct iwl_cmd;
c79dd5b5 280struct iwl_priv;
5d08cd1d 281
857485c0
TW
282struct iwl_cmd_meta {
283 struct iwl_cmd_meta *source;
5d08cd1d
CH
284 union {
285 struct sk_buff *skb;
c79dd5b5 286 int (*callback)(struct iwl_priv *priv,
857485c0 287 struct iwl_cmd *cmd, struct sk_buff *skb);
5d08cd1d
CH
288 } __attribute__ ((packed)) u;
289
290 /* The CMD_SIZE_HUGE flag bit indicates that the command
291 * structure is stored at the end of the shared queue memory. */
292 u32 flags;
499b1883
TW
293 DECLARE_PCI_UNMAP_ADDR(mapping)
294 DECLARE_PCI_UNMAP_LEN(len)
5d08cd1d
CH
295} __attribute__ ((packed));
296
d2f18bfd 297#define IWL_CMD_MAX_PAYLOAD 320
bd68fb6f 298
bc47279f 299/**
857485c0 300 * struct iwl_cmd
bc47279f
BC
301 *
302 * For allocation of the command and tx queues, this establishes the overall
303 * size of the largest command we send to uCode, except for a scan command
304 * (which is relatively huge; space is allocated separately).
305 */
857485c0
TW
306struct iwl_cmd {
307 struct iwl_cmd_meta meta; /* driver data */
308 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 309 union {
5d08cd1d
CH
310 u32 flags;
311 u8 val8;
312 u16 val16;
313 u32 val32;
83d527d9 314 struct iwl_tx_cmd tx;
bd68fb6f 315 u8 payload[IWL_CMD_MAX_PAYLOAD];
5d08cd1d
CH
316 } __attribute__ ((packed)) cmd;
317} __attribute__ ((packed));
318
3257e5d4 319
857485c0 320struct iwl_host_cmd {
5d08cd1d
CH
321 u8 id;
322 u16 len;
857485c0 323 struct iwl_cmd_meta meta;
5d08cd1d
CH
324 const void *data;
325};
326
857485c0
TW
327#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \
328 sizeof(struct iwl_cmd_meta))
5d08cd1d
CH
329
330/*
331 * RX related structures and functions
332 */
333#define RX_FREE_BUFFERS 64
334#define RX_LOW_WATERMARK 8
335
336#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
337#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
338#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
339
340/**
a55360e4 341 * struct iwl_rx_queue - Rx queue
5d08cd1d
CH
342 * @read: Shared index to newest available Rx buffer
343 * @write: Shared index to oldest written Rx packet
344 * @free_count: Number of pre-allocated buffers in rx_free
345 * @rx_free: list of free SKBs for use
346 * @rx_used: List of Rx buffers with no SKB
347 * @need_update: flag to indicate we need to update read/write index
348 *
a55360e4 349 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 350 */
a55360e4 351struct iwl_rx_queue {
5d08cd1d
CH
352 __le32 *bd;
353 dma_addr_t dma_addr;
a55360e4
TW
354 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
355 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
356 u32 read;
357 u32 write;
358 u32 free_count;
359 struct list_head rx_free;
360 struct list_head rx_used;
361 int need_update;
8d86422a
WT
362 struct iwl_rb_status *rb_stts;
363 dma_addr_t rb_stts_dma;
5d08cd1d
CH
364 spinlock_t lock;
365};
366
367#define IWL_SUPPORTED_RATES_IE_LEN 8
368
5d08cd1d
CH
369#define MAX_TID_COUNT 9
370
371#define IWL_INVALID_RATE 0xFF
372#define IWL_INVALID_VALUE -1
373
bc47279f 374/**
6def9761 375 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
376 * @txq_id: Tx queue used for Tx attempt
377 * @frame_count: # frames attempted by Tx command
378 * @wait_for_ba: Expect block-ack before next Tx reply
379 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
380 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
381 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
382 * @rate_n_flags: Rate at which Tx was attempted
383 *
384 * If REPLY_TX indicates that aggregation was attempted, driver must wait
385 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
386 * until block ack arrives.
387 */
6def9761 388struct iwl_ht_agg {
5d08cd1d
CH
389 u16 txq_id;
390 u16 frame_count;
391 u16 wait_for_ba;
392 u16 start_idx;
fe01b477 393 u64 bitmap;
5d08cd1d 394 u32 rate_n_flags;
fe01b477
RR
395#define IWL_AGG_OFF 0
396#define IWL_AGG_ON 1
397#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
398#define IWL_EMPTYING_HW_QUEUE_DELBA 3
399 u8 state;
5d08cd1d 400};
fe01b477 401
5d08cd1d 402
6def9761 403struct iwl_tid_data {
5d08cd1d 404 u16 seq_number;
fe01b477 405 u16 tfds_in_queue;
6def9761 406 struct iwl_ht_agg agg;
5d08cd1d
CH
407};
408
6def9761 409struct iwl_hw_key {
5d08cd1d
CH
410 enum ieee80211_key_alg alg;
411 int keylen;
0211ddda 412 u8 keyidx;
5d08cd1d
CH
413 u8 key[32];
414};
415
a78fe754 416union iwl_ht_rate_supp {
5d08cd1d
CH
417 u16 rates;
418 struct {
419 u8 siso_rate;
420 u8 mimo_rate;
421 };
422};
423
5d08cd1d 424#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
5d08cd1d
CH
425#define CFG_HT_MPDU_DENSITY_2USEC (0x5)
426#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_2USEC
427
9e0cc6de
RR
428struct iwl_ht_info {
429 /* self configuration data */
5d08cd1d 430 u8 is_ht;
9e0cc6de 431 u8 supported_chan_width;
12837be1 432 u8 sm_ps;
9e0cc6de 433 u8 is_green_field;
bb54244b 434 u8 sgf; /* HT_SHORT_GI_* short guard interval */
5d08cd1d
CH
435 u8 max_amsdu_size;
436 u8 ampdu_factor;
437 u8 mpdu_density;
d9fe60de 438 struct ieee80211_mcs_info mcs;
9e0cc6de 439 /* BSS related data */
5d08cd1d 440 u8 extension_chan_offset;
5d08cd1d 441 u8 tx_chan_width;
9e0cc6de
RR
442 u8 ht_protection;
443 u8 non_GF_STA_present;
5d08cd1d 444};
5d08cd1d 445
1ff50bda 446union iwl_qos_capabity {
5d08cd1d
CH
447 struct {
448 u8 edca_count:4; /* bit 0-3 */
449 u8 q_ack:1; /* bit 4 */
450 u8 queue_request:1; /* bit 5 */
451 u8 txop_request:1; /* bit 6 */
452 u8 reserved:1; /* bit 7 */
453 } q_AP;
454 struct {
455 u8 acvo_APSD:1; /* bit 0 */
456 u8 acvi_APSD:1; /* bit 1 */
457 u8 ac_bk_APSD:1; /* bit 2 */
458 u8 ac_be_APSD:1; /* bit 3 */
459 u8 q_ack:1; /* bit 4 */
460 u8 max_len:2; /* bit 5-6 */
461 u8 more_data_ack:1; /* bit 7 */
462 } q_STA;
463 u8 val;
464};
465
466/* QoS structures */
1ff50bda 467struct iwl_qos_info {
5d08cd1d 468 int qos_active;
1ff50bda
EG
469 union iwl_qos_capabity qos_cap;
470 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 471};
5d08cd1d
CH
472
473#define STA_PS_STATUS_WAKE 0
474#define STA_PS_STATUS_SLEEP 1
475
85d41495
KA
476struct iwl3945_tid_data {
477 u16 seq_number;
478};
479
480struct iwl3945_hw_key {
481 enum ieee80211_key_alg alg;
482 int keylen;
483 u8 key[32];
484};
485
486struct iwl3945_station_entry {
487 struct iwl3945_addsta_cmd sta;
488 struct iwl3945_tid_data tid[MAX_TID_COUNT];
489 u8 used;
490 u8 ps_status;
491 struct iwl3945_hw_key keyinfo;
492};
493
6def9761 494struct iwl_station_entry {
133636de 495 struct iwl_addsta_cmd sta;
6def9761 496 struct iwl_tid_data tid[MAX_TID_COUNT];
5d08cd1d
CH
497 u8 used;
498 u8 ps_status;
6def9761 499 struct iwl_hw_key keyinfo;
5d08cd1d
CH
500};
501
502/* one for each uCode image (inst/data, boot/init/runtime) */
503struct fw_desc {
504 void *v_addr; /* access by driver */
505 dma_addr_t p_addr; /* access by card's busmaster DMA */
506 u32 len; /* bytes */
507};
508
509/* uCode file layout */
14b3d338 510struct iwl_ucode {
c02b3acd 511 __le32 ver; /* major/minor/API/serial */
5d08cd1d
CH
512 __le32 inst_size; /* bytes of runtime instructions */
513 __le32 data_size; /* bytes of runtime data */
514 __le32 init_size; /* bytes of initialization instructions */
515 __le32 init_data_size; /* bytes of initialization data */
516 __le32 boot_size; /* bytes of bootstrap instructions */
517 u8 data[0]; /* data in same order as "size" elements */
518};
519
bb8c093b 520struct iwl4965_ibss_seq {
5d08cd1d
CH
521 u8 mac[ETH_ALEN];
522 u16 seq_num;
523 u16 frag_num;
524 unsigned long packet_time;
525 struct list_head list;
526};
527
f0832f13
EG
528struct iwl_sensitivity_ranges {
529 u16 min_nrg_cck;
530 u16 max_nrg_cck;
531
532 u16 nrg_th_cck;
533 u16 nrg_th_ofdm;
534
535 u16 auto_corr_min_ofdm;
536 u16 auto_corr_min_ofdm_mrc;
537 u16 auto_corr_min_ofdm_x1;
538 u16 auto_corr_min_ofdm_mrc_x1;
539
540 u16 auto_corr_max_ofdm;
541 u16 auto_corr_max_ofdm_mrc;
542 u16 auto_corr_max_ofdm_x1;
543 u16 auto_corr_max_ofdm_mrc_x1;
544
545 u16 auto_corr_max_cck;
546 u16 auto_corr_max_cck_mrc;
547 u16 auto_corr_min_cck;
548 u16 auto_corr_min_cck_mrc;
549};
550
099b40b7 551
b5047f78
TW
552#define KELVIN_TO_CELSIUS(x) ((x)-273)
553#define CELSIUS_TO_KELVIN(x) ((x)+273)
554
555
bc47279f 556/**
5425e490 557 * struct iwl_hw_params
bc47279f 558 * @max_txq_num: Max # Tx queues supported
f3f911d1 559 * @dma_chnl_num: Number of Tx DMA/FIFO channels
4ddbb7d0 560 * @scd_bc_tbls_size: size of scheduler byte count tables
099b40b7
RR
561 * @tx/rx_chains_num: Number of TX/RX chains
562 * @valid_tx/rx_ant: usable antennas
bc47279f 563 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 564 * @max_rxq_log: Log-base-2 of max_rxq_size
099b40b7 565 * @rx_buf_size: Rx buffer size
141c43a3 566 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f
BC
567 * @max_stations:
568 * @bcast_sta_id:
099b40b7
RR
569 * @fat_channel: is 40MHz width possible in band 2.4
570 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
571 * @sw_crypto: 0 for hw, 1 for sw
572 * @max_xxx_size: for ucode uses
573 * @ct_kill_threshold: temperature threshold
a96a27f9 574 * @calib_init_cfg: setup initial calibrations for the hw
f0832f13 575 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 576 */
5425e490 577struct iwl_hw_params {
f3f911d1
ZY
578 u8 max_txq_num;
579 u8 dma_chnl_num;
4ddbb7d0 580 u16 scd_bc_tbls_size;
ec35cf2a
TW
581 u8 tx_chains_num;
582 u8 rx_chains_num;
583 u8 valid_tx_ant;
584 u8 valid_rx_ant;
5d08cd1d 585 u16 max_rxq_size;
ec35cf2a 586 u16 max_rxq_log;
9ee1ba47 587 u32 rx_buf_size;
141c43a3 588 u32 rx_wrt_ptr_reg;
9ee1ba47 589 u32 max_pkt_size;
5d08cd1d
CH
590 u8 max_stations;
591 u8 bcast_sta_id;
099b40b7
RR
592 u8 fat_channel;
593 u8 sw_crypto;
594 u32 max_inst_size;
595 u32 max_data_size;
596 u32 max_bsm_size;
597 u32 ct_kill_threshold; /* value in hw-dependent units */
be5d56ed 598 u32 calib_init_cfg;
f0832f13 599 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
600};
601
5d08cd1d 602
5d08cd1d
CH
603/******************************************************************************
604 *
a33c2f47
EG
605 * Functions implemented in core module which are forward declared here
606 * for use by iwl-[4-5].c
5d08cd1d 607 *
a33c2f47
EG
608 * NOTE: The implementation of these functions are not hardware specific
609 * which is why they are in the core module files.
5d08cd1d
CH
610 *
611 * Naming convention --
a33c2f47 612 * iwl_ <-- Is part of iwlwifi
5d08cd1d 613 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
bb8c093b
CH
614 * iwl4965_bg_ <-- Called from work queue context
615 * iwl4965_mac_ <-- mac80211 callback
5d08cd1d
CH
616 *
617 ****************************************************************************/
5b9f8cd3
EG
618extern void iwl_update_chain_flags(struct iwl_priv *priv);
619extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src);
a33c2f47 620extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 621extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 622extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 623extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
624static inline int iwl_queue_used(const struct iwl_queue *q, int i)
625{
626 return q->write_ptr > q->read_ptr ?
627 (i >= q->read_ptr && i < q->write_ptr) :
628 !(i < q->read_ptr && i >= q->write_ptr);
629}
630
631
632static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge)
633{
634 /* This is for scan command, the big buffer at end of command array */
635 if (is_huge)
636 return q->n_window; /* must be power of 2 */
637
638 /* Otherwise, use normal size buffers */
639 return index & (q->n_window - 1);
640}
641
642
4ddbb7d0
TW
643struct iwl_dma_ptr {
644 dma_addr_t dma;
645 void *addr;
b481de9c
ZY
646 size_t size;
647};
648
34c22cf9
WT
649#define HT_SHORT_GI_20MHZ (1 << 0)
650#define HT_SHORT_GI_40MHZ (1 << 1)
651
b481de9c
ZY
652#define IWL_CHANNEL_WIDTH_20MHZ 0
653#define IWL_CHANNEL_WIDTH_40MHZ 1
654
b481de9c
ZY
655#define IWL_OPERATION_MODE_AUTO 0
656#define IWL_OPERATION_MODE_HT_ONLY 1
657#define IWL_OPERATION_MODE_MIXED 2
658#define IWL_OPERATION_MODE_20MHZ 3
659
3195cdb7
TW
660#define IWL_TX_CRC_SIZE 4
661#define IWL_TX_DELIMITER_SIZE 4
b481de9c 662
b481de9c 663#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 664
b481de9c 665/* Sensitivity and chain noise calibration */
b481de9c
ZY
666#define INITIALIZATION_VALUE 0xFFFF
667#define CAL_NUM_OF_BEACONS 20
668#define MAXIMUM_ALLOWED_PATHLOSS 15
669
b481de9c
ZY
670#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
671
672#define MAX_FA_OFDM 50
673#define MIN_FA_OFDM 5
674#define MAX_FA_CCK 50
675#define MIN_FA_CCK 5
676
b481de9c
ZY
677#define AUTO_CORR_STEP_OFDM 1
678
b481de9c
ZY
679#define AUTO_CORR_STEP_CCK 3
680#define AUTO_CORR_MAX_TH_CCK 160
681
b481de9c
ZY
682#define NRG_DIFF 2
683#define NRG_STEP_CCK 2
684#define NRG_MARGIN 8
685#define MAX_NUMBER_CCK_NO_FA 100
686
687#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
688
689#define CHAIN_A 0
690#define CHAIN_B 1
691#define CHAIN_C 2
692#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
693#define ALL_BAND_FILTER 0xFF00
694#define IN_BAND_FILTER 0xFF
695#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
696
3195cdb7
TW
697#define NRG_NUM_PREV_STAT_L 20
698#define NUM_RX_CHAINS 3
699
bb8c093b 700enum iwl4965_false_alarm_state {
b481de9c
ZY
701 IWL_FA_TOO_MANY = 0,
702 IWL_FA_TOO_FEW = 1,
703 IWL_FA_GOOD_RANGE = 2,
704};
705
bb8c093b 706enum iwl4965_chain_noise_state {
b481de9c 707 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
708 IWL_CHAIN_NOISE_ACCUMULATE,
709 IWL_CHAIN_NOISE_CALIBRATED,
710 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
711};
712
bb8c093b 713enum iwl4965_calib_enabled_state {
b481de9c
ZY
714 IWL_CALIB_DISABLED = 0, /* must be 0 */
715 IWL_CALIB_ENABLED = 1,
716};
717
f69f42a6
TW
718
719/*
720 * enum iwl_calib
721 * defines the order in which results of initial calibrations
722 * should be sent to the runtime uCode
723 */
724enum iwl_calib {
725 IWL_CALIB_XTAL,
819500c5 726 IWL_CALIB_DC,
f69f42a6
TW
727 IWL_CALIB_LO,
728 IWL_CALIB_TX_IQ,
729 IWL_CALIB_TX_IQ_PERD,
201706ac 730 IWL_CALIB_BASE_BAND,
f69f42a6
TW
731 IWL_CALIB_MAX
732};
733
6e21f2c1
TW
734/* Opaque calibration results */
735struct iwl_calib_result {
736 void *buf;
737 size_t buf_len;
7c616cba
TW
738};
739
dbb983b7
RR
740enum ucode_type {
741 UCODE_NONE = 0,
742 UCODE_INIT,
743 UCODE_RT
744};
745
b481de9c 746/* Sensitivity calib data */
f0832f13 747struct iwl_sensitivity_data {
b481de9c
ZY
748 u32 auto_corr_ofdm;
749 u32 auto_corr_ofdm_mrc;
750 u32 auto_corr_ofdm_x1;
751 u32 auto_corr_ofdm_mrc_x1;
752 u32 auto_corr_cck;
753 u32 auto_corr_cck_mrc;
754
755 u32 last_bad_plcp_cnt_ofdm;
756 u32 last_fa_cnt_ofdm;
757 u32 last_bad_plcp_cnt_cck;
758 u32 last_fa_cnt_cck;
759
760 u32 nrg_curr_state;
761 u32 nrg_prev_state;
762 u32 nrg_value[10];
763 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
764 u32 nrg_silence_ref;
765 u32 nrg_energy_idx;
766 u32 nrg_silence_idx;
767 u32 nrg_th_cck;
768 s32 nrg_auto_corr_silence_diff;
769 u32 num_in_cck_no_fa;
770 u32 nrg_th_ofdm;
b481de9c
ZY
771};
772
773/* Chain noise (differential Rx gain) calib data */
f0832f13 774struct iwl_chain_noise_data {
04816448 775 u32 active_chains;
b481de9c
ZY
776 u32 chain_noise_a;
777 u32 chain_noise_b;
778 u32 chain_noise_c;
779 u32 chain_signal_a;
780 u32 chain_signal_b;
781 u32 chain_signal_c;
04816448 782 u16 beacon_count;
b481de9c
ZY
783 u8 disconn_array[NUM_RX_CHAINS];
784 u8 delta_gain_code[NUM_RX_CHAINS];
785 u8 radio_write;
04816448 786 u8 state;
b481de9c
ZY
787};
788
abceddb4
BC
789#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
790#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 791
5d08cd1d 792
5d08cd1d
CH
793enum {
794 MEASUREMENT_READY = (1 << 0),
795 MEASUREMENT_ACTIVE = (1 << 1),
796};
797
5d08cd1d 798
dfe7d458
RR
799#define IWL_MAX_NUM_QUEUES 20 /* FIXME: do dynamic allocation */
800
c79dd5b5 801struct iwl_priv {
5d08cd1d
CH
802
803 /* ieee device used by generic ieee processing code */
804 struct ieee80211_hw *hw;
805 struct ieee80211_channel *ieee_channels;
806 struct ieee80211_rate *ieee_rates;
82b9a121 807 struct iwl_cfg *cfg;
5d08cd1d
CH
808
809 /* temporary frame storage list */
810 struct list_head free_frames;
811 int frames_count;
812
8318d78a 813 enum ieee80211_band band;
5d08cd1d
CH
814 int alloc_rxb_skb;
815
c79dd5b5 816 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 817 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 818
8318d78a 819 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 820
4a8a4322 821#if defined(CONFIG_IWLAGN_SPECTRUM_MEASUREMENT) || defined(CONFIG_IWL3945_SPECTRUM_MEASUREMENT)
5d08cd1d 822 /* spectrum measurement report caching */
2aa6ab86 823 struct iwl_spectrum_notification measure_report;
5d08cd1d
CH
824 u8 measurement_status;
825#endif
826 /* ucode beacon time */
827 u32 ucode_beacon_time;
828
bb8c093b 829 /* we allocate array of iwl4965_channel_info for NIC's valid channels.
5d08cd1d 830 * Access via channel # using indirect index array */
bf85ea4f 831 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
832 u8 channel_count; /* # of channels */
833
85d41495
KA
834 /* each calibration channel group in the EEPROM has a derived
835 * clip setting for each rate. 3945 only.*/
836 const struct iwl3945_clip_group clip39_groups[5];
837
5d08cd1d
CH
838 /* thermal calibration */
839 s32 temperature; /* degrees Kelvin */
840 s32 last_temperature;
841
7c616cba 842 /* init calibration results */
6e21f2c1 843 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 844
5d08cd1d
CH
845 /* Scan related variables */
846 unsigned long last_scan_jiffies;
7878a5a4 847 unsigned long next_scan_jiffies;
5d08cd1d
CH
848 unsigned long scan_start;
849 unsigned long scan_pass_start;
850 unsigned long scan_start_tsf;
76eff18b 851 struct iwl_scan_cmd *scan;
5d08cd1d
CH
852 int scan_bands;
853 int one_direct_scan;
854 u8 direct_ssid_len;
855 u8 direct_ssid[IW_ESSID_MAX_SIZE];
76eff18b
TW
856 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
857 u8 mgmt_tx_ant;
5d08cd1d
CH
858
859 /* spinlock */
860 spinlock_t lock; /* protect general shared data */
861 spinlock_t hcmd_lock; /* protect hcmd */
862 struct mutex mutex;
863
864 /* basic pci-network driver stuff */
865 struct pci_dev *pci_dev;
866
867 /* pci hardware address support */
868 void __iomem *hw_base;
b661c819
TW
869 u32 hw_rev;
870 u32 hw_wa_rev;
871 u8 rev_id;
5d08cd1d
CH
872
873 /* uCode images, save to reload in case of failure */
c02b3acd
CR
874 u32 ucode_ver; /* version of ucode, copy of
875 iwl_ucode.ver */
5d08cd1d
CH
876 struct fw_desc ucode_code; /* runtime inst */
877 struct fw_desc ucode_data; /* runtime data original */
878 struct fw_desc ucode_data_backup; /* runtime data save/restore */
879 struct fw_desc ucode_init; /* initialization inst */
880 struct fw_desc ucode_init_data; /* initialization data */
881 struct fw_desc ucode_boot; /* bootstrap inst */
dbb983b7
RR
882 enum ucode_type ucode_type;
883 u8 ucode_write_complete; /* the image write is complete */
5d08cd1d
CH
884
885
3195c1f3 886 struct iwl_rxon_time_cmd rxon_timing;
5d08cd1d
CH
887
888 /* We declare this const so it can only be
889 * changed via explicit cast within the
890 * routines that actually update the physical
891 * hardware */
c1adf9fb
GG
892 const struct iwl_rxon_cmd active_rxon;
893 struct iwl_rxon_cmd staging_rxon;
5d08cd1d
CH
894
895 int error_recovering;
c1adf9fb 896 struct iwl_rxon_cmd recovery_rxon;
5d08cd1d
CH
897
898 /* 1st responses from initialize and runtime uCode images.
899 * 4965's initialize alive response contains some calibration data. */
885ba202
TW
900 struct iwl_init_alive_resp card_alive_init;
901 struct iwl_alive_resp card_alive;
4a8a4322 902#if defined(CONFIG_IWLWIFI_RFKILL) || defined(CONFIG_IWL3945_RFKILL)
80fcc9e2 903 struct rfkill *rfkill;
ad97edd2 904#endif
5d08cd1d 905
4a8a4322 906#if defined(CONFIG_IWLWIFI_LEDS) || defined(CONFIG_IWL3945_LEDS)
ab53d8af
MA
907 unsigned long last_blink_time;
908 u8 last_blink_rate;
909 u8 allow_blinking;
910 u64 led_tpt;
5d08cd1d
CH
911#endif
912
4a8a4322
AK
913#ifdef CONFIG_IWLWIFI_LEDS
914 struct iwl_led led[IWL_LED_TRG_MAX];
915#endif
916
917#ifdef CONFIG_IWL3945_LEDS
918 struct iwl3945_led led39[IWL_LED_TRG_MAX];
919 unsigned int rxtxpackets;
920#endif
5d08cd1d
CH
921 u16 active_rate;
922 u16 active_rate_basic;
923
5d08cd1d 924 u8 assoc_station_added;
5d08cd1d 925 u8 start_calib;
f0832f13
EG
926 struct iwl_sensitivity_data sensitivity_data;
927 struct iwl_chain_noise_data chain_noise_data;
5d08cd1d 928 __le16 sensitivity_tbl[HD_TABLE_SIZE];
5d08cd1d 929
9e0cc6de 930 struct iwl_ht_info current_ht_config;
5d08cd1d
CH
931 u8 last_phy_res[100];
932
5d08cd1d
CH
933 /* Rate scaling data */
934 s8 data_retry_limit;
935 u8 retry_rate;
936
937 wait_queue_head_t wait_command_queue;
938
939 int activity_timer_active;
940
941 /* Rx and Tx DMA processing queues */
a55360e4 942 struct iwl_rx_queue rxq;
16466903 943 struct iwl_tx_queue txq[IWL_MAX_NUM_QUEUES];
5d08cd1d 944 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
945 struct iwl_dma_ptr kw; /* keep warm address */
946 struct iwl_dma_ptr scd_bc_tbls;
947
5d08cd1d
CH
948 u32 scd_base_addr; /* scheduler sram base address */
949
950 unsigned long status;
5d08cd1d 951
a96a27f9 952 int last_rx_rssi; /* From Rx packet statistics */
5d08cd1d
CH
953 int last_rx_noise; /* From beacon statistics */
954
19758bef
TW
955 /* counts mgmt, ctl, and data packets */
956 struct traffic_stats {
957 u32 cnt;
958 u64 bytes;
959 } tx_stats[3], rx_stats[3];
960
5da4b55f 961 struct iwl_power_mgr power_data;
5d08cd1d 962
8f91aecb 963 struct iwl_notif_statistics statistics;
5d08cd1d
CH
964 unsigned long last_statistics_time;
965
966 /* context information */
5d08cd1d
CH
967 u16 rates_mask;
968
969 u32 power_mode;
970 u32 antenna;
971 u8 bssid[ETH_ALEN];
972 u16 rts_threshold;
973 u8 mac_addr[ETH_ALEN];
974
975 /*station table variables */
976 spinlock_t sta_lock;
977 int num_stations;
6def9761 978 struct iwl_station_entry stations[IWL_STATION_COUNT];
6974e363
EG
979 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
980 u8 default_wep_key;
981 u8 key_mapping_key;
80fb47a1 982 unsigned long ucode_key_table;
5d08cd1d
CH
983
984 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 985 u8 is_open;
5d08cd1d
CH
986
987 u8 mac80211_registered;
5d08cd1d 988
5d08cd1d
CH
989 /* Rx'd packet timing information */
990 u32 last_beacon_time;
991 u64 last_tsf;
992
5d08cd1d 993 /* eeprom */
073d3f5f
TW
994 u8 *eeprom;
995 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 996
05c914fe 997 enum nl80211_iftype iw_mode;
5d08cd1d
CH
998
999 struct sk_buff *ibss_beacon;
1000
1001 /* Last Rx'd beacon timestamp */
3109ece1 1002 u64 timestamp;
5d08cd1d 1003 u16 beacon_int;
32bfd35d 1004 struct ieee80211_vif *vif;
5d08cd1d 1005
8cd812bc 1006 /*Added for 3945 */
3832ec9d
AK
1007 void *shared_virt;
1008 dma_addr_t shared_phys;
1009 /*End*/
5425e490 1010 struct iwl_hw_params hw_params;
4ddbb7d0 1011
059ff826 1012
5d08cd1d
CH
1013 /* Current association information needed to configure the
1014 * hardware */
1015 u16 assoc_id;
1016 u16 assoc_capability;
5d08cd1d 1017
1ff50bda 1018 struct iwl_qos_info qos_data;
5d08cd1d
CH
1019
1020 struct workqueue_struct *workqueue;
1021
1022 struct work_struct up;
1023 struct work_struct restart;
1024 struct work_struct calibrated_work;
1025 struct work_struct scan_completed;
1026 struct work_struct rx_replenish;
1027 struct work_struct rf_kill;
1028 struct work_struct abort_scan;
1029 struct work_struct update_link_led;
1030 struct work_struct auth_work;
1031 struct work_struct report_work;
1032 struct work_struct request_scan;
1033 struct work_struct beacon_update;
1034
1035 struct tasklet_struct irq_tasklet;
1036
c90a74ba 1037 struct delayed_work set_power_save;
5d08cd1d
CH
1038 struct delayed_work init_alive_start;
1039 struct delayed_work alive_start;
5d08cd1d 1040 struct delayed_work scan_check;
4a8a4322
AK
1041
1042 /*For 3945 only*/
1043 struct delayed_work thermal_periodic;
1044
630fe9b6
TW
1045 /* TX Power */
1046 s8 tx_power_user_lmt;
1047 s8 tx_power_channel_lmt;
5d08cd1d 1048
5d08cd1d 1049
4a8a4322 1050#if defined(CONFIG_IWLWIFI_DEBUG) || defined(CONFIG_IWL3945_DEBUG)
5d08cd1d 1051 /* debugging info */
bf403db8 1052 u32 debug_level;
5d08cd1d
CH
1053 u32 framecnt_to_us;
1054 atomic_t restrict_refcnt;
712b6cf5
TW
1055#ifdef CONFIG_IWLWIFI_DEBUGFS
1056 /* debugfs */
1057 struct iwl_debugfs *dbgfs;
1058#endif /* CONFIG_IWLWIFI_DEBUGFS */
1059#endif /* CONFIG_IWLWIFI_DEBUG */
5d08cd1d
CH
1060
1061 struct work_struct txpower_work;
445c2dff
TW
1062 u32 disable_sens_cal;
1063 u32 disable_chain_noise_cal;
203566f3 1064 u32 disable_tx_power_cal;
16e727e8 1065 struct work_struct run_time_calib_work;
5d08cd1d 1066 struct timer_list statistics_periodic;
4a8a4322
AK
1067
1068 /*For 3945*/
1069#define IWL_DEFAULT_TX_POWER 0x0F
1070 s8 user_txpower_limit;
1071 s8 max_channel_txpower_limit;
1072
1073 struct iwl3945_scan_cmd *scan39;
1074
1075 /* We declare this const so it can only be
1076 * changed via explicit cast within the
1077 * routines that actually update the physical
1078 * hardware */
1079 const struct iwl3945_rxon_cmd active39_rxon;
1080 struct iwl3945_rxon_cmd staging39_rxon;
1081 struct iwl3945_rxon_cmd recovery39_rxon;
1082
4a8a4322
AK
1083 struct iwl3945_power_mgr power_data_39;
1084 struct iwl3945_notif_statistics statistics_39;
1085
1086 struct iwl3945_station_entry stations_39[IWL_STATION_COUNT];
1087
1088 /* eeprom */
1089 struct iwl3945_eeprom eeprom39;
1090
1091 u32 sta_supp_rates;
1092 u8 call_post_assoc_from_beacon;
1093
c79dd5b5 1094}; /*iwl_priv */
5d08cd1d 1095
36470749
RR
1096static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1097{
1098 set_bit(txq_id, &priv->txq_ctx_active_msk);
1099}
1100
1101static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1102{
1103 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1104}
1105
994d31f7 1106#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6
TW
1107const char *iwl_get_tx_fail_reason(u32 status);
1108#else
1109static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; }
1110#endif
1111
1112
a332f8d6
TW
1113static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1114 int txq_id, int idx)
1115{
1116 if (priv->txq[txq_id].txb[idx].skb[0])
1117 return (struct ieee80211_hdr *)priv->txq[txq_id].
1118 txb[idx].skb[0]->data;
1119 return NULL;
1120}
a332f8d6
TW
1121
1122
3109ece1 1123static inline int iwl_is_associated(struct iwl_priv *priv)
5d08cd1d
CH
1124{
1125 return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1126}
1127
bf85ea4f 1128static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1129{
1130 if (ch_info == NULL)
1131 return 0;
1132 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1133}
1134
bf85ea4f 1135static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1136{
1137 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1138}
1139
bf85ea4f 1140static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1141{
8318d78a 1142 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1143}
1144
bf85ea4f 1145static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1146{
8318d78a 1147 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1148}
1149
bf85ea4f 1150static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1151{
1152 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1153}
1154
bf85ea4f 1155static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1156{
1157 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1158}
1159
be1f3ab6 1160#endif /* __iwl_dev_h__ */
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