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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
eb7ae89c | 3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
759ef89f | 22 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
24 | * | |
25 | *****************************************************************************/ | |
fcd427bb | 26 | /* |
3e0d4cb1 | 27 | * Please use this file (iwl-dev.h) for driver implementation definitions. |
5a36ba0e | 28 | * Please use iwl-commands.h for uCode API definitions. |
fcd427bb BC |
29 | * Please use iwl-4965-hw.h for hardware-related definitions. |
30 | */ | |
31 | ||
be1f3ab6 EG |
32 | #ifndef __iwl_dev_h__ |
33 | #define __iwl_dev_h__ | |
b481de9c | 34 | |
5d08cd1d CH |
35 | #include <linux/pci.h> /* for struct pci_device_id */ |
36 | #include <linux/kernel.h> | |
37 | #include <net/ieee80211_radiotap.h> | |
38 | ||
ad97edd2 | 39 | #include "iwl-rfkill.h" |
6bc913bd | 40 | #include "iwl-eeprom.h" |
5d08cd1d | 41 | #include "iwl-4965-hw.h" |
d20b3c65 | 42 | #include "iwl-3945-hw.h" |
6f83eaa1 | 43 | #include "iwl-csr.h" |
5d08cd1d | 44 | #include "iwl-prph.h" |
0a6857e7 | 45 | #include "iwl-debug.h" |
ab53d8af | 46 | #include "iwl-led.h" |
5da4b55f | 47 | #include "iwl-power.h" |
e227ceac | 48 | #include "iwl-agn-rs.h" |
5d08cd1d | 49 | |
fed9017e RR |
50 | /* configuration for the iwl4965 */ |
51 | extern struct iwl_cfg iwl4965_agn_cfg; | |
5a6a256e TW |
52 | extern struct iwl_cfg iwl5300_agn_cfg; |
53 | extern struct iwl_cfg iwl5100_agn_cfg; | |
54 | extern struct iwl_cfg iwl5350_agn_cfg; | |
47408639 EK |
55 | extern struct iwl_cfg iwl5100_bg_cfg; |
56 | extern struct iwl_cfg iwl5100_abg_cfg; | |
7100e924 | 57 | extern struct iwl_cfg iwl5150_agn_cfg; |
fed9017e | 58 | |
099b40b7 RR |
59 | /* CT-KILL constants */ |
60 | #define CT_KILL_THRESHOLD 110 /* in Celsius */ | |
4bf775cd | 61 | |
5d08cd1d CH |
62 | /* Default noise level to report when noise measurement is not available. |
63 | * This may be because we're: | |
64 | * 1) Not associated (4965, no beacon statistics being sent to driver) | |
65 | * 2) Scanning (noise measurement does not apply to associated channel) | |
66 | * 3) Receiving CCK (3945 delivers noise info only for OFDM frames) | |
67 | * Use default noise value of -127 ... this is below the range of measurable | |
68 | * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user. | |
69 | * Also, -127 works better than 0 when averaging frames with/without | |
70 | * noise info (e.g. averaging might be done in app); measured dBm values are | |
71 | * always negative ... using a negative value as the default keeps all | |
72 | * averages within an s8's (used in some apps) range of negative values. */ | |
73 | #define IWL_NOISE_MEAS_NOT_AVAILABLE (-127) | |
74 | ||
5d08cd1d CH |
75 | /* |
76 | * RTS threshold here is total size [2347] minus 4 FCS bytes | |
77 | * Per spec: | |
78 | * a value of 0 means RTS on all data/management packets | |
79 | * a value > max MSDU size means no RTS | |
80 | * else RTS for data/management frames where MPDU is larger | |
81 | * than RTS value. | |
82 | */ | |
83 | #define DEFAULT_RTS_THRESHOLD 2347U | |
84 | #define MIN_RTS_THRESHOLD 0U | |
85 | #define MAX_RTS_THRESHOLD 2347U | |
86 | #define MAX_MSDU_SIZE 2304U | |
87 | #define MAX_MPDU_SIZE 2346U | |
88 | #define DEFAULT_BEACON_INTERVAL 100U | |
89 | #define DEFAULT_SHORT_RETRY_LIMIT 7U | |
90 | #define DEFAULT_LONG_RETRY_LIMIT 4U | |
91 | ||
a55360e4 | 92 | struct iwl_rx_mem_buffer { |
4018517a JB |
93 | dma_addr_t real_dma_addr; |
94 | dma_addr_t aligned_dma_addr; | |
5d08cd1d CH |
95 | struct sk_buff *skb; |
96 | struct list_head list; | |
97 | }; | |
98 | ||
5d08cd1d CH |
99 | /* |
100 | * Generic queue structure | |
101 | * | |
102 | * Contains common data for Rx and Tx queues | |
103 | */ | |
443cfd45 | 104 | struct iwl_queue { |
5d08cd1d CH |
105 | int n_bd; /* number of BDs in this queue */ |
106 | int write_ptr; /* 1-st empty entry (index) host_w*/ | |
107 | int read_ptr; /* last used entry (index) host_r*/ | |
108 | dma_addr_t dma_addr; /* physical addr for BD's */ | |
109 | int n_window; /* safe queue window */ | |
110 | u32 id; | |
111 | int low_mark; /* low watermark, resume queue if free | |
112 | * space more than this */ | |
113 | int high_mark; /* high watermark, stop queue if free | |
114 | * space less than this */ | |
115 | } __attribute__ ((packed)); | |
116 | ||
bc47279f | 117 | /* One for each TFD */ |
8567c63e | 118 | struct iwl_tx_info { |
499b1883 | 119 | struct sk_buff *skb[IWL_NUM_OF_TBS - 1]; |
5d08cd1d CH |
120 | }; |
121 | ||
122 | /** | |
16466903 | 123 | * struct iwl_tx_queue - Tx Queue for DMA |
bc47279f BC |
124 | * @q: generic Rx/Tx queue descriptor |
125 | * @bd: base of circular buffer of TFDs | |
126 | * @cmd: array of command/Tx buffers | |
127 | * @dma_addr_cmd: physical address of cmd/tx buffer array | |
128 | * @txb: array of per-TFD driver data | |
129 | * @need_update: indicates need to update read/write index | |
130 | * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled | |
5d08cd1d | 131 | * |
bc47279f BC |
132 | * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame |
133 | * descriptors) and required locking structures. | |
5d08cd1d | 134 | */ |
16466903 | 135 | struct iwl_tx_queue { |
443cfd45 | 136 | struct iwl_queue q; |
499b1883 | 137 | struct iwl_tfd *tfds; |
da99c4b6 | 138 | struct iwl_cmd *cmd[TFD_TX_CMD_SLOTS]; |
8567c63e | 139 | struct iwl_tx_info *txb; |
3fd07a1e TW |
140 | u8 need_update; |
141 | u8 sched_retry; | |
142 | u8 active; | |
143 | u8 swq_id; | |
5d08cd1d CH |
144 | }; |
145 | ||
146 | #define IWL_NUM_SCAN_RATES (2) | |
147 | ||
bb8c093b | 148 | struct iwl4965_channel_tgd_info { |
5d08cd1d CH |
149 | u8 type; |
150 | s8 max_power; | |
151 | }; | |
152 | ||
bb8c093b | 153 | struct iwl4965_channel_tgh_info { |
5d08cd1d CH |
154 | s64 last_radar_time; |
155 | }; | |
156 | ||
d20b3c65 SO |
157 | #define IWL4965_MAX_RATE (33) |
158 | ||
159 | /* current Tx power values to use, one for each rate for each channel. | |
160 | * requested power is limited by: | |
161 | * -- regulatory EEPROM limits for this channel | |
162 | * -- hardware capabilities (clip-powers) | |
163 | * -- spectrum management | |
164 | * -- user preference (e.g. iwconfig) | |
165 | * when requested power is set, base power index must also be set. */ | |
166 | struct iwl3945_channel_power_info { | |
167 | struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */ | |
168 | s8 power_table_index; /* actual (compenst'd) index into gain table */ | |
169 | s8 base_power_index; /* gain index for power at factory temp. */ | |
170 | s8 requested_power; /* power (dBm) requested for this chnl/rate */ | |
171 | }; | |
172 | ||
173 | /* current scan Tx power values to use, one for each scan rate for each | |
174 | * channel. */ | |
175 | struct iwl3945_scan_power_info { | |
176 | struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */ | |
177 | s8 power_table_index; /* actual (compenst'd) index into gain table */ | |
178 | s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */ | |
179 | }; | |
180 | ||
5d08cd1d CH |
181 | /* |
182 | * One for each channel, holds all channel setup data | |
183 | * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant | |
184 | * with one another! | |
185 | */ | |
bf85ea4f | 186 | struct iwl_channel_info { |
bb8c093b CH |
187 | struct iwl4965_channel_tgd_info tgd; |
188 | struct iwl4965_channel_tgh_info tgh; | |
073d3f5f TW |
189 | struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */ |
190 | struct iwl_eeprom_channel fat_eeprom; /* EEPROM regulatory limit for | |
191 | * FAT channel */ | |
5d08cd1d CH |
192 | |
193 | u8 channel; /* channel number */ | |
194 | u8 flags; /* flags copied from EEPROM */ | |
195 | s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
fcd427bb | 196 | s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */ |
5d08cd1d CH |
197 | s8 min_power; /* always 0 */ |
198 | s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */ | |
199 | ||
200 | u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */ | |
201 | u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */ | |
8318d78a | 202 | enum ieee80211_band band; |
5d08cd1d | 203 | |
5d08cd1d CH |
204 | /* FAT channel info */ |
205 | s8 fat_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
206 | s8 fat_curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */ | |
207 | s8 fat_min_power; /* always 0 */ | |
208 | s8 fat_scan_power; /* (dBm) eeprom, direct scans, any rate */ | |
209 | u8 fat_flags; /* flags copied from EEPROM */ | |
fcd427bb | 210 | u8 fat_extension_channel; /* HT_IE_EXT_CHANNEL_* */ |
d20b3c65 SO |
211 | |
212 | /* Radio/DSP gain settings for each "normal" data Tx rate. | |
213 | * These include, in addition to RF and DSP gain, a few fields for | |
214 | * remembering/modifying gain settings (indexes). */ | |
215 | struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE]; | |
216 | ||
217 | /* Radio/DSP gain settings for each scan rate, for directed scans. */ | |
218 | struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES]; | |
5d08cd1d CH |
219 | }; |
220 | ||
5d08cd1d CH |
221 | |
222 | #define IWL_TX_FIFO_AC0 0 | |
223 | #define IWL_TX_FIFO_AC1 1 | |
224 | #define IWL_TX_FIFO_AC2 2 | |
225 | #define IWL_TX_FIFO_AC3 3 | |
226 | #define IWL_TX_FIFO_HCCA_1 5 | |
227 | #define IWL_TX_FIFO_HCCA_2 6 | |
228 | #define IWL_TX_FIFO_NONE 7 | |
229 | ||
230 | /* Minimum number of queues. MAX_NUM is defined in hw specific files */ | |
231 | #define IWL_MIN_NUM_QUEUES 4 | |
232 | ||
233 | /* Power management (not Tx power) structures */ | |
234 | ||
6f4083aa TW |
235 | enum iwl_pwr_src { |
236 | IWL_PWR_SRC_VMAIN, | |
237 | IWL_PWR_SRC_VAUX, | |
238 | }; | |
239 | ||
5d08cd1d CH |
240 | #define IEEE80211_DATA_LEN 2304 |
241 | #define IEEE80211_4ADDR_LEN 30 | |
242 | #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) | |
243 | #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) | |
244 | ||
fcab423d | 245 | struct iwl_frame { |
5d08cd1d CH |
246 | union { |
247 | struct ieee80211_hdr frame; | |
4bf64efd | 248 | struct iwl_tx_beacon_cmd beacon; |
5d08cd1d CH |
249 | u8 raw[IEEE80211_FRAME_LEN]; |
250 | u8 cmd[360]; | |
251 | } u; | |
252 | struct list_head list; | |
253 | }; | |
254 | ||
5d08cd1d CH |
255 | #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) |
256 | #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) | |
257 | #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) | |
258 | ||
259 | enum { | |
260 | /* CMD_SIZE_NORMAL = 0, */ | |
261 | CMD_SIZE_HUGE = (1 << 0), | |
262 | /* CMD_SYNC = 0, */ | |
263 | CMD_ASYNC = (1 << 1), | |
264 | /* CMD_NO_SKB = 0, */ | |
265 | CMD_WANT_SKB = (1 << 2), | |
266 | }; | |
267 | ||
857485c0 | 268 | struct iwl_cmd; |
c79dd5b5 | 269 | struct iwl_priv; |
5d08cd1d | 270 | |
857485c0 TW |
271 | struct iwl_cmd_meta { |
272 | struct iwl_cmd_meta *source; | |
5d08cd1d CH |
273 | union { |
274 | struct sk_buff *skb; | |
c79dd5b5 | 275 | int (*callback)(struct iwl_priv *priv, |
857485c0 | 276 | struct iwl_cmd *cmd, struct sk_buff *skb); |
5d08cd1d CH |
277 | } __attribute__ ((packed)) u; |
278 | ||
279 | /* The CMD_SIZE_HUGE flag bit indicates that the command | |
280 | * structure is stored at the end of the shared queue memory. */ | |
281 | u32 flags; | |
499b1883 TW |
282 | DECLARE_PCI_UNMAP_ADDR(mapping) |
283 | DECLARE_PCI_UNMAP_LEN(len) | |
5d08cd1d CH |
284 | } __attribute__ ((packed)); |
285 | ||
d2f18bfd | 286 | #define IWL_CMD_MAX_PAYLOAD 320 |
bd68fb6f | 287 | |
bc47279f | 288 | /** |
857485c0 | 289 | * struct iwl_cmd |
bc47279f BC |
290 | * |
291 | * For allocation of the command and tx queues, this establishes the overall | |
292 | * size of the largest command we send to uCode, except for a scan command | |
293 | * (which is relatively huge; space is allocated separately). | |
294 | */ | |
857485c0 TW |
295 | struct iwl_cmd { |
296 | struct iwl_cmd_meta meta; /* driver data */ | |
297 | struct iwl_cmd_header hdr; /* uCode API */ | |
5d08cd1d | 298 | union { |
5d08cd1d CH |
299 | u32 flags; |
300 | u8 val8; | |
301 | u16 val16; | |
302 | u32 val32; | |
83d527d9 | 303 | struct iwl_tx_cmd tx; |
bd68fb6f | 304 | u8 payload[IWL_CMD_MAX_PAYLOAD]; |
5d08cd1d CH |
305 | } __attribute__ ((packed)) cmd; |
306 | } __attribute__ ((packed)); | |
307 | ||
3257e5d4 | 308 | |
857485c0 | 309 | struct iwl_host_cmd { |
5d08cd1d CH |
310 | u8 id; |
311 | u16 len; | |
857485c0 | 312 | struct iwl_cmd_meta meta; |
5d08cd1d CH |
313 | const void *data; |
314 | }; | |
315 | ||
857485c0 TW |
316 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \ |
317 | sizeof(struct iwl_cmd_meta)) | |
5d08cd1d CH |
318 | |
319 | /* | |
320 | * RX related structures and functions | |
321 | */ | |
322 | #define RX_FREE_BUFFERS 64 | |
323 | #define RX_LOW_WATERMARK 8 | |
324 | ||
325 | #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 | |
326 | #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 | |
327 | #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 | |
328 | ||
329 | /** | |
a55360e4 | 330 | * struct iwl_rx_queue - Rx queue |
5d08cd1d CH |
331 | * @read: Shared index to newest available Rx buffer |
332 | * @write: Shared index to oldest written Rx packet | |
333 | * @free_count: Number of pre-allocated buffers in rx_free | |
334 | * @rx_free: list of free SKBs for use | |
335 | * @rx_used: List of Rx buffers with no SKB | |
336 | * @need_update: flag to indicate we need to update read/write index | |
337 | * | |
a55360e4 | 338 | * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers |
5d08cd1d | 339 | */ |
a55360e4 | 340 | struct iwl_rx_queue { |
5d08cd1d CH |
341 | __le32 *bd; |
342 | dma_addr_t dma_addr; | |
a55360e4 TW |
343 | struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; |
344 | struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; | |
5d08cd1d CH |
345 | u32 read; |
346 | u32 write; | |
347 | u32 free_count; | |
348 | struct list_head rx_free; | |
349 | struct list_head rx_used; | |
350 | int need_update; | |
8d86422a WT |
351 | struct iwl_rb_status *rb_stts; |
352 | dma_addr_t rb_stts_dma; | |
5d08cd1d CH |
353 | spinlock_t lock; |
354 | }; | |
355 | ||
356 | #define IWL_SUPPORTED_RATES_IE_LEN 8 | |
357 | ||
5d08cd1d CH |
358 | #define MAX_TID_COUNT 9 |
359 | ||
360 | #define IWL_INVALID_RATE 0xFF | |
361 | #define IWL_INVALID_VALUE -1 | |
362 | ||
bc47279f | 363 | /** |
6def9761 | 364 | * struct iwl_ht_agg -- aggregation status while waiting for block-ack |
bc47279f BC |
365 | * @txq_id: Tx queue used for Tx attempt |
366 | * @frame_count: # frames attempted by Tx command | |
367 | * @wait_for_ba: Expect block-ack before next Tx reply | |
368 | * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window | |
369 | * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window | |
370 | * @bitmap1: High order, one bit for each frame pending ACK in Tx window | |
371 | * @rate_n_flags: Rate at which Tx was attempted | |
372 | * | |
373 | * If REPLY_TX indicates that aggregation was attempted, driver must wait | |
374 | * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info | |
375 | * until block ack arrives. | |
376 | */ | |
6def9761 | 377 | struct iwl_ht_agg { |
5d08cd1d CH |
378 | u16 txq_id; |
379 | u16 frame_count; | |
380 | u16 wait_for_ba; | |
381 | u16 start_idx; | |
fe01b477 | 382 | u64 bitmap; |
5d08cd1d | 383 | u32 rate_n_flags; |
fe01b477 RR |
384 | #define IWL_AGG_OFF 0 |
385 | #define IWL_AGG_ON 1 | |
386 | #define IWL_EMPTYING_HW_QUEUE_ADDBA 2 | |
387 | #define IWL_EMPTYING_HW_QUEUE_DELBA 3 | |
388 | u8 state; | |
5d08cd1d | 389 | }; |
fe01b477 | 390 | |
5d08cd1d | 391 | |
6def9761 | 392 | struct iwl_tid_data { |
5d08cd1d | 393 | u16 seq_number; |
fe01b477 | 394 | u16 tfds_in_queue; |
6def9761 | 395 | struct iwl_ht_agg agg; |
5d08cd1d CH |
396 | }; |
397 | ||
6def9761 | 398 | struct iwl_hw_key { |
5d08cd1d CH |
399 | enum ieee80211_key_alg alg; |
400 | int keylen; | |
0211ddda | 401 | u8 keyidx; |
5d08cd1d CH |
402 | u8 key[32]; |
403 | }; | |
404 | ||
bb8c093b | 405 | union iwl4965_ht_rate_supp { |
5d08cd1d CH |
406 | u16 rates; |
407 | struct { | |
408 | u8 siso_rate; | |
409 | u8 mimo_rate; | |
410 | }; | |
411 | }; | |
412 | ||
5d08cd1d | 413 | #define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3) |
5d08cd1d CH |
414 | #define CFG_HT_MPDU_DENSITY_2USEC (0x5) |
415 | #define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_2USEC | |
416 | ||
9e0cc6de RR |
417 | struct iwl_ht_info { |
418 | /* self configuration data */ | |
5d08cd1d | 419 | u8 is_ht; |
9e0cc6de | 420 | u8 supported_chan_width; |
12837be1 | 421 | u8 sm_ps; |
9e0cc6de | 422 | u8 is_green_field; |
bb54244b | 423 | u8 sgf; /* HT_SHORT_GI_* short guard interval */ |
5d08cd1d CH |
424 | u8 max_amsdu_size; |
425 | u8 ampdu_factor; | |
426 | u8 mpdu_density; | |
d9fe60de | 427 | struct ieee80211_mcs_info mcs; |
9e0cc6de | 428 | /* BSS related data */ |
5d08cd1d | 429 | u8 extension_chan_offset; |
5d08cd1d | 430 | u8 tx_chan_width; |
9e0cc6de RR |
431 | u8 ht_protection; |
432 | u8 non_GF_STA_present; | |
5d08cd1d | 433 | }; |
5d08cd1d | 434 | |
1ff50bda | 435 | union iwl_qos_capabity { |
5d08cd1d CH |
436 | struct { |
437 | u8 edca_count:4; /* bit 0-3 */ | |
438 | u8 q_ack:1; /* bit 4 */ | |
439 | u8 queue_request:1; /* bit 5 */ | |
440 | u8 txop_request:1; /* bit 6 */ | |
441 | u8 reserved:1; /* bit 7 */ | |
442 | } q_AP; | |
443 | struct { | |
444 | u8 acvo_APSD:1; /* bit 0 */ | |
445 | u8 acvi_APSD:1; /* bit 1 */ | |
446 | u8 ac_bk_APSD:1; /* bit 2 */ | |
447 | u8 ac_be_APSD:1; /* bit 3 */ | |
448 | u8 q_ack:1; /* bit 4 */ | |
449 | u8 max_len:2; /* bit 5-6 */ | |
450 | u8 more_data_ack:1; /* bit 7 */ | |
451 | } q_STA; | |
452 | u8 val; | |
453 | }; | |
454 | ||
455 | /* QoS structures */ | |
1ff50bda | 456 | struct iwl_qos_info { |
5d08cd1d | 457 | int qos_active; |
1ff50bda EG |
458 | union iwl_qos_capabity qos_cap; |
459 | struct iwl_qosparam_cmd def_qos_parm; | |
5d08cd1d | 460 | }; |
5d08cd1d CH |
461 | |
462 | #define STA_PS_STATUS_WAKE 0 | |
463 | #define STA_PS_STATUS_SLEEP 1 | |
464 | ||
6def9761 | 465 | struct iwl_station_entry { |
133636de | 466 | struct iwl_addsta_cmd sta; |
6def9761 | 467 | struct iwl_tid_data tid[MAX_TID_COUNT]; |
5d08cd1d CH |
468 | u8 used; |
469 | u8 ps_status; | |
6def9761 | 470 | struct iwl_hw_key keyinfo; |
5d08cd1d CH |
471 | }; |
472 | ||
473 | /* one for each uCode image (inst/data, boot/init/runtime) */ | |
474 | struct fw_desc { | |
475 | void *v_addr; /* access by driver */ | |
476 | dma_addr_t p_addr; /* access by card's busmaster DMA */ | |
477 | u32 len; /* bytes */ | |
478 | }; | |
479 | ||
480 | /* uCode file layout */ | |
14b3d338 | 481 | struct iwl_ucode { |
c02b3acd | 482 | __le32 ver; /* major/minor/API/serial */ |
5d08cd1d CH |
483 | __le32 inst_size; /* bytes of runtime instructions */ |
484 | __le32 data_size; /* bytes of runtime data */ | |
485 | __le32 init_size; /* bytes of initialization instructions */ | |
486 | __le32 init_data_size; /* bytes of initialization data */ | |
487 | __le32 boot_size; /* bytes of bootstrap instructions */ | |
488 | u8 data[0]; /* data in same order as "size" elements */ | |
489 | }; | |
490 | ||
bb8c093b | 491 | struct iwl4965_ibss_seq { |
5d08cd1d CH |
492 | u8 mac[ETH_ALEN]; |
493 | u16 seq_num; | |
494 | u16 frag_num; | |
495 | unsigned long packet_time; | |
496 | struct list_head list; | |
497 | }; | |
498 | ||
f0832f13 EG |
499 | struct iwl_sensitivity_ranges { |
500 | u16 min_nrg_cck; | |
501 | u16 max_nrg_cck; | |
502 | ||
503 | u16 nrg_th_cck; | |
504 | u16 nrg_th_ofdm; | |
505 | ||
506 | u16 auto_corr_min_ofdm; | |
507 | u16 auto_corr_min_ofdm_mrc; | |
508 | u16 auto_corr_min_ofdm_x1; | |
509 | u16 auto_corr_min_ofdm_mrc_x1; | |
510 | ||
511 | u16 auto_corr_max_ofdm; | |
512 | u16 auto_corr_max_ofdm_mrc; | |
513 | u16 auto_corr_max_ofdm_x1; | |
514 | u16 auto_corr_max_ofdm_mrc_x1; | |
515 | ||
516 | u16 auto_corr_max_cck; | |
517 | u16 auto_corr_max_cck_mrc; | |
518 | u16 auto_corr_min_cck; | |
519 | u16 auto_corr_min_cck_mrc; | |
520 | }; | |
521 | ||
099b40b7 | 522 | |
b5047f78 TW |
523 | #define KELVIN_TO_CELSIUS(x) ((x)-273) |
524 | #define CELSIUS_TO_KELVIN(x) ((x)+273) | |
525 | ||
526 | ||
bc47279f | 527 | /** |
5425e490 | 528 | * struct iwl_hw_params |
bc47279f | 529 | * @max_txq_num: Max # Tx queues supported |
f3f911d1 | 530 | * @dma_chnl_num: Number of Tx DMA/FIFO channels |
4ddbb7d0 | 531 | * @scd_bc_tbls_size: size of scheduler byte count tables |
099b40b7 RR |
532 | * @tx/rx_chains_num: Number of TX/RX chains |
533 | * @valid_tx/rx_ant: usable antennas | |
bc47279f | 534 | * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2) |
bc47279f | 535 | * @max_rxq_log: Log-base-2 of max_rxq_size |
099b40b7 | 536 | * @rx_buf_size: Rx buffer size |
bc47279f BC |
537 | * @max_stations: |
538 | * @bcast_sta_id: | |
099b40b7 RR |
539 | * @fat_channel: is 40MHz width possible in band 2.4 |
540 | * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ) | |
541 | * @sw_crypto: 0 for hw, 1 for sw | |
542 | * @max_xxx_size: for ucode uses | |
543 | * @ct_kill_threshold: temperature threshold | |
a96a27f9 | 544 | * @calib_init_cfg: setup initial calibrations for the hw |
f0832f13 | 545 | * @struct iwl_sensitivity_ranges: range of sensitivity values |
bc47279f | 546 | */ |
5425e490 | 547 | struct iwl_hw_params { |
f3f911d1 ZY |
548 | u8 max_txq_num; |
549 | u8 dma_chnl_num; | |
4ddbb7d0 | 550 | u16 scd_bc_tbls_size; |
ec35cf2a TW |
551 | u8 tx_chains_num; |
552 | u8 rx_chains_num; | |
553 | u8 valid_tx_ant; | |
554 | u8 valid_rx_ant; | |
5d08cd1d | 555 | u16 max_rxq_size; |
ec35cf2a | 556 | u16 max_rxq_log; |
9ee1ba47 RR |
557 | u32 rx_buf_size; |
558 | u32 max_pkt_size; | |
5d08cd1d CH |
559 | u8 max_stations; |
560 | u8 bcast_sta_id; | |
099b40b7 RR |
561 | u8 fat_channel; |
562 | u8 sw_crypto; | |
563 | u32 max_inst_size; | |
564 | u32 max_data_size; | |
565 | u32 max_bsm_size; | |
566 | u32 ct_kill_threshold; /* value in hw-dependent units */ | |
be5d56ed | 567 | u32 calib_init_cfg; |
f0832f13 | 568 | const struct iwl_sensitivity_ranges *sens; |
5d08cd1d CH |
569 | }; |
570 | ||
5d08cd1d | 571 | |
5d08cd1d CH |
572 | /****************************************************************************** |
573 | * | |
a33c2f47 EG |
574 | * Functions implemented in core module which are forward declared here |
575 | * for use by iwl-[4-5].c | |
5d08cd1d | 576 | * |
a33c2f47 EG |
577 | * NOTE: The implementation of these functions are not hardware specific |
578 | * which is why they are in the core module files. | |
5d08cd1d CH |
579 | * |
580 | * Naming convention -- | |
a33c2f47 | 581 | * iwl_ <-- Is part of iwlwifi |
5d08cd1d | 582 | * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX) |
bb8c093b CH |
583 | * iwl4965_bg_ <-- Called from work queue context |
584 | * iwl4965_mac_ <-- mac80211 callback | |
5d08cd1d CH |
585 | * |
586 | ****************************************************************************/ | |
5b9f8cd3 EG |
587 | extern void iwl_update_chain_flags(struct iwl_priv *priv); |
588 | extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src); | |
a33c2f47 | 589 | extern const u8 iwl_bcast_addr[ETH_ALEN]; |
b3bbacb7 | 590 | extern int iwl_rxq_stop(struct iwl_priv *priv); |
da1bc453 | 591 | extern void iwl_txq_ctx_stop(struct iwl_priv *priv); |
443cfd45 | 592 | extern int iwl_queue_space(const struct iwl_queue *q); |
fd4abac5 TW |
593 | static inline int iwl_queue_used(const struct iwl_queue *q, int i) |
594 | { | |
595 | return q->write_ptr > q->read_ptr ? | |
596 | (i >= q->read_ptr && i < q->write_ptr) : | |
597 | !(i < q->read_ptr && i >= q->write_ptr); | |
598 | } | |
599 | ||
600 | ||
601 | static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge) | |
602 | { | |
603 | /* This is for scan command, the big buffer at end of command array */ | |
604 | if (is_huge) | |
605 | return q->n_window; /* must be power of 2 */ | |
606 | ||
607 | /* Otherwise, use normal size buffers */ | |
608 | return index & (q->n_window - 1); | |
609 | } | |
610 | ||
611 | ||
4ddbb7d0 TW |
612 | struct iwl_dma_ptr { |
613 | dma_addr_t dma; | |
614 | void *addr; | |
b481de9c ZY |
615 | size_t size; |
616 | }; | |
617 | ||
34c22cf9 WT |
618 | #define HT_SHORT_GI_20MHZ (1 << 0) |
619 | #define HT_SHORT_GI_40MHZ (1 << 1) | |
620 | ||
b481de9c ZY |
621 | #define IWL_CHANNEL_WIDTH_20MHZ 0 |
622 | #define IWL_CHANNEL_WIDTH_40MHZ 1 | |
623 | ||
b481de9c ZY |
624 | #define IWL_OPERATION_MODE_AUTO 0 |
625 | #define IWL_OPERATION_MODE_HT_ONLY 1 | |
626 | #define IWL_OPERATION_MODE_MIXED 2 | |
627 | #define IWL_OPERATION_MODE_20MHZ 3 | |
628 | ||
3195cdb7 TW |
629 | #define IWL_TX_CRC_SIZE 4 |
630 | #define IWL_TX_DELIMITER_SIZE 4 | |
b481de9c | 631 | |
b481de9c | 632 | #define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000 |
b481de9c | 633 | |
b481de9c | 634 | /* Sensitivity and chain noise calibration */ |
b481de9c ZY |
635 | #define INITIALIZATION_VALUE 0xFFFF |
636 | #define CAL_NUM_OF_BEACONS 20 | |
637 | #define MAXIMUM_ALLOWED_PATHLOSS 15 | |
638 | ||
b481de9c ZY |
639 | #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3 |
640 | ||
641 | #define MAX_FA_OFDM 50 | |
642 | #define MIN_FA_OFDM 5 | |
643 | #define MAX_FA_CCK 50 | |
644 | #define MIN_FA_CCK 5 | |
645 | ||
b481de9c ZY |
646 | #define AUTO_CORR_STEP_OFDM 1 |
647 | ||
b481de9c ZY |
648 | #define AUTO_CORR_STEP_CCK 3 |
649 | #define AUTO_CORR_MAX_TH_CCK 160 | |
650 | ||
b481de9c ZY |
651 | #define NRG_DIFF 2 |
652 | #define NRG_STEP_CCK 2 | |
653 | #define NRG_MARGIN 8 | |
654 | #define MAX_NUMBER_CCK_NO_FA 100 | |
655 | ||
656 | #define AUTO_CORR_CCK_MIN_VAL_DEF (125) | |
657 | ||
658 | #define CHAIN_A 0 | |
659 | #define CHAIN_B 1 | |
660 | #define CHAIN_C 2 | |
661 | #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4 | |
662 | #define ALL_BAND_FILTER 0xFF00 | |
663 | #define IN_BAND_FILTER 0xFF | |
664 | #define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF | |
665 | ||
3195cdb7 TW |
666 | #define NRG_NUM_PREV_STAT_L 20 |
667 | #define NUM_RX_CHAINS 3 | |
668 | ||
bb8c093b | 669 | enum iwl4965_false_alarm_state { |
b481de9c ZY |
670 | IWL_FA_TOO_MANY = 0, |
671 | IWL_FA_TOO_FEW = 1, | |
672 | IWL_FA_GOOD_RANGE = 2, | |
673 | }; | |
674 | ||
bb8c093b | 675 | enum iwl4965_chain_noise_state { |
b481de9c | 676 | IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */ |
04816448 GE |
677 | IWL_CHAIN_NOISE_ACCUMULATE, |
678 | IWL_CHAIN_NOISE_CALIBRATED, | |
679 | IWL_CHAIN_NOISE_DONE, | |
b481de9c ZY |
680 | }; |
681 | ||
bb8c093b | 682 | enum iwl4965_calib_enabled_state { |
b481de9c ZY |
683 | IWL_CALIB_DISABLED = 0, /* must be 0 */ |
684 | IWL_CALIB_ENABLED = 1, | |
685 | }; | |
686 | ||
f69f42a6 TW |
687 | |
688 | /* | |
689 | * enum iwl_calib | |
690 | * defines the order in which results of initial calibrations | |
691 | * should be sent to the runtime uCode | |
692 | */ | |
693 | enum iwl_calib { | |
694 | IWL_CALIB_XTAL, | |
819500c5 | 695 | IWL_CALIB_DC, |
f69f42a6 TW |
696 | IWL_CALIB_LO, |
697 | IWL_CALIB_TX_IQ, | |
698 | IWL_CALIB_TX_IQ_PERD, | |
201706ac | 699 | IWL_CALIB_BASE_BAND, |
f69f42a6 TW |
700 | IWL_CALIB_MAX |
701 | }; | |
702 | ||
6e21f2c1 TW |
703 | /* Opaque calibration results */ |
704 | struct iwl_calib_result { | |
705 | void *buf; | |
706 | size_t buf_len; | |
7c616cba TW |
707 | }; |
708 | ||
dbb983b7 RR |
709 | enum ucode_type { |
710 | UCODE_NONE = 0, | |
711 | UCODE_INIT, | |
712 | UCODE_RT | |
713 | }; | |
714 | ||
b481de9c | 715 | /* Sensitivity calib data */ |
f0832f13 | 716 | struct iwl_sensitivity_data { |
b481de9c ZY |
717 | u32 auto_corr_ofdm; |
718 | u32 auto_corr_ofdm_mrc; | |
719 | u32 auto_corr_ofdm_x1; | |
720 | u32 auto_corr_ofdm_mrc_x1; | |
721 | u32 auto_corr_cck; | |
722 | u32 auto_corr_cck_mrc; | |
723 | ||
724 | u32 last_bad_plcp_cnt_ofdm; | |
725 | u32 last_fa_cnt_ofdm; | |
726 | u32 last_bad_plcp_cnt_cck; | |
727 | u32 last_fa_cnt_cck; | |
728 | ||
729 | u32 nrg_curr_state; | |
730 | u32 nrg_prev_state; | |
731 | u32 nrg_value[10]; | |
732 | u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L]; | |
733 | u32 nrg_silence_ref; | |
734 | u32 nrg_energy_idx; | |
735 | u32 nrg_silence_idx; | |
736 | u32 nrg_th_cck; | |
737 | s32 nrg_auto_corr_silence_diff; | |
738 | u32 num_in_cck_no_fa; | |
739 | u32 nrg_th_ofdm; | |
b481de9c ZY |
740 | }; |
741 | ||
742 | /* Chain noise (differential Rx gain) calib data */ | |
f0832f13 | 743 | struct iwl_chain_noise_data { |
04816448 | 744 | u32 active_chains; |
b481de9c ZY |
745 | u32 chain_noise_a; |
746 | u32 chain_noise_b; | |
747 | u32 chain_noise_c; | |
748 | u32 chain_signal_a; | |
749 | u32 chain_signal_b; | |
750 | u32 chain_signal_c; | |
04816448 | 751 | u16 beacon_count; |
b481de9c ZY |
752 | u8 disconn_array[NUM_RX_CHAINS]; |
753 | u8 delta_gain_code[NUM_RX_CHAINS]; | |
754 | u8 radio_write; | |
04816448 | 755 | u8 state; |
b481de9c ZY |
756 | }; |
757 | ||
abceddb4 BC |
758 | #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */ |
759 | #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ | |
b481de9c | 760 | |
5d08cd1d | 761 | |
5d08cd1d CH |
762 | enum { |
763 | MEASUREMENT_READY = (1 << 0), | |
764 | MEASUREMENT_ACTIVE = (1 << 1), | |
765 | }; | |
766 | ||
5d08cd1d | 767 | |
dfe7d458 RR |
768 | #define IWL_MAX_NUM_QUEUES 20 /* FIXME: do dynamic allocation */ |
769 | ||
c79dd5b5 | 770 | struct iwl_priv { |
5d08cd1d CH |
771 | |
772 | /* ieee device used by generic ieee processing code */ | |
773 | struct ieee80211_hw *hw; | |
774 | struct ieee80211_channel *ieee_channels; | |
775 | struct ieee80211_rate *ieee_rates; | |
82b9a121 | 776 | struct iwl_cfg *cfg; |
5d08cd1d CH |
777 | |
778 | /* temporary frame storage list */ | |
779 | struct list_head free_frames; | |
780 | int frames_count; | |
781 | ||
8318d78a | 782 | enum ieee80211_band band; |
5d08cd1d CH |
783 | int alloc_rxb_skb; |
784 | ||
c79dd5b5 | 785 | void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv, |
a55360e4 | 786 | struct iwl_rx_mem_buffer *rxb); |
5d08cd1d | 787 | |
8318d78a | 788 | struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; |
5d08cd1d | 789 | |
4fc22b21 | 790 | #ifdef CONFIG_IWLAGN_SPECTRUM_MEASUREMENT |
5d08cd1d | 791 | /* spectrum measurement report caching */ |
2aa6ab86 | 792 | struct iwl_spectrum_notification measure_report; |
5d08cd1d CH |
793 | u8 measurement_status; |
794 | #endif | |
795 | /* ucode beacon time */ | |
796 | u32 ucode_beacon_time; | |
797 | ||
bb8c093b | 798 | /* we allocate array of iwl4965_channel_info for NIC's valid channels. |
5d08cd1d | 799 | * Access via channel # using indirect index array */ |
bf85ea4f | 800 | struct iwl_channel_info *channel_info; /* channel info array */ |
5d08cd1d CH |
801 | u8 channel_count; /* # of channels */ |
802 | ||
5d08cd1d CH |
803 | /* thermal calibration */ |
804 | s32 temperature; /* degrees Kelvin */ | |
805 | s32 last_temperature; | |
806 | ||
7c616cba | 807 | /* init calibration results */ |
6e21f2c1 | 808 | struct iwl_calib_result calib_results[IWL_CALIB_MAX]; |
7c616cba | 809 | |
5d08cd1d CH |
810 | /* Scan related variables */ |
811 | unsigned long last_scan_jiffies; | |
7878a5a4 | 812 | unsigned long next_scan_jiffies; |
5d08cd1d CH |
813 | unsigned long scan_start; |
814 | unsigned long scan_pass_start; | |
815 | unsigned long scan_start_tsf; | |
76eff18b | 816 | struct iwl_scan_cmd *scan; |
5d08cd1d CH |
817 | int scan_bands; |
818 | int one_direct_scan; | |
819 | u8 direct_ssid_len; | |
820 | u8 direct_ssid[IW_ESSID_MAX_SIZE]; | |
76eff18b TW |
821 | u8 scan_tx_ant[IEEE80211_NUM_BANDS]; |
822 | u8 mgmt_tx_ant; | |
5d08cd1d CH |
823 | |
824 | /* spinlock */ | |
825 | spinlock_t lock; /* protect general shared data */ | |
826 | spinlock_t hcmd_lock; /* protect hcmd */ | |
827 | struct mutex mutex; | |
828 | ||
829 | /* basic pci-network driver stuff */ | |
830 | struct pci_dev *pci_dev; | |
831 | ||
832 | /* pci hardware address support */ | |
833 | void __iomem *hw_base; | |
b661c819 TW |
834 | u32 hw_rev; |
835 | u32 hw_wa_rev; | |
836 | u8 rev_id; | |
5d08cd1d CH |
837 | |
838 | /* uCode images, save to reload in case of failure */ | |
c02b3acd CR |
839 | u32 ucode_ver; /* version of ucode, copy of |
840 | iwl_ucode.ver */ | |
5d08cd1d CH |
841 | struct fw_desc ucode_code; /* runtime inst */ |
842 | struct fw_desc ucode_data; /* runtime data original */ | |
843 | struct fw_desc ucode_data_backup; /* runtime data save/restore */ | |
844 | struct fw_desc ucode_init; /* initialization inst */ | |
845 | struct fw_desc ucode_init_data; /* initialization data */ | |
846 | struct fw_desc ucode_boot; /* bootstrap inst */ | |
dbb983b7 RR |
847 | enum ucode_type ucode_type; |
848 | u8 ucode_write_complete; /* the image write is complete */ | |
5d08cd1d CH |
849 | |
850 | ||
3195c1f3 | 851 | struct iwl_rxon_time_cmd rxon_timing; |
5d08cd1d CH |
852 | |
853 | /* We declare this const so it can only be | |
854 | * changed via explicit cast within the | |
855 | * routines that actually update the physical | |
856 | * hardware */ | |
c1adf9fb GG |
857 | const struct iwl_rxon_cmd active_rxon; |
858 | struct iwl_rxon_cmd staging_rxon; | |
5d08cd1d CH |
859 | |
860 | int error_recovering; | |
c1adf9fb | 861 | struct iwl_rxon_cmd recovery_rxon; |
5d08cd1d CH |
862 | |
863 | /* 1st responses from initialize and runtime uCode images. | |
864 | * 4965's initialize alive response contains some calibration data. */ | |
885ba202 TW |
865 | struct iwl_init_alive_resp card_alive_init; |
866 | struct iwl_alive_resp card_alive; | |
eadd3c4b | 867 | #ifdef CONFIG_IWLWIFI_RFKILL |
80fcc9e2 | 868 | struct rfkill *rfkill; |
ad97edd2 | 869 | #endif |
5d08cd1d | 870 | |
36316126 | 871 | #ifdef CONFIG_IWLWIFI_LEDS |
0eee6127 | 872 | struct iwl_led led[IWL_LED_TRG_MAX]; |
ab53d8af MA |
873 | unsigned long last_blink_time; |
874 | u8 last_blink_rate; | |
875 | u8 allow_blinking; | |
876 | u64 led_tpt; | |
5d08cd1d CH |
877 | #endif |
878 | ||
879 | u16 active_rate; | |
880 | u16 active_rate_basic; | |
881 | ||
5d08cd1d | 882 | u8 assoc_station_added; |
5d08cd1d | 883 | u8 start_calib; |
f0832f13 EG |
884 | struct iwl_sensitivity_data sensitivity_data; |
885 | struct iwl_chain_noise_data chain_noise_data; | |
5d08cd1d | 886 | __le16 sensitivity_tbl[HD_TABLE_SIZE]; |
5d08cd1d | 887 | |
9e0cc6de | 888 | struct iwl_ht_info current_ht_config; |
5d08cd1d CH |
889 | u8 last_phy_res[100]; |
890 | ||
5d08cd1d CH |
891 | /* Rate scaling data */ |
892 | s8 data_retry_limit; | |
893 | u8 retry_rate; | |
894 | ||
895 | wait_queue_head_t wait_command_queue; | |
896 | ||
897 | int activity_timer_active; | |
898 | ||
899 | /* Rx and Tx DMA processing queues */ | |
a55360e4 | 900 | struct iwl_rx_queue rxq; |
16466903 | 901 | struct iwl_tx_queue txq[IWL_MAX_NUM_QUEUES]; |
5d08cd1d | 902 | unsigned long txq_ctx_active_msk; |
4ddbb7d0 TW |
903 | struct iwl_dma_ptr kw; /* keep warm address */ |
904 | struct iwl_dma_ptr scd_bc_tbls; | |
905 | ||
5d08cd1d CH |
906 | u32 scd_base_addr; /* scheduler sram base address */ |
907 | ||
908 | unsigned long status; | |
5d08cd1d | 909 | |
a96a27f9 | 910 | int last_rx_rssi; /* From Rx packet statistics */ |
5d08cd1d CH |
911 | int last_rx_noise; /* From beacon statistics */ |
912 | ||
19758bef TW |
913 | /* counts mgmt, ctl, and data packets */ |
914 | struct traffic_stats { | |
915 | u32 cnt; | |
916 | u64 bytes; | |
917 | } tx_stats[3], rx_stats[3]; | |
918 | ||
5da4b55f | 919 | struct iwl_power_mgr power_data; |
5d08cd1d | 920 | |
8f91aecb | 921 | struct iwl_notif_statistics statistics; |
5d08cd1d CH |
922 | unsigned long last_statistics_time; |
923 | ||
924 | /* context information */ | |
5d08cd1d CH |
925 | u16 rates_mask; |
926 | ||
927 | u32 power_mode; | |
928 | u32 antenna; | |
929 | u8 bssid[ETH_ALEN]; | |
930 | u16 rts_threshold; | |
931 | u8 mac_addr[ETH_ALEN]; | |
932 | ||
933 | /*station table variables */ | |
934 | spinlock_t sta_lock; | |
935 | int num_stations; | |
6def9761 | 936 | struct iwl_station_entry stations[IWL_STATION_COUNT]; |
6974e363 EG |
937 | struct iwl_wep_key wep_keys[WEP_KEYS_MAX]; |
938 | u8 default_wep_key; | |
939 | u8 key_mapping_key; | |
80fb47a1 | 940 | unsigned long ucode_key_table; |
5d08cd1d CH |
941 | |
942 | /* Indication if ieee80211_ops->open has been called */ | |
69dc5d9d | 943 | u8 is_open; |
5d08cd1d CH |
944 | |
945 | u8 mac80211_registered; | |
5d08cd1d | 946 | |
5d08cd1d CH |
947 | /* Rx'd packet timing information */ |
948 | u32 last_beacon_time; | |
949 | u64 last_tsf; | |
950 | ||
5d08cd1d | 951 | /* eeprom */ |
073d3f5f TW |
952 | u8 *eeprom; |
953 | struct iwl_eeprom_calib_info *calib_info; | |
5d08cd1d | 954 | |
05c914fe | 955 | enum nl80211_iftype iw_mode; |
5d08cd1d CH |
956 | |
957 | struct sk_buff *ibss_beacon; | |
958 | ||
959 | /* Last Rx'd beacon timestamp */ | |
3109ece1 | 960 | u64 timestamp; |
5d08cd1d | 961 | u16 beacon_int; |
32bfd35d | 962 | struct ieee80211_vif *vif; |
5d08cd1d | 963 | |
5425e490 | 964 | struct iwl_hw_params hw_params; |
4ddbb7d0 | 965 | |
059ff826 | 966 | |
5d08cd1d CH |
967 | /* Current association information needed to configure the |
968 | * hardware */ | |
969 | u16 assoc_id; | |
970 | u16 assoc_capability; | |
5d08cd1d | 971 | |
1ff50bda | 972 | struct iwl_qos_info qos_data; |
5d08cd1d CH |
973 | |
974 | struct workqueue_struct *workqueue; | |
975 | ||
976 | struct work_struct up; | |
977 | struct work_struct restart; | |
978 | struct work_struct calibrated_work; | |
979 | struct work_struct scan_completed; | |
980 | struct work_struct rx_replenish; | |
981 | struct work_struct rf_kill; | |
982 | struct work_struct abort_scan; | |
983 | struct work_struct update_link_led; | |
984 | struct work_struct auth_work; | |
985 | struct work_struct report_work; | |
986 | struct work_struct request_scan; | |
987 | struct work_struct beacon_update; | |
988 | ||
989 | struct tasklet_struct irq_tasklet; | |
990 | ||
c90a74ba | 991 | struct delayed_work set_power_save; |
5d08cd1d CH |
992 | struct delayed_work init_alive_start; |
993 | struct delayed_work alive_start; | |
5d08cd1d | 994 | struct delayed_work scan_check; |
630fe9b6 TW |
995 | /* TX Power */ |
996 | s8 tx_power_user_lmt; | |
997 | s8 tx_power_channel_lmt; | |
5d08cd1d | 998 | |
5d08cd1d | 999 | |
0a6857e7 | 1000 | #ifdef CONFIG_IWLWIFI_DEBUG |
5d08cd1d | 1001 | /* debugging info */ |
bf403db8 | 1002 | u32 debug_level; |
5d08cd1d CH |
1003 | u32 framecnt_to_us; |
1004 | atomic_t restrict_refcnt; | |
712b6cf5 TW |
1005 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1006 | /* debugfs */ | |
1007 | struct iwl_debugfs *dbgfs; | |
1008 | #endif /* CONFIG_IWLWIFI_DEBUGFS */ | |
1009 | #endif /* CONFIG_IWLWIFI_DEBUG */ | |
5d08cd1d CH |
1010 | |
1011 | struct work_struct txpower_work; | |
445c2dff TW |
1012 | u32 disable_sens_cal; |
1013 | u32 disable_chain_noise_cal; | |
203566f3 | 1014 | u32 disable_tx_power_cal; |
16e727e8 | 1015 | struct work_struct run_time_calib_work; |
5d08cd1d | 1016 | struct timer_list statistics_periodic; |
c79dd5b5 | 1017 | }; /*iwl_priv */ |
5d08cd1d | 1018 | |
36470749 RR |
1019 | static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id) |
1020 | { | |
1021 | set_bit(txq_id, &priv->txq_ctx_active_msk); | |
1022 | } | |
1023 | ||
1024 | static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id) | |
1025 | { | |
1026 | clear_bit(txq_id, &priv->txq_ctx_active_msk); | |
1027 | } | |
1028 | ||
994d31f7 | 1029 | #ifdef CONFIG_IWLWIFI_DEBUG |
a332f8d6 TW |
1030 | const char *iwl_get_tx_fail_reason(u32 status); |
1031 | #else | |
1032 | static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; } | |
1033 | #endif | |
1034 | ||
1035 | ||
a332f8d6 TW |
1036 | static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv, |
1037 | int txq_id, int idx) | |
1038 | { | |
1039 | if (priv->txq[txq_id].txb[idx].skb[0]) | |
1040 | return (struct ieee80211_hdr *)priv->txq[txq_id]. | |
1041 | txb[idx].skb[0]->data; | |
1042 | return NULL; | |
1043 | } | |
a332f8d6 TW |
1044 | |
1045 | ||
3109ece1 | 1046 | static inline int iwl_is_associated(struct iwl_priv *priv) |
5d08cd1d CH |
1047 | { |
1048 | return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0; | |
1049 | } | |
1050 | ||
bf85ea4f | 1051 | static inline int is_channel_valid(const struct iwl_channel_info *ch_info) |
5d08cd1d CH |
1052 | { |
1053 | if (ch_info == NULL) | |
1054 | return 0; | |
1055 | return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0; | |
1056 | } | |
1057 | ||
bf85ea4f | 1058 | static inline int is_channel_radar(const struct iwl_channel_info *ch_info) |
5d08cd1d CH |
1059 | { |
1060 | return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0; | |
1061 | } | |
1062 | ||
bf85ea4f | 1063 | static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info) |
5d08cd1d | 1064 | { |
8318d78a | 1065 | return ch_info->band == IEEE80211_BAND_5GHZ; |
5d08cd1d CH |
1066 | } |
1067 | ||
bf85ea4f | 1068 | static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info) |
5d08cd1d | 1069 | { |
8318d78a | 1070 | return ch_info->band == IEEE80211_BAND_2GHZ; |
5d08cd1d CH |
1071 | } |
1072 | ||
bf85ea4f | 1073 | static inline int is_channel_passive(const struct iwl_channel_info *ch) |
5d08cd1d CH |
1074 | { |
1075 | return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0; | |
1076 | } | |
1077 | ||
bf85ea4f | 1078 | static inline int is_channel_ibss(const struct iwl_channel_info *ch) |
5d08cd1d CH |
1079 | { |
1080 | return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0; | |
1081 | } | |
1082 | ||
be1f3ab6 | 1083 | #endif /* __iwl_dev_h__ */ |