Commit | Line | Data |
---|---|---|
34cf6ff6 AK |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
1f447808 | 8 | * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved. |
34cf6ff6 AK |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
759ef89f | 28 | * Intel Linux Wireless <ilw@linux.intel.com> |
34cf6ff6 AK |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
1f447808 | 33 | * Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved. |
34cf6ff6 AK |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | *****************************************************************************/ | |
62 | ||
63 | ||
64 | #include <linux/kernel.h> | |
65 | #include <linux/module.h> | |
5a0e3ad6 | 66 | #include <linux/slab.h> |
34cf6ff6 AK |
67 | #include <linux/init.h> |
68 | ||
69 | #include <net/mac80211.h> | |
70 | ||
5a36ba0e | 71 | #include "iwl-commands.h" |
3e0d4cb1 | 72 | #include "iwl-dev.h" |
34cf6ff6 | 73 | #include "iwl-core.h" |
0a6857e7 | 74 | #include "iwl-debug.h" |
34cf6ff6 | 75 | #include "iwl-eeprom.h" |
3395f6e9 | 76 | #include "iwl-io.h" |
34cf6ff6 | 77 | |
bf85ea4f AK |
78 | /************************** EEPROM BANDS **************************** |
79 | * | |
80 | * The iwl_eeprom_band definitions below provide the mapping from the | |
81 | * EEPROM contents to the specific channel number supported for each | |
82 | * band. | |
83 | * | |
84 | * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3 | |
85 | * definition below maps to physical channel 42 in the 5.2GHz spectrum. | |
86 | * The specific geography and calibration information for that channel | |
87 | * is contained in the eeprom map itself. | |
88 | * | |
89 | * During init, we copy the eeprom information and channel map | |
90 | * information into priv->channel_info_24/52 and priv->channel_map_24/52 | |
91 | * | |
92 | * channel_map_24/52 provides the index in the channel_info array for a | |
93 | * given channel. We have to have two separate maps as there is channel | |
94 | * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and | |
95 | * band_2 | |
96 | * | |
97 | * A value of 0xff stored in the channel_map indicates that the channel | |
98 | * is not supported by the hardware at all. | |
99 | * | |
100 | * A value of 0xfe in the channel_map indicates that the channel is not | |
101 | * valid for Tx with the current hardware. This means that | |
102 | * while the system can tune and receive on a given channel, it may not | |
103 | * be able to associate or transmit any frames on that | |
104 | * channel. There is no corresponding channel information for that | |
105 | * entry. | |
106 | * | |
107 | *********************************************************************/ | |
108 | ||
109 | /* 2.4 GHz */ | |
110 | const u8 iwl_eeprom_band_1[14] = { | |
111 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 | |
112 | }; | |
113 | ||
114 | /* 5.2 GHz bands */ | |
115 | static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */ | |
116 | 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 | |
117 | }; | |
118 | ||
119 | static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */ | |
120 | 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 | |
121 | }; | |
122 | ||
123 | static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */ | |
124 | 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 | |
125 | }; | |
126 | ||
127 | static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */ | |
128 | 145, 149, 153, 157, 161, 165 | |
129 | }; | |
130 | ||
7aafef1c | 131 | static const u8 iwl_eeprom_band_6[] = { /* 2.4 ht40 channel */ |
bf85ea4f AK |
132 | 1, 2, 3, 4, 5, 6, 7 |
133 | }; | |
134 | ||
7aafef1c | 135 | static const u8 iwl_eeprom_band_7[] = { /* 5.2 ht40 channel */ |
bf85ea4f AK |
136 | 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 |
137 | }; | |
138 | ||
34cf6ff6 AK |
139 | /****************************************************************************** |
140 | * | |
141 | * EEPROM related functions | |
142 | * | |
143 | ******************************************************************************/ | |
144 | ||
d3f5ba95 | 145 | static int iwl_eeprom_verify_signature(struct iwl_priv *priv) |
34cf6ff6 | 146 | { |
f41bb897 WYG |
147 | u32 gp = iwl_read32(priv, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK; |
148 | int ret = 0; | |
149 | ||
d058ff8b | 150 | IWL_DEBUG_EEPROM(priv, "EEPROM signature=0x%08x\n", gp); |
f41bb897 WYG |
151 | switch (gp) { |
152 | case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP: | |
153 | if (priv->nvm_device_type != NVM_DEVICE_TYPE_OTP) { | |
154 | IWL_ERR(priv, "EEPROM with bad signature: 0x%08x\n", | |
155 | gp); | |
156 | ret = -ENOENT; | |
157 | } | |
158 | break; | |
159 | case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K: | |
160 | case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K: | |
161 | if (priv->nvm_device_type != NVM_DEVICE_TYPE_EEPROM) { | |
162 | IWL_ERR(priv, "OTP with bad signature: 0x%08x\n", gp); | |
163 | ret = -ENOENT; | |
164 | } | |
165 | break; | |
166 | case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP: | |
167 | default: | |
168 | IWL_ERR(priv, "bad EEPROM/OTP signature, type=%s, " | |
169 | "EEPROM_GP=0x%08x\n", | |
170 | (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) | |
171 | ? "OTP" : "EEPROM", gp); | |
172 | ret = -ENOENT; | |
173 | break; | |
34cf6ff6 | 174 | } |
f41bb897 | 175 | return ret; |
34cf6ff6 | 176 | } |
34cf6ff6 | 177 | |
415e4993 WYG |
178 | static void iwl_set_otp_access(struct iwl_priv *priv, enum iwl_access_mode mode) |
179 | { | |
180 | u32 otpgp; | |
181 | ||
182 | otpgp = iwl_read32(priv, CSR_OTP_GP_REG); | |
183 | if (mode == IWL_OTP_ACCESS_ABSOLUTE) | |
184 | iwl_clear_bit(priv, CSR_OTP_GP_REG, | |
185 | CSR_OTP_GP_REG_OTP_ACCESS_MODE); | |
186 | else | |
187 | iwl_set_bit(priv, CSR_OTP_GP_REG, | |
188 | CSR_OTP_GP_REG_OTP_ACCESS_MODE); | |
189 | } | |
190 | ||
0848e297 WYG |
191 | static int iwlcore_get_nvm_type(struct iwl_priv *priv) |
192 | { | |
193 | u32 otpgp; | |
194 | int nvm_type; | |
195 | ||
196 | /* OTP only valid for CP/PP and after */ | |
197 | switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { | |
b23a0524 WYG |
198 | case CSR_HW_REV_TYPE_NONE: |
199 | IWL_ERR(priv, "Unknown hardware type\n"); | |
200 | return -ENOENT; | |
0848e297 WYG |
201 | case CSR_HW_REV_TYPE_3945: |
202 | case CSR_HW_REV_TYPE_4965: | |
203 | case CSR_HW_REV_TYPE_5300: | |
204 | case CSR_HW_REV_TYPE_5350: | |
205 | case CSR_HW_REV_TYPE_5100: | |
206 | case CSR_HW_REV_TYPE_5150: | |
207 | nvm_type = NVM_DEVICE_TYPE_EEPROM; | |
208 | break; | |
209 | default: | |
210 | otpgp = iwl_read32(priv, CSR_OTP_GP_REG); | |
211 | if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT) | |
212 | nvm_type = NVM_DEVICE_TYPE_OTP; | |
213 | else | |
214 | nvm_type = NVM_DEVICE_TYPE_EEPROM; | |
215 | break; | |
216 | } | |
217 | return nvm_type; | |
218 | } | |
219 | ||
073d3f5f TW |
220 | const u8 *iwlcore_eeprom_query_addr(const struct iwl_priv *priv, size_t offset) |
221 | { | |
7cb1b088 | 222 | BUG_ON(offset >= priv->cfg->base_params->eeprom_size); |
073d3f5f TW |
223 | return &priv->eeprom[offset]; |
224 | } | |
225 | EXPORT_SYMBOL(iwlcore_eeprom_query_addr); | |
34cf6ff6 | 226 | |
0848e297 WYG |
227 | static int iwl_init_otp_access(struct iwl_priv *priv) |
228 | { | |
229 | int ret; | |
230 | ||
231 | /* Enable 40MHz radio clock */ | |
232 | _iwl_write32(priv, CSR_GP_CNTRL, | |
233 | _iwl_read32(priv, CSR_GP_CNTRL) | | |
234 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
235 | ||
236 | /* wait for clock to be ready */ | |
1739d332 AK |
237 | ret = iwl_poll_bit(priv, CSR_GP_CNTRL, |
238 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
0848e297 WYG |
239 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
240 | 25000); | |
241 | if (ret < 0) | |
242 | IWL_ERR(priv, "Time out access OTP\n"); | |
243 | else { | |
d77b034f RC |
244 | iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, |
245 | APMG_PS_CTRL_VAL_RESET_REQ); | |
246 | udelay(5); | |
247 | iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, | |
248 | APMG_PS_CTRL_VAL_RESET_REQ); | |
32004ee4 WYG |
249 | |
250 | /* | |
251 | * CSR auto clock gate disable bit - | |
252 | * this is only applicable for HW with OTP shadow RAM | |
253 | */ | |
7cb1b088 | 254 | if (priv->cfg->base_params->shadow_ram_support) |
32004ee4 WYG |
255 | iwl_set_bit(priv, CSR_DBG_LINK_PWR_MGMT_REG, |
256 | CSR_RESET_LINK_PWR_MGMT_DISABLED); | |
0848e297 WYG |
257 | } |
258 | return ret; | |
259 | } | |
260 | ||
af6b8ee3 | 261 | static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, __le16 *eeprom_data) |
415e4993 WYG |
262 | { |
263 | int ret = 0; | |
264 | u32 r; | |
265 | u32 otpgp; | |
266 | ||
267 | _iwl_write32(priv, CSR_EEPROM_REG, | |
268 | CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); | |
1739d332 AK |
269 | ret = iwl_poll_bit(priv, CSR_EEPROM_REG, |
270 | CSR_EEPROM_REG_READ_VALID_MSK, | |
415e4993 WYG |
271 | CSR_EEPROM_REG_READ_VALID_MSK, |
272 | IWL_EEPROM_ACCESS_TIMEOUT); | |
273 | if (ret < 0) { | |
274 | IWL_ERR(priv, "Time out reading OTP[%d]\n", addr); | |
275 | return ret; | |
276 | } | |
277 | r = _iwl_read_direct32(priv, CSR_EEPROM_REG); | |
278 | /* check for ECC errors: */ | |
279 | otpgp = iwl_read32(priv, CSR_OTP_GP_REG); | |
280 | if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) { | |
281 | /* stop in this case */ | |
282 | /* set the uncorrectable OTP ECC bit for acknowledgement */ | |
283 | iwl_set_bit(priv, CSR_OTP_GP_REG, | |
284 | CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); | |
285 | IWL_ERR(priv, "Uncorrectable OTP ECC error, abort OTP read\n"); | |
286 | return -EINVAL; | |
287 | } | |
288 | if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) { | |
289 | /* continue in this case */ | |
290 | /* set the correctable OTP ECC bit for acknowledgement */ | |
291 | iwl_set_bit(priv, CSR_OTP_GP_REG, | |
292 | CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK); | |
293 | IWL_ERR(priv, "Correctable OTP ECC error, continue read\n"); | |
294 | } | |
af6b8ee3 | 295 | *eeprom_data = cpu_to_le16(r >> 16); |
415e4993 WYG |
296 | return 0; |
297 | } | |
298 | ||
299 | /* | |
300 | * iwl_is_otp_empty: check for empty OTP | |
301 | */ | |
302 | static bool iwl_is_otp_empty(struct iwl_priv *priv) | |
303 | { | |
af6b8ee3 JB |
304 | u16 next_link_addr = 0; |
305 | __le16 link_value; | |
415e4993 WYG |
306 | bool is_empty = false; |
307 | ||
308 | /* locate the beginning of OTP link list */ | |
309 | if (!iwl_read_otp_word(priv, next_link_addr, &link_value)) { | |
310 | if (!link_value) { | |
311 | IWL_ERR(priv, "OTP is empty\n"); | |
312 | is_empty = true; | |
313 | } | |
314 | } else { | |
315 | IWL_ERR(priv, "Unable to read first block of OTP list.\n"); | |
316 | is_empty = true; | |
317 | } | |
318 | ||
319 | return is_empty; | |
320 | } | |
321 | ||
322 | ||
323 | /* | |
324 | * iwl_find_otp_image: find EEPROM image in OTP | |
325 | * finding the OTP block that contains the EEPROM image. | |
326 | * the last valid block on the link list (the block _before_ the last block) | |
327 | * is the block we should read and used to configure the device. | |
328 | * If all the available OTP blocks are full, the last block will be the block | |
329 | * we should read and used to configure the device. | |
330 | * only perform this operation if shadow RAM is disabled | |
331 | */ | |
332 | static int iwl_find_otp_image(struct iwl_priv *priv, | |
333 | u16 *validblockaddr) | |
334 | { | |
af6b8ee3 JB |
335 | u16 next_link_addr = 0, valid_addr; |
336 | __le16 link_value = 0; | |
415e4993 WYG |
337 | int usedblocks = 0; |
338 | ||
339 | /* set addressing mode to absolute to traverse the link list */ | |
340 | iwl_set_otp_access(priv, IWL_OTP_ACCESS_ABSOLUTE); | |
341 | ||
342 | /* checking for empty OTP or error */ | |
343 | if (iwl_is_otp_empty(priv)) | |
344 | return -EINVAL; | |
345 | ||
346 | /* | |
347 | * start traverse link list | |
348 | * until reach the max number of OTP blocks | |
349 | * different devices have different number of OTP blocks | |
350 | */ | |
351 | do { | |
352 | /* save current valid block address | |
353 | * check for more block on the link list | |
354 | */ | |
355 | valid_addr = next_link_addr; | |
af6b8ee3 | 356 | next_link_addr = le16_to_cpu(link_value) * sizeof(u16); |
d058ff8b | 357 | IWL_DEBUG_EEPROM(priv, "OTP blocks %d addr 0x%x\n", |
415e4993 WYG |
358 | usedblocks, next_link_addr); |
359 | if (iwl_read_otp_word(priv, next_link_addr, &link_value)) | |
360 | return -EINVAL; | |
361 | if (!link_value) { | |
362 | /* | |
2facba76 | 363 | * reach the end of link list, return success and |
415e4993 WYG |
364 | * set address point to the starting address |
365 | * of the image | |
366 | */ | |
2facba76 JS |
367 | *validblockaddr = valid_addr; |
368 | /* skip first 2 bytes (link list pointer) */ | |
369 | *validblockaddr += 2; | |
370 | return 0; | |
415e4993 WYG |
371 | } |
372 | /* more in the link list, continue */ | |
373 | usedblocks++; | |
7cb1b088 | 374 | } while (usedblocks <= priv->cfg->base_params->max_ll_items); |
2facba76 JS |
375 | |
376 | /* OTP has no valid blocks */ | |
d058ff8b | 377 | IWL_DEBUG_EEPROM(priv, "OTP has no valid blocks\n"); |
2facba76 | 378 | return -EINVAL; |
415e4993 WYG |
379 | } |
380 | ||
3be63ff0 WYG |
381 | const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset) |
382 | { | |
383 | return priv->cfg->ops->lib->eeprom_ops.query_addr(priv, offset); | |
384 | } | |
385 | EXPORT_SYMBOL(iwl_eeprom_query_addr); | |
386 | ||
387 | u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset) | |
388 | { | |
389 | if (!priv->eeprom) | |
390 | return 0; | |
391 | return (u16)priv->eeprom[offset] | ((u16)priv->eeprom[offset + 1] << 8); | |
392 | } | |
393 | EXPORT_SYMBOL(iwl_eeprom_query16); | |
394 | ||
34cf6ff6 AK |
395 | /** |
396 | * iwl_eeprom_init - read EEPROM contents | |
397 | * | |
398 | * Load the EEPROM contents from adapter into priv->eeprom | |
399 | * | |
400 | * NOTE: This routine uses the non-debug IO access functions. | |
401 | */ | |
c79dd5b5 | 402 | int iwl_eeprom_init(struct iwl_priv *priv) |
34cf6ff6 | 403 | { |
af6b8ee3 | 404 | __le16 *e; |
3395f6e9 | 405 | u32 gp = iwl_read32(priv, CSR_EEPROM_GP); |
0848e297 | 406 | int sz; |
34cf6ff6 | 407 | int ret; |
34cf6ff6 | 408 | u16 addr; |
415e4993 WYG |
409 | u16 validblockaddr = 0; |
410 | u16 cache_addr = 0; | |
0848e297 WYG |
411 | |
412 | priv->nvm_device_type = iwlcore_get_nvm_type(priv); | |
b23a0524 WYG |
413 | if (priv->nvm_device_type == -ENOENT) |
414 | return -ENOENT; | |
073d3f5f | 415 | /* allocate eeprom */ |
7cb1b088 | 416 | sz = priv->cfg->base_params->eeprom_size; |
d058ff8b | 417 | IWL_DEBUG_EEPROM(priv, "NVM size = %d\n", sz); |
073d3f5f TW |
418 | priv->eeprom = kzalloc(sz, GFP_KERNEL); |
419 | if (!priv->eeprom) { | |
420 | ret = -ENOMEM; | |
421 | goto alloc_err; | |
422 | } | |
af6b8ee3 | 423 | e = (__le16 *)priv->eeprom; |
34cf6ff6 | 424 | |
f8701fe3 | 425 | priv->cfg->ops->lib->apm_ops.init(priv); |
e43ab94d | 426 | |
d3f5ba95 | 427 | ret = iwl_eeprom_verify_signature(priv); |
073d3f5f | 428 | if (ret < 0) { |
15b1687c | 429 | IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp); |
073d3f5f TW |
430 | ret = -ENOENT; |
431 | goto err; | |
34cf6ff6 AK |
432 | } |
433 | ||
434 | /* Make sure driver (instead of uCode) is allowed to read EEPROM */ | |
435 | ret = priv->cfg->ops->lib->eeprom_ops.acquire_semaphore(priv); | |
436 | if (ret < 0) { | |
15b1687c | 437 | IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n"); |
073d3f5f TW |
438 | ret = -ENOENT; |
439 | goto err; | |
34cf6ff6 | 440 | } |
88521364 | 441 | |
e43ab94d | 442 | if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) { |
88521364 | 443 | |
0848e297 WYG |
444 | ret = iwl_init_otp_access(priv); |
445 | if (ret) { | |
446 | IWL_ERR(priv, "Failed to initialize OTP access.\n"); | |
447 | ret = -ENOENT; | |
415e4993 | 448 | goto done; |
0848e297 WYG |
449 | } |
450 | _iwl_write32(priv, CSR_EEPROM_GP, | |
451 | iwl_read32(priv, CSR_EEPROM_GP) & | |
452 | ~CSR_EEPROM_GP_IF_OWNER_MSK); | |
415e4993 WYG |
453 | |
454 | iwl_set_bit(priv, CSR_OTP_GP_REG, | |
0848e297 WYG |
455 | CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK | |
456 | CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); | |
415e4993 | 457 | /* traversing the linked list if no shadow ram supported */ |
7cb1b088 | 458 | if (!priv->cfg->base_params->shadow_ram_support) { |
415e4993 WYG |
459 | if (iwl_find_otp_image(priv, &validblockaddr)) { |
460 | ret = -ENOENT; | |
0848e297 WYG |
461 | goto done; |
462 | } | |
415e4993 WYG |
463 | } |
464 | for (addr = validblockaddr; addr < validblockaddr + sz; | |
465 | addr += sizeof(u16)) { | |
af6b8ee3 | 466 | __le16 eeprom_data; |
415e4993 WYG |
467 | |
468 | ret = iwl_read_otp_word(priv, addr, &eeprom_data); | |
469 | if (ret) | |
0848e297 | 470 | goto done; |
415e4993 WYG |
471 | e[cache_addr / 2] = eeprom_data; |
472 | cache_addr += sizeof(u16); | |
0848e297 WYG |
473 | } |
474 | } else { | |
475 | /* eeprom is an array of 16bit values */ | |
476 | for (addr = 0; addr < sz; addr += sizeof(u16)) { | |
477 | u32 r; | |
478 | ||
479 | _iwl_write32(priv, CSR_EEPROM_REG, | |
480 | CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); | |
481 | ||
1739d332 AK |
482 | ret = iwl_poll_bit(priv, CSR_EEPROM_REG, |
483 | CSR_EEPROM_REG_READ_VALID_MSK, | |
0848e297 WYG |
484 | CSR_EEPROM_REG_READ_VALID_MSK, |
485 | IWL_EEPROM_ACCESS_TIMEOUT); | |
486 | if (ret < 0) { | |
487 | IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr); | |
488 | goto done; | |
489 | } | |
490 | r = _iwl_read_direct32(priv, CSR_EEPROM_REG); | |
af6b8ee3 | 491 | e[addr / 2] = cpu_to_le16(r >> 16); |
34cf6ff6 | 492 | } |
34cf6ff6 | 493 | } |
d1358f62 | 494 | |
d058ff8b | 495 | IWL_DEBUG_EEPROM(priv, "NVM Type: %s, version: 0x%x\n", |
d1358f62 JB |
496 | (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) |
497 | ? "OTP" : "EEPROM", | |
498 | iwl_eeprom_query16(priv, EEPROM_VERSION)); | |
499 | ||
34cf6ff6 | 500 | ret = 0; |
34cf6ff6 AK |
501 | done: |
502 | priv->cfg->ops->lib->eeprom_ops.release_semaphore(priv); | |
d1358f62 | 503 | |
073d3f5f TW |
504 | err: |
505 | if (ret) | |
0848e297 | 506 | iwl_eeprom_free(priv); |
f8701fe3 | 507 | /* Reset chip to save power until we load uCode during "up". */ |
14e8e4af | 508 | iwl_apm_stop(priv); |
073d3f5f | 509 | alloc_err: |
34cf6ff6 AK |
510 | return ret; |
511 | } | |
512 | EXPORT_SYMBOL(iwl_eeprom_init); | |
513 | ||
073d3f5f TW |
514 | void iwl_eeprom_free(struct iwl_priv *priv) |
515 | { | |
3ac7f146 | 516 | kfree(priv->eeprom); |
073d3f5f TW |
517 | priv->eeprom = NULL; |
518 | } | |
519 | EXPORT_SYMBOL(iwl_eeprom_free); | |
520 | ||
bf85ea4f | 521 | static void iwl_init_band_reference(const struct iwl_priv *priv, |
073d3f5f TW |
522 | int eep_band, int *eeprom_ch_count, |
523 | const struct iwl_eeprom_channel **eeprom_ch_info, | |
524 | const u8 **eeprom_ch_index) | |
bf85ea4f | 525 | { |
073d3f5f TW |
526 | u32 offset = priv->cfg->ops->lib-> |
527 | eeprom_ops.regulatory_bands[eep_band - 1]; | |
528 | switch (eep_band) { | |
bf85ea4f AK |
529 | case 1: /* 2.4GHz band */ |
530 | *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1); | |
073d3f5f TW |
531 | *eeprom_ch_info = (struct iwl_eeprom_channel *) |
532 | iwl_eeprom_query_addr(priv, offset); | |
bf85ea4f AK |
533 | *eeprom_ch_index = iwl_eeprom_band_1; |
534 | break; | |
535 | case 2: /* 4.9GHz band */ | |
536 | *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2); | |
073d3f5f TW |
537 | *eeprom_ch_info = (struct iwl_eeprom_channel *) |
538 | iwl_eeprom_query_addr(priv, offset); | |
bf85ea4f AK |
539 | *eeprom_ch_index = iwl_eeprom_band_2; |
540 | break; | |
541 | case 3: /* 5.2GHz band */ | |
542 | *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3); | |
073d3f5f TW |
543 | *eeprom_ch_info = (struct iwl_eeprom_channel *) |
544 | iwl_eeprom_query_addr(priv, offset); | |
bf85ea4f AK |
545 | *eeprom_ch_index = iwl_eeprom_band_3; |
546 | break; | |
547 | case 4: /* 5.5GHz band */ | |
548 | *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4); | |
073d3f5f TW |
549 | *eeprom_ch_info = (struct iwl_eeprom_channel *) |
550 | iwl_eeprom_query_addr(priv, offset); | |
bf85ea4f AK |
551 | *eeprom_ch_index = iwl_eeprom_band_4; |
552 | break; | |
553 | case 5: /* 5.7GHz band */ | |
554 | *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5); | |
073d3f5f TW |
555 | *eeprom_ch_info = (struct iwl_eeprom_channel *) |
556 | iwl_eeprom_query_addr(priv, offset); | |
bf85ea4f AK |
557 | *eeprom_ch_index = iwl_eeprom_band_5; |
558 | break; | |
7aafef1c | 559 | case 6: /* 2.4GHz ht40 channels */ |
bf85ea4f | 560 | *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6); |
073d3f5f TW |
561 | *eeprom_ch_info = (struct iwl_eeprom_channel *) |
562 | iwl_eeprom_query_addr(priv, offset); | |
bf85ea4f AK |
563 | *eeprom_ch_index = iwl_eeprom_band_6; |
564 | break; | |
7aafef1c | 565 | case 7: /* 5 GHz ht40 channels */ |
bf85ea4f | 566 | *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7); |
073d3f5f TW |
567 | *eeprom_ch_info = (struct iwl_eeprom_channel *) |
568 | iwl_eeprom_query_addr(priv, offset); | |
bf85ea4f AK |
569 | *eeprom_ch_index = iwl_eeprom_band_7; |
570 | break; | |
571 | default: | |
572 | BUG(); | |
573 | return; | |
574 | } | |
575 | } | |
576 | ||
577 | #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \ | |
578 | ? # x " " : "") | |
bf85ea4f | 579 | /** |
3b24716f | 580 | * iwl_mod_ht40_chan_info - Copy ht40 channel info into driver's priv. |
bf85ea4f AK |
581 | * |
582 | * Does not set up a command, or touch hardware. | |
583 | */ | |
3b24716f | 584 | static int iwl_mod_ht40_chan_info(struct iwl_priv *priv, |
bf85ea4f | 585 | enum ieee80211_band band, u16 channel, |
073d3f5f | 586 | const struct iwl_eeprom_channel *eeprom_ch, |
3b24716f | 587 | u8 clear_ht40_extension_channel) |
bf85ea4f AK |
588 | { |
589 | struct iwl_channel_info *ch_info; | |
590 | ||
591 | ch_info = (struct iwl_channel_info *) | |
8622e705 | 592 | iwl_get_channel_info(priv, band, channel); |
bf85ea4f AK |
593 | |
594 | if (!is_channel_valid(ch_info)) | |
595 | return -1; | |
596 | ||
d058ff8b | 597 | IWL_DEBUG_EEPROM(priv, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):" |
630fe9b6 | 598 | " Ad-Hoc %ssupported\n", |
bf85ea4f AK |
599 | ch_info->channel, |
600 | is_channel_a_band(ch_info) ? | |
601 | "5.2" : "2.4", | |
602 | CHECK_AND_PRINT(IBSS), | |
603 | CHECK_AND_PRINT(ACTIVE), | |
604 | CHECK_AND_PRINT(RADAR), | |
605 | CHECK_AND_PRINT(WIDE), | |
bf85ea4f AK |
606 | CHECK_AND_PRINT(DFS), |
607 | eeprom_ch->flags, | |
608 | eeprom_ch->max_power_avg, | |
609 | ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) | |
610 | && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? | |
611 | "" : "not "); | |
612 | ||
7aafef1c WYG |
613 | ch_info->ht40_eeprom = *eeprom_ch; |
614 | ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg; | |
7aafef1c | 615 | ch_info->ht40_flags = eeprom_ch->flags; |
6c3069b1 RC |
616 | if (eeprom_ch->flags & EEPROM_CHANNEL_VALID) |
617 | ch_info->ht40_extension_channel &= ~clear_ht40_extension_channel; | |
bf85ea4f AK |
618 | |
619 | return 0; | |
620 | } | |
621 | ||
622 | #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \ | |
623 | ? # x " " : "") | |
624 | ||
625 | /** | |
626 | * iwl_init_channel_map - Set up driver's info for all possible channels | |
627 | */ | |
628 | int iwl_init_channel_map(struct iwl_priv *priv) | |
629 | { | |
630 | int eeprom_ch_count = 0; | |
631 | const u8 *eeprom_ch_index = NULL; | |
073d3f5f | 632 | const struct iwl_eeprom_channel *eeprom_ch_info = NULL; |
bf85ea4f AK |
633 | int band, ch; |
634 | struct iwl_channel_info *ch_info; | |
635 | ||
636 | if (priv->channel_count) { | |
d058ff8b | 637 | IWL_DEBUG_EEPROM(priv, "Channel map already initialized.\n"); |
bf85ea4f AK |
638 | return 0; |
639 | } | |
640 | ||
d058ff8b | 641 | IWL_DEBUG_EEPROM(priv, "Initializing regulatory info from EEPROM\n"); |
bf85ea4f AK |
642 | |
643 | priv->channel_count = | |
644 | ARRAY_SIZE(iwl_eeprom_band_1) + | |
645 | ARRAY_SIZE(iwl_eeprom_band_2) + | |
646 | ARRAY_SIZE(iwl_eeprom_band_3) + | |
647 | ARRAY_SIZE(iwl_eeprom_band_4) + | |
648 | ARRAY_SIZE(iwl_eeprom_band_5); | |
649 | ||
d058ff8b WYG |
650 | IWL_DEBUG_EEPROM(priv, "Parsing data for %d channels.\n", |
651 | priv->channel_count); | |
bf85ea4f AK |
652 | |
653 | priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) * | |
654 | priv->channel_count, GFP_KERNEL); | |
655 | if (!priv->channel_info) { | |
15b1687c | 656 | IWL_ERR(priv, "Could not allocate channel_info\n"); |
bf85ea4f AK |
657 | priv->channel_count = 0; |
658 | return -ENOMEM; | |
659 | } | |
660 | ||
661 | ch_info = priv->channel_info; | |
662 | ||
663 | /* Loop through the 5 EEPROM bands adding them in order to the | |
664 | * channel map we maintain (that contains additional information than | |
665 | * what just in the EEPROM) */ | |
666 | for (band = 1; band <= 5; band++) { | |
667 | ||
668 | iwl_init_band_reference(priv, band, &eeprom_ch_count, | |
669 | &eeprom_ch_info, &eeprom_ch_index); | |
670 | ||
671 | /* Loop through each band adding each of the channels */ | |
672 | for (ch = 0; ch < eeprom_ch_count; ch++) { | |
673 | ch_info->channel = eeprom_ch_index[ch]; | |
674 | ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ : | |
675 | IEEE80211_BAND_5GHZ; | |
676 | ||
677 | /* permanently store EEPROM's channel regulatory flags | |
678 | * and max power in channel info database. */ | |
679 | ch_info->eeprom = eeprom_ch_info[ch]; | |
680 | ||
681 | /* Copy the run-time flags so they are there even on | |
682 | * invalid channels */ | |
683 | ch_info->flags = eeprom_ch_info[ch].flags; | |
7aafef1c | 684 | /* First write that ht40 is not enabled, and then enable |
963f5517 | 685 | * one by one */ |
7aafef1c | 686 | ch_info->ht40_extension_channel = |
3b24716f | 687 | IEEE80211_CHAN_NO_HT40; |
bf85ea4f AK |
688 | |
689 | if (!(is_channel_valid(ch_info))) { | |
d058ff8b WYG |
690 | IWL_DEBUG_EEPROM(priv, |
691 | "Ch. %d Flags %x [%sGHz] - " | |
bf85ea4f AK |
692 | "No traffic\n", |
693 | ch_info->channel, | |
694 | ch_info->flags, | |
695 | is_channel_a_band(ch_info) ? | |
696 | "5.2" : "2.4"); | |
697 | ch_info++; | |
698 | continue; | |
699 | } | |
700 | ||
701 | /* Initialize regulatory-based run-time data */ | |
702 | ch_info->max_power_avg = ch_info->curr_txpow = | |
703 | eeprom_ch_info[ch].max_power_avg; | |
704 | ch_info->scan_power = eeprom_ch_info[ch].max_power_avg; | |
705 | ch_info->min_power = 0; | |
706 | ||
d058ff8b WYG |
707 | IWL_DEBUG_EEPROM(priv, "Ch. %d [%sGHz] " |
708 | "%s%s%s%s%s%s(0x%02x %ddBm):" | |
630fe9b6 | 709 | " Ad-Hoc %ssupported\n", |
bf85ea4f AK |
710 | ch_info->channel, |
711 | is_channel_a_band(ch_info) ? | |
712 | "5.2" : "2.4", | |
713 | CHECK_AND_PRINT_I(VALID), | |
714 | CHECK_AND_PRINT_I(IBSS), | |
715 | CHECK_AND_PRINT_I(ACTIVE), | |
716 | CHECK_AND_PRINT_I(RADAR), | |
717 | CHECK_AND_PRINT_I(WIDE), | |
bf85ea4f AK |
718 | CHECK_AND_PRINT_I(DFS), |
719 | eeprom_ch_info[ch].flags, | |
720 | eeprom_ch_info[ch].max_power_avg, | |
721 | ((eeprom_ch_info[ch]. | |
722 | flags & EEPROM_CHANNEL_IBSS) | |
723 | && !(eeprom_ch_info[ch]. | |
724 | flags & EEPROM_CHANNEL_RADAR)) | |
725 | ? "" : "not "); | |
726 | ||
62ea9c5b | 727 | /* Set the tx_power_user_lmt to the highest power |
bf85ea4f AK |
728 | * supported by any channel */ |
729 | if (eeprom_ch_info[ch].max_power_avg > | |
630fe9b6 TW |
730 | priv->tx_power_user_lmt) |
731 | priv->tx_power_user_lmt = | |
bf85ea4f AK |
732 | eeprom_ch_info[ch].max_power_avg; |
733 | ||
734 | ch_info++; | |
735 | } | |
736 | } | |
737 | ||
7aafef1c | 738 | /* Check if we do have HT40 channels */ |
a89d03c4 | 739 | if (priv->cfg->ops->lib->eeprom_ops.regulatory_bands[5] == |
7aafef1c | 740 | EEPROM_REGULATORY_BAND_NO_HT40 && |
a89d03c4 | 741 | priv->cfg->ops->lib->eeprom_ops.regulatory_bands[6] == |
7aafef1c | 742 | EEPROM_REGULATORY_BAND_NO_HT40) |
e6148917 SO |
743 | return 0; |
744 | ||
7aafef1c | 745 | /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */ |
bf85ea4f AK |
746 | for (band = 6; band <= 7; band++) { |
747 | enum ieee80211_band ieeeband; | |
bf85ea4f AK |
748 | |
749 | iwl_init_band_reference(priv, band, &eeprom_ch_count, | |
750 | &eeprom_ch_info, &eeprom_ch_index); | |
751 | ||
752 | /* EEPROM band 6 is 2.4, band 7 is 5 GHz */ | |
753 | ieeeband = | |
754 | (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; | |
755 | ||
756 | /* Loop through each band adding each of the channels */ | |
757 | for (ch = 0; ch < eeprom_ch_count; ch++) { | |
bf85ea4f | 758 | /* Set up driver's info for lower half */ |
3b24716f | 759 | iwl_mod_ht40_chan_info(priv, ieeeband, |
da6833cb | 760 | eeprom_ch_index[ch], |
3b24716f ZY |
761 | &eeprom_ch_info[ch], |
762 | IEEE80211_CHAN_NO_HT40PLUS); | |
bf85ea4f AK |
763 | |
764 | /* Set up driver's info for upper half */ | |
3b24716f ZY |
765 | iwl_mod_ht40_chan_info(priv, ieeeband, |
766 | eeprom_ch_index[ch] + 4, | |
767 | &eeprom_ch_info[ch], | |
768 | IEEE80211_CHAN_NO_HT40MINUS); | |
bf85ea4f AK |
769 | } |
770 | } | |
771 | ||
ab9fd1bf WYG |
772 | /* for newer device (6000 series and up) |
773 | * EEPROM contain enhanced tx power information | |
774 | * driver need to process addition information | |
775 | * to determine the max channel tx power limits | |
776 | */ | |
777 | if (priv->cfg->ops->lib->eeprom_ops.update_enhanced_txpower) | |
778 | priv->cfg->ops->lib->eeprom_ops.update_enhanced_txpower(priv); | |
779 | ||
bf85ea4f AK |
780 | return 0; |
781 | } | |
782 | EXPORT_SYMBOL(iwl_init_channel_map); | |
783 | ||
784 | /* | |
da6833cb | 785 | * iwl_free_channel_map - undo allocations in iwl_init_channel_map |
bf85ea4f AK |
786 | */ |
787 | void iwl_free_channel_map(struct iwl_priv *priv) | |
788 | { | |
789 | kfree(priv->channel_info); | |
790 | priv->channel_count = 0; | |
791 | } | |
e6148917 | 792 | EXPORT_SYMBOL(iwl_free_channel_map); |
bf85ea4f AK |
793 | |
794 | /** | |
795 | * iwl_get_channel_info - Find driver's private channel info | |
796 | * | |
797 | * Based on band and channel number. | |
798 | */ | |
82a66bbb TW |
799 | const struct iwl_channel_info *iwl_get_channel_info(const struct iwl_priv *priv, |
800 | enum ieee80211_band band, u16 channel) | |
bf85ea4f AK |
801 | { |
802 | int i; | |
803 | ||
804 | switch (band) { | |
805 | case IEEE80211_BAND_5GHZ: | |
806 | for (i = 14; i < priv->channel_count; i++) { | |
807 | if (priv->channel_info[i].channel == channel) | |
808 | return &priv->channel_info[i]; | |
809 | } | |
810 | break; | |
811 | case IEEE80211_BAND_2GHZ: | |
812 | if (channel >= 1 && channel <= 14) | |
813 | return &priv->channel_info[channel - 1]; | |
814 | break; | |
815 | default: | |
816 | BUG(); | |
817 | } | |
818 | ||
819 | return NULL; | |
820 | } | |
8622e705 | 821 | EXPORT_SYMBOL(iwl_get_channel_info); |