projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iwlwifi: iwlmvm: LAR: disable LAR support due to NVM vs TLV conflict
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-nvm-parse.c
CommitLineData
b1e1adfa
JB		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
8b4139dc 9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
b1e1adfa
JB		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
410dc5aa 26 * in the file called COPYING.
b1e1adfa
JB		 27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
51368bf7 34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
8b4139dc 35 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
b1e1adfa
JB		 36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *****************************************************************************/
64#include <linux/types.h>
65#include <linux/slab.h>
66#include <linux/export.h>
9f32e017 67#include <linux/etherdevice.h>
1e0b393a 68#include <linux/pci.h>
48e29340 69#include "iwl-drv.h"
b1e1adfa
JB		 70#include "iwl-modparams.h"
71#include "iwl-nvm-parse.h"
72
73/* NVM offsets (in words) definitions */
74enum wkp_nvm_offsets {
75 /* NVM HW-Section offset (in words) definitions */
76 HW_ADDR = 0x15,
77
77db0a3c 78 /* NVM SW-Section offset (in words) definitions */
b1e1adfa
JB		 79 NVM_SW_SECTION = 0x1C0,
80 NVM_VERSION = 0,
81 RADIO_CFG = 1,
82 SKU = 2,
83 N_HW_ADDRS = 3,
84 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
85
77db0a3c 86 /* NVM calibration section offset (in words) definitions */
b1e1adfa
JB		 87 NVM_CALIB_SECTION = 0x2B8,
88 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION
89};
90
77db0a3c
EH		 91enum family_8000_nvm_offsets {
92 /* NVM HW-Section offset (in words) definitions */
1e0b393a
EH		 93 HW_ADDR0_WFPM_FAMILY_8000 = 0x12,
94 HW_ADDR1_WFPM_FAMILY_8000 = 0x16,
95 HW_ADDR0_PCIE_FAMILY_8000 = 0x8A,
96 HW_ADDR1_PCIE_FAMILY_8000 = 0x8E,
77db0a3c
EH		 97 MAC_ADDRESS_OVERRIDE_FAMILY_8000 = 1,
98
99 /* NVM SW-Section offset (in words) definitions */
100 NVM_SW_SECTION_FAMILY_8000 = 0x1C0,
101 NVM_VERSION_FAMILY_8000 = 0,
102 RADIO_CFG_FAMILY_8000 = 2,
103 SKU_FAMILY_8000 = 4,
104 N_HW_ADDRS_FAMILY_8000 = 5,
105
106 /* NVM REGULATORY -Section offset (in words) definitions */
107 NVM_CHANNELS_FAMILY_8000 = 0,
d0d15197
MG		 108 NVM_LAR_OFFSET_FAMILY_8000 = 0x4C7,
109 NVM_LAR_ENABLED_FAMILY_8000 = 0x7,
77db0a3c
EH		 110
111 /* NVM calibration section offset (in words) definitions */
112 NVM_CALIB_SECTION_FAMILY_8000 = 0x2B8,
113 XTAL_CALIB_FAMILY_8000 = 0x316 - NVM_CALIB_SECTION_FAMILY_8000
114};
115
b1e1adfa
JB		 116/* SKU Capabilities (actual values from NVM definition) */
117enum nvm_sku_bits {
118 NVM_SKU_CAP_BAND_24GHZ = BIT(0),
119 NVM_SKU_CAP_BAND_52GHZ = BIT(1),
120 NVM_SKU_CAP_11N_ENABLE = BIT(2),
bfc824b0 121 NVM_SKU_CAP_11AC_ENABLE = BIT(3),
b1e1adfa
JB		 122};
123
b1e1adfa
JB		 124/*
125 * These are the channel numbers in the order that they are stored in the NVM
126 */
127static const u8 iwl_nvm_channels[] = {
128 /* 2.4 GHz */
129 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
130 /* 5 GHz */
131 36, 40, 44 , 48, 52, 56, 60, 64,
132 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
133 149, 153, 157, 161, 165
134};
135
77db0a3c
EH		 136static const u8 iwl_nvm_channels_family_8000[] = {
137 /* 2.4 GHz */
9b1c9a66 138 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
77db0a3c
EH		 139 /* 5 GHz */
140 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
141 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
142 149, 153, 157, 161, 165, 169, 173, 177, 181
143};
144
749f1fe1 145#define IWL_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
77db0a3c 146#define IWL_NUM_CHANNELS_FAMILY_8000 ARRAY_SIZE(iwl_nvm_channels_family_8000)
749f1fe1 147#define NUM_2GHZ_CHANNELS 14
9b1c9a66 148#define NUM_2GHZ_CHANNELS_FAMILY_8000 14
749f1fe1
EH		 149#define FIRST_2GHZ_HT_MINUS 5
150#define LAST_2GHZ_HT_PLUS 9
b281c93d
MG		 151#define LAST_5GHZ_HT 165
152#define LAST_5GHZ_HT_FAMILY_8000 181
b1e1adfa 153
b1e1adfa
JB		 154/* rate data (static) */
155static struct ieee80211_rate iwl_cfg80211_rates[] = {
156 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
157 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
158 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
159 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
161 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
162 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
163 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
164 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
165 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
166 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
167 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
168 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
169 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
170 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
171};
172#define RATES_24_OFFS 0
173#define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
174#define RATES_52_OFFS 4
175#define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
176
177/**
178 * enum iwl_nvm_channel_flags - channel flags in NVM
179 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
180 * @NVM_CHANNEL_IBSS: usable as an IBSS channel
181 * @NVM_CHANNEL_ACTIVE: active scanning allowed
182 * @NVM_CHANNEL_RADAR: radar detection required
9ee6dace
DS		 183 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
184 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
185 * on same channel on 2.4 or same UNII band on 5.2
b1e1adfa
JB		 186 * @NVM_CHANNEL_WIDE: 20 MHz channel okay (?)
187 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay (?)
33158fef
EL		 188 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay (?)
189 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay (?)
b1e1adfa
JB		 190 */
191enum iwl_nvm_channel_flags {
192 NVM_CHANNEL_VALID = BIT(0),
193 NVM_CHANNEL_IBSS = BIT(1),
194 NVM_CHANNEL_ACTIVE = BIT(3),
195 NVM_CHANNEL_RADAR = BIT(4),
9ee6dace
DS		 196 NVM_CHANNEL_INDOOR_ONLY = BIT(5),
197 NVM_CHANNEL_GO_CONCURRENT = BIT(6),
b1e1adfa
JB		 198 NVM_CHANNEL_WIDE = BIT(8),
199 NVM_CHANNEL_40MHZ = BIT(9),
33158fef
EL		 200 NVM_CHANNEL_80MHZ = BIT(10),
201 NVM_CHANNEL_160MHZ = BIT(11),
b1e1adfa
JB		 202};
203
204#define CHECK_AND_PRINT_I(x) \
205 ((ch_flags & NVM_CHANNEL_##x) ? # x " " : "")
206
770ceda6 207static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz,
b281c93d 208 u16 nvm_flags, const struct iwl_cfg *cfg)
770ceda6
AN		 209{
210 u32 flags = IEEE80211_CHAN_NO_HT40;
b281c93d
MG		 211 u32 last_5ghz_ht = LAST_5GHZ_HT;
212
213 if (cfg->device_family == IWL_DEVICE_FAMILY_8000)
214 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000;
770ceda6
AN		 215
216 if (!is_5ghz && (nvm_flags & NVM_CHANNEL_40MHZ)) {
217 if (ch_num <= LAST_2GHZ_HT_PLUS)
218 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
219 if (ch_num >= FIRST_2GHZ_HT_MINUS)
220 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
b281c93d 221 } else if (ch_num <= last_5ghz_ht && (nvm_flags & NVM_CHANNEL_40MHZ)) {
770ceda6
AN		 222 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
223 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
224 else
225 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
226 }
227 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
228 flags |= IEEE80211_CHAN_NO_80MHZ;
229 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
230 flags |= IEEE80211_CHAN_NO_160MHZ;
231
232 if (!(nvm_flags & NVM_CHANNEL_IBSS))
233 flags |= IEEE80211_CHAN_NO_IR;
234
235 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
236 flags |= IEEE80211_CHAN_NO_IR;
237
238 if (nvm_flags & NVM_CHANNEL_RADAR)
239 flags |= IEEE80211_CHAN_RADAR;
240
241 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
242 flags |= IEEE80211_CHAN_INDOOR_ONLY;
243
244 /* Set the GO concurrent flag only in case that NO_IR is set.
245 * Otherwise it is meaningless
246 */
247 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
248 (flags & IEEE80211_CHAN_NO_IR))
249 flags |= IEEE80211_CHAN_GO_CONCURRENT;
250
251 return flags;
252}
253
b1e1adfa
JB		 254static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
255 struct iwl_nvm_data *data,
770ceda6
AN		 256 const __le16 * const nvm_ch_flags,
257 bool lar_supported)
b1e1adfa
JB		 258{
259 int ch_idx;
260 int n_channels = 0;
261 struct ieee80211_channel *channel;
262 u16 ch_flags;
263 bool is_5ghz;
749f1fe1 264 int num_of_ch, num_2ghz_channels;
77db0a3c
EH		 265 const u8 *nvm_chan;
266
267 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
268 num_of_ch = IWL_NUM_CHANNELS;
269 nvm_chan = &iwl_nvm_channels[0];
749f1fe1 270 num_2ghz_channels = NUM_2GHZ_CHANNELS;
77db0a3c
EH		 271 } else {
272 num_of_ch = IWL_NUM_CHANNELS_FAMILY_8000;
273 nvm_chan = &iwl_nvm_channels_family_8000[0];
749f1fe1 274 num_2ghz_channels = NUM_2GHZ_CHANNELS_FAMILY_8000;
77db0a3c 275 }
b1e1adfa 276
77db0a3c 277 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
b1e1adfa 278 ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx);
c5128654 279
749f1fe1 280 if (ch_idx >= num_2ghz_channels &&
c5128654 281 !data->sku_cap_band_52GHz_enable)
a76f3bfe 282 continue;
c5128654 283
770ceda6 284 if (!lar_supported && !(ch_flags & NVM_CHANNEL_VALID)) {
a76f3bfe
EP		 285 /*
286 * Channels might become valid later if lar is
287 * supported, hence we still want to add them to
288 * the list of supported channels to cfg80211.
289 */
b1e1adfa
JB		 290 IWL_DEBUG_EEPROM(dev,
291 "Ch. %d Flags %x [%sGHz] - No traffic\n",
77db0a3c 292 nvm_chan[ch_idx],
b1e1adfa 293 ch_flags,
749f1fe1 294 (ch_idx >= num_2ghz_channels) ?
b1e1adfa
JB		 295 "5.2" : "2.4");
296 continue;
297 }
298
299 channel = &data->channels[n_channels];
300 n_channels++;
301
77db0a3c 302 channel->hw_value = nvm_chan[ch_idx];
749f1fe1 303 channel->band = (ch_idx < num_2ghz_channels) ?
b1e1adfa
JB		 304 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
305 channel->center_freq =
306 ieee80211_channel_to_frequency(
307 channel->hw_value, channel->band);
308
b1e1adfa
JB		 309 /* Initialize regulatory-based run-time data */
310
88f2fd73
MG		 311 /*
312 * Default value - highest tx power value. max_power
313 * is not used in mvm, and is used for backwards compatibility
314 */
22d059a5 315 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
b1e1adfa 316 is_5ghz = channel->band == IEEE80211_BAND_5GHZ;
770ceda6
AN		 317
318 /* don't put limitations in case we're using LAR */
319 if (!lar_supported)
320 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
321 ch_idx, is_5ghz,
b281c93d 322 ch_flags, cfg);
770ceda6
AN		 323 else
324 channel->flags = 0;
325
b1e1adfa 326 IWL_DEBUG_EEPROM(dev,
9ee6dace 327 "Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n",
b1e1adfa
JB		 328 channel->hw_value,
329 is_5ghz ? "5.2" : "2.4",
330 CHECK_AND_PRINT_I(VALID),
331 CHECK_AND_PRINT_I(IBSS),
332 CHECK_AND_PRINT_I(ACTIVE),
333 CHECK_AND_PRINT_I(RADAR),
334 CHECK_AND_PRINT_I(WIDE),
9ee6dace
DS		 335 CHECK_AND_PRINT_I(INDOOR_ONLY),
336 CHECK_AND_PRINT_I(GO_CONCURRENT),
b1e1adfa
JB		 337 ch_flags,
338 channel->max_power,
339 ((ch_flags & NVM_CHANNEL_IBSS) &&
340 !(ch_flags & NVM_CHANNEL_RADAR))
341 ? "" : "not ");
342 }
343
344 return n_channels;
345}
346
33158fef
EL		 347static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg,
348 struct iwl_nvm_data *data,
6ca89f1f
JB		 349 struct ieee80211_sta_vht_cap *vht_cap,
350 u8 tx_chains, u8 rx_chains)
33158fef 351{
6ca89f1f
JB		 352 int num_rx_ants = num_of_ant(rx_chains);
353 int num_tx_ants = num_of_ant(tx_chains);
c064ddf3
EH		 354 unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
355 IEEE80211_VHT_MAX_AMPDU_1024K);
48e6de61 356
33158fef
EL		 357 vht_cap->vht_supported = true;
358
359 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
360 IEEE80211_VHT_CAP_RXSTBC_1 |
361 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
e36b766d 362 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
c064ddf3
EH		 363 max_ampdu_exponent <<
364 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
33158fef 365
a3576ff2
ES		 366 if (cfg->ht_params->ldpc)
367 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
368
6ca89f1f 369 if (num_tx_ants > 1)
5f7a6f9b 370 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
6ca89f1f
JB		 371 else
372 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
5f7a6f9b 373
33158fef
EL		 374 if (iwlwifi_mod_params.amsdu_size_8K)
375 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
376
377 vht_cap->vht_mcs.rx_mcs_map =
378 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
379 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
380 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
381 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
382 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
383 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
384 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
385 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
386
6ca89f1f
JB		 387 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
388 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
33158fef
EL		 389 /* this works because NOT_SUPPORTED == 3 */
390 vht_cap->vht_mcs.rx_mcs_map |=
391 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
392 }
393
394 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
395}
396
b1e1adfa 397static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
77db0a3c
EH		 398 struct iwl_nvm_data *data,
399 const __le16 *ch_section, bool enable_vht,
770ceda6 400 u8 tx_chains, u8 rx_chains, bool lar_supported)
b1e1adfa 401{
77db0a3c 402 int n_channels;
b1e1adfa
JB		 403 int n_used = 0;
404 struct ieee80211_supported_band *sband;
405
77db0a3c
EH		 406 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
407 n_channels = iwl_init_channel_map(
408 dev, cfg, data,
770ceda6 409 &ch_section[NVM_CHANNELS], lar_supported);
77db0a3c
EH		 410 else
411 n_channels = iwl_init_channel_map(
412 dev, cfg, data,
770ceda6
AN		 413 &ch_section[NVM_CHANNELS_FAMILY_8000],
414 lar_supported);
77db0a3c 415
b1e1adfa
JB		 416 sband = &data->bands[IEEE80211_BAND_2GHZ];
417 sband->band = IEEE80211_BAND_2GHZ;
418 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
419 sband->n_bitrates = N_RATES_24;
420 n_used += iwl_init_sband_channels(data, sband, n_channels,
421 IEEE80211_BAND_2GHZ);
9ce4fa72
EG		 422 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_2GHZ,
423 tx_chains, rx_chains);
b1e1adfa
JB		 424
425 sband = &data->bands[IEEE80211_BAND_5GHZ];
426 sband->band = IEEE80211_BAND_5GHZ;
427 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
428 sband->n_bitrates = N_RATES_52;
429 n_used += iwl_init_sband_channels(data, sband, n_channels,
430 IEEE80211_BAND_5GHZ);
9ce4fa72
EG		 431 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_5GHZ,
432 tx_chains, rx_chains);
bfc824b0 433 if (enable_vht)
6ca89f1f
JB		 434 iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap,
435 tx_chains, rx_chains);
b1e1adfa
JB		 436
437 if (n_channels != n_used)
438 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
439 n_used, n_channels);
440}
441
77db0a3c
EH		 442static int iwl_get_sku(const struct iwl_cfg *cfg,
443 const __le16 *nvm_sw)
444{
445 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
446 return le16_to_cpup(nvm_sw + SKU);
447 else
448 return le32_to_cpup((__le32 *)(nvm_sw + SKU_FAMILY_8000));
449}
450
451static int iwl_get_nvm_version(const struct iwl_cfg *cfg,
452 const __le16 *nvm_sw)
453{
454 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
455 return le16_to_cpup(nvm_sw + NVM_VERSION);
456 else
457 return le32_to_cpup((__le32 *)(nvm_sw +
458 NVM_VERSION_FAMILY_8000));
459}
460
461static int iwl_get_radio_cfg(const struct iwl_cfg *cfg,
462 const __le16 *nvm_sw)
463{
464 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
465 return le16_to_cpup(nvm_sw + RADIO_CFG);
466 else
467 return le32_to_cpup((__le32 *)(nvm_sw + RADIO_CFG_FAMILY_8000));
468}
469
470#define N_HW_ADDRS_MASK_FAMILY_8000 0xF
471static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg,
472 const __le16 *nvm_sw)
473{
474 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
475 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
476 else
477 return le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000))
478 & N_HW_ADDRS_MASK_FAMILY_8000;
479}
480
481static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
482 struct iwl_nvm_data *data,
483 u32 radio_cfg)
484{
485 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
486 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
487 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
488 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
489 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
77db0a3c
EH		 490 return;
491 }
492
493 /* set the radio configuration for family 8000 */
494 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK_FAMILY_8000(radio_cfg);
495 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK_FAMILY_8000(radio_cfg);
496 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK_FAMILY_8000(radio_cfg);
497 data->radio_cfg_pnum = NVM_RF_CFG_FLAVOR_MSK_FAMILY_8000(radio_cfg);
a0544272
MH		 498 data->valid_tx_ant = NVM_RF_CFG_TX_ANT_MSK_FAMILY_8000(radio_cfg);
499 data->valid_rx_ant = NVM_RF_CFG_RX_ANT_MSK_FAMILY_8000(radio_cfg);
77db0a3c
EH		 500}
501
502static void iwl_set_hw_address(const struct iwl_cfg *cfg,
503 struct iwl_nvm_data *data,
504 const __le16 *nvm_sec)
505{
9f32e017 506 const u8 *hw_addr = (const u8 *)(nvm_sec + HW_ADDR);
77db0a3c
EH		 507
508 /* The byte order is little endian 16 bit, meaning 214365 */
509 data->hw_addr[0] = hw_addr[1];
510 data->hw_addr[1] = hw_addr[0];
511 data->hw_addr[2] = hw_addr[3];
512 data->hw_addr[3] = hw_addr[2];
513 data->hw_addr[4] = hw_addr[5];
514 data->hw_addr[5] = hw_addr[4];
515}
516
6a68a39f
EH		 517static void iwl_set_hw_address_family_8000(struct device *dev,
518 const struct iwl_cfg *cfg,
9f32e017
EH		 519 struct iwl_nvm_data *data,
520 const __le16 *mac_override,
521 const __le16 *nvm_hw)
522{
523 const u8 *hw_addr;
524
525 if (mac_override) {
526 hw_addr = (const u8 *)(mac_override +
527 MAC_ADDRESS_OVERRIDE_FAMILY_8000);
528
529 /* The byte order is little endian 16 bit, meaning 214365 */
530 data->hw_addr[0] = hw_addr[1];
531 data->hw_addr[1] = hw_addr[0];
532 data->hw_addr[2] = hw_addr[3];
533 data->hw_addr[3] = hw_addr[2];
534 data->hw_addr[4] = hw_addr[5];
535 data->hw_addr[5] = hw_addr[4];
536
6a68a39f 537 if (is_valid_ether_addr(data->hw_addr))
9f32e017 538 return;
6a68a39f
EH		 539
540 IWL_ERR_DEV(dev,
541 "mac address from nvm override section is not valid\n");
9f32e017
EH		 542 }
543
6a68a39f 544 if (nvm_hw) {
1e0b393a
EH		 545 /* read the MAC address from OTP */
546 if (!dev_is_pci(dev) || (data->nvm_version < 0xE08)) {
547 /* read the mac address from the WFPM location */
548 hw_addr = (const u8 *)(nvm_hw +
549 HW_ADDR0_WFPM_FAMILY_8000);
550 data->hw_addr[0] = hw_addr[3];
551 data->hw_addr[1] = hw_addr[2];
552 data->hw_addr[2] = hw_addr[1];
553 data->hw_addr[3] = hw_addr[0];
554
555 hw_addr = (const u8 *)(nvm_hw +
556 HW_ADDR1_WFPM_FAMILY_8000);
557 data->hw_addr[4] = hw_addr[1];
558 data->hw_addr[5] = hw_addr[0];
559 } else if ((data->nvm_version >= 0xE08) &&
560 (data->nvm_version < 0xE0B)) {
561 /* read "reverse order" from the PCIe location */
562 hw_addr = (const u8 *)(nvm_hw +
563 HW_ADDR0_PCIE_FAMILY_8000);
564 data->hw_addr[5] = hw_addr[2];
565 data->hw_addr[4] = hw_addr[1];
566 data->hw_addr[3] = hw_addr[0];
567
568 hw_addr = (const u8 *)(nvm_hw +
569 HW_ADDR1_PCIE_FAMILY_8000);
570 data->hw_addr[2] = hw_addr[3];
571 data->hw_addr[1] = hw_addr[2];
572 data->hw_addr[0] = hw_addr[1];
573 } else {
574 /* read from the PCIe location */
575 hw_addr = (const u8 *)(nvm_hw +
576 HW_ADDR0_PCIE_FAMILY_8000);
577 data->hw_addr[5] = hw_addr[0];
578 data->hw_addr[4] = hw_addr[1];
579 data->hw_addr[3] = hw_addr[2];
580
581 hw_addr = (const u8 *)(nvm_hw +
582 HW_ADDR1_PCIE_FAMILY_8000);
583 data->hw_addr[2] = hw_addr[1];
584 data->hw_addr[1] = hw_addr[2];
585 data->hw_addr[0] = hw_addr[3];
586 }
ca55eb47
EH		 587 if (!is_valid_ether_addr(data->hw_addr))
588 IWL_ERR_DEV(dev,
589 "mac address from hw section is not valid\n");
1e0b393a 590
6a68a39f
EH		 591 return;
592 }
9f32e017 593
6a68a39f 594 IWL_ERR_DEV(dev, "mac address is not found\n");
9f32e017
EH		 595}
596
b1e1adfa
JB		 597struct iwl_nvm_data *
598iwl_parse_nvm_data(struct device *dev, const struct iwl_cfg *cfg,
599 const __le16 *nvm_hw, const __le16 *nvm_sw,
77db0a3c 600 const __le16 *nvm_calib, const __le16 *regulatory,
770ceda6 601 const __le16 *mac_override, u8 tx_chains, u8 rx_chains,
d0d15197 602 bool lar_fw_supported)
b1e1adfa
JB		 603{
604 struct iwl_nvm_data *data;
77db0a3c
EH		 605 u32 sku;
606 u32 radio_cfg;
d0d15197 607 u16 lar_config;
77db0a3c
EH		 608
609 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
610 data = kzalloc(sizeof(*data) +
611 sizeof(struct ieee80211_channel) *
612 IWL_NUM_CHANNELS,
613 GFP_KERNEL);
614 else
615 data = kzalloc(sizeof(*data) +
616 sizeof(struct ieee80211_channel) *
617 IWL_NUM_CHANNELS_FAMILY_8000,
618 GFP_KERNEL);
b1e1adfa
JB		 619 if (!data)
620 return NULL;
621
77db0a3c 622 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
b1e1adfa 623
77db0a3c
EH		 624 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw);
625 iwl_set_radio_cfg(cfg, data, radio_cfg);
a0544272
MH		 626 if (data->valid_tx_ant)
627 tx_chains &= data->valid_tx_ant;
628 if (data->valid_rx_ant)
629 rx_chains &= data->valid_rx_ant;
b1e1adfa 630
77db0a3c 631 sku = iwl_get_sku(cfg, nvm_sw);
b1e1adfa
JB		 632 data->sku_cap_band_24GHz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
633 data->sku_cap_band_52GHz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
634 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
77db0a3c 635 data->sku_cap_11ac_enable = sku & NVM_SKU_CAP_11AC_ENABLE;
b1e1adfa
JB		 636 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
637 data->sku_cap_11n_enable = false;
638
77db0a3c 639 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
b1e1adfa 640
77db0a3c
EH		 641 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
642 /* Checking for required sections */
643 if (!nvm_calib) {
644 IWL_ERR_DEV(dev,
645 "Can't parse empty Calib NVM sections\n");
1270c416 646 kfree(data);
77db0a3c
EH		 647 return NULL;
648 }
649 /* in family 8000 Xtal calibration values moved to OTP */
650 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
651 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
b1e1adfa
JB		 652 }
653
77db0a3c
EH		 654 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
655 iwl_set_hw_address(cfg, data, nvm_hw);
b1e1adfa 656
77db0a3c
EH		 657 iwl_init_sbands(dev, cfg, data, nvm_sw,
658 sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains,
d0d15197 659 rx_chains, lar_fw_supported);
77db0a3c 660 } else {
d0d15197
MG		 661 lar_config = le16_to_cpup(regulatory +
662 NVM_LAR_OFFSET_FAMILY_8000);
663 data->lar_enabled = !!(lar_config &
664 NVM_LAR_ENABLED_FAMILY_8000);
665
77db0a3c 666 /* MAC address in family 8000 */
6a68a39f
EH		 667 iwl_set_hw_address_family_8000(dev, cfg, data, mac_override,
668 nvm_hw);
b1e1adfa 669
77db0a3c
EH		 670 iwl_init_sbands(dev, cfg, data, regulatory,
671 sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains,
d0d15197
MG		 672 rx_chains, lar_fw_supported &&
673 data->lar_enabled);
77db0a3c 674 }
b1e1adfa 675
33b2f684 676 data->calib_version = 255;
b1e1adfa
JB		 677
678 return data;
679}
48e29340 680IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
af45a900
AN		 681
682static u32 iwl_nvm_get_regdom_bw_flags(const u8 *nvm_chan,
b281c93d
MG		 683 int ch_idx, u16 nvm_flags,
684 const struct iwl_cfg *cfg)
af45a900
AN		 685{
686 u32 flags = NL80211_RRF_NO_HT40;
b281c93d
MG		 687 u32 last_5ghz_ht = LAST_5GHZ_HT;
688
689 if (cfg->device_family == IWL_DEVICE_FAMILY_8000)
690 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000;
af45a900
AN		 691
692 if (ch_idx < NUM_2GHZ_CHANNELS &&
693 (nvm_flags & NVM_CHANNEL_40MHZ)) {
694 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
695 flags &= ~NL80211_RRF_NO_HT40PLUS;
696 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
697 flags &= ~NL80211_RRF_NO_HT40MINUS;
b281c93d 698 } else if (nvm_chan[ch_idx] <= last_5ghz_ht &&
af45a900
AN		 699 (nvm_flags & NVM_CHANNEL_40MHZ)) {
700 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
701 flags &= ~NL80211_RRF_NO_HT40PLUS;
702 else
703 flags &= ~NL80211_RRF_NO_HT40MINUS;
704 }
705
706 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
707 flags |= NL80211_RRF_NO_80MHZ;
708 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
709 flags |= NL80211_RRF_NO_160MHZ;
710
af45a900
AN		 711 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
712 flags |= NL80211_RRF_NO_IR;
713
714 if (nvm_flags & NVM_CHANNEL_RADAR)
715 flags |= NL80211_RRF_DFS;
716
717 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
718 flags |= NL80211_RRF_NO_OUTDOOR;
719
720 /* Set the GO concurrent flag only in case that NO_IR is set.
721 * Otherwise it is meaningless
722 */
723 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
724 (flags & NL80211_RRF_NO_IR))
725 flags |= NL80211_RRF_GO_CONCURRENT;
726
727 return flags;
728}
729
730struct ieee80211_regdomain *
162ee3c9
AN		 731iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
732 int num_of_ch, __le32 *channels, u16 fw_mcc)
af45a900
AN		 733{
734 int ch_idx;
735 u16 ch_flags, prev_ch_flags = 0;
162ee3c9
AN		 736 const u8 *nvm_chan = cfg->device_family == IWL_DEVICE_FAMILY_8000 ?
737 iwl_nvm_channels_family_8000 : iwl_nvm_channels;
af45a900
AN		 738 struct ieee80211_regdomain *regd;
739 int size_of_regd;
740 struct ieee80211_reg_rule *rule;
741 enum ieee80211_band band;
742 int center_freq, prev_center_freq = 0;
743 int valid_rules = 0;
744 bool new_rule;
745
746 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
747 return ERR_PTR(-EINVAL);
748
749 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
750 num_of_ch);
751
752 /* build a regdomain rule for every valid channel */
753 size_of_regd =
754 sizeof(struct ieee80211_regdomain) +
755 num_of_ch * sizeof(struct ieee80211_reg_rule);
756
757 regd = kzalloc(size_of_regd, GFP_KERNEL);
758 if (!regd)
759 return ERR_PTR(-ENOMEM);
760
761 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
762 ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
763 band = (ch_idx < NUM_2GHZ_CHANNELS) ?
764 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
765 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
766 band);
767 new_rule = false;
768
769 if (!(ch_flags & NVM_CHANNEL_VALID)) {
770 IWL_DEBUG_DEV(dev, IWL_DL_LAR,
771 "Ch. %d Flags %x [%sGHz] - No traffic\n",
772 nvm_chan[ch_idx],
773 ch_flags,
774 (ch_idx >= NUM_2GHZ_CHANNELS) ?
775 "5.2" : "2.4");
776 continue;
777 }
778
779 /* we can't continue the same rule */
780 if (ch_idx == 0 || prev_ch_flags != ch_flags ||
781 center_freq - prev_center_freq > 20) {
782 valid_rules++;
783 new_rule = true;
784 }
785
786 rule = &regd->reg_rules[valid_rules - 1];
787
788 if (new_rule)
789 rule->freq_range.start_freq_khz =
790 MHZ_TO_KHZ(center_freq - 10);
791
792 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
793
794 /* this doesn't matter - not used by FW */
795 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
02a50495
EP		 796 rule->power_rule.max_eirp =
797 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
af45a900
AN		 798
799 rule->flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
b281c93d 800 ch_flags, cfg);
af45a900
AN		 801
802 /* rely on auto-calculation to merge BW of contiguous chans */
803 rule->flags |= NL80211_RRF_AUTO_BW;
804 rule->freq_range.max_bandwidth_khz = 0;
805
806 prev_ch_flags = ch_flags;
807 prev_center_freq = center_freq;
808
809 IWL_DEBUG_DEV(dev, IWL_DL_LAR,
bdf2fae8 810 "Ch. %d [%sGHz] %s%s%s%s%s%s%s%s%s(0x%02x): Ad-Hoc %ssupported\n",
af45a900
AN		 811 center_freq,
812 band == IEEE80211_BAND_5GHZ ? "5.2" : "2.4",
813 CHECK_AND_PRINT_I(VALID),
af45a900
AN		 814 CHECK_AND_PRINT_I(ACTIVE),
815 CHECK_AND_PRINT_I(RADAR),
816 CHECK_AND_PRINT_I(WIDE),
817 CHECK_AND_PRINT_I(40MHZ),
818 CHECK_AND_PRINT_I(80MHZ),
819 CHECK_AND_PRINT_I(160MHZ),
820 CHECK_AND_PRINT_I(INDOOR_ONLY),
821 CHECK_AND_PRINT_I(GO_CONCURRENT),
822 ch_flags,
bdf2fae8 823 ((ch_flags & NVM_CHANNEL_ACTIVE) &&
af45a900
AN		 824 !(ch_flags & NVM_CHANNEL_RADAR))
825 ? "" : "not ");
826 }
827
828 regd->n_reg_rules = valid_rules;
829
830 /* set alpha2 from FW. */
831 regd->alpha2[0] = fw_mcc >> 8;
832 regd->alpha2[1] = fw_mcc & 0xff;
833
834 return regd;
835}
836IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
Linux kernel - Deliverables
This page took 0.315015 seconds and 5 git commands to generate.