Merge branch 'fix/rt5645' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-nvm-parse.c
CommitLineData
b1e1adfa
JB
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
5f0d98f2 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
b1e1adfa
JB
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
410dc5aa 26 * in the file called COPYING.
b1e1adfa
JB
27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
51368bf7 34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
5f0d98f2 35 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
b1e1adfa
JB
36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *****************************************************************************/
64#include <linux/types.h>
65#include <linux/slab.h>
66#include <linux/export.h>
9f32e017 67#include <linux/etherdevice.h>
1e0b393a 68#include <linux/pci.h>
48e29340 69#include "iwl-drv.h"
b1e1adfa
JB
70#include "iwl-modparams.h"
71#include "iwl-nvm-parse.h"
72
73/* NVM offsets (in words) definitions */
74enum wkp_nvm_offsets {
75 /* NVM HW-Section offset (in words) definitions */
76 HW_ADDR = 0x15,
77
77db0a3c 78 /* NVM SW-Section offset (in words) definitions */
b1e1adfa
JB
79 NVM_SW_SECTION = 0x1C0,
80 NVM_VERSION = 0,
81 RADIO_CFG = 1,
82 SKU = 2,
83 N_HW_ADDRS = 3,
84 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
85
77db0a3c 86 /* NVM calibration section offset (in words) definitions */
b1e1adfa
JB
87 NVM_CALIB_SECTION = 0x2B8,
88 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION
89};
90
77db0a3c
EH
91enum family_8000_nvm_offsets {
92 /* NVM HW-Section offset (in words) definitions */
1e0b393a
EH
93 HW_ADDR0_WFPM_FAMILY_8000 = 0x12,
94 HW_ADDR1_WFPM_FAMILY_8000 = 0x16,
95 HW_ADDR0_PCIE_FAMILY_8000 = 0x8A,
96 HW_ADDR1_PCIE_FAMILY_8000 = 0x8E,
77db0a3c
EH
97 MAC_ADDRESS_OVERRIDE_FAMILY_8000 = 1,
98
99 /* NVM SW-Section offset (in words) definitions */
100 NVM_SW_SECTION_FAMILY_8000 = 0x1C0,
101 NVM_VERSION_FAMILY_8000 = 0,
5dd9c68a
EG
102 RADIO_CFG_FAMILY_8000 = 0,
103 SKU_FAMILY_8000 = 2,
104 N_HW_ADDRS_FAMILY_8000 = 3,
ce500071 105
77db0a3c
EH
106 /* NVM REGULATORY -Section offset (in words) definitions */
107 NVM_CHANNELS_FAMILY_8000 = 0,
f5528631
AN
108 NVM_LAR_OFFSET_FAMILY_8000_OLD = 0x4C7,
109 NVM_LAR_OFFSET_FAMILY_8000 = 0x507,
d0d15197 110 NVM_LAR_ENABLED_FAMILY_8000 = 0x7,
77db0a3c
EH
111
112 /* NVM calibration section offset (in words) definitions */
113 NVM_CALIB_SECTION_FAMILY_8000 = 0x2B8,
114 XTAL_CALIB_FAMILY_8000 = 0x316 - NVM_CALIB_SECTION_FAMILY_8000
115};
116
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JB
117/* SKU Capabilities (actual values from NVM definition) */
118enum nvm_sku_bits {
5f0d98f2
EG
119 NVM_SKU_CAP_BAND_24GHZ = BIT(0),
120 NVM_SKU_CAP_BAND_52GHZ = BIT(1),
121 NVM_SKU_CAP_11N_ENABLE = BIT(2),
122 NVM_SKU_CAP_11AC_ENABLE = BIT(3),
123 NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
b1e1adfa
JB
124};
125
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JB
126/*
127 * These are the channel numbers in the order that they are stored in the NVM
128 */
129static const u8 iwl_nvm_channels[] = {
130 /* 2.4 GHz */
131 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
132 /* 5 GHz */
133 36, 40, 44 , 48, 52, 56, 60, 64,
134 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
135 149, 153, 157, 161, 165
136};
137
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EH
138static const u8 iwl_nvm_channels_family_8000[] = {
139 /* 2.4 GHz */
9b1c9a66 140 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
77db0a3c
EH
141 /* 5 GHz */
142 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
143 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
144 149, 153, 157, 161, 165, 169, 173, 177, 181
145};
146
749f1fe1 147#define IWL_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
77db0a3c 148#define IWL_NUM_CHANNELS_FAMILY_8000 ARRAY_SIZE(iwl_nvm_channels_family_8000)
749f1fe1 149#define NUM_2GHZ_CHANNELS 14
9b1c9a66 150#define NUM_2GHZ_CHANNELS_FAMILY_8000 14
749f1fe1
EH
151#define FIRST_2GHZ_HT_MINUS 5
152#define LAST_2GHZ_HT_PLUS 9
b281c93d
MG
153#define LAST_5GHZ_HT 165
154#define LAST_5GHZ_HT_FAMILY_8000 181
ce500071 155#define N_HW_ADDR_MASK 0xF
b1e1adfa 156
b1e1adfa
JB
157/* rate data (static) */
158static struct ieee80211_rate iwl_cfg80211_rates[] = {
159 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
160 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
161 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
162 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
164 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
165 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
166 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
167 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
168 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
169 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
170 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
171 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
172 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
173 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
174};
175#define RATES_24_OFFS 0
176#define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
177#define RATES_52_OFFS 4
178#define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
179
180/**
181 * enum iwl_nvm_channel_flags - channel flags in NVM
182 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
183 * @NVM_CHANNEL_IBSS: usable as an IBSS channel
184 * @NVM_CHANNEL_ACTIVE: active scanning allowed
185 * @NVM_CHANNEL_RADAR: radar detection required
9ee6dace
DS
186 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
187 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
188 * on same channel on 2.4 or same UNII band on 5.2
b1e1adfa
JB
189 * @NVM_CHANNEL_WIDE: 20 MHz channel okay (?)
190 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay (?)
33158fef
EL
191 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay (?)
192 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay (?)
b1e1adfa
JB
193 */
194enum iwl_nvm_channel_flags {
195 NVM_CHANNEL_VALID = BIT(0),
196 NVM_CHANNEL_IBSS = BIT(1),
197 NVM_CHANNEL_ACTIVE = BIT(3),
198 NVM_CHANNEL_RADAR = BIT(4),
9ee6dace
DS
199 NVM_CHANNEL_INDOOR_ONLY = BIT(5),
200 NVM_CHANNEL_GO_CONCURRENT = BIT(6),
b1e1adfa
JB
201 NVM_CHANNEL_WIDE = BIT(8),
202 NVM_CHANNEL_40MHZ = BIT(9),
33158fef
EL
203 NVM_CHANNEL_80MHZ = BIT(10),
204 NVM_CHANNEL_160MHZ = BIT(11),
b1e1adfa
JB
205};
206
207#define CHECK_AND_PRINT_I(x) \
208 ((ch_flags & NVM_CHANNEL_##x) ? # x " " : "")
209
770ceda6 210static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz,
b281c93d 211 u16 nvm_flags, const struct iwl_cfg *cfg)
770ceda6
AN
212{
213 u32 flags = IEEE80211_CHAN_NO_HT40;
b281c93d
MG
214 u32 last_5ghz_ht = LAST_5GHZ_HT;
215
216 if (cfg->device_family == IWL_DEVICE_FAMILY_8000)
217 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000;
770ceda6
AN
218
219 if (!is_5ghz && (nvm_flags & NVM_CHANNEL_40MHZ)) {
220 if (ch_num <= LAST_2GHZ_HT_PLUS)
221 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
222 if (ch_num >= FIRST_2GHZ_HT_MINUS)
223 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
b281c93d 224 } else if (ch_num <= last_5ghz_ht && (nvm_flags & NVM_CHANNEL_40MHZ)) {
770ceda6
AN
225 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
226 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
227 else
228 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
229 }
230 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
231 flags |= IEEE80211_CHAN_NO_80MHZ;
232 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
233 flags |= IEEE80211_CHAN_NO_160MHZ;
234
235 if (!(nvm_flags & NVM_CHANNEL_IBSS))
236 flags |= IEEE80211_CHAN_NO_IR;
237
238 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
239 flags |= IEEE80211_CHAN_NO_IR;
240
241 if (nvm_flags & NVM_CHANNEL_RADAR)
242 flags |= IEEE80211_CHAN_RADAR;
243
244 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
245 flags |= IEEE80211_CHAN_INDOOR_ONLY;
246
247 /* Set the GO concurrent flag only in case that NO_IR is set.
248 * Otherwise it is meaningless
249 */
250 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
251 (flags & IEEE80211_CHAN_NO_IR))
06f207fc 252 flags |= IEEE80211_CHAN_IR_CONCURRENT;
770ceda6
AN
253
254 return flags;
255}
256
b1e1adfa
JB
257static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
258 struct iwl_nvm_data *data,
770ceda6
AN
259 const __le16 * const nvm_ch_flags,
260 bool lar_supported)
b1e1adfa
JB
261{
262 int ch_idx;
263 int n_channels = 0;
264 struct ieee80211_channel *channel;
265 u16 ch_flags;
266 bool is_5ghz;
749f1fe1 267 int num_of_ch, num_2ghz_channels;
77db0a3c
EH
268 const u8 *nvm_chan;
269
270 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
271 num_of_ch = IWL_NUM_CHANNELS;
272 nvm_chan = &iwl_nvm_channels[0];
749f1fe1 273 num_2ghz_channels = NUM_2GHZ_CHANNELS;
77db0a3c
EH
274 } else {
275 num_of_ch = IWL_NUM_CHANNELS_FAMILY_8000;
276 nvm_chan = &iwl_nvm_channels_family_8000[0];
749f1fe1 277 num_2ghz_channels = NUM_2GHZ_CHANNELS_FAMILY_8000;
77db0a3c 278 }
b1e1adfa 279
77db0a3c 280 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
b1e1adfa 281 ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx);
c5128654 282
749f1fe1 283 if (ch_idx >= num_2ghz_channels &&
c5128654 284 !data->sku_cap_band_52GHz_enable)
a76f3bfe 285 continue;
c5128654 286
770ceda6 287 if (!lar_supported && !(ch_flags & NVM_CHANNEL_VALID)) {
a76f3bfe
EP
288 /*
289 * Channels might become valid later if lar is
290 * supported, hence we still want to add them to
291 * the list of supported channels to cfg80211.
292 */
b1e1adfa
JB
293 IWL_DEBUG_EEPROM(dev,
294 "Ch. %d Flags %x [%sGHz] - No traffic\n",
77db0a3c 295 nvm_chan[ch_idx],
b1e1adfa 296 ch_flags,
749f1fe1 297 (ch_idx >= num_2ghz_channels) ?
b1e1adfa
JB
298 "5.2" : "2.4");
299 continue;
300 }
301
302 channel = &data->channels[n_channels];
303 n_channels++;
304
77db0a3c 305 channel->hw_value = nvm_chan[ch_idx];
749f1fe1 306 channel->band = (ch_idx < num_2ghz_channels) ?
b1e1adfa
JB
307 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
308 channel->center_freq =
309 ieee80211_channel_to_frequency(
310 channel->hw_value, channel->band);
311
b1e1adfa
JB
312 /* Initialize regulatory-based run-time data */
313
88f2fd73
MG
314 /*
315 * Default value - highest tx power value. max_power
316 * is not used in mvm, and is used for backwards compatibility
317 */
22d059a5 318 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
b1e1adfa 319 is_5ghz = channel->band == IEEE80211_BAND_5GHZ;
770ceda6
AN
320
321 /* don't put limitations in case we're using LAR */
322 if (!lar_supported)
323 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
324 ch_idx, is_5ghz,
b281c93d 325 ch_flags, cfg);
770ceda6
AN
326 else
327 channel->flags = 0;
328
b1e1adfa 329 IWL_DEBUG_EEPROM(dev,
9ee6dace 330 "Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n",
b1e1adfa
JB
331 channel->hw_value,
332 is_5ghz ? "5.2" : "2.4",
333 CHECK_AND_PRINT_I(VALID),
334 CHECK_AND_PRINT_I(IBSS),
335 CHECK_AND_PRINT_I(ACTIVE),
336 CHECK_AND_PRINT_I(RADAR),
337 CHECK_AND_PRINT_I(WIDE),
9ee6dace
DS
338 CHECK_AND_PRINT_I(INDOOR_ONLY),
339 CHECK_AND_PRINT_I(GO_CONCURRENT),
b1e1adfa
JB
340 ch_flags,
341 channel->max_power,
342 ((ch_flags & NVM_CHANNEL_IBSS) &&
343 !(ch_flags & NVM_CHANNEL_RADAR))
344 ? "" : "not ");
345 }
346
347 return n_channels;
348}
349
33158fef
EL
350static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg,
351 struct iwl_nvm_data *data,
6ca89f1f
JB
352 struct ieee80211_sta_vht_cap *vht_cap,
353 u8 tx_chains, u8 rx_chains)
33158fef 354{
6ca89f1f
JB
355 int num_rx_ants = num_of_ant(rx_chains);
356 int num_tx_ants = num_of_ant(tx_chains);
c064ddf3
EH
357 unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
358 IEEE80211_VHT_MAX_AMPDU_1024K);
48e6de61 359
33158fef
EL
360 vht_cap->vht_supported = true;
361
362 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
363 IEEE80211_VHT_CAP_RXSTBC_1 |
364 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
e36b766d 365 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
c064ddf3
EH
366 max_ampdu_exponent <<
367 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
33158fef 368
a3576ff2
ES
369 if (cfg->ht_params->ldpc)
370 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
371
5f0d98f2
EG
372 if (data->sku_cap_mimo_disabled) {
373 num_rx_ants = 1;
374 num_tx_ants = 1;
375 }
376
6ca89f1f 377 if (num_tx_ants > 1)
5f7a6f9b 378 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
6ca89f1f
JB
379 else
380 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
5f7a6f9b 381
33158fef
EL
382 if (iwlwifi_mod_params.amsdu_size_8K)
383 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
384
385 vht_cap->vht_mcs.rx_mcs_map =
386 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
387 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
388 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
389 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
390 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
391 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
392 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
393 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
394
6ca89f1f
JB
395 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
396 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
33158fef
EL
397 /* this works because NOT_SUPPORTED == 3 */
398 vht_cap->vht_mcs.rx_mcs_map |=
399 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
400 }
401
402 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
403}
404
b1e1adfa 405static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
77db0a3c 406 struct iwl_nvm_data *data,
2926f958 407 const __le16 *ch_section,
770ceda6 408 u8 tx_chains, u8 rx_chains, bool lar_supported)
b1e1adfa 409{
77db0a3c 410 int n_channels;
b1e1adfa
JB
411 int n_used = 0;
412 struct ieee80211_supported_band *sband;
413
77db0a3c
EH
414 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
415 n_channels = iwl_init_channel_map(
416 dev, cfg, data,
770ceda6 417 &ch_section[NVM_CHANNELS], lar_supported);
77db0a3c
EH
418 else
419 n_channels = iwl_init_channel_map(
420 dev, cfg, data,
770ceda6
AN
421 &ch_section[NVM_CHANNELS_FAMILY_8000],
422 lar_supported);
77db0a3c 423
b1e1adfa
JB
424 sband = &data->bands[IEEE80211_BAND_2GHZ];
425 sband->band = IEEE80211_BAND_2GHZ;
426 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
427 sband->n_bitrates = N_RATES_24;
428 n_used += iwl_init_sband_channels(data, sband, n_channels,
429 IEEE80211_BAND_2GHZ);
9ce4fa72
EG
430 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_2GHZ,
431 tx_chains, rx_chains);
b1e1adfa
JB
432
433 sband = &data->bands[IEEE80211_BAND_5GHZ];
434 sband->band = IEEE80211_BAND_5GHZ;
435 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
436 sband->n_bitrates = N_RATES_52;
437 n_used += iwl_init_sband_channels(data, sband, n_channels,
438 IEEE80211_BAND_5GHZ);
9ce4fa72
EG
439 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_5GHZ,
440 tx_chains, rx_chains);
2926f958 441 if (data->sku_cap_11ac_enable)
6ca89f1f
JB
442 iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap,
443 tx_chains, rx_chains);
b1e1adfa
JB
444
445 if (n_channels != n_used)
446 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
447 n_used, n_channels);
448}
449
5dd9c68a
EG
450static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
451 const __le16 *phy_sku)
77db0a3c
EH
452{
453 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
454 return le16_to_cpup(nvm_sw + SKU);
ce500071 455
5dd9c68a 456 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000));
77db0a3c
EH
457}
458
5dd9c68a 459static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
77db0a3c
EH
460{
461 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
462 return le16_to_cpup(nvm_sw + NVM_VERSION);
463 else
464 return le32_to_cpup((__le32 *)(nvm_sw +
465 NVM_VERSION_FAMILY_8000));
466}
467
5dd9c68a
EG
468static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
469 const __le16 *phy_sku)
77db0a3c
EH
470{
471 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
472 return le16_to_cpup(nvm_sw + RADIO_CFG);
ce500071 473
f115fdfd 474 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_8000));
ce500071 475
77db0a3c
EH
476}
477
5dd9c68a 478static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
77db0a3c 479{
ce500071
EH
480 int n_hw_addr;
481
77db0a3c
EH
482 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
483 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
ce500071 484
5dd9c68a 485 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
ce500071
EH
486
487 return n_hw_addr & N_HW_ADDR_MASK;
77db0a3c
EH
488}
489
490static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
491 struct iwl_nvm_data *data,
492 u32 radio_cfg)
493{
494 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
495 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
496 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
497 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
498 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
77db0a3c
EH
499 return;
500 }
501
502 /* set the radio configuration for family 8000 */
503 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK_FAMILY_8000(radio_cfg);
504 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK_FAMILY_8000(radio_cfg);
505 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK_FAMILY_8000(radio_cfg);
506 data->radio_cfg_pnum = NVM_RF_CFG_FLAVOR_MSK_FAMILY_8000(radio_cfg);
a0544272
MH
507 data->valid_tx_ant = NVM_RF_CFG_TX_ANT_MSK_FAMILY_8000(radio_cfg);
508 data->valid_rx_ant = NVM_RF_CFG_RX_ANT_MSK_FAMILY_8000(radio_cfg);
77db0a3c
EH
509}
510
511static void iwl_set_hw_address(const struct iwl_cfg *cfg,
512 struct iwl_nvm_data *data,
513 const __le16 *nvm_sec)
514{
9f32e017 515 const u8 *hw_addr = (const u8 *)(nvm_sec + HW_ADDR);
77db0a3c
EH
516
517 /* The byte order is little endian 16 bit, meaning 214365 */
518 data->hw_addr[0] = hw_addr[1];
519 data->hw_addr[1] = hw_addr[0];
520 data->hw_addr[2] = hw_addr[3];
521 data->hw_addr[3] = hw_addr[2];
522 data->hw_addr[4] = hw_addr[5];
523 data->hw_addr[5] = hw_addr[4];
524}
525
6a68a39f
EH
526static void iwl_set_hw_address_family_8000(struct device *dev,
527 const struct iwl_cfg *cfg,
9f32e017
EH
528 struct iwl_nvm_data *data,
529 const __le16 *mac_override,
8ba2d7a1
EH
530 const __le16 *nvm_hw,
531 u32 mac_addr0, u32 mac_addr1)
9f32e017
EH
532{
533 const u8 *hw_addr;
534
535 if (mac_override) {
18f84673
LK
536 static const u8 reserved_mac[] = {
537 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
538 };
539
9f32e017
EH
540 hw_addr = (const u8 *)(mac_override +
541 MAC_ADDRESS_OVERRIDE_FAMILY_8000);
542
be88a1ad
LK
543 /*
544 * Store the MAC address from MAO section.
545 * No byte swapping is required in MAO section
546 */
547 memcpy(data->hw_addr, hw_addr, ETH_ALEN);
9f32e017 548
18f84673
LK
549 /*
550 * Force the use of the OTP MAC address in case of reserved MAC
551 * address in the NVM, or if address is given but invalid.
552 */
553 if (is_valid_ether_addr(data->hw_addr) &&
554 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
9f32e017 555 return;
6a68a39f
EH
556
557 IWL_ERR_DEV(dev,
558 "mac address from nvm override section is not valid\n");
9f32e017
EH
559 }
560
6a68a39f 561 if (nvm_hw) {
8ba2d7a1
EH
562 /* read the MAC address from HW resisters */
563 hw_addr = (const u8 *)&mac_addr0;
564 data->hw_addr[0] = hw_addr[3];
565 data->hw_addr[1] = hw_addr[2];
566 data->hw_addr[2] = hw_addr[1];
567 data->hw_addr[3] = hw_addr[0];
568
569 hw_addr = (const u8 *)&mac_addr1;
570 data->hw_addr[4] = hw_addr[1];
571 data->hw_addr[5] = hw_addr[0];
572
ca55eb47
EH
573 if (!is_valid_ether_addr(data->hw_addr))
574 IWL_ERR_DEV(dev,
575 "mac address from hw section is not valid\n");
1e0b393a 576
6a68a39f
EH
577 return;
578 }
9f32e017 579
6a68a39f 580 IWL_ERR_DEV(dev, "mac address is not found\n");
9f32e017
EH
581}
582
b1e1adfa
JB
583struct iwl_nvm_data *
584iwl_parse_nvm_data(struct device *dev, const struct iwl_cfg *cfg,
585 const __le16 *nvm_hw, const __le16 *nvm_sw,
77db0a3c 586 const __le16 *nvm_calib, const __le16 *regulatory,
ce500071 587 const __le16 *mac_override, const __le16 *phy_sku,
5dd9c68a 588 u8 tx_chains, u8 rx_chains, bool lar_fw_supported,
8ba2d7a1 589 u32 mac_addr0, u32 mac_addr1)
b1e1adfa
JB
590{
591 struct iwl_nvm_data *data;
77db0a3c
EH
592 u32 sku;
593 u32 radio_cfg;
d0d15197 594 u16 lar_config;
77db0a3c
EH
595
596 if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
597 data = kzalloc(sizeof(*data) +
598 sizeof(struct ieee80211_channel) *
599 IWL_NUM_CHANNELS,
600 GFP_KERNEL);
601 else
602 data = kzalloc(sizeof(*data) +
603 sizeof(struct ieee80211_channel) *
604 IWL_NUM_CHANNELS_FAMILY_8000,
605 GFP_KERNEL);
b1e1adfa
JB
606 if (!data)
607 return NULL;
608
77db0a3c 609 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
b1e1adfa 610
5dd9c68a 611 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
77db0a3c 612 iwl_set_radio_cfg(cfg, data, radio_cfg);
a0544272
MH
613 if (data->valid_tx_ant)
614 tx_chains &= data->valid_tx_ant;
615 if (data->valid_rx_ant)
616 rx_chains &= data->valid_rx_ant;
b1e1adfa 617
5dd9c68a 618 sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
b1e1adfa
JB
619 data->sku_cap_band_24GHz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
620 data->sku_cap_band_52GHz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
621 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
622 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
623 data->sku_cap_11n_enable = false;
2926f958
EP
624 data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
625 (sku & NVM_SKU_CAP_11AC_ENABLE);
5f0d98f2 626 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
b1e1adfa 627
5dd9c68a 628 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
b1e1adfa 629
77db0a3c
EH
630 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
631 /* Checking for required sections */
632 if (!nvm_calib) {
633 IWL_ERR_DEV(dev,
634 "Can't parse empty Calib NVM sections\n");
1270c416 635 kfree(data);
77db0a3c
EH
636 return NULL;
637 }
638 /* in family 8000 Xtal calibration values moved to OTP */
639 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
640 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
b1e1adfa
JB
641 }
642
77db0a3c
EH
643 if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
644 iwl_set_hw_address(cfg, data, nvm_hw);
b1e1adfa 645
77db0a3c 646 iwl_init_sbands(dev, cfg, data, nvm_sw,
2926f958 647 tx_chains, rx_chains, lar_fw_supported);
77db0a3c 648 } else {
f5528631
AN
649 u16 lar_offset = data->nvm_version < 0xE39 ?
650 NVM_LAR_OFFSET_FAMILY_8000_OLD :
651 NVM_LAR_OFFSET_FAMILY_8000;
652
653 lar_config = le16_to_cpup(regulatory + lar_offset);
d0d15197
MG
654 data->lar_enabled = !!(lar_config &
655 NVM_LAR_ENABLED_FAMILY_8000);
656
77db0a3c 657 /* MAC address in family 8000 */
6a68a39f 658 iwl_set_hw_address_family_8000(dev, cfg, data, mac_override,
8ba2d7a1 659 nvm_hw, mac_addr0, mac_addr1);
b1e1adfa 660
77db0a3c 661 iwl_init_sbands(dev, cfg, data, regulatory,
2926f958
EP
662 tx_chains, rx_chains,
663 lar_fw_supported && data->lar_enabled);
77db0a3c 664 }
b1e1adfa 665
33b2f684 666 data->calib_version = 255;
b1e1adfa
JB
667
668 return data;
669}
48e29340 670IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
af45a900
AN
671
672static u32 iwl_nvm_get_regdom_bw_flags(const u8 *nvm_chan,
b281c93d
MG
673 int ch_idx, u16 nvm_flags,
674 const struct iwl_cfg *cfg)
af45a900
AN
675{
676 u32 flags = NL80211_RRF_NO_HT40;
b281c93d
MG
677 u32 last_5ghz_ht = LAST_5GHZ_HT;
678
679 if (cfg->device_family == IWL_DEVICE_FAMILY_8000)
680 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000;
af45a900
AN
681
682 if (ch_idx < NUM_2GHZ_CHANNELS &&
683 (nvm_flags & NVM_CHANNEL_40MHZ)) {
684 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
685 flags &= ~NL80211_RRF_NO_HT40PLUS;
686 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
687 flags &= ~NL80211_RRF_NO_HT40MINUS;
b281c93d 688 } else if (nvm_chan[ch_idx] <= last_5ghz_ht &&
af45a900
AN
689 (nvm_flags & NVM_CHANNEL_40MHZ)) {
690 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
691 flags &= ~NL80211_RRF_NO_HT40PLUS;
692 else
693 flags &= ~NL80211_RRF_NO_HT40MINUS;
694 }
695
696 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
697 flags |= NL80211_RRF_NO_80MHZ;
698 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
699 flags |= NL80211_RRF_NO_160MHZ;
700
af45a900
AN
701 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
702 flags |= NL80211_RRF_NO_IR;
703
704 if (nvm_flags & NVM_CHANNEL_RADAR)
705 flags |= NL80211_RRF_DFS;
706
707 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
708 flags |= NL80211_RRF_NO_OUTDOOR;
709
710 /* Set the GO concurrent flag only in case that NO_IR is set.
711 * Otherwise it is meaningless
712 */
713 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
714 (flags & NL80211_RRF_NO_IR))
715 flags |= NL80211_RRF_GO_CONCURRENT;
716
717 return flags;
718}
719
720struct ieee80211_regdomain *
162ee3c9
AN
721iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
722 int num_of_ch, __le32 *channels, u16 fw_mcc)
af45a900
AN
723{
724 int ch_idx;
725 u16 ch_flags, prev_ch_flags = 0;
162ee3c9
AN
726 const u8 *nvm_chan = cfg->device_family == IWL_DEVICE_FAMILY_8000 ?
727 iwl_nvm_channels_family_8000 : iwl_nvm_channels;
af45a900
AN
728 struct ieee80211_regdomain *regd;
729 int size_of_regd;
730 struct ieee80211_reg_rule *rule;
731 enum ieee80211_band band;
732 int center_freq, prev_center_freq = 0;
733 int valid_rules = 0;
734 bool new_rule;
4557eaba
AN
735 int max_num_ch = cfg->device_family == IWL_DEVICE_FAMILY_8000 ?
736 IWL_NUM_CHANNELS_FAMILY_8000 : IWL_NUM_CHANNELS;
af45a900
AN
737
738 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
739 return ERR_PTR(-EINVAL);
740
4557eaba
AN
741 if (WARN_ON(num_of_ch > max_num_ch))
742 num_of_ch = max_num_ch;
743
af45a900
AN
744 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
745 num_of_ch);
746
747 /* build a regdomain rule for every valid channel */
748 size_of_regd =
749 sizeof(struct ieee80211_regdomain) +
750 num_of_ch * sizeof(struct ieee80211_reg_rule);
751
752 regd = kzalloc(size_of_regd, GFP_KERNEL);
753 if (!regd)
754 return ERR_PTR(-ENOMEM);
755
756 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
757 ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
758 band = (ch_idx < NUM_2GHZ_CHANNELS) ?
759 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
760 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
761 band);
762 new_rule = false;
763
764 if (!(ch_flags & NVM_CHANNEL_VALID)) {
765 IWL_DEBUG_DEV(dev, IWL_DL_LAR,
766 "Ch. %d Flags %x [%sGHz] - No traffic\n",
767 nvm_chan[ch_idx],
768 ch_flags,
769 (ch_idx >= NUM_2GHZ_CHANNELS) ?
770 "5.2" : "2.4");
771 continue;
772 }
773
774 /* we can't continue the same rule */
775 if (ch_idx == 0 || prev_ch_flags != ch_flags ||
776 center_freq - prev_center_freq > 20) {
777 valid_rules++;
778 new_rule = true;
779 }
780
781 rule = &regd->reg_rules[valid_rules - 1];
782
783 if (new_rule)
784 rule->freq_range.start_freq_khz =
785 MHZ_TO_KHZ(center_freq - 10);
786
787 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
788
789 /* this doesn't matter - not used by FW */
790 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
02a50495
EP
791 rule->power_rule.max_eirp =
792 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
af45a900
AN
793
794 rule->flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
b281c93d 795 ch_flags, cfg);
af45a900
AN
796
797 /* rely on auto-calculation to merge BW of contiguous chans */
798 rule->flags |= NL80211_RRF_AUTO_BW;
799 rule->freq_range.max_bandwidth_khz = 0;
800
801 prev_ch_flags = ch_flags;
802 prev_center_freq = center_freq;
803
804 IWL_DEBUG_DEV(dev, IWL_DL_LAR,
bdf2fae8 805 "Ch. %d [%sGHz] %s%s%s%s%s%s%s%s%s(0x%02x): Ad-Hoc %ssupported\n",
af45a900
AN
806 center_freq,
807 band == IEEE80211_BAND_5GHZ ? "5.2" : "2.4",
808 CHECK_AND_PRINT_I(VALID),
af45a900
AN
809 CHECK_AND_PRINT_I(ACTIVE),
810 CHECK_AND_PRINT_I(RADAR),
811 CHECK_AND_PRINT_I(WIDE),
812 CHECK_AND_PRINT_I(40MHZ),
813 CHECK_AND_PRINT_I(80MHZ),
814 CHECK_AND_PRINT_I(160MHZ),
815 CHECK_AND_PRINT_I(INDOOR_ONLY),
816 CHECK_AND_PRINT_I(GO_CONCURRENT),
817 ch_flags,
bdf2fae8 818 ((ch_flags & NVM_CHANNEL_ACTIVE) &&
af45a900
AN
819 !(ch_flags & NVM_CHANNEL_RADAR))
820 ? "" : "not ");
821 }
822
823 regd->n_reg_rules = valid_rules;
824
825 /* set alpha2 from FW. */
826 regd->alpha2[0] = fw_mcc >> 8;
827 regd->alpha2[1] = fw_mcc & 0xff;
828
829 return regd;
830}
831IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
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