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a55360e4 TW |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
1781a07f | 30 | #include <linux/etherdevice.h> |
a55360e4 | 31 | #include <net/mac80211.h> |
a05ffd39 | 32 | #include <asm/unaligned.h> |
a55360e4 TW |
33 | #include "iwl-eeprom.h" |
34 | #include "iwl-dev.h" | |
35 | #include "iwl-core.h" | |
36 | #include "iwl-sta.h" | |
37 | #include "iwl-io.h" | |
c1354754 | 38 | #include "iwl-calib.h" |
a55360e4 TW |
39 | #include "iwl-helpers.h" |
40 | /************************** RX-FUNCTIONS ****************************/ | |
41 | /* | |
42 | * Rx theory of operation | |
43 | * | |
44 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), | |
45 | * each of which point to Receive Buffers to be filled by the NIC. These get | |
46 | * used not only for Rx frames, but for any command response or notification | |
47 | * from the NIC. The driver and NIC manage the Rx buffers by means | |
48 | * of indexes into the circular buffer. | |
49 | * | |
50 | * Rx Queue Indexes | |
51 | * The host/firmware share two index registers for managing the Rx buffers. | |
52 | * | |
53 | * The READ index maps to the first position that the firmware may be writing | |
54 | * to -- the driver can read up to (but not including) this position and get | |
55 | * good data. | |
56 | * The READ index is managed by the firmware once the card is enabled. | |
57 | * | |
58 | * The WRITE index maps to the last position the driver has read from -- the | |
59 | * position preceding WRITE is the last slot the firmware can place a packet. | |
60 | * | |
61 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
62 | * WRITE = READ. | |
63 | * | |
64 | * During initialization, the host sets up the READ queue position to the first | |
65 | * INDEX position, and WRITE to the last (READ - 1 wrapped) | |
66 | * | |
67 | * When the firmware places a packet in a buffer, it will advance the READ index | |
68 | * and fire the RX interrupt. The driver can then query the READ index and | |
69 | * process as many packets as possible, moving the WRITE index forward as it | |
70 | * resets the Rx queue buffers with new memory. | |
71 | * | |
72 | * The management in the driver is as follows: | |
73 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
74 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
75 | * to replenish the iwl->rxq->rx_free. | |
76 | * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the | |
77 | * iwl->rxq is replenished and the READ INDEX is updated (updating the | |
78 | * 'processed' and 'read' driver indexes as well) | |
79 | * + A received packet is processed and handed to the kernel network stack, | |
80 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
81 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
82 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
83 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
84 | * were enough free buffers and RX_STALLED is set it is cleared. | |
85 | * | |
86 | * | |
87 | * Driver sequence: | |
88 | * | |
89 | * iwl_rx_queue_alloc() Allocates rx_free | |
90 | * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
91 | * iwl_rx_queue_restock | |
92 | * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx | |
93 | * queue, updates firmware pointers, and updates | |
94 | * the WRITE index. If insufficient rx_free buffers | |
95 | * are available, schedules iwl_rx_replenish | |
96 | * | |
97 | * -- enable interrupts -- | |
98 | * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the | |
99 | * READ INDEX, detaching the SKB from the pool. | |
100 | * Moves the packet buffer from queue to rx_used. | |
101 | * Calls iwl_rx_queue_restock to refill any empty | |
102 | * slots. | |
103 | * ... | |
104 | * | |
105 | */ | |
106 | ||
107 | /** | |
108 | * iwl_rx_queue_space - Return number of free slots available in queue. | |
109 | */ | |
110 | int iwl_rx_queue_space(const struct iwl_rx_queue *q) | |
111 | { | |
112 | int s = q->read - q->write; | |
113 | if (s <= 0) | |
114 | s += RX_QUEUE_SIZE; | |
115 | /* keep some buffer to not confuse full and empty queue */ | |
116 | s -= 2; | |
117 | if (s < 0) | |
118 | s = 0; | |
119 | return s; | |
120 | } | |
121 | EXPORT_SYMBOL(iwl_rx_queue_space); | |
122 | ||
123 | /** | |
124 | * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue | |
125 | */ | |
126 | int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q) | |
127 | { | |
128 | u32 reg = 0; | |
129 | int ret = 0; | |
130 | unsigned long flags; | |
131 | ||
132 | spin_lock_irqsave(&q->lock, flags); | |
133 | ||
134 | if (q->need_update == 0) | |
135 | goto exit_unlock; | |
136 | ||
137 | /* If power-saving is in use, make sure device is awake */ | |
138 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
139 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
140 | ||
141 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
142 | iwl_set_bit(priv, CSR_GP_CNTRL, | |
143 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
144 | goto exit_unlock; | |
145 | } | |
146 | ||
147 | ret = iwl_grab_nic_access(priv); | |
148 | if (ret) | |
149 | goto exit_unlock; | |
150 | ||
151 | /* Device expects a multiple of 8 */ | |
152 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, | |
153 | q->write & ~0x7); | |
154 | iwl_release_nic_access(priv); | |
155 | ||
156 | /* Else device is assumed to be awake */ | |
157 | } else | |
158 | /* Device expects a multiple of 8 */ | |
159 | iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7); | |
160 | ||
161 | ||
162 | q->need_update = 0; | |
163 | ||
164 | exit_unlock: | |
165 | spin_unlock_irqrestore(&q->lock, flags); | |
166 | return ret; | |
167 | } | |
168 | EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr); | |
169 | /** | |
170 | * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr | |
171 | */ | |
172 | static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv, | |
173 | dma_addr_t dma_addr) | |
174 | { | |
175 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
176 | } | |
177 | ||
178 | /** | |
179 | * iwl_rx_queue_restock - refill RX queue from pre-allocated pool | |
180 | * | |
181 | * If there are slots in the RX queue that need to be restocked, | |
182 | * and we have free pre-allocated buffers, fill the ranks as much | |
183 | * as we can, pulling from rx_free. | |
184 | * | |
185 | * This moves the 'write' index forward to catch up with 'processed', and | |
186 | * also updates the memory address in the firmware to reference the new | |
187 | * target buffer. | |
188 | */ | |
189 | int iwl_rx_queue_restock(struct iwl_priv *priv) | |
190 | { | |
191 | struct iwl_rx_queue *rxq = &priv->rxq; | |
192 | struct list_head *element; | |
193 | struct iwl_rx_mem_buffer *rxb; | |
194 | unsigned long flags; | |
195 | int write; | |
196 | int ret = 0; | |
197 | ||
198 | spin_lock_irqsave(&rxq->lock, flags); | |
199 | write = rxq->write & ~0x7; | |
200 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { | |
201 | /* Get next free Rx buffer, remove from free list */ | |
202 | element = rxq->rx_free.next; | |
203 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
204 | list_del(element); | |
205 | ||
206 | /* Point to Rx buffer via next RBD in circular buffer */ | |
207 | rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->dma_addr); | |
208 | rxq->queue[rxq->write] = rxb; | |
209 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
210 | rxq->free_count--; | |
211 | } | |
212 | spin_unlock_irqrestore(&rxq->lock, flags); | |
213 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
214 | * refill it */ | |
215 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
216 | queue_work(priv->workqueue, &priv->rx_replenish); | |
217 | ||
218 | ||
219 | /* If we've added more space for the firmware to place data, tell it. | |
220 | * Increment device's write pointer in multiples of 8. */ | |
221 | if ((write != (rxq->write & ~0x7)) | |
222 | || (abs(rxq->write - rxq->read) > 7)) { | |
223 | spin_lock_irqsave(&rxq->lock, flags); | |
224 | rxq->need_update = 1; | |
225 | spin_unlock_irqrestore(&rxq->lock, flags); | |
226 | ret = iwl_rx_queue_update_write_ptr(priv, rxq); | |
227 | } | |
228 | ||
229 | return ret; | |
230 | } | |
231 | EXPORT_SYMBOL(iwl_rx_queue_restock); | |
232 | ||
233 | ||
234 | /** | |
235 | * iwl_rx_replenish - Move all used packet from rx_used to rx_free | |
236 | * | |
237 | * When moving to rx_free an SKB is allocated for the slot. | |
238 | * | |
239 | * Also restock the Rx queue via iwl_rx_queue_restock. | |
240 | * This is called as a scheduled work item (except for during initialization) | |
241 | */ | |
242 | void iwl_rx_allocate(struct iwl_priv *priv) | |
243 | { | |
244 | struct iwl_rx_queue *rxq = &priv->rxq; | |
245 | struct list_head *element; | |
246 | struct iwl_rx_mem_buffer *rxb; | |
247 | unsigned long flags; | |
248 | spin_lock_irqsave(&rxq->lock, flags); | |
249 | while (!list_empty(&rxq->rx_used)) { | |
250 | element = rxq->rx_used.next; | |
251 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
252 | ||
253 | /* Alloc a new receive buffer */ | |
254 | rxb->skb = alloc_skb(priv->hw_params.rx_buf_size, | |
255 | __GFP_NOWARN | GFP_ATOMIC); | |
256 | if (!rxb->skb) { | |
257 | if (net_ratelimit()) | |
258 | printk(KERN_CRIT DRV_NAME | |
259 | ": Can not allocate SKB buffers\n"); | |
260 | /* We don't reschedule replenish work here -- we will | |
261 | * call the restock method and if it still needs | |
262 | * more buffers it will schedule replenish */ | |
263 | break; | |
264 | } | |
265 | priv->alloc_rxb_skb++; | |
266 | list_del(element); | |
267 | ||
268 | /* Get physical address of RB/SKB */ | |
269 | rxb->dma_addr = | |
270 | pci_map_single(priv->pci_dev, rxb->skb->data, | |
271 | priv->hw_params.rx_buf_size, PCI_DMA_FROMDEVICE); | |
272 | list_add_tail(&rxb->list, &rxq->rx_free); | |
273 | rxq->free_count++; | |
274 | } | |
275 | spin_unlock_irqrestore(&rxq->lock, flags); | |
276 | } | |
277 | EXPORT_SYMBOL(iwl_rx_allocate); | |
278 | ||
279 | void iwl_rx_replenish(struct iwl_priv *priv) | |
280 | { | |
281 | unsigned long flags; | |
282 | ||
283 | iwl_rx_allocate(priv); | |
284 | ||
285 | spin_lock_irqsave(&priv->lock, flags); | |
286 | iwl_rx_queue_restock(priv); | |
287 | spin_unlock_irqrestore(&priv->lock, flags); | |
288 | } | |
289 | EXPORT_SYMBOL(iwl_rx_replenish); | |
290 | ||
291 | ||
292 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. | |
293 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL | |
294 | * This free routine walks the list of POOL entries and if SKB is set to | |
295 | * non NULL it is unmapped and freed | |
296 | */ | |
297 | void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
298 | { | |
299 | int i; | |
300 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
301 | if (rxq->pool[i].skb != NULL) { | |
302 | pci_unmap_single(priv->pci_dev, | |
303 | rxq->pool[i].dma_addr, | |
304 | priv->hw_params.rx_buf_size, | |
305 | PCI_DMA_FROMDEVICE); | |
306 | dev_kfree_skb(rxq->pool[i].skb); | |
307 | } | |
308 | } | |
309 | ||
310 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
311 | rxq->dma_addr); | |
312 | rxq->bd = NULL; | |
313 | } | |
314 | EXPORT_SYMBOL(iwl_rx_queue_free); | |
315 | ||
316 | int iwl_rx_queue_alloc(struct iwl_priv *priv) | |
317 | { | |
318 | struct iwl_rx_queue *rxq = &priv->rxq; | |
319 | struct pci_dev *dev = priv->pci_dev; | |
320 | int i; | |
321 | ||
322 | spin_lock_init(&rxq->lock); | |
323 | INIT_LIST_HEAD(&rxq->rx_free); | |
324 | INIT_LIST_HEAD(&rxq->rx_used); | |
325 | ||
326 | /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */ | |
327 | rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr); | |
328 | if (!rxq->bd) | |
329 | return -ENOMEM; | |
330 | ||
331 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
332 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) | |
333 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
334 | ||
335 | /* Set us so that we have processed and used all buffers, but have | |
336 | * not restocked the Rx queue with fresh buffers */ | |
337 | rxq->read = rxq->write = 0; | |
338 | rxq->free_count = 0; | |
339 | rxq->need_update = 0; | |
340 | return 0; | |
341 | } | |
342 | EXPORT_SYMBOL(iwl_rx_queue_alloc); | |
343 | ||
344 | void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
345 | { | |
346 | unsigned long flags; | |
347 | int i; | |
348 | spin_lock_irqsave(&rxq->lock, flags); | |
349 | INIT_LIST_HEAD(&rxq->rx_free); | |
350 | INIT_LIST_HEAD(&rxq->rx_used); | |
351 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
352 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
353 | /* In the reset function, these buffers may have been allocated | |
354 | * to an SKB, so we need to unmap and free potential storage */ | |
355 | if (rxq->pool[i].skb != NULL) { | |
356 | pci_unmap_single(priv->pci_dev, | |
357 | rxq->pool[i].dma_addr, | |
358 | priv->hw_params.rx_buf_size, | |
359 | PCI_DMA_FROMDEVICE); | |
360 | priv->alloc_rxb_skb--; | |
361 | dev_kfree_skb(rxq->pool[i].skb); | |
362 | rxq->pool[i].skb = NULL; | |
363 | } | |
364 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
365 | } | |
366 | ||
367 | /* Set us so that we have processed and used all buffers, but have | |
368 | * not restocked the Rx queue with fresh buffers */ | |
369 | rxq->read = rxq->write = 0; | |
370 | rxq->free_count = 0; | |
371 | spin_unlock_irqrestore(&rxq->lock, flags); | |
372 | } | |
373 | EXPORT_SYMBOL(iwl_rx_queue_reset); | |
374 | ||
1053d35f RR |
375 | int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) |
376 | { | |
377 | int ret; | |
378 | unsigned long flags; | |
8cd519e8 WT |
379 | u32 rb_size; |
380 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ | |
381 | const u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT why this stalls RX */ | |
1053d35f RR |
382 | |
383 | spin_lock_irqsave(&priv->lock, flags); | |
384 | ret = iwl_grab_nic_access(priv); | |
385 | if (ret) { | |
386 | spin_unlock_irqrestore(&priv->lock, flags); | |
387 | return ret; | |
388 | } | |
389 | ||
390 | if (priv->cfg->mod_params->amsdu_size_8K) | |
391 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; | |
392 | else | |
393 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | |
394 | ||
395 | /* Stop Rx DMA */ | |
396 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | |
397 | ||
398 | /* Reset driver's Rx queue write index */ | |
399 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); | |
400 | ||
401 | /* Tell device where to find RBD circular buffer in DRAM */ | |
402 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
8cd519e8 | 403 | (u32)(rxq->dma_addr >> 8)); |
1053d35f RR |
404 | |
405 | /* Tell device where in DRAM to update its Rx status */ | |
406 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
d67f5489 | 407 | (priv->shared_phys + priv->rb_closed_offset) >> 4); |
1053d35f | 408 | |
8cd519e8 WT |
409 | /* Enable Rx DMA |
410 | * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set becuase of HW bug in | |
411 | * the credit mechanism in 5000 HW RX FIFO | |
412 | * Direct rx interrupts to hosts | |
413 | * Rx buffer size 4 or 8k | |
414 | * RB timeout 0x10 | |
415 | * 256 RBDs | |
416 | */ | |
1053d35f RR |
417 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, |
418 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | | |
8cd519e8 | 419 | FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | |
1053d35f | 420 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | |
8cd519e8 WT |
421 | rb_size| |
422 | (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| | |
423 | (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); | |
1053d35f RR |
424 | |
425 | iwl_release_nic_access(priv); | |
8cd519e8 WT |
426 | |
427 | iwl_write32(priv, CSR_INT_COALESCING, 0x40); | |
428 | ||
1053d35f RR |
429 | spin_unlock_irqrestore(&priv->lock, flags); |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
b3bbacb7 TW |
434 | int iwl_rxq_stop(struct iwl_priv *priv) |
435 | { | |
436 | int ret; | |
437 | unsigned long flags; | |
438 | ||
439 | spin_lock_irqsave(&priv->lock, flags); | |
440 | ret = iwl_grab_nic_access(priv); | |
441 | if (unlikely(ret)) { | |
442 | spin_unlock_irqrestore(&priv->lock, flags); | |
443 | return ret; | |
444 | } | |
445 | ||
446 | /* stop Rx DMA */ | |
447 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | |
448 | ret = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG, | |
449 | (1 << 24), 1000); | |
450 | if (ret < 0) | |
451 | IWL_ERROR("Can't stop Rx DMA.\n"); | |
452 | ||
453 | iwl_release_nic_access(priv); | |
454 | spin_unlock_irqrestore(&priv->lock, flags); | |
455 | ||
456 | return 0; | |
457 | } | |
458 | EXPORT_SYMBOL(iwl_rxq_stop); | |
459 | ||
c1354754 TW |
460 | void iwl_rx_missed_beacon_notif(struct iwl_priv *priv, |
461 | struct iwl_rx_mem_buffer *rxb) | |
462 | ||
463 | { | |
c1354754 TW |
464 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
465 | struct iwl4965_missed_beacon_notif *missed_beacon; | |
466 | ||
467 | missed_beacon = &pkt->u.missed_beacon; | |
468 | if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) { | |
469 | IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n", | |
470 | le32_to_cpu(missed_beacon->consequtive_missed_beacons), | |
471 | le32_to_cpu(missed_beacon->total_missed_becons), | |
472 | le32_to_cpu(missed_beacon->num_recvd_beacons), | |
473 | le32_to_cpu(missed_beacon->num_expected_beacons)); | |
474 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
475 | iwl_init_sensitivity(priv); | |
476 | } | |
c1354754 TW |
477 | } |
478 | EXPORT_SYMBOL(iwl_rx_missed_beacon_notif); | |
8f91aecb | 479 | |
0c70515f RR |
480 | int iwl_rx_agg_start(struct iwl_priv *priv, const u8 *addr, int tid, u16 ssn) |
481 | { | |
482 | unsigned long flags; | |
483 | int sta_id; | |
484 | ||
485 | sta_id = iwl_find_station(priv, addr); | |
486 | if (sta_id == IWL_INVALID_STATION) | |
487 | return -ENXIO; | |
488 | ||
489 | spin_lock_irqsave(&priv->sta_lock, flags); | |
490 | priv->stations[sta_id].sta.station_flags_msk = 0; | |
491 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK; | |
492 | priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid; | |
493 | priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn); | |
494 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
495 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
496 | ||
497 | return iwl_send_add_sta(priv, &priv->stations[sta_id].sta, | |
498 | CMD_ASYNC); | |
499 | } | |
500 | EXPORT_SYMBOL(iwl_rx_agg_start); | |
501 | ||
502 | int iwl_rx_agg_stop(struct iwl_priv *priv, const u8 *addr, int tid) | |
503 | { | |
504 | unsigned long flags; | |
505 | int sta_id; | |
506 | ||
507 | sta_id = iwl_find_station(priv, addr); | |
508 | if (sta_id == IWL_INVALID_STATION) | |
509 | return -ENXIO; | |
510 | ||
511 | spin_lock_irqsave(&priv->sta_lock, flags); | |
512 | priv->stations[sta_id].sta.station_flags_msk = 0; | |
513 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK; | |
514 | priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid; | |
515 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
516 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
517 | ||
518 | return iwl_send_add_sta(priv, &priv->stations[sta_id].sta, | |
519 | CMD_ASYNC); | |
520 | } | |
521 | EXPORT_SYMBOL(iwl_rx_agg_stop); | |
522 | ||
8f91aecb EG |
523 | |
524 | /* Calculate noise level, based on measurements during network silence just | |
525 | * before arriving beacon. This measurement can be done only if we know | |
526 | * exactly when to expect beacons, therefore only when we're associated. */ | |
527 | static void iwl_rx_calc_noise(struct iwl_priv *priv) | |
528 | { | |
529 | struct statistics_rx_non_phy *rx_info | |
530 | = &(priv->statistics.rx.general); | |
531 | int num_active_rx = 0; | |
532 | int total_silence = 0; | |
533 | int bcn_silence_a = | |
534 | le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER; | |
535 | int bcn_silence_b = | |
536 | le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER; | |
537 | int bcn_silence_c = | |
538 | le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER; | |
539 | ||
540 | if (bcn_silence_a) { | |
541 | total_silence += bcn_silence_a; | |
542 | num_active_rx++; | |
543 | } | |
544 | if (bcn_silence_b) { | |
545 | total_silence += bcn_silence_b; | |
546 | num_active_rx++; | |
547 | } | |
548 | if (bcn_silence_c) { | |
549 | total_silence += bcn_silence_c; | |
550 | num_active_rx++; | |
551 | } | |
552 | ||
553 | /* Average among active antennas */ | |
554 | if (num_active_rx) | |
555 | priv->last_rx_noise = (total_silence / num_active_rx) - 107; | |
556 | else | |
557 | priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
558 | ||
559 | IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", | |
560 | bcn_silence_a, bcn_silence_b, bcn_silence_c, | |
561 | priv->last_rx_noise); | |
562 | } | |
563 | ||
564 | #define REG_RECALIB_PERIOD (60) | |
565 | ||
566 | void iwl_rx_statistics(struct iwl_priv *priv, | |
567 | struct iwl_rx_mem_buffer *rxb) | |
568 | { | |
5225640b | 569 | int change; |
8f91aecb EG |
570 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
571 | ||
572 | IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n", | |
573 | (int)sizeof(priv->statistics), pkt->len); | |
574 | ||
5225640b ZY |
575 | change = ((priv->statistics.general.temperature != |
576 | pkt->u.stats.general.temperature) || | |
577 | ((priv->statistics.flag & | |
578 | STATISTICS_REPLY_FLG_FAT_MODE_MSK) != | |
579 | (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK))); | |
580 | ||
8f91aecb EG |
581 | memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics)); |
582 | ||
583 | set_bit(STATUS_STATISTICS, &priv->status); | |
584 | ||
585 | /* Reschedule the statistics timer to occur in | |
586 | * REG_RECALIB_PERIOD seconds to ensure we get a | |
587 | * thermal update even if the uCode doesn't give | |
588 | * us one */ | |
589 | mod_timer(&priv->statistics_periodic, jiffies + | |
590 | msecs_to_jiffies(REG_RECALIB_PERIOD * 1000)); | |
591 | ||
592 | if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) && | |
593 | (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) { | |
594 | iwl_rx_calc_noise(priv); | |
595 | queue_work(priv->workqueue, &priv->run_time_calib_work); | |
596 | } | |
597 | ||
598 | iwl_leds_background(priv); | |
599 | ||
5225640b ZY |
600 | if (priv->cfg->ops->lib->temperature && change) |
601 | priv->cfg->ops->lib->temperature(priv); | |
8f91aecb EG |
602 | } |
603 | EXPORT_SYMBOL(iwl_rx_statistics); | |
1781a07f EG |
604 | |
605 | #define PERFECT_RSSI (-20) /* dBm */ | |
606 | #define WORST_RSSI (-95) /* dBm */ | |
607 | #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI) | |
608 | ||
609 | /* Calculate an indication of rx signal quality (a percentage, not dBm!). | |
610 | * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info | |
611 | * about formulas used below. */ | |
612 | static int iwl_calc_sig_qual(int rssi_dbm, int noise_dbm) | |
613 | { | |
614 | int sig_qual; | |
615 | int degradation = PERFECT_RSSI - rssi_dbm; | |
616 | ||
617 | /* If we get a noise measurement, use signal-to-noise ratio (SNR) | |
618 | * as indicator; formula is (signal dbm - noise dbm). | |
619 | * SNR at or above 40 is a great signal (100%). | |
620 | * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator. | |
621 | * Weakest usable signal is usually 10 - 15 dB SNR. */ | |
622 | if (noise_dbm) { | |
623 | if (rssi_dbm - noise_dbm >= 40) | |
624 | return 100; | |
625 | else if (rssi_dbm < noise_dbm) | |
626 | return 0; | |
627 | sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2; | |
628 | ||
629 | /* Else use just the signal level. | |
630 | * This formula is a least squares fit of data points collected and | |
631 | * compared with a reference system that had a percentage (%) display | |
632 | * for signal quality. */ | |
633 | } else | |
634 | sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation * | |
635 | (15 * RSSI_RANGE + 62 * degradation)) / | |
636 | (RSSI_RANGE * RSSI_RANGE); | |
637 | ||
638 | if (sig_qual > 100) | |
639 | sig_qual = 100; | |
640 | else if (sig_qual < 1) | |
641 | sig_qual = 0; | |
642 | ||
643 | return sig_qual; | |
644 | } | |
645 | ||
646 | #ifdef CONFIG_IWLWIFI_DEBUG | |
647 | ||
648 | /** | |
649 | * iwl_dbg_report_frame - dump frame to syslog during debug sessions | |
650 | * | |
651 | * You may hack this function to show different aspects of received frames, | |
652 | * including selective frame dumps. | |
653 | * group100 parameter selects whether to show 1 out of 100 good frames. | |
654 | * | |
655 | * TODO: This was originally written for 3945, need to audit for | |
656 | * proper operation with 4965. | |
657 | */ | |
658 | static void iwl_dbg_report_frame(struct iwl_priv *priv, | |
659 | struct iwl_rx_packet *pkt, | |
660 | struct ieee80211_hdr *header, int group100) | |
661 | { | |
662 | u32 to_us; | |
663 | u32 print_summary = 0; | |
664 | u32 print_dump = 0; /* set to 1 to dump all frames' contents */ | |
665 | u32 hundred = 0; | |
666 | u32 dataframe = 0; | |
667 | __le16 fc; | |
668 | u16 seq_ctl; | |
669 | u16 channel; | |
670 | u16 phy_flags; | |
671 | int rate_sym; | |
672 | u16 length; | |
673 | u16 status; | |
674 | u16 bcn_tmr; | |
675 | u32 tsf_low; | |
676 | u64 tsf; | |
677 | u8 rssi; | |
678 | u8 agc; | |
679 | u16 sig_avg; | |
680 | u16 noise_diff; | |
681 | struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt); | |
682 | struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt); | |
683 | struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt); | |
684 | u8 *data = IWL_RX_DATA(pkt); | |
685 | ||
686 | if (likely(!(priv->debug_level & IWL_DL_RX))) | |
687 | return; | |
688 | ||
689 | /* MAC header */ | |
690 | fc = header->frame_control; | |
691 | seq_ctl = le16_to_cpu(header->seq_ctrl); | |
692 | ||
693 | /* metadata */ | |
694 | channel = le16_to_cpu(rx_hdr->channel); | |
695 | phy_flags = le16_to_cpu(rx_hdr->phy_flags); | |
696 | rate_sym = rx_hdr->rate; | |
697 | length = le16_to_cpu(rx_hdr->len); | |
698 | ||
699 | /* end-of-frame status and timestamp */ | |
700 | status = le32_to_cpu(rx_end->status); | |
701 | bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp); | |
702 | tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff; | |
703 | tsf = le64_to_cpu(rx_end->timestamp); | |
704 | ||
705 | /* signal statistics */ | |
706 | rssi = rx_stats->rssi; | |
707 | agc = rx_stats->agc; | |
708 | sig_avg = le16_to_cpu(rx_stats->sig_avg); | |
709 | noise_diff = le16_to_cpu(rx_stats->noise_diff); | |
710 | ||
711 | to_us = !compare_ether_addr(header->addr1, priv->mac_addr); | |
712 | ||
713 | /* if data frame is to us and all is good, | |
714 | * (optionally) print summary for only 1 out of every 100 */ | |
715 | if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) == | |
716 | cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) { | |
717 | dataframe = 1; | |
718 | if (!group100) | |
719 | print_summary = 1; /* print each frame */ | |
720 | else if (priv->framecnt_to_us < 100) { | |
721 | priv->framecnt_to_us++; | |
722 | print_summary = 0; | |
723 | } else { | |
724 | priv->framecnt_to_us = 0; | |
725 | print_summary = 1; | |
726 | hundred = 1; | |
727 | } | |
728 | } else { | |
729 | /* print summary for all other frames */ | |
730 | print_summary = 1; | |
731 | } | |
732 | ||
733 | if (print_summary) { | |
734 | char *title; | |
735 | int rate_idx; | |
736 | u32 bitrate; | |
737 | ||
738 | if (hundred) | |
739 | title = "100Frames"; | |
740 | else if (ieee80211_has_retry(fc)) | |
741 | title = "Retry"; | |
742 | else if (ieee80211_is_assoc_resp(fc)) | |
743 | title = "AscRsp"; | |
744 | else if (ieee80211_is_reassoc_resp(fc)) | |
745 | title = "RasRsp"; | |
746 | else if (ieee80211_is_probe_resp(fc)) { | |
747 | title = "PrbRsp"; | |
748 | print_dump = 1; /* dump frame contents */ | |
749 | } else if (ieee80211_is_beacon(fc)) { | |
750 | title = "Beacon"; | |
751 | print_dump = 1; /* dump frame contents */ | |
752 | } else if (ieee80211_is_atim(fc)) | |
753 | title = "ATIM"; | |
754 | else if (ieee80211_is_auth(fc)) | |
755 | title = "Auth"; | |
756 | else if (ieee80211_is_deauth(fc)) | |
757 | title = "DeAuth"; | |
758 | else if (ieee80211_is_disassoc(fc)) | |
759 | title = "DisAssoc"; | |
760 | else | |
761 | title = "Frame"; | |
762 | ||
763 | rate_idx = iwl_hwrate_to_plcp_idx(rate_sym); | |
764 | if (unlikely(rate_idx == -1)) | |
765 | bitrate = 0; | |
766 | else | |
767 | bitrate = iwl_rates[rate_idx].ieee / 2; | |
768 | ||
769 | /* print frame summary. | |
770 | * MAC addresses show just the last byte (for brevity), | |
771 | * but you can hack it to show more, if you'd like to. */ | |
772 | if (dataframe) | |
773 | IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, " | |
774 | "len=%u, rssi=%d, chnl=%d, rate=%u, \n", | |
775 | title, le16_to_cpu(fc), header->addr1[5], | |
776 | length, rssi, channel, bitrate); | |
777 | else { | |
778 | /* src/dst addresses assume managed mode */ | |
779 | IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, " | |
780 | "src=0x%02x, rssi=%u, tim=%lu usec, " | |
781 | "phy=0x%02x, chnl=%d\n", | |
782 | title, le16_to_cpu(fc), header->addr1[5], | |
783 | header->addr3[5], rssi, | |
784 | tsf_low - priv->scan_start_tsf, | |
785 | phy_flags, channel); | |
786 | } | |
787 | } | |
788 | if (print_dump) | |
789 | iwl_print_hex_dump(priv, IWL_DL_RX, data, length); | |
790 | } | |
791 | #else | |
792 | static inline void iwl_dbg_report_frame(struct iwl_priv *priv, | |
793 | struct iwl_rx_packet *pkt, | |
794 | struct ieee80211_hdr *header, | |
795 | int group100) | |
796 | { | |
797 | } | |
798 | #endif | |
799 | ||
1781a07f EG |
800 | static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len) |
801 | { | |
802 | /* 0 - mgmt, 1 - cnt, 2 - data */ | |
803 | int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2; | |
804 | priv->rx_stats[idx].cnt++; | |
805 | priv->rx_stats[idx].bytes += len; | |
806 | } | |
807 | ||
808 | /* | |
809 | * returns non-zero if packet should be dropped | |
810 | */ | |
811 | static int iwl_set_decrypted_flag(struct iwl_priv *priv, | |
812 | struct ieee80211_hdr *hdr, | |
813 | u32 decrypt_res, | |
814 | struct ieee80211_rx_status *stats) | |
815 | { | |
816 | u16 fc = le16_to_cpu(hdr->frame_control); | |
817 | ||
818 | if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) | |
819 | return 0; | |
820 | ||
821 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
822 | return 0; | |
823 | ||
824 | IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res); | |
825 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { | |
826 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
827 | /* The uCode has got a bad phase 1 Key, pushes the packet. | |
828 | * Decryption will be done in SW. */ | |
829 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
830 | RX_RES_STATUS_BAD_KEY_TTAK) | |
831 | break; | |
832 | ||
833 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
834 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
835 | RX_RES_STATUS_BAD_ICV_MIC) { | |
836 | /* bad ICV, the packet is destroyed since the | |
837 | * decryption is inplace, drop it */ | |
838 | IWL_DEBUG_RX("Packet destroyed\n"); | |
839 | return -1; | |
840 | } | |
841 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
842 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
843 | RX_RES_STATUS_DECRYPT_OK) { | |
844 | IWL_DEBUG_RX("hw decrypt successfully!!!\n"); | |
845 | stats->flag |= RX_FLAG_DECRYPTED; | |
846 | } | |
847 | break; | |
848 | ||
849 | default: | |
850 | break; | |
851 | } | |
852 | return 0; | |
853 | } | |
854 | ||
855 | static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in) | |
856 | { | |
857 | u32 decrypt_out = 0; | |
858 | ||
859 | if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) == | |
860 | RX_RES_STATUS_STATION_FOUND) | |
861 | decrypt_out |= (RX_RES_STATUS_STATION_FOUND | | |
862 | RX_RES_STATUS_NO_STATION_INFO_MISMATCH); | |
863 | ||
864 | decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK); | |
865 | ||
866 | /* packet was not encrypted */ | |
867 | if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == | |
868 | RX_RES_STATUS_SEC_TYPE_NONE) | |
869 | return decrypt_out; | |
870 | ||
871 | /* packet was encrypted with unknown alg */ | |
872 | if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == | |
873 | RX_RES_STATUS_SEC_TYPE_ERR) | |
874 | return decrypt_out; | |
875 | ||
876 | /* decryption was not done in HW */ | |
877 | if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) != | |
878 | RX_MPDU_RES_STATUS_DEC_DONE_MSK) | |
879 | return decrypt_out; | |
880 | ||
881 | switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) { | |
882 | ||
883 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
884 | /* alg is CCM: check MIC only */ | |
885 | if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK)) | |
886 | /* Bad MIC */ | |
887 | decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; | |
888 | else | |
889 | decrypt_out |= RX_RES_STATUS_DECRYPT_OK; | |
890 | ||
891 | break; | |
892 | ||
893 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
894 | if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) { | |
895 | /* Bad TTAK */ | |
896 | decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK; | |
897 | break; | |
898 | } | |
899 | /* fall through if TTAK OK */ | |
900 | default: | |
901 | if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK)) | |
902 | decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; | |
903 | else | |
904 | decrypt_out |= RX_RES_STATUS_DECRYPT_OK; | |
905 | break; | |
906 | }; | |
907 | ||
908 | IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", | |
909 | decrypt_in, decrypt_out); | |
910 | ||
911 | return decrypt_out; | |
912 | } | |
913 | ||
4b8817b2 | 914 | static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv, |
1781a07f EG |
915 | int include_phy, |
916 | struct iwl_rx_mem_buffer *rxb, | |
917 | struct ieee80211_rx_status *stats) | |
918 | { | |
919 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
caab8f1a TW |
920 | struct iwl_rx_phy_res *rx_start = (include_phy) ? |
921 | (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) : NULL; | |
1781a07f EG |
922 | struct ieee80211_hdr *hdr; |
923 | u16 len; | |
924 | __le32 *rx_end; | |
925 | unsigned int skblen; | |
926 | u32 ampdu_status; | |
927 | u32 ampdu_status_legacy; | |
928 | ||
929 | if (!include_phy && priv->last_phy_res[0]) | |
caab8f1a | 930 | rx_start = (struct iwl_rx_phy_res *)&priv->last_phy_res[1]; |
1781a07f EG |
931 | |
932 | if (!rx_start) { | |
933 | IWL_ERROR("MPDU frame without a PHY data\n"); | |
934 | return; | |
935 | } | |
936 | if (include_phy) { | |
937 | hdr = (struct ieee80211_hdr *)((u8 *) &rx_start[1] + | |
938 | rx_start->cfg_phy_cnt); | |
939 | ||
940 | len = le16_to_cpu(rx_start->byte_count); | |
941 | ||
caab8f1a TW |
942 | rx_end = (__le32 *)((u8 *) &pkt->u.raw[0] + |
943 | sizeof(struct iwl_rx_phy_res) + | |
1781a07f EG |
944 | rx_start->cfg_phy_cnt + len); |
945 | ||
946 | } else { | |
947 | struct iwl4965_rx_mpdu_res_start *amsdu = | |
948 | (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw; | |
949 | ||
950 | hdr = (struct ieee80211_hdr *)(pkt->u.raw + | |
951 | sizeof(struct iwl4965_rx_mpdu_res_start)); | |
952 | len = le16_to_cpu(amsdu->byte_count); | |
953 | rx_start->byte_count = amsdu->byte_count; | |
954 | rx_end = (__le32 *) (((u8 *) hdr) + len); | |
955 | } | |
1781a07f EG |
956 | |
957 | ampdu_status = le32_to_cpu(*rx_end); | |
958 | skblen = ((u8 *) rx_end - (u8 *) &pkt->u.raw[0]) + sizeof(u32); | |
959 | ||
960 | if (!include_phy) { | |
961 | /* New status scheme, need to translate */ | |
962 | ampdu_status_legacy = ampdu_status; | |
963 | ampdu_status = iwl_translate_rx_status(priv, ampdu_status); | |
964 | } | |
965 | ||
966 | /* start from MAC */ | |
967 | skb_reserve(rxb->skb, (void *)hdr - (void *)pkt); | |
968 | skb_put(rxb->skb, len); /* end where data ends */ | |
969 | ||
970 | /* We only process data packets if the interface is open */ | |
971 | if (unlikely(!priv->is_open)) { | |
972 | IWL_DEBUG_DROP_LIMIT | |
973 | ("Dropping packet while interface is not open.\n"); | |
974 | return; | |
975 | } | |
976 | ||
1781a07f EG |
977 | hdr = (struct ieee80211_hdr *)rxb->skb->data; |
978 | ||
979 | /* in case of HW accelerated crypto and bad decryption, drop */ | |
980 | if (!priv->hw_params.sw_crypto && | |
981 | iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats)) | |
982 | return; | |
983 | ||
1781a07f EG |
984 | iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len); |
985 | ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats); | |
986 | priv->alloc_rxb_skb--; | |
987 | rxb->skb = NULL; | |
988 | } | |
989 | ||
990 | /* Calc max signal level (dBm) among 3 possible receivers */ | |
caab8f1a TW |
991 | static inline int iwl_calc_rssi(struct iwl_priv *priv, |
992 | struct iwl_rx_phy_res *rx_resp) | |
1781a07f | 993 | { |
caab8f1a | 994 | return priv->cfg->ops->utils->calc_rssi(priv, rx_resp); |
1781a07f EG |
995 | } |
996 | ||
caab8f1a | 997 | |
1781a07f EG |
998 | static void iwl_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id) |
999 | { | |
1000 | unsigned long flags; | |
1001 | ||
1002 | spin_lock_irqsave(&priv->sta_lock, flags); | |
1003 | priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK; | |
1004 | priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK; | |
1005 | priv->stations[sta_id].sta.sta.modify_mask = 0; | |
1006 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
1007 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1008 | ||
1009 | iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC); | |
1010 | } | |
1011 | ||
1012 | static void iwl_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr) | |
1013 | { | |
1014 | /* FIXME: need locking over ps_status ??? */ | |
1015 | u8 sta_id = iwl_find_station(priv, addr); | |
1016 | ||
1017 | if (sta_id != IWL_INVALID_STATION) { | |
1018 | u8 sta_awake = priv->stations[sta_id]. | |
1019 | ps_status == STA_PS_STATUS_WAKE; | |
1020 | ||
1021 | if (sta_awake && ps_bit) | |
1022 | priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP; | |
1023 | else if (!sta_awake && !ps_bit) { | |
1024 | iwl_sta_modify_ps_wake(priv, sta_id); | |
1025 | priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE; | |
1026 | } | |
1027 | } | |
1028 | } | |
1029 | ||
4b8817b2 | 1030 | /* This is necessary only for a number of statistics, see the caller. */ |
1781a07f EG |
1031 | static int iwl_is_network_packet(struct iwl_priv *priv, |
1032 | struct ieee80211_hdr *header) | |
1033 | { | |
1034 | /* Filter incoming packets to determine if they are targeted toward | |
1035 | * this network, discarding packets coming from ourselves */ | |
1036 | switch (priv->iw_mode) { | |
05c914fe | 1037 | case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */ |
4b8817b2 EG |
1038 | /* packets to our IBSS update information */ |
1039 | return !compare_ether_addr(header->addr3, priv->bssid); | |
05c914fe | 1040 | case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */ |
4b8817b2 EG |
1041 | /* packets to our IBSS update information */ |
1042 | return !compare_ether_addr(header->addr2, priv->bssid); | |
1781a07f | 1043 | default: |
4b8817b2 | 1044 | return 1; |
1781a07f | 1045 | } |
1781a07f EG |
1046 | } |
1047 | ||
1048 | /* Called for REPLY_RX (legacy ABG frames), or | |
1049 | * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */ | |
1050 | void iwl_rx_reply_rx(struct iwl_priv *priv, | |
1051 | struct iwl_rx_mem_buffer *rxb) | |
1052 | { | |
1053 | struct ieee80211_hdr *header; | |
1054 | struct ieee80211_rx_status rx_status; | |
1055 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1056 | /* Use phy data (Rx signal strength, etc.) contained within | |
1057 | * this rx packet for legacy frames, | |
1058 | * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */ | |
1059 | int include_phy = (pkt->hdr.cmd == REPLY_RX); | |
caab8f1a TW |
1060 | struct iwl_rx_phy_res *rx_start = (include_phy) ? |
1061 | (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) : | |
1062 | (struct iwl_rx_phy_res *)&priv->last_phy_res[1]; | |
1781a07f EG |
1063 | __le32 *rx_end; |
1064 | unsigned int len = 0; | |
1065 | u16 fc; | |
1066 | u8 network_packet; | |
1067 | ||
1068 | rx_status.mactime = le64_to_cpu(rx_start->timestamp); | |
1069 | rx_status.freq = | |
1070 | ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel)); | |
1071 | rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? | |
1072 | IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; | |
1073 | rx_status.rate_idx = | |
1074 | iwl_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags)); | |
1075 | if (rx_status.band == IEEE80211_BAND_5GHZ) | |
1076 | rx_status.rate_idx -= IWL_FIRST_OFDM_RATE; | |
1077 | ||
1781a07f | 1078 | rx_status.flag = 0; |
b94d8eea AK |
1079 | |
1080 | /* TSF isn't reliable. In order to allow smooth user experience, | |
1081 | * this W/A doesn't propagate it to the mac80211 */ | |
1082 | /*rx_status.flag |= RX_FLAG_TSFT;*/ | |
1781a07f EG |
1083 | |
1084 | if ((unlikely(rx_start->cfg_phy_cnt > 20))) { | |
1085 | IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n", | |
1086 | rx_start->cfg_phy_cnt); | |
1087 | return; | |
1088 | } | |
1089 | ||
1090 | if (!include_phy) { | |
1091 | if (priv->last_phy_res[0]) | |
caab8f1a | 1092 | rx_start = (struct iwl_rx_phy_res *) |
1781a07f EG |
1093 | &priv->last_phy_res[1]; |
1094 | else | |
1095 | rx_start = NULL; | |
1096 | } | |
1097 | ||
1098 | if (!rx_start) { | |
1099 | IWL_ERROR("MPDU frame without a PHY data\n"); | |
1100 | return; | |
1101 | } | |
1102 | ||
1103 | if (include_phy) { | |
1104 | header = (struct ieee80211_hdr *)((u8 *) &rx_start[1] | |
1105 | + rx_start->cfg_phy_cnt); | |
1106 | ||
1107 | len = le16_to_cpu(rx_start->byte_count); | |
1108 | rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt + | |
caab8f1a | 1109 | sizeof(struct iwl_rx_phy_res) + len); |
1781a07f EG |
1110 | } else { |
1111 | struct iwl4965_rx_mpdu_res_start *amsdu = | |
1112 | (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw; | |
1113 | ||
1114 | header = (void *)(pkt->u.raw + | |
1115 | sizeof(struct iwl4965_rx_mpdu_res_start)); | |
1116 | len = le16_to_cpu(amsdu->byte_count); | |
1117 | rx_end = (__le32 *) (pkt->u.raw + | |
1118 | sizeof(struct iwl4965_rx_mpdu_res_start) + len); | |
1119 | } | |
1120 | ||
1121 | if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) || | |
1122 | !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) { | |
1123 | IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", | |
1124 | le32_to_cpu(*rx_end)); | |
1125 | return; | |
1126 | } | |
1127 | ||
1128 | priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp); | |
1129 | ||
1130 | /* Find max signal strength (dBm) among 3 antenna/receiver chains */ | |
1131 | rx_status.signal = iwl_calc_rssi(priv, rx_start); | |
1132 | ||
1133 | /* Meaningful noise values are available only from beacon statistics, | |
1134 | * which are gathered only when associated, and indicate noise | |
1135 | * only for the associated network channel ... | |
1136 | * Ignore these noise values while scanning (other channels) */ | |
1137 | if (iwl_is_associated(priv) && | |
1138 | !test_bit(STATUS_SCANNING, &priv->status)) { | |
1139 | rx_status.noise = priv->last_rx_noise; | |
1140 | rx_status.qual = iwl_calc_sig_qual(rx_status.signal, | |
1141 | rx_status.noise); | |
1142 | } else { | |
1143 | rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
1144 | rx_status.qual = iwl_calc_sig_qual(rx_status.signal, 0); | |
1145 | } | |
1146 | ||
1147 | /* Reset beacon noise level if not associated. */ | |
1148 | if (!iwl_is_associated(priv)) | |
1149 | priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
1150 | ||
1151 | /* Set "1" to report good data frames in groups of 100 */ | |
1152 | /* FIXME: need to optimze the call: */ | |
1153 | iwl_dbg_report_frame(priv, pkt, header, 1); | |
1154 | ||
1155 | IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n", | |
1156 | rx_status.signal, rx_status.noise, rx_status.signal, | |
1157 | (unsigned long long)rx_status.mactime); | |
1158 | ||
6f0a2c4d BR |
1159 | /* |
1160 | * "antenna number" | |
1161 | * | |
1162 | * It seems that the antenna field in the phy flags value | |
1163 | * is actually a bitfield. This is undefined by radiotap, | |
1164 | * it wants an actual antenna number but I always get "7" | |
1165 | * for most legacy frames I receive indicating that the | |
1166 | * same frame was received on all three RX chains. | |
1167 | * | |
1168 | * I think this field should be removed in favour of a | |
1169 | * new 802.11n radiotap field "RX chains" that is defined | |
1170 | * as a bitmask. | |
1171 | */ | |
1172 | rx_status.antenna = le16_to_cpu(rx_start->phy_flags & | |
1173 | RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4; | |
1174 | ||
1175 | /* set the preamble flag if appropriate */ | |
1176 | if (rx_start->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) | |
1177 | rx_status.flag |= RX_FLAG_SHORTPRE; | |
1178 | ||
4b8817b2 | 1179 | /* Take shortcut when only in monitor mode */ |
05c914fe | 1180 | if (priv->iw_mode == NL80211_IFTYPE_MONITOR) { |
4b8817b2 | 1181 | iwl_pass_packet_to_mac80211(priv, include_phy, |
1781a07f EG |
1182 | rxb, &rx_status); |
1183 | return; | |
1184 | } | |
1185 | ||
1186 | network_packet = iwl_is_network_packet(priv, header); | |
1187 | if (network_packet) { | |
1188 | priv->last_rx_rssi = rx_status.signal; | |
1189 | priv->last_beacon_time = priv->ucode_beacon_time; | |
1190 | priv->last_tsf = le64_to_cpu(rx_start->timestamp); | |
1191 | } | |
1192 | ||
1193 | fc = le16_to_cpu(header->frame_control); | |
1194 | switch (fc & IEEE80211_FCTL_FTYPE) { | |
1195 | case IEEE80211_FTYPE_MGMT: | |
4b8817b2 | 1196 | case IEEE80211_FTYPE_DATA: |
05c914fe | 1197 | if (priv->iw_mode == NL80211_IFTYPE_AP) |
1781a07f EG |
1198 | iwl_update_ps_mode(priv, fc & IEEE80211_FCTL_PM, |
1199 | header->addr2); | |
4b8817b2 | 1200 | /* fall through */ |
1781a07f | 1201 | default: |
4b8817b2 EG |
1202 | iwl_pass_packet_to_mac80211(priv, include_phy, rxb, |
1203 | &rx_status); | |
1781a07f EG |
1204 | break; |
1205 | ||
1206 | } | |
1207 | } | |
1208 | EXPORT_SYMBOL(iwl_rx_reply_rx); | |
1209 | ||
1210 | /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD). | |
1211 | * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */ | |
1212 | void iwl_rx_reply_rx_phy(struct iwl_priv *priv, | |
1213 | struct iwl_rx_mem_buffer *rxb) | |
1214 | { | |
1215 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1216 | priv->last_phy_res[0] = 1; | |
1217 | memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]), | |
caab8f1a | 1218 | sizeof(struct iwl_rx_phy_res)); |
1781a07f EG |
1219 | } |
1220 | EXPORT_SYMBOL(iwl_rx_reply_rx_phy); |