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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
fb4961db | 3 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
522376d2 | 37 | #include "iwl-agn-hw.h" |
ed277c93 | 38 | #include "iwl-op-mode.h" |
c17d0681 | 39 | #include "iwl-trans-pcie-int.h" |
1053d35f | 40 | |
522376d2 EG |
41 | #define IWL_TX_CRC_SIZE 4 |
42 | #define IWL_TX_DELIMITER_SIZE 4 | |
43 | ||
48d42c42 EG |
44 | /** |
45 | * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
46 | */ | |
6d8f6eeb | 47 | void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
48 | struct iwl_tx_queue *txq, |
49 | u16 byte_cnt) | |
50 | { | |
105183b1 | 51 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
105183b1 EG |
52 | struct iwl_trans_pcie *trans_pcie = |
53 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
48d42c42 EG |
54 | int write_ptr = txq->q.write_ptr; |
55 | int txq_id = txq->q.id; | |
56 | u8 sec_ctl = 0; | |
57 | u8 sta_id = 0; | |
58 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
59 | __le16 bc_ent; | |
132f98c2 EG |
60 | struct iwl_tx_cmd *tx_cmd = |
61 | (struct iwl_tx_cmd *) txq->cmd[txq->q.write_ptr]->payload; | |
48d42c42 | 62 | |
105183b1 EG |
63 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
64 | ||
48d42c42 EG |
65 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
66 | ||
132f98c2 EG |
67 | sta_id = tx_cmd->sta_id; |
68 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
69 | |
70 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
71 | case TX_CMD_SEC_CCM: | |
72 | len += CCMP_MIC_LEN; | |
73 | break; | |
74 | case TX_CMD_SEC_TKIP: | |
75 | len += TKIP_ICV_LEN; | |
76 | break; | |
77 | case TX_CMD_SEC_WEP: | |
78 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
79 | break; | |
80 | } | |
81 | ||
82 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); | |
83 | ||
84 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
85 | ||
86 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
87 | scd_bc_tbl[txq_id]. | |
88 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
89 | } | |
90 | ||
fd4abac5 TW |
91 | /** |
92 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
93 | */ | |
fd656935 | 94 | void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq) |
fd4abac5 TW |
95 | { |
96 | u32 reg = 0; | |
fd4abac5 TW |
97 | int txq_id = txq->q.id; |
98 | ||
99 | if (txq->need_update == 0) | |
7bfedc59 | 100 | return; |
fd4abac5 | 101 | |
0dde86b2 | 102 | if (cfg(trans)->base_params->shadow_reg_enable) { |
f81c1f48 | 103 | /* shadow register enabled */ |
1042db2a | 104 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
105 | txq->q.write_ptr | (txq_id << 8)); |
106 | } else { | |
107 | /* if we're trying to save power */ | |
fd656935 | 108 | if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) { |
f81c1f48 WYG |
109 | /* wake up nic if it's powered down ... |
110 | * uCode will wake up, and interrupt us again, so next | |
111 | * time we'll skip this part. */ | |
1042db2a | 112 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
fd4abac5 | 113 | |
f81c1f48 | 114 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
fd656935 | 115 | IWL_DEBUG_INFO(trans, |
f81c1f48 WYG |
116 | "Tx queue %d requesting wakeup," |
117 | " GP1 = 0x%x\n", txq_id, reg); | |
1042db2a | 118 | iwl_set_bit(trans, CSR_GP_CNTRL, |
f81c1f48 WYG |
119 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
120 | return; | |
121 | } | |
fd4abac5 | 122 | |
1042db2a | 123 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
fd4abac5 | 124 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 125 | |
f81c1f48 WYG |
126 | /* |
127 | * else not in power-save mode, | |
128 | * uCode will never sleep when we're | |
129 | * trying to tx (during RFKILL, we're not trying to tx). | |
130 | */ | |
131 | } else | |
1042db2a | 132 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
133 | txq->q.write_ptr | (txq_id << 8)); |
134 | } | |
fd4abac5 | 135 | txq->need_update = 0; |
fd4abac5 | 136 | } |
fd4abac5 | 137 | |
214d14d4 JB |
138 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
139 | { | |
140 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
141 | ||
142 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
143 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
144 | addr |= | |
145 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
146 | ||
147 | return addr; | |
148 | } | |
149 | ||
150 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
151 | { | |
152 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
153 | ||
154 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
155 | } | |
156 | ||
157 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
158 | dma_addr_t addr, u16 len) | |
159 | { | |
160 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
161 | u16 hi_n_len = len << 4; | |
162 | ||
163 | put_unaligned_le32(addr, &tb->lo); | |
164 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
165 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
166 | ||
167 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
168 | ||
169 | tfd->num_tbs = idx + 1; | |
170 | } | |
171 | ||
172 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
173 | { | |
174 | return tfd->num_tbs & 0x1f; | |
175 | } | |
176 | ||
6d8f6eeb | 177 | static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta, |
253a634c | 178 | struct iwl_tfd *tfd, enum dma_data_direction dma_dir) |
214d14d4 | 179 | { |
214d14d4 JB |
180 | int i; |
181 | int num_tbs; | |
182 | ||
214d14d4 JB |
183 | /* Sanity check on number of chunks */ |
184 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
185 | ||
186 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 187 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
188 | /* @todo issue fatal error, it is quite serious situation */ |
189 | return; | |
190 | } | |
191 | ||
192 | /* Unmap tx_cmd */ | |
193 | if (num_tbs) | |
1042db2a | 194 | dma_unmap_single(trans->dev, |
4ce7cc2b JB |
195 | dma_unmap_addr(meta, mapping), |
196 | dma_unmap_len(meta, len), | |
795414db | 197 | DMA_BIDIRECTIONAL); |
214d14d4 JB |
198 | |
199 | /* Unmap chunks, if any. */ | |
200 | for (i = 1; i < num_tbs; i++) | |
1042db2a | 201 | dma_unmap_single(trans->dev, iwl_tfd_tb_get_addr(tfd, i), |
e815407d | 202 | iwl_tfd_tb_get_len(tfd, i), dma_dir); |
4ce7cc2b JB |
203 | } |
204 | ||
205 | /** | |
206 | * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 207 | * @trans - transport private data |
4ce7cc2b | 208 | * @txq - tx queue |
1359ca4f | 209 | * @index - the index of the TFD to be freed |
39644e9a | 210 | *@dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
211 | * |
212 | * Does NOT advance any TFD circular buffer read/write indexes | |
213 | * Does NOT free the TFD itself (which is within circular buffer) | |
214 | */ | |
6d8f6eeb | 215 | void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
39644e9a | 216 | int index, enum dma_data_direction dma_dir) |
4ce7cc2b JB |
217 | { |
218 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 219 | |
015c15e1 JB |
220 | lockdep_assert_held(&txq->lock); |
221 | ||
39644e9a | 222 | iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index], dma_dir); |
214d14d4 JB |
223 | |
224 | /* free SKB */ | |
2c452297 | 225 | if (txq->skbs) { |
214d14d4 JB |
226 | struct sk_buff *skb; |
227 | ||
2c452297 | 228 | skb = txq->skbs[index]; |
214d14d4 | 229 | |
909e9b23 EG |
230 | /* Can be called from irqs-disabled context |
231 | * If skb is not NULL, it means that the whole queue is being | |
232 | * freed and that the queue is not empty - free the skb | |
233 | */ | |
214d14d4 | 234 | if (skb) { |
ed277c93 | 235 | iwl_op_mode_free_skb(trans->op_mode, skb); |
2c452297 | 236 | txq->skbs[index] = NULL; |
214d14d4 JB |
237 | } |
238 | } | |
239 | } | |
240 | ||
6d8f6eeb | 241 | int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans, |
214d14d4 JB |
242 | struct iwl_tx_queue *txq, |
243 | dma_addr_t addr, u16 len, | |
4c42db0f | 244 | u8 reset) |
214d14d4 JB |
245 | { |
246 | struct iwl_queue *q; | |
247 | struct iwl_tfd *tfd, *tfd_tmp; | |
248 | u32 num_tbs; | |
249 | ||
250 | q = &txq->q; | |
4ce7cc2b | 251 | tfd_tmp = txq->tfds; |
214d14d4 JB |
252 | tfd = &tfd_tmp[q->write_ptr]; |
253 | ||
254 | if (reset) | |
255 | memset(tfd, 0, sizeof(*tfd)); | |
256 | ||
257 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
258 | ||
259 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
260 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 261 | IWL_ERR(trans, "Error can not send more than %d chunks\n", |
214d14d4 JB |
262 | IWL_NUM_OF_TBS); |
263 | return -EINVAL; | |
264 | } | |
265 | ||
266 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
267 | return -EINVAL; | |
268 | ||
269 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
6d8f6eeb | 270 | IWL_ERR(trans, "Unaligned address = %llx\n", |
214d14d4 JB |
271 | (unsigned long long)addr); |
272 | ||
273 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
fd4abac5 TW |
278 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
279 | * DMA services | |
280 | * | |
281 | * Theory of operation | |
282 | * | |
283 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
284 | * of buffer descriptors, each of which points to one or more data buffers for | |
285 | * the device to read from or fill. Driver and device exchange status of each | |
286 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
287 | * entries in each circular buffer, to protect against confusing empty and full | |
288 | * queue states. | |
289 | * | |
290 | * The device reads or writes the data in the queues via the device's several | |
291 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
292 | * | |
293 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
294 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
295 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
296 | * Tx queue resumed. | |
297 | * | |
fd4abac5 TW |
298 | ***************************************************/ |
299 | ||
300 | int iwl_queue_space(const struct iwl_queue *q) | |
301 | { | |
302 | int s = q->read_ptr - q->write_ptr; | |
303 | ||
304 | if (q->read_ptr > q->write_ptr) | |
305 | s -= q->n_bd; | |
306 | ||
307 | if (s <= 0) | |
308 | s += q->n_window; | |
309 | /* keep some reserve to not confuse empty and full situations */ | |
310 | s -= 2; | |
311 | if (s < 0) | |
312 | s = 0; | |
313 | return s; | |
314 | } | |
fd4abac5 | 315 | |
1053d35f RR |
316 | /** |
317 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
318 | */ | |
6d8f6eeb | 319 | int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) |
1053d35f RR |
320 | { |
321 | q->n_bd = count; | |
322 | q->n_window = slots_num; | |
323 | q->id = id; | |
324 | ||
325 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
326 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
327 | if (WARN_ON(!is_power_of_2(count))) |
328 | return -EINVAL; | |
1053d35f RR |
329 | |
330 | /* slots_num must be power-of-two size, otherwise | |
331 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
332 | if (WARN_ON(!is_power_of_2(slots_num))) |
333 | return -EINVAL; | |
1053d35f RR |
334 | |
335 | q->low_mark = q->n_window / 4; | |
336 | if (q->low_mark < 4) | |
337 | q->low_mark = 4; | |
338 | ||
339 | q->high_mark = q->n_window / 8; | |
340 | if (q->high_mark < 2) | |
341 | q->high_mark = 2; | |
342 | ||
343 | q->write_ptr = q->read_ptr = 0; | |
344 | ||
345 | return 0; | |
346 | } | |
347 | ||
6d8f6eeb | 348 | static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
48d42c42 EG |
349 | struct iwl_tx_queue *txq) |
350 | { | |
105183b1 EG |
351 | struct iwl_trans_pcie *trans_pcie = |
352 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
6d8f6eeb | 353 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
48d42c42 EG |
354 | int txq_id = txq->q.id; |
355 | int read_ptr = txq->q.read_ptr; | |
356 | u8 sta_id = 0; | |
357 | __le16 bc_ent; | |
132f98c2 EG |
358 | struct iwl_tx_cmd *tx_cmd = |
359 | (struct iwl_tx_cmd *) txq->cmd[txq->q.read_ptr]->payload; | |
48d42c42 EG |
360 | |
361 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
362 | ||
c6f600fc | 363 | if (txq_id != trans_pcie->cmd_queue) |
132f98c2 | 364 | sta_id = tx_cmd->sta_id; |
48d42c42 EG |
365 | |
366 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
367 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
368 | ||
369 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
370 | scd_bc_tbl[txq_id]. | |
371 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
372 | } | |
373 | ||
6d8f6eeb | 374 | static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid, |
48d42c42 EG |
375 | u16 txq_id) |
376 | { | |
377 | u32 tbl_dw_addr; | |
378 | u32 tbl_dw; | |
379 | u16 scd_q2ratid; | |
380 | ||
105183b1 EG |
381 | struct iwl_trans_pcie *trans_pcie = |
382 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
383 | ||
48d42c42 EG |
384 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; |
385 | ||
105183b1 | 386 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
387 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
388 | ||
1042db2a | 389 | tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr); |
48d42c42 EG |
390 | |
391 | if (txq_id & 0x1) | |
392 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
393 | else | |
394 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
395 | ||
1042db2a | 396 | iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
397 | |
398 | return 0; | |
399 | } | |
400 | ||
6d8f6eeb | 401 | static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id) |
48d42c42 EG |
402 | { |
403 | /* Simply stop the queue, but don't change any configuration; | |
404 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1042db2a | 405 | iwl_write_prph(trans, |
48d42c42 EG |
406 | SCD_QUEUE_STATUS_BITS(txq_id), |
407 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
408 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
409 | } | |
410 | ||
6d8f6eeb | 411 | void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, |
48d42c42 EG |
412 | int txq_id, u32 index) |
413 | { | |
0ca24daf | 414 | IWL_DEBUG_TX_QUEUES(trans, "Q %d WrPtr: %d\n", txq_id, index & 0xff); |
1042db2a | 415 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
48d42c42 | 416 | (index & 0xff) | (txq_id << 8)); |
1042db2a | 417 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), index); |
48d42c42 EG |
418 | } |
419 | ||
c91bd124 | 420 | void iwl_trans_tx_queue_set_status(struct iwl_trans *trans, |
9eae88fa JB |
421 | struct iwl_tx_queue *txq, |
422 | int tx_fifo_id, bool active) | |
48d42c42 EG |
423 | { |
424 | int txq_id = txq->q.id; | |
48d42c42 | 425 | |
1042db2a | 426 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), |
48d42c42 EG |
427 | (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | |
428 | (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | | |
429 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
430 | SCD_QUEUE_STTS_REG_MSK); | |
431 | ||
1dcedc8e | 432 | if (active) |
9eae88fa JB |
433 | IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d\n", |
434 | txq_id, tx_fifo_id); | |
1dcedc8e | 435 | else |
9eae88fa | 436 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
76bc10fc EG |
437 | } |
438 | ||
9eae88fa JB |
439 | void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans, int txq_id, int fifo, |
440 | int sta_id, int tid, int frame_limit, u16 ssn) | |
48d42c42 | 441 | { |
9eae88fa | 442 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 | 443 | unsigned long flags; |
9eae88fa | 444 | u16 ra_tid = BUILD_RAxTID(sta_id, tid); |
48d42c42 | 445 | |
9eae88fa JB |
446 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
447 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 448 | |
7b11488f | 449 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
48d42c42 EG |
450 | |
451 | /* Stop this Tx queue before configuring it */ | |
6d8f6eeb | 452 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
48d42c42 EG |
453 | |
454 | /* Map receiver-address / traffic-ID to this queue */ | |
6d8f6eeb | 455 | iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id); |
48d42c42 EG |
456 | |
457 | /* Set this queue as a chain-building queue */ | |
9eae88fa | 458 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); |
48d42c42 EG |
459 | |
460 | /* enable aggregations for the queue */ | |
9eae88fa | 461 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); |
48d42c42 EG |
462 | |
463 | /* Place first TFD at index corresponding to start sequence number. | |
464 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
465 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
466 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
467 | iwl_trans_set_wr_ptrs(trans, txq_id, ssn); | |
48d42c42 EG |
468 | |
469 | /* Set up Tx window size and frame limit for this queue */ | |
1042db2a | 470 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + |
9eae88fa JB |
471 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
472 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
473 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
474 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
475 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
48d42c42 | 476 | |
1042db2a | 477 | iwl_set_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id)); |
48d42c42 EG |
478 | |
479 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
8ad71bef | 480 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], |
9eae88fa | 481 | fifo, true); |
a0eaad71 | 482 | |
7b11488f | 483 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
48d42c42 EG |
484 | } |
485 | ||
9eae88fa | 486 | void iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int txq_id) |
288712a6 | 487 | { |
8ad71bef | 488 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
288712a6 | 489 | |
9eae88fa JB |
490 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
491 | WARN_ONCE(1, "queue %d not used", txq_id); | |
492 | return; | |
48d42c42 EG |
493 | } |
494 | ||
bc237730 | 495 | iwlagn_tx_queue_stop_scheduler(trans, txq_id); |
7f01d567 | 496 | |
9eae88fa | 497 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); |
48d42c42 | 498 | |
bc237730 EG |
499 | trans_pcie->txq[txq_id].q.read_ptr = 0; |
500 | trans_pcie->txq[txq_id].q.write_ptr = 0; | |
bc237730 | 501 | iwl_trans_set_wr_ptrs(trans, txq_id, 0); |
48d42c42 | 502 | |
9eae88fa JB |
503 | iwl_clear_bits_prph(trans, SCD_INTERRUPT_MASK, BIT(txq_id)); |
504 | ||
505 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], | |
506 | 0, false); | |
48d42c42 EG |
507 | } |
508 | ||
fd4abac5 TW |
509 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
510 | ||
511 | /** | |
512 | * iwl_enqueue_hcmd - enqueue a uCode command | |
513 | * @priv: device private data point | |
514 | * @cmd: a point to the ucode command structure | |
515 | * | |
516 | * The function returns < 0 values to indicate the operation is | |
517 | * failed. On success, it turns the index (> 0) of command in the | |
518 | * command queue. | |
519 | */ | |
6d8f6eeb | 520 | static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
fd4abac5 | 521 | { |
8ad71bef | 522 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c6f600fc | 523 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 524 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
525 | struct iwl_device_cmd *out_cmd; |
526 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 527 | dma_addr_t phys_addr; |
f3674227 | 528 | u32 idx; |
4ce7cc2b | 529 | u16 copy_size, cmd_size; |
4ce7cc2b JB |
530 | bool had_nocopy = false; |
531 | int i; | |
532 | u8 *cmd_dest; | |
533 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
534 | const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {}; | |
535 | int trace_lens[IWL_MAX_CMD_TFDS + 1] = {}; | |
536 | int trace_idx; | |
537 | #endif | |
fd4abac5 | 538 | |
4ce7cc2b JB |
539 | copy_size = sizeof(out_cmd->hdr); |
540 | cmd_size = sizeof(out_cmd->hdr); | |
541 | ||
542 | /* need one for the header if the first is NOCOPY */ | |
543 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1); | |
544 | ||
545 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
546 | if (!cmd->len[i]) | |
547 | continue; | |
548 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { | |
549 | had_nocopy = true; | |
550 | } else { | |
551 | /* NOCOPY must not be followed by normal! */ | |
552 | if (WARN_ON(had_nocopy)) | |
553 | return -EINVAL; | |
554 | copy_size += cmd->len[i]; | |
555 | } | |
556 | cmd_size += cmd->len[i]; | |
557 | } | |
fd4abac5 | 558 | |
3e41ace5 JB |
559 | /* |
560 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
561 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
562 | * allocated into separate TFDs, then we will need to | |
563 | * increase the size of the buffers. | |
3e41ace5 | 564 | */ |
4ce7cc2b | 565 | if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE)) |
3e41ace5 | 566 | return -EINVAL; |
fd4abac5 | 567 | |
015c15e1 | 568 | spin_lock_bh(&txq->lock); |
3598e177 | 569 | |
c2acea8e | 570 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 571 | spin_unlock_bh(&txq->lock); |
3598e177 | 572 | |
6d8f6eeb | 573 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 574 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
fd4abac5 TW |
575 | return -ENOSPC; |
576 | } | |
577 | ||
4ce7cc2b | 578 | idx = get_cmd_index(q, q->write_ptr); |
da99c4b6 | 579 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
580 | out_meta = &txq->meta[idx]; |
581 | ||
8ce73f3a | 582 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
583 | if (cmd->flags & CMD_WANT_SKB) |
584 | out_meta->source = cmd; | |
fd4abac5 | 585 | |
4ce7cc2b | 586 | /* set up the header */ |
fd4abac5 | 587 | |
4ce7cc2b | 588 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 589 | out_cmd->hdr.flags = 0; |
cefeaa5f | 590 | out_cmd->hdr.sequence = |
c6f600fc | 591 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | |
cefeaa5f | 592 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
593 | |
594 | /* and copy the data that needs to be copied */ | |
595 | ||
132f98c2 | 596 | cmd_dest = out_cmd->payload; |
4ce7cc2b JB |
597 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { |
598 | if (!cmd->len[i]) | |
599 | continue; | |
600 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) | |
601 | break; | |
602 | memcpy(cmd_dest, cmd->data[i], cmd->len[i]); | |
603 | cmd_dest += cmd->len[i]; | |
ded2ae7c | 604 | } |
4ce7cc2b | 605 | |
6d8f6eeb | 606 | IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, " |
4ce7cc2b JB |
607 | "%d bytes at %d[%d]:%d\n", |
608 | get_cmd_string(out_cmd->hdr.cmd), | |
609 | out_cmd->hdr.cmd, | |
610 | le16_to_cpu(out_cmd->hdr.sequence), cmd_size, | |
c6f600fc | 611 | q->write_ptr, idx, trans_pcie->cmd_queue); |
4ce7cc2b | 612 | |
1042db2a | 613 | phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size, |
795414db | 614 | DMA_BIDIRECTIONAL); |
1042db2a | 615 | if (unlikely(dma_mapping_error(trans->dev, phys_addr))) { |
2c46f72e JB |
616 | idx = -ENOMEM; |
617 | goto out; | |
618 | } | |
619 | ||
2e724443 | 620 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
4ce7cc2b JB |
621 | dma_unmap_len_set(out_meta, len, copy_size); |
622 | ||
6d8f6eeb EG |
623 | iwlagn_txq_attach_buf_to_tfd(trans, txq, |
624 | phys_addr, copy_size, 1); | |
4ce7cc2b JB |
625 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING |
626 | trace_bufs[0] = &out_cmd->hdr; | |
627 | trace_lens[0] = copy_size; | |
628 | trace_idx = 1; | |
629 | #endif | |
630 | ||
631 | for (i = 0; i < IWL_MAX_CMD_TFDS; i++) { | |
632 | if (!cmd->len[i]) | |
633 | continue; | |
634 | if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)) | |
635 | continue; | |
1042db2a | 636 | phys_addr = dma_map_single(trans->dev, |
6d8f6eeb | 637 | (void *)cmd->data[i], |
3be3fdb5 | 638 | cmd->len[i], DMA_BIDIRECTIONAL); |
1042db2a | 639 | if (dma_mapping_error(trans->dev, phys_addr)) { |
6d8f6eeb | 640 | iwlagn_unmap_tfd(trans, out_meta, |
e815407d | 641 | &txq->tfds[q->write_ptr], |
3be3fdb5 | 642 | DMA_BIDIRECTIONAL); |
4ce7cc2b JB |
643 | idx = -ENOMEM; |
644 | goto out; | |
645 | } | |
646 | ||
6d8f6eeb | 647 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
4ce7cc2b JB |
648 | cmd->len[i], 0); |
649 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
650 | trace_bufs[trace_idx] = cmd->data[i]; | |
651 | trace_lens[trace_idx] = cmd->len[i]; | |
652 | trace_idx++; | |
653 | #endif | |
654 | } | |
df833b1d | 655 | |
afaf6b57 | 656 | out_meta->flags = cmd->flags; |
2c46f72e JB |
657 | |
658 | txq->need_update = 1; | |
659 | ||
4ce7cc2b JB |
660 | /* check that tracing gets all possible blocks */ |
661 | BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3); | |
662 | #ifdef CONFIG_IWLWIFI_DEVICE_TRACING | |
6c1011e1 | 663 | trace_iwlwifi_dev_hcmd(trans->dev, cmd->flags, |
4ce7cc2b JB |
664 | trace_bufs[0], trace_lens[0], |
665 | trace_bufs[1], trace_lens[1], | |
666 | trace_bufs[2], trace_lens[2]); | |
667 | #endif | |
df833b1d | 668 | |
fd4abac5 TW |
669 | /* Increment and update queue's write index */ |
670 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
fd656935 | 671 | iwl_txq_update_write_ptr(trans, txq); |
fd4abac5 | 672 | |
2c46f72e | 673 | out: |
015c15e1 | 674 | spin_unlock_bh(&txq->lock); |
7bfedc59 | 675 | return idx; |
fd4abac5 TW |
676 | } |
677 | ||
17b88929 TW |
678 | /** |
679 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
680 | * | |
681 | * When FW advances 'R' index, all entries between old and new 'R' index | |
682 | * need to be reclaimed. As result, some free space forms. If there is | |
683 | * enough free space (> low mark), wake the stack that feeds us. | |
684 | */ | |
3e10caeb EG |
685 | static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id, |
686 | int idx) | |
17b88929 | 687 | { |
3e10caeb | 688 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
8ad71bef | 689 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; |
17b88929 TW |
690 | struct iwl_queue *q = &txq->q; |
691 | int nfreed = 0; | |
692 | ||
015c15e1 JB |
693 | lockdep_assert_held(&txq->lock); |
694 | ||
499b1883 | 695 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
3e10caeb | 696 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " |
2e5d04da DH |
697 | "index %d is out of range [0-%d] %d %d.\n", __func__, |
698 | txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr); | |
17b88929 TW |
699 | return; |
700 | } | |
701 | ||
499b1883 TW |
702 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
703 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 704 | |
499b1883 | 705 | if (nfreed++ > 0) { |
3e10caeb | 706 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 | 707 | q->write_ptr, q->read_ptr); |
bcb9321c | 708 | iwl_op_mode_nic_error(trans->op_mode); |
17b88929 | 709 | } |
da99c4b6 | 710 | |
17b88929 TW |
711 | } |
712 | } | |
713 | ||
714 | /** | |
715 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
716 | * @rxb: Rx buffer to reclaim | |
247c61d6 EG |
717 | * @handler_status: return value of the handler of the command |
718 | * (put in setup_rx_handlers) | |
17b88929 TW |
719 | * |
720 | * If an Rx buffer has an async callback associated with it the callback | |
721 | * will be executed. The attached skb (if present) will only be freed | |
722 | * if the callback returns 1 | |
723 | */ | |
48a2d66f | 724 | void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_cmd_buffer *rxb, |
247c61d6 | 725 | int handler_status) |
17b88929 | 726 | { |
2f301227 | 727 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
728 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
729 | int txq_id = SEQ_TO_QUEUE(sequence); | |
730 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 731 | int cmd_index; |
c2acea8e JB |
732 | struct iwl_device_cmd *cmd; |
733 | struct iwl_cmd_meta *meta; | |
8ad71bef | 734 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c6f600fc | 735 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
736 | |
737 | /* If a Tx command is being handled and it isn't in the actual | |
738 | * command queue then there a command routing bug has been introduced | |
739 | * in the queue management code. */ | |
c6f600fc | 740 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 741 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
c6f600fc MV |
742 | txq_id, trans_pcie->cmd_queue, sequence, |
743 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
744 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 745 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 746 | return; |
01ef9323 | 747 | } |
17b88929 | 748 | |
015c15e1 JB |
749 | spin_lock(&txq->lock); |
750 | ||
4ce7cc2b | 751 | cmd_index = get_cmd_index(&txq->q, index); |
dd487449 ZY |
752 | cmd = txq->cmd[cmd_index]; |
753 | meta = &txq->meta[cmd_index]; | |
17b88929 | 754 | |
282cdb32 JB |
755 | txq->time_stamp = jiffies; |
756 | ||
6d8f6eeb EG |
757 | iwlagn_unmap_tfd(trans, meta, &txq->tfds[index], |
758 | DMA_BIDIRECTIONAL); | |
c33de625 | 759 | |
17b88929 | 760 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 761 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 762 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 763 | |
65b94a4a JB |
764 | meta->source->resp_pkt = pkt; |
765 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
766 | meta->source->_rx_page_order = hw_params(trans).rx_page_order; | |
247c61d6 | 767 | meta->source->handler_status = handler_status; |
247c61d6 | 768 | } |
2624e96c | 769 | |
3e10caeb | 770 | iwl_hcmd_queue_reclaim(trans, txq_id, index); |
17b88929 | 771 | |
c2acea8e | 772 | if (!(meta->flags & CMD_ASYNC)) { |
05c89b91 WYG |
773 | if (!test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) { |
774 | IWL_WARN(trans, | |
775 | "HCMD_ACTIVE already clear for command %s\n", | |
776 | get_cmd_string(cmd->hdr.cmd)); | |
777 | } | |
6d8f6eeb EG |
778 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
779 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", | |
d2dfe6df | 780 | get_cmd_string(cmd->hdr.cmd)); |
69a10b29 | 781 | wake_up(&trans->wait_command_queue); |
17b88929 | 782 | } |
3598e177 | 783 | |
dd487449 | 784 | meta->flags = 0; |
3598e177 | 785 | |
015c15e1 | 786 | spin_unlock(&txq->lock); |
17b88929 | 787 | } |
253a634c | 788 | |
253a634c EG |
789 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
790 | ||
6d8f6eeb | 791 | static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c EG |
792 | { |
793 | int ret; | |
794 | ||
795 | /* An asynchronous command can not expect an SKB to be set. */ | |
796 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
797 | return -EINVAL; | |
798 | ||
253a634c | 799 | |
6d8f6eeb | 800 | ret = iwl_enqueue_hcmd(trans, cmd); |
253a634c | 801 | if (ret < 0) { |
721c32f7 | 802 | IWL_ERR(trans, |
b36b110c | 803 | "Error sending %s: enqueue_hcmd failed: %d\n", |
253a634c EG |
804 | get_cmd_string(cmd->id), ret); |
805 | return ret; | |
806 | } | |
807 | return 0; | |
808 | } | |
809 | ||
6d8f6eeb | 810 | static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 811 | { |
8ad71bef | 812 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
813 | int cmd_idx; |
814 | int ret; | |
815 | ||
6d8f6eeb | 816 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
253a634c EG |
817 | get_cmd_string(cmd->id)); |
818 | ||
2cc39c94 JB |
819 | if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE, |
820 | &trans->shrd->status))) { | |
821 | IWL_ERR(trans, "Command %s: a command is already active!\n", | |
822 | get_cmd_string(cmd->id)); | |
823 | return -EIO; | |
824 | } | |
825 | ||
6d8f6eeb | 826 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
253a634c EG |
827 | get_cmd_string(cmd->id)); |
828 | ||
6d8f6eeb | 829 | cmd_idx = iwl_enqueue_hcmd(trans, cmd); |
253a634c EG |
830 | if (cmd_idx < 0) { |
831 | ret = cmd_idx; | |
6d8f6eeb | 832 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
721c32f7 | 833 | IWL_ERR(trans, |
b36b110c | 834 | "Error sending %s: enqueue_hcmd failed: %d\n", |
253a634c EG |
835 | get_cmd_string(cmd->id), ret); |
836 | return ret; | |
837 | } | |
838 | ||
69a10b29 | 839 | ret = wait_event_timeout(trans->wait_command_queue, |
6d8f6eeb | 840 | !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status), |
253a634c EG |
841 | HOST_COMPLETE_TIMEOUT); |
842 | if (!ret) { | |
6d8f6eeb | 843 | if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) { |
d10630af | 844 | struct iwl_tx_queue *txq = |
c6f600fc | 845 | &trans_pcie->txq[trans_pcie->cmd_queue]; |
d10630af WYG |
846 | struct iwl_queue *q = &txq->q; |
847 | ||
721c32f7 | 848 | IWL_ERR(trans, |
253a634c EG |
849 | "Error sending %s: time out after %dms.\n", |
850 | get_cmd_string(cmd->id), | |
851 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
852 | ||
721c32f7 | 853 | IWL_ERR(trans, |
d10630af WYG |
854 | "Current CMD queue read_ptr %d write_ptr %d\n", |
855 | q->read_ptr, q->write_ptr); | |
856 | ||
6d8f6eeb EG |
857 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); |
858 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command" | |
253a634c EG |
859 | "%s\n", get_cmd_string(cmd->id)); |
860 | ret = -ETIMEDOUT; | |
861 | goto cancel; | |
862 | } | |
863 | } | |
864 | ||
65b94a4a | 865 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 866 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
253a634c EG |
867 | get_cmd_string(cmd->id)); |
868 | ret = -EIO; | |
869 | goto cancel; | |
870 | } | |
871 | ||
872 | return 0; | |
873 | ||
874 | cancel: | |
875 | if (cmd->flags & CMD_WANT_SKB) { | |
876 | /* | |
877 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
878 | * TX cmd queue. Otherwise in case the cmd comes | |
879 | * in later, it will possibly set an invalid | |
880 | * address (cmd->meta.source). | |
881 | */ | |
c6f600fc | 882 | trans_pcie->txq[trans_pcie->cmd_queue].meta[cmd_idx].flags &= |
253a634c EG |
883 | ~CMD_WANT_SKB; |
884 | } | |
9cac4943 | 885 | |
65b94a4a JB |
886 | if (cmd->resp_pkt) { |
887 | iwl_free_resp(cmd); | |
888 | cmd->resp_pkt = NULL; | |
253a634c EG |
889 | } |
890 | ||
891 | return ret; | |
892 | } | |
893 | ||
6d8f6eeb | 894 | int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c EG |
895 | { |
896 | if (cmd->flags & CMD_ASYNC) | |
6d8f6eeb | 897 | return iwl_send_cmd_async(trans, cmd); |
253a634c | 898 | |
6d8f6eeb | 899 | return iwl_send_cmd_sync(trans, cmd); |
253a634c EG |
900 | } |
901 | ||
a0eaad71 | 902 | /* Frees buffers until index _not_ inclusive */ |
464021ff EG |
903 | int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index, |
904 | struct sk_buff_head *skbs) | |
a0eaad71 | 905 | { |
8ad71bef EG |
906 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
907 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
a0eaad71 | 908 | struct iwl_queue *q = &txq->q; |
a0eaad71 | 909 | int last_to_free; |
464021ff | 910 | int freed = 0; |
a0eaad71 | 911 | |
39644e9a | 912 | /* This function is not meant to release cmd queue*/ |
c6f600fc | 913 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) |
39644e9a EG |
914 | return 0; |
915 | ||
015c15e1 JB |
916 | lockdep_assert_held(&txq->lock); |
917 | ||
a0eaad71 EG |
918 | /*Since we free until index _not_ inclusive, the one before index is |
919 | * the last we will free. This one must be used */ | |
920 | last_to_free = iwl_queue_dec_wrap(index, q->n_bd); | |
921 | ||
922 | if ((index >= q->n_bd) || | |
923 | (iwl_queue_used(q, last_to_free) == 0)) { | |
924 | IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), " | |
925 | "last_to_free %d is out of range [0-%d] %d %d.\n", | |
926 | __func__, txq_id, last_to_free, q->n_bd, | |
927 | q->write_ptr, q->read_ptr); | |
464021ff | 928 | return 0; |
a0eaad71 EG |
929 | } |
930 | ||
a0eaad71 | 931 | if (WARN_ON(!skb_queue_empty(skbs))) |
464021ff | 932 | return 0; |
a0eaad71 EG |
933 | |
934 | for (; | |
935 | q->read_ptr != index; | |
936 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
937 | ||
2c452297 | 938 | if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL)) |
a0eaad71 EG |
939 | continue; |
940 | ||
2c452297 | 941 | __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]); |
a0eaad71 | 942 | |
2c452297 | 943 | txq->skbs[txq->q.read_ptr] = NULL; |
a0eaad71 | 944 | |
6d8f6eeb | 945 | iwlagn_txq_inval_byte_cnt_tbl(trans, txq); |
a0eaad71 | 946 | |
39644e9a | 947 | iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr, DMA_TO_DEVICE); |
464021ff | 948 | freed++; |
a0eaad71 | 949 | } |
464021ff | 950 | return freed; |
a0eaad71 | 951 | } |