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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
8 | * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
33 | * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. | |
34 | * All rights reserved. | |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
e6bb4c9c | 63 | #include <linux/interrupt.h> |
87e5666c | 64 | #include <linux/debugfs.h> |
e6bb4c9c | 65 | |
a0f6b0a2 | 66 | #include "iwl-dev.h" |
c85eb619 | 67 | #include "iwl-trans.h" |
02aca585 EG |
68 | #include "iwl-core.h" |
69 | #include "iwl-helpers.h" | |
ab697a9f | 70 | #include "iwl-trans-int-pcie.h" |
02aca585 EG |
71 | /*TODO remove uneeded includes when the transport layer tx_free will be here */ |
72 | #include "iwl-agn.h" | |
e419d62d | 73 | #include "iwl-core.h" |
48f20d35 | 74 | #include "iwl-shared.h" |
c85eb619 | 75 | |
5a878bf6 | 76 | static int iwl_trans_rx_alloc(struct iwl_trans *trans) |
c85eb619 | 77 | { |
5a878bf6 EG |
78 | struct iwl_trans_pcie *trans_pcie = |
79 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
80 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
81 | struct device *dev = bus(trans)->dev; | |
c85eb619 | 82 | |
5a878bf6 | 83 | memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq)); |
c85eb619 EG |
84 | |
85 | spin_lock_init(&rxq->lock); | |
86 | INIT_LIST_HEAD(&rxq->rx_free); | |
87 | INIT_LIST_HEAD(&rxq->rx_used); | |
88 | ||
89 | if (WARN_ON(rxq->bd || rxq->rb_stts)) | |
90 | return -EINVAL; | |
91 | ||
92 | /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */ | |
a0f6b0a2 EG |
93 | rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
94 | &rxq->bd_dma, GFP_KERNEL); | |
c85eb619 EG |
95 | if (!rxq->bd) |
96 | goto err_bd; | |
a0f6b0a2 | 97 | memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE); |
c85eb619 EG |
98 | |
99 | /*Allocate the driver's pointer to receive buffer status */ | |
100 | rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts), | |
101 | &rxq->rb_stts_dma, GFP_KERNEL); | |
102 | if (!rxq->rb_stts) | |
103 | goto err_rb_stts; | |
104 | memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts)); | |
105 | ||
106 | return 0; | |
107 | ||
108 | err_rb_stts: | |
a0f6b0a2 EG |
109 | dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
110 | rxq->bd, rxq->bd_dma); | |
c85eb619 EG |
111 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); |
112 | rxq->bd = NULL; | |
113 | err_bd: | |
114 | return -ENOMEM; | |
115 | } | |
116 | ||
5a878bf6 | 117 | static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans) |
c85eb619 | 118 | { |
5a878bf6 EG |
119 | struct iwl_trans_pcie *trans_pcie = |
120 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
121 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
a0f6b0a2 | 122 | int i; |
c85eb619 EG |
123 | |
124 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
125 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
126 | /* In the reset function, these buffers may have been allocated | |
127 | * to an SKB, so we need to unmap and free potential storage */ | |
128 | if (rxq->pool[i].page != NULL) { | |
5a878bf6 EG |
129 | dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma, |
130 | PAGE_SIZE << hw_params(trans).rx_page_order, | |
c85eb619 | 131 | DMA_FROM_DEVICE); |
5a878bf6 | 132 | __iwl_free_pages(priv(trans), rxq->pool[i].page); |
c85eb619 EG |
133 | rxq->pool[i].page = NULL; |
134 | } | |
135 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
136 | } | |
a0f6b0a2 EG |
137 | } |
138 | ||
ab697a9f EG |
139 | static void iwl_trans_rx_hw_init(struct iwl_priv *priv, |
140 | struct iwl_rx_queue *rxq) | |
141 | { | |
142 | u32 rb_size; | |
143 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ | |
144 | u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */ | |
145 | ||
146 | rb_timeout = RX_RB_TIMEOUT; | |
147 | ||
148 | if (iwlagn_mod_params.amsdu_size_8K) | |
149 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; | |
150 | else | |
151 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | |
152 | ||
153 | /* Stop Rx DMA */ | |
154 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | |
155 | ||
156 | /* Reset driver's Rx queue write index */ | |
157 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); | |
158 | ||
159 | /* Tell device where to find RBD circular buffer in DRAM */ | |
160 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
161 | (u32)(rxq->bd_dma >> 8)); | |
162 | ||
163 | /* Tell device where in DRAM to update its Rx status */ | |
164 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
165 | rxq->rb_stts_dma >> 4); | |
166 | ||
167 | /* Enable Rx DMA | |
168 | * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in | |
169 | * the credit mechanism in 5000 HW RX FIFO | |
170 | * Direct rx interrupts to hosts | |
171 | * Rx buffer size 4 or 8k | |
172 | * RB timeout 0x10 | |
173 | * 256 RBDs | |
174 | */ | |
175 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, | |
176 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | | |
177 | FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | | |
178 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | | |
179 | FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | | |
180 | rb_size| | |
181 | (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| | |
182 | (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); | |
183 | ||
184 | /* Set interrupt coalescing timer to default (2048 usecs) */ | |
185 | iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); | |
186 | } | |
187 | ||
5a878bf6 | 188 | static int iwl_rx_init(struct iwl_trans *trans) |
a0f6b0a2 | 189 | { |
5a878bf6 EG |
190 | struct iwl_trans_pcie *trans_pcie = |
191 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
192 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
193 | ||
a0f6b0a2 EG |
194 | int i, err; |
195 | unsigned long flags; | |
196 | ||
197 | if (!rxq->bd) { | |
5a878bf6 | 198 | err = iwl_trans_rx_alloc(trans); |
a0f6b0a2 EG |
199 | if (err) |
200 | return err; | |
201 | } | |
202 | ||
203 | spin_lock_irqsave(&rxq->lock, flags); | |
204 | INIT_LIST_HEAD(&rxq->rx_free); | |
205 | INIT_LIST_HEAD(&rxq->rx_used); | |
206 | ||
5a878bf6 | 207 | iwl_trans_rxq_free_rx_bufs(trans); |
c85eb619 EG |
208 | |
209 | for (i = 0; i < RX_QUEUE_SIZE; i++) | |
210 | rxq->queue[i] = NULL; | |
211 | ||
212 | /* Set us so that we have processed and used all buffers, but have | |
213 | * not restocked the Rx queue with fresh buffers */ | |
214 | rxq->read = rxq->write = 0; | |
215 | rxq->write_actual = 0; | |
216 | rxq->free_count = 0; | |
217 | spin_unlock_irqrestore(&rxq->lock, flags); | |
218 | ||
5a878bf6 | 219 | iwlagn_rx_replenish(trans); |
ab697a9f | 220 | |
5a878bf6 | 221 | iwl_trans_rx_hw_init(priv(trans), rxq); |
ab697a9f | 222 | |
5a878bf6 | 223 | spin_lock_irqsave(&trans->shrd->lock, flags); |
ab697a9f | 224 | rxq->need_update = 1; |
5a878bf6 EG |
225 | iwl_rx_queue_update_write_ptr(trans, rxq); |
226 | spin_unlock_irqrestore(&trans->shrd->lock, flags); | |
ab697a9f | 227 | |
c85eb619 EG |
228 | return 0; |
229 | } | |
230 | ||
5a878bf6 | 231 | static void iwl_trans_pcie_rx_free(struct iwl_trans *trans) |
a0f6b0a2 | 232 | { |
5a878bf6 EG |
233 | struct iwl_trans_pcie *trans_pcie = |
234 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
235 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
236 | ||
a0f6b0a2 EG |
237 | unsigned long flags; |
238 | ||
239 | /*if rxq->bd is NULL, it means that nothing has been allocated, | |
240 | * exit now */ | |
241 | if (!rxq->bd) { | |
5a878bf6 | 242 | IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); |
a0f6b0a2 EG |
243 | return; |
244 | } | |
245 | ||
246 | spin_lock_irqsave(&rxq->lock, flags); | |
5a878bf6 | 247 | iwl_trans_rxq_free_rx_bufs(trans); |
a0f6b0a2 EG |
248 | spin_unlock_irqrestore(&rxq->lock, flags); |
249 | ||
5a878bf6 | 250 | dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE, |
a0f6b0a2 EG |
251 | rxq->bd, rxq->bd_dma); |
252 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); | |
253 | rxq->bd = NULL; | |
254 | ||
255 | if (rxq->rb_stts) | |
5a878bf6 | 256 | dma_free_coherent(bus(trans)->dev, |
a0f6b0a2 EG |
257 | sizeof(struct iwl_rb_status), |
258 | rxq->rb_stts, rxq->rb_stts_dma); | |
259 | else | |
5a878bf6 | 260 | IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n"); |
a0f6b0a2 EG |
261 | memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma)); |
262 | rxq->rb_stts = NULL; | |
263 | } | |
264 | ||
c2c52e8b EG |
265 | static int iwl_trans_rx_stop(struct iwl_priv *priv) |
266 | { | |
267 | ||
268 | /* stop Rx DMA */ | |
269 | iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | |
270 | return iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG, | |
271 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); | |
272 | } | |
273 | ||
02aca585 EG |
274 | static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv, |
275 | struct iwl_dma_ptr *ptr, size_t size) | |
276 | { | |
277 | if (WARN_ON(ptr->addr)) | |
278 | return -EINVAL; | |
279 | ||
d5934110 | 280 | ptr->addr = dma_alloc_coherent(priv->bus->dev, size, |
02aca585 EG |
281 | &ptr->dma, GFP_KERNEL); |
282 | if (!ptr->addr) | |
283 | return -ENOMEM; | |
284 | ptr->size = size; | |
285 | return 0; | |
286 | } | |
287 | ||
1359ca4f EG |
288 | static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv, |
289 | struct iwl_dma_ptr *ptr) | |
290 | { | |
291 | if (unlikely(!ptr->addr)) | |
292 | return; | |
293 | ||
d5934110 | 294 | dma_free_coherent(priv->bus->dev, ptr->size, ptr->addr, ptr->dma); |
1359ca4f EG |
295 | memset(ptr, 0, sizeof(*ptr)); |
296 | } | |
297 | ||
02aca585 EG |
298 | static int iwl_trans_txq_alloc(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
299 | int slots_num, u32 txq_id) | |
300 | { | |
d6189124 | 301 | size_t tfd_sz = hw_params(priv).tfd_size * TFD_QUEUE_SIZE_MAX; |
02aca585 EG |
302 | int i; |
303 | ||
304 | if (WARN_ON(txq->meta || txq->cmd || txq->txb || txq->tfds)) | |
305 | return -EINVAL; | |
306 | ||
1359ca4f EG |
307 | txq->q.n_window = slots_num; |
308 | ||
02aca585 EG |
309 | txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num, |
310 | GFP_KERNEL); | |
311 | txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num, | |
312 | GFP_KERNEL); | |
313 | ||
314 | if (!txq->meta || !txq->cmd) | |
315 | goto error; | |
316 | ||
317 | for (i = 0; i < slots_num; i++) { | |
318 | txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd), | |
319 | GFP_KERNEL); | |
320 | if (!txq->cmd[i]) | |
321 | goto error; | |
322 | } | |
323 | ||
324 | /* Alloc driver data array and TFD circular buffer */ | |
325 | /* Driver private data, only for Tx (not command) queues, | |
326 | * not shared with device. */ | |
cefeaa5f | 327 | if (txq_id != priv->shrd->cmd_queue) { |
02aca585 EG |
328 | txq->txb = kzalloc(sizeof(txq->txb[0]) * |
329 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
330 | if (!txq->txb) { | |
331 | IWL_ERR(priv, "kmalloc for auxiliary BD " | |
332 | "structures failed\n"); | |
333 | goto error; | |
334 | } | |
335 | } else { | |
336 | txq->txb = NULL; | |
337 | } | |
338 | ||
339 | /* Circular buffer of transmit frame descriptors (TFDs), | |
340 | * shared with device */ | |
d5934110 | 341 | txq->tfds = dma_alloc_coherent(priv->bus->dev, tfd_sz, &txq->q.dma_addr, |
02aca585 EG |
342 | GFP_KERNEL); |
343 | if (!txq->tfds) { | |
344 | IWL_ERR(priv, "dma_alloc_coherent(%zd) failed\n", tfd_sz); | |
345 | goto error; | |
346 | } | |
347 | txq->q.id = txq_id; | |
348 | ||
349 | return 0; | |
350 | error: | |
351 | kfree(txq->txb); | |
352 | txq->txb = NULL; | |
353 | /* since txq->cmd has been zeroed, | |
354 | * all non allocated cmd[i] will be NULL */ | |
355 | if (txq->cmd) | |
356 | for (i = 0; i < slots_num; i++) | |
357 | kfree(txq->cmd[i]); | |
358 | kfree(txq->meta); | |
359 | kfree(txq->cmd); | |
360 | txq->meta = NULL; | |
361 | txq->cmd = NULL; | |
362 | ||
363 | return -ENOMEM; | |
364 | ||
365 | } | |
366 | ||
367 | static int iwl_trans_txq_init(struct iwl_priv *priv, struct iwl_tx_queue *txq, | |
368 | int slots_num, u32 txq_id) | |
369 | { | |
370 | int ret; | |
371 | ||
372 | txq->need_update = 0; | |
373 | memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num); | |
374 | ||
375 | /* | |
376 | * For the default queues 0-3, set up the swq_id | |
377 | * already -- all others need to get one later | |
378 | * (if they need one at all). | |
379 | */ | |
380 | if (txq_id < 4) | |
381 | iwl_set_swq_id(txq, txq_id, txq_id); | |
382 | ||
383 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
384 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
385 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
386 | ||
387 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
388 | ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, | |
389 | txq_id); | |
390 | if (ret) | |
391 | return ret; | |
392 | ||
393 | /* | |
394 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
395 | * given Tx queue, and enable the DMA channel used for that queue. | |
396 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
397 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
398 | txq->q.dma_addr >> 8); | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
c170b867 EG |
403 | /** |
404 | * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's | |
405 | */ | |
406 | static void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id) | |
407 | { | |
408 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
409 | struct iwl_queue *q = &txq->q; | |
410 | ||
411 | if (!q->n_bd) | |
412 | return; | |
413 | ||
414 | while (q->write_ptr != q->read_ptr) { | |
415 | /* The read_ptr needs to bound by q->n_window */ | |
416 | iwlagn_txq_free_tfd(priv, txq, get_cmd_index(q, q->read_ptr)); | |
417 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); | |
418 | } | |
419 | } | |
420 | ||
1359ca4f EG |
421 | /** |
422 | * iwl_tx_queue_free - Deallocate DMA queue. | |
423 | * @txq: Transmit queue to deallocate. | |
424 | * | |
425 | * Empty queue by removing and destroying all BD's. | |
426 | * Free all buffers. | |
427 | * 0-fill, but do not free "txq" descriptor structure. | |
428 | */ | |
429 | static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id) | |
430 | { | |
431 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
d5934110 | 432 | struct device *dev = priv->bus->dev; |
1359ca4f EG |
433 | int i; |
434 | if (WARN_ON(!txq)) | |
435 | return; | |
436 | ||
437 | iwl_tx_queue_unmap(priv, txq_id); | |
438 | ||
439 | /* De-alloc array of command/tx buffers */ | |
440 | for (i = 0; i < txq->q.n_window; i++) | |
441 | kfree(txq->cmd[i]); | |
442 | ||
443 | /* De-alloc circular buffer of TFDs */ | |
444 | if (txq->q.n_bd) { | |
d6189124 | 445 | dma_free_coherent(dev, hw_params(priv).tfd_size * |
1359ca4f EG |
446 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
447 | memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr)); | |
448 | } | |
449 | ||
450 | /* De-alloc array of per-TFD driver data */ | |
451 | kfree(txq->txb); | |
452 | txq->txb = NULL; | |
453 | ||
454 | /* deallocate arrays */ | |
455 | kfree(txq->cmd); | |
456 | kfree(txq->meta); | |
457 | txq->cmd = NULL; | |
458 | txq->meta = NULL; | |
459 | ||
460 | /* 0-fill queue descriptor structure */ | |
461 | memset(txq, 0, sizeof(*txq)); | |
462 | } | |
463 | ||
464 | /** | |
465 | * iwl_trans_tx_free - Free TXQ Context | |
466 | * | |
467 | * Destroy all TX DMA queues and structures | |
468 | */ | |
e6bb4c9c | 469 | static void iwl_trans_pcie_tx_free(struct iwl_priv *priv) |
1359ca4f EG |
470 | { |
471 | int txq_id; | |
105183b1 EG |
472 | struct iwl_trans *trans = trans(priv); |
473 | struct iwl_trans_pcie *trans_pcie = | |
474 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1359ca4f EG |
475 | |
476 | /* Tx queues */ | |
477 | if (priv->txq) { | |
d6189124 EG |
478 | for (txq_id = 0; |
479 | txq_id < hw_params(priv).max_txq_num; txq_id++) | |
1359ca4f EG |
480 | iwl_tx_queue_free(priv, txq_id); |
481 | } | |
482 | ||
483 | kfree(priv->txq); | |
484 | priv->txq = NULL; | |
485 | ||
486 | iwlagn_free_dma_ptr(priv, &priv->kw); | |
487 | ||
105183b1 | 488 | iwlagn_free_dma_ptr(priv, &trans_pcie->scd_bc_tbls); |
1359ca4f EG |
489 | } |
490 | ||
02aca585 EG |
491 | /** |
492 | * iwl_trans_tx_alloc - allocate TX context | |
493 | * Allocate all Tx DMA structures and initialize them | |
494 | * | |
495 | * @param priv | |
496 | * @return error code | |
497 | */ | |
498 | static int iwl_trans_tx_alloc(struct iwl_priv *priv) | |
499 | { | |
500 | int ret; | |
501 | int txq_id, slots_num; | |
105183b1 EG |
502 | struct iwl_trans *trans = trans(priv); |
503 | struct iwl_trans_pcie *trans_pcie = | |
504 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
02aca585 EG |
505 | |
506 | /*It is not allowed to alloc twice, so warn when this happens. | |
507 | * We cannot rely on the previous allocation, so free and fail */ | |
508 | if (WARN_ON(priv->txq)) { | |
509 | ret = -EINVAL; | |
510 | goto error; | |
511 | } | |
512 | ||
105183b1 | 513 | ret = iwlagn_alloc_dma_ptr(priv, &trans_pcie->scd_bc_tbls, |
d6189124 | 514 | hw_params(priv).scd_bc_tbls_size); |
02aca585 EG |
515 | if (ret) { |
516 | IWL_ERR(priv, "Scheduler BC Table allocation failed\n"); | |
517 | goto error; | |
518 | } | |
519 | ||
520 | /* Alloc keep-warm buffer */ | |
521 | ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE); | |
522 | if (ret) { | |
523 | IWL_ERR(priv, "Keep Warm allocation failed\n"); | |
524 | goto error; | |
525 | } | |
526 | ||
527 | priv->txq = kzalloc(sizeof(struct iwl_tx_queue) * | |
528 | priv->cfg->base_params->num_of_queues, GFP_KERNEL); | |
529 | if (!priv->txq) { | |
530 | IWL_ERR(priv, "Not enough memory for txq\n"); | |
531 | ret = ENOMEM; | |
532 | goto error; | |
533 | } | |
534 | ||
535 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
d6189124 | 536 | for (txq_id = 0; txq_id < hw_params(priv).max_txq_num; txq_id++) { |
cefeaa5f | 537 | slots_num = (txq_id == priv->shrd->cmd_queue) ? |
02aca585 EG |
538 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
539 | ret = iwl_trans_txq_alloc(priv, &priv->txq[txq_id], slots_num, | |
540 | txq_id); | |
541 | if (ret) { | |
542 | IWL_ERR(priv, "Tx %d queue alloc failed\n", txq_id); | |
543 | goto error; | |
544 | } | |
545 | } | |
546 | ||
547 | return 0; | |
548 | ||
549 | error: | |
e6bb4c9c | 550 | iwl_trans_tx_free(trans(priv)); |
02aca585 EG |
551 | |
552 | return ret; | |
553 | } | |
392f8b78 | 554 | static int iwl_tx_init(struct iwl_priv *priv) |
02aca585 EG |
555 | { |
556 | int ret; | |
557 | int txq_id, slots_num; | |
558 | unsigned long flags; | |
559 | bool alloc = false; | |
560 | ||
561 | if (!priv->txq) { | |
562 | ret = iwl_trans_tx_alloc(priv); | |
563 | if (ret) | |
564 | goto error; | |
565 | alloc = true; | |
566 | } | |
567 | ||
10b15e6f | 568 | spin_lock_irqsave(&priv->shrd->lock, flags); |
02aca585 EG |
569 | |
570 | /* Turn off all Tx DMA fifos */ | |
b3c2ce13 | 571 | iwl_write_prph(priv, SCD_TXFACT, 0); |
02aca585 EG |
572 | |
573 | /* Tell NIC where to find the "keep warm" buffer */ | |
574 | iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4); | |
575 | ||
10b15e6f | 576 | spin_unlock_irqrestore(&priv->shrd->lock, flags); |
02aca585 EG |
577 | |
578 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
d6189124 | 579 | for (txq_id = 0; txq_id < hw_params(priv).max_txq_num; txq_id++) { |
cefeaa5f | 580 | slots_num = (txq_id == priv->shrd->cmd_queue) ? |
02aca585 EG |
581 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
582 | ret = iwl_trans_txq_init(priv, &priv->txq[txq_id], slots_num, | |
583 | txq_id); | |
584 | if (ret) { | |
585 | IWL_ERR(priv, "Tx %d queue init failed\n", txq_id); | |
586 | goto error; | |
587 | } | |
588 | } | |
589 | ||
590 | return 0; | |
591 | error: | |
592 | /*Upon error, free only if we allocated something */ | |
593 | if (alloc) | |
e6bb4c9c | 594 | iwl_trans_tx_free(trans(priv)); |
02aca585 EG |
595 | return ret; |
596 | } | |
597 | ||
392f8b78 EG |
598 | static void iwl_set_pwr_vmain(struct iwl_priv *priv) |
599 | { | |
600 | /* | |
601 | * (for documentation purposes) | |
602 | * to set power to V_AUX, do: | |
603 | ||
604 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) | |
605 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
606 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
607 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
608 | */ | |
609 | ||
610 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
611 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
612 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
613 | } | |
614 | ||
615 | static int iwl_nic_init(struct iwl_priv *priv) | |
616 | { | |
617 | unsigned long flags; | |
618 | ||
619 | /* nic_init */ | |
10b15e6f | 620 | spin_lock_irqsave(&priv->shrd->lock, flags); |
392f8b78 EG |
621 | iwl_apm_init(priv); |
622 | ||
623 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ | |
624 | iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF); | |
625 | ||
10b15e6f | 626 | spin_unlock_irqrestore(&priv->shrd->lock, flags); |
392f8b78 EG |
627 | |
628 | iwl_set_pwr_vmain(priv); | |
629 | ||
630 | priv->cfg->lib->nic_config(priv); | |
631 | ||
632 | /* Allocate the RX queue, or reset if it is already allocated */ | |
5a878bf6 | 633 | iwl_rx_init(trans(priv)); |
392f8b78 EG |
634 | |
635 | /* Allocate or reset and init all Tx and Command queues */ | |
636 | if (iwl_tx_init(priv)) | |
637 | return -ENOMEM; | |
638 | ||
639 | if (priv->cfg->base_params->shadow_reg_enable) { | |
640 | /* enable shadow regs in HW */ | |
641 | iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL, | |
642 | 0x800FFFFF); | |
643 | } | |
644 | ||
63013ae3 | 645 | set_bit(STATUS_INIT, &priv->shrd->status); |
392f8b78 EG |
646 | |
647 | return 0; | |
648 | } | |
649 | ||
650 | #define HW_READY_TIMEOUT (50) | |
651 | ||
652 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
653 | static int iwl_set_hw_ready(struct iwl_priv *priv) | |
654 | { | |
655 | int ret; | |
656 | ||
657 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
658 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
659 | ||
660 | /* See if we got it */ | |
661 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
662 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
663 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
664 | HW_READY_TIMEOUT); | |
665 | ||
666 | IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : ""); | |
667 | return ret; | |
668 | } | |
669 | ||
670 | /* Note: returns standard 0/-ERROR code */ | |
e6bb4c9c | 671 | static int iwl_trans_pcie_prepare_card_hw(struct iwl_priv *priv) |
392f8b78 EG |
672 | { |
673 | int ret; | |
674 | ||
0286cee0 | 675 | IWL_DEBUG_INFO(priv, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 EG |
676 | |
677 | ret = iwl_set_hw_ready(priv); | |
678 | if (ret >= 0) | |
679 | return 0; | |
680 | ||
681 | /* If HW is not ready, prepare the conditions to check again */ | |
682 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
683 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
684 | ||
685 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
686 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
687 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
688 | ||
689 | if (ret < 0) | |
690 | return ret; | |
691 | ||
692 | /* HW should be ready by now, check again. */ | |
693 | ret = iwl_set_hw_ready(priv); | |
694 | if (ret >= 0) | |
695 | return 0; | |
696 | return ret; | |
697 | } | |
698 | ||
e6bb4c9c | 699 | static int iwl_trans_pcie_start_device(struct iwl_priv *priv) |
392f8b78 EG |
700 | { |
701 | int ret; | |
702 | ||
703 | priv->ucode_owner = IWL_OWNERSHIP_DRIVER; | |
704 | ||
705 | if ((priv->cfg->sku & EEPROM_SKU_CAP_AMT_ENABLE) && | |
e6bb4c9c | 706 | iwl_trans_pcie_prepare_card_hw(priv)) { |
392f8b78 EG |
707 | IWL_WARN(priv, "Exit HW not ready\n"); |
708 | return -EIO; | |
709 | } | |
710 | ||
711 | /* If platform's RF_KILL switch is NOT set to KILL */ | |
712 | if (iwl_read32(priv, CSR_GP_CNTRL) & | |
713 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
63013ae3 | 714 | clear_bit(STATUS_RF_KILL_HW, &priv->shrd->status); |
392f8b78 | 715 | else |
63013ae3 | 716 | set_bit(STATUS_RF_KILL_HW, &priv->shrd->status); |
392f8b78 EG |
717 | |
718 | if (iwl_is_rfkill(priv)) { | |
719 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, true); | |
0c325769 | 720 | iwl_enable_interrupts(trans(priv)); |
392f8b78 EG |
721 | return -ERFKILL; |
722 | } | |
723 | ||
724 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | |
725 | ||
726 | ret = iwl_nic_init(priv); | |
727 | if (ret) { | |
728 | IWL_ERR(priv, "Unable to init nic\n"); | |
729 | return ret; | |
730 | } | |
731 | ||
732 | /* make sure rfkill handshake bits are cleared */ | |
733 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
734 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
735 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); | |
736 | ||
737 | /* clear (again), then enable host interrupts */ | |
738 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | |
0c325769 | 739 | iwl_enable_interrupts(trans(priv)); |
392f8b78 EG |
740 | |
741 | /* really make sure rfkill handshake bits are cleared */ | |
742 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
743 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
744 | ||
745 | return 0; | |
746 | } | |
747 | ||
b3c2ce13 EG |
748 | /* |
749 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
10b15e6f | 750 | * must be called under priv->shrd->lock and mac access |
b3c2ce13 EG |
751 | */ |
752 | static void iwl_trans_txq_set_sched(struct iwl_priv *priv, u32 mask) | |
753 | { | |
754 | iwl_write_prph(priv, SCD_TXFACT, mask); | |
755 | } | |
756 | ||
757 | #define IWL_AC_UNSET -1 | |
758 | ||
759 | struct queue_to_fifo_ac { | |
760 | s8 fifo, ac; | |
761 | }; | |
762 | ||
763 | static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = { | |
764 | { IWL_TX_FIFO_VO, IEEE80211_AC_VO, }, | |
765 | { IWL_TX_FIFO_VI, IEEE80211_AC_VI, }, | |
766 | { IWL_TX_FIFO_BE, IEEE80211_AC_BE, }, | |
767 | { IWL_TX_FIFO_BK, IEEE80211_AC_BK, }, | |
768 | { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, }, | |
769 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
770 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
771 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
772 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
773 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
72c04ce0 | 774 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, |
b3c2ce13 EG |
775 | }; |
776 | ||
777 | static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = { | |
778 | { IWL_TX_FIFO_VO, IEEE80211_AC_VO, }, | |
779 | { IWL_TX_FIFO_VI, IEEE80211_AC_VI, }, | |
780 | { IWL_TX_FIFO_BE, IEEE80211_AC_BE, }, | |
781 | { IWL_TX_FIFO_BK, IEEE80211_AC_BK, }, | |
782 | { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, }, | |
783 | { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, }, | |
784 | { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, }, | |
785 | { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, }, | |
786 | { IWL_TX_FIFO_BE_IPAN, 2, }, | |
787 | { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, }, | |
72c04ce0 | 788 | { IWL_TX_FIFO_AUX, IWL_AC_UNSET, }, |
b3c2ce13 | 789 | }; |
e6bb4c9c | 790 | static void iwl_trans_pcie_tx_start(struct iwl_priv *priv) |
b3c2ce13 EG |
791 | { |
792 | const struct queue_to_fifo_ac *queue_to_fifo; | |
793 | struct iwl_rxon_context *ctx; | |
105183b1 EG |
794 | struct iwl_trans *trans = trans(priv); |
795 | struct iwl_trans_pcie *trans_pcie = | |
796 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
b3c2ce13 EG |
797 | u32 a; |
798 | unsigned long flags; | |
799 | int i, chan; | |
800 | u32 reg_val; | |
801 | ||
105183b1 | 802 | spin_lock_irqsave(&trans->shrd->lock, flags); |
b3c2ce13 | 803 | |
105183b1 EG |
804 | trans_pcie->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR); |
805 | a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND; | |
b3c2ce13 | 806 | /* reset conext data memory */ |
105183b1 | 807 | for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND; |
b3c2ce13 EG |
808 | a += 4) |
809 | iwl_write_targ_mem(priv, a, 0); | |
810 | /* reset tx status memory */ | |
105183b1 | 811 | for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND; |
b3c2ce13 EG |
812 | a += 4) |
813 | iwl_write_targ_mem(priv, a, 0); | |
105183b1 | 814 | for (; a < trans_pcie->scd_base_addr + |
d6189124 EG |
815 | SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(priv).max_txq_num); |
816 | a += 4) | |
b3c2ce13 EG |
817 | iwl_write_targ_mem(priv, a, 0); |
818 | ||
819 | iwl_write_prph(priv, SCD_DRAM_BASE_ADDR, | |
105183b1 | 820 | trans_pcie->scd_bc_tbls.dma >> 10); |
b3c2ce13 EG |
821 | |
822 | /* Enable DMA channel */ | |
823 | for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++) | |
824 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
825 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
826 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
827 | ||
828 | /* Update FH chicken bits */ | |
829 | reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG); | |
830 | iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG, | |
831 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
832 | ||
833 | iwl_write_prph(priv, SCD_QUEUECHAIN_SEL, | |
834 | SCD_QUEUECHAIN_SEL_ALL(priv)); | |
835 | iwl_write_prph(priv, SCD_AGGR_SEL, 0); | |
836 | ||
837 | /* initiate the queues */ | |
d6189124 | 838 | for (i = 0; i < hw_params(priv).max_txq_num; i++) { |
b3c2ce13 EG |
839 | iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0); |
840 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); | |
105183b1 | 841 | iwl_write_targ_mem(priv, trans_pcie->scd_base_addr + |
b3c2ce13 | 842 | SCD_CONTEXT_QUEUE_OFFSET(i), 0); |
105183b1 | 843 | iwl_write_targ_mem(priv, trans_pcie->scd_base_addr + |
b3c2ce13 EG |
844 | SCD_CONTEXT_QUEUE_OFFSET(i) + |
845 | sizeof(u32), | |
846 | ((SCD_WIN_SIZE << | |
847 | SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
848 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
849 | ((SCD_FRAME_LIMIT << | |
850 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
851 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
852 | } | |
853 | ||
854 | iwl_write_prph(priv, SCD_INTERRUPT_MASK, | |
105183b1 | 855 | IWL_MASK(0, hw_params(trans).max_txq_num)); |
b3c2ce13 EG |
856 | |
857 | /* Activate all Tx DMA/FIFO channels */ | |
858 | iwl_trans_txq_set_sched(priv, IWL_MASK(0, 7)); | |
859 | ||
860 | /* map queues to FIFOs */ | |
861 | if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)) | |
862 | queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo; | |
863 | else | |
864 | queue_to_fifo = iwlagn_default_queue_to_tx_fifo; | |
865 | ||
cefeaa5f | 866 | iwl_trans_set_wr_ptrs(priv, priv->shrd->cmd_queue, 0); |
b3c2ce13 EG |
867 | |
868 | /* make sure all queue are not stopped */ | |
869 | memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped)); | |
870 | for (i = 0; i < 4; i++) | |
871 | atomic_set(&priv->queue_stop_count[i], 0); | |
872 | for_each_context(priv, ctx) | |
873 | ctx->last_tx_rejected = false; | |
874 | ||
875 | /* reset to 0 to enable all the queue first */ | |
876 | priv->txq_ctx_active_msk = 0; | |
877 | ||
72c04ce0 JB |
878 | BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) != |
879 | IWLAGN_FIRST_AMPDU_QUEUE); | |
880 | BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) != | |
881 | IWLAGN_FIRST_AMPDU_QUEUE); | |
b3c2ce13 | 882 | |
72c04ce0 | 883 | for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) { |
b3c2ce13 EG |
884 | int fifo = queue_to_fifo[i].fifo; |
885 | int ac = queue_to_fifo[i].ac; | |
886 | ||
887 | iwl_txq_ctx_activate(priv, i); | |
888 | ||
889 | if (fifo == IWL_TX_FIFO_UNUSED) | |
890 | continue; | |
891 | ||
892 | if (ac != IWL_AC_UNSET) | |
893 | iwl_set_swq_id(&priv->txq[i], ac, i); | |
48d42c42 | 894 | iwl_trans_tx_queue_set_status(priv, &priv->txq[i], fifo, 0); |
b3c2ce13 EG |
895 | } |
896 | ||
10b15e6f | 897 | spin_unlock_irqrestore(&priv->shrd->lock, flags); |
b3c2ce13 EG |
898 | |
899 | /* Enable L1-Active */ | |
900 | iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG, | |
901 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
902 | } | |
903 | ||
c170b867 EG |
904 | /** |
905 | * iwlagn_txq_ctx_stop - Stop all Tx DMA channels | |
906 | */ | |
907 | static int iwl_trans_tx_stop(struct iwl_priv *priv) | |
908 | { | |
909 | int ch, txq_id; | |
910 | unsigned long flags; | |
911 | ||
912 | /* Turn off all Tx DMA fifos */ | |
10b15e6f | 913 | spin_lock_irqsave(&priv->shrd->lock, flags); |
c170b867 | 914 | |
b3c2ce13 | 915 | iwl_trans_txq_set_sched(priv, 0); |
c170b867 EG |
916 | |
917 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
02f6f659 | 918 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { |
c170b867 EG |
919 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); |
920 | if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG, | |
921 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), | |
922 | 1000)) | |
923 | IWL_ERR(priv, "Failing on timeout while stopping" | |
924 | " DMA channel %d [0x%08x]", ch, | |
925 | iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG)); | |
926 | } | |
10b15e6f | 927 | spin_unlock_irqrestore(&priv->shrd->lock, flags); |
c170b867 EG |
928 | |
929 | if (!priv->txq) { | |
930 | IWL_WARN(priv, "Stopping tx queues that aren't allocated..."); | |
931 | return 0; | |
932 | } | |
933 | ||
934 | /* Unmap DMA from host system and free skb's */ | |
d6189124 | 935 | for (txq_id = 0; txq_id < hw_params(priv).max_txq_num; txq_id++) |
c170b867 EG |
936 | iwl_tx_queue_unmap(priv, txq_id); |
937 | ||
938 | return 0; | |
939 | } | |
940 | ||
e6bb4c9c | 941 | static void iwl_trans_pcie_stop_device(struct iwl_priv *priv) |
ab6cf8e8 | 942 | { |
ab6cf8e8 EG |
943 | /* stop and reset the on-board processor */ |
944 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
945 | ||
946 | /* tell the device to stop sending interrupts */ | |
0c325769 | 947 | iwl_trans_disable_sync_irq(trans(priv)); |
ab6cf8e8 EG |
948 | |
949 | /* device going down, Stop using ICT table */ | |
0c325769 | 950 | iwl_disable_ict(trans(priv)); |
ab6cf8e8 EG |
951 | |
952 | /* | |
953 | * If a HW restart happens during firmware loading, | |
954 | * then the firmware loading might call this function | |
955 | * and later it might be called again due to the | |
956 | * restart. So don't process again if the device is | |
957 | * already dead. | |
958 | */ | |
63013ae3 | 959 | if (test_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status)) { |
ab6cf8e8 EG |
960 | iwl_trans_tx_stop(priv); |
961 | iwl_trans_rx_stop(priv); | |
962 | ||
963 | /* Power-down device's busmaster DMA clocks */ | |
964 | iwl_write_prph(priv, APMG_CLK_DIS_REG, | |
965 | APMG_CLK_VAL_DMA_CLK_RQT); | |
966 | udelay(5); | |
967 | } | |
968 | ||
969 | /* Make sure (redundant) we've released our request to stay awake */ | |
970 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
971 | ||
972 | /* Stop the device, and put it in low power state */ | |
973 | iwl_apm_stop(priv); | |
974 | } | |
975 | ||
e6bb4c9c | 976 | static struct iwl_tx_cmd *iwl_trans_pcie_get_tx_cmd(struct iwl_priv *priv, |
47c1b496 EG |
977 | int txq_id) |
978 | { | |
979 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
980 | struct iwl_queue *q = &txq->q; | |
981 | struct iwl_device_cmd *dev_cmd; | |
982 | ||
983 | if (unlikely(iwl_queue_space(q) < q->high_mark)) | |
984 | return NULL; | |
985 | ||
986 | /* | |
987 | * Set up the Tx-command (not MAC!) header. | |
988 | * Store the chosen Tx queue and TFD index within the sequence field; | |
989 | * after Tx, uCode's Tx response will return this value so driver can | |
990 | * locate the frame within the tx queue and do post-tx processing. | |
991 | */ | |
992 | dev_cmd = txq->cmd[q->write_ptr]; | |
993 | memset(dev_cmd, 0, sizeof(*dev_cmd)); | |
994 | dev_cmd->hdr.cmd = REPLY_TX; | |
995 | dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
996 | INDEX_TO_SEQ(q->write_ptr))); | |
997 | return &dev_cmd->cmd.tx; | |
998 | } | |
999 | ||
e6bb4c9c | 1000 | static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb, |
47c1b496 EG |
1001 | struct iwl_tx_cmd *tx_cmd, int txq_id, __le16 fc, bool ampdu, |
1002 | struct iwl_rxon_context *ctx) | |
1003 | { | |
1004 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1005 | struct iwl_queue *q = &txq->q; | |
1006 | struct iwl_device_cmd *dev_cmd = txq->cmd[q->write_ptr]; | |
1007 | struct iwl_cmd_meta *out_meta; | |
1008 | ||
1009 | dma_addr_t phys_addr = 0; | |
1010 | dma_addr_t txcmd_phys; | |
1011 | dma_addr_t scratch_phys; | |
1012 | u16 len, firstlen, secondlen; | |
1013 | u8 wait_write_ptr = 0; | |
1014 | u8 hdr_len = ieee80211_hdrlen(fc); | |
1015 | ||
1016 | /* Set up driver data for this TFD */ | |
1017 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); | |
1018 | txq->txb[q->write_ptr].skb = skb; | |
1019 | txq->txb[q->write_ptr].ctx = ctx; | |
1020 | ||
1021 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
1022 | out_meta = &txq->meta[q->write_ptr]; | |
1023 | ||
1024 | /* | |
1025 | * Use the first empty entry in this queue's command buffer array | |
1026 | * to contain the Tx command and MAC header concatenated together | |
1027 | * (payload data will be in another buffer). | |
1028 | * Size of this varies, due to varying MAC header length. | |
1029 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
1030 | * of the MAC header (device reads on dword boundaries). | |
1031 | * We'll tell device about this padding later. | |
1032 | */ | |
1033 | len = sizeof(struct iwl_tx_cmd) + | |
1034 | sizeof(struct iwl_cmd_header) + hdr_len; | |
1035 | firstlen = (len + 3) & ~3; | |
1036 | ||
1037 | /* Tell NIC about any 2-byte padding after MAC header */ | |
1038 | if (firstlen != len) | |
1039 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
1040 | ||
1041 | /* Physical address of this Tx command's header (not MAC header!), | |
1042 | * within command buffer array. */ | |
d5934110 | 1043 | txcmd_phys = dma_map_single(priv->bus->dev, |
47c1b496 EG |
1044 | &dev_cmd->hdr, firstlen, |
1045 | DMA_BIDIRECTIONAL); | |
d5934110 | 1046 | if (unlikely(dma_mapping_error(priv->bus->dev, txcmd_phys))) |
47c1b496 EG |
1047 | return -1; |
1048 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); | |
1049 | dma_unmap_len_set(out_meta, len, firstlen); | |
1050 | ||
1051 | if (!ieee80211_has_morefrags(fc)) { | |
1052 | txq->need_update = 1; | |
1053 | } else { | |
1054 | wait_write_ptr = 1; | |
1055 | txq->need_update = 0; | |
1056 | } | |
1057 | ||
1058 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
1059 | * if any (802.11 null frames have no payload). */ | |
1060 | secondlen = skb->len - hdr_len; | |
1061 | if (secondlen > 0) { | |
d5934110 | 1062 | phys_addr = dma_map_single(priv->bus->dev, skb->data + hdr_len, |
47c1b496 | 1063 | secondlen, DMA_TO_DEVICE); |
d5934110 EG |
1064 | if (unlikely(dma_mapping_error(priv->bus->dev, phys_addr))) { |
1065 | dma_unmap_single(priv->bus->dev, | |
47c1b496 EG |
1066 | dma_unmap_addr(out_meta, mapping), |
1067 | dma_unmap_len(out_meta, len), | |
1068 | DMA_BIDIRECTIONAL); | |
1069 | return -1; | |
1070 | } | |
1071 | } | |
1072 | ||
1073 | /* Attach buffers to TFD */ | |
1074 | iwlagn_txq_attach_buf_to_tfd(priv, txq, txcmd_phys, firstlen, 1); | |
1075 | if (secondlen > 0) | |
1076 | iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, | |
1077 | secondlen, 0); | |
1078 | ||
1079 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + | |
1080 | offsetof(struct iwl_tx_cmd, scratch); | |
1081 | ||
1082 | /* take back ownership of DMA buffer to enable update */ | |
d5934110 | 1083 | dma_sync_single_for_cpu(priv->bus->dev, txcmd_phys, firstlen, |
47c1b496 EG |
1084 | DMA_BIDIRECTIONAL); |
1085 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
1086 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
1087 | ||
1088 | IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n", | |
1089 | le16_to_cpu(dev_cmd->hdr.sequence)); | |
1090 | IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); | |
1091 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); | |
1092 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
1093 | ||
1094 | /* Set up entry for this TFD in Tx byte-count array */ | |
1095 | if (ampdu) | |
48d42c42 | 1096 | iwl_trans_txq_update_byte_cnt_tbl(priv, txq, |
47c1b496 EG |
1097 | le16_to_cpu(tx_cmd->len)); |
1098 | ||
d5934110 | 1099 | dma_sync_single_for_device(priv->bus->dev, txcmd_phys, firstlen, |
47c1b496 EG |
1100 | DMA_BIDIRECTIONAL); |
1101 | ||
1102 | trace_iwlwifi_dev_tx(priv, | |
1103 | &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr], | |
1104 | sizeof(struct iwl_tfd), | |
1105 | &dev_cmd->hdr, firstlen, | |
1106 | skb->data + hdr_len, secondlen); | |
1107 | ||
1108 | /* Tell device the write index *just past* this latest filled TFD */ | |
1109 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1110 | iwl_txq_update_write_ptr(priv, txq); | |
1111 | ||
1112 | /* | |
1113 | * At this point the frame is "transmitted" successfully | |
1114 | * and we will get a TX status notification eventually, | |
1115 | * regardless of the value of ret. "ret" only indicates | |
1116 | * whether or not we should update the write pointer. | |
1117 | */ | |
a0eaad71 | 1118 | if (iwl_queue_space(q) < q->high_mark) { |
47c1b496 EG |
1119 | if (wait_write_ptr) { |
1120 | txq->need_update = 1; | |
1121 | iwl_txq_update_write_ptr(priv, txq); | |
1122 | } else { | |
1123 | iwl_stop_queue(priv, txq); | |
1124 | } | |
1125 | } | |
1126 | return 0; | |
1127 | } | |
1128 | ||
e6bb4c9c | 1129 | static void iwl_trans_pcie_kick_nic(struct iwl_priv *priv) |
56d90f4c EG |
1130 | { |
1131 | /* Remove all resets to allow NIC to operate */ | |
1132 | iwl_write32(priv, CSR_RESET, 0); | |
1133 | } | |
1134 | ||
e6bb4c9c EG |
1135 | static int iwl_trans_pcie_request_irq(struct iwl_trans *trans) |
1136 | { | |
5a878bf6 EG |
1137 | struct iwl_trans_pcie *trans_pcie = |
1138 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
e6bb4c9c EG |
1139 | int err; |
1140 | ||
0c325769 EG |
1141 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
1142 | ||
1143 | tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long)) | |
1144 | iwl_irq_tasklet, (unsigned long)trans); | |
e6bb4c9c | 1145 | |
0c325769 | 1146 | iwl_alloc_isr_ict(trans); |
e6bb4c9c EG |
1147 | |
1148 | err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED, | |
0c325769 | 1149 | DRV_NAME, trans); |
e6bb4c9c | 1150 | if (err) { |
0c325769 EG |
1151 | IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq); |
1152 | iwl_free_isr_ict(trans); | |
e6bb4c9c EG |
1153 | return err; |
1154 | } | |
1155 | ||
5a878bf6 | 1156 | INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish); |
e6bb4c9c EG |
1157 | return 0; |
1158 | } | |
1159 | ||
a0eaad71 EG |
1160 | static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, |
1161 | int ssn, u32 status, struct sk_buff_head *skbs) | |
1162 | { | |
1163 | struct iwl_priv *priv = priv(trans); | |
1164 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1165 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ | |
1166 | int tfd_num = ssn & (txq->q.n_bd - 1); | |
1167 | u8 agg_state; | |
1168 | bool cond; | |
1169 | ||
1170 | if (txq->sched_retry) { | |
1171 | agg_state = | |
1172 | priv->stations[txq->sta_id].tid[txq->tid].agg.state; | |
1173 | cond = (agg_state != IWL_EMPTYING_HW_QUEUE_DELBA); | |
1174 | } else { | |
1175 | cond = (status != TX_STATUS_FAIL_PASSIVE_NO_RX); | |
1176 | } | |
1177 | ||
1178 | if (txq->q.read_ptr != tfd_num) { | |
1179 | IWL_DEBUG_TX_REPLY(trans, "Retry scheduler reclaim " | |
1180 | "scd_ssn=%d idx=%d txq=%d swq=%d\n", | |
1181 | ssn , tfd_num, txq_id, txq->swq_id); | |
1182 | iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs); | |
1183 | if (iwl_queue_space(&txq->q) > txq->q.low_mark && cond) | |
1184 | iwl_wake_queue(priv, txq); | |
1185 | } | |
1186 | } | |
1187 | ||
0c325769 | 1188 | static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans *trans) |
a27367d2 | 1189 | { |
0c325769 EG |
1190 | unsigned long flags; |
1191 | struct iwl_trans_pcie *trans_pcie = | |
1192 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1193 | ||
1194 | spin_lock_irqsave(&trans->shrd->lock, flags); | |
1195 | iwl_disable_interrupts(trans); | |
1196 | spin_unlock_irqrestore(&trans->shrd->lock, flags); | |
1197 | ||
a27367d2 | 1198 | /* wait to make sure we flush pending tasklet*/ |
0c325769 EG |
1199 | synchronize_irq(bus(trans)->irq); |
1200 | tasklet_kill(&trans_pcie->irq_tasklet); | |
a27367d2 EG |
1201 | } |
1202 | ||
e6bb4c9c | 1203 | static void iwl_trans_pcie_free(struct iwl_priv *priv) |
34c1b7ba | 1204 | { |
0c325769 EG |
1205 | free_irq(priv->bus->irq, trans(priv)); |
1206 | iwl_free_isr_ict(trans(priv)); | |
e6bb4c9c EG |
1207 | kfree(trans(priv)); |
1208 | trans(priv) = NULL; | |
34c1b7ba EG |
1209 | } |
1210 | ||
57210f7c EG |
1211 | #ifdef CONFIG_PM |
1212 | ||
1213 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) | |
1214 | { | |
1215 | /* | |
1216 | * This function is called when system goes into suspend state | |
1217 | * mac80211 will call iwl_mac_stop() from the mac80211 suspend function | |
1218 | * first but since iwl_mac_stop() has no knowledge of who the caller is, | |
1219 | * it will not call apm_ops.stop() to stop the DMA operation. | |
1220 | * Calling apm_ops.stop here to make sure we stop the DMA. | |
1221 | * | |
1222 | * But of course ... if we have configured WoWLAN then we did other | |
1223 | * things already :-) | |
1224 | */ | |
1225 | if (!trans->shrd->wowlan) | |
1226 | iwl_apm_stop(priv(trans)); | |
1227 | ||
1228 | return 0; | |
1229 | } | |
1230 | ||
1231 | static int iwl_trans_pcie_resume(struct iwl_trans *trans) | |
1232 | { | |
1233 | bool hw_rfkill = false; | |
1234 | ||
0c325769 | 1235 | iwl_enable_interrupts(trans); |
57210f7c EG |
1236 | |
1237 | if (!(iwl_read32(priv(trans), CSR_GP_CNTRL) & | |
1238 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
1239 | hw_rfkill = true; | |
1240 | ||
1241 | if (hw_rfkill) | |
1242 | set_bit(STATUS_RF_KILL_HW, &trans->shrd->status); | |
1243 | else | |
1244 | clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status); | |
1245 | ||
1246 | wiphy_rfkill_set_hw_state(priv(trans)->hw->wiphy, hw_rfkill); | |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | #else /* CONFIG_PM */ | |
1251 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) | |
1252 | { return 0; } | |
1253 | ||
1254 | static int iwl_trans_pcie_resume(struct iwl_trans *trans) | |
1255 | { return 0; } | |
1256 | ||
1257 | #endif /* CONFIG_PM */ | |
1258 | ||
e6bb4c9c | 1259 | const struct iwl_trans_ops trans_ops_pcie; |
e419d62d | 1260 | |
e6bb4c9c EG |
1261 | static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd) |
1262 | { | |
1263 | struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) + | |
1264 | sizeof(struct iwl_trans_pcie), | |
1265 | GFP_KERNEL); | |
1266 | if (iwl_trans) { | |
5a878bf6 EG |
1267 | struct iwl_trans_pcie *trans_pcie = |
1268 | IWL_TRANS_GET_PCIE_TRANS(iwl_trans); | |
e6bb4c9c EG |
1269 | iwl_trans->ops = &trans_ops_pcie; |
1270 | iwl_trans->shrd = shrd; | |
5a878bf6 | 1271 | trans_pcie->trans = iwl_trans; |
e6bb4c9c | 1272 | } |
ab6cf8e8 | 1273 | |
e6bb4c9c EG |
1274 | return iwl_trans; |
1275 | } | |
47c1b496 | 1276 | |
87e5666c EG |
1277 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1278 | /* create and remove of files */ | |
1279 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 1280 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c EG |
1281 | &iwl_dbgfs_##name##_ops)) \ |
1282 | return -ENOMEM; \ | |
1283 | } while (0) | |
1284 | ||
1285 | /* file operation */ | |
1286 | #define DEBUGFS_READ_FUNC(name) \ | |
1287 | static ssize_t iwl_dbgfs_##name##_read(struct file *file, \ | |
1288 | char __user *user_buf, \ | |
1289 | size_t count, loff_t *ppos); | |
1290 | ||
1291 | #define DEBUGFS_WRITE_FUNC(name) \ | |
1292 | static ssize_t iwl_dbgfs_##name##_write(struct file *file, \ | |
1293 | const char __user *user_buf, \ | |
1294 | size_t count, loff_t *ppos); | |
1295 | ||
1296 | ||
1297 | static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file) | |
1298 | { | |
1299 | file->private_data = inode->i_private; | |
1300 | return 0; | |
1301 | } | |
1302 | ||
1303 | #define DEBUGFS_READ_FILE_OPS(name) \ | |
1304 | DEBUGFS_READ_FUNC(name); \ | |
1305 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1306 | .read = iwl_dbgfs_##name##_read, \ | |
1307 | .open = iwl_dbgfs_open_file_generic, \ | |
1308 | .llseek = generic_file_llseek, \ | |
1309 | }; | |
1310 | ||
1311 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ | |
1312 | DEBUGFS_READ_FUNC(name); \ | |
1313 | DEBUGFS_WRITE_FUNC(name); \ | |
1314 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1315 | .write = iwl_dbgfs_##name##_write, \ | |
1316 | .read = iwl_dbgfs_##name##_read, \ | |
1317 | .open = iwl_dbgfs_open_file_generic, \ | |
1318 | .llseek = generic_file_llseek, \ | |
1319 | }; | |
1320 | ||
1321 | static ssize_t iwl_dbgfs_traffic_log_read(struct file *file, | |
1322 | char __user *user_buf, | |
1323 | size_t count, loff_t *ppos) | |
1324 | { | |
5a878bf6 EG |
1325 | struct iwl_trans *trans = file->private_data; |
1326 | struct iwl_priv *priv = priv(trans); | |
87e5666c EG |
1327 | int pos = 0, ofs = 0; |
1328 | int cnt = 0, entry; | |
5a878bf6 EG |
1329 | struct iwl_trans_pcie *trans_pcie = |
1330 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
87e5666c EG |
1331 | struct iwl_tx_queue *txq; |
1332 | struct iwl_queue *q; | |
5a878bf6 | 1333 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
87e5666c EG |
1334 | char *buf; |
1335 | int bufsz = ((IWL_TRAFFIC_ENTRIES * IWL_TRAFFIC_ENTRY_SIZE * 64) * 2) + | |
1336 | (priv->cfg->base_params->num_of_queues * 32 * 8) + 400; | |
1337 | const u8 *ptr; | |
1338 | ssize_t ret; | |
1339 | ||
1340 | if (!priv->txq) { | |
5a878bf6 | 1341 | IWL_ERR(trans, "txq not ready\n"); |
87e5666c EG |
1342 | return -EAGAIN; |
1343 | } | |
1344 | buf = kzalloc(bufsz, GFP_KERNEL); | |
1345 | if (!buf) { | |
5a878bf6 | 1346 | IWL_ERR(trans, "Can not allocate buffer\n"); |
87e5666c EG |
1347 | return -ENOMEM; |
1348 | } | |
1349 | pos += scnprintf(buf + pos, bufsz - pos, "Tx Queue\n"); | |
5a878bf6 | 1350 | for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) { |
87e5666c EG |
1351 | txq = &priv->txq[cnt]; |
1352 | q = &txq->q; | |
1353 | pos += scnprintf(buf + pos, bufsz - pos, | |
1354 | "q[%d]: read_ptr: %u, write_ptr: %u\n", | |
1355 | cnt, q->read_ptr, q->write_ptr); | |
1356 | } | |
1357 | if (priv->tx_traffic && | |
5a878bf6 | 1358 | (iwl_get_debug_level(trans->shrd) & IWL_DL_TX)) { |
87e5666c EG |
1359 | ptr = priv->tx_traffic; |
1360 | pos += scnprintf(buf + pos, bufsz - pos, | |
5a878bf6 | 1361 | "Tx Traffic idx: %u\n", priv->tx_traffic_idx); |
87e5666c EG |
1362 | for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) { |
1363 | for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16; | |
1364 | entry++, ofs += 16) { | |
1365 | pos += scnprintf(buf + pos, bufsz - pos, | |
1366 | "0x%.4x ", ofs); | |
1367 | hex_dump_to_buffer(ptr + ofs, 16, 16, 2, | |
1368 | buf + pos, bufsz - pos, 0); | |
1369 | pos += strlen(buf + pos); | |
1370 | if (bufsz - pos > 0) | |
1371 | buf[pos++] = '\n'; | |
1372 | } | |
1373 | } | |
1374 | } | |
1375 | ||
1376 | pos += scnprintf(buf + pos, bufsz - pos, "Rx Queue\n"); | |
1377 | pos += scnprintf(buf + pos, bufsz - pos, | |
1378 | "read: %u, write: %u\n", | |
1379 | rxq->read, rxq->write); | |
1380 | ||
1381 | if (priv->rx_traffic && | |
5a878bf6 | 1382 | (iwl_get_debug_level(trans->shrd) & IWL_DL_RX)) { |
87e5666c EG |
1383 | ptr = priv->rx_traffic; |
1384 | pos += scnprintf(buf + pos, bufsz - pos, | |
5a878bf6 | 1385 | "Rx Traffic idx: %u\n", priv->rx_traffic_idx); |
87e5666c EG |
1386 | for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) { |
1387 | for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16; | |
1388 | entry++, ofs += 16) { | |
1389 | pos += scnprintf(buf + pos, bufsz - pos, | |
1390 | "0x%.4x ", ofs); | |
1391 | hex_dump_to_buffer(ptr + ofs, 16, 16, 2, | |
1392 | buf + pos, bufsz - pos, 0); | |
1393 | pos += strlen(buf + pos); | |
1394 | if (bufsz - pos > 0) | |
1395 | buf[pos++] = '\n'; | |
1396 | } | |
1397 | } | |
1398 | } | |
1399 | ||
1400 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1401 | kfree(buf); | |
1402 | return ret; | |
1403 | } | |
1404 | ||
1405 | static ssize_t iwl_dbgfs_traffic_log_write(struct file *file, | |
1406 | const char __user *user_buf, | |
1407 | size_t count, loff_t *ppos) | |
1408 | { | |
5a878bf6 | 1409 | struct iwl_trans *trans = file->private_data; |
87e5666c EG |
1410 | char buf[8]; |
1411 | int buf_size; | |
1412 | int traffic_log; | |
1413 | ||
1414 | memset(buf, 0, sizeof(buf)); | |
1415 | buf_size = min(count, sizeof(buf) - 1); | |
1416 | if (copy_from_user(buf, user_buf, buf_size)) | |
1417 | return -EFAULT; | |
1418 | if (sscanf(buf, "%d", &traffic_log) != 1) | |
1419 | return -EFAULT; | |
1420 | if (traffic_log == 0) | |
5a878bf6 | 1421 | iwl_reset_traffic_log(priv(trans)); |
87e5666c EG |
1422 | |
1423 | return count; | |
1424 | } | |
1425 | ||
1426 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, | |
1427 | char __user *user_buf, | |
1428 | size_t count, loff_t *ppos) { | |
1429 | ||
5a878bf6 EG |
1430 | struct iwl_trans *trans = file->private_data; |
1431 | struct iwl_priv *priv = priv(trans); | |
87e5666c EG |
1432 | struct iwl_tx_queue *txq; |
1433 | struct iwl_queue *q; | |
1434 | char *buf; | |
1435 | int pos = 0; | |
1436 | int cnt; | |
1437 | int ret; | |
1438 | const size_t bufsz = sizeof(char) * 64 * | |
1439 | priv->cfg->base_params->num_of_queues; | |
1440 | ||
1441 | if (!priv->txq) { | |
1442 | IWL_ERR(priv, "txq not ready\n"); | |
1443 | return -EAGAIN; | |
1444 | } | |
1445 | buf = kzalloc(bufsz, GFP_KERNEL); | |
1446 | if (!buf) | |
1447 | return -ENOMEM; | |
1448 | ||
5a878bf6 | 1449 | for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) { |
87e5666c EG |
1450 | txq = &priv->txq[cnt]; |
1451 | q = &txq->q; | |
1452 | pos += scnprintf(buf + pos, bufsz - pos, | |
1453 | "hwq %.2d: read=%u write=%u stop=%d" | |
1454 | " swq_id=%#.2x (ac %d/hwq %d)\n", | |
1455 | cnt, q->read_ptr, q->write_ptr, | |
1456 | !!test_bit(cnt, priv->queue_stopped), | |
1457 | txq->swq_id, txq->swq_id & 3, | |
1458 | (txq->swq_id >> 2) & 0x1f); | |
1459 | if (cnt >= 4) | |
1460 | continue; | |
1461 | /* for the ACs, display the stop count too */ | |
1462 | pos += scnprintf(buf + pos, bufsz - pos, | |
1463 | " stop-count: %d\n", | |
1464 | atomic_read(&priv->queue_stop_count[cnt])); | |
1465 | } | |
1466 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1467 | kfree(buf); | |
1468 | return ret; | |
1469 | } | |
1470 | ||
1471 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
1472 | char __user *user_buf, | |
1473 | size_t count, loff_t *ppos) { | |
5a878bf6 EG |
1474 | struct iwl_trans *trans = file->private_data; |
1475 | struct iwl_trans_pcie *trans_pcie = | |
1476 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1477 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
87e5666c EG |
1478 | char buf[256]; |
1479 | int pos = 0; | |
1480 | const size_t bufsz = sizeof(buf); | |
1481 | ||
1482 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1483 | rxq->read); | |
1484 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1485 | rxq->write); | |
1486 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", | |
1487 | rxq->free_count); | |
1488 | if (rxq->rb_stts) { | |
1489 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1490 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1491 | } else { | |
1492 | pos += scnprintf(buf + pos, bufsz - pos, | |
1493 | "closed_rb_num: Not Allocated\n"); | |
1494 | } | |
1495 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1496 | } | |
1497 | ||
7ff94706 EG |
1498 | static ssize_t iwl_dbgfs_log_event_read(struct file *file, |
1499 | char __user *user_buf, | |
1500 | size_t count, loff_t *ppos) | |
1501 | { | |
1502 | struct iwl_trans *trans = file->private_data; | |
1503 | char *buf; | |
1504 | int pos = 0; | |
1505 | ssize_t ret = -ENOMEM; | |
1506 | ||
1507 | ret = pos = iwl_dump_nic_event_log(priv(trans), true, &buf, true); | |
1508 | if (buf) { | |
1509 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1510 | kfree(buf); | |
1511 | } | |
1512 | return ret; | |
1513 | } | |
1514 | ||
1515 | static ssize_t iwl_dbgfs_log_event_write(struct file *file, | |
1516 | const char __user *user_buf, | |
1517 | size_t count, loff_t *ppos) | |
1518 | { | |
1519 | struct iwl_trans *trans = file->private_data; | |
1520 | u32 event_log_flag; | |
1521 | char buf[8]; | |
1522 | int buf_size; | |
1523 | ||
1524 | memset(buf, 0, sizeof(buf)); | |
1525 | buf_size = min(count, sizeof(buf) - 1); | |
1526 | if (copy_from_user(buf, user_buf, buf_size)) | |
1527 | return -EFAULT; | |
1528 | if (sscanf(buf, "%d", &event_log_flag) != 1) | |
1529 | return -EFAULT; | |
1530 | if (event_log_flag == 1) | |
1531 | iwl_dump_nic_event_log(priv(trans), true, NULL, false); | |
1532 | ||
1533 | return count; | |
1534 | } | |
1535 | ||
1f7b6172 EG |
1536 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
1537 | char __user *user_buf, | |
1538 | size_t count, loff_t *ppos) { | |
1539 | ||
1540 | struct iwl_trans *trans = file->private_data; | |
1541 | struct iwl_trans_pcie *trans_pcie = | |
1542 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1543 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
1544 | ||
1545 | int pos = 0; | |
1546 | char *buf; | |
1547 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
1548 | ssize_t ret; | |
1549 | ||
1550 | buf = kzalloc(bufsz, GFP_KERNEL); | |
1551 | if (!buf) { | |
1552 | IWL_ERR(trans, "Can not allocate Buffer\n"); | |
1553 | return -ENOMEM; | |
1554 | } | |
1555 | ||
1556 | pos += scnprintf(buf + pos, bufsz - pos, | |
1557 | "Interrupt Statistics Report:\n"); | |
1558 | ||
1559 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
1560 | isr_stats->hw); | |
1561 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
1562 | isr_stats->sw); | |
1563 | if (isr_stats->sw || isr_stats->hw) { | |
1564 | pos += scnprintf(buf + pos, bufsz - pos, | |
1565 | "\tLast Restarting Code: 0x%X\n", | |
1566 | isr_stats->err_code); | |
1567 | } | |
1568 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1569 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
1570 | isr_stats->sch); | |
1571 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
1572 | isr_stats->alive); | |
1573 | #endif | |
1574 | pos += scnprintf(buf + pos, bufsz - pos, | |
1575 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
1576 | ||
1577 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
1578 | isr_stats->ctkill); | |
1579 | ||
1580 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
1581 | isr_stats->wakeup); | |
1582 | ||
1583 | pos += scnprintf(buf + pos, bufsz - pos, | |
1584 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
1585 | ||
1586 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
1587 | isr_stats->tx); | |
1588 | ||
1589 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
1590 | isr_stats->unhandled); | |
1591 | ||
1592 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1593 | kfree(buf); | |
1594 | return ret; | |
1595 | } | |
1596 | ||
1597 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
1598 | const char __user *user_buf, | |
1599 | size_t count, loff_t *ppos) | |
1600 | { | |
1601 | struct iwl_trans *trans = file->private_data; | |
1602 | struct iwl_trans_pcie *trans_pcie = | |
1603 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1604 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
1605 | ||
1606 | char buf[8]; | |
1607 | int buf_size; | |
1608 | u32 reset_flag; | |
1609 | ||
1610 | memset(buf, 0, sizeof(buf)); | |
1611 | buf_size = min(count, sizeof(buf) - 1); | |
1612 | if (copy_from_user(buf, user_buf, buf_size)) | |
1613 | return -EFAULT; | |
1614 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
1615 | return -EFAULT; | |
1616 | if (reset_flag == 0) | |
1617 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
1618 | ||
1619 | return count; | |
1620 | } | |
1621 | ||
87e5666c | 1622 | DEBUGFS_READ_WRITE_FILE_OPS(traffic_log); |
7ff94706 | 1623 | DEBUGFS_READ_WRITE_FILE_OPS(log_event); |
1f7b6172 | 1624 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
87e5666c EG |
1625 | DEBUGFS_READ_FILE_OPS(rx_queue); |
1626 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
1627 | ||
1628 | /* | |
1629 | * Create the debugfs files and directories | |
1630 | * | |
1631 | */ | |
1632 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
1633 | struct dentry *dir) | |
1634 | { | |
87e5666c EG |
1635 | DEBUGFS_ADD_FILE(traffic_log, dir, S_IWUSR | S_IRUSR); |
1636 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); | |
1637 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
7ff94706 | 1638 | DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR); |
1f7b6172 | 1639 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
87e5666c EG |
1640 | return 0; |
1641 | } | |
1642 | #else | |
1643 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
1644 | struct dentry *dir) | |
1645 | { return 0; } | |
1646 | ||
1647 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ | |
1648 | ||
e6bb4c9c EG |
1649 | const struct iwl_trans_ops trans_ops_pcie = { |
1650 | .alloc = iwl_trans_pcie_alloc, | |
1651 | .request_irq = iwl_trans_pcie_request_irq, | |
1652 | .start_device = iwl_trans_pcie_start_device, | |
1653 | .prepare_card_hw = iwl_trans_pcie_prepare_card_hw, | |
1654 | .stop_device = iwl_trans_pcie_stop_device, | |
48d42c42 | 1655 | |
e6bb4c9c | 1656 | .tx_start = iwl_trans_pcie_tx_start, |
48d42c42 | 1657 | |
e6bb4c9c EG |
1658 | .rx_free = iwl_trans_pcie_rx_free, |
1659 | .tx_free = iwl_trans_pcie_tx_free, | |
34c1b7ba | 1660 | |
e6bb4c9c EG |
1661 | .send_cmd = iwl_trans_pcie_send_cmd, |
1662 | .send_cmd_pdu = iwl_trans_pcie_send_cmd_pdu, | |
c85eb619 | 1663 | |
e6bb4c9c EG |
1664 | .get_tx_cmd = iwl_trans_pcie_get_tx_cmd, |
1665 | .tx = iwl_trans_pcie_tx, | |
a0eaad71 | 1666 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 1667 | |
e6bb4c9c EG |
1668 | .txq_agg_disable = iwl_trans_pcie_txq_agg_disable, |
1669 | .txq_agg_setup = iwl_trans_pcie_txq_agg_setup, | |
34c1b7ba | 1670 | |
e6bb4c9c | 1671 | .kick_nic = iwl_trans_pcie_kick_nic, |
1e89cbac | 1672 | |
0c325769 | 1673 | .disable_sync_irq = iwl_trans_pcie_disable_sync_irq, |
e6bb4c9c | 1674 | .free = iwl_trans_pcie_free, |
87e5666c EG |
1675 | |
1676 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, | |
57210f7c EG |
1677 | .suspend = iwl_trans_pcie_suspend, |
1678 | .resume = iwl_trans_pcie_resume, | |
e6bb4c9c | 1679 | }; |
ab697a9f | 1680 |