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iwlagn: move iwl_suspend / iwl_resume to the transport layer
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
e6bb4c9c 63#include <linux/interrupt.h>
87e5666c 64#include <linux/debugfs.h>
e6bb4c9c 65
a0f6b0a2 66#include "iwl-dev.h"
c85eb619 67#include "iwl-trans.h"
02aca585
EG		 68#include "iwl-core.h"
69#include "iwl-helpers.h"
ab697a9f 70#include "iwl-trans-int-pcie.h"
02aca585
EG		 71/*TODO remove uneeded includes when the transport layer tx_free will be here */
72#include "iwl-agn.h"
e419d62d 73#include "iwl-core.h"
48f20d35 74#include "iwl-shared.h"
c85eb619 75
5a878bf6 76static int iwl_trans_rx_alloc(struct iwl_trans *trans)
c85eb619 77{
5a878bf6
EG		 78 struct iwl_trans_pcie *trans_pcie =
79 IWL_TRANS_GET_PCIE_TRANS(trans);
80 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
81 struct device *dev = bus(trans)->dev;
c85eb619 82
5a878bf6 83 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
c85eb619
EG		 84
85 spin_lock_init(&rxq->lock);
86 INIT_LIST_HEAD(&rxq->rx_free);
87 INIT_LIST_HEAD(&rxq->rx_used);
88
89 if (WARN_ON(rxq->bd || rxq->rb_stts))
90 return -EINVAL;
91
92 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
a0f6b0a2
EG		 93 rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
94 &rxq->bd_dma, GFP_KERNEL);
c85eb619
EG		 95 if (!rxq->bd)
96 goto err_bd;
a0f6b0a2 97 memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
c85eb619
EG		 98
99 /*Allocate the driver's pointer to receive buffer status */
100 rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
101 &rxq->rb_stts_dma, GFP_KERNEL);
102 if (!rxq->rb_stts)
103 goto err_rb_stts;
104 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
105
106 return 0;
107
108err_rb_stts:
a0f6b0a2
EG		 109 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
110 rxq->bd, rxq->bd_dma);
c85eb619
EG		 111 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
112 rxq->bd = NULL;
113err_bd:
114 return -ENOMEM;
115}
116
5a878bf6 117static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
c85eb619 118{
5a878bf6
EG		 119 struct iwl_trans_pcie *trans_pcie =
120 IWL_TRANS_GET_PCIE_TRANS(trans);
121 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
a0f6b0a2 122 int i;
c85eb619
EG		 123
124 /* Fill the rx_used queue with _all_ of the Rx buffers */
125 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
126 /* In the reset function, these buffers may have been allocated
127 * to an SKB, so we need to unmap and free potential storage */
128 if (rxq->pool[i].page != NULL) {
5a878bf6
EG		 129 dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
130 PAGE_SIZE << hw_params(trans).rx_page_order,
c85eb619 131 DMA_FROM_DEVICE);
5a878bf6 132 __iwl_free_pages(priv(trans), rxq->pool[i].page);
c85eb619
EG		 133 rxq->pool[i].page = NULL;
134 }
135 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
136 }
a0f6b0a2
EG		 137}
138
ab697a9f
EG		 139static void iwl_trans_rx_hw_init(struct iwl_priv *priv,
140 struct iwl_rx_queue *rxq)
141{
142 u32 rb_size;
143 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
144 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
145
146 rb_timeout = RX_RB_TIMEOUT;
147
148 if (iwlagn_mod_params.amsdu_size_8K)
149 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
150 else
151 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
152
153 /* Stop Rx DMA */
154 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
155
156 /* Reset driver's Rx queue write index */
157 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
158
159 /* Tell device where to find RBD circular buffer in DRAM */
160 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
161 (u32)(rxq->bd_dma >> 8));
162
163 /* Tell device where in DRAM to update its Rx status */
164 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
165 rxq->rb_stts_dma >> 4);
166
167 /* Enable Rx DMA
168 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
169 * the credit mechanism in 5000 HW RX FIFO
170 * Direct rx interrupts to hosts
171 * Rx buffer size 4 or 8k
172 * RB timeout 0x10
173 * 256 RBDs
174 */
175 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
176 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
177 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
178 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
179 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
180 rb_size|
181 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
182 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
183
184 /* Set interrupt coalescing timer to default (2048 usecs) */
185 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
186}
187
5a878bf6 188static int iwl_rx_init(struct iwl_trans *trans)
a0f6b0a2 189{
5a878bf6
EG		 190 struct iwl_trans_pcie *trans_pcie =
191 IWL_TRANS_GET_PCIE_TRANS(trans);
192 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
193
a0f6b0a2
EG		 194 int i, err;
195 unsigned long flags;
196
197 if (!rxq->bd) {
5a878bf6 198 err = iwl_trans_rx_alloc(trans);
a0f6b0a2
EG		 199 if (err)
200 return err;
201 }
202
203 spin_lock_irqsave(&rxq->lock, flags);
204 INIT_LIST_HEAD(&rxq->rx_free);
205 INIT_LIST_HEAD(&rxq->rx_used);
206
5a878bf6 207 iwl_trans_rxq_free_rx_bufs(trans);
c85eb619
EG		 208
209 for (i = 0; i < RX_QUEUE_SIZE; i++)
210 rxq->queue[i] = NULL;
211
212 /* Set us so that we have processed and used all buffers, but have
213 * not restocked the Rx queue with fresh buffers */
214 rxq->read = rxq->write = 0;
215 rxq->write_actual = 0;
216 rxq->free_count = 0;
217 spin_unlock_irqrestore(&rxq->lock, flags);
218
5a878bf6 219 iwlagn_rx_replenish(trans);
ab697a9f 220
5a878bf6 221 iwl_trans_rx_hw_init(priv(trans), rxq);
ab697a9f 222
5a878bf6 223 spin_lock_irqsave(&trans->shrd->lock, flags);
ab697a9f 224 rxq->need_update = 1;
5a878bf6
EG		 225 iwl_rx_queue_update_write_ptr(trans, rxq);
226 spin_unlock_irqrestore(&trans->shrd->lock, flags);
ab697a9f 227
c85eb619
EG		 228 return 0;
229}
230
5a878bf6 231static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
a0f6b0a2 232{
5a878bf6
EG		 233 struct iwl_trans_pcie *trans_pcie =
234 IWL_TRANS_GET_PCIE_TRANS(trans);
235 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
236
a0f6b0a2
EG		 237 unsigned long flags;
238
239 /*if rxq->bd is NULL, it means that nothing has been allocated,
240 * exit now */
241 if (!rxq->bd) {
5a878bf6 242 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
a0f6b0a2
EG		 243 return;
244 }
245
246 spin_lock_irqsave(&rxq->lock, flags);
5a878bf6 247 iwl_trans_rxq_free_rx_bufs(trans);
a0f6b0a2
EG		 248 spin_unlock_irqrestore(&rxq->lock, flags);
249
5a878bf6 250 dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
a0f6b0a2
EG		 251 rxq->bd, rxq->bd_dma);
252 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
253 rxq->bd = NULL;
254
255 if (rxq->rb_stts)
5a878bf6 256 dma_free_coherent(bus(trans)->dev,
a0f6b0a2
EG		 257 sizeof(struct iwl_rb_status),
258 rxq->rb_stts, rxq->rb_stts_dma);
259 else
5a878bf6 260 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
a0f6b0a2
EG		 261 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
262 rxq->rb_stts = NULL;
263}
264
c2c52e8b
EG		 265static int iwl_trans_rx_stop(struct iwl_priv *priv)
266{
267
268 /* stop Rx DMA */
269 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
270 return iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
271 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
272}
273
02aca585
EG		 274static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
275 struct iwl_dma_ptr *ptr, size_t size)
276{
277 if (WARN_ON(ptr->addr))
278 return -EINVAL;
279
d5934110 280 ptr->addr = dma_alloc_coherent(priv->bus->dev, size,
02aca585
EG		 281 &ptr->dma, GFP_KERNEL);
282 if (!ptr->addr)
283 return -ENOMEM;
284 ptr->size = size;
285 return 0;
286}
287
1359ca4f
EG		 288static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
289 struct iwl_dma_ptr *ptr)
290{
291 if (unlikely(!ptr->addr))
292 return;
293
d5934110 294 dma_free_coherent(priv->bus->dev, ptr->size, ptr->addr, ptr->dma);
1359ca4f
EG		 295 memset(ptr, 0, sizeof(*ptr));
296}
297
02aca585
EG		 298static int iwl_trans_txq_alloc(struct iwl_priv *priv, struct iwl_tx_queue *txq,
299 int slots_num, u32 txq_id)
300{
d6189124 301 size_t tfd_sz = hw_params(priv).tfd_size * TFD_QUEUE_SIZE_MAX;
02aca585
EG		 302 int i;
303
304 if (WARN_ON(txq->meta || txq->cmd || txq->txb || txq->tfds))
305 return -EINVAL;
306
1359ca4f
EG		 307 txq->q.n_window = slots_num;
308
02aca585
EG		 309 txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num,
310 GFP_KERNEL);
311 txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num,
312 GFP_KERNEL);
313
314 if (!txq->meta || !txq->cmd)
315 goto error;
316
317 for (i = 0; i < slots_num; i++) {
318 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
319 GFP_KERNEL);
320 if (!txq->cmd[i])
321 goto error;
322 }
323
324 /* Alloc driver data array and TFD circular buffer */
325 /* Driver private data, only for Tx (not command) queues,
326 * not shared with device. */
cefeaa5f 327 if (txq_id != priv->shrd->cmd_queue) {
02aca585
EG		 328 txq->txb = kzalloc(sizeof(txq->txb[0]) *
329 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
330 if (!txq->txb) {
331 IWL_ERR(priv, "kmalloc for auxiliary BD "
332 "structures failed\n");
333 goto error;
334 }
335 } else {
336 txq->txb = NULL;
337 }
338
339 /* Circular buffer of transmit frame descriptors (TFDs),
340 * shared with device */
d5934110 341 txq->tfds = dma_alloc_coherent(priv->bus->dev, tfd_sz, &txq->q.dma_addr,
02aca585
EG		 342 GFP_KERNEL);
343 if (!txq->tfds) {
344 IWL_ERR(priv, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
345 goto error;
346 }
347 txq->q.id = txq_id;
348
349 return 0;
350error:
351 kfree(txq->txb);
352 txq->txb = NULL;
353 /* since txq->cmd has been zeroed,
354 * all non allocated cmd[i] will be NULL */
355 if (txq->cmd)
356 for (i = 0; i < slots_num; i++)
357 kfree(txq->cmd[i]);
358 kfree(txq->meta);
359 kfree(txq->cmd);
360 txq->meta = NULL;
361 txq->cmd = NULL;
362
363 return -ENOMEM;
364
365}
366
367static int iwl_trans_txq_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
368 int slots_num, u32 txq_id)
369{
370 int ret;
371
372 txq->need_update = 0;
373 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
374
375 /*
376 * For the default queues 0-3, set up the swq_id
377 * already -- all others need to get one later
378 * (if they need one at all).
379 */
380 if (txq_id < 4)
381 iwl_set_swq_id(txq, txq_id, txq_id);
382
383 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
384 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
385 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
386
387 /* Initialize queue's high/low-water marks, and head/tail indexes */
388 ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
389 txq_id);
390 if (ret)
391 return ret;
392
393 /*
394 * Tell nic where to find circular buffer of Tx Frame Descriptors for
395 * given Tx queue, and enable the DMA channel used for that queue.
396 * Circular buffer (TFD queue in DRAM) physical base address */
397 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
398 txq->q.dma_addr >> 8);
399
400 return 0;
401}
402
c170b867
EG		 403/**
404 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
405 */
406static void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
407{
408 struct iwl_tx_queue *txq = &priv->txq[txq_id];
409 struct iwl_queue *q = &txq->q;
410
411 if (!q->n_bd)
412 return;
413
414 while (q->write_ptr != q->read_ptr) {
415 /* The read_ptr needs to bound by q->n_window */
416 iwlagn_txq_free_tfd(priv, txq, get_cmd_index(q, q->read_ptr));
417 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
418 }
419}
420
1359ca4f
EG		 421/**
422 * iwl_tx_queue_free - Deallocate DMA queue.
423 * @txq: Transmit queue to deallocate.
424 *
425 * Empty queue by removing and destroying all BD's.
426 * Free all buffers.
427 * 0-fill, but do not free "txq" descriptor structure.
428 */
429static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
430{
431 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d5934110 432 struct device *dev = priv->bus->dev;
1359ca4f
EG		 433 int i;
434 if (WARN_ON(!txq))
435 return;
436
437 iwl_tx_queue_unmap(priv, txq_id);
438
439 /* De-alloc array of command/tx buffers */
440 for (i = 0; i < txq->q.n_window; i++)
441 kfree(txq->cmd[i]);
442
443 /* De-alloc circular buffer of TFDs */
444 if (txq->q.n_bd) {
d6189124 445 dma_free_coherent(dev, hw_params(priv).tfd_size *
1359ca4f
EG		 446 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
447 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
448 }
449
450 /* De-alloc array of per-TFD driver data */
451 kfree(txq->txb);
452 txq->txb = NULL;
453
454 /* deallocate arrays */
455 kfree(txq->cmd);
456 kfree(txq->meta);
457 txq->cmd = NULL;
458 txq->meta = NULL;
459
460 /* 0-fill queue descriptor structure */
461 memset(txq, 0, sizeof(*txq));
462}
463
464/**
465 * iwl_trans_tx_free - Free TXQ Context
466 *
467 * Destroy all TX DMA queues and structures
468 */
e6bb4c9c 469static void iwl_trans_pcie_tx_free(struct iwl_priv *priv)
1359ca4f
EG		 470{
471 int txq_id;
472
473 /* Tx queues */
474 if (priv->txq) {
d6189124
EG		 475 for (txq_id = 0;
476 txq_id < hw_params(priv).max_txq_num; txq_id++)
1359ca4f
EG		 477 iwl_tx_queue_free(priv, txq_id);
478 }
479
480 kfree(priv->txq);
481 priv->txq = NULL;
482
483 iwlagn_free_dma_ptr(priv, &priv->kw);
484
485 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
486}
487
02aca585
EG		 488/**
489 * iwl_trans_tx_alloc - allocate TX context
490 * Allocate all Tx DMA structures and initialize them
491 *
492 * @param priv
493 * @return error code
494 */
495static int iwl_trans_tx_alloc(struct iwl_priv *priv)
496{
497 int ret;
498 int txq_id, slots_num;
499
500 /*It is not allowed to alloc twice, so warn when this happens.
501 * We cannot rely on the previous allocation, so free and fail */
502 if (WARN_ON(priv->txq)) {
503 ret = -EINVAL;
504 goto error;
505 }
506
507 ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
d6189124 508 hw_params(priv).scd_bc_tbls_size);
02aca585
EG		 509 if (ret) {
510 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
511 goto error;
512 }
513
514 /* Alloc keep-warm buffer */
515 ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
516 if (ret) {
517 IWL_ERR(priv, "Keep Warm allocation failed\n");
518 goto error;
519 }
520
521 priv->txq = kzalloc(sizeof(struct iwl_tx_queue) *
522 priv->cfg->base_params->num_of_queues, GFP_KERNEL);
523 if (!priv->txq) {
524 IWL_ERR(priv, "Not enough memory for txq\n");
525 ret = ENOMEM;
526 goto error;
527 }
528
529 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
d6189124 530 for (txq_id = 0; txq_id < hw_params(priv).max_txq_num; txq_id++) {
cefeaa5f 531 slots_num = (txq_id == priv->shrd->cmd_queue) ?
02aca585
EG		 532 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
533 ret = iwl_trans_txq_alloc(priv, &priv->txq[txq_id], slots_num,
534 txq_id);
535 if (ret) {
536 IWL_ERR(priv, "Tx %d queue alloc failed\n", txq_id);
537 goto error;
538 }
539 }
540
541 return 0;
542
543error:
e6bb4c9c 544 iwl_trans_tx_free(trans(priv));
02aca585
EG		 545
546 return ret;
547}
392f8b78 548static int iwl_tx_init(struct iwl_priv *priv)
02aca585
EG		 549{
550 int ret;
551 int txq_id, slots_num;
552 unsigned long flags;
553 bool alloc = false;
554
555 if (!priv->txq) {
556 ret = iwl_trans_tx_alloc(priv);
557 if (ret)
558 goto error;
559 alloc = true;
560 }
561
10b15e6f 562 spin_lock_irqsave(&priv->shrd->lock, flags);
02aca585
EG		 563
564 /* Turn off all Tx DMA fifos */
b3c2ce13 565 iwl_write_prph(priv, SCD_TXFACT, 0);
02aca585
EG		 566
567 /* Tell NIC where to find the "keep warm" buffer */
568 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
569
10b15e6f 570 spin_unlock_irqrestore(&priv->shrd->lock, flags);
02aca585
EG		 571
572 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
d6189124 573 for (txq_id = 0; txq_id < hw_params(priv).max_txq_num; txq_id++) {
cefeaa5f 574 slots_num = (txq_id == priv->shrd->cmd_queue) ?
02aca585
EG		 575 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
576 ret = iwl_trans_txq_init(priv, &priv->txq[txq_id], slots_num,
577 txq_id);
578 if (ret) {
579 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
580 goto error;
581 }
582 }
583
584 return 0;
585error:
586 /*Upon error, free only if we allocated something */
587 if (alloc)
e6bb4c9c 588 iwl_trans_tx_free(trans(priv));
02aca585
EG		 589 return ret;
590}
591
392f8b78
EG		 592static void iwl_set_pwr_vmain(struct iwl_priv *priv)
593{
594/*
595 * (for documentation purposes)
596 * to set power to V_AUX, do:
597
598 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
599 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
600 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
601 ~APMG_PS_CTRL_MSK_PWR_SRC);
602 */
603
604 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
605 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
606 ~APMG_PS_CTRL_MSK_PWR_SRC);
607}
608
609static int iwl_nic_init(struct iwl_priv *priv)
610{
611 unsigned long flags;
612
613 /* nic_init */
10b15e6f 614 spin_lock_irqsave(&priv->shrd->lock, flags);
392f8b78
EG		 615 iwl_apm_init(priv);
616
617 /* Set interrupt coalescing calibration timer to default (512 usecs) */
618 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
619
10b15e6f 620 spin_unlock_irqrestore(&priv->shrd->lock, flags);
392f8b78
EG		 621
622 iwl_set_pwr_vmain(priv);
623
624 priv->cfg->lib->nic_config(priv);
625
626 /* Allocate the RX queue, or reset if it is already allocated */
5a878bf6 627 iwl_rx_init(trans(priv));
392f8b78
EG		 628
629 /* Allocate or reset and init all Tx and Command queues */
630 if (iwl_tx_init(priv))
631 return -ENOMEM;
632
633 if (priv->cfg->base_params->shadow_reg_enable) {
634 /* enable shadow regs in HW */
635 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
636 0x800FFFFF);
637 }
638
63013ae3 639 set_bit(STATUS_INIT, &priv->shrd->status);
392f8b78
EG		 640
641 return 0;
642}
643
644#define HW_READY_TIMEOUT (50)
645
646/* Note: returns poll_bit return value, which is >= 0 if success */
647static int iwl_set_hw_ready(struct iwl_priv *priv)
648{
649 int ret;
650
651 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
652 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
653
654 /* See if we got it */
655 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
656 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
657 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
658 HW_READY_TIMEOUT);
659
660 IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : "");
661 return ret;
662}
663
664/* Note: returns standard 0/-ERROR code */
e6bb4c9c 665static int iwl_trans_pcie_prepare_card_hw(struct iwl_priv *priv)
392f8b78
EG		 666{
667 int ret;
668
0286cee0 669 IWL_DEBUG_INFO(priv, "iwl_trans_prepare_card_hw enter\n");
392f8b78
EG		 670
671 ret = iwl_set_hw_ready(priv);
672 if (ret >= 0)
673 return 0;
674
675 /* If HW is not ready, prepare the conditions to check again */
676 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
677 CSR_HW_IF_CONFIG_REG_PREPARE);
678
679 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
680 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
681 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
682
683 if (ret < 0)
684 return ret;
685
686 /* HW should be ready by now, check again. */
687 ret = iwl_set_hw_ready(priv);
688 if (ret >= 0)
689 return 0;
690 return ret;
691}
692
e6bb4c9c 693static int iwl_trans_pcie_start_device(struct iwl_priv *priv)
392f8b78
EG		 694{
695 int ret;
696
697 priv->ucode_owner = IWL_OWNERSHIP_DRIVER;
698
699 if ((priv->cfg->sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
e6bb4c9c 700 iwl_trans_pcie_prepare_card_hw(priv)) {
392f8b78
EG		 701 IWL_WARN(priv, "Exit HW not ready\n");
702 return -EIO;
703 }
704
705 /* If platform's RF_KILL switch is NOT set to KILL */
706 if (iwl_read32(priv, CSR_GP_CNTRL) &
707 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
63013ae3 708 clear_bit(STATUS_RF_KILL_HW, &priv->shrd->status);
392f8b78 709 else
63013ae3 710 set_bit(STATUS_RF_KILL_HW, &priv->shrd->status);
392f8b78
EG		 711
712 if (iwl_is_rfkill(priv)) {
713 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
714 iwl_enable_interrupts(priv);
715 return -ERFKILL;
716 }
717
718 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
719
720 ret = iwl_nic_init(priv);
721 if (ret) {
722 IWL_ERR(priv, "Unable to init nic\n");
723 return ret;
724 }
725
726 /* make sure rfkill handshake bits are cleared */
727 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
728 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
729 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
730
731 /* clear (again), then enable host interrupts */
732 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
733 iwl_enable_interrupts(priv);
734
735 /* really make sure rfkill handshake bits are cleared */
736 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
737 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
738
739 return 0;
740}
741
b3c2ce13
EG		 742/*
743 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
10b15e6f 744 * must be called under priv->shrd->lock and mac access
b3c2ce13
EG		 745 */
746static void iwl_trans_txq_set_sched(struct iwl_priv *priv, u32 mask)
747{
748 iwl_write_prph(priv, SCD_TXFACT, mask);
749}
750
751#define IWL_AC_UNSET -1
752
753struct queue_to_fifo_ac {
754 s8 fifo, ac;
755};
756
757static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
758 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
759 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
760 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
761 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
762 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
763 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
764 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
765 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
766 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
767 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
72c04ce0 768 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
b3c2ce13
EG		 769};
770
771static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
772 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
773 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
774 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
775 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
776 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
777 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
778 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
779 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
780 { IWL_TX_FIFO_BE_IPAN, 2, },
781 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
72c04ce0 782 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
b3c2ce13 783};
e6bb4c9c 784static void iwl_trans_pcie_tx_start(struct iwl_priv *priv)
b3c2ce13
EG		 785{
786 const struct queue_to_fifo_ac *queue_to_fifo;
787 struct iwl_rxon_context *ctx;
788 u32 a;
789 unsigned long flags;
790 int i, chan;
791 u32 reg_val;
792
10b15e6f 793 spin_lock_irqsave(&priv->shrd->lock, flags);
b3c2ce13
EG		 794
795 priv->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR);
796 a = priv->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
797 /* reset conext data memory */
798 for (; a < priv->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
799 a += 4)
800 iwl_write_targ_mem(priv, a, 0);
801 /* reset tx status memory */
802 for (; a < priv->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
803 a += 4)
804 iwl_write_targ_mem(priv, a, 0);
805 for (; a < priv->scd_base_addr +
d6189124
EG		 806 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(priv).max_txq_num);
807 a += 4)
b3c2ce13
EG		 808 iwl_write_targ_mem(priv, a, 0);
809
810 iwl_write_prph(priv, SCD_DRAM_BASE_ADDR,
811 priv->scd_bc_tbls.dma >> 10);
812
813 /* Enable DMA channel */
814 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
815 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
816 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
817 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
818
819 /* Update FH chicken bits */
820 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
821 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
822 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
823
824 iwl_write_prph(priv, SCD_QUEUECHAIN_SEL,
825 SCD_QUEUECHAIN_SEL_ALL(priv));
826 iwl_write_prph(priv, SCD_AGGR_SEL, 0);
827
828 /* initiate the queues */
d6189124 829 for (i = 0; i < hw_params(priv).max_txq_num; i++) {
b3c2ce13
EG		 830 iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0);
831 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
832 iwl_write_targ_mem(priv, priv->scd_base_addr +
833 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
834 iwl_write_targ_mem(priv, priv->scd_base_addr +
835 SCD_CONTEXT_QUEUE_OFFSET(i) +
836 sizeof(u32),
837 ((SCD_WIN_SIZE <<
838 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
839 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
840 ((SCD_FRAME_LIMIT <<
841 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
842 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
843 }
844
845 iwl_write_prph(priv, SCD_INTERRUPT_MASK,
d6189124 846 IWL_MASK(0, hw_params(priv).max_txq_num));
b3c2ce13
EG		 847
848 /* Activate all Tx DMA/FIFO channels */
849 iwl_trans_txq_set_sched(priv, IWL_MASK(0, 7));
850
851 /* map queues to FIFOs */
852 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
853 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
854 else
855 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
856
cefeaa5f 857 iwl_trans_set_wr_ptrs(priv, priv->shrd->cmd_queue, 0);
b3c2ce13
EG		 858
859 /* make sure all queue are not stopped */
860 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
861 for (i = 0; i < 4; i++)
862 atomic_set(&priv->queue_stop_count[i], 0);
863 for_each_context(priv, ctx)
864 ctx->last_tx_rejected = false;
865
866 /* reset to 0 to enable all the queue first */
867 priv->txq_ctx_active_msk = 0;
868
72c04ce0
JB		 869 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) !=
870 IWLAGN_FIRST_AMPDU_QUEUE);
871 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) !=
872 IWLAGN_FIRST_AMPDU_QUEUE);
b3c2ce13 873
72c04ce0 874 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
b3c2ce13
EG		 875 int fifo = queue_to_fifo[i].fifo;
876 int ac = queue_to_fifo[i].ac;
877
878 iwl_txq_ctx_activate(priv, i);
879
880 if (fifo == IWL_TX_FIFO_UNUSED)
881 continue;
882
883 if (ac != IWL_AC_UNSET)
884 iwl_set_swq_id(&priv->txq[i], ac, i);
48d42c42 885 iwl_trans_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
b3c2ce13
EG		 886 }
887
10b15e6f 888 spin_unlock_irqrestore(&priv->shrd->lock, flags);
b3c2ce13
EG		 889
890 /* Enable L1-Active */
891 iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG,
892 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
893}
894
c170b867
EG		 895/**
896 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
897 */
898static int iwl_trans_tx_stop(struct iwl_priv *priv)
899{
900 int ch, txq_id;
901 unsigned long flags;
902
903 /* Turn off all Tx DMA fifos */
10b15e6f 904 spin_lock_irqsave(&priv->shrd->lock, flags);
c170b867 905
b3c2ce13 906 iwl_trans_txq_set_sched(priv, 0);
c170b867
EG		 907
908 /* Stop each Tx DMA channel, and wait for it to be idle */
02f6f659 909 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
c170b867
EG		 910 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
911 if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
912 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
913 1000))
914 IWL_ERR(priv, "Failing on timeout while stopping"
915 " DMA channel %d [0x%08x]", ch,
916 iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG));
917 }
10b15e6f 918 spin_unlock_irqrestore(&priv->shrd->lock, flags);
c170b867
EG		 919
920 if (!priv->txq) {
921 IWL_WARN(priv, "Stopping tx queues that aren't allocated...");
922 return 0;
923 }
924
925 /* Unmap DMA from host system and free skb's */
d6189124 926 for (txq_id = 0; txq_id < hw_params(priv).max_txq_num; txq_id++)
c170b867
EG		 927 iwl_tx_queue_unmap(priv, txq_id);
928
929 return 0;
930}
931
e6bb4c9c 932static void iwl_trans_pcie_stop_device(struct iwl_priv *priv)
ab6cf8e8
EG		 933{
934 unsigned long flags;
935
936 /* stop and reset the on-board processor */
937 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
938
939 /* tell the device to stop sending interrupts */
10b15e6f 940 spin_lock_irqsave(&priv->shrd->lock, flags);
ab6cf8e8 941 iwl_disable_interrupts(priv);
10b15e6f 942 spin_unlock_irqrestore(&priv->shrd->lock, flags);
e6bb4c9c 943 iwl_trans_sync_irq(trans(priv));
ab6cf8e8
EG		 944
945 /* device going down, Stop using ICT table */
946 iwl_disable_ict(priv);
947
948 /*
949 * If a HW restart happens during firmware loading,
950 * then the firmware loading might call this function
951 * and later it might be called again due to the
952 * restart. So don't process again if the device is
953 * already dead.
954 */
63013ae3 955 if (test_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status)) {
ab6cf8e8
EG		 956 iwl_trans_tx_stop(priv);
957 iwl_trans_rx_stop(priv);
958
959 /* Power-down device's busmaster DMA clocks */
960 iwl_write_prph(priv, APMG_CLK_DIS_REG,
961 APMG_CLK_VAL_DMA_CLK_RQT);
962 udelay(5);
963 }
964
965 /* Make sure (redundant) we've released our request to stay awake */
966 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
967
968 /* Stop the device, and put it in low power state */
969 iwl_apm_stop(priv);
970}
971
e6bb4c9c 972static struct iwl_tx_cmd *iwl_trans_pcie_get_tx_cmd(struct iwl_priv *priv,
47c1b496
EG		 973 int txq_id)
974{
975 struct iwl_tx_queue *txq = &priv->txq[txq_id];
976 struct iwl_queue *q = &txq->q;
977 struct iwl_device_cmd *dev_cmd;
978
979 if (unlikely(iwl_queue_space(q) < q->high_mark))
980 return NULL;
981
982 /*
983 * Set up the Tx-command (not MAC!) header.
984 * Store the chosen Tx queue and TFD index within the sequence field;
985 * after Tx, uCode's Tx response will return this value so driver can
986 * locate the frame within the tx queue and do post-tx processing.
987 */
988 dev_cmd = txq->cmd[q->write_ptr];
989 memset(dev_cmd, 0, sizeof(*dev_cmd));
990 dev_cmd->hdr.cmd = REPLY_TX;
991 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
992 INDEX_TO_SEQ(q->write_ptr)));
993 return &dev_cmd->cmd.tx;
994}
995
e6bb4c9c 996static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb,
47c1b496
EG		 997 struct iwl_tx_cmd *tx_cmd, int txq_id, __le16 fc, bool ampdu,
998 struct iwl_rxon_context *ctx)
999{
1000 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1001 struct iwl_queue *q = &txq->q;
1002 struct iwl_device_cmd *dev_cmd = txq->cmd[q->write_ptr];
1003 struct iwl_cmd_meta *out_meta;
1004
1005 dma_addr_t phys_addr = 0;
1006 dma_addr_t txcmd_phys;
1007 dma_addr_t scratch_phys;
1008 u16 len, firstlen, secondlen;
1009 u8 wait_write_ptr = 0;
1010 u8 hdr_len = ieee80211_hdrlen(fc);
1011
1012 /* Set up driver data for this TFD */
1013 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
1014 txq->txb[q->write_ptr].skb = skb;
1015 txq->txb[q->write_ptr].ctx = ctx;
1016
1017 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1018 out_meta = &txq->meta[q->write_ptr];
1019
1020 /*
1021 * Use the first empty entry in this queue's command buffer array
1022 * to contain the Tx command and MAC header concatenated together
1023 * (payload data will be in another buffer).
1024 * Size of this varies, due to varying MAC header length.
1025 * If end is not dword aligned, we'll have 2 extra bytes at the end
1026 * of the MAC header (device reads on dword boundaries).
1027 * We'll tell device about this padding later.
1028 */
1029 len = sizeof(struct iwl_tx_cmd) +
1030 sizeof(struct iwl_cmd_header) + hdr_len;
1031 firstlen = (len + 3) & ~3;
1032
1033 /* Tell NIC about any 2-byte padding after MAC header */
1034 if (firstlen != len)
1035 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1036
1037 /* Physical address of this Tx command's header (not MAC header!),
1038 * within command buffer array. */
d5934110 1039 txcmd_phys = dma_map_single(priv->bus->dev,
47c1b496
EG		 1040 &dev_cmd->hdr, firstlen,
1041 DMA_BIDIRECTIONAL);
d5934110 1042 if (unlikely(dma_mapping_error(priv->bus->dev, txcmd_phys)))
47c1b496
EG		 1043 return -1;
1044 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1045 dma_unmap_len_set(out_meta, len, firstlen);
1046
1047 if (!ieee80211_has_morefrags(fc)) {
1048 txq->need_update = 1;
1049 } else {
1050 wait_write_ptr = 1;
1051 txq->need_update = 0;
1052 }
1053
1054 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1055 * if any (802.11 null frames have no payload). */
1056 secondlen = skb->len - hdr_len;
1057 if (secondlen > 0) {
d5934110 1058 phys_addr = dma_map_single(priv->bus->dev, skb->data + hdr_len,
47c1b496 1059 secondlen, DMA_TO_DEVICE);
d5934110
EG		 1060 if (unlikely(dma_mapping_error(priv->bus->dev, phys_addr))) {
1061 dma_unmap_single(priv->bus->dev,
47c1b496
EG		 1062 dma_unmap_addr(out_meta, mapping),
1063 dma_unmap_len(out_meta, len),
1064 DMA_BIDIRECTIONAL);
1065 return -1;
1066 }
1067 }
1068
1069 /* Attach buffers to TFD */
1070 iwlagn_txq_attach_buf_to_tfd(priv, txq, txcmd_phys, firstlen, 1);
1071 if (secondlen > 0)
1072 iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr,
1073 secondlen, 0);
1074
1075 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1076 offsetof(struct iwl_tx_cmd, scratch);
1077
1078 /* take back ownership of DMA buffer to enable update */
d5934110 1079 dma_sync_single_for_cpu(priv->bus->dev, txcmd_phys, firstlen,
47c1b496
EG		 1080 DMA_BIDIRECTIONAL);
1081 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1082 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1083
1084 IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
1085 le16_to_cpu(dev_cmd->hdr.sequence));
1086 IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1087 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1088 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1089
1090 /* Set up entry for this TFD in Tx byte-count array */
1091 if (ampdu)
48d42c42 1092 iwl_trans_txq_update_byte_cnt_tbl(priv, txq,
47c1b496
EG		 1093 le16_to_cpu(tx_cmd->len));
1094
d5934110 1095 dma_sync_single_for_device(priv->bus->dev, txcmd_phys, firstlen,
47c1b496
EG		 1096 DMA_BIDIRECTIONAL);
1097
1098 trace_iwlwifi_dev_tx(priv,
1099 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1100 sizeof(struct iwl_tfd),
1101 &dev_cmd->hdr, firstlen,
1102 skb->data + hdr_len, secondlen);
1103
1104 /* Tell device the write index *just past* this latest filled TFD */
1105 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1106 iwl_txq_update_write_ptr(priv, txq);
1107
1108 /*
1109 * At this point the frame is "transmitted" successfully
1110 * and we will get a TX status notification eventually,
1111 * regardless of the value of ret. "ret" only indicates
1112 * whether or not we should update the write pointer.
1113 */
1114 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
1115 if (wait_write_ptr) {
1116 txq->need_update = 1;
1117 iwl_txq_update_write_ptr(priv, txq);
1118 } else {
1119 iwl_stop_queue(priv, txq);
1120 }
1121 }
1122 return 0;
1123}
1124
e6bb4c9c 1125static void iwl_trans_pcie_kick_nic(struct iwl_priv *priv)
56d90f4c
EG		 1126{
1127 /* Remove all resets to allow NIC to operate */
1128 iwl_write32(priv, CSR_RESET, 0);
1129}
1130
e6bb4c9c
EG		 1131static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1132{
5a878bf6
EG		 1133 struct iwl_trans_pcie *trans_pcie =
1134 IWL_TRANS_GET_PCIE_TRANS(trans);
e6bb4c9c
EG		 1135 struct iwl_priv *priv = priv(trans);
1136 int err;
1137
1138 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
1139 iwl_irq_tasklet, (unsigned long)priv);
1140
1141 iwl_alloc_isr_ict(priv);
1142
1143 err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
1144 DRV_NAME, priv);
1145 if (err) {
1146 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->bus->irq);
1147 iwl_free_isr_ict(priv);
1148 return err;
1149 }
1150
5a878bf6 1151 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
e6bb4c9c
EG		 1152 return 0;
1153}
1154
1155static void iwl_trans_pcie_sync_irq(struct iwl_priv *priv)
a27367d2
EG		 1156{
1157 /* wait to make sure we flush pending tasklet*/
d5934110 1158 synchronize_irq(priv->bus->irq);
a27367d2
EG		 1159 tasklet_kill(&priv->irq_tasklet);
1160}
1161
e6bb4c9c 1162static void iwl_trans_pcie_free(struct iwl_priv *priv)
34c1b7ba 1163{
d5934110 1164 free_irq(priv->bus->irq, priv);
34c1b7ba 1165 iwl_free_isr_ict(priv);
e6bb4c9c
EG		 1166 kfree(trans(priv));
1167 trans(priv) = NULL;
34c1b7ba
EG		 1168}
1169
57210f7c
EG		 1170#ifdef CONFIG_PM
1171
1172static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1173{
1174 /*
1175 * This function is called when system goes into suspend state
1176 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
1177 * first but since iwl_mac_stop() has no knowledge of who the caller is,
1178 * it will not call apm_ops.stop() to stop the DMA operation.
1179 * Calling apm_ops.stop here to make sure we stop the DMA.
1180 *
1181 * But of course ... if we have configured WoWLAN then we did other
1182 * things already :-)
1183 */
1184 if (!trans->shrd->wowlan)
1185 iwl_apm_stop(priv(trans));
1186
1187 return 0;
1188}
1189
1190static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1191{
1192 bool hw_rfkill = false;
1193
1194 iwl_enable_interrupts(priv(trans));
1195
1196 if (!(iwl_read32(priv(trans), CSR_GP_CNTRL) &
1197 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1198 hw_rfkill = true;
1199
1200 if (hw_rfkill)
1201 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1202 else
1203 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1204
1205 wiphy_rfkill_set_hw_state(priv(trans)->hw->wiphy, hw_rfkill);
1206
1207 return 0;
1208}
1209#else /* CONFIG_PM */
1210static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1211{ return 0; }
1212
1213static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1214{ return 0; }
1215
1216#endif /* CONFIG_PM */
1217
e6bb4c9c 1218const struct iwl_trans_ops trans_ops_pcie;
e419d62d 1219
e6bb4c9c
EG		 1220static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
1221{
1222 struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
1223 sizeof(struct iwl_trans_pcie),
1224 GFP_KERNEL);
1225 if (iwl_trans) {
5a878bf6
EG		 1226 struct iwl_trans_pcie *trans_pcie =
1227 IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
e6bb4c9c
EG		 1228 iwl_trans->ops = &trans_ops_pcie;
1229 iwl_trans->shrd = shrd;
5a878bf6 1230 trans_pcie->trans = iwl_trans;
e6bb4c9c 1231 }
ab6cf8e8 1232
e6bb4c9c
EG		 1233 return iwl_trans;
1234}
47c1b496 1235
87e5666c
EG		 1236#ifdef CONFIG_IWLWIFI_DEBUGFS
1237/* create and remove of files */
1238#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 1239 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c
EG		 1240 &iwl_dbgfs_##name##_ops)) \
1241 return -ENOMEM; \
1242} while (0)
1243
1244/* file operation */
1245#define DEBUGFS_READ_FUNC(name) \
1246static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1247 char __user *user_buf, \
1248 size_t count, loff_t *ppos);
1249
1250#define DEBUGFS_WRITE_FUNC(name) \
1251static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1252 const char __user *user_buf, \
1253 size_t count, loff_t *ppos);
1254
1255
1256static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1257{
1258 file->private_data = inode->i_private;
1259 return 0;
1260}
1261
1262#define DEBUGFS_READ_FILE_OPS(name) \
1263 DEBUGFS_READ_FUNC(name); \
1264static const struct file_operations iwl_dbgfs_##name##_ops = { \
1265 .read = iwl_dbgfs_##name##_read, \
1266 .open = iwl_dbgfs_open_file_generic, \
1267 .llseek = generic_file_llseek, \
1268};
1269
1270#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1271 DEBUGFS_READ_FUNC(name); \
1272 DEBUGFS_WRITE_FUNC(name); \
1273static const struct file_operations iwl_dbgfs_##name##_ops = { \
1274 .write = iwl_dbgfs_##name##_write, \
1275 .read = iwl_dbgfs_##name##_read, \
1276 .open = iwl_dbgfs_open_file_generic, \
1277 .llseek = generic_file_llseek, \
1278};
1279
1280static ssize_t iwl_dbgfs_traffic_log_read(struct file *file,
1281 char __user *user_buf,
1282 size_t count, loff_t *ppos)
1283{
5a878bf6
EG		 1284 struct iwl_trans *trans = file->private_data;
1285 struct iwl_priv *priv = priv(trans);
87e5666c
EG		 1286 int pos = 0, ofs = 0;
1287 int cnt = 0, entry;
5a878bf6
EG		 1288 struct iwl_trans_pcie *trans_pcie =
1289 IWL_TRANS_GET_PCIE_TRANS(trans);
87e5666c
EG		 1290 struct iwl_tx_queue *txq;
1291 struct iwl_queue *q;
5a878bf6 1292 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
87e5666c
EG		 1293 char *buf;
1294 int bufsz = ((IWL_TRAFFIC_ENTRIES * IWL_TRAFFIC_ENTRY_SIZE * 64) * 2) +
1295 (priv->cfg->base_params->num_of_queues * 32 * 8) + 400;
1296 const u8 *ptr;
1297 ssize_t ret;
1298
1299 if (!priv->txq) {
5a878bf6 1300 IWL_ERR(trans, "txq not ready\n");
87e5666c
EG		 1301 return -EAGAIN;
1302 }
1303 buf = kzalloc(bufsz, GFP_KERNEL);
1304 if (!buf) {
5a878bf6 1305 IWL_ERR(trans, "Can not allocate buffer\n");
87e5666c
EG		 1306 return -ENOMEM;
1307 }
1308 pos += scnprintf(buf + pos, bufsz - pos, "Tx Queue\n");
5a878bf6 1309 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
87e5666c
EG		 1310 txq = &priv->txq[cnt];
1311 q = &txq->q;
1312 pos += scnprintf(buf + pos, bufsz - pos,
1313 "q[%d]: read_ptr: %u, write_ptr: %u\n",
1314 cnt, q->read_ptr, q->write_ptr);
1315 }
1316 if (priv->tx_traffic &&
5a878bf6 1317 (iwl_get_debug_level(trans->shrd) & IWL_DL_TX)) {
87e5666c
EG		 1318 ptr = priv->tx_traffic;
1319 pos += scnprintf(buf + pos, bufsz - pos,
5a878bf6 1320 "Tx Traffic idx: %u\n", priv->tx_traffic_idx);
87e5666c
EG		 1321 for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) {
1322 for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16;
1323 entry++, ofs += 16) {
1324 pos += scnprintf(buf + pos, bufsz - pos,
1325 "0x%.4x ", ofs);
1326 hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
1327 buf + pos, bufsz - pos, 0);
1328 pos += strlen(buf + pos);
1329 if (bufsz - pos > 0)
1330 buf[pos++] = '\n';
1331 }
1332 }
1333 }
1334
1335 pos += scnprintf(buf + pos, bufsz - pos, "Rx Queue\n");
1336 pos += scnprintf(buf + pos, bufsz - pos,
1337 "read: %u, write: %u\n",
1338 rxq->read, rxq->write);
1339
1340 if (priv->rx_traffic &&
5a878bf6 1341 (iwl_get_debug_level(trans->shrd) & IWL_DL_RX)) {
87e5666c
EG		 1342 ptr = priv->rx_traffic;
1343 pos += scnprintf(buf + pos, bufsz - pos,
5a878bf6 1344 "Rx Traffic idx: %u\n", priv->rx_traffic_idx);
87e5666c
EG		 1345 for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) {
1346 for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16;
1347 entry++, ofs += 16) {
1348 pos += scnprintf(buf + pos, bufsz - pos,
1349 "0x%.4x ", ofs);
1350 hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
1351 buf + pos, bufsz - pos, 0);
1352 pos += strlen(buf + pos);
1353 if (bufsz - pos > 0)
1354 buf[pos++] = '\n';
1355 }
1356 }
1357 }
1358
1359 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1360 kfree(buf);
1361 return ret;
1362}
1363
1364static ssize_t iwl_dbgfs_traffic_log_write(struct file *file,
1365 const char __user *user_buf,
1366 size_t count, loff_t *ppos)
1367{
5a878bf6 1368 struct iwl_trans *trans = file->private_data;
87e5666c
EG		 1369 char buf[8];
1370 int buf_size;
1371 int traffic_log;
1372
1373 memset(buf, 0, sizeof(buf));
1374 buf_size = min(count, sizeof(buf) - 1);
1375 if (copy_from_user(buf, user_buf, buf_size))
1376 return -EFAULT;
1377 if (sscanf(buf, "%d", &traffic_log) != 1)
1378 return -EFAULT;
1379 if (traffic_log == 0)
5a878bf6 1380 iwl_reset_traffic_log(priv(trans));
87e5666c
EG		 1381
1382 return count;
1383}
1384
1385static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1386 char __user *user_buf,
1387 size_t count, loff_t *ppos) {
1388
5a878bf6
EG		 1389 struct iwl_trans *trans = file->private_data;
1390 struct iwl_priv *priv = priv(trans);
87e5666c
EG		 1391 struct iwl_tx_queue *txq;
1392 struct iwl_queue *q;
1393 char *buf;
1394 int pos = 0;
1395 int cnt;
1396 int ret;
1397 const size_t bufsz = sizeof(char) * 64 *
1398 priv->cfg->base_params->num_of_queues;
1399
1400 if (!priv->txq) {
1401 IWL_ERR(priv, "txq not ready\n");
1402 return -EAGAIN;
1403 }
1404 buf = kzalloc(bufsz, GFP_KERNEL);
1405 if (!buf)
1406 return -ENOMEM;
1407
5a878bf6 1408 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
87e5666c
EG		 1409 txq = &priv->txq[cnt];
1410 q = &txq->q;
1411 pos += scnprintf(buf + pos, bufsz - pos,
1412 "hwq %.2d: read=%u write=%u stop=%d"
1413 " swq_id=%#.2x (ac %d/hwq %d)\n",
1414 cnt, q->read_ptr, q->write_ptr,
1415 !!test_bit(cnt, priv->queue_stopped),
1416 txq->swq_id, txq->swq_id & 3,
1417 (txq->swq_id >> 2) & 0x1f);
1418 if (cnt >= 4)
1419 continue;
1420 /* for the ACs, display the stop count too */
1421 pos += scnprintf(buf + pos, bufsz - pos,
1422 " stop-count: %d\n",
1423 atomic_read(&priv->queue_stop_count[cnt]));
1424 }
1425 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1426 kfree(buf);
1427 return ret;
1428}
1429
1430static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1431 char __user *user_buf,
1432 size_t count, loff_t *ppos) {
5a878bf6
EG		 1433 struct iwl_trans *trans = file->private_data;
1434 struct iwl_trans_pcie *trans_pcie =
1435 IWL_TRANS_GET_PCIE_TRANS(trans);
1436 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
87e5666c
EG		 1437 char buf[256];
1438 int pos = 0;
1439 const size_t bufsz = sizeof(buf);
1440
1441 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1442 rxq->read);
1443 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1444 rxq->write);
1445 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1446 rxq->free_count);
1447 if (rxq->rb_stts) {
1448 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1449 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1450 } else {
1451 pos += scnprintf(buf + pos, bufsz - pos,
1452 "closed_rb_num: Not Allocated\n");
1453 }
1454 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1455}
1456
1457DEBUGFS_READ_WRITE_FILE_OPS(traffic_log);
1458DEBUGFS_READ_FILE_OPS(rx_queue);
1459DEBUGFS_READ_FILE_OPS(tx_queue);
1460
1461/*
1462 * Create the debugfs files and directories
1463 *
1464 */
1465static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1466 struct dentry *dir)
1467{
87e5666c
EG		 1468 DEBUGFS_ADD_FILE(traffic_log, dir, S_IWUSR | S_IRUSR);
1469 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1470 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1471 return 0;
1472}
1473#else
1474static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1475 struct dentry *dir)
1476{ return 0; }
1477
1478#endif /*CONFIG_IWLWIFI_DEBUGFS */
1479
e6bb4c9c
EG		 1480const struct iwl_trans_ops trans_ops_pcie = {
1481 .alloc = iwl_trans_pcie_alloc,
1482 .request_irq = iwl_trans_pcie_request_irq,
1483 .start_device = iwl_trans_pcie_start_device,
1484 .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
1485 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 1486
e6bb4c9c 1487 .tx_start = iwl_trans_pcie_tx_start,
48d42c42 1488
e6bb4c9c
EG		 1489 .rx_free = iwl_trans_pcie_rx_free,
1490 .tx_free = iwl_trans_pcie_tx_free,
34c1b7ba 1491
e6bb4c9c
EG		 1492 .send_cmd = iwl_trans_pcie_send_cmd,
1493 .send_cmd_pdu = iwl_trans_pcie_send_cmd_pdu,
c85eb619 1494
e6bb4c9c
EG		 1495 .get_tx_cmd = iwl_trans_pcie_get_tx_cmd,
1496 .tx = iwl_trans_pcie_tx,
34c1b7ba 1497
e6bb4c9c
EG		 1498 .txq_agg_disable = iwl_trans_pcie_txq_agg_disable,
1499 .txq_agg_setup = iwl_trans_pcie_txq_agg_setup,
34c1b7ba 1500
e6bb4c9c 1501 .kick_nic = iwl_trans_pcie_kick_nic,
1e89cbac 1502
e6bb4c9c
EG		 1503 .sync_irq = iwl_trans_pcie_sync_irq,
1504 .free = iwl_trans_pcie_free,
87e5666c
EG		 1505
1506 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
57210f7c
EG		 1507 .suspend = iwl_trans_pcie_suspend,
1508 .resume = iwl_trans_pcie_resume,
e6bb4c9c 1509};
ab697a9f 1510
Linux kernel - Deliverables
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