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iwlagn: transport handler can register debugfs entries
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
e6bb4c9c 63#include <linux/interrupt.h>
87e5666c 64#include <linux/debugfs.h>
e6bb4c9c 65
a0f6b0a2 66#include "iwl-dev.h"
c85eb619 67#include "iwl-trans.h"
02aca585
EG		 68#include "iwl-core.h"
69#include "iwl-helpers.h"
ab697a9f 70#include "iwl-trans-int-pcie.h"
02aca585
EG		 71/*TODO remove uneeded includes when the transport layer tx_free will be here */
72#include "iwl-agn.h"
e419d62d 73#include "iwl-core.h"
48f20d35 74#include "iwl-shared.h"
c85eb619
EG		 75
76static int iwl_trans_rx_alloc(struct iwl_priv *priv)
77{
78 struct iwl_rx_queue *rxq = &priv->rxq;
d5934110 79 struct device *dev = priv->bus->dev;
c85eb619
EG		 80
81 memset(&priv->rxq, 0, sizeof(priv->rxq));
82
83 spin_lock_init(&rxq->lock);
84 INIT_LIST_HEAD(&rxq->rx_free);
85 INIT_LIST_HEAD(&rxq->rx_used);
86
87 if (WARN_ON(rxq->bd || rxq->rb_stts))
88 return -EINVAL;
89
90 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
a0f6b0a2
EG		 91 rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
92 &rxq->bd_dma, GFP_KERNEL);
c85eb619
EG		 93 if (!rxq->bd)
94 goto err_bd;
a0f6b0a2 95 memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
c85eb619
EG		 96
97 /*Allocate the driver's pointer to receive buffer status */
98 rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
99 &rxq->rb_stts_dma, GFP_KERNEL);
100 if (!rxq->rb_stts)
101 goto err_rb_stts;
102 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
103
104 return 0;
105
106err_rb_stts:
a0f6b0a2
EG		 107 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
108 rxq->bd, rxq->bd_dma);
c85eb619
EG		 109 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
110 rxq->bd = NULL;
111err_bd:
112 return -ENOMEM;
113}
114
a0f6b0a2 115static void iwl_trans_rxq_free_rx_bufs(struct iwl_priv *priv)
c85eb619
EG		 116{
117 struct iwl_rx_queue *rxq = &priv->rxq;
a0f6b0a2 118 int i;
c85eb619
EG		 119
120 /* Fill the rx_used queue with _all_ of the Rx buffers */
121 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
122 /* In the reset function, these buffers may have been allocated
123 * to an SKB, so we need to unmap and free potential storage */
124 if (rxq->pool[i].page != NULL) {
d5934110 125 dma_unmap_page(priv->bus->dev, rxq->pool[i].page_dma,
d6189124 126 PAGE_SIZE << hw_params(priv).rx_page_order,
c85eb619
EG		 127 DMA_FROM_DEVICE);
128 __iwl_free_pages(priv, rxq->pool[i].page);
129 rxq->pool[i].page = NULL;
130 }
131 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
132 }
a0f6b0a2
EG		 133}
134
ab697a9f
EG		 135static void iwl_trans_rx_hw_init(struct iwl_priv *priv,
136 struct iwl_rx_queue *rxq)
137{
138 u32 rb_size;
139 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
140 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
141
142 rb_timeout = RX_RB_TIMEOUT;
143
144 if (iwlagn_mod_params.amsdu_size_8K)
145 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
146 else
147 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
148
149 /* Stop Rx DMA */
150 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
151
152 /* Reset driver's Rx queue write index */
153 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
154
155 /* Tell device where to find RBD circular buffer in DRAM */
156 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
157 (u32)(rxq->bd_dma >> 8));
158
159 /* Tell device where in DRAM to update its Rx status */
160 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
161 rxq->rb_stts_dma >> 4);
162
163 /* Enable Rx DMA
164 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
165 * the credit mechanism in 5000 HW RX FIFO
166 * Direct rx interrupts to hosts
167 * Rx buffer size 4 or 8k
168 * RB timeout 0x10
169 * 256 RBDs
170 */
171 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
172 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
173 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
174 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
175 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
176 rb_size|
177 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
178 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
179
180 /* Set interrupt coalescing timer to default (2048 usecs) */
181 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
182}
183
392f8b78 184static int iwl_rx_init(struct iwl_priv *priv)
a0f6b0a2
EG		 185{
186 struct iwl_rx_queue *rxq = &priv->rxq;
187 int i, err;
188 unsigned long flags;
189
190 if (!rxq->bd) {
191 err = iwl_trans_rx_alloc(priv);
192 if (err)
193 return err;
194 }
195
196 spin_lock_irqsave(&rxq->lock, flags);
197 INIT_LIST_HEAD(&rxq->rx_free);
198 INIT_LIST_HEAD(&rxq->rx_used);
199
200 iwl_trans_rxq_free_rx_bufs(priv);
c85eb619
EG		 201
202 for (i = 0; i < RX_QUEUE_SIZE; i++)
203 rxq->queue[i] = NULL;
204
205 /* Set us so that we have processed and used all buffers, but have
206 * not restocked the Rx queue with fresh buffers */
207 rxq->read = rxq->write = 0;
208 rxq->write_actual = 0;
209 rxq->free_count = 0;
210 spin_unlock_irqrestore(&rxq->lock, flags);
211
ab697a9f
EG		 212 iwlagn_rx_replenish(priv);
213
214 iwl_trans_rx_hw_init(priv, rxq);
215
10b15e6f 216 spin_lock_irqsave(&priv->shrd->lock, flags);
ab697a9f
EG		 217 rxq->need_update = 1;
218 iwl_rx_queue_update_write_ptr(priv, rxq);
10b15e6f 219 spin_unlock_irqrestore(&priv->shrd->lock, flags);
ab697a9f 220
c85eb619
EG		 221 return 0;
222}
223
e6bb4c9c 224static void iwl_trans_pcie_rx_free(struct iwl_priv *priv)
a0f6b0a2
EG		 225{
226 struct iwl_rx_queue *rxq = &priv->rxq;
227 unsigned long flags;
228
229 /*if rxq->bd is NULL, it means that nothing has been allocated,
230 * exit now */
231 if (!rxq->bd) {
232 IWL_DEBUG_INFO(priv, "Free NULL rx context\n");
233 return;
234 }
235
236 spin_lock_irqsave(&rxq->lock, flags);
237 iwl_trans_rxq_free_rx_bufs(priv);
238 spin_unlock_irqrestore(&rxq->lock, flags);
239
d5934110 240 dma_free_coherent(priv->bus->dev, sizeof(__le32) * RX_QUEUE_SIZE,
a0f6b0a2
EG		 241 rxq->bd, rxq->bd_dma);
242 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
243 rxq->bd = NULL;
244
245 if (rxq->rb_stts)
d5934110 246 dma_free_coherent(priv->bus->dev,
a0f6b0a2
EG		 247 sizeof(struct iwl_rb_status),
248 rxq->rb_stts, rxq->rb_stts_dma);
249 else
250 IWL_DEBUG_INFO(priv, "Free rxq->rb_stts which is NULL\n");
251 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
252 rxq->rb_stts = NULL;
253}
254
c2c52e8b
EG		 255static int iwl_trans_rx_stop(struct iwl_priv *priv)
256{
257
258 /* stop Rx DMA */
259 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
260 return iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
261 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
262}
263
02aca585
EG		 264static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
265 struct iwl_dma_ptr *ptr, size_t size)
266{
267 if (WARN_ON(ptr->addr))
268 return -EINVAL;
269
d5934110 270 ptr->addr = dma_alloc_coherent(priv->bus->dev, size,
02aca585
EG		 271 &ptr->dma, GFP_KERNEL);
272 if (!ptr->addr)
273 return -ENOMEM;
274 ptr->size = size;
275 return 0;
276}
277
1359ca4f
EG		 278static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
279 struct iwl_dma_ptr *ptr)
280{
281 if (unlikely(!ptr->addr))
282 return;
283
d5934110 284 dma_free_coherent(priv->bus->dev, ptr->size, ptr->addr, ptr->dma);
1359ca4f
EG		 285 memset(ptr, 0, sizeof(*ptr));
286}
287
02aca585
EG		 288static int iwl_trans_txq_alloc(struct iwl_priv *priv, struct iwl_tx_queue *txq,
289 int slots_num, u32 txq_id)
290{
d6189124 291 size_t tfd_sz = hw_params(priv).tfd_size * TFD_QUEUE_SIZE_MAX;
02aca585
EG		 292 int i;
293
294 if (WARN_ON(txq->meta || txq->cmd || txq->txb || txq->tfds))
295 return -EINVAL;
296
1359ca4f
EG		 297 txq->q.n_window = slots_num;
298
02aca585
EG		 299 txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num,
300 GFP_KERNEL);
301 txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num,
302 GFP_KERNEL);
303
304 if (!txq->meta || !txq->cmd)
305 goto error;
306
307 for (i = 0; i < slots_num; i++) {
308 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
309 GFP_KERNEL);
310 if (!txq->cmd[i])
311 goto error;
312 }
313
314 /* Alloc driver data array and TFD circular buffer */
315 /* Driver private data, only for Tx (not command) queues,
316 * not shared with device. */
cefeaa5f 317 if (txq_id != priv->shrd->cmd_queue) {
02aca585
EG		 318 txq->txb = kzalloc(sizeof(txq->txb[0]) *
319 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
320 if (!txq->txb) {
321 IWL_ERR(priv, "kmalloc for auxiliary BD "
322 "structures failed\n");
323 goto error;
324 }
325 } else {
326 txq->txb = NULL;
327 }
328
329 /* Circular buffer of transmit frame descriptors (TFDs),
330 * shared with device */
d5934110 331 txq->tfds = dma_alloc_coherent(priv->bus->dev, tfd_sz, &txq->q.dma_addr,
02aca585
EG		 332 GFP_KERNEL);
333 if (!txq->tfds) {
334 IWL_ERR(priv, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
335 goto error;
336 }
337 txq->q.id = txq_id;
338
339 return 0;
340error:
341 kfree(txq->txb);
342 txq->txb = NULL;
343 /* since txq->cmd has been zeroed,
344 * all non allocated cmd[i] will be NULL */
345 if (txq->cmd)
346 for (i = 0; i < slots_num; i++)
347 kfree(txq->cmd[i]);
348 kfree(txq->meta);
349 kfree(txq->cmd);
350 txq->meta = NULL;
351 txq->cmd = NULL;
352
353 return -ENOMEM;
354
355}
356
357static int iwl_trans_txq_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
358 int slots_num, u32 txq_id)
359{
360 int ret;
361
362 txq->need_update = 0;
363 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
364
365 /*
366 * For the default queues 0-3, set up the swq_id
367 * already -- all others need to get one later
368 * (if they need one at all).
369 */
370 if (txq_id < 4)
371 iwl_set_swq_id(txq, txq_id, txq_id);
372
373 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
374 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
375 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
376
377 /* Initialize queue's high/low-water marks, and head/tail indexes */
378 ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
379 txq_id);
380 if (ret)
381 return ret;
382
383 /*
384 * Tell nic where to find circular buffer of Tx Frame Descriptors for
385 * given Tx queue, and enable the DMA channel used for that queue.
386 * Circular buffer (TFD queue in DRAM) physical base address */
387 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
388 txq->q.dma_addr >> 8);
389
390 return 0;
391}
392
c170b867
EG		 393/**
394 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
395 */
396static void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
397{
398 struct iwl_tx_queue *txq = &priv->txq[txq_id];
399 struct iwl_queue *q = &txq->q;
400
401 if (!q->n_bd)
402 return;
403
404 while (q->write_ptr != q->read_ptr) {
405 /* The read_ptr needs to bound by q->n_window */
406 iwlagn_txq_free_tfd(priv, txq, get_cmd_index(q, q->read_ptr));
407 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
408 }
409}
410
1359ca4f
EG		 411/**
412 * iwl_tx_queue_free - Deallocate DMA queue.
413 * @txq: Transmit queue to deallocate.
414 *
415 * Empty queue by removing and destroying all BD's.
416 * Free all buffers.
417 * 0-fill, but do not free "txq" descriptor structure.
418 */
419static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
420{
421 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d5934110 422 struct device *dev = priv->bus->dev;
1359ca4f
EG		 423 int i;
424 if (WARN_ON(!txq))
425 return;
426
427 iwl_tx_queue_unmap(priv, txq_id);
428
429 /* De-alloc array of command/tx buffers */
430 for (i = 0; i < txq->q.n_window; i++)
431 kfree(txq->cmd[i]);
432
433 /* De-alloc circular buffer of TFDs */
434 if (txq->q.n_bd) {
d6189124 435 dma_free_coherent(dev, hw_params(priv).tfd_size *
1359ca4f
EG		 436 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
437 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
438 }
439
440 /* De-alloc array of per-TFD driver data */
441 kfree(txq->txb);
442 txq->txb = NULL;
443
444 /* deallocate arrays */
445 kfree(txq->cmd);
446 kfree(txq->meta);
447 txq->cmd = NULL;
448 txq->meta = NULL;
449
450 /* 0-fill queue descriptor structure */
451 memset(txq, 0, sizeof(*txq));
452}
453
454/**
455 * iwl_trans_tx_free - Free TXQ Context
456 *
457 * Destroy all TX DMA queues and structures
458 */
e6bb4c9c 459static void iwl_trans_pcie_tx_free(struct iwl_priv *priv)
1359ca4f
EG		 460{
461 int txq_id;
462
463 /* Tx queues */
464 if (priv->txq) {
d6189124
EG		 465 for (txq_id = 0;
466 txq_id < hw_params(priv).max_txq_num; txq_id++)
1359ca4f
EG		 467 iwl_tx_queue_free(priv, txq_id);
468 }
469
470 kfree(priv->txq);
471 priv->txq = NULL;
472
473 iwlagn_free_dma_ptr(priv, &priv->kw);
474
475 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
476}
477
02aca585
EG		 478/**
479 * iwl_trans_tx_alloc - allocate TX context
480 * Allocate all Tx DMA structures and initialize them
481 *
482 * @param priv
483 * @return error code
484 */
485static int iwl_trans_tx_alloc(struct iwl_priv *priv)
486{
487 int ret;
488 int txq_id, slots_num;
489
490 /*It is not allowed to alloc twice, so warn when this happens.
491 * We cannot rely on the previous allocation, so free and fail */
492 if (WARN_ON(priv->txq)) {
493 ret = -EINVAL;
494 goto error;
495 }
496
497 ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
d6189124 498 hw_params(priv).scd_bc_tbls_size);
02aca585
EG		 499 if (ret) {
500 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
501 goto error;
502 }
503
504 /* Alloc keep-warm buffer */
505 ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
506 if (ret) {
507 IWL_ERR(priv, "Keep Warm allocation failed\n");
508 goto error;
509 }
510
511 priv->txq = kzalloc(sizeof(struct iwl_tx_queue) *
512 priv->cfg->base_params->num_of_queues, GFP_KERNEL);
513 if (!priv->txq) {
514 IWL_ERR(priv, "Not enough memory for txq\n");
515 ret = ENOMEM;
516 goto error;
517 }
518
519 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
d6189124 520 for (txq_id = 0; txq_id < hw_params(priv).max_txq_num; txq_id++) {
cefeaa5f 521 slots_num = (txq_id == priv->shrd->cmd_queue) ?
02aca585
EG		 522 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
523 ret = iwl_trans_txq_alloc(priv, &priv->txq[txq_id], slots_num,
524 txq_id);
525 if (ret) {
526 IWL_ERR(priv, "Tx %d queue alloc failed\n", txq_id);
527 goto error;
528 }
529 }
530
531 return 0;
532
533error:
e6bb4c9c 534 iwl_trans_tx_free(trans(priv));
02aca585
EG		 535
536 return ret;
537}
392f8b78 538static int iwl_tx_init(struct iwl_priv *priv)
02aca585
EG		 539{
540 int ret;
541 int txq_id, slots_num;
542 unsigned long flags;
543 bool alloc = false;
544
545 if (!priv->txq) {
546 ret = iwl_trans_tx_alloc(priv);
547 if (ret)
548 goto error;
549 alloc = true;
550 }
551
10b15e6f 552 spin_lock_irqsave(&priv->shrd->lock, flags);
02aca585
EG		 553
554 /* Turn off all Tx DMA fifos */
b3c2ce13 555 iwl_write_prph(priv, SCD_TXFACT, 0);
02aca585
EG		 556
557 /* Tell NIC where to find the "keep warm" buffer */
558 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
559
10b15e6f 560 spin_unlock_irqrestore(&priv->shrd->lock, flags);
02aca585
EG		 561
562 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
d6189124 563 for (txq_id = 0; txq_id < hw_params(priv).max_txq_num; txq_id++) {
cefeaa5f 564 slots_num = (txq_id == priv->shrd->cmd_queue) ?
02aca585
EG		 565 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
566 ret = iwl_trans_txq_init(priv, &priv->txq[txq_id], slots_num,
567 txq_id);
568 if (ret) {
569 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
570 goto error;
571 }
572 }
573
574 return 0;
575error:
576 /*Upon error, free only if we allocated something */
577 if (alloc)
e6bb4c9c 578 iwl_trans_tx_free(trans(priv));
02aca585
EG		 579 return ret;
580}
581
392f8b78
EG		 582static void iwl_set_pwr_vmain(struct iwl_priv *priv)
583{
584/*
585 * (for documentation purposes)
586 * to set power to V_AUX, do:
587
588 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
589 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
590 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
591 ~APMG_PS_CTRL_MSK_PWR_SRC);
592 */
593
594 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
595 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
596 ~APMG_PS_CTRL_MSK_PWR_SRC);
597}
598
599static int iwl_nic_init(struct iwl_priv *priv)
600{
601 unsigned long flags;
602
603 /* nic_init */
10b15e6f 604 spin_lock_irqsave(&priv->shrd->lock, flags);
392f8b78
EG		 605 iwl_apm_init(priv);
606
607 /* Set interrupt coalescing calibration timer to default (512 usecs) */
608 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
609
10b15e6f 610 spin_unlock_irqrestore(&priv->shrd->lock, flags);
392f8b78
EG		 611
612 iwl_set_pwr_vmain(priv);
613
614 priv->cfg->lib->nic_config(priv);
615
616 /* Allocate the RX queue, or reset if it is already allocated */
617 iwl_rx_init(priv);
618
619 /* Allocate or reset and init all Tx and Command queues */
620 if (iwl_tx_init(priv))
621 return -ENOMEM;
622
623 if (priv->cfg->base_params->shadow_reg_enable) {
624 /* enable shadow regs in HW */
625 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
626 0x800FFFFF);
627 }
628
63013ae3 629 set_bit(STATUS_INIT, &priv->shrd->status);
392f8b78
EG		 630
631 return 0;
632}
633
634#define HW_READY_TIMEOUT (50)
635
636/* Note: returns poll_bit return value, which is >= 0 if success */
637static int iwl_set_hw_ready(struct iwl_priv *priv)
638{
639 int ret;
640
641 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
642 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
643
644 /* See if we got it */
645 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
646 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
647 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
648 HW_READY_TIMEOUT);
649
650 IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : "");
651 return ret;
652}
653
654/* Note: returns standard 0/-ERROR code */
e6bb4c9c 655static int iwl_trans_pcie_prepare_card_hw(struct iwl_priv *priv)
392f8b78
EG		 656{
657 int ret;
658
0286cee0 659 IWL_DEBUG_INFO(priv, "iwl_trans_prepare_card_hw enter\n");
392f8b78
EG		 660
661 ret = iwl_set_hw_ready(priv);
662 if (ret >= 0)
663 return 0;
664
665 /* If HW is not ready, prepare the conditions to check again */
666 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
667 CSR_HW_IF_CONFIG_REG_PREPARE);
668
669 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
670 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
671 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
672
673 if (ret < 0)
674 return ret;
675
676 /* HW should be ready by now, check again. */
677 ret = iwl_set_hw_ready(priv);
678 if (ret >= 0)
679 return 0;
680 return ret;
681}
682
e6bb4c9c 683static int iwl_trans_pcie_start_device(struct iwl_priv *priv)
392f8b78
EG		 684{
685 int ret;
686
687 priv->ucode_owner = IWL_OWNERSHIP_DRIVER;
688
689 if ((priv->cfg->sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
e6bb4c9c 690 iwl_trans_pcie_prepare_card_hw(priv)) {
392f8b78
EG		 691 IWL_WARN(priv, "Exit HW not ready\n");
692 return -EIO;
693 }
694
695 /* If platform's RF_KILL switch is NOT set to KILL */
696 if (iwl_read32(priv, CSR_GP_CNTRL) &
697 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
63013ae3 698 clear_bit(STATUS_RF_KILL_HW, &priv->shrd->status);
392f8b78 699 else
63013ae3 700 set_bit(STATUS_RF_KILL_HW, &priv->shrd->status);
392f8b78
EG		 701
702 if (iwl_is_rfkill(priv)) {
703 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
704 iwl_enable_interrupts(priv);
705 return -ERFKILL;
706 }
707
708 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
709
710 ret = iwl_nic_init(priv);
711 if (ret) {
712 IWL_ERR(priv, "Unable to init nic\n");
713 return ret;
714 }
715
716 /* make sure rfkill handshake bits are cleared */
717 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
718 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
719 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
720
721 /* clear (again), then enable host interrupts */
722 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
723 iwl_enable_interrupts(priv);
724
725 /* really make sure rfkill handshake bits are cleared */
726 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
727 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
728
729 return 0;
730}
731
b3c2ce13
EG		 732/*
733 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
10b15e6f 734 * must be called under priv->shrd->lock and mac access
b3c2ce13
EG		 735 */
736static void iwl_trans_txq_set_sched(struct iwl_priv *priv, u32 mask)
737{
738 iwl_write_prph(priv, SCD_TXFACT, mask);
739}
740
741#define IWL_AC_UNSET -1
742
743struct queue_to_fifo_ac {
744 s8 fifo, ac;
745};
746
747static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
748 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
749 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
750 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
751 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
752 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
753 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
754 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
755 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
756 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
757 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
72c04ce0 758 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
b3c2ce13
EG		 759};
760
761static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
762 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
763 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
764 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
765 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
766 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
767 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
768 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
769 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
770 { IWL_TX_FIFO_BE_IPAN, 2, },
771 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
72c04ce0 772 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
b3c2ce13 773};
e6bb4c9c 774static void iwl_trans_pcie_tx_start(struct iwl_priv *priv)
b3c2ce13
EG		 775{
776 const struct queue_to_fifo_ac *queue_to_fifo;
777 struct iwl_rxon_context *ctx;
778 u32 a;
779 unsigned long flags;
780 int i, chan;
781 u32 reg_val;
782
10b15e6f 783 spin_lock_irqsave(&priv->shrd->lock, flags);
b3c2ce13
EG		 784
785 priv->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR);
786 a = priv->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
787 /* reset conext data memory */
788 for (; a < priv->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
789 a += 4)
790 iwl_write_targ_mem(priv, a, 0);
791 /* reset tx status memory */
792 for (; a < priv->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
793 a += 4)
794 iwl_write_targ_mem(priv, a, 0);
795 for (; a < priv->scd_base_addr +
d6189124
EG		 796 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(priv).max_txq_num);
797 a += 4)
b3c2ce13
EG		 798 iwl_write_targ_mem(priv, a, 0);
799
800 iwl_write_prph(priv, SCD_DRAM_BASE_ADDR,
801 priv->scd_bc_tbls.dma >> 10);
802
803 /* Enable DMA channel */
804 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
805 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
806 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
807 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
808
809 /* Update FH chicken bits */
810 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
811 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
812 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
813
814 iwl_write_prph(priv, SCD_QUEUECHAIN_SEL,
815 SCD_QUEUECHAIN_SEL_ALL(priv));
816 iwl_write_prph(priv, SCD_AGGR_SEL, 0);
817
818 /* initiate the queues */
d6189124 819 for (i = 0; i < hw_params(priv).max_txq_num; i++) {
b3c2ce13
EG		 820 iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0);
821 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
822 iwl_write_targ_mem(priv, priv->scd_base_addr +
823 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
824 iwl_write_targ_mem(priv, priv->scd_base_addr +
825 SCD_CONTEXT_QUEUE_OFFSET(i) +
826 sizeof(u32),
827 ((SCD_WIN_SIZE <<
828 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
829 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
830 ((SCD_FRAME_LIMIT <<
831 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
832 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
833 }
834
835 iwl_write_prph(priv, SCD_INTERRUPT_MASK,
d6189124 836 IWL_MASK(0, hw_params(priv).max_txq_num));
b3c2ce13
EG		 837
838 /* Activate all Tx DMA/FIFO channels */
839 iwl_trans_txq_set_sched(priv, IWL_MASK(0, 7));
840
841 /* map queues to FIFOs */
842 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
843 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
844 else
845 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
846
cefeaa5f 847 iwl_trans_set_wr_ptrs(priv, priv->shrd->cmd_queue, 0);
b3c2ce13
EG		 848
849 /* make sure all queue are not stopped */
850 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
851 for (i = 0; i < 4; i++)
852 atomic_set(&priv->queue_stop_count[i], 0);
853 for_each_context(priv, ctx)
854 ctx->last_tx_rejected = false;
855
856 /* reset to 0 to enable all the queue first */
857 priv->txq_ctx_active_msk = 0;
858
72c04ce0
JB		 859 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) !=
860 IWLAGN_FIRST_AMPDU_QUEUE);
861 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) !=
862 IWLAGN_FIRST_AMPDU_QUEUE);
b3c2ce13 863
72c04ce0 864 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
b3c2ce13
EG		 865 int fifo = queue_to_fifo[i].fifo;
866 int ac = queue_to_fifo[i].ac;
867
868 iwl_txq_ctx_activate(priv, i);
869
870 if (fifo == IWL_TX_FIFO_UNUSED)
871 continue;
872
873 if (ac != IWL_AC_UNSET)
874 iwl_set_swq_id(&priv->txq[i], ac, i);
48d42c42 875 iwl_trans_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
b3c2ce13
EG		 876 }
877
10b15e6f 878 spin_unlock_irqrestore(&priv->shrd->lock, flags);
b3c2ce13
EG		 879
880 /* Enable L1-Active */
881 iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG,
882 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
883}
884
c170b867
EG		 885/**
886 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
887 */
888static int iwl_trans_tx_stop(struct iwl_priv *priv)
889{
890 int ch, txq_id;
891 unsigned long flags;
892
893 /* Turn off all Tx DMA fifos */
10b15e6f 894 spin_lock_irqsave(&priv->shrd->lock, flags);
c170b867 895
b3c2ce13 896 iwl_trans_txq_set_sched(priv, 0);
c170b867
EG		 897
898 /* Stop each Tx DMA channel, and wait for it to be idle */
02f6f659 899 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
c170b867
EG		 900 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
901 if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
902 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
903 1000))
904 IWL_ERR(priv, "Failing on timeout while stopping"
905 " DMA channel %d [0x%08x]", ch,
906 iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG));
907 }
10b15e6f 908 spin_unlock_irqrestore(&priv->shrd->lock, flags);
c170b867
EG		 909
910 if (!priv->txq) {
911 IWL_WARN(priv, "Stopping tx queues that aren't allocated...");
912 return 0;
913 }
914
915 /* Unmap DMA from host system and free skb's */
d6189124 916 for (txq_id = 0; txq_id < hw_params(priv).max_txq_num; txq_id++)
c170b867
EG		 917 iwl_tx_queue_unmap(priv, txq_id);
918
919 return 0;
920}
921
e6bb4c9c 922static void iwl_trans_pcie_stop_device(struct iwl_priv *priv)
ab6cf8e8
EG		 923{
924 unsigned long flags;
925
926 /* stop and reset the on-board processor */
927 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
928
929 /* tell the device to stop sending interrupts */
10b15e6f 930 spin_lock_irqsave(&priv->shrd->lock, flags);
ab6cf8e8 931 iwl_disable_interrupts(priv);
10b15e6f 932 spin_unlock_irqrestore(&priv->shrd->lock, flags);
e6bb4c9c 933 iwl_trans_sync_irq(trans(priv));
ab6cf8e8
EG		 934
935 /* device going down, Stop using ICT table */
936 iwl_disable_ict(priv);
937
938 /*
939 * If a HW restart happens during firmware loading,
940 * then the firmware loading might call this function
941 * and later it might be called again due to the
942 * restart. So don't process again if the device is
943 * already dead.
944 */
63013ae3 945 if (test_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status)) {
ab6cf8e8
EG		 946 iwl_trans_tx_stop(priv);
947 iwl_trans_rx_stop(priv);
948
949 /* Power-down device's busmaster DMA clocks */
950 iwl_write_prph(priv, APMG_CLK_DIS_REG,
951 APMG_CLK_VAL_DMA_CLK_RQT);
952 udelay(5);
953 }
954
955 /* Make sure (redundant) we've released our request to stay awake */
956 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
957
958 /* Stop the device, and put it in low power state */
959 iwl_apm_stop(priv);
960}
961
e6bb4c9c 962static struct iwl_tx_cmd *iwl_trans_pcie_get_tx_cmd(struct iwl_priv *priv,
47c1b496
EG		 963 int txq_id)
964{
965 struct iwl_tx_queue *txq = &priv->txq[txq_id];
966 struct iwl_queue *q = &txq->q;
967 struct iwl_device_cmd *dev_cmd;
968
969 if (unlikely(iwl_queue_space(q) < q->high_mark))
970 return NULL;
971
972 /*
973 * Set up the Tx-command (not MAC!) header.
974 * Store the chosen Tx queue and TFD index within the sequence field;
975 * after Tx, uCode's Tx response will return this value so driver can
976 * locate the frame within the tx queue and do post-tx processing.
977 */
978 dev_cmd = txq->cmd[q->write_ptr];
979 memset(dev_cmd, 0, sizeof(*dev_cmd));
980 dev_cmd->hdr.cmd = REPLY_TX;
981 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
982 INDEX_TO_SEQ(q->write_ptr)));
983 return &dev_cmd->cmd.tx;
984}
985
e6bb4c9c 986static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb,
47c1b496
EG		 987 struct iwl_tx_cmd *tx_cmd, int txq_id, __le16 fc, bool ampdu,
988 struct iwl_rxon_context *ctx)
989{
990 struct iwl_tx_queue *txq = &priv->txq[txq_id];
991 struct iwl_queue *q = &txq->q;
992 struct iwl_device_cmd *dev_cmd = txq->cmd[q->write_ptr];
993 struct iwl_cmd_meta *out_meta;
994
995 dma_addr_t phys_addr = 0;
996 dma_addr_t txcmd_phys;
997 dma_addr_t scratch_phys;
998 u16 len, firstlen, secondlen;
999 u8 wait_write_ptr = 0;
1000 u8 hdr_len = ieee80211_hdrlen(fc);
1001
1002 /* Set up driver data for this TFD */
1003 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
1004 txq->txb[q->write_ptr].skb = skb;
1005 txq->txb[q->write_ptr].ctx = ctx;
1006
1007 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1008 out_meta = &txq->meta[q->write_ptr];
1009
1010 /*
1011 * Use the first empty entry in this queue's command buffer array
1012 * to contain the Tx command and MAC header concatenated together
1013 * (payload data will be in another buffer).
1014 * Size of this varies, due to varying MAC header length.
1015 * If end is not dword aligned, we'll have 2 extra bytes at the end
1016 * of the MAC header (device reads on dword boundaries).
1017 * We'll tell device about this padding later.
1018 */
1019 len = sizeof(struct iwl_tx_cmd) +
1020 sizeof(struct iwl_cmd_header) + hdr_len;
1021 firstlen = (len + 3) & ~3;
1022
1023 /* Tell NIC about any 2-byte padding after MAC header */
1024 if (firstlen != len)
1025 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1026
1027 /* Physical address of this Tx command's header (not MAC header!),
1028 * within command buffer array. */
d5934110 1029 txcmd_phys = dma_map_single(priv->bus->dev,
47c1b496
EG		 1030 &dev_cmd->hdr, firstlen,
1031 DMA_BIDIRECTIONAL);
d5934110 1032 if (unlikely(dma_mapping_error(priv->bus->dev, txcmd_phys)))
47c1b496
EG		 1033 return -1;
1034 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1035 dma_unmap_len_set(out_meta, len, firstlen);
1036
1037 if (!ieee80211_has_morefrags(fc)) {
1038 txq->need_update = 1;
1039 } else {
1040 wait_write_ptr = 1;
1041 txq->need_update = 0;
1042 }
1043
1044 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1045 * if any (802.11 null frames have no payload). */
1046 secondlen = skb->len - hdr_len;
1047 if (secondlen > 0) {
d5934110 1048 phys_addr = dma_map_single(priv->bus->dev, skb->data + hdr_len,
47c1b496 1049 secondlen, DMA_TO_DEVICE);
d5934110
EG		 1050 if (unlikely(dma_mapping_error(priv->bus->dev, phys_addr))) {
1051 dma_unmap_single(priv->bus->dev,
47c1b496
EG		 1052 dma_unmap_addr(out_meta, mapping),
1053 dma_unmap_len(out_meta, len),
1054 DMA_BIDIRECTIONAL);
1055 return -1;
1056 }
1057 }
1058
1059 /* Attach buffers to TFD */
1060 iwlagn_txq_attach_buf_to_tfd(priv, txq, txcmd_phys, firstlen, 1);
1061 if (secondlen > 0)
1062 iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr,
1063 secondlen, 0);
1064
1065 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1066 offsetof(struct iwl_tx_cmd, scratch);
1067
1068 /* take back ownership of DMA buffer to enable update */
d5934110 1069 dma_sync_single_for_cpu(priv->bus->dev, txcmd_phys, firstlen,
47c1b496
EG		 1070 DMA_BIDIRECTIONAL);
1071 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1072 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1073
1074 IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
1075 le16_to_cpu(dev_cmd->hdr.sequence));
1076 IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1077 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1078 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1079
1080 /* Set up entry for this TFD in Tx byte-count array */
1081 if (ampdu)
48d42c42 1082 iwl_trans_txq_update_byte_cnt_tbl(priv, txq,
47c1b496
EG		 1083 le16_to_cpu(tx_cmd->len));
1084
d5934110 1085 dma_sync_single_for_device(priv->bus->dev, txcmd_phys, firstlen,
47c1b496
EG		 1086 DMA_BIDIRECTIONAL);
1087
1088 trace_iwlwifi_dev_tx(priv,
1089 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1090 sizeof(struct iwl_tfd),
1091 &dev_cmd->hdr, firstlen,
1092 skb->data + hdr_len, secondlen);
1093
1094 /* Tell device the write index *just past* this latest filled TFD */
1095 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1096 iwl_txq_update_write_ptr(priv, txq);
1097
1098 /*
1099 * At this point the frame is "transmitted" successfully
1100 * and we will get a TX status notification eventually,
1101 * regardless of the value of ret. "ret" only indicates
1102 * whether or not we should update the write pointer.
1103 */
1104 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
1105 if (wait_write_ptr) {
1106 txq->need_update = 1;
1107 iwl_txq_update_write_ptr(priv, txq);
1108 } else {
1109 iwl_stop_queue(priv, txq);
1110 }
1111 }
1112 return 0;
1113}
1114
e6bb4c9c 1115static void iwl_trans_pcie_kick_nic(struct iwl_priv *priv)
56d90f4c
EG		 1116{
1117 /* Remove all resets to allow NIC to operate */
1118 iwl_write32(priv, CSR_RESET, 0);
1119}
1120
e6bb4c9c
EG		 1121static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1122{
1123 struct iwl_priv *priv = priv(trans);
1124 int err;
1125
1126 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
1127 iwl_irq_tasklet, (unsigned long)priv);
1128
1129 iwl_alloc_isr_ict(priv);
1130
1131 err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
1132 DRV_NAME, priv);
1133 if (err) {
1134 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->bus->irq);
1135 iwl_free_isr_ict(priv);
1136 return err;
1137 }
1138
1139 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
1140 return 0;
1141}
1142
1143static void iwl_trans_pcie_sync_irq(struct iwl_priv *priv)
a27367d2
EG		 1144{
1145 /* wait to make sure we flush pending tasklet*/
d5934110 1146 synchronize_irq(priv->bus->irq);
a27367d2
EG		 1147 tasklet_kill(&priv->irq_tasklet);
1148}
1149
e6bb4c9c 1150static void iwl_trans_pcie_free(struct iwl_priv *priv)
34c1b7ba 1151{
d5934110 1152 free_irq(priv->bus->irq, priv);
34c1b7ba 1153 iwl_free_isr_ict(priv);
e6bb4c9c
EG		 1154 kfree(trans(priv));
1155 trans(priv) = NULL;
34c1b7ba
EG		 1156}
1157
e6bb4c9c 1158const struct iwl_trans_ops trans_ops_pcie;
e419d62d 1159
e6bb4c9c
EG		 1160static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
1161{
1162 struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
1163 sizeof(struct iwl_trans_pcie),
1164 GFP_KERNEL);
1165 if (iwl_trans) {
1166 iwl_trans->ops = &trans_ops_pcie;
1167 iwl_trans->shrd = shrd;
1168 }
ab6cf8e8 1169
e6bb4c9c
EG		 1170 return iwl_trans;
1171}
47c1b496 1172
87e5666c
EG		 1173#ifdef CONFIG_IWLWIFI_DEBUGFS
1174/* create and remove of files */
1175#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1176 if (!debugfs_create_file(#name, mode, parent, priv, \
1177 &iwl_dbgfs_##name##_ops)) \
1178 return -ENOMEM; \
1179} while (0)
1180
1181/* file operation */
1182#define DEBUGFS_READ_FUNC(name) \
1183static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1184 char __user *user_buf, \
1185 size_t count, loff_t *ppos);
1186
1187#define DEBUGFS_WRITE_FUNC(name) \
1188static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1189 const char __user *user_buf, \
1190 size_t count, loff_t *ppos);
1191
1192
1193static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1194{
1195 file->private_data = inode->i_private;
1196 return 0;
1197}
1198
1199#define DEBUGFS_READ_FILE_OPS(name) \
1200 DEBUGFS_READ_FUNC(name); \
1201static const struct file_operations iwl_dbgfs_##name##_ops = { \
1202 .read = iwl_dbgfs_##name##_read, \
1203 .open = iwl_dbgfs_open_file_generic, \
1204 .llseek = generic_file_llseek, \
1205};
1206
1207#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1208 DEBUGFS_READ_FUNC(name); \
1209 DEBUGFS_WRITE_FUNC(name); \
1210static const struct file_operations iwl_dbgfs_##name##_ops = { \
1211 .write = iwl_dbgfs_##name##_write, \
1212 .read = iwl_dbgfs_##name##_read, \
1213 .open = iwl_dbgfs_open_file_generic, \
1214 .llseek = generic_file_llseek, \
1215};
1216
1217static ssize_t iwl_dbgfs_traffic_log_read(struct file *file,
1218 char __user *user_buf,
1219 size_t count, loff_t *ppos)
1220{
1221 struct iwl_priv *priv = file->private_data;
1222 int pos = 0, ofs = 0;
1223 int cnt = 0, entry;
1224 struct iwl_tx_queue *txq;
1225 struct iwl_queue *q;
1226 struct iwl_rx_queue *rxq = &priv->rxq;
1227 char *buf;
1228 int bufsz = ((IWL_TRAFFIC_ENTRIES * IWL_TRAFFIC_ENTRY_SIZE * 64) * 2) +
1229 (priv->cfg->base_params->num_of_queues * 32 * 8) + 400;
1230 const u8 *ptr;
1231 ssize_t ret;
1232
1233 if (!priv->txq) {
1234 IWL_ERR(priv, "txq not ready\n");
1235 return -EAGAIN;
1236 }
1237 buf = kzalloc(bufsz, GFP_KERNEL);
1238 if (!buf) {
1239 IWL_ERR(priv, "Can not allocate buffer\n");
1240 return -ENOMEM;
1241 }
1242 pos += scnprintf(buf + pos, bufsz - pos, "Tx Queue\n");
1243 for (cnt = 0; cnt < hw_params(priv).max_txq_num; cnt++) {
1244 txq = &priv->txq[cnt];
1245 q = &txq->q;
1246 pos += scnprintf(buf + pos, bufsz - pos,
1247 "q[%d]: read_ptr: %u, write_ptr: %u\n",
1248 cnt, q->read_ptr, q->write_ptr);
1249 }
1250 if (priv->tx_traffic &&
1251 (iwl_get_debug_level(priv->shrd) & IWL_DL_TX)) {
1252 ptr = priv->tx_traffic;
1253 pos += scnprintf(buf + pos, bufsz - pos,
1254 "Tx Traffic idx: %u\n", priv->tx_traffic_idx);
1255 for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) {
1256 for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16;
1257 entry++, ofs += 16) {
1258 pos += scnprintf(buf + pos, bufsz - pos,
1259 "0x%.4x ", ofs);
1260 hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
1261 buf + pos, bufsz - pos, 0);
1262 pos += strlen(buf + pos);
1263 if (bufsz - pos > 0)
1264 buf[pos++] = '\n';
1265 }
1266 }
1267 }
1268
1269 pos += scnprintf(buf + pos, bufsz - pos, "Rx Queue\n");
1270 pos += scnprintf(buf + pos, bufsz - pos,
1271 "read: %u, write: %u\n",
1272 rxq->read, rxq->write);
1273
1274 if (priv->rx_traffic &&
1275 (iwl_get_debug_level(priv->shrd) & IWL_DL_RX)) {
1276 ptr = priv->rx_traffic;
1277 pos += scnprintf(buf + pos, bufsz - pos,
1278 "Rx Traffic idx: %u\n", priv->rx_traffic_idx);
1279 for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) {
1280 for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16;
1281 entry++, ofs += 16) {
1282 pos += scnprintf(buf + pos, bufsz - pos,
1283 "0x%.4x ", ofs);
1284 hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
1285 buf + pos, bufsz - pos, 0);
1286 pos += strlen(buf + pos);
1287 if (bufsz - pos > 0)
1288 buf[pos++] = '\n';
1289 }
1290 }
1291 }
1292
1293 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1294 kfree(buf);
1295 return ret;
1296}
1297
1298static ssize_t iwl_dbgfs_traffic_log_write(struct file *file,
1299 const char __user *user_buf,
1300 size_t count, loff_t *ppos)
1301{
1302 struct iwl_priv *priv = file->private_data;
1303 char buf[8];
1304 int buf_size;
1305 int traffic_log;
1306
1307 memset(buf, 0, sizeof(buf));
1308 buf_size = min(count, sizeof(buf) - 1);
1309 if (copy_from_user(buf, user_buf, buf_size))
1310 return -EFAULT;
1311 if (sscanf(buf, "%d", &traffic_log) != 1)
1312 return -EFAULT;
1313 if (traffic_log == 0)
1314 iwl_reset_traffic_log(priv);
1315
1316 return count;
1317}
1318
1319static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1320 char __user *user_buf,
1321 size_t count, loff_t *ppos) {
1322
1323 struct iwl_priv *priv = file->private_data;
1324 struct iwl_tx_queue *txq;
1325 struct iwl_queue *q;
1326 char *buf;
1327 int pos = 0;
1328 int cnt;
1329 int ret;
1330 const size_t bufsz = sizeof(char) * 64 *
1331 priv->cfg->base_params->num_of_queues;
1332
1333 if (!priv->txq) {
1334 IWL_ERR(priv, "txq not ready\n");
1335 return -EAGAIN;
1336 }
1337 buf = kzalloc(bufsz, GFP_KERNEL);
1338 if (!buf)
1339 return -ENOMEM;
1340
1341 for (cnt = 0; cnt < hw_params(priv).max_txq_num; cnt++) {
1342 txq = &priv->txq[cnt];
1343 q = &txq->q;
1344 pos += scnprintf(buf + pos, bufsz - pos,
1345 "hwq %.2d: read=%u write=%u stop=%d"
1346 " swq_id=%#.2x (ac %d/hwq %d)\n",
1347 cnt, q->read_ptr, q->write_ptr,
1348 !!test_bit(cnt, priv->queue_stopped),
1349 txq->swq_id, txq->swq_id & 3,
1350 (txq->swq_id >> 2) & 0x1f);
1351 if (cnt >= 4)
1352 continue;
1353 /* for the ACs, display the stop count too */
1354 pos += scnprintf(buf + pos, bufsz - pos,
1355 " stop-count: %d\n",
1356 atomic_read(&priv->queue_stop_count[cnt]));
1357 }
1358 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1359 kfree(buf);
1360 return ret;
1361}
1362
1363static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1364 char __user *user_buf,
1365 size_t count, loff_t *ppos) {
1366 struct iwl_priv *priv = file->private_data;
1367 struct iwl_rx_queue *rxq = &priv->rxq;
1368 char buf[256];
1369 int pos = 0;
1370 const size_t bufsz = sizeof(buf);
1371
1372 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1373 rxq->read);
1374 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1375 rxq->write);
1376 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1377 rxq->free_count);
1378 if (rxq->rb_stts) {
1379 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1380 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1381 } else {
1382 pos += scnprintf(buf + pos, bufsz - pos,
1383 "closed_rb_num: Not Allocated\n");
1384 }
1385 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1386}
1387
1388DEBUGFS_READ_WRITE_FILE_OPS(traffic_log);
1389DEBUGFS_READ_FILE_OPS(rx_queue);
1390DEBUGFS_READ_FILE_OPS(tx_queue);
1391
1392/*
1393 * Create the debugfs files and directories
1394 *
1395 */
1396static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1397 struct dentry *dir)
1398{
1399 struct iwl_priv *priv = priv(trans);
1400
1401 DEBUGFS_ADD_FILE(traffic_log, dir, S_IWUSR | S_IRUSR);
1402 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1403 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1404 return 0;
1405}
1406#else
1407static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1408 struct dentry *dir)
1409{ return 0; }
1410
1411#endif /*CONFIG_IWLWIFI_DEBUGFS */
1412
e6bb4c9c
EG		 1413const struct iwl_trans_ops trans_ops_pcie = {
1414 .alloc = iwl_trans_pcie_alloc,
1415 .request_irq = iwl_trans_pcie_request_irq,
1416 .start_device = iwl_trans_pcie_start_device,
1417 .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
1418 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 1419
e6bb4c9c 1420 .tx_start = iwl_trans_pcie_tx_start,
48d42c42 1421
e6bb4c9c
EG		 1422 .rx_free = iwl_trans_pcie_rx_free,
1423 .tx_free = iwl_trans_pcie_tx_free,
34c1b7ba 1424
e6bb4c9c
EG		 1425 .send_cmd = iwl_trans_pcie_send_cmd,
1426 .send_cmd_pdu = iwl_trans_pcie_send_cmd_pdu,
c85eb619 1427
e6bb4c9c
EG		 1428 .get_tx_cmd = iwl_trans_pcie_get_tx_cmd,
1429 .tx = iwl_trans_pcie_tx,
34c1b7ba 1430
e6bb4c9c
EG		 1431 .txq_agg_disable = iwl_trans_pcie_txq_agg_disable,
1432 .txq_agg_setup = iwl_trans_pcie_txq_agg_setup,
34c1b7ba 1433
e6bb4c9c 1434 .kick_nic = iwl_trans_pcie_kick_nic,
1e89cbac 1435
e6bb4c9c
EG		 1436 .sync_irq = iwl_trans_pcie_sync_irq,
1437 .free = iwl_trans_pcie_free,
87e5666c
EG		 1438
1439 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
e6bb4c9c 1440};
ab697a9f 1441
Linux kernel - Deliverables
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