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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
fd4abac5 | 30 | #include <linux/etherdevice.h> |
d43c36dc | 31 | #include <linux/sched.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
1053d35f RR |
33 | #include <net/mac80211.h> |
34 | #include "iwl-eeprom.h" | |
35 | #include "iwl-dev.h" | |
36 | #include "iwl-core.h" | |
37 | #include "iwl-sta.h" | |
38 | #include "iwl-io.h" | |
39 | #include "iwl-helpers.h" | |
40 | ||
fd4abac5 TW |
41 | /** |
42 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
43 | */ | |
7bfedc59 | 44 | void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
fd4abac5 TW |
45 | { |
46 | u32 reg = 0; | |
fd4abac5 TW |
47 | int txq_id = txq->q.id; |
48 | ||
49 | if (txq->need_update == 0) | |
7bfedc59 | 50 | return; |
fd4abac5 TW |
51 | |
52 | /* if we're trying to save power */ | |
53 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
54 | /* wake up nic if it's powered down ... | |
55 | * uCode will wake up, and interrupt us again, so next | |
56 | * time we'll skip this part. */ | |
57 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
58 | ||
59 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
309e731a BC |
60 | IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", |
61 | txq_id, reg); | |
fd4abac5 TW |
62 | iwl_set_bit(priv, CSR_GP_CNTRL, |
63 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
7bfedc59 | 64 | return; |
fd4abac5 TW |
65 | } |
66 | ||
fd4abac5 TW |
67 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
68 | txq->q.write_ptr | (txq_id << 8)); | |
fd4abac5 TW |
69 | |
70 | /* else not in power-save mode, uCode will never sleep when we're | |
71 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
72 | } else | |
73 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
74 | txq->q.write_ptr | (txq_id << 8)); | |
75 | ||
76 | txq->need_update = 0; | |
fd4abac5 TW |
77 | } |
78 | EXPORT_SYMBOL(iwl_txq_update_write_ptr); | |
79 | ||
1053d35f RR |
80 | /** |
81 | * iwl_tx_queue_free - Deallocate DMA queue. | |
82 | * @txq: Transmit queue to deallocate. | |
83 | * | |
84 | * Empty queue by removing and destroying all BD's. | |
85 | * Free all buffers. | |
86 | * 0-fill, but do not free "txq" descriptor structure. | |
87 | */ | |
a8e74e27 | 88 | void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id) |
1053d35f | 89 | { |
da99c4b6 | 90 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; |
443cfd45 | 91 | struct iwl_queue *q = &txq->q; |
f36d04ab | 92 | struct device *dev = &priv->pci_dev->dev; |
71c55d90 | 93 | int i; |
1053d35f RR |
94 | |
95 | if (q->n_bd == 0) | |
96 | return; | |
97 | ||
98 | /* first, empty all BD's */ | |
99 | for (; q->write_ptr != q->read_ptr; | |
100 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) | |
7aaa1d79 | 101 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); |
1053d35f | 102 | |
1053d35f | 103 | /* De-alloc array of command/tx buffers */ |
961ba60a | 104 | for (i = 0; i < TFD_TX_CMD_SLOTS; i++) |
da99c4b6 | 105 | kfree(txq->cmd[i]); |
1053d35f RR |
106 | |
107 | /* De-alloc circular buffer of TFDs */ | |
108 | if (txq->q.n_bd) | |
f36d04ab SG |
109 | dma_free_coherent(dev, priv->hw_params.tfd_size * |
110 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
1053d35f RR |
111 | |
112 | /* De-alloc array of per-TFD driver data */ | |
113 | kfree(txq->txb); | |
114 | txq->txb = NULL; | |
115 | ||
c2acea8e JB |
116 | /* deallocate arrays */ |
117 | kfree(txq->cmd); | |
118 | kfree(txq->meta); | |
119 | txq->cmd = NULL; | |
120 | txq->meta = NULL; | |
121 | ||
1053d35f RR |
122 | /* 0-fill queue descriptor structure */ |
123 | memset(txq, 0, sizeof(*txq)); | |
124 | } | |
a8e74e27 | 125 | EXPORT_SYMBOL(iwl_tx_queue_free); |
961ba60a TW |
126 | |
127 | /** | |
128 | * iwl_cmd_queue_free - Deallocate DMA queue. | |
129 | * @txq: Transmit queue to deallocate. | |
130 | * | |
131 | * Empty queue by removing and destroying all BD's. | |
132 | * Free all buffers. | |
133 | * 0-fill, but do not free "txq" descriptor structure. | |
134 | */ | |
3e5d238f | 135 | void iwl_cmd_queue_free(struct iwl_priv *priv) |
961ba60a | 136 | { |
13bb9483 | 137 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; |
961ba60a | 138 | struct iwl_queue *q = &txq->q; |
f36d04ab | 139 | struct device *dev = &priv->pci_dev->dev; |
71c55d90 | 140 | int i; |
dd487449 | 141 | bool huge = false; |
961ba60a TW |
142 | |
143 | if (q->n_bd == 0) | |
144 | return; | |
145 | ||
dd487449 ZY |
146 | for (; q->read_ptr != q->write_ptr; |
147 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
148 | /* we have no way to tell if it is a huge cmd ATM */ | |
149 | i = get_cmd_index(q, q->read_ptr, 0); | |
150 | ||
151 | if (txq->meta[i].flags & CMD_SIZE_HUGE) { | |
152 | huge = true; | |
153 | continue; | |
154 | } | |
155 | ||
156 | pci_unmap_single(priv->pci_dev, | |
2e724443 FT |
157 | dma_unmap_addr(&txq->meta[i], mapping), |
158 | dma_unmap_len(&txq->meta[i], len), | |
dd487449 ZY |
159 | PCI_DMA_BIDIRECTIONAL); |
160 | } | |
161 | if (huge) { | |
162 | i = q->n_window; | |
163 | pci_unmap_single(priv->pci_dev, | |
2e724443 FT |
164 | dma_unmap_addr(&txq->meta[i], mapping), |
165 | dma_unmap_len(&txq->meta[i], len), | |
dd487449 ZY |
166 | PCI_DMA_BIDIRECTIONAL); |
167 | } | |
168 | ||
961ba60a TW |
169 | /* De-alloc array of command/tx buffers */ |
170 | for (i = 0; i <= TFD_CMD_SLOTS; i++) | |
171 | kfree(txq->cmd[i]); | |
172 | ||
173 | /* De-alloc circular buffer of TFDs */ | |
174 | if (txq->q.n_bd) | |
f36d04ab SG |
175 | dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd, |
176 | txq->tfds, txq->q.dma_addr); | |
961ba60a | 177 | |
28142986 RC |
178 | /* deallocate arrays */ |
179 | kfree(txq->cmd); | |
180 | kfree(txq->meta); | |
181 | txq->cmd = NULL; | |
182 | txq->meta = NULL; | |
183 | ||
961ba60a TW |
184 | /* 0-fill queue descriptor structure */ |
185 | memset(txq, 0, sizeof(*txq)); | |
186 | } | |
3e5d238f AK |
187 | EXPORT_SYMBOL(iwl_cmd_queue_free); |
188 | ||
fd4abac5 TW |
189 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
190 | * DMA services | |
191 | * | |
192 | * Theory of operation | |
193 | * | |
194 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
195 | * of buffer descriptors, each of which points to one or more data buffers for | |
196 | * the device to read from or fill. Driver and device exchange status of each | |
197 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
198 | * entries in each circular buffer, to protect against confusing empty and full | |
199 | * queue states. | |
200 | * | |
201 | * The device reads or writes the data in the queues via the device's several | |
202 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
203 | * | |
204 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
205 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
206 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
207 | * Tx queue resumed. | |
208 | * | |
209 | * See more detailed info in iwl-4965-hw.h. | |
210 | ***************************************************/ | |
211 | ||
212 | int iwl_queue_space(const struct iwl_queue *q) | |
213 | { | |
214 | int s = q->read_ptr - q->write_ptr; | |
215 | ||
216 | if (q->read_ptr > q->write_ptr) | |
217 | s -= q->n_bd; | |
218 | ||
219 | if (s <= 0) | |
220 | s += q->n_window; | |
221 | /* keep some reserve to not confuse empty and full situations */ | |
222 | s -= 2; | |
223 | if (s < 0) | |
224 | s = 0; | |
225 | return s; | |
226 | } | |
227 | EXPORT_SYMBOL(iwl_queue_space); | |
228 | ||
229 | ||
1053d35f RR |
230 | /** |
231 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
232 | */ | |
443cfd45 | 233 | static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
234 | int count, int slots_num, u32 id) |
235 | { | |
236 | q->n_bd = count; | |
237 | q->n_window = slots_num; | |
238 | q->id = id; | |
239 | ||
240 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
241 | * and iwl_queue_dec_wrap are broken. */ | |
242 | BUG_ON(!is_power_of_2(count)); | |
243 | ||
244 | /* slots_num must be power-of-two size, otherwise | |
245 | * get_cmd_index is broken. */ | |
246 | BUG_ON(!is_power_of_2(slots_num)); | |
247 | ||
248 | q->low_mark = q->n_window / 4; | |
249 | if (q->low_mark < 4) | |
250 | q->low_mark = 4; | |
251 | ||
252 | q->high_mark = q->n_window / 8; | |
253 | if (q->high_mark < 2) | |
254 | q->high_mark = 2; | |
255 | ||
256 | q->write_ptr = q->read_ptr = 0; | |
b74e31a9 WYG |
257 | q->last_read_ptr = 0; |
258 | q->repeat_same_read_ptr = 0; | |
1053d35f RR |
259 | |
260 | return 0; | |
261 | } | |
262 | ||
263 | /** | |
264 | * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
265 | */ | |
266 | static int iwl_tx_queue_alloc(struct iwl_priv *priv, | |
16466903 | 267 | struct iwl_tx_queue *txq, u32 id) |
1053d35f | 268 | { |
f36d04ab | 269 | struct device *dev = &priv->pci_dev->dev; |
3978e5bc | 270 | size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; |
1053d35f RR |
271 | |
272 | /* Driver private data, only for Tx (not command) queues, | |
273 | * not shared with device. */ | |
13bb9483 | 274 | if (id != priv->cmd_queue) { |
519c7c41 | 275 | txq->txb = kzalloc(sizeof(txq->txb[0]) * |
1053d35f RR |
276 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); |
277 | if (!txq->txb) { | |
15b1687c | 278 | IWL_ERR(priv, "kmalloc for auxiliary BD " |
1053d35f RR |
279 | "structures failed\n"); |
280 | goto error; | |
281 | } | |
3978e5bc | 282 | } else { |
1053d35f | 283 | txq->txb = NULL; |
3978e5bc | 284 | } |
1053d35f RR |
285 | |
286 | /* Circular buffer of transmit frame descriptors (TFDs), | |
287 | * shared with device */ | |
f36d04ab SG |
288 | txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, |
289 | GFP_KERNEL); | |
499b1883 | 290 | if (!txq->tfds) { |
3978e5bc | 291 | IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz); |
1053d35f RR |
292 | goto error; |
293 | } | |
294 | txq->q.id = id; | |
295 | ||
296 | return 0; | |
297 | ||
298 | error: | |
299 | kfree(txq->txb); | |
300 | txq->txb = NULL; | |
301 | ||
302 | return -ENOMEM; | |
303 | } | |
304 | ||
1053d35f RR |
305 | /** |
306 | * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue | |
307 | */ | |
a8e74e27 SO |
308 | int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
309 | int slots_num, u32 txq_id) | |
1053d35f | 310 | { |
da99c4b6 | 311 | int i, len; |
73b7d742 | 312 | int ret; |
c2acea8e | 313 | int actual_slots = slots_num; |
1053d35f RR |
314 | |
315 | /* | |
316 | * Alloc buffer array for commands (Tx or other types of commands). | |
13bb9483 | 317 | * For the command queue (#4/#9), allocate command space + one big |
1053d35f RR |
318 | * command for scan, since scan command is very huge; the system will |
319 | * not have two scans at the same time, so only one is needed. | |
320 | * For normal Tx queues (all other queues), no super-size command | |
321 | * space is needed. | |
322 | */ | |
13bb9483 | 323 | if (txq_id == priv->cmd_queue) |
c2acea8e JB |
324 | actual_slots++; |
325 | ||
326 | txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots, | |
327 | GFP_KERNEL); | |
328 | txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots, | |
329 | GFP_KERNEL); | |
330 | ||
331 | if (!txq->meta || !txq->cmd) | |
332 | goto out_free_arrays; | |
333 | ||
334 | len = sizeof(struct iwl_device_cmd); | |
335 | for (i = 0; i < actual_slots; i++) { | |
336 | /* only happens for cmd queue */ | |
337 | if (i == slots_num) | |
89612124 | 338 | len = IWL_MAX_CMD_SIZE; |
da99c4b6 | 339 | |
49898852 | 340 | txq->cmd[i] = kmalloc(len, GFP_KERNEL); |
da99c4b6 | 341 | if (!txq->cmd[i]) |
73b7d742 | 342 | goto err; |
da99c4b6 | 343 | } |
1053d35f RR |
344 | |
345 | /* Alloc driver data array and TFD circular buffer */ | |
73b7d742 TW |
346 | ret = iwl_tx_queue_alloc(priv, txq, txq_id); |
347 | if (ret) | |
348 | goto err; | |
1053d35f | 349 | |
1053d35f RR |
350 | txq->need_update = 0; |
351 | ||
1a716557 JB |
352 | /* |
353 | * Aggregation TX queues will get their ID when aggregation begins; | |
354 | * they overwrite the setting done here. The command FIFO doesn't | |
355 | * need an swq_id so don't set one to catch errors, all others can | |
356 | * be set up to the identity mapping. | |
357 | */ | |
13bb9483 | 358 | if (txq_id != priv->cmd_queue) |
45af8195 JB |
359 | txq->swq_id = txq_id; |
360 | ||
1053d35f RR |
361 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise |
362 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
363 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
364 | ||
365 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
366 | iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
367 | ||
368 | /* Tell device where to find queue */ | |
a8e74e27 | 369 | priv->cfg->ops->lib->txq_init(priv, txq); |
1053d35f RR |
370 | |
371 | return 0; | |
73b7d742 | 372 | err: |
c2acea8e | 373 | for (i = 0; i < actual_slots; i++) |
73b7d742 | 374 | kfree(txq->cmd[i]); |
c2acea8e JB |
375 | out_free_arrays: |
376 | kfree(txq->meta); | |
377 | kfree(txq->cmd); | |
73b7d742 | 378 | |
73b7d742 | 379 | return -ENOMEM; |
1053d35f | 380 | } |
a8e74e27 SO |
381 | EXPORT_SYMBOL(iwl_tx_queue_init); |
382 | ||
de0f60ea ZY |
383 | void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
384 | int slots_num, u32 txq_id) | |
385 | { | |
386 | int actual_slots = slots_num; | |
387 | ||
13bb9483 | 388 | if (txq_id == priv->cmd_queue) |
de0f60ea ZY |
389 | actual_slots++; |
390 | ||
391 | memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots); | |
392 | ||
393 | txq->need_update = 0; | |
394 | ||
395 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
396 | iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
397 | ||
398 | /* Tell device where to find queue */ | |
399 | priv->cfg->ops->lib->txq_init(priv, txq); | |
400 | } | |
401 | EXPORT_SYMBOL(iwl_tx_queue_reset); | |
402 | ||
fd4abac5 TW |
403 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
404 | ||
405 | /** | |
406 | * iwl_enqueue_hcmd - enqueue a uCode command | |
407 | * @priv: device private data point | |
408 | * @cmd: a point to the ucode command structure | |
409 | * | |
410 | * The function returns < 0 values to indicate the operation is | |
411 | * failed. On success, it turns the index (> 0) of command in the | |
412 | * command queue. | |
413 | */ | |
414 | int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
415 | { | |
13bb9483 | 416 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; |
fd4abac5 | 417 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
418 | struct iwl_device_cmd *out_cmd; |
419 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 420 | dma_addr_t phys_addr; |
fd4abac5 | 421 | unsigned long flags; |
7bfedc59 | 422 | int len; |
f3674227 TW |
423 | u32 idx; |
424 | u16 fix_size; | |
0975cc8f | 425 | bool is_ct_kill = false; |
fd4abac5 TW |
426 | |
427 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); | |
428 | fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
429 | ||
430 | /* If any of the command structures end up being larger than | |
431 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
89612124 AK |
432 | * we will need to increase the size of the TFD entries |
433 | * Also, check to see if command buffer should not exceed the size | |
434 | * of device_cmd and max_cmd_size. */ | |
fd4abac5 | 435 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && |
c2acea8e | 436 | !(cmd->flags & CMD_SIZE_HUGE)); |
89612124 | 437 | BUG_ON(fix_size > IWL_MAX_CMD_SIZE); |
fd4abac5 | 438 | |
7812b167 | 439 | if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) { |
f2f21b49 RC |
440 | IWL_WARN(priv, "Not sending command - %s KILL\n", |
441 | iwl_is_rfkill(priv) ? "RF" : "CT"); | |
fd4abac5 TW |
442 | return -EIO; |
443 | } | |
444 | ||
c2acea8e | 445 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
2d237f71 | 446 | IWL_ERR(priv, "No space in command queue\n"); |
0975cc8f WYG |
447 | if (priv->cfg->ops->lib->tt_ops.ct_kill_check) { |
448 | is_ct_kill = | |
449 | priv->cfg->ops->lib->tt_ops.ct_kill_check(priv); | |
450 | } | |
451 | if (!is_ct_kill) { | |
7812b167 WYG |
452 | IWL_ERR(priv, "Restarting adapter due to queue full\n"); |
453 | queue_work(priv->workqueue, &priv->restart); | |
454 | } | |
fd4abac5 TW |
455 | return -ENOSPC; |
456 | } | |
457 | ||
458 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
459 | ||
dd487449 ZY |
460 | /* If this is a huge cmd, mark the huge flag also on the meta.flags |
461 | * of the _original_ cmd. This is used for DMA mapping clean up. | |
462 | */ | |
463 | if (cmd->flags & CMD_SIZE_HUGE) { | |
464 | idx = get_cmd_index(q, q->write_ptr, 0); | |
465 | txq->meta[idx].flags = CMD_SIZE_HUGE; | |
466 | } | |
467 | ||
c2acea8e | 468 | idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE); |
da99c4b6 | 469 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
470 | out_meta = &txq->meta[idx]; |
471 | ||
8ce73f3a | 472 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
473 | out_meta->flags = cmd->flags; |
474 | if (cmd->flags & CMD_WANT_SKB) | |
475 | out_meta->source = cmd; | |
476 | if (cmd->flags & CMD_ASYNC) | |
477 | out_meta->callback = cmd->callback; | |
fd4abac5 TW |
478 | |
479 | out_cmd->hdr.cmd = cmd->id; | |
fd4abac5 TW |
480 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); |
481 | ||
482 | /* At this point, the out_cmd now has all of the incoming cmd | |
483 | * information */ | |
484 | ||
485 | out_cmd->hdr.flags = 0; | |
13bb9483 | 486 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) | |
fd4abac5 | 487 | INDEX_TO_SEQ(q->write_ptr)); |
c2acea8e | 488 | if (cmd->flags & CMD_SIZE_HUGE) |
9734cb23 | 489 | out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; |
c2acea8e | 490 | len = sizeof(struct iwl_device_cmd); |
89612124 AK |
491 | if (idx == TFD_CMD_SLOTS) |
492 | len = IWL_MAX_CMD_SIZE; | |
fd4abac5 | 493 | |
ded2ae7c EK |
494 | #ifdef CONFIG_IWLWIFI_DEBUG |
495 | switch (out_cmd->hdr.cmd) { | |
496 | case REPLY_TX_LINK_QUALITY_CMD: | |
497 | case SENSITIVITY_CMD: | |
e1623446 | 498 | IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
499 | "%d bytes at %d[%d]:%d\n", |
500 | get_cmd_string(out_cmd->hdr.cmd), | |
501 | out_cmd->hdr.cmd, | |
502 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
13bb9483 JB |
503 | q->write_ptr, idx, priv->cmd_queue); |
504 | break; | |
ded2ae7c | 505 | default: |
e1623446 | 506 | IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
507 | "%d bytes at %d[%d]:%d\n", |
508 | get_cmd_string(out_cmd->hdr.cmd), | |
509 | out_cmd->hdr.cmd, | |
510 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
13bb9483 | 511 | q->write_ptr, idx, priv->cmd_queue); |
ded2ae7c EK |
512 | } |
513 | #endif | |
fd4abac5 TW |
514 | txq->need_update = 1; |
515 | ||
518099a8 SO |
516 | if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl) |
517 | /* Set up entry in queue's byte count circular buffer */ | |
518 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); | |
fd4abac5 | 519 | |
df833b1d RC |
520 | phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr, |
521 | fix_size, PCI_DMA_BIDIRECTIONAL); | |
2e724443 FT |
522 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
523 | dma_unmap_len_set(out_meta, len, fix_size); | |
df833b1d | 524 | |
be1a71a1 JB |
525 | trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags); |
526 | ||
df833b1d RC |
527 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
528 | phys_addr, fix_size, 1, | |
529 | U32_PAD(cmd->len)); | |
530 | ||
fd4abac5 TW |
531 | /* Increment and update queue's write index */ |
532 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
7bfedc59 | 533 | iwl_txq_update_write_ptr(priv, txq); |
fd4abac5 TW |
534 | |
535 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
7bfedc59 | 536 | return idx; |
fd4abac5 TW |
537 | } |
538 | ||
17b88929 TW |
539 | /** |
540 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
541 | * | |
542 | * When FW advances 'R' index, all entries between old and new 'R' index | |
543 | * need to be reclaimed. As result, some free space forms. If there is | |
544 | * enough free space (> low mark), wake the stack that feeds us. | |
545 | */ | |
499b1883 TW |
546 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, |
547 | int idx, int cmd_idx) | |
17b88929 TW |
548 | { |
549 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
550 | struct iwl_queue *q = &txq->q; | |
551 | int nfreed = 0; | |
552 | ||
499b1883 | 553 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
15b1687c | 554 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
17b88929 | 555 | "is out of range [0-%d] %d %d.\n", txq_id, |
499b1883 | 556 | idx, q->n_bd, q->write_ptr, q->read_ptr); |
17b88929 TW |
557 | return; |
558 | } | |
559 | ||
499b1883 TW |
560 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
561 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 562 | |
499b1883 | 563 | if (nfreed++ > 0) { |
15b1687c | 564 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 TW |
565 | q->write_ptr, q->read_ptr); |
566 | queue_work(priv->workqueue, &priv->restart); | |
567 | } | |
da99c4b6 | 568 | |
17b88929 TW |
569 | } |
570 | } | |
571 | ||
572 | /** | |
573 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
574 | * @rxb: Rx buffer to reclaim | |
575 | * | |
576 | * If an Rx buffer has an async callback associated with it the callback | |
577 | * will be executed. The attached skb (if present) will only be freed | |
578 | * if the callback returns 1 | |
579 | */ | |
580 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
581 | { | |
2f301227 | 582 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
583 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
584 | int txq_id = SEQ_TO_QUEUE(sequence); | |
585 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 586 | int cmd_index; |
9734cb23 | 587 | bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); |
c2acea8e JB |
588 | struct iwl_device_cmd *cmd; |
589 | struct iwl_cmd_meta *meta; | |
13bb9483 | 590 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; |
17b88929 TW |
591 | |
592 | /* If a Tx command is being handled and it isn't in the actual | |
593 | * command queue then there a command routing bug has been introduced | |
594 | * in the queue management code. */ | |
13bb9483 JB |
595 | if (WARN(txq_id != priv->cmd_queue, |
596 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", | |
597 | txq_id, priv->cmd_queue, sequence, | |
598 | priv->txq[priv->cmd_queue].q.read_ptr, | |
599 | priv->txq[priv->cmd_queue].q.write_ptr)) { | |
ec741164 | 600 | iwl_print_hex_error(priv, pkt, 32); |
55d6a3cd | 601 | return; |
01ef9323 | 602 | } |
17b88929 | 603 | |
dd487449 ZY |
604 | /* If this is a huge cmd, clear the huge flag on the meta.flags |
605 | * of the _original_ cmd. So that iwl_cmd_queue_free won't unmap | |
606 | * the DMA buffer for the scan (huge) command. | |
607 | */ | |
608 | if (huge) { | |
609 | cmd_index = get_cmd_index(&txq->q, index, 0); | |
610 | txq->meta[cmd_index].flags = 0; | |
611 | } | |
612 | cmd_index = get_cmd_index(&txq->q, index, huge); | |
613 | cmd = txq->cmd[cmd_index]; | |
614 | meta = &txq->meta[cmd_index]; | |
17b88929 | 615 | |
c33de625 | 616 | pci_unmap_single(priv->pci_dev, |
2e724443 FT |
617 | dma_unmap_addr(meta, mapping), |
618 | dma_unmap_len(meta, len), | |
c33de625 RC |
619 | PCI_DMA_BIDIRECTIONAL); |
620 | ||
17b88929 | 621 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 622 | if (meta->flags & CMD_WANT_SKB) { |
2f301227 ZY |
623 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); |
624 | rxb->page = NULL; | |
5696aea6 | 625 | } else if (meta->callback) |
2f301227 | 626 | meta->callback(priv, cmd, pkt); |
17b88929 | 627 | |
499b1883 | 628 | iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index); |
17b88929 | 629 | |
c2acea8e | 630 | if (!(meta->flags & CMD_ASYNC)) { |
17b88929 | 631 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); |
91dd6c27 | 632 | IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n", |
d2dfe6df | 633 | get_cmd_string(cmd->hdr.cmd)); |
17b88929 TW |
634 | wake_up_interruptible(&priv->wait_command_queue); |
635 | } | |
dd487449 | 636 | meta->flags = 0; |
17b88929 TW |
637 | } |
638 | EXPORT_SYMBOL(iwl_tx_cmd_complete); | |
639 | ||
994d31f7 | 640 | #ifdef CONFIG_IWLWIFI_DEBUG |
04569cbe WYG |
641 | #define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x |
642 | #define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x | |
a332f8d6 TW |
643 | |
644 | const char *iwl_get_tx_fail_reason(u32 status) | |
645 | { | |
646 | switch (status & TX_STATUS_MSK) { | |
647 | case TX_STATUS_SUCCESS: | |
648 | return "SUCCESS"; | |
04569cbe WYG |
649 | TX_STATUS_POSTPONE(DELAY); |
650 | TX_STATUS_POSTPONE(FEW_BYTES); | |
651 | TX_STATUS_POSTPONE(BT_PRIO); | |
652 | TX_STATUS_POSTPONE(QUIET_PERIOD); | |
653 | TX_STATUS_POSTPONE(CALC_TTAK); | |
654 | TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY); | |
655 | TX_STATUS_FAIL(SHORT_LIMIT); | |
656 | TX_STATUS_FAIL(LONG_LIMIT); | |
657 | TX_STATUS_FAIL(FIFO_UNDERRUN); | |
658 | TX_STATUS_FAIL(DRAIN_FLOW); | |
659 | TX_STATUS_FAIL(RFKILL_FLUSH); | |
660 | TX_STATUS_FAIL(LIFE_EXPIRE); | |
661 | TX_STATUS_FAIL(DEST_PS); | |
662 | TX_STATUS_FAIL(HOST_ABORTED); | |
663 | TX_STATUS_FAIL(BT_RETRY); | |
664 | TX_STATUS_FAIL(STA_INVALID); | |
665 | TX_STATUS_FAIL(FRAG_DROPPED); | |
666 | TX_STATUS_FAIL(TID_DISABLE); | |
667 | TX_STATUS_FAIL(FIFO_FLUSHED); | |
668 | TX_STATUS_FAIL(INSUFFICIENT_CF_POLL); | |
669 | TX_STATUS_FAIL(FW_DROP); | |
670 | TX_STATUS_FAIL(STA_COLOR_MISMATCH_DROP); | |
a332f8d6 TW |
671 | } |
672 | ||
673 | return "UNKNOWN"; | |
674 | } | |
675 | EXPORT_SYMBOL(iwl_get_tx_fail_reason); | |
676 | #endif /* CONFIG_IWLWIFI_DEBUG */ |