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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
901069c7 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
fd4abac5 | 30 | #include <linux/etherdevice.h> |
d43c36dc | 31 | #include <linux/sched.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
1053d35f RR |
33 | #include <net/mac80211.h> |
34 | #include "iwl-eeprom.h" | |
214d14d4 | 35 | #include "iwl-agn.h" |
1053d35f RR |
36 | #include "iwl-dev.h" |
37 | #include "iwl-core.h" | |
38 | #include "iwl-sta.h" | |
39 | #include "iwl-io.h" | |
40 | #include "iwl-helpers.h" | |
41 | ||
fd4abac5 TW |
42 | /** |
43 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
44 | */ | |
7bfedc59 | 45 | void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
fd4abac5 TW |
46 | { |
47 | u32 reg = 0; | |
fd4abac5 TW |
48 | int txq_id = txq->q.id; |
49 | ||
50 | if (txq->need_update == 0) | |
7bfedc59 | 51 | return; |
fd4abac5 | 52 | |
f81c1f48 WYG |
53 | if (priv->cfg->base_params->shadow_reg_enable) { |
54 | /* shadow register enabled */ | |
55 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
56 | txq->q.write_ptr | (txq_id << 8)); | |
57 | } else { | |
58 | /* if we're trying to save power */ | |
59 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
60 | /* wake up nic if it's powered down ... | |
61 | * uCode will wake up, and interrupt us again, so next | |
62 | * time we'll skip this part. */ | |
63 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
fd4abac5 | 64 | |
f81c1f48 WYG |
65 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
66 | IWL_DEBUG_INFO(priv, | |
67 | "Tx queue %d requesting wakeup," | |
68 | " GP1 = 0x%x\n", txq_id, reg); | |
69 | iwl_set_bit(priv, CSR_GP_CNTRL, | |
70 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
71 | return; | |
72 | } | |
fd4abac5 | 73 | |
f81c1f48 | 74 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
fd4abac5 | 75 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 76 | |
f81c1f48 WYG |
77 | /* |
78 | * else not in power-save mode, | |
79 | * uCode will never sleep when we're | |
80 | * trying to tx (during RFKILL, we're not trying to tx). | |
81 | */ | |
82 | } else | |
83 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
84 | txq->q.write_ptr | (txq_id << 8)); | |
85 | } | |
fd4abac5 | 86 | txq->need_update = 0; |
fd4abac5 | 87 | } |
fd4abac5 | 88 | |
214d14d4 JB |
89 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
90 | { | |
91 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
92 | ||
93 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
94 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
95 | addr |= | |
96 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
97 | ||
98 | return addr; | |
99 | } | |
100 | ||
101 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
102 | { | |
103 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
104 | ||
105 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
106 | } | |
107 | ||
108 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
109 | dma_addr_t addr, u16 len) | |
110 | { | |
111 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
112 | u16 hi_n_len = len << 4; | |
113 | ||
114 | put_unaligned_le32(addr, &tb->lo); | |
115 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
116 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
117 | ||
118 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
119 | ||
120 | tfd->num_tbs = idx + 1; | |
121 | } | |
122 | ||
123 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
124 | { | |
125 | return tfd->num_tbs & 0x1f; | |
126 | } | |
127 | ||
128 | /** | |
129 | * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
130 | * @priv - driver private data | |
131 | * @txq - tx queue | |
132 | * | |
133 | * Does NOT advance any TFD circular buffer read/write indexes | |
134 | * Does NOT free the TFD itself (which is within circular buffer) | |
135 | */ | |
136 | void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
137 | { | |
138 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; | |
139 | struct iwl_tfd *tfd; | |
140 | struct pci_dev *dev = priv->pci_dev; | |
141 | int index = txq->q.read_ptr; | |
142 | int i; | |
143 | int num_tbs; | |
144 | ||
145 | tfd = &tfd_tmp[index]; | |
146 | ||
147 | /* Sanity check on number of chunks */ | |
148 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
149 | ||
150 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
151 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
152 | /* @todo issue fatal error, it is quite serious situation */ | |
153 | return; | |
154 | } | |
155 | ||
156 | /* Unmap tx_cmd */ | |
157 | if (num_tbs) | |
158 | pci_unmap_single(dev, | |
159 | dma_unmap_addr(&txq->meta[index], mapping), | |
160 | dma_unmap_len(&txq->meta[index], len), | |
161 | PCI_DMA_BIDIRECTIONAL); | |
162 | ||
163 | /* Unmap chunks, if any. */ | |
164 | for (i = 1; i < num_tbs; i++) | |
165 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), | |
166 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
167 | ||
168 | /* free SKB */ | |
169 | if (txq->txb) { | |
170 | struct sk_buff *skb; | |
171 | ||
172 | skb = txq->txb[txq->q.read_ptr].skb; | |
173 | ||
174 | /* can be called from irqs-disabled context */ | |
175 | if (skb) { | |
176 | dev_kfree_skb_any(skb); | |
177 | txq->txb[txq->q.read_ptr].skb = NULL; | |
178 | } | |
179 | } | |
180 | } | |
181 | ||
182 | int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
183 | struct iwl_tx_queue *txq, | |
184 | dma_addr_t addr, u16 len, | |
185 | u8 reset, u8 pad) | |
186 | { | |
187 | struct iwl_queue *q; | |
188 | struct iwl_tfd *tfd, *tfd_tmp; | |
189 | u32 num_tbs; | |
190 | ||
191 | q = &txq->q; | |
192 | tfd_tmp = (struct iwl_tfd *)txq->tfds; | |
193 | tfd = &tfd_tmp[q->write_ptr]; | |
194 | ||
195 | if (reset) | |
196 | memset(tfd, 0, sizeof(*tfd)); | |
197 | ||
198 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
199 | ||
200 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
201 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
202 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
203 | IWL_NUM_OF_TBS); | |
204 | return -EINVAL; | |
205 | } | |
206 | ||
207 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) | |
208 | return -EINVAL; | |
209 | ||
210 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
211 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
212 | (unsigned long long)addr); | |
213 | ||
214 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 | /* | |
220 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
221 | * given Tx queue, and enable the DMA channel used for that queue. | |
222 | * | |
223 | * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
224 | * channels supported in hardware. | |
225 | */ | |
226 | static int iwlagn_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
227 | { | |
228 | int txq_id = txq->q.id; | |
229 | ||
230 | /* Circular buffer (TFD queue in DRAM) physical base address */ | |
231 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
232 | txq->q.dma_addr >> 8); | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
387f3381 SG |
237 | /** |
238 | * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's | |
239 | */ | |
240 | void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id) | |
241 | { | |
242 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
243 | struct iwl_queue *q = &txq->q; | |
244 | ||
245 | if (q->n_bd == 0) | |
246 | return; | |
247 | ||
248 | while (q->write_ptr != q->read_ptr) { | |
214d14d4 | 249 | iwlagn_txq_free_tfd(priv, txq); |
387f3381 SG |
250 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
251 | } | |
252 | } | |
253 | ||
1053d35f RR |
254 | /** |
255 | * iwl_tx_queue_free - Deallocate DMA queue. | |
256 | * @txq: Transmit queue to deallocate. | |
257 | * | |
258 | * Empty queue by removing and destroying all BD's. | |
259 | * Free all buffers. | |
260 | * 0-fill, but do not free "txq" descriptor structure. | |
261 | */ | |
a8e74e27 | 262 | void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id) |
1053d35f | 263 | { |
da99c4b6 | 264 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; |
f36d04ab | 265 | struct device *dev = &priv->pci_dev->dev; |
71c55d90 | 266 | int i; |
1053d35f | 267 | |
387f3381 | 268 | iwl_tx_queue_unmap(priv, txq_id); |
1053d35f | 269 | |
1053d35f | 270 | /* De-alloc array of command/tx buffers */ |
961ba60a | 271 | for (i = 0; i < TFD_TX_CMD_SLOTS; i++) |
da99c4b6 | 272 | kfree(txq->cmd[i]); |
1053d35f RR |
273 | |
274 | /* De-alloc circular buffer of TFDs */ | |
275 | if (txq->q.n_bd) | |
f36d04ab SG |
276 | dma_free_coherent(dev, priv->hw_params.tfd_size * |
277 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
1053d35f RR |
278 | |
279 | /* De-alloc array of per-TFD driver data */ | |
280 | kfree(txq->txb); | |
281 | txq->txb = NULL; | |
282 | ||
c2acea8e JB |
283 | /* deallocate arrays */ |
284 | kfree(txq->cmd); | |
285 | kfree(txq->meta); | |
286 | txq->cmd = NULL; | |
287 | txq->meta = NULL; | |
288 | ||
1053d35f RR |
289 | /* 0-fill queue descriptor structure */ |
290 | memset(txq, 0, sizeof(*txq)); | |
291 | } | |
961ba60a TW |
292 | |
293 | /** | |
387f3381 | 294 | * iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue |
961ba60a | 295 | */ |
387f3381 | 296 | void iwl_cmd_queue_unmap(struct iwl_priv *priv) |
961ba60a | 297 | { |
13bb9483 | 298 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; |
961ba60a | 299 | struct iwl_queue *q = &txq->q; |
71c55d90 | 300 | int i; |
961ba60a TW |
301 | |
302 | if (q->n_bd == 0) | |
303 | return; | |
304 | ||
387f3381 | 305 | while (q->read_ptr != q->write_ptr) { |
dd487449 ZY |
306 | i = get_cmd_index(q, q->read_ptr, 0); |
307 | ||
3598e177 | 308 | if (txq->meta[i].flags & CMD_MAPPED) { |
387f3381 SG |
309 | pci_unmap_single(priv->pci_dev, |
310 | dma_unmap_addr(&txq->meta[i], mapping), | |
311 | dma_unmap_len(&txq->meta[i], len), | |
312 | PCI_DMA_BIDIRECTIONAL); | |
3598e177 SG |
313 | txq->meta[i].flags = 0; |
314 | } | |
dd487449 | 315 | |
3598e177 | 316 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
dd487449 | 317 | } |
387f3381 | 318 | |
3598e177 SG |
319 | i = q->n_window; |
320 | if (txq->meta[i].flags & CMD_MAPPED) { | |
dd487449 | 321 | pci_unmap_single(priv->pci_dev, |
2e724443 FT |
322 | dma_unmap_addr(&txq->meta[i], mapping), |
323 | dma_unmap_len(&txq->meta[i], len), | |
dd487449 | 324 | PCI_DMA_BIDIRECTIONAL); |
3598e177 | 325 | txq->meta[i].flags = 0; |
dd487449 | 326 | } |
387f3381 SG |
327 | } |
328 | ||
329 | /** | |
330 | * iwl_cmd_queue_free - Deallocate DMA queue. | |
331 | * @txq: Transmit queue to deallocate. | |
332 | * | |
333 | * Empty queue by removing and destroying all BD's. | |
334 | * Free all buffers. | |
335 | * 0-fill, but do not free "txq" descriptor structure. | |
336 | */ | |
337 | void iwl_cmd_queue_free(struct iwl_priv *priv) | |
338 | { | |
339 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; | |
340 | struct device *dev = &priv->pci_dev->dev; | |
341 | int i; | |
342 | ||
343 | iwl_cmd_queue_unmap(priv); | |
dd487449 | 344 | |
961ba60a TW |
345 | /* De-alloc array of command/tx buffers */ |
346 | for (i = 0; i <= TFD_CMD_SLOTS; i++) | |
347 | kfree(txq->cmd[i]); | |
348 | ||
349 | /* De-alloc circular buffer of TFDs */ | |
350 | if (txq->q.n_bd) | |
f36d04ab SG |
351 | dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd, |
352 | txq->tfds, txq->q.dma_addr); | |
961ba60a | 353 | |
28142986 RC |
354 | /* deallocate arrays */ |
355 | kfree(txq->cmd); | |
356 | kfree(txq->meta); | |
357 | txq->cmd = NULL; | |
358 | txq->meta = NULL; | |
359 | ||
961ba60a TW |
360 | /* 0-fill queue descriptor structure */ |
361 | memset(txq, 0, sizeof(*txq)); | |
362 | } | |
3e5d238f | 363 | |
fd4abac5 TW |
364 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
365 | * DMA services | |
366 | * | |
367 | * Theory of operation | |
368 | * | |
369 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
370 | * of buffer descriptors, each of which points to one or more data buffers for | |
371 | * the device to read from or fill. Driver and device exchange status of each | |
372 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
373 | * entries in each circular buffer, to protect against confusing empty and full | |
374 | * queue states. | |
375 | * | |
376 | * The device reads or writes the data in the queues via the device's several | |
377 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
378 | * | |
379 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
380 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
381 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
382 | * Tx queue resumed. | |
383 | * | |
fd4abac5 TW |
384 | ***************************************************/ |
385 | ||
386 | int iwl_queue_space(const struct iwl_queue *q) | |
387 | { | |
388 | int s = q->read_ptr - q->write_ptr; | |
389 | ||
390 | if (q->read_ptr > q->write_ptr) | |
391 | s -= q->n_bd; | |
392 | ||
393 | if (s <= 0) | |
394 | s += q->n_window; | |
395 | /* keep some reserve to not confuse empty and full situations */ | |
396 | s -= 2; | |
397 | if (s < 0) | |
398 | s = 0; | |
399 | return s; | |
400 | } | |
fd4abac5 TW |
401 | |
402 | ||
1053d35f RR |
403 | /** |
404 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
405 | */ | |
443cfd45 | 406 | static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
407 | int count, int slots_num, u32 id) |
408 | { | |
409 | q->n_bd = count; | |
410 | q->n_window = slots_num; | |
411 | q->id = id; | |
412 | ||
413 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
414 | * and iwl_queue_dec_wrap are broken. */ | |
3e41ace5 JB |
415 | if (WARN_ON(!is_power_of_2(count))) |
416 | return -EINVAL; | |
1053d35f RR |
417 | |
418 | /* slots_num must be power-of-two size, otherwise | |
419 | * get_cmd_index is broken. */ | |
3e41ace5 JB |
420 | if (WARN_ON(!is_power_of_2(slots_num))) |
421 | return -EINVAL; | |
1053d35f RR |
422 | |
423 | q->low_mark = q->n_window / 4; | |
424 | if (q->low_mark < 4) | |
425 | q->low_mark = 4; | |
426 | ||
427 | q->high_mark = q->n_window / 8; | |
428 | if (q->high_mark < 2) | |
429 | q->high_mark = 2; | |
430 | ||
431 | q->write_ptr = q->read_ptr = 0; | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
436 | /** | |
437 | * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
438 | */ | |
439 | static int iwl_tx_queue_alloc(struct iwl_priv *priv, | |
16466903 | 440 | struct iwl_tx_queue *txq, u32 id) |
1053d35f | 441 | { |
f36d04ab | 442 | struct device *dev = &priv->pci_dev->dev; |
3978e5bc | 443 | size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; |
1053d35f RR |
444 | |
445 | /* Driver private data, only for Tx (not command) queues, | |
446 | * not shared with device. */ | |
13bb9483 | 447 | if (id != priv->cmd_queue) { |
519c7c41 | 448 | txq->txb = kzalloc(sizeof(txq->txb[0]) * |
1053d35f RR |
449 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); |
450 | if (!txq->txb) { | |
15b1687c | 451 | IWL_ERR(priv, "kmalloc for auxiliary BD " |
1053d35f RR |
452 | "structures failed\n"); |
453 | goto error; | |
454 | } | |
3978e5bc | 455 | } else { |
1053d35f | 456 | txq->txb = NULL; |
3978e5bc | 457 | } |
1053d35f RR |
458 | |
459 | /* Circular buffer of transmit frame descriptors (TFDs), | |
460 | * shared with device */ | |
f36d04ab SG |
461 | txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, |
462 | GFP_KERNEL); | |
499b1883 | 463 | if (!txq->tfds) { |
3978e5bc | 464 | IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz); |
1053d35f RR |
465 | goto error; |
466 | } | |
467 | txq->q.id = id; | |
468 | ||
469 | return 0; | |
470 | ||
471 | error: | |
472 | kfree(txq->txb); | |
473 | txq->txb = NULL; | |
474 | ||
475 | return -ENOMEM; | |
476 | } | |
477 | ||
1053d35f RR |
478 | /** |
479 | * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue | |
480 | */ | |
a8e74e27 SO |
481 | int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
482 | int slots_num, u32 txq_id) | |
1053d35f | 483 | { |
da99c4b6 | 484 | int i, len; |
73b7d742 | 485 | int ret; |
c2acea8e | 486 | int actual_slots = slots_num; |
1053d35f RR |
487 | |
488 | /* | |
489 | * Alloc buffer array for commands (Tx or other types of commands). | |
13bb9483 | 490 | * For the command queue (#4/#9), allocate command space + one big |
1053d35f RR |
491 | * command for scan, since scan command is very huge; the system will |
492 | * not have two scans at the same time, so only one is needed. | |
493 | * For normal Tx queues (all other queues), no super-size command | |
494 | * space is needed. | |
495 | */ | |
13bb9483 | 496 | if (txq_id == priv->cmd_queue) |
c2acea8e JB |
497 | actual_slots++; |
498 | ||
499 | txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots, | |
500 | GFP_KERNEL); | |
501 | txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots, | |
502 | GFP_KERNEL); | |
503 | ||
504 | if (!txq->meta || !txq->cmd) | |
505 | goto out_free_arrays; | |
506 | ||
507 | len = sizeof(struct iwl_device_cmd); | |
508 | for (i = 0; i < actual_slots; i++) { | |
509 | /* only happens for cmd queue */ | |
510 | if (i == slots_num) | |
89612124 | 511 | len = IWL_MAX_CMD_SIZE; |
da99c4b6 | 512 | |
49898852 | 513 | txq->cmd[i] = kmalloc(len, GFP_KERNEL); |
da99c4b6 | 514 | if (!txq->cmd[i]) |
73b7d742 | 515 | goto err; |
da99c4b6 | 516 | } |
1053d35f RR |
517 | |
518 | /* Alloc driver data array and TFD circular buffer */ | |
73b7d742 TW |
519 | ret = iwl_tx_queue_alloc(priv, txq, txq_id); |
520 | if (ret) | |
521 | goto err; | |
1053d35f | 522 | |
1053d35f RR |
523 | txq->need_update = 0; |
524 | ||
1a716557 | 525 | /* |
ea9b307f JB |
526 | * For the default queues 0-3, set up the swq_id |
527 | * already -- all others need to get one later | |
528 | * (if they need one at all). | |
1a716557 | 529 | */ |
ea9b307f JB |
530 | if (txq_id < 4) |
531 | iwl_set_swq_id(txq, txq_id, txq_id); | |
45af8195 | 532 | |
1053d35f RR |
533 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise |
534 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
535 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
536 | ||
537 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
3e41ace5 JB |
538 | ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
539 | if (ret) | |
540 | return ret; | |
1053d35f RR |
541 | |
542 | /* Tell device where to find queue */ | |
214d14d4 | 543 | iwlagn_tx_queue_init(priv, txq); |
1053d35f RR |
544 | |
545 | return 0; | |
73b7d742 | 546 | err: |
c2acea8e | 547 | for (i = 0; i < actual_slots; i++) |
73b7d742 | 548 | kfree(txq->cmd[i]); |
c2acea8e JB |
549 | out_free_arrays: |
550 | kfree(txq->meta); | |
551 | kfree(txq->cmd); | |
73b7d742 | 552 | |
73b7d742 | 553 | return -ENOMEM; |
1053d35f | 554 | } |
a8e74e27 | 555 | |
de0f60ea ZY |
556 | void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
557 | int slots_num, u32 txq_id) | |
558 | { | |
559 | int actual_slots = slots_num; | |
560 | ||
13bb9483 | 561 | if (txq_id == priv->cmd_queue) |
de0f60ea ZY |
562 | actual_slots++; |
563 | ||
564 | memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots); | |
565 | ||
566 | txq->need_update = 0; | |
567 | ||
568 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
569 | iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
570 | ||
571 | /* Tell device where to find queue */ | |
214d14d4 | 572 | iwlagn_tx_queue_init(priv, txq); |
de0f60ea | 573 | } |
de0f60ea | 574 | |
fd4abac5 TW |
575 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
576 | ||
577 | /** | |
578 | * iwl_enqueue_hcmd - enqueue a uCode command | |
579 | * @priv: device private data point | |
580 | * @cmd: a point to the ucode command structure | |
581 | * | |
582 | * The function returns < 0 values to indicate the operation is | |
583 | * failed. On success, it turns the index (> 0) of command in the | |
584 | * command queue. | |
585 | */ | |
586 | int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
587 | { | |
13bb9483 | 588 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; |
fd4abac5 | 589 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
590 | struct iwl_device_cmd *out_cmd; |
591 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 592 | dma_addr_t phys_addr; |
fd4abac5 | 593 | unsigned long flags; |
f3674227 TW |
594 | u32 idx; |
595 | u16 fix_size; | |
0975cc8f | 596 | bool is_ct_kill = false; |
fd4abac5 | 597 | |
3fa50738 | 598 | fix_size = (u16)(cmd->len[0] + sizeof(out_cmd->hdr)); |
fd4abac5 | 599 | |
3e41ace5 JB |
600 | /* |
601 | * If any of the command structures end up being larger than | |
fd4abac5 | 602 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then |
89612124 AK |
603 | * we will need to increase the size of the TFD entries |
604 | * Also, check to see if command buffer should not exceed the size | |
3e41ace5 JB |
605 | * of device_cmd and max_cmd_size. |
606 | */ | |
607 | if (WARN_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
608 | !(cmd->flags & CMD_SIZE_HUGE))) | |
609 | return -EINVAL; | |
610 | ||
611 | if (WARN_ON(fix_size > IWL_MAX_CMD_SIZE)) | |
612 | return -EINVAL; | |
fd4abac5 | 613 | |
7812b167 | 614 | if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) { |
f2f21b49 RC |
615 | IWL_WARN(priv, "Not sending command - %s KILL\n", |
616 | iwl_is_rfkill(priv) ? "RF" : "CT"); | |
fd4abac5 TW |
617 | return -EIO; |
618 | } | |
7b21f00e JB |
619 | |
620 | /* | |
621 | * As we only have a single huge buffer, check that the command | |
622 | * is synchronous (otherwise buffers could end up being reused). | |
623 | */ | |
624 | ||
625 | if (WARN_ON((cmd->flags & CMD_ASYNC) && (cmd->flags & CMD_SIZE_HUGE))) | |
626 | return -EINVAL; | |
fd4abac5 | 627 | |
3598e177 SG |
628 | spin_lock_irqsave(&priv->hcmd_lock, flags); |
629 | ||
c2acea8e | 630 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
3598e177 SG |
631 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); |
632 | ||
2d237f71 | 633 | IWL_ERR(priv, "No space in command queue\n"); |
f42e7662 | 634 | is_ct_kill = iwl_check_for_ct_kill(priv); |
0975cc8f | 635 | if (!is_ct_kill) { |
7812b167 | 636 | IWL_ERR(priv, "Restarting adapter due to queue full\n"); |
e649437f | 637 | iwlagn_fw_error(priv, false); |
7812b167 | 638 | } |
fd4abac5 TW |
639 | return -ENOSPC; |
640 | } | |
641 | ||
c2acea8e | 642 | idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE); |
da99c4b6 | 643 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
644 | out_meta = &txq->meta[idx]; |
645 | ||
3598e177 SG |
646 | if (WARN_ON(out_meta->flags & CMD_MAPPED)) { |
647 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
648 | return -ENOSPC; | |
649 | } | |
650 | ||
8ce73f3a | 651 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
652 | if (cmd->flags & CMD_WANT_SKB) |
653 | out_meta->source = cmd; | |
654 | if (cmd->flags & CMD_ASYNC) | |
655 | out_meta->callback = cmd->callback; | |
fd4abac5 TW |
656 | |
657 | out_cmd->hdr.cmd = cmd->id; | |
3fa50738 | 658 | memcpy(&out_cmd->cmd.payload, cmd->data[0], cmd->len[0]); |
fd4abac5 TW |
659 | |
660 | /* At this point, the out_cmd now has all of the incoming cmd | |
661 | * information */ | |
662 | ||
663 | out_cmd->hdr.flags = 0; | |
13bb9483 | 664 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) | |
fd4abac5 | 665 | INDEX_TO_SEQ(q->write_ptr)); |
c2acea8e | 666 | if (cmd->flags & CMD_SIZE_HUGE) |
9734cb23 | 667 | out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; |
fd4abac5 | 668 | |
ded2ae7c EK |
669 | #ifdef CONFIG_IWLWIFI_DEBUG |
670 | switch (out_cmd->hdr.cmd) { | |
671 | case REPLY_TX_LINK_QUALITY_CMD: | |
672 | case SENSITIVITY_CMD: | |
e1623446 | 673 | IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
674 | "%d bytes at %d[%d]:%d\n", |
675 | get_cmd_string(out_cmd->hdr.cmd), | |
676 | out_cmd->hdr.cmd, | |
677 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
13bb9483 JB |
678 | q->write_ptr, idx, priv->cmd_queue); |
679 | break; | |
ded2ae7c | 680 | default: |
e1623446 | 681 | IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
682 | "%d bytes at %d[%d]:%d\n", |
683 | get_cmd_string(out_cmd->hdr.cmd), | |
684 | out_cmd->hdr.cmd, | |
685 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
13bb9483 | 686 | q->write_ptr, idx, priv->cmd_queue); |
ded2ae7c EK |
687 | } |
688 | #endif | |
df833b1d RC |
689 | phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr, |
690 | fix_size, PCI_DMA_BIDIRECTIONAL); | |
2c46f72e JB |
691 | if (unlikely(pci_dma_mapping_error(priv->pci_dev, phys_addr))) { |
692 | idx = -ENOMEM; | |
693 | goto out; | |
694 | } | |
695 | ||
2e724443 FT |
696 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
697 | dma_unmap_len_set(out_meta, len, fix_size); | |
df833b1d | 698 | |
2c46f72e JB |
699 | out_meta->flags = cmd->flags | CMD_MAPPED; |
700 | ||
701 | txq->need_update = 1; | |
702 | ||
be1a71a1 JB |
703 | trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags); |
704 | ||
214d14d4 JB |
705 | iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, fix_size, 1, |
706 | U32_PAD(cmd->len[0])); | |
df833b1d | 707 | |
fd4abac5 TW |
708 | /* Increment and update queue's write index */ |
709 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
7bfedc59 | 710 | iwl_txq_update_write_ptr(priv, txq); |
fd4abac5 | 711 | |
2c46f72e | 712 | out: |
fd4abac5 | 713 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); |
7bfedc59 | 714 | return idx; |
fd4abac5 TW |
715 | } |
716 | ||
17b88929 TW |
717 | /** |
718 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
719 | * | |
720 | * When FW advances 'R' index, all entries between old and new 'R' index | |
721 | * need to be reclaimed. As result, some free space forms. If there is | |
722 | * enough free space (> low mark), wake the stack that feeds us. | |
723 | */ | |
499b1883 TW |
724 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, |
725 | int idx, int cmd_idx) | |
17b88929 TW |
726 | { |
727 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
728 | struct iwl_queue *q = &txq->q; | |
729 | int nfreed = 0; | |
730 | ||
499b1883 | 731 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
15b1687c | 732 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
17b88929 | 733 | "is out of range [0-%d] %d %d.\n", txq_id, |
499b1883 | 734 | idx, q->n_bd, q->write_ptr, q->read_ptr); |
17b88929 TW |
735 | return; |
736 | } | |
737 | ||
499b1883 TW |
738 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
739 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 740 | |
499b1883 | 741 | if (nfreed++ > 0) { |
15b1687c | 742 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 | 743 | q->write_ptr, q->read_ptr); |
e649437f | 744 | iwlagn_fw_error(priv, false); |
17b88929 | 745 | } |
da99c4b6 | 746 | |
17b88929 TW |
747 | } |
748 | } | |
749 | ||
750 | /** | |
751 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
752 | * @rxb: Rx buffer to reclaim | |
753 | * | |
754 | * If an Rx buffer has an async callback associated with it the callback | |
755 | * will be executed. The attached skb (if present) will only be freed | |
756 | * if the callback returns 1 | |
757 | */ | |
758 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
759 | { | |
2f301227 | 760 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
761 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
762 | int txq_id = SEQ_TO_QUEUE(sequence); | |
763 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 764 | int cmd_index; |
9734cb23 | 765 | bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); |
c2acea8e JB |
766 | struct iwl_device_cmd *cmd; |
767 | struct iwl_cmd_meta *meta; | |
13bb9483 | 768 | struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; |
3598e177 | 769 | unsigned long flags; |
17b88929 TW |
770 | |
771 | /* If a Tx command is being handled and it isn't in the actual | |
772 | * command queue then there a command routing bug has been introduced | |
773 | * in the queue management code. */ | |
13bb9483 JB |
774 | if (WARN(txq_id != priv->cmd_queue, |
775 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", | |
776 | txq_id, priv->cmd_queue, sequence, | |
777 | priv->txq[priv->cmd_queue].q.read_ptr, | |
778 | priv->txq[priv->cmd_queue].q.write_ptr)) { | |
ec741164 | 779 | iwl_print_hex_error(priv, pkt, 32); |
55d6a3cd | 780 | return; |
01ef9323 | 781 | } |
17b88929 | 782 | |
dd487449 ZY |
783 | cmd_index = get_cmd_index(&txq->q, index, huge); |
784 | cmd = txq->cmd[cmd_index]; | |
785 | meta = &txq->meta[cmd_index]; | |
17b88929 | 786 | |
c33de625 | 787 | pci_unmap_single(priv->pci_dev, |
2e724443 FT |
788 | dma_unmap_addr(meta, mapping), |
789 | dma_unmap_len(meta, len), | |
c33de625 RC |
790 | PCI_DMA_BIDIRECTIONAL); |
791 | ||
17b88929 | 792 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 793 | if (meta->flags & CMD_WANT_SKB) { |
2f301227 ZY |
794 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); |
795 | rxb->page = NULL; | |
2624e96c SG |
796 | } else if (meta->callback) |
797 | meta->callback(priv, cmd, pkt); | |
798 | ||
799 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
17b88929 | 800 | |
499b1883 | 801 | iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index); |
17b88929 | 802 | |
c2acea8e | 803 | if (!(meta->flags & CMD_ASYNC)) { |
17b88929 | 804 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); |
91dd6c27 | 805 | IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n", |
d2dfe6df | 806 | get_cmd_string(cmd->hdr.cmd)); |
17b88929 TW |
807 | wake_up_interruptible(&priv->wait_command_queue); |
808 | } | |
3598e177 SG |
809 | |
810 | /* Mark as unmapped */ | |
dd487449 | 811 | meta->flags = 0; |
3598e177 SG |
812 | |
813 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
17b88929 | 814 | } |