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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
fd4abac5 | 30 | #include <linux/etherdevice.h> |
1053d35f RR |
31 | #include <net/mac80211.h> |
32 | #include "iwl-eeprom.h" | |
33 | #include "iwl-dev.h" | |
34 | #include "iwl-core.h" | |
35 | #include "iwl-sta.h" | |
36 | #include "iwl-io.h" | |
37 | #include "iwl-helpers.h" | |
38 | ||
39 | /** | |
40 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
41 | * | |
42 | * Does NOT advance any TFD circular buffer read/write indexes | |
43 | * Does NOT free the TFD itself (which is within circular buffer) | |
44 | */ | |
16466903 | 45 | int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
1053d35f RR |
46 | { |
47 | struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0]; | |
48 | struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr]; | |
49 | struct pci_dev *dev = priv->pci_dev; | |
50 | int i; | |
51 | int counter = 0; | |
52 | int index, is_odd; | |
53 | ||
54 | /* Host command buffers stay mapped in memory, nothing to clean */ | |
55 | if (txq->q.id == IWL_CMD_QUEUE_NUM) | |
56 | return 0; | |
57 | ||
58 | /* Sanity check on number of chunks */ | |
59 | counter = IWL_GET_BITS(*bd, num_tbs); | |
60 | if (counter > MAX_NUM_OF_TBS) { | |
61 | IWL_ERROR("Too many chunks: %i\n", counter); | |
62 | /* @todo issue fatal error, it is quite serious situation */ | |
63 | return 0; | |
64 | } | |
65 | ||
66 | /* Unmap chunks, if any. | |
67 | * TFD info for odd chunks is different format than for even chunks. */ | |
68 | for (i = 0; i < counter; i++) { | |
69 | index = i / 2; | |
70 | is_odd = i & 0x1; | |
71 | ||
72 | if (is_odd) | |
73 | pci_unmap_single( | |
74 | dev, | |
75 | IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) | | |
76 | (IWL_GET_BITS(bd->pa[index], | |
77 | tb2_addr_hi20) << 16), | |
78 | IWL_GET_BITS(bd->pa[index], tb2_len), | |
79 | PCI_DMA_TODEVICE); | |
80 | ||
81 | else if (i > 0) | |
82 | pci_unmap_single(dev, | |
83 | le32_to_cpu(bd->pa[index].tb1_addr), | |
84 | IWL_GET_BITS(bd->pa[index], tb1_len), | |
85 | PCI_DMA_TODEVICE); | |
86 | ||
87 | /* Free SKB, if any, for this chunk */ | |
88 | if (txq->txb[txq->q.read_ptr].skb[i]) { | |
89 | struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i]; | |
90 | ||
91 | dev_kfree_skb(skb); | |
92 | txq->txb[txq->q.read_ptr].skb[i] = NULL; | |
93 | } | |
94 | } | |
95 | return 0; | |
96 | } | |
97 | EXPORT_SYMBOL(iwl_hw_txq_free_tfd); | |
98 | ||
fd4abac5 TW |
99 | |
100 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr, | |
101 | dma_addr_t addr, u16 len) | |
102 | { | |
103 | int index, is_odd; | |
104 | struct iwl_tfd_frame *tfd = ptr; | |
105 | u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs); | |
106 | ||
107 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
108 | if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) { | |
109 | IWL_ERROR("Error can not send more than %d chunks\n", | |
110 | MAX_NUM_OF_TBS); | |
111 | return -EINVAL; | |
112 | } | |
113 | ||
114 | index = num_tbs / 2; | |
115 | is_odd = num_tbs & 0x1; | |
116 | ||
117 | if (!is_odd) { | |
118 | tfd->pa[index].tb1_addr = cpu_to_le32(addr); | |
119 | IWL_SET_BITS(tfd->pa[index], tb1_addr_hi, | |
120 | iwl_get_dma_hi_address(addr)); | |
121 | IWL_SET_BITS(tfd->pa[index], tb1_len, len); | |
122 | } else { | |
123 | IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16, | |
124 | (u32) (addr & 0xffff)); | |
125 | IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16); | |
126 | IWL_SET_BITS(tfd->pa[index], tb2_len, len); | |
127 | } | |
128 | ||
129 | IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1); | |
130 | ||
131 | return 0; | |
132 | } | |
133 | EXPORT_SYMBOL(iwl_hw_txq_attach_buf_to_tfd); | |
134 | ||
135 | /** | |
136 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
137 | */ | |
138 | int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
139 | { | |
140 | u32 reg = 0; | |
141 | int ret = 0; | |
142 | int txq_id = txq->q.id; | |
143 | ||
144 | if (txq->need_update == 0) | |
145 | return ret; | |
146 | ||
147 | /* if we're trying to save power */ | |
148 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
149 | /* wake up nic if it's powered down ... | |
150 | * uCode will wake up, and interrupt us again, so next | |
151 | * time we'll skip this part. */ | |
152 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
153 | ||
154 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
155 | IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg); | |
156 | iwl_set_bit(priv, CSR_GP_CNTRL, | |
157 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
158 | return ret; | |
159 | } | |
160 | ||
161 | /* restore this queue's parameters in nic hardware. */ | |
162 | ret = iwl_grab_nic_access(priv); | |
163 | if (ret) | |
164 | return ret; | |
165 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, | |
166 | txq->q.write_ptr | (txq_id << 8)); | |
167 | iwl_release_nic_access(priv); | |
168 | ||
169 | /* else not in power-save mode, uCode will never sleep when we're | |
170 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
171 | } else | |
172 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
173 | txq->q.write_ptr | (txq_id << 8)); | |
174 | ||
175 | txq->need_update = 0; | |
176 | ||
177 | return ret; | |
178 | } | |
179 | EXPORT_SYMBOL(iwl_txq_update_write_ptr); | |
180 | ||
181 | ||
1053d35f RR |
182 | /** |
183 | * iwl_tx_queue_free - Deallocate DMA queue. | |
184 | * @txq: Transmit queue to deallocate. | |
185 | * | |
186 | * Empty queue by removing and destroying all BD's. | |
187 | * Free all buffers. | |
188 | * 0-fill, but do not free "txq" descriptor structure. | |
189 | */ | |
16466903 | 190 | static void iwl_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
1053d35f | 191 | { |
443cfd45 | 192 | struct iwl_queue *q = &txq->q; |
1053d35f RR |
193 | struct pci_dev *dev = priv->pci_dev; |
194 | int len; | |
195 | ||
196 | if (q->n_bd == 0) | |
197 | return; | |
198 | ||
199 | /* first, empty all BD's */ | |
200 | for (; q->write_ptr != q->read_ptr; | |
201 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) | |
202 | iwl_hw_txq_free_tfd(priv, txq); | |
203 | ||
204 | len = sizeof(struct iwl_cmd) * q->n_window; | |
205 | if (q->id == IWL_CMD_QUEUE_NUM) | |
206 | len += IWL_MAX_SCAN_SIZE; | |
207 | ||
208 | /* De-alloc array of command/tx buffers */ | |
209 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); | |
210 | ||
211 | /* De-alloc circular buffer of TFDs */ | |
212 | if (txq->q.n_bd) | |
213 | pci_free_consistent(dev, sizeof(struct iwl_tfd_frame) * | |
214 | txq->q.n_bd, txq->bd, txq->q.dma_addr); | |
215 | ||
216 | /* De-alloc array of per-TFD driver data */ | |
217 | kfree(txq->txb); | |
218 | txq->txb = NULL; | |
219 | ||
220 | /* 0-fill queue descriptor structure */ | |
221 | memset(txq, 0, sizeof(*txq)); | |
222 | } | |
223 | ||
fd4abac5 TW |
224 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
225 | * DMA services | |
226 | * | |
227 | * Theory of operation | |
228 | * | |
229 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
230 | * of buffer descriptors, each of which points to one or more data buffers for | |
231 | * the device to read from or fill. Driver and device exchange status of each | |
232 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
233 | * entries in each circular buffer, to protect against confusing empty and full | |
234 | * queue states. | |
235 | * | |
236 | * The device reads or writes the data in the queues via the device's several | |
237 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
238 | * | |
239 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
240 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
241 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
242 | * Tx queue resumed. | |
243 | * | |
244 | * See more detailed info in iwl-4965-hw.h. | |
245 | ***************************************************/ | |
246 | ||
247 | int iwl_queue_space(const struct iwl_queue *q) | |
248 | { | |
249 | int s = q->read_ptr - q->write_ptr; | |
250 | ||
251 | if (q->read_ptr > q->write_ptr) | |
252 | s -= q->n_bd; | |
253 | ||
254 | if (s <= 0) | |
255 | s += q->n_window; | |
256 | /* keep some reserve to not confuse empty and full situations */ | |
257 | s -= 2; | |
258 | if (s < 0) | |
259 | s = 0; | |
260 | return s; | |
261 | } | |
262 | EXPORT_SYMBOL(iwl_queue_space); | |
263 | ||
264 | ||
1053d35f RR |
265 | /** |
266 | * iwl_hw_txq_ctx_free - Free TXQ Context | |
267 | * | |
268 | * Destroy all TX DMA queues and structures | |
269 | */ | |
270 | void iwl_hw_txq_ctx_free(struct iwl_priv *priv) | |
271 | { | |
272 | int txq_id; | |
273 | ||
274 | /* Tx queues */ | |
275 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
276 | iwl_tx_queue_free(priv, &priv->txq[txq_id]); | |
277 | ||
278 | /* Keep-warm buffer */ | |
279 | iwl_kw_free(priv); | |
280 | } | |
281 | EXPORT_SYMBOL(iwl_hw_txq_ctx_free); | |
282 | ||
283 | /** | |
284 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
285 | */ | |
443cfd45 | 286 | static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
287 | int count, int slots_num, u32 id) |
288 | { | |
289 | q->n_bd = count; | |
290 | q->n_window = slots_num; | |
291 | q->id = id; | |
292 | ||
293 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
294 | * and iwl_queue_dec_wrap are broken. */ | |
295 | BUG_ON(!is_power_of_2(count)); | |
296 | ||
297 | /* slots_num must be power-of-two size, otherwise | |
298 | * get_cmd_index is broken. */ | |
299 | BUG_ON(!is_power_of_2(slots_num)); | |
300 | ||
301 | q->low_mark = q->n_window / 4; | |
302 | if (q->low_mark < 4) | |
303 | q->low_mark = 4; | |
304 | ||
305 | q->high_mark = q->n_window / 8; | |
306 | if (q->high_mark < 2) | |
307 | q->high_mark = 2; | |
308 | ||
309 | q->write_ptr = q->read_ptr = 0; | |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
314 | /** | |
315 | * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
316 | */ | |
317 | static int iwl_tx_queue_alloc(struct iwl_priv *priv, | |
16466903 | 318 | struct iwl_tx_queue *txq, u32 id) |
1053d35f RR |
319 | { |
320 | struct pci_dev *dev = priv->pci_dev; | |
321 | ||
322 | /* Driver private data, only for Tx (not command) queues, | |
323 | * not shared with device. */ | |
324 | if (id != IWL_CMD_QUEUE_NUM) { | |
325 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
326 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
327 | if (!txq->txb) { | |
328 | IWL_ERROR("kmalloc for auxiliary BD " | |
329 | "structures failed\n"); | |
330 | goto error; | |
331 | } | |
332 | } else | |
333 | txq->txb = NULL; | |
334 | ||
335 | /* Circular buffer of transmit frame descriptors (TFDs), | |
336 | * shared with device */ | |
337 | txq->bd = pci_alloc_consistent(dev, | |
338 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX, | |
339 | &txq->q.dma_addr); | |
340 | ||
341 | if (!txq->bd) { | |
342 | IWL_ERROR("pci_alloc_consistent(%zd) failed\n", | |
343 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX); | |
344 | goto error; | |
345 | } | |
346 | txq->q.id = id; | |
347 | ||
348 | return 0; | |
349 | ||
350 | error: | |
351 | kfree(txq->txb); | |
352 | txq->txb = NULL; | |
353 | ||
354 | return -ENOMEM; | |
355 | } | |
356 | ||
357 | /* | |
358 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
359 | * given Tx queue, and enable the DMA channel used for that queue. | |
360 | * | |
361 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
362 | * channels supported in hardware. | |
363 | */ | |
364 | static int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
16466903 | 365 | struct iwl_tx_queue *txq) |
1053d35f RR |
366 | { |
367 | int rc; | |
368 | unsigned long flags; | |
369 | int txq_id = txq->q.id; | |
370 | ||
371 | spin_lock_irqsave(&priv->lock, flags); | |
372 | rc = iwl_grab_nic_access(priv); | |
373 | if (rc) { | |
374 | spin_unlock_irqrestore(&priv->lock, flags); | |
375 | return rc; | |
376 | } | |
377 | ||
378 | /* Circular buffer (TFD queue in DRAM) physical base address */ | |
379 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
380 | txq->q.dma_addr >> 8); | |
381 | ||
382 | /* Enable DMA channel, using same id as for TFD queue */ | |
383 | iwl_write_direct32( | |
384 | priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), | |
385 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
386 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL); | |
387 | iwl_release_nic_access(priv); | |
388 | spin_unlock_irqrestore(&priv->lock, flags); | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
393 | /** | |
394 | * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue | |
395 | */ | |
396 | static int iwl_tx_queue_init(struct iwl_priv *priv, | |
16466903 | 397 | struct iwl_tx_queue *txq, |
1053d35f RR |
398 | int slots_num, u32 txq_id) |
399 | { | |
400 | struct pci_dev *dev = priv->pci_dev; | |
401 | int len; | |
402 | int rc = 0; | |
403 | ||
404 | /* | |
405 | * Alloc buffer array for commands (Tx or other types of commands). | |
406 | * For the command queue (#4), allocate command space + one big | |
407 | * command for scan, since scan command is very huge; the system will | |
408 | * not have two scans at the same time, so only one is needed. | |
409 | * For normal Tx queues (all other queues), no super-size command | |
410 | * space is needed. | |
411 | */ | |
412 | len = sizeof(struct iwl_cmd) * slots_num; | |
413 | if (txq_id == IWL_CMD_QUEUE_NUM) | |
414 | len += IWL_MAX_SCAN_SIZE; | |
415 | txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd); | |
416 | if (!txq->cmd) | |
417 | return -ENOMEM; | |
418 | ||
419 | /* Alloc driver data array and TFD circular buffer */ | |
420 | rc = iwl_tx_queue_alloc(priv, txq, txq_id); | |
421 | if (rc) { | |
422 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); | |
423 | ||
424 | return -ENOMEM; | |
425 | } | |
426 | txq->need_update = 0; | |
427 | ||
428 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
429 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
430 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
431 | ||
432 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
433 | iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
434 | ||
435 | /* Tell device where to find queue */ | |
436 | iwl_hw_tx_queue_init(priv, txq); | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | /** | |
442 | * iwl_txq_ctx_reset - Reset TX queue context | |
443 | * Destroys all DMA structures and initialise them again | |
444 | * | |
445 | * @param priv | |
446 | * @return error code | |
447 | */ | |
448 | int iwl_txq_ctx_reset(struct iwl_priv *priv) | |
449 | { | |
450 | int ret = 0; | |
451 | int txq_id, slots_num; | |
452 | ||
453 | iwl_kw_free(priv); | |
454 | ||
455 | /* Free all tx/cmd queues and keep-warm buffer */ | |
456 | iwl_hw_txq_ctx_free(priv); | |
457 | ||
458 | /* Alloc keep-warm buffer */ | |
459 | ret = iwl_kw_alloc(priv); | |
460 | if (ret) { | |
461 | IWL_ERROR("Keep Warm allocation failed"); | |
462 | goto error_kw; | |
463 | } | |
464 | ||
465 | /* Turn off all Tx DMA fifos */ | |
466 | ret = priv->cfg->ops->lib->disable_tx_fifo(priv); | |
467 | if (unlikely(ret)) | |
468 | goto error_reset; | |
469 | ||
470 | /* Tell nic where to find the keep-warm buffer */ | |
471 | ret = iwl_kw_init(priv); | |
472 | if (ret) { | |
473 | IWL_ERROR("kw_init failed\n"); | |
474 | goto error_reset; | |
475 | } | |
476 | ||
477 | /* Alloc and init all (default 16) Tx queues, | |
478 | * including the command queue (#4) */ | |
479 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { | |
480 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? | |
481 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
482 | ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num, | |
483 | txq_id); | |
484 | if (ret) { | |
485 | IWL_ERROR("Tx %d queue init failed\n", txq_id); | |
486 | goto error; | |
487 | } | |
488 | } | |
489 | ||
490 | return ret; | |
491 | ||
492 | error: | |
493 | iwl_hw_txq_ctx_free(priv); | |
494 | error_reset: | |
495 | iwl_kw_free(priv); | |
496 | error_kw: | |
497 | return ret; | |
498 | } | |
fd4abac5 TW |
499 | |
500 | /* | |
501 | * handle build REPLY_TX command notification. | |
502 | */ | |
503 | static void iwl_tx_cmd_build_basic(struct iwl_priv *priv, | |
504 | struct iwl_tx_cmd *tx_cmd, | |
505 | struct ieee80211_tx_control *ctrl, | |
506 | struct ieee80211_hdr *hdr, | |
507 | int is_unicast, u8 std_id) | |
508 | { | |
509 | u16 fc = le16_to_cpu(hdr->frame_control); | |
510 | __le32 tx_flags = tx_cmd->tx_flags; | |
511 | ||
512 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
513 | if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) { | |
514 | tx_flags |= TX_CMD_FLG_ACK_MSK; | |
515 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) | |
516 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
517 | if (ieee80211_is_probe_response(fc) && | |
518 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) | |
519 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
520 | } else { | |
521 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
522 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
523 | } | |
524 | ||
525 | if (ieee80211_is_back_request(fc)) | |
526 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; | |
527 | ||
528 | ||
529 | tx_cmd->sta_id = std_id; | |
530 | if (ieee80211_get_morefrag(hdr)) | |
531 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; | |
532 | ||
533 | if (ieee80211_is_qos_data(fc)) { | |
534 | u8 *qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc)); | |
535 | tx_cmd->tid_tspec = qc[0] & 0xf; | |
536 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
537 | } else { | |
538 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
539 | } | |
540 | ||
541 | if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) { | |
542 | tx_flags |= TX_CMD_FLG_RTS_MSK; | |
543 | tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
544 | } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) { | |
545 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
546 | tx_flags |= TX_CMD_FLG_CTS_MSK; | |
547 | } | |
548 | ||
549 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
550 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
551 | ||
552 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
553 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) { | |
554 | if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ || | |
555 | (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ) | |
556 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); | |
557 | else | |
558 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); | |
559 | } else { | |
560 | tx_cmd->timeout.pm_frame_timeout = 0; | |
561 | } | |
562 | ||
563 | tx_cmd->driver_txop = 0; | |
564 | tx_cmd->tx_flags = tx_flags; | |
565 | tx_cmd->next_frame_len = 0; | |
566 | } | |
567 | ||
568 | #define RTS_HCCA_RETRY_LIMIT 3 | |
569 | #define RTS_DFAULT_RETRY_LIMIT 60 | |
570 | ||
571 | static void iwl_tx_cmd_build_rate(struct iwl_priv *priv, | |
572 | struct iwl_tx_cmd *tx_cmd, | |
573 | struct ieee80211_tx_control *ctrl, | |
574 | u16 fc, int sta_id, | |
575 | int is_hcca) | |
576 | { | |
577 | u8 rts_retry_limit = 0; | |
578 | u8 data_retry_limit = 0; | |
579 | u8 rate_plcp; | |
580 | u16 rate_flags = 0; | |
581 | int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1); | |
582 | ||
583 | rate_plcp = iwl_rates[rate_idx].plcp; | |
584 | ||
585 | rts_retry_limit = (is_hcca) ? | |
586 | RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT; | |
587 | ||
588 | if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE)) | |
589 | rate_flags |= RATE_MCS_CCK_MSK; | |
590 | ||
591 | ||
592 | if (ieee80211_is_probe_response(fc)) { | |
593 | data_retry_limit = 3; | |
594 | if (data_retry_limit < rts_retry_limit) | |
595 | rts_retry_limit = data_retry_limit; | |
596 | } else | |
597 | data_retry_limit = IWL_DEFAULT_TX_RETRY; | |
598 | ||
599 | if (priv->data_retry_limit != -1) | |
600 | data_retry_limit = priv->data_retry_limit; | |
601 | ||
602 | ||
603 | if (ieee80211_is_data(fc)) { | |
604 | tx_cmd->initial_rate_index = 0; | |
605 | tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; | |
606 | } else { | |
607 | switch (fc & IEEE80211_FCTL_STYPE) { | |
608 | case IEEE80211_STYPE_AUTH: | |
609 | case IEEE80211_STYPE_DEAUTH: | |
610 | case IEEE80211_STYPE_ASSOC_REQ: | |
611 | case IEEE80211_STYPE_REASSOC_REQ: | |
612 | if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) { | |
613 | tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
614 | tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK; | |
615 | } | |
616 | break; | |
617 | default: | |
618 | break; | |
619 | } | |
620 | ||
621 | /* Alternate between antenna A and B for successive frames */ | |
622 | if (priv->use_ant_b_for_management_frame) { | |
623 | priv->use_ant_b_for_management_frame = 0; | |
624 | rate_flags |= RATE_MCS_ANT_B_MSK; | |
625 | } else { | |
626 | priv->use_ant_b_for_management_frame = 1; | |
627 | rate_flags |= RATE_MCS_ANT_A_MSK; | |
628 | } | |
629 | } | |
630 | ||
631 | tx_cmd->rts_retry_limit = rts_retry_limit; | |
632 | tx_cmd->data_retry_limit = data_retry_limit; | |
633 | tx_cmd->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags); | |
634 | } | |
635 | ||
636 | static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv, | |
637 | struct ieee80211_tx_control *ctl, | |
638 | struct iwl_tx_cmd *tx_cmd, | |
639 | struct sk_buff *skb_frag, | |
640 | int sta_id) | |
641 | { | |
ccc038ab | 642 | struct ieee80211_key_conf *keyconf = ctl->hw_key; |
fd4abac5 | 643 | |
ccc038ab | 644 | switch (keyconf->alg) { |
fd4abac5 TW |
645 | case ALG_CCMP: |
646 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; | |
ccc038ab | 647 | memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); |
fd4abac5 TW |
648 | if (ctl->flags & IEEE80211_TXCTL_AMPDU) |
649 | tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; | |
650 | IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n"); | |
651 | break; | |
652 | ||
653 | case ALG_TKIP: | |
654 | tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; | |
ccc038ab | 655 | ieee80211_get_tkip_key(keyconf, skb_frag, |
fd4abac5 TW |
656 | IEEE80211_TKIP_P2_KEY, tx_cmd->key); |
657 | IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n"); | |
658 | break; | |
659 | ||
660 | case ALG_WEP: | |
fd4abac5 | 661 | tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP | |
ccc038ab EG |
662 | (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT); |
663 | ||
664 | if (keyconf->keylen == WEP_KEY_LEN_128) | |
665 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; | |
666 | ||
667 | memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); | |
fd4abac5 TW |
668 | |
669 | IWL_DEBUG_TX("Configuring packet for WEP encryption " | |
ccc038ab | 670 | "with key %d\n", keyconf->keyidx); |
fd4abac5 TW |
671 | break; |
672 | ||
673 | default: | |
ccc038ab | 674 | printk(KERN_ERR "Unknown encode alg %d\n", keyconf->alg); |
fd4abac5 TW |
675 | break; |
676 | } | |
677 | } | |
678 | ||
679 | static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len) | |
680 | { | |
681 | /* 0 - mgmt, 1 - cnt, 2 - data */ | |
682 | int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2; | |
683 | priv->tx_stats[idx].cnt++; | |
684 | priv->tx_stats[idx].bytes += len; | |
685 | } | |
686 | ||
687 | /* | |
688 | * start REPLY_TX command process | |
689 | */ | |
690 | int iwl_tx_skb(struct iwl_priv *priv, | |
691 | struct sk_buff *skb, struct ieee80211_tx_control *ctl) | |
692 | { | |
693 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
694 | struct iwl_tfd_frame *tfd; | |
695 | u32 *control_flags; | |
696 | int txq_id = ctl->queue; | |
697 | struct iwl_tx_queue *txq = NULL; | |
698 | struct iwl_queue *q = NULL; | |
699 | dma_addr_t phys_addr; | |
700 | dma_addr_t txcmd_phys; | |
701 | dma_addr_t scratch_phys; | |
702 | struct iwl_cmd *out_cmd = NULL; | |
703 | struct iwl_tx_cmd *tx_cmd; | |
704 | u16 len, idx, len_org; | |
705 | u16 seq_number = 0; | |
706 | u8 id, hdr_len, unicast; | |
707 | u8 sta_id; | |
708 | u16 fc; | |
709 | u8 wait_write_ptr = 0; | |
710 | u8 tid = 0; | |
711 | u8 *qc = NULL; | |
712 | unsigned long flags; | |
713 | int ret; | |
714 | ||
715 | spin_lock_irqsave(&priv->lock, flags); | |
716 | if (iwl_is_rfkill(priv)) { | |
717 | IWL_DEBUG_DROP("Dropping - RF KILL\n"); | |
718 | goto drop_unlock; | |
719 | } | |
720 | ||
721 | if (!priv->vif) { | |
722 | IWL_DEBUG_DROP("Dropping - !priv->vif\n"); | |
723 | goto drop_unlock; | |
724 | } | |
725 | ||
726 | if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) { | |
727 | IWL_ERROR("ERROR: No TX rate available.\n"); | |
728 | goto drop_unlock; | |
729 | } | |
730 | ||
731 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
732 | id = 0; | |
733 | ||
734 | fc = le16_to_cpu(hdr->frame_control); | |
735 | ||
736 | #ifdef CONFIG_IWLWIFI_DEBUG | |
737 | if (ieee80211_is_auth(fc)) | |
738 | IWL_DEBUG_TX("Sending AUTH frame\n"); | |
739 | else if (ieee80211_is_assoc_request(fc)) | |
740 | IWL_DEBUG_TX("Sending ASSOC frame\n"); | |
741 | else if (ieee80211_is_reassoc_request(fc)) | |
742 | IWL_DEBUG_TX("Sending REASSOC frame\n"); | |
743 | #endif | |
744 | ||
745 | /* drop all data frame if we are not associated */ | |
746 | if (((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) && | |
747 | (!iwl_is_associated(priv) || | |
748 | ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id) || | |
749 | !priv->assoc_station_added)) { | |
750 | IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n"); | |
751 | goto drop_unlock; | |
752 | } | |
753 | ||
754 | spin_unlock_irqrestore(&priv->lock, flags); | |
755 | ||
756 | hdr_len = ieee80211_get_hdrlen(fc); | |
757 | ||
758 | /* Find (or create) index into station table for destination station */ | |
759 | sta_id = iwl_get_sta_id(priv, hdr); | |
760 | if (sta_id == IWL_INVALID_STATION) { | |
761 | DECLARE_MAC_BUF(mac); | |
762 | ||
763 | IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n", | |
764 | print_mac(mac, hdr->addr1)); | |
765 | goto drop; | |
766 | } | |
767 | ||
768 | IWL_DEBUG_TX("station Id %d\n", sta_id); | |
769 | ||
770 | if (ieee80211_is_qos_data(fc)) { | |
771 | qc = ieee80211_get_qos_ctrl(hdr, hdr_len); | |
772 | tid = qc[0] & 0xf; | |
773 | seq_number = priv->stations[sta_id].tid[tid].seq_number & | |
774 | IEEE80211_SCTL_SEQ; | |
775 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
776 | (hdr->seq_ctrl & | |
777 | __constant_cpu_to_le16(IEEE80211_SCTL_FRAG)); | |
778 | seq_number += 0x10; | |
779 | #ifdef CONFIG_IWL4965_HT | |
780 | /* aggregation is on for this <sta,tid> */ | |
781 | if (ctl->flags & IEEE80211_TXCTL_AMPDU) | |
782 | txq_id = priv->stations[sta_id].tid[tid].agg.txq_id; | |
783 | priv->stations[sta_id].tid[tid].tfds_in_queue++; | |
784 | #endif /* CONFIG_IWL4965_HT */ | |
785 | } | |
786 | ||
787 | /* Descriptor for chosen Tx queue */ | |
788 | txq = &priv->txq[txq_id]; | |
789 | q = &txq->q; | |
790 | ||
791 | spin_lock_irqsave(&priv->lock, flags); | |
792 | ||
793 | /* Set up first empty TFD within this queue's circular TFD buffer */ | |
794 | tfd = &txq->bd[q->write_ptr]; | |
795 | memset(tfd, 0, sizeof(*tfd)); | |
796 | control_flags = (u32 *) tfd; | |
797 | idx = get_cmd_index(q, q->write_ptr, 0); | |
798 | ||
799 | /* Set up driver data for this TFD */ | |
800 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); | |
801 | txq->txb[q->write_ptr].skb[0] = skb; | |
802 | memcpy(&(txq->txb[q->write_ptr].status.control), | |
803 | ctl, sizeof(struct ieee80211_tx_control)); | |
804 | ||
805 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
806 | out_cmd = &txq->cmd[idx]; | |
807 | tx_cmd = &out_cmd->cmd.tx; | |
808 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
809 | memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd)); | |
810 | ||
811 | /* | |
812 | * Set up the Tx-command (not MAC!) header. | |
813 | * Store the chosen Tx queue and TFD index within the sequence field; | |
814 | * after Tx, uCode's Tx response will return this value so driver can | |
815 | * locate the frame within the tx queue and do post-tx processing. | |
816 | */ | |
817 | out_cmd->hdr.cmd = REPLY_TX; | |
818 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
819 | INDEX_TO_SEQ(q->write_ptr))); | |
820 | ||
821 | /* Copy MAC header from skb into command buffer */ | |
822 | memcpy(tx_cmd->hdr, hdr, hdr_len); | |
823 | ||
824 | /* | |
825 | * Use the first empty entry in this queue's command buffer array | |
826 | * to contain the Tx command and MAC header concatenated together | |
827 | * (payload data will be in another buffer). | |
828 | * Size of this varies, due to varying MAC header length. | |
829 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
830 | * of the MAC header (device reads on dword boundaries). | |
831 | * We'll tell device about this padding later. | |
832 | */ | |
833 | len = sizeof(struct iwl_tx_cmd) + | |
834 | sizeof(struct iwl_cmd_header) + hdr_len; | |
835 | ||
836 | len_org = len; | |
837 | len = (len + 3) & ~3; | |
838 | ||
839 | if (len_org != len) | |
840 | len_org = 1; | |
841 | else | |
842 | len_org = 0; | |
843 | ||
844 | /* Physical address of this Tx command's header (not MAC header!), | |
845 | * within command buffer array. */ | |
846 | txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl_cmd) * idx + | |
847 | offsetof(struct iwl_cmd, hdr); | |
848 | ||
849 | /* Add buffer containing Tx command and MAC(!) header to TFD's | |
850 | * first entry */ | |
851 | iwl_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len); | |
852 | ||
853 | if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) | |
854 | iwl_tx_cmd_build_hwcrypto(priv, ctl, tx_cmd, skb, sta_id); | |
855 | ||
856 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
857 | * if any (802.11 null frames have no payload). */ | |
858 | len = skb->len - hdr_len; | |
859 | if (len) { | |
860 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
861 | len, PCI_DMA_TODEVICE); | |
862 | iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len); | |
863 | } | |
864 | ||
865 | /* Tell NIC about any 2-byte padding after MAC header */ | |
866 | if (len_org) | |
867 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
868 | ||
869 | /* Total # bytes to be transmitted */ | |
870 | len = (u16)skb->len; | |
871 | tx_cmd->len = cpu_to_le16(len); | |
872 | /* TODO need this for burst mode later on */ | |
873 | iwl_tx_cmd_build_basic(priv, tx_cmd, ctl, hdr, unicast, sta_id); | |
874 | ||
875 | /* set is_hcca to 0; it probably will never be implemented */ | |
876 | iwl_tx_cmd_build_rate(priv, tx_cmd, ctl, fc, sta_id, 0); | |
877 | ||
878 | iwl_update_tx_stats(priv, fc, len); | |
879 | ||
880 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + | |
881 | offsetof(struct iwl_tx_cmd, scratch); | |
882 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
883 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys); | |
884 | ||
885 | if (!ieee80211_get_morefrag(hdr)) { | |
886 | txq->need_update = 1; | |
887 | if (qc) | |
888 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
889 | } else { | |
890 | wait_write_ptr = 1; | |
891 | txq->need_update = 0; | |
892 | } | |
893 | ||
894 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); | |
895 | ||
896 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
897 | ||
898 | /* Set up entry for this TFD in Tx byte-count array */ | |
899 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len); | |
900 | ||
901 | /* Tell device the write index *just past* this latest filled TFD */ | |
902 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
903 | ret = iwl_txq_update_write_ptr(priv, txq); | |
904 | spin_unlock_irqrestore(&priv->lock, flags); | |
905 | ||
906 | if (ret) | |
907 | return ret; | |
908 | ||
909 | if ((iwl_queue_space(q) < q->high_mark) | |
910 | && priv->mac80211_registered) { | |
911 | if (wait_write_ptr) { | |
912 | spin_lock_irqsave(&priv->lock, flags); | |
913 | txq->need_update = 1; | |
914 | iwl_txq_update_write_ptr(priv, txq); | |
915 | spin_unlock_irqrestore(&priv->lock, flags); | |
916 | } | |
917 | ||
918 | ieee80211_stop_queue(priv->hw, ctl->queue); | |
919 | } | |
920 | ||
921 | return 0; | |
922 | ||
923 | drop_unlock: | |
924 | spin_unlock_irqrestore(&priv->lock, flags); | |
925 | drop: | |
926 | return -1; | |
927 | } | |
928 | EXPORT_SYMBOL(iwl_tx_skb); | |
929 | ||
930 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
931 | ||
932 | /** | |
933 | * iwl_enqueue_hcmd - enqueue a uCode command | |
934 | * @priv: device private data point | |
935 | * @cmd: a point to the ucode command structure | |
936 | * | |
937 | * The function returns < 0 values to indicate the operation is | |
938 | * failed. On success, it turns the index (> 0) of command in the | |
939 | * command queue. | |
940 | */ | |
941 | int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
942 | { | |
943 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; | |
944 | struct iwl_queue *q = &txq->q; | |
945 | struct iwl_tfd_frame *tfd; | |
946 | u32 *control_flags; | |
947 | struct iwl_cmd *out_cmd; | |
948 | u32 idx; | |
949 | u16 fix_size; | |
950 | dma_addr_t phys_addr; | |
951 | int ret; | |
952 | unsigned long flags; | |
953 | ||
954 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); | |
955 | fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
956 | ||
957 | /* If any of the command structures end up being larger than | |
958 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
959 | * we will need to increase the size of the TFD entries */ | |
960 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
961 | !(cmd->meta.flags & CMD_SIZE_HUGE)); | |
962 | ||
963 | if (iwl_is_rfkill(priv)) { | |
964 | IWL_DEBUG_INFO("Not sending command - RF KILL"); | |
965 | return -EIO; | |
966 | } | |
967 | ||
968 | if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) { | |
969 | IWL_ERROR("No space for Tx\n"); | |
970 | return -ENOSPC; | |
971 | } | |
972 | ||
973 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
974 | ||
975 | tfd = &txq->bd[q->write_ptr]; | |
976 | memset(tfd, 0, sizeof(*tfd)); | |
977 | ||
978 | control_flags = (u32 *) tfd; | |
979 | ||
980 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); | |
981 | out_cmd = &txq->cmd[idx]; | |
982 | ||
983 | out_cmd->hdr.cmd = cmd->id; | |
984 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); | |
985 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
986 | ||
987 | /* At this point, the out_cmd now has all of the incoming cmd | |
988 | * information */ | |
989 | ||
990 | out_cmd->hdr.flags = 0; | |
991 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
992 | INDEX_TO_SEQ(q->write_ptr)); | |
993 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) | |
994 | out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME); | |
995 | ||
996 | phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx + | |
997 | offsetof(struct iwl_cmd, hdr); | |
998 | iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size); | |
999 | ||
1000 | IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, " | |
1001 | "%d bytes at %d[%d]:%d\n", | |
1002 | get_cmd_string(out_cmd->hdr.cmd), | |
1003 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), | |
1004 | fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM); | |
1005 | ||
1006 | txq->need_update = 1; | |
1007 | ||
1008 | /* Set up entry in queue's byte count circular buffer */ | |
1009 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); | |
1010 | ||
1011 | /* Increment and update queue's write index */ | |
1012 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1013 | ret = iwl_txq_update_write_ptr(priv, txq); | |
1014 | ||
1015 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
1016 | return ret ? ret : idx; | |
1017 | } | |
1018 |