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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
fd4abac5 | 30 | #include <linux/etherdevice.h> |
1053d35f RR |
31 | #include <net/mac80211.h> |
32 | #include "iwl-eeprom.h" | |
33 | #include "iwl-dev.h" | |
34 | #include "iwl-core.h" | |
35 | #include "iwl-sta.h" | |
36 | #include "iwl-io.h" | |
37 | #include "iwl-helpers.h" | |
38 | ||
30e553e3 TW |
39 | static const u16 default_tid_to_tx_fifo[] = { |
40 | IWL_TX_FIFO_AC1, | |
41 | IWL_TX_FIFO_AC0, | |
42 | IWL_TX_FIFO_AC0, | |
43 | IWL_TX_FIFO_AC1, | |
44 | IWL_TX_FIFO_AC2, | |
45 | IWL_TX_FIFO_AC2, | |
46 | IWL_TX_FIFO_AC3, | |
47 | IWL_TX_FIFO_AC3, | |
48 | IWL_TX_FIFO_NONE, | |
49 | IWL_TX_FIFO_NONE, | |
50 | IWL_TX_FIFO_NONE, | |
51 | IWL_TX_FIFO_NONE, | |
52 | IWL_TX_FIFO_NONE, | |
53 | IWL_TX_FIFO_NONE, | |
54 | IWL_TX_FIFO_NONE, | |
55 | IWL_TX_FIFO_NONE, | |
56 | IWL_TX_FIFO_AC3 | |
57 | }; | |
58 | ||
4ddbb7d0 TW |
59 | static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv, |
60 | struct iwl_dma_ptr *ptr, size_t size) | |
61 | { | |
62 | ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma); | |
63 | if (!ptr->addr) | |
64 | return -ENOMEM; | |
65 | ptr->size = size; | |
66 | return 0; | |
67 | } | |
68 | ||
69 | static inline void iwl_free_dma_ptr(struct iwl_priv *priv, | |
70 | struct iwl_dma_ptr *ptr) | |
71 | { | |
72 | if (unlikely(!ptr->addr)) | |
73 | return; | |
74 | ||
75 | pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma); | |
76 | memset(ptr, 0, sizeof(*ptr)); | |
77 | } | |
78 | ||
fd4abac5 TW |
79 | /** |
80 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
81 | */ | |
82 | int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
83 | { | |
84 | u32 reg = 0; | |
85 | int ret = 0; | |
86 | int txq_id = txq->q.id; | |
87 | ||
88 | if (txq->need_update == 0) | |
89 | return ret; | |
90 | ||
91 | /* if we're trying to save power */ | |
92 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
93 | /* wake up nic if it's powered down ... | |
94 | * uCode will wake up, and interrupt us again, so next | |
95 | * time we'll skip this part. */ | |
96 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
97 | ||
98 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
e1623446 | 99 | IWL_DEBUG_INFO(priv, "Requesting wakeup, GP1 = 0x%x\n", reg); |
fd4abac5 TW |
100 | iwl_set_bit(priv, CSR_GP_CNTRL, |
101 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
102 | return ret; | |
103 | } | |
104 | ||
fd4abac5 TW |
105 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
106 | txq->q.write_ptr | (txq_id << 8)); | |
fd4abac5 TW |
107 | |
108 | /* else not in power-save mode, uCode will never sleep when we're | |
109 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
110 | } else | |
111 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
112 | txq->q.write_ptr | (txq_id << 8)); | |
113 | ||
114 | txq->need_update = 0; | |
115 | ||
116 | return ret; | |
117 | } | |
118 | EXPORT_SYMBOL(iwl_txq_update_write_ptr); | |
119 | ||
120 | ||
1053d35f RR |
121 | /** |
122 | * iwl_tx_queue_free - Deallocate DMA queue. | |
123 | * @txq: Transmit queue to deallocate. | |
124 | * | |
125 | * Empty queue by removing and destroying all BD's. | |
126 | * Free all buffers. | |
127 | * 0-fill, but do not free "txq" descriptor structure. | |
128 | */ | |
a8e74e27 | 129 | void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id) |
1053d35f | 130 | { |
da99c4b6 | 131 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; |
443cfd45 | 132 | struct iwl_queue *q = &txq->q; |
1053d35f | 133 | struct pci_dev *dev = priv->pci_dev; |
961ba60a | 134 | int i, len; |
1053d35f RR |
135 | |
136 | if (q->n_bd == 0) | |
137 | return; | |
138 | ||
139 | /* first, empty all BD's */ | |
140 | for (; q->write_ptr != q->read_ptr; | |
141 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) | |
7aaa1d79 | 142 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); |
1053d35f | 143 | |
c2acea8e | 144 | len = sizeof(struct iwl_device_cmd) * q->n_window; |
1053d35f RR |
145 | |
146 | /* De-alloc array of command/tx buffers */ | |
961ba60a | 147 | for (i = 0; i < TFD_TX_CMD_SLOTS; i++) |
da99c4b6 | 148 | kfree(txq->cmd[i]); |
1053d35f RR |
149 | |
150 | /* De-alloc circular buffer of TFDs */ | |
151 | if (txq->q.n_bd) | |
a8e74e27 | 152 | pci_free_consistent(dev, priv->hw_params.tfd_size * |
499b1883 | 153 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
1053d35f RR |
154 | |
155 | /* De-alloc array of per-TFD driver data */ | |
156 | kfree(txq->txb); | |
157 | txq->txb = NULL; | |
158 | ||
c2acea8e JB |
159 | /* deallocate arrays */ |
160 | kfree(txq->cmd); | |
161 | kfree(txq->meta); | |
162 | txq->cmd = NULL; | |
163 | txq->meta = NULL; | |
164 | ||
1053d35f RR |
165 | /* 0-fill queue descriptor structure */ |
166 | memset(txq, 0, sizeof(*txq)); | |
167 | } | |
a8e74e27 | 168 | EXPORT_SYMBOL(iwl_tx_queue_free); |
961ba60a TW |
169 | |
170 | /** | |
171 | * iwl_cmd_queue_free - Deallocate DMA queue. | |
172 | * @txq: Transmit queue to deallocate. | |
173 | * | |
174 | * Empty queue by removing and destroying all BD's. | |
175 | * Free all buffers. | |
176 | * 0-fill, but do not free "txq" descriptor structure. | |
177 | */ | |
3e5d238f | 178 | void iwl_cmd_queue_free(struct iwl_priv *priv) |
961ba60a TW |
179 | { |
180 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; | |
181 | struct iwl_queue *q = &txq->q; | |
182 | struct pci_dev *dev = priv->pci_dev; | |
183 | int i, len; | |
184 | ||
185 | if (q->n_bd == 0) | |
186 | return; | |
187 | ||
c2acea8e | 188 | len = sizeof(struct iwl_device_cmd) * q->n_window; |
961ba60a TW |
189 | len += IWL_MAX_SCAN_SIZE; |
190 | ||
191 | /* De-alloc array of command/tx buffers */ | |
192 | for (i = 0; i <= TFD_CMD_SLOTS; i++) | |
193 | kfree(txq->cmd[i]); | |
194 | ||
195 | /* De-alloc circular buffer of TFDs */ | |
196 | if (txq->q.n_bd) | |
3e5d238f | 197 | pci_free_consistent(dev, priv->hw_params.tfd_size * |
499b1883 | 198 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
961ba60a TW |
199 | |
200 | /* 0-fill queue descriptor structure */ | |
201 | memset(txq, 0, sizeof(*txq)); | |
202 | } | |
3e5d238f AK |
203 | EXPORT_SYMBOL(iwl_cmd_queue_free); |
204 | ||
fd4abac5 TW |
205 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
206 | * DMA services | |
207 | * | |
208 | * Theory of operation | |
209 | * | |
210 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
211 | * of buffer descriptors, each of which points to one or more data buffers for | |
212 | * the device to read from or fill. Driver and device exchange status of each | |
213 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
214 | * entries in each circular buffer, to protect against confusing empty and full | |
215 | * queue states. | |
216 | * | |
217 | * The device reads or writes the data in the queues via the device's several | |
218 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
219 | * | |
220 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
221 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
222 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
223 | * Tx queue resumed. | |
224 | * | |
225 | * See more detailed info in iwl-4965-hw.h. | |
226 | ***************************************************/ | |
227 | ||
228 | int iwl_queue_space(const struct iwl_queue *q) | |
229 | { | |
230 | int s = q->read_ptr - q->write_ptr; | |
231 | ||
232 | if (q->read_ptr > q->write_ptr) | |
233 | s -= q->n_bd; | |
234 | ||
235 | if (s <= 0) | |
236 | s += q->n_window; | |
237 | /* keep some reserve to not confuse empty and full situations */ | |
238 | s -= 2; | |
239 | if (s < 0) | |
240 | s = 0; | |
241 | return s; | |
242 | } | |
243 | EXPORT_SYMBOL(iwl_queue_space); | |
244 | ||
245 | ||
1053d35f RR |
246 | /** |
247 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
248 | */ | |
443cfd45 | 249 | static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
250 | int count, int slots_num, u32 id) |
251 | { | |
252 | q->n_bd = count; | |
253 | q->n_window = slots_num; | |
254 | q->id = id; | |
255 | ||
256 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
257 | * and iwl_queue_dec_wrap are broken. */ | |
258 | BUG_ON(!is_power_of_2(count)); | |
259 | ||
260 | /* slots_num must be power-of-two size, otherwise | |
261 | * get_cmd_index is broken. */ | |
262 | BUG_ON(!is_power_of_2(slots_num)); | |
263 | ||
264 | q->low_mark = q->n_window / 4; | |
265 | if (q->low_mark < 4) | |
266 | q->low_mark = 4; | |
267 | ||
268 | q->high_mark = q->n_window / 8; | |
269 | if (q->high_mark < 2) | |
270 | q->high_mark = 2; | |
271 | ||
272 | q->write_ptr = q->read_ptr = 0; | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
277 | /** | |
278 | * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
279 | */ | |
280 | static int iwl_tx_queue_alloc(struct iwl_priv *priv, | |
16466903 | 281 | struct iwl_tx_queue *txq, u32 id) |
1053d35f RR |
282 | { |
283 | struct pci_dev *dev = priv->pci_dev; | |
3978e5bc | 284 | size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; |
1053d35f RR |
285 | |
286 | /* Driver private data, only for Tx (not command) queues, | |
287 | * not shared with device. */ | |
288 | if (id != IWL_CMD_QUEUE_NUM) { | |
289 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
290 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
291 | if (!txq->txb) { | |
15b1687c | 292 | IWL_ERR(priv, "kmalloc for auxiliary BD " |
1053d35f RR |
293 | "structures failed\n"); |
294 | goto error; | |
295 | } | |
3978e5bc | 296 | } else { |
1053d35f | 297 | txq->txb = NULL; |
3978e5bc | 298 | } |
1053d35f RR |
299 | |
300 | /* Circular buffer of transmit frame descriptors (TFDs), | |
301 | * shared with device */ | |
3978e5bc | 302 | txq->tfds = pci_alloc_consistent(dev, tfd_sz, &txq->q.dma_addr); |
1053d35f | 303 | |
499b1883 | 304 | if (!txq->tfds) { |
3978e5bc | 305 | IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz); |
1053d35f RR |
306 | goto error; |
307 | } | |
308 | txq->q.id = id; | |
309 | ||
310 | return 0; | |
311 | ||
312 | error: | |
313 | kfree(txq->txb); | |
314 | txq->txb = NULL; | |
315 | ||
316 | return -ENOMEM; | |
317 | } | |
318 | ||
1053d35f RR |
319 | /** |
320 | * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue | |
321 | */ | |
a8e74e27 SO |
322 | int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
323 | int slots_num, u32 txq_id) | |
1053d35f | 324 | { |
da99c4b6 | 325 | int i, len; |
73b7d742 | 326 | int ret; |
c2acea8e | 327 | int actual_slots = slots_num; |
1053d35f RR |
328 | |
329 | /* | |
330 | * Alloc buffer array for commands (Tx or other types of commands). | |
331 | * For the command queue (#4), allocate command space + one big | |
332 | * command for scan, since scan command is very huge; the system will | |
333 | * not have two scans at the same time, so only one is needed. | |
334 | * For normal Tx queues (all other queues), no super-size command | |
335 | * space is needed. | |
336 | */ | |
c2acea8e JB |
337 | if (txq_id == IWL_CMD_QUEUE_NUM) |
338 | actual_slots++; | |
339 | ||
340 | txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots, | |
341 | GFP_KERNEL); | |
342 | txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots, | |
343 | GFP_KERNEL); | |
344 | ||
345 | if (!txq->meta || !txq->cmd) | |
346 | goto out_free_arrays; | |
347 | ||
348 | len = sizeof(struct iwl_device_cmd); | |
349 | for (i = 0; i < actual_slots; i++) { | |
350 | /* only happens for cmd queue */ | |
351 | if (i == slots_num) | |
352 | len += IWL_MAX_SCAN_SIZE; | |
da99c4b6 | 353 | |
49898852 | 354 | txq->cmd[i] = kmalloc(len, GFP_KERNEL); |
da99c4b6 | 355 | if (!txq->cmd[i]) |
73b7d742 | 356 | goto err; |
da99c4b6 | 357 | } |
1053d35f RR |
358 | |
359 | /* Alloc driver data array and TFD circular buffer */ | |
73b7d742 TW |
360 | ret = iwl_tx_queue_alloc(priv, txq, txq_id); |
361 | if (ret) | |
362 | goto err; | |
1053d35f | 363 | |
1053d35f RR |
364 | txq->need_update = 0; |
365 | ||
45af8195 JB |
366 | /* aggregation TX queues will get their ID when aggregation begins */ |
367 | if (txq_id <= IWL_TX_FIFO_AC3) | |
368 | txq->swq_id = txq_id; | |
369 | ||
1053d35f RR |
370 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise |
371 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
372 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
373 | ||
374 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
375 | iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
376 | ||
377 | /* Tell device where to find queue */ | |
a8e74e27 | 378 | priv->cfg->ops->lib->txq_init(priv, txq); |
1053d35f RR |
379 | |
380 | return 0; | |
73b7d742 | 381 | err: |
c2acea8e | 382 | for (i = 0; i < actual_slots; i++) |
73b7d742 | 383 | kfree(txq->cmd[i]); |
c2acea8e JB |
384 | out_free_arrays: |
385 | kfree(txq->meta); | |
386 | kfree(txq->cmd); | |
73b7d742 | 387 | |
73b7d742 | 388 | return -ENOMEM; |
1053d35f | 389 | } |
a8e74e27 SO |
390 | EXPORT_SYMBOL(iwl_tx_queue_init); |
391 | ||
da1bc453 TW |
392 | /** |
393 | * iwl_hw_txq_ctx_free - Free TXQ Context | |
394 | * | |
395 | * Destroy all TX DMA queues and structures | |
396 | */ | |
397 | void iwl_hw_txq_ctx_free(struct iwl_priv *priv) | |
398 | { | |
399 | int txq_id; | |
400 | ||
401 | /* Tx queues */ | |
402 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
961ba60a TW |
403 | if (txq_id == IWL_CMD_QUEUE_NUM) |
404 | iwl_cmd_queue_free(priv); | |
405 | else | |
406 | iwl_tx_queue_free(priv, txq_id); | |
da1bc453 | 407 | |
4ddbb7d0 TW |
408 | iwl_free_dma_ptr(priv, &priv->kw); |
409 | ||
410 | iwl_free_dma_ptr(priv, &priv->scd_bc_tbls); | |
da1bc453 TW |
411 | } |
412 | EXPORT_SYMBOL(iwl_hw_txq_ctx_free); | |
413 | ||
1053d35f RR |
414 | /** |
415 | * iwl_txq_ctx_reset - Reset TX queue context | |
a96a27f9 | 416 | * Destroys all DMA structures and initialize them again |
1053d35f RR |
417 | * |
418 | * @param priv | |
419 | * @return error code | |
420 | */ | |
421 | int iwl_txq_ctx_reset(struct iwl_priv *priv) | |
422 | { | |
423 | int ret = 0; | |
424 | int txq_id, slots_num; | |
da1bc453 | 425 | unsigned long flags; |
1053d35f | 426 | |
1053d35f RR |
427 | /* Free all tx/cmd queues and keep-warm buffer */ |
428 | iwl_hw_txq_ctx_free(priv); | |
429 | ||
4ddbb7d0 TW |
430 | ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls, |
431 | priv->hw_params.scd_bc_tbls_size); | |
432 | if (ret) { | |
15b1687c | 433 | IWL_ERR(priv, "Scheduler BC Table allocation failed\n"); |
4ddbb7d0 TW |
434 | goto error_bc_tbls; |
435 | } | |
1053d35f | 436 | /* Alloc keep-warm buffer */ |
4ddbb7d0 | 437 | ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE); |
1053d35f | 438 | if (ret) { |
15b1687c | 439 | IWL_ERR(priv, "Keep Warm allocation failed\n"); |
1053d35f RR |
440 | goto error_kw; |
441 | } | |
da1bc453 | 442 | spin_lock_irqsave(&priv->lock, flags); |
1053d35f RR |
443 | |
444 | /* Turn off all Tx DMA fifos */ | |
da1bc453 TW |
445 | priv->cfg->ops->lib->txq_set_sched(priv, 0); |
446 | ||
4ddbb7d0 TW |
447 | /* Tell NIC where to find the "keep warm" buffer */ |
448 | iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4); | |
449 | ||
da1bc453 TW |
450 | spin_unlock_irqrestore(&priv->lock, flags); |
451 | ||
da1bc453 | 452 | /* Alloc and init all Tx queues, including the command queue (#4) */ |
1053d35f RR |
453 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { |
454 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? | |
455 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
456 | ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num, | |
457 | txq_id); | |
458 | if (ret) { | |
15b1687c | 459 | IWL_ERR(priv, "Tx %d queue init failed\n", txq_id); |
1053d35f RR |
460 | goto error; |
461 | } | |
462 | } | |
463 | ||
464 | return ret; | |
465 | ||
466 | error: | |
467 | iwl_hw_txq_ctx_free(priv); | |
4ddbb7d0 | 468 | iwl_free_dma_ptr(priv, &priv->kw); |
1053d35f | 469 | error_kw: |
4ddbb7d0 TW |
470 | iwl_free_dma_ptr(priv, &priv->scd_bc_tbls); |
471 | error_bc_tbls: | |
1053d35f RR |
472 | return ret; |
473 | } | |
a33c2f47 | 474 | |
da1bc453 TW |
475 | /** |
476 | * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory | |
477 | */ | |
478 | void iwl_txq_ctx_stop(struct iwl_priv *priv) | |
479 | { | |
f3f911d1 | 480 | int ch; |
da1bc453 TW |
481 | unsigned long flags; |
482 | ||
da1bc453 TW |
483 | /* Turn off all Tx DMA fifos */ |
484 | spin_lock_irqsave(&priv->lock, flags); | |
da1bc453 TW |
485 | |
486 | priv->cfg->ops->lib->txq_set_sched(priv, 0); | |
487 | ||
488 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
f3f911d1 ZY |
489 | for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) { |
490 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
da1bc453 | 491 | iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG, |
f3f911d1 | 492 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), |
f056658b | 493 | 1000); |
da1bc453 | 494 | } |
da1bc453 TW |
495 | spin_unlock_irqrestore(&priv->lock, flags); |
496 | ||
497 | /* Deallocate memory for all Tx queues */ | |
498 | iwl_hw_txq_ctx_free(priv); | |
499 | } | |
500 | EXPORT_SYMBOL(iwl_txq_ctx_stop); | |
fd4abac5 TW |
501 | |
502 | /* | |
503 | * handle build REPLY_TX command notification. | |
504 | */ | |
505 | static void iwl_tx_cmd_build_basic(struct iwl_priv *priv, | |
506 | struct iwl_tx_cmd *tx_cmd, | |
e039fa4a | 507 | struct ieee80211_tx_info *info, |
fd4abac5 | 508 | struct ieee80211_hdr *hdr, |
0e7690f1 | 509 | u8 std_id) |
fd4abac5 | 510 | { |
fd7c8a40 | 511 | __le16 fc = hdr->frame_control; |
fd4abac5 TW |
512 | __le32 tx_flags = tx_cmd->tx_flags; |
513 | ||
514 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
e039fa4a | 515 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
fd4abac5 | 516 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 517 | if (ieee80211_is_mgmt(fc)) |
fd4abac5 | 518 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 519 | if (ieee80211_is_probe_resp(fc) && |
fd4abac5 TW |
520 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
521 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
522 | } else { | |
523 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
524 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
525 | } | |
526 | ||
fd7c8a40 | 527 | if (ieee80211_is_back_req(fc)) |
fd4abac5 TW |
528 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; |
529 | ||
530 | ||
531 | tx_cmd->sta_id = std_id; | |
8b7b1e05 | 532 | if (ieee80211_has_morefrags(fc)) |
fd4abac5 TW |
533 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
534 | ||
fd7c8a40 HH |
535 | if (ieee80211_is_data_qos(fc)) { |
536 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
fd4abac5 TW |
537 | tx_cmd->tid_tspec = qc[0] & 0xf; |
538 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
539 | } else { | |
540 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
541 | } | |
542 | ||
a326a5d0 | 543 | priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags); |
fd4abac5 TW |
544 | |
545 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
546 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
547 | ||
548 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
549 | if (ieee80211_is_mgmt(fc)) { |
550 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
fd4abac5 TW |
551 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); |
552 | else | |
553 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); | |
554 | } else { | |
555 | tx_cmd->timeout.pm_frame_timeout = 0; | |
556 | } | |
557 | ||
558 | tx_cmd->driver_txop = 0; | |
559 | tx_cmd->tx_flags = tx_flags; | |
560 | tx_cmd->next_frame_len = 0; | |
561 | } | |
562 | ||
563 | #define RTS_HCCA_RETRY_LIMIT 3 | |
564 | #define RTS_DFAULT_RETRY_LIMIT 60 | |
565 | ||
566 | static void iwl_tx_cmd_build_rate(struct iwl_priv *priv, | |
567 | struct iwl_tx_cmd *tx_cmd, | |
e039fa4a | 568 | struct ieee80211_tx_info *info, |
fd7c8a40 | 569 | __le16 fc, int sta_id, |
fd4abac5 TW |
570 | int is_hcca) |
571 | { | |
76eff18b TW |
572 | u32 rate_flags = 0; |
573 | int rate_idx; | |
fd4abac5 TW |
574 | u8 rts_retry_limit = 0; |
575 | u8 data_retry_limit = 0; | |
576 | u8 rate_plcp; | |
2e92e6f2 | 577 | |
e039fa4a | 578 | rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff, |
2e92e6f2 | 579 | IWL_RATE_COUNT - 1); |
fd4abac5 TW |
580 | |
581 | rate_plcp = iwl_rates[rate_idx].plcp; | |
582 | ||
583 | rts_retry_limit = (is_hcca) ? | |
584 | RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT; | |
585 | ||
586 | if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE)) | |
587 | rate_flags |= RATE_MCS_CCK_MSK; | |
588 | ||
589 | ||
fd7c8a40 | 590 | if (ieee80211_is_probe_resp(fc)) { |
fd4abac5 TW |
591 | data_retry_limit = 3; |
592 | if (data_retry_limit < rts_retry_limit) | |
593 | rts_retry_limit = data_retry_limit; | |
594 | } else | |
595 | data_retry_limit = IWL_DEFAULT_TX_RETRY; | |
596 | ||
597 | if (priv->data_retry_limit != -1) | |
598 | data_retry_limit = priv->data_retry_limit; | |
599 | ||
600 | ||
601 | if (ieee80211_is_data(fc)) { | |
602 | tx_cmd->initial_rate_index = 0; | |
603 | tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; | |
604 | } else { | |
fd7c8a40 HH |
605 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { |
606 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
607 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
608 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
609 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
fd4abac5 TW |
610 | if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) { |
611 | tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
612 | tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK; | |
613 | } | |
614 | break; | |
615 | default: | |
616 | break; | |
617 | } | |
618 | ||
76eff18b TW |
619 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant); |
620 | rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant); | |
fd4abac5 TW |
621 | } |
622 | ||
623 | tx_cmd->rts_retry_limit = rts_retry_limit; | |
624 | tx_cmd->data_retry_limit = data_retry_limit; | |
e7d326ac | 625 | tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags); |
fd4abac5 TW |
626 | } |
627 | ||
628 | static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv, | |
e039fa4a | 629 | struct ieee80211_tx_info *info, |
fd4abac5 TW |
630 | struct iwl_tx_cmd *tx_cmd, |
631 | struct sk_buff *skb_frag, | |
632 | int sta_id) | |
633 | { | |
e039fa4a | 634 | struct ieee80211_key_conf *keyconf = info->control.hw_key; |
fd4abac5 | 635 | |
ccc038ab | 636 | switch (keyconf->alg) { |
fd4abac5 TW |
637 | case ALG_CCMP: |
638 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; | |
ccc038ab | 639 | memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); |
e039fa4a | 640 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
fd4abac5 | 641 | tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; |
e1623446 | 642 | IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n"); |
fd4abac5 TW |
643 | break; |
644 | ||
645 | case ALG_TKIP: | |
646 | tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; | |
ccc038ab | 647 | ieee80211_get_tkip_key(keyconf, skb_frag, |
fd4abac5 | 648 | IEEE80211_TKIP_P2_KEY, tx_cmd->key); |
e1623446 | 649 | IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n"); |
fd4abac5 TW |
650 | break; |
651 | ||
652 | case ALG_WEP: | |
fd4abac5 | 653 | tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP | |
ccc038ab EG |
654 | (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT); |
655 | ||
656 | if (keyconf->keylen == WEP_KEY_LEN_128) | |
657 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; | |
658 | ||
659 | memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); | |
fd4abac5 | 660 | |
e1623446 | 661 | IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption " |
ccc038ab | 662 | "with key %d\n", keyconf->keyidx); |
fd4abac5 TW |
663 | break; |
664 | ||
665 | default: | |
978785a3 | 666 | IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg); |
fd4abac5 TW |
667 | break; |
668 | } | |
669 | } | |
670 | ||
fd4abac5 TW |
671 | /* |
672 | * start REPLY_TX command process | |
673 | */ | |
e039fa4a | 674 | int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
fd4abac5 TW |
675 | { |
676 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 677 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
f3674227 TW |
678 | struct iwl_tx_queue *txq; |
679 | struct iwl_queue *q; | |
c2acea8e JB |
680 | struct iwl_device_cmd *out_cmd; |
681 | struct iwl_cmd_meta *out_meta; | |
f3674227 TW |
682 | struct iwl_tx_cmd *tx_cmd; |
683 | int swq_id, txq_id; | |
fd4abac5 TW |
684 | dma_addr_t phys_addr; |
685 | dma_addr_t txcmd_phys; | |
686 | dma_addr_t scratch_phys; | |
b88b15df | 687 | u16 len, len_org; |
fd4abac5 | 688 | u16 seq_number = 0; |
fd7c8a40 | 689 | __le16 fc; |
0e7690f1 | 690 | u8 hdr_len; |
f3674227 | 691 | u8 sta_id; |
fd4abac5 TW |
692 | u8 wait_write_ptr = 0; |
693 | u8 tid = 0; | |
694 | u8 *qc = NULL; | |
695 | unsigned long flags; | |
696 | int ret; | |
697 | ||
698 | spin_lock_irqsave(&priv->lock, flags); | |
699 | if (iwl_is_rfkill(priv)) { | |
e1623446 | 700 | IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n"); |
fd4abac5 TW |
701 | goto drop_unlock; |
702 | } | |
703 | ||
e039fa4a | 704 | if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == |
2e92e6f2 | 705 | IWL_INVALID_RATE) { |
15b1687c | 706 | IWL_ERR(priv, "ERROR: No TX rate available.\n"); |
fd4abac5 TW |
707 | goto drop_unlock; |
708 | } | |
709 | ||
fd7c8a40 | 710 | fc = hdr->frame_control; |
fd4abac5 TW |
711 | |
712 | #ifdef CONFIG_IWLWIFI_DEBUG | |
713 | if (ieee80211_is_auth(fc)) | |
e1623446 | 714 | IWL_DEBUG_TX(priv, "Sending AUTH frame\n"); |
fd7c8a40 | 715 | else if (ieee80211_is_assoc_req(fc)) |
e1623446 | 716 | IWL_DEBUG_TX(priv, "Sending ASSOC frame\n"); |
fd7c8a40 | 717 | else if (ieee80211_is_reassoc_req(fc)) |
e1623446 | 718 | IWL_DEBUG_TX(priv, "Sending REASSOC frame\n"); |
fd4abac5 TW |
719 | #endif |
720 | ||
aa065263 | 721 | /* drop all non-injected data frame if we are not associated */ |
fd7c8a40 | 722 | if (ieee80211_is_data(fc) && |
aa065263 | 723 | !(info->flags & IEEE80211_TX_CTL_INJECTED) && |
d10c4ec8 | 724 | (!iwl_is_associated(priv) || |
05c914fe | 725 | ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) || |
d10c4ec8 | 726 | !priv->assoc_station_added)) { |
e1623446 | 727 | IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n"); |
fd4abac5 TW |
728 | goto drop_unlock; |
729 | } | |
730 | ||
7294ec95 | 731 | hdr_len = ieee80211_hdrlen(fc); |
fd4abac5 TW |
732 | |
733 | /* Find (or create) index into station table for destination station */ | |
aa065263 GS |
734 | if (info->flags & IEEE80211_TX_CTL_INJECTED) |
735 | sta_id = priv->hw_params.bcast_sta_id; | |
736 | else | |
737 | sta_id = iwl_get_sta_id(priv, hdr); | |
fd4abac5 | 738 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 739 | IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n", |
e174961c | 740 | hdr->addr1); |
3995bd93 | 741 | goto drop_unlock; |
fd4abac5 TW |
742 | } |
743 | ||
e1623446 | 744 | IWL_DEBUG_TX(priv, "station Id %d\n", sta_id); |
fd4abac5 | 745 | |
45af8195 | 746 | txq_id = skb_get_queue_mapping(skb); |
fd7c8a40 HH |
747 | if (ieee80211_is_data_qos(fc)) { |
748 | qc = ieee80211_get_qos_ctl(hdr); | |
7294ec95 | 749 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
e6a6cf4c RC |
750 | if (unlikely(tid >= MAX_TID_COUNT)) |
751 | goto drop_unlock; | |
f3674227 TW |
752 | seq_number = priv->stations[sta_id].tid[tid].seq_number; |
753 | seq_number &= IEEE80211_SCTL_SEQ; | |
754 | hdr->seq_ctrl = hdr->seq_ctrl & | |
c1b4aa3f | 755 | cpu_to_le16(IEEE80211_SCTL_FRAG); |
f3674227 | 756 | hdr->seq_ctrl |= cpu_to_le16(seq_number); |
fd4abac5 | 757 | seq_number += 0x10; |
fd4abac5 | 758 | /* aggregation is on for this <sta,tid> */ |
45af8195 | 759 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
fd4abac5 | 760 | txq_id = priv->stations[sta_id].tid[tid].agg.txq_id; |
fd4abac5 TW |
761 | } |
762 | ||
fd4abac5 | 763 | txq = &priv->txq[txq_id]; |
45af8195 | 764 | swq_id = txq->swq_id; |
fd4abac5 TW |
765 | q = &txq->q; |
766 | ||
3995bd93 JB |
767 | if (unlikely(iwl_queue_space(q) < q->high_mark)) |
768 | goto drop_unlock; | |
769 | ||
770 | if (ieee80211_is_data_qos(fc)) | |
771 | priv->stations[sta_id].tid[tid].tfds_in_queue++; | |
fd4abac5 | 772 | |
fd4abac5 TW |
773 | /* Set up driver data for this TFD */ |
774 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); | |
775 | txq->txb[q->write_ptr].skb[0] = skb; | |
fd4abac5 TW |
776 | |
777 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
b88b15df | 778 | out_cmd = txq->cmd[q->write_ptr]; |
c2acea8e | 779 | out_meta = &txq->meta[q->write_ptr]; |
fd4abac5 TW |
780 | tx_cmd = &out_cmd->cmd.tx; |
781 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
782 | memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd)); | |
783 | ||
784 | /* | |
785 | * Set up the Tx-command (not MAC!) header. | |
786 | * Store the chosen Tx queue and TFD index within the sequence field; | |
787 | * after Tx, uCode's Tx response will return this value so driver can | |
788 | * locate the frame within the tx queue and do post-tx processing. | |
789 | */ | |
790 | out_cmd->hdr.cmd = REPLY_TX; | |
791 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
792 | INDEX_TO_SEQ(q->write_ptr))); | |
793 | ||
794 | /* Copy MAC header from skb into command buffer */ | |
795 | memcpy(tx_cmd->hdr, hdr, hdr_len); | |
796 | ||
df833b1d RC |
797 | |
798 | /* Total # bytes to be transmitted */ | |
799 | len = (u16)skb->len; | |
800 | tx_cmd->len = cpu_to_le16(len); | |
801 | ||
802 | if (info->control.hw_key) | |
803 | iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id); | |
804 | ||
805 | /* TODO need this for burst mode later on */ | |
806 | iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id); | |
20594eb0 | 807 | iwl_dbg_log_tx_data_frame(priv, len, hdr); |
df833b1d RC |
808 | |
809 | /* set is_hcca to 0; it probably will never be implemented */ | |
810 | iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0); | |
811 | ||
22fdf3c9 | 812 | iwl_update_stats(priv, true, fc, len); |
fd4abac5 TW |
813 | /* |
814 | * Use the first empty entry in this queue's command buffer array | |
815 | * to contain the Tx command and MAC header concatenated together | |
816 | * (payload data will be in another buffer). | |
817 | * Size of this varies, due to varying MAC header length. | |
818 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
819 | * of the MAC header (device reads on dword boundaries). | |
820 | * We'll tell device about this padding later. | |
821 | */ | |
822 | len = sizeof(struct iwl_tx_cmd) + | |
823 | sizeof(struct iwl_cmd_header) + hdr_len; | |
824 | ||
825 | len_org = len; | |
826 | len = (len + 3) & ~3; | |
827 | ||
828 | if (len_org != len) | |
829 | len_org = 1; | |
830 | else | |
831 | len_org = 0; | |
832 | ||
df833b1d RC |
833 | /* Tell NIC about any 2-byte padding after MAC header */ |
834 | if (len_org) | |
835 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
836 | ||
fd4abac5 TW |
837 | /* Physical address of this Tx command's header (not MAC header!), |
838 | * within command buffer array. */ | |
499b1883 | 839 | txcmd_phys = pci_map_single(priv->pci_dev, |
df833b1d | 840 | &out_cmd->hdr, len, |
96891cee | 841 | PCI_DMA_BIDIRECTIONAL); |
c2acea8e JB |
842 | pci_unmap_addr_set(out_meta, mapping, txcmd_phys); |
843 | pci_unmap_len_set(out_meta, len, len); | |
fd4abac5 TW |
844 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
845 | * first entry */ | |
7aaa1d79 SO |
846 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
847 | txcmd_phys, len, 1, 0); | |
fd4abac5 | 848 | |
df833b1d RC |
849 | if (!ieee80211_has_morefrags(hdr->frame_control)) { |
850 | txq->need_update = 1; | |
851 | if (qc) | |
852 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
853 | } else { | |
854 | wait_write_ptr = 1; | |
855 | txq->need_update = 0; | |
856 | } | |
fd4abac5 TW |
857 | |
858 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
859 | * if any (802.11 null frames have no payload). */ | |
860 | len = skb->len - hdr_len; | |
861 | if (len) { | |
862 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
863 | len, PCI_DMA_TODEVICE); | |
7aaa1d79 SO |
864 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
865 | phys_addr, len, | |
866 | 0, 0); | |
fd4abac5 TW |
867 | } |
868 | ||
fd4abac5 | 869 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + |
df833b1d RC |
870 | offsetof(struct iwl_tx_cmd, scratch); |
871 | ||
872 | len = sizeof(struct iwl_tx_cmd) + | |
873 | sizeof(struct iwl_cmd_header) + hdr_len; | |
874 | /* take back ownership of DMA buffer to enable update */ | |
875 | pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys, | |
876 | len, PCI_DMA_BIDIRECTIONAL); | |
fd4abac5 | 877 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); |
499b1883 | 878 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); |
fd4abac5 | 879 | |
d2ee9cd2 RC |
880 | IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n", |
881 | le16_to_cpu(out_cmd->hdr.sequence)); | |
882 | IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags)); | |
3d816c77 RC |
883 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); |
884 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
fd4abac5 TW |
885 | |
886 | /* Set up entry for this TFD in Tx byte-count array */ | |
7b80ece4 RC |
887 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
888 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, | |
df833b1d RC |
889 | le16_to_cpu(tx_cmd->len)); |
890 | ||
891 | pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys, | |
892 | len, PCI_DMA_BIDIRECTIONAL); | |
fd4abac5 TW |
893 | |
894 | /* Tell device the write index *just past* this latest filled TFD */ | |
895 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
896 | ret = iwl_txq_update_write_ptr(priv, txq); | |
897 | spin_unlock_irqrestore(&priv->lock, flags); | |
898 | ||
899 | if (ret) | |
900 | return ret; | |
901 | ||
143b09ef | 902 | if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) { |
fd4abac5 TW |
903 | if (wait_write_ptr) { |
904 | spin_lock_irqsave(&priv->lock, flags); | |
905 | txq->need_update = 1; | |
906 | iwl_txq_update_write_ptr(priv, txq); | |
907 | spin_unlock_irqrestore(&priv->lock, flags); | |
143b09ef | 908 | } else { |
e4e72fb4 | 909 | iwl_stop_queue(priv, txq->swq_id); |
fd4abac5 | 910 | } |
fd4abac5 TW |
911 | } |
912 | ||
913 | return 0; | |
914 | ||
915 | drop_unlock: | |
916 | spin_unlock_irqrestore(&priv->lock, flags); | |
fd4abac5 TW |
917 | return -1; |
918 | } | |
919 | EXPORT_SYMBOL(iwl_tx_skb); | |
920 | ||
921 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
922 | ||
923 | /** | |
924 | * iwl_enqueue_hcmd - enqueue a uCode command | |
925 | * @priv: device private data point | |
926 | * @cmd: a point to the ucode command structure | |
927 | * | |
928 | * The function returns < 0 values to indicate the operation is | |
929 | * failed. On success, it turns the index (> 0) of command in the | |
930 | * command queue. | |
931 | */ | |
932 | int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
933 | { | |
934 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; | |
935 | struct iwl_queue *q = &txq->q; | |
c2acea8e JB |
936 | struct iwl_device_cmd *out_cmd; |
937 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 938 | dma_addr_t phys_addr; |
fd4abac5 | 939 | unsigned long flags; |
f3674227 TW |
940 | int len, ret; |
941 | u32 idx; | |
942 | u16 fix_size; | |
fd4abac5 TW |
943 | |
944 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); | |
945 | fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
946 | ||
947 | /* If any of the command structures end up being larger than | |
948 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
949 | * we will need to increase the size of the TFD entries */ | |
950 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
c2acea8e | 951 | !(cmd->flags & CMD_SIZE_HUGE)); |
fd4abac5 TW |
952 | |
953 | if (iwl_is_rfkill(priv)) { | |
4c423a2b | 954 | IWL_DEBUG_INFO(priv, "Not sending command - RF KILL\n"); |
fd4abac5 TW |
955 | return -EIO; |
956 | } | |
957 | ||
c2acea8e | 958 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
15b1687c | 959 | IWL_ERR(priv, "No space for Tx\n"); |
fd4abac5 TW |
960 | return -ENOSPC; |
961 | } | |
962 | ||
963 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
964 | ||
c2acea8e | 965 | idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE); |
da99c4b6 | 966 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
967 | out_meta = &txq->meta[idx]; |
968 | ||
8ce73f3a | 969 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
970 | out_meta->flags = cmd->flags; |
971 | if (cmd->flags & CMD_WANT_SKB) | |
972 | out_meta->source = cmd; | |
973 | if (cmd->flags & CMD_ASYNC) | |
974 | out_meta->callback = cmd->callback; | |
fd4abac5 TW |
975 | |
976 | out_cmd->hdr.cmd = cmd->id; | |
fd4abac5 TW |
977 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); |
978 | ||
979 | /* At this point, the out_cmd now has all of the incoming cmd | |
980 | * information */ | |
981 | ||
982 | out_cmd->hdr.flags = 0; | |
983 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
984 | INDEX_TO_SEQ(q->write_ptr)); | |
c2acea8e | 985 | if (cmd->flags & CMD_SIZE_HUGE) |
9734cb23 | 986 | out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; |
c2acea8e | 987 | len = sizeof(struct iwl_device_cmd); |
df833b1d | 988 | len += (idx == TFD_CMD_SLOTS) ? IWL_MAX_SCAN_SIZE : 0; |
499b1883 | 989 | |
fd4abac5 | 990 | |
ded2ae7c EK |
991 | #ifdef CONFIG_IWLWIFI_DEBUG |
992 | switch (out_cmd->hdr.cmd) { | |
993 | case REPLY_TX_LINK_QUALITY_CMD: | |
994 | case SENSITIVITY_CMD: | |
e1623446 | 995 | IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
996 | "%d bytes at %d[%d]:%d\n", |
997 | get_cmd_string(out_cmd->hdr.cmd), | |
998 | out_cmd->hdr.cmd, | |
999 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
1000 | q->write_ptr, idx, IWL_CMD_QUEUE_NUM); | |
1001 | break; | |
1002 | default: | |
e1623446 | 1003 | IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
1004 | "%d bytes at %d[%d]:%d\n", |
1005 | get_cmd_string(out_cmd->hdr.cmd), | |
1006 | out_cmd->hdr.cmd, | |
1007 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
1008 | q->write_ptr, idx, IWL_CMD_QUEUE_NUM); | |
1009 | } | |
1010 | #endif | |
fd4abac5 TW |
1011 | txq->need_update = 1; |
1012 | ||
518099a8 SO |
1013 | if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl) |
1014 | /* Set up entry in queue's byte count circular buffer */ | |
1015 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); | |
fd4abac5 | 1016 | |
df833b1d RC |
1017 | phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr, |
1018 | fix_size, PCI_DMA_BIDIRECTIONAL); | |
c2acea8e JB |
1019 | pci_unmap_addr_set(out_meta, mapping, phys_addr); |
1020 | pci_unmap_len_set(out_meta, len, fix_size); | |
df833b1d RC |
1021 | |
1022 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, | |
1023 | phys_addr, fix_size, 1, | |
1024 | U32_PAD(cmd->len)); | |
1025 | ||
fd4abac5 TW |
1026 | /* Increment and update queue's write index */ |
1027 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1028 | ret = iwl_txq_update_write_ptr(priv, txq); | |
1029 | ||
1030 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
1031 | return ret ? ret : idx; | |
1032 | } | |
1033 | ||
17b88929 TW |
1034 | int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) |
1035 | { | |
1036 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1037 | struct iwl_queue *q = &txq->q; | |
1038 | struct iwl_tx_info *tx_info; | |
1039 | int nfreed = 0; | |
1040 | ||
1041 | if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { | |
15b1687c | 1042 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
17b88929 TW |
1043 | "is out of range [0-%d] %d %d.\n", txq_id, |
1044 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
1045 | return 0; | |
1046 | } | |
1047 | ||
499b1883 TW |
1048 | for (index = iwl_queue_inc_wrap(index, q->n_bd); |
1049 | q->read_ptr != index; | |
1050 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 TW |
1051 | |
1052 | tx_info = &txq->txb[txq->q.read_ptr]; | |
1053 | ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]); | |
1054 | tx_info->skb[0] = NULL; | |
17b88929 | 1055 | |
972cf447 TW |
1056 | if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl) |
1057 | priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq); | |
1058 | ||
7aaa1d79 | 1059 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); |
17b88929 TW |
1060 | nfreed++; |
1061 | } | |
1062 | return nfreed; | |
1063 | } | |
1064 | EXPORT_SYMBOL(iwl_tx_queue_reclaim); | |
1065 | ||
1066 | ||
1067 | /** | |
1068 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
1069 | * | |
1070 | * When FW advances 'R' index, all entries between old and new 'R' index | |
1071 | * need to be reclaimed. As result, some free space forms. If there is | |
1072 | * enough free space (> low mark), wake the stack that feeds us. | |
1073 | */ | |
499b1883 TW |
1074 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, |
1075 | int idx, int cmd_idx) | |
17b88929 TW |
1076 | { |
1077 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1078 | struct iwl_queue *q = &txq->q; | |
1079 | int nfreed = 0; | |
1080 | ||
499b1883 | 1081 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
15b1687c | 1082 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
17b88929 | 1083 | "is out of range [0-%d] %d %d.\n", txq_id, |
499b1883 | 1084 | idx, q->n_bd, q->write_ptr, q->read_ptr); |
17b88929 TW |
1085 | return; |
1086 | } | |
1087 | ||
499b1883 | 1088 | pci_unmap_single(priv->pci_dev, |
c2acea8e JB |
1089 | pci_unmap_addr(&txq->meta[cmd_idx], mapping), |
1090 | pci_unmap_len(&txq->meta[cmd_idx], len), | |
96891cee | 1091 | PCI_DMA_BIDIRECTIONAL); |
499b1883 TW |
1092 | |
1093 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; | |
1094 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 1095 | |
499b1883 | 1096 | if (nfreed++ > 0) { |
15b1687c | 1097 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 TW |
1098 | q->write_ptr, q->read_ptr); |
1099 | queue_work(priv->workqueue, &priv->restart); | |
1100 | } | |
da99c4b6 | 1101 | |
17b88929 TW |
1102 | } |
1103 | } | |
1104 | ||
1105 | /** | |
1106 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
1107 | * @rxb: Rx buffer to reclaim | |
1108 | * | |
1109 | * If an Rx buffer has an async callback associated with it the callback | |
1110 | * will be executed. The attached skb (if present) will only be freed | |
1111 | * if the callback returns 1 | |
1112 | */ | |
1113 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
1114 | { | |
1115 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1116 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | |
1117 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1118 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1119 | int cmd_index; |
9734cb23 | 1120 | bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); |
c2acea8e JB |
1121 | struct iwl_device_cmd *cmd; |
1122 | struct iwl_cmd_meta *meta; | |
17b88929 TW |
1123 | |
1124 | /* If a Tx command is being handled and it isn't in the actual | |
1125 | * command queue then there a command routing bug has been introduced | |
1126 | * in the queue management code. */ | |
55d6a3cd | 1127 | if (WARN(txq_id != IWL_CMD_QUEUE_NUM, |
01ef9323 WT |
1128 | "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n", |
1129 | txq_id, sequence, | |
1130 | priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr, | |
1131 | priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) { | |
ec741164 | 1132 | iwl_print_hex_error(priv, pkt, 32); |
55d6a3cd | 1133 | return; |
01ef9323 | 1134 | } |
17b88929 TW |
1135 | |
1136 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); | |
da99c4b6 | 1137 | cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; |
c2acea8e | 1138 | meta = &priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_index]; |
17b88929 TW |
1139 | |
1140 | /* Input error checking is done when commands are added to queue. */ | |
c2acea8e JB |
1141 | if (meta->flags & CMD_WANT_SKB) { |
1142 | meta->source->reply_skb = rxb->skb; | |
17b88929 | 1143 | rxb->skb = NULL; |
5696aea6 JB |
1144 | } else if (meta->callback) |
1145 | meta->callback(priv, cmd, rxb->skb); | |
17b88929 | 1146 | |
499b1883 | 1147 | iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index); |
17b88929 | 1148 | |
c2acea8e | 1149 | if (!(meta->flags & CMD_ASYNC)) { |
17b88929 TW |
1150 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); |
1151 | wake_up_interruptible(&priv->wait_command_queue); | |
1152 | } | |
1153 | } | |
1154 | EXPORT_SYMBOL(iwl_tx_cmd_complete); | |
1155 | ||
30e553e3 TW |
1156 | /* |
1157 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
1158 | * Called only when finding queue for aggregation. | |
1159 | * Should never return anything < 7, because they should already | |
1160 | * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6). | |
1161 | */ | |
1162 | static int iwl_txq_ctx_activate_free(struct iwl_priv *priv) | |
1163 | { | |
1164 | int txq_id; | |
1165 | ||
1166 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
1167 | if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk)) | |
1168 | return txq_id; | |
1169 | return -1; | |
1170 | } | |
1171 | ||
1172 | int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn) | |
1173 | { | |
1174 | int sta_id; | |
1175 | int tx_fifo; | |
1176 | int txq_id; | |
1177 | int ret; | |
1178 | unsigned long flags; | |
1179 | struct iwl_tid_data *tid_data; | |
30e553e3 TW |
1180 | |
1181 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) | |
1182 | tx_fifo = default_tid_to_tx_fifo[tid]; | |
1183 | else | |
1184 | return -EINVAL; | |
1185 | ||
39aadf8c | 1186 | IWL_WARN(priv, "%s on ra = %pM tid = %d\n", |
e174961c | 1187 | __func__, ra, tid); |
30e553e3 TW |
1188 | |
1189 | sta_id = iwl_find_station(priv, ra); | |
3eb92969 WYG |
1190 | if (sta_id == IWL_INVALID_STATION) { |
1191 | IWL_ERR(priv, "Start AGG on invalid station\n"); | |
30e553e3 | 1192 | return -ENXIO; |
3eb92969 | 1193 | } |
082e708a RK |
1194 | if (unlikely(tid >= MAX_TID_COUNT)) |
1195 | return -EINVAL; | |
30e553e3 TW |
1196 | |
1197 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) { | |
15b1687c | 1198 | IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n"); |
30e553e3 TW |
1199 | return -ENXIO; |
1200 | } | |
1201 | ||
1202 | txq_id = iwl_txq_ctx_activate_free(priv); | |
3eb92969 WYG |
1203 | if (txq_id == -1) { |
1204 | IWL_ERR(priv, "No free aggregation queue available\n"); | |
30e553e3 | 1205 | return -ENXIO; |
3eb92969 | 1206 | } |
30e553e3 TW |
1207 | |
1208 | spin_lock_irqsave(&priv->sta_lock, flags); | |
1209 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1210 | *ssn = SEQ_TO_SN(tid_data->seq_number); | |
1211 | tid_data->agg.txq_id = txq_id; | |
45af8195 | 1212 | priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(tx_fifo, txq_id); |
30e553e3 TW |
1213 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
1214 | ||
1215 | ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo, | |
1216 | sta_id, tid, *ssn); | |
1217 | if (ret) | |
1218 | return ret; | |
1219 | ||
1220 | if (tid_data->tfds_in_queue == 0) { | |
3eb92969 | 1221 | IWL_DEBUG_HT(priv, "HW queue is empty\n"); |
30e553e3 TW |
1222 | tid_data->agg.state = IWL_AGG_ON; |
1223 | ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid); | |
1224 | } else { | |
e1623446 | 1225 | IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n", |
30e553e3 TW |
1226 | tid_data->tfds_in_queue); |
1227 | tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA; | |
1228 | } | |
1229 | return ret; | |
1230 | } | |
1231 | EXPORT_SYMBOL(iwl_tx_agg_start); | |
1232 | ||
1233 | int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid) | |
1234 | { | |
1235 | int tx_fifo_id, txq_id, sta_id, ssn = -1; | |
1236 | struct iwl_tid_data *tid_data; | |
1237 | int ret, write_ptr, read_ptr; | |
1238 | unsigned long flags; | |
30e553e3 TW |
1239 | |
1240 | if (!ra) { | |
15b1687c | 1241 | IWL_ERR(priv, "ra = NULL\n"); |
30e553e3 TW |
1242 | return -EINVAL; |
1243 | } | |
1244 | ||
e6a6cf4c RC |
1245 | if (unlikely(tid >= MAX_TID_COUNT)) |
1246 | return -EINVAL; | |
1247 | ||
30e553e3 TW |
1248 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) |
1249 | tx_fifo_id = default_tid_to_tx_fifo[tid]; | |
1250 | else | |
1251 | return -EINVAL; | |
1252 | ||
1253 | sta_id = iwl_find_station(priv, ra); | |
1254 | ||
a2f1cbeb WYG |
1255 | if (sta_id == IWL_INVALID_STATION) { |
1256 | IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid); | |
30e553e3 | 1257 | return -ENXIO; |
a2f1cbeb | 1258 | } |
30e553e3 TW |
1259 | |
1260 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON) | |
39aadf8c | 1261 | IWL_WARN(priv, "Stopping AGG while state not IWL_AGG_ON\n"); |
30e553e3 TW |
1262 | |
1263 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1264 | ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; | |
1265 | txq_id = tid_data->agg.txq_id; | |
1266 | write_ptr = priv->txq[txq_id].q.write_ptr; | |
1267 | read_ptr = priv->txq[txq_id].q.read_ptr; | |
1268 | ||
1269 | /* The queue is not empty */ | |
1270 | if (write_ptr != read_ptr) { | |
e1623446 | 1271 | IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n"); |
30e553e3 TW |
1272 | priv->stations[sta_id].tid[tid].agg.state = |
1273 | IWL_EMPTYING_HW_QUEUE_DELBA; | |
1274 | return 0; | |
1275 | } | |
1276 | ||
e1623446 | 1277 | IWL_DEBUG_HT(priv, "HW queue is empty\n"); |
30e553e3 TW |
1278 | priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF; |
1279 | ||
1280 | spin_lock_irqsave(&priv->lock, flags); | |
1281 | ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn, | |
1282 | tx_fifo_id); | |
1283 | spin_unlock_irqrestore(&priv->lock, flags); | |
1284 | ||
1285 | if (ret) | |
1286 | return ret; | |
1287 | ||
1288 | ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid); | |
1289 | ||
1290 | return 0; | |
1291 | } | |
1292 | EXPORT_SYMBOL(iwl_tx_agg_stop); | |
1293 | ||
1294 | int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id) | |
1295 | { | |
1296 | struct iwl_queue *q = &priv->txq[txq_id].q; | |
1297 | u8 *addr = priv->stations[sta_id].sta.sta.addr; | |
1298 | struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid]; | |
1299 | ||
1300 | switch (priv->stations[sta_id].tid[tid].agg.state) { | |
1301 | case IWL_EMPTYING_HW_QUEUE_DELBA: | |
1302 | /* We are reclaiming the last packet of the */ | |
1303 | /* aggregated HW queue */ | |
3fd07a1e TW |
1304 | if ((txq_id == tid_data->agg.txq_id) && |
1305 | (q->read_ptr == q->write_ptr)) { | |
30e553e3 TW |
1306 | u16 ssn = SEQ_TO_SN(tid_data->seq_number); |
1307 | int tx_fifo = default_tid_to_tx_fifo[tid]; | |
e1623446 | 1308 | IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n"); |
30e553e3 TW |
1309 | priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, |
1310 | ssn, tx_fifo); | |
1311 | tid_data->agg.state = IWL_AGG_OFF; | |
1312 | ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid); | |
1313 | } | |
1314 | break; | |
1315 | case IWL_EMPTYING_HW_QUEUE_ADDBA: | |
1316 | /* We are reclaiming the last packet of the queue */ | |
1317 | if (tid_data->tfds_in_queue == 0) { | |
e1623446 | 1318 | IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n"); |
30e553e3 TW |
1319 | tid_data->agg.state = IWL_AGG_ON; |
1320 | ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid); | |
1321 | } | |
1322 | break; | |
1323 | } | |
1324 | return 0; | |
1325 | } | |
1326 | EXPORT_SYMBOL(iwl_txq_check_empty); | |
30e553e3 | 1327 | |
653fa4a0 EG |
1328 | /** |
1329 | * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack | |
1330 | * | |
1331 | * Go through block-ack's bitmap of ACK'd frames, update driver's record of | |
1332 | * ACK vs. not. This gets sent to mac80211, then to rate scaling algo. | |
1333 | */ | |
1334 | static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv, | |
1335 | struct iwl_ht_agg *agg, | |
1336 | struct iwl_compressed_ba_resp *ba_resp) | |
1337 | ||
1338 | { | |
1339 | int i, sh, ack; | |
1340 | u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl); | |
1341 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
1342 | u64 bitmap; | |
1343 | int successes = 0; | |
1344 | struct ieee80211_tx_info *info; | |
1345 | ||
1346 | if (unlikely(!agg->wait_for_ba)) { | |
15b1687c | 1347 | IWL_ERR(priv, "Received BA when not expected\n"); |
653fa4a0 EG |
1348 | return -EINVAL; |
1349 | } | |
1350 | ||
1351 | /* Mark that the expected block-ack response arrived */ | |
1352 | agg->wait_for_ba = 0; | |
e1623446 | 1353 | IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl); |
653fa4a0 EG |
1354 | |
1355 | /* Calculate shift to align block-ack bits with our Tx window bits */ | |
3fd07a1e | 1356 | sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4); |
653fa4a0 EG |
1357 | if (sh < 0) /* tbw something is wrong with indices */ |
1358 | sh += 0x100; | |
1359 | ||
1360 | /* don't use 64-bit values for now */ | |
1361 | bitmap = le64_to_cpu(ba_resp->bitmap) >> sh; | |
1362 | ||
1363 | if (agg->frame_count > (64 - sh)) { | |
e1623446 | 1364 | IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size"); |
653fa4a0 EG |
1365 | return -1; |
1366 | } | |
1367 | ||
1368 | /* check for success or failure according to the | |
1369 | * transmitted bitmap and block-ack bitmap */ | |
1370 | bitmap &= agg->bitmap; | |
1371 | ||
1372 | /* For each frame attempted in aggregation, | |
1373 | * update driver's record of tx frame's status. */ | |
1374 | for (i = 0; i < agg->frame_count ; i++) { | |
4aa41f12 | 1375 | ack = bitmap & (1ULL << i); |
653fa4a0 | 1376 | successes += !!ack; |
e1623446 | 1377 | IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n", |
c3056065 | 1378 | ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff, |
653fa4a0 EG |
1379 | agg->start_idx + i); |
1380 | } | |
1381 | ||
1382 | info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]); | |
1383 | memset(&info->status, 0, sizeof(info->status)); | |
1384 | info->flags = IEEE80211_TX_STAT_ACK; | |
1385 | info->flags |= IEEE80211_TX_STAT_AMPDU; | |
1386 | info->status.ampdu_ack_map = successes; | |
1387 | info->status.ampdu_ack_len = agg->frame_count; | |
1388 | iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info); | |
1389 | ||
e1623446 | 1390 | IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap); |
653fa4a0 EG |
1391 | |
1392 | return 0; | |
1393 | } | |
1394 | ||
1395 | /** | |
1396 | * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA | |
1397 | * | |
1398 | * Handles block-acknowledge notification from device, which reports success | |
1399 | * of frames sent via aggregation. | |
1400 | */ | |
1401 | void iwl_rx_reply_compressed_ba(struct iwl_priv *priv, | |
1402 | struct iwl_rx_mem_buffer *rxb) | |
1403 | { | |
1404 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1405 | struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba; | |
653fa4a0 EG |
1406 | struct iwl_tx_queue *txq = NULL; |
1407 | struct iwl_ht_agg *agg; | |
3fd07a1e TW |
1408 | int index; |
1409 | int sta_id; | |
1410 | int tid; | |
653fa4a0 EG |
1411 | |
1412 | /* "flow" corresponds to Tx queue */ | |
1413 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
1414 | ||
1415 | /* "ssn" is start of block-ack Tx window, corresponds to index | |
1416 | * (in Tx queue's circular buffer) of first TFD/frame in window */ | |
1417 | u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); | |
1418 | ||
1419 | if (scd_flow >= priv->hw_params.max_txq_num) { | |
15b1687c WT |
1420 | IWL_ERR(priv, |
1421 | "BUG_ON scd_flow is bigger than number of queues\n"); | |
653fa4a0 EG |
1422 | return; |
1423 | } | |
1424 | ||
1425 | txq = &priv->txq[scd_flow]; | |
3fd07a1e TW |
1426 | sta_id = ba_resp->sta_id; |
1427 | tid = ba_resp->tid; | |
1428 | agg = &priv->stations[sta_id].tid[tid].agg; | |
653fa4a0 EG |
1429 | |
1430 | /* Find index just before block-ack window */ | |
1431 | index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd); | |
1432 | ||
1433 | /* TODO: Need to get this copy more safely - now good for debug */ | |
1434 | ||
e1623446 | 1435 | IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, " |
653fa4a0 EG |
1436 | "sta_id = %d\n", |
1437 | agg->wait_for_ba, | |
e174961c | 1438 | (u8 *) &ba_resp->sta_addr_lo32, |
653fa4a0 | 1439 | ba_resp->sta_id); |
e1623446 | 1440 | IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = " |
653fa4a0 EG |
1441 | "%d, scd_ssn = %d\n", |
1442 | ba_resp->tid, | |
1443 | ba_resp->seq_ctl, | |
1444 | (unsigned long long)le64_to_cpu(ba_resp->bitmap), | |
1445 | ba_resp->scd_flow, | |
1446 | ba_resp->scd_ssn); | |
e1623446 | 1447 | IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n", |
653fa4a0 EG |
1448 | agg->start_idx, |
1449 | (unsigned long long)agg->bitmap); | |
1450 | ||
1451 | /* Update driver's record of ACK vs. not for each frame in window */ | |
1452 | iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp); | |
1453 | ||
1454 | /* Release all TFDs before the SSN, i.e. all TFDs in front of | |
1455 | * block-ack window (we assume that they've been successfully | |
1456 | * transmitted ... if not, it's too late anyway). */ | |
1457 | if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) { | |
1458 | /* calculate mac80211 ampdu sw queue to wake */ | |
653fa4a0 | 1459 | int freed = iwl_tx_queue_reclaim(priv, scd_flow, index); |
3fd07a1e TW |
1460 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
1461 | ||
1462 | if ((iwl_queue_space(&txq->q) > txq->q.low_mark) && | |
1463 | priv->mac80211_registered && | |
1464 | (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) | |
e4e72fb4 | 1465 | iwl_wake_queue(priv, txq->swq_id); |
3fd07a1e TW |
1466 | |
1467 | iwl_txq_check_empty(priv, sta_id, tid, scd_flow); | |
653fa4a0 EG |
1468 | } |
1469 | } | |
1470 | EXPORT_SYMBOL(iwl_rx_reply_compressed_ba); | |
1471 | ||
994d31f7 | 1472 | #ifdef CONFIG_IWLWIFI_DEBUG |
a332f8d6 TW |
1473 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x |
1474 | ||
1475 | const char *iwl_get_tx_fail_reason(u32 status) | |
1476 | { | |
1477 | switch (status & TX_STATUS_MSK) { | |
1478 | case TX_STATUS_SUCCESS: | |
1479 | return "SUCCESS"; | |
1480 | TX_STATUS_ENTRY(SHORT_LIMIT); | |
1481 | TX_STATUS_ENTRY(LONG_LIMIT); | |
1482 | TX_STATUS_ENTRY(FIFO_UNDERRUN); | |
1483 | TX_STATUS_ENTRY(MGMNT_ABORT); | |
1484 | TX_STATUS_ENTRY(NEXT_FRAG); | |
1485 | TX_STATUS_ENTRY(LIFE_EXPIRE); | |
1486 | TX_STATUS_ENTRY(DEST_PS); | |
1487 | TX_STATUS_ENTRY(ABORTED); | |
1488 | TX_STATUS_ENTRY(BT_RETRY); | |
1489 | TX_STATUS_ENTRY(STA_INVALID); | |
1490 | TX_STATUS_ENTRY(FRAG_DROPPED); | |
1491 | TX_STATUS_ENTRY(TID_DISABLE); | |
1492 | TX_STATUS_ENTRY(FRAME_FLUSHED); | |
1493 | TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); | |
1494 | TX_STATUS_ENTRY(TX_LOCKED); | |
1495 | TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); | |
1496 | } | |
1497 | ||
1498 | return "UNKNOWN"; | |
1499 | } | |
1500 | EXPORT_SYMBOL(iwl_get_tx_fail_reason); | |
1501 | #endif /* CONFIG_IWLWIFI_DEBUG */ |