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792bc3cb WYG |
1 | /****************************************************************************** |
2 | * | |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
4e318262 | 5 | * Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved. |
792bc3cb WYG |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #include <linux/kernel.h> | |
792bc3cb WYG |
31 | #include <linux/init.h> |
32 | ||
33 | #include "iwl-dev.h" | |
34 | #include "iwl-core.h" | |
81b8176e | 35 | #include "iwl-io.h" |
19e6cda0 | 36 | #include "iwl-agn-hw.h" |
741a6266 | 37 | #include "iwl-agn.h" |
0de76736 | 38 | #include "iwl-agn-calib.h" |
bdfbf092 | 39 | #include "iwl-trans.h" |
dda61a44 | 40 | #include "iwl-fh.h" |
d0f76d68 | 41 | #include "iwl-op-mode.h" |
741a6266 | 42 | |
f4012413 WYG |
43 | static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = { |
44 | {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP, | |
45 | 0, COEX_UNASSOC_IDLE_FLAGS}, | |
46 | {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP, | |
47 | 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS}, | |
48 | {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP, | |
49 | 0, COEX_UNASSOC_AUTO_SCAN_FLAGS}, | |
50 | {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP, | |
51 | 0, COEX_CALIBRATION_FLAGS}, | |
52 | {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP, | |
53 | 0, COEX_PERIODIC_CALIBRATION_FLAGS}, | |
54 | {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP, | |
55 | 0, COEX_CONNECTION_ESTAB_FLAGS}, | |
56 | {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP, | |
57 | 0, COEX_ASSOCIATED_IDLE_FLAGS}, | |
58 | {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP, | |
59 | 0, COEX_ASSOC_MANUAL_SCAN_FLAGS}, | |
60 | {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP, | |
61 | 0, COEX_ASSOC_AUTO_SCAN_FLAGS}, | |
62 | {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP, | |
63 | 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS}, | |
64 | {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS}, | |
65 | {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS}, | |
66 | {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP, | |
67 | 0, COEX_STAND_ALONE_DEBUG_FLAGS}, | |
68 | {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP, | |
69 | 0, COEX_IPAN_ASSOC_LEVEL_FLAGS}, | |
70 | {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS}, | |
71 | {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS} | |
72 | }; | |
73 | ||
de7f5f92 DF |
74 | /****************************************************************************** |
75 | * | |
76 | * uCode download functions | |
77 | * | |
78 | ******************************************************************************/ | |
79 | ||
0692fe41 JB |
80 | static inline const struct fw_img * |
81 | iwl_get_ucode_image(struct iwl_priv *priv, enum iwl_ucode_type ucode_type) | |
8929c24b | 82 | { |
6dfa8d01 DS |
83 | if (ucode_type >= IWL_UCODE_TYPE_MAX) |
84 | return NULL; | |
85 | ||
86 | return &priv->fw->img[ucode_type]; | |
8929c24b DF |
87 | } |
88 | ||
741a6266 WYG |
89 | /* |
90 | * Calibration | |
91 | */ | |
e1991885 | 92 | static int iwl_set_Xtal_calib(struct iwl_priv *priv) |
741a6266 WYG |
93 | { |
94 | struct iwl_calib_xtal_freq_cmd cmd; | |
95 | __le16 *xtal_calib = | |
e1991885 | 96 | (__le16 *)iwl_eeprom_query_addr(priv->shrd, EEPROM_XTAL); |
741a6266 | 97 | |
1f8bf039 | 98 | iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD); |
741a6266 WYG |
99 | cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]); |
100 | cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]); | |
e1991885 | 101 | return iwl_calib_set(priv, (void *)&cmd, sizeof(cmd)); |
741a6266 WYG |
102 | } |
103 | ||
e1991885 | 104 | static int iwl_set_temperature_offset_calib(struct iwl_priv *priv) |
bf53f939 SZ |
105 | { |
106 | struct iwl_calib_temperature_offset_cmd cmd; | |
107 | __le16 *offset_calib = | |
e1991885 | 108 | (__le16 *)iwl_eeprom_query_addr(priv->shrd, |
ab36eab2 | 109 | EEPROM_RAW_TEMPERATURE); |
1f8bf039 WYG |
110 | |
111 | memset(&cmd, 0, sizeof(cmd)); | |
112 | iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD); | |
456fc37e | 113 | memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(*offset_calib)); |
bf53f939 SZ |
114 | if (!(cmd.radio_sensor_offset)) |
115 | cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET; | |
1f8bf039 | 116 | |
e1991885 | 117 | IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n", |
2e277996 | 118 | le16_to_cpu(cmd.radio_sensor_offset)); |
e1991885 | 119 | return iwl_calib_set(priv, (void *)&cmd, sizeof(cmd)); |
bf53f939 SZ |
120 | } |
121 | ||
e1991885 | 122 | static int iwl_set_temperature_offset_calib_v2(struct iwl_priv *priv) |
c6f30347 WYG |
123 | { |
124 | struct iwl_calib_temperature_offset_v2_cmd cmd; | |
e1991885 | 125 | __le16 *offset_calib_high = (__le16 *)iwl_eeprom_query_addr(priv->shrd, |
c6f30347 WYG |
126 | EEPROM_KELVIN_TEMPERATURE); |
127 | __le16 *offset_calib_low = | |
e1991885 | 128 | (__le16 *)iwl_eeprom_query_addr(priv->shrd, |
ab36eab2 | 129 | EEPROM_RAW_TEMPERATURE); |
7d8f2d50 | 130 | struct iwl_eeprom_calib_hdr *hdr; |
c6f30347 WYG |
131 | |
132 | memset(&cmd, 0, sizeof(cmd)); | |
133 | iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD); | |
e1991885 | 134 | hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv->shrd, |
7d8f2d50 | 135 | EEPROM_CALIB_ALL); |
c6f30347 | 136 | memcpy(&cmd.radio_sensor_offset_high, offset_calib_high, |
00085006 | 137 | sizeof(*offset_calib_high)); |
c6f30347 | 138 | memcpy(&cmd.radio_sensor_offset_low, offset_calib_low, |
00085006 | 139 | sizeof(*offset_calib_low)); |
c6f30347 | 140 | if (!(cmd.radio_sensor_offset_low)) { |
e1991885 | 141 | IWL_DEBUG_CALIB(priv, "no info in EEPROM, use default\n"); |
c6f30347 WYG |
142 | cmd.radio_sensor_offset_low = DEFAULT_RADIO_SENSOR_OFFSET; |
143 | cmd.radio_sensor_offset_high = DEFAULT_RADIO_SENSOR_OFFSET; | |
144 | } | |
7d8f2d50 WYG |
145 | memcpy(&cmd.burntVoltageRef, &hdr->voltage, |
146 | sizeof(hdr->voltage)); | |
c6f30347 | 147 | |
e1991885 | 148 | IWL_DEBUG_CALIB(priv, "Radio sensor offset high: %d\n", |
c6f30347 | 149 | le16_to_cpu(cmd.radio_sensor_offset_high)); |
e1991885 | 150 | IWL_DEBUG_CALIB(priv, "Radio sensor offset low: %d\n", |
c6f30347 | 151 | le16_to_cpu(cmd.radio_sensor_offset_low)); |
e1991885 | 152 | IWL_DEBUG_CALIB(priv, "Voltage Ref: %d\n", |
c6f30347 WYG |
153 | le16_to_cpu(cmd.burntVoltageRef)); |
154 | ||
e1991885 | 155 | return iwl_calib_set(priv, (void *)&cmd, sizeof(cmd)); |
c6f30347 WYG |
156 | } |
157 | ||
e1991885 | 158 | static int iwl_send_calib_cfg(struct iwl_priv *priv) |
741a6266 WYG |
159 | { |
160 | struct iwl_calib_cfg_cmd calib_cfg_cmd; | |
161 | struct iwl_host_cmd cmd = { | |
162 | .id = CALIBRATION_CFG_CMD, | |
3fa50738 JB |
163 | .len = { sizeof(struct iwl_calib_cfg_cmd), }, |
164 | .data = { &calib_cfg_cmd, }, | |
741a6266 WYG |
165 | }; |
166 | ||
167 | memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); | |
168 | calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; | |
169 | calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; | |
170 | calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; | |
df2a4dc8 WYG |
171 | calib_cfg_cmd.ucd_calib_cfg.flags = |
172 | IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK; | |
741a6266 | 173 | |
e10a0533 | 174 | return iwl_dvm_send_cmd(priv, &cmd); |
741a6266 WYG |
175 | } |
176 | ||
247c61d6 | 177 | int iwlagn_rx_calib_result(struct iwl_priv *priv, |
48a2d66f | 178 | struct iwl_rx_cmd_buffer *rxb, |
247c61d6 | 179 | struct iwl_device_cmd *cmd) |
741a6266 WYG |
180 | { |
181 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
f8d7c1a1 | 182 | struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->data; |
741a6266 | 183 | int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; |
741a6266 WYG |
184 | |
185 | /* reduce the size of the length field itself */ | |
186 | len -= 4; | |
187 | ||
e1991885 | 188 | if (iwl_calib_set(priv, hdr, len)) |
f02c2fd3 JB |
189 | IWL_ERR(priv, "Failed to record calibration data %d\n", |
190 | hdr->op_code); | |
191 | ||
247c61d6 | 192 | return 0; |
741a6266 WYG |
193 | } |
194 | ||
e1991885 | 195 | int iwl_init_alive_start(struct iwl_priv *priv) |
741a6266 | 196 | { |
ca7966c8 | 197 | int ret; |
741a6266 | 198 | |
e1991885 JB |
199 | if (cfg(priv)->bt_params && |
200 | cfg(priv)->bt_params->advanced_bt_coexist) { | |
f7322f8f WYG |
201 | /* |
202 | * Tell uCode we are ready to perform calibration | |
203 | * need to perform this before any calibration | |
204 | * no need to close the envlope since we are going | |
205 | * to load the runtime uCode later. | |
206 | */ | |
e1991885 | 207 | ret = iwl_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN, |
f7322f8f | 208 | BT_COEX_PRIO_TBL_EVT_INIT_CALIB2); |
ca7966c8 JB |
209 | if (ret) |
210 | return ret; | |
f7322f8f WYG |
211 | |
212 | } | |
ca7966c8 | 213 | |
e1991885 | 214 | ret = iwl_send_calib_cfg(priv); |
ca7966c8 JB |
215 | if (ret) |
216 | return ret; | |
bf53f939 SZ |
217 | |
218 | /** | |
219 | * temperature offset calibration is only needed for runtime ucode, | |
220 | * so prepare the value now. | |
221 | */ | |
e1991885 JB |
222 | if (cfg(priv)->need_temp_offset_calib) { |
223 | if (cfg(priv)->temp_offset_v2) | |
224 | return iwl_set_temperature_offset_calib_v2(priv); | |
c6f30347 | 225 | else |
e1991885 | 226 | return iwl_set_temperature_offset_calib(priv); |
c6f30347 | 227 | } |
741a6266 | 228 | |
ca7966c8 | 229 | return 0; |
741a6266 WYG |
230 | } |
231 | ||
e1991885 | 232 | static int iwl_send_wimax_coex(struct iwl_priv *priv) |
f4012413 WYG |
233 | { |
234 | struct iwl_wimax_coex_cmd coex_cmd; | |
235 | ||
e1991885 | 236 | if (cfg(priv)->base_params->support_wimax_coexist) { |
f4012413 WYG |
237 | /* UnMask wake up src at associated sleep */ |
238 | coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK; | |
239 | ||
240 | /* UnMask wake up src at unassociated sleep */ | |
241 | coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK; | |
242 | memcpy(coex_cmd.sta_prio, cu_priorities, | |
243 | sizeof(struct iwl_wimax_coex_event_entry) * | |
244 | COEX_NUM_OF_EVENTS); | |
245 | ||
246 | /* enabling the coexistence feature */ | |
247 | coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK; | |
248 | ||
249 | /* enabling the priorities tables */ | |
250 | coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK; | |
251 | } else { | |
252 | /* coexistence is disabled */ | |
253 | memset(&coex_cmd, 0, sizeof(coex_cmd)); | |
254 | } | |
e10a0533 | 255 | return iwl_dvm_send_cmd_pdu(priv, |
e419d62d | 256 | COEX_PRIORITY_TABLE_CMD, CMD_SYNC, |
f4012413 WYG |
257 | sizeof(coex_cmd), &coex_cmd); |
258 | } | |
259 | ||
66128b14 | 260 | static const u8 iwl_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = { |
aeb4a2ee WYG |
261 | ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | |
262 | (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
263 | ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
264 | (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
265 | ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
266 | (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
267 | ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
268 | (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
269 | ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
270 | (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
271 | ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
272 | (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
273 | ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
274 | (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
275 | ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
276 | (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
277 | ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) | | |
278 | (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)), | |
279 | 0, 0, 0, 0, 0, 0, 0 | |
280 | }; | |
281 | ||
e1991885 | 282 | void iwl_send_prio_tbl(struct iwl_priv *priv) |
aeb4a2ee WYG |
283 | { |
284 | struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd; | |
285 | ||
66128b14 DF |
286 | memcpy(prio_tbl_cmd.prio_tbl, iwl_bt_prio_tbl, |
287 | sizeof(iwl_bt_prio_tbl)); | |
e10a0533 | 288 | if (iwl_dvm_send_cmd_pdu(priv, |
e419d62d | 289 | REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC, |
aeb4a2ee | 290 | sizeof(prio_tbl_cmd), &prio_tbl_cmd)) |
e1991885 | 291 | IWL_ERR(priv, "failed to send BT prio tbl command\n"); |
aeb4a2ee WYG |
292 | } |
293 | ||
e1991885 | 294 | int iwl_send_bt_env(struct iwl_priv *priv, u8 action, u8 type) |
aeb4a2ee WYG |
295 | { |
296 | struct iwl_bt_coex_prot_env_cmd env_cmd; | |
ca7966c8 | 297 | int ret; |
aeb4a2ee WYG |
298 | |
299 | env_cmd.action = action; | |
300 | env_cmd.type = type; | |
e10a0533 | 301 | ret = iwl_dvm_send_cmd_pdu(priv, |
e419d62d | 302 | REPLY_BT_COEX_PROT_ENV, CMD_SYNC, |
ca7966c8 JB |
303 | sizeof(env_cmd), &env_cmd); |
304 | if (ret) | |
e1991885 | 305 | IWL_ERR(priv, "failed to send BT env command\n"); |
ca7966c8 | 306 | return ret; |
aeb4a2ee WYG |
307 | } |
308 | ||
309 | ||
e1991885 | 310 | static int iwl_alive_notify(struct iwl_priv *priv) |
741a6266 | 311 | { |
7415952f | 312 | int ret; |
741a6266 | 313 | |
e1991885 | 314 | iwl_trans_fw_alive(trans(priv)); |
e755f882 JB |
315 | |
316 | priv->passive_no_rx = false; | |
317 | priv->transport_queue_stop = 0; | |
e7cad69c | 318 | |
e1991885 | 319 | ret = iwl_send_wimax_coex(priv); |
7415952f WYG |
320 | if (ret) |
321 | return ret; | |
322 | ||
38622419 | 323 | if (!cfg(priv)->no_xtal_calib) { |
e1991885 | 324 | ret = iwl_set_Xtal_calib(priv); |
93b64105 JB |
325 | if (ret) |
326 | return ret; | |
327 | } | |
741a6266 | 328 | |
e1991885 | 329 | return iwl_send_calib_results(priv); |
741a6266 | 330 | } |
db41dd27 WYG |
331 | |
332 | ||
333 | /** | |
334 | * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host, | |
335 | * using sample data 100 bytes apart. If these sample points are good, | |
336 | * it's a pretty good bet that everything between them is good, too. | |
337 | */ | |
6dfa8d01 | 338 | static int iwl_verify_sec_sparse(struct iwl_priv *priv, |
0692fe41 | 339 | const struct fw_desc *fw_desc) |
db41dd27 | 340 | { |
35b1d92d JB |
341 | __le32 *image = (__le32 *)fw_desc->v_addr; |
342 | u32 len = fw_desc->len; | |
db41dd27 | 343 | u32 val; |
db41dd27 WYG |
344 | u32 i; |
345 | ||
e1991885 | 346 | IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len); |
db41dd27 WYG |
347 | |
348 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
349 | /* read data comes through single port, auto-incr addr */ | |
350 | /* NOTE: Use the debugless read so we don't flood kernel log | |
351 | * if IWL_DL_IO is set */ | |
e1991885 | 352 | iwl_write_direct32(trans(priv), HBUS_TARG_MEM_RADDR, |
6dfa8d01 | 353 | i + fw_desc->offset); |
e1991885 | 354 | val = iwl_read32(trans(priv), HBUS_TARG_MEM_RDAT); |
fb66216f JB |
355 | if (val != le32_to_cpu(*image)) |
356 | return -EIO; | |
db41dd27 WYG |
357 | } |
358 | ||
fb66216f | 359 | return 0; |
db41dd27 WYG |
360 | } |
361 | ||
6dfa8d01 | 362 | static void iwl_print_mismatch_sec(struct iwl_priv *priv, |
0692fe41 | 363 | const struct fw_desc *fw_desc) |
db41dd27 | 364 | { |
35b1d92d JB |
365 | __le32 *image = (__le32 *)fw_desc->v_addr; |
366 | u32 len = fw_desc->len; | |
db41dd27 | 367 | u32 val; |
fb66216f JB |
368 | u32 offs; |
369 | int errors = 0; | |
db41dd27 | 370 | |
e1991885 | 371 | IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len); |
db41dd27 | 372 | |
e1991885 | 373 | iwl_write_direct32(trans(priv), HBUS_TARG_MEM_RADDR, |
6dfa8d01 | 374 | fw_desc->offset); |
db41dd27 | 375 | |
fb66216f JB |
376 | for (offs = 0; |
377 | offs < len && errors < 20; | |
378 | offs += sizeof(u32), image++) { | |
db41dd27 | 379 | /* read data comes through single port, auto-incr addr */ |
e1991885 | 380 | val = iwl_read32(trans(priv), HBUS_TARG_MEM_RDAT); |
db41dd27 | 381 | if (val != le32_to_cpu(*image)) { |
e1991885 | 382 | IWL_ERR(priv, "uCode INST section at " |
fb66216f JB |
383 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
384 | offs, val, le32_to_cpu(*image)); | |
385 | errors++; | |
db41dd27 WYG |
386 | } |
387 | } | |
db41dd27 WYG |
388 | } |
389 | ||
390 | /** | |
391 | * iwl_verify_ucode - determine which instruction image is in SRAM, | |
392 | * and verify its contents | |
393 | */ | |
e1991885 | 394 | static int iwl_verify_ucode(struct iwl_priv *priv, |
de7f5f92 | 395 | enum iwl_ucode_type ucode_type) |
db41dd27 | 396 | { |
0692fe41 | 397 | const struct fw_img *img = iwl_get_ucode_image(priv, ucode_type); |
baa00056 DF |
398 | |
399 | if (!img) { | |
e1991885 | 400 | IWL_ERR(priv, "Invalid ucode requested (%d)\n", ucode_type); |
baa00056 DF |
401 | return -EINVAL; |
402 | } | |
403 | ||
6dfa8d01 | 404 | if (!iwl_verify_sec_sparse(priv, &img->sec[IWL_UCODE_SECTION_INST])) { |
e1991885 | 405 | IWL_DEBUG_FW(priv, "uCode is good in inst SRAM\n"); |
db41dd27 WYG |
406 | return 0; |
407 | } | |
408 | ||
e1991885 | 409 | IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n"); |
fb66216f | 410 | |
6dfa8d01 | 411 | iwl_print_mismatch_sec(priv, &img->sec[IWL_UCODE_SECTION_INST]); |
fb66216f | 412 | return -EIO; |
db41dd27 | 413 | } |
ca7966c8 | 414 | |
69a679b0 | 415 | struct iwl_alive_data { |
ca7966c8 JB |
416 | bool valid; |
417 | u8 subtype; | |
418 | }; | |
419 | ||
4bd14dd5 | 420 | static void iwl_alive_fn(struct iwl_notif_wait_data *notif_wait, |
ca7966c8 JB |
421 | struct iwl_rx_packet *pkt, |
422 | void *data) | |
423 | { | |
4bd14dd5 JB |
424 | struct iwl_priv *priv = |
425 | container_of(notif_wait, struct iwl_priv, notif_wait); | |
69a679b0 | 426 | struct iwl_alive_data *alive_data = data; |
ca7966c8 JB |
427 | struct iwl_alive_resp *palive; |
428 | ||
f8d7c1a1 | 429 | palive = (void *)pkt->data; |
ca7966c8 | 430 | |
e1991885 | 431 | IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision " |
ca7966c8 JB |
432 | "0x%01X 0x%01X\n", |
433 | palive->is_valid, palive->ver_type, | |
434 | palive->ver_subtype); | |
435 | ||
e1991885 | 436 | priv->shrd->device_pointers.error_event_table = |
ca7966c8 | 437 | le32_to_cpu(palive->error_event_table_ptr); |
e1991885 | 438 | priv->shrd->device_pointers.log_event_table = |
ca7966c8 JB |
439 | le32_to_cpu(palive->log_event_table_ptr); |
440 | ||
441 | alive_data->subtype = palive->ver_subtype; | |
442 | alive_data->valid = palive->is_valid == UCODE_VALID_OK; | |
443 | } | |
444 | ||
445 | #define UCODE_ALIVE_TIMEOUT HZ | |
446 | #define UCODE_CALIB_TIMEOUT (2*HZ) | |
447 | ||
e1991885 | 448 | int iwl_load_ucode_wait_alive(struct iwl_priv *priv, |
de7f5f92 | 449 | enum iwl_ucode_type ucode_type) |
ca7966c8 JB |
450 | { |
451 | struct iwl_notification_wait alive_wait; | |
69a679b0 | 452 | struct iwl_alive_data alive_data; |
0692fe41 | 453 | const struct fw_img *fw; |
ca7966c8 | 454 | int ret; |
de7f5f92 | 455 | enum iwl_ucode_type old_type; |
ca7966c8 | 456 | |
e1991885 JB |
457 | old_type = priv->shrd->ucode_type; |
458 | priv->shrd->ucode_type = ucode_type; | |
459 | fw = iwl_get_ucode_image(priv, ucode_type); | |
ca7966c8 | 460 | |
8f7ffbe2 DS |
461 | priv->ucode_loaded = false; |
462 | ||
cf614297 EG |
463 | if (!fw) |
464 | return -EINVAL; | |
465 | ||
4bd14dd5 | 466 | iwl_init_notification_wait(&priv->notif_wait, &alive_wait, REPLY_ALIVE, |
f4720893 JB |
467 | iwl_alive_fn, &alive_data); |
468 | ||
e1991885 | 469 | ret = iwl_trans_start_fw(trans(priv), fw); |
ca7966c8 | 470 | if (ret) { |
e1991885 | 471 | priv->shrd->ucode_type = old_type; |
4bd14dd5 | 472 | iwl_remove_notification(&priv->notif_wait, &alive_wait); |
ca7966c8 JB |
473 | return ret; |
474 | } | |
475 | ||
ca7966c8 JB |
476 | /* |
477 | * Some things may run in the background now, but we | |
478 | * just wait for the ALIVE notification here. | |
479 | */ | |
4bd14dd5 | 480 | ret = iwl_wait_notification(&priv->notif_wait, &alive_wait, |
dd5fe104 | 481 | UCODE_ALIVE_TIMEOUT); |
ca7966c8 | 482 | if (ret) { |
e1991885 | 483 | priv->shrd->ucode_type = old_type; |
ca7966c8 JB |
484 | return ret; |
485 | } | |
486 | ||
487 | if (!alive_data.valid) { | |
e1991885 JB |
488 | IWL_ERR(priv, "Loaded ucode is not valid!\n"); |
489 | priv->shrd->ucode_type = old_type; | |
ca7966c8 JB |
490 | return -EIO; |
491 | } | |
492 | ||
c8ac61cf JB |
493 | /* |
494 | * This step takes a long time (60-80ms!!) and | |
495 | * WoWLAN image should be loaded quickly, so | |
496 | * skip it for WoWLAN. | |
497 | */ | |
498 | if (ucode_type != IWL_UCODE_WOWLAN) { | |
e1991885 | 499 | ret = iwl_verify_ucode(priv, ucode_type); |
c8ac61cf | 500 | if (ret) { |
e1991885 | 501 | priv->shrd->ucode_type = old_type; |
c8ac61cf JB |
502 | return ret; |
503 | } | |
ca7966c8 | 504 | |
c8ac61cf JB |
505 | /* delay a bit to give rfkill time to run */ |
506 | msleep(5); | |
507 | } | |
ca7966c8 | 508 | |
e1991885 | 509 | ret = iwl_alive_notify(priv); |
ca7966c8 | 510 | if (ret) { |
e1991885 | 511 | IWL_WARN(priv, |
ca7966c8 | 512 | "Could not complete ALIVE transition: %d\n", ret); |
e1991885 | 513 | priv->shrd->ucode_type = old_type; |
ca7966c8 JB |
514 | return ret; |
515 | } | |
516 | ||
8f7ffbe2 DS |
517 | priv->ucode_loaded = true; |
518 | ||
ca7966c8 JB |
519 | return 0; |
520 | } | |
521 | ||
e1991885 | 522 | int iwl_run_init_ucode(struct iwl_priv *priv) |
ca7966c8 JB |
523 | { |
524 | struct iwl_notification_wait calib_wait; | |
525 | int ret; | |
526 | ||
b1eea297 | 527 | lockdep_assert_held(&priv->mutex); |
ca7966c8 JB |
528 | |
529 | /* No init ucode required? Curious, but maybe ok */ | |
6dfa8d01 | 530 | if (!priv->fw->img[IWL_UCODE_INIT].sec[0].len) |
ca7966c8 JB |
531 | return 0; |
532 | ||
b5ea1624 | 533 | if (priv->init_ucode_run) |
ca7966c8 JB |
534 | return 0; |
535 | ||
4bd14dd5 | 536 | iwl_init_notification_wait(&priv->notif_wait, &calib_wait, |
ca7966c8 JB |
537 | CALIBRATION_COMPLETE_NOTIFICATION, |
538 | NULL, NULL); | |
539 | ||
540 | /* Will also start the device */ | |
e1991885 | 541 | ret = iwl_load_ucode_wait_alive(priv, IWL_UCODE_INIT); |
ca7966c8 JB |
542 | if (ret) |
543 | goto error; | |
544 | ||
e1991885 | 545 | ret = iwl_init_alive_start(priv); |
ca7966c8 JB |
546 | if (ret) |
547 | goto error; | |
548 | ||
549 | /* | |
550 | * Some things may run in the background now, but we | |
551 | * just wait for the calibration complete notification. | |
552 | */ | |
4bd14dd5 | 553 | ret = iwl_wait_notification(&priv->notif_wait, &calib_wait, |
dd5fe104 | 554 | UCODE_CALIB_TIMEOUT); |
b5ea1624 DS |
555 | if (!ret) |
556 | priv->init_ucode_run = true; | |
ca7966c8 JB |
557 | |
558 | goto out; | |
559 | ||
560 | error: | |
4bd14dd5 | 561 | iwl_remove_notification(&priv->notif_wait, &calib_wait); |
ca7966c8 JB |
562 | out: |
563 | /* Whatever happened, stop the device */ | |
e1991885 | 564 | iwl_trans_stop_device(trans(priv)); |
8f7ffbe2 DS |
565 | priv->ucode_loaded = false; |
566 | ||
ca7966c8 JB |
567 | return ret; |
568 | } |