Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
eb7ae89c | 3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/wireless.h> | |
39 | #include <linux/firmware.h> | |
b481de9c ZY |
40 | #include <linux/etherdevice.h> |
41 | #include <linux/if_arp.h> | |
42 | ||
43 | #include <net/ieee80211_radiotap.h> | |
44 | #include <net/mac80211.h> | |
45 | ||
46 | #include <asm/div64.h> | |
47 | ||
82b9a121 | 48 | #include "iwl-3945-core.h" |
b481de9c ZY |
49 | #include "iwl-3945.h" |
50 | #include "iwl-helpers.h" | |
51 | ||
c8b0e6e1 | 52 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 53 | u32 iwl3945_debug_level; |
b481de9c ZY |
54 | #endif |
55 | ||
bb8c093b CH |
56 | static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv, |
57 | struct iwl3945_tx_queue *txq); | |
416e1438 | 58 | |
b481de9c ZY |
59 | /****************************************************************************** |
60 | * | |
61 | * module boiler plate | |
62 | * | |
63 | ******************************************************************************/ | |
64 | ||
65 | /* module parameters */ | |
6440adb5 CB |
66 | static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */ |
67 | static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */ | |
68 | static int iwl3945_param_disable; /* def: 0 = enable radio */ | |
9fbab516 | 69 | static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */ |
6440adb5 CB |
70 | int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */ |
71 | static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */ | |
dfe7d458 | 72 | int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */ |
b481de9c ZY |
73 | |
74 | /* | |
75 | * module name, copyright, version, etc. | |
76 | * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk | |
77 | */ | |
78 | ||
79 | #define DRV_DESCRIPTION \ | |
80 | "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux" | |
81 | ||
c8b0e6e1 | 82 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
83 | #define VD "d" |
84 | #else | |
85 | #define VD | |
86 | #endif | |
87 | ||
c8b0e6e1 | 88 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
89 | #define VS "s" |
90 | #else | |
91 | #define VS | |
92 | #endif | |
93 | ||
b9e0b449 | 94 | #define IWLWIFI_VERSION "1.2.26k" VD VS |
eb7ae89c | 95 | #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation" |
b481de9c ZY |
96 | #define DRV_VERSION IWLWIFI_VERSION |
97 | ||
b481de9c ZY |
98 | |
99 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
100 | MODULE_VERSION(DRV_VERSION); | |
101 | MODULE_AUTHOR(DRV_COPYRIGHT); | |
102 | MODULE_LICENSE("GPL"); | |
103 | ||
8318d78a JB |
104 | static const struct ieee80211_supported_band *iwl3945_get_band( |
105 | struct iwl3945_priv *priv, enum ieee80211_band band) | |
b481de9c | 106 | { |
8318d78a | 107 | return priv->hw->wiphy->bands[band]; |
b481de9c ZY |
108 | } |
109 | ||
bb8c093b | 110 | static int iwl3945_is_empty_essid(const char *essid, int essid_len) |
b481de9c ZY |
111 | { |
112 | /* Single white space is for Linksys APs */ | |
113 | if (essid_len == 1 && essid[0] == ' ') | |
114 | return 1; | |
115 | ||
116 | /* Otherwise, if the entire essid is 0, we assume it is hidden */ | |
117 | while (essid_len) { | |
118 | essid_len--; | |
119 | if (essid[essid_len] != '\0') | |
120 | return 0; | |
121 | } | |
122 | ||
123 | return 1; | |
124 | } | |
125 | ||
bb8c093b | 126 | static const char *iwl3945_escape_essid(const char *essid, u8 essid_len) |
b481de9c ZY |
127 | { |
128 | static char escaped[IW_ESSID_MAX_SIZE * 2 + 1]; | |
129 | const char *s = essid; | |
130 | char *d = escaped; | |
131 | ||
bb8c093b | 132 | if (iwl3945_is_empty_essid(essid, essid_len)) { |
b481de9c ZY |
133 | memcpy(escaped, "<hidden>", sizeof("<hidden>")); |
134 | return escaped; | |
135 | } | |
136 | ||
137 | essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE); | |
138 | while (essid_len--) { | |
139 | if (*s == '\0') { | |
140 | *d++ = '\\'; | |
141 | *d++ = '0'; | |
142 | s++; | |
143 | } else | |
144 | *d++ = *s++; | |
145 | } | |
146 | *d = '\0'; | |
147 | return escaped; | |
148 | } | |
149 | ||
b481de9c ZY |
150 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
151 | * DMA services | |
152 | * | |
153 | * Theory of operation | |
154 | * | |
6440adb5 CB |
155 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer |
156 | * of buffer descriptors, each of which points to one or more data buffers for | |
157 | * the device to read from or fill. Driver and device exchange status of each | |
158 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
159 | * entries in each circular buffer, to protect against confusing empty and full | |
160 | * queue states. | |
161 | * | |
162 | * The device reads or writes the data in the queues via the device's several | |
163 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
b481de9c ZY |
164 | * |
165 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
166 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
167 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
168 | * Tx queue resumed. | |
169 | * | |
6440adb5 CB |
170 | * The 3945 operates with six queues: One receive queue, one transmit queue |
171 | * (#4) for sending commands to the device firmware, and four transmit queues | |
172 | * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused. | |
b481de9c ZY |
173 | ***************************************************/ |
174 | ||
c54b679d | 175 | int iwl3945_queue_space(const struct iwl3945_queue *q) |
b481de9c | 176 | { |
fc4b6853 | 177 | int s = q->read_ptr - q->write_ptr; |
b481de9c | 178 | |
fc4b6853 | 179 | if (q->read_ptr > q->write_ptr) |
b481de9c ZY |
180 | s -= q->n_bd; |
181 | ||
182 | if (s <= 0) | |
183 | s += q->n_window; | |
184 | /* keep some reserve to not confuse empty and full situations */ | |
185 | s -= 2; | |
186 | if (s < 0) | |
187 | s = 0; | |
188 | return s; | |
189 | } | |
190 | ||
c54b679d | 191 | int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i) |
b481de9c | 192 | { |
fc4b6853 TW |
193 | return q->write_ptr > q->read_ptr ? |
194 | (i >= q->read_ptr && i < q->write_ptr) : | |
195 | !(i < q->read_ptr && i >= q->write_ptr); | |
b481de9c ZY |
196 | } |
197 | ||
c54b679d | 198 | |
bb8c093b | 199 | static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge) |
b481de9c | 200 | { |
6440adb5 | 201 | /* This is for scan command, the big buffer at end of command array */ |
b481de9c | 202 | if (is_huge) |
6440adb5 | 203 | return q->n_window; /* must be power of 2 */ |
b481de9c | 204 | |
6440adb5 | 205 | /* Otherwise, use normal size buffers */ |
b481de9c ZY |
206 | return index & (q->n_window - 1); |
207 | } | |
208 | ||
6440adb5 CB |
209 | /** |
210 | * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes | |
211 | */ | |
bb8c093b | 212 | static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q, |
b481de9c ZY |
213 | int count, int slots_num, u32 id) |
214 | { | |
215 | q->n_bd = count; | |
216 | q->n_window = slots_num; | |
217 | q->id = id; | |
218 | ||
c54b679d TW |
219 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap |
220 | * and iwl_queue_dec_wrap are broken. */ | |
b481de9c ZY |
221 | BUG_ON(!is_power_of_2(count)); |
222 | ||
223 | /* slots_num must be power-of-two size, otherwise | |
224 | * get_cmd_index is broken. */ | |
225 | BUG_ON(!is_power_of_2(slots_num)); | |
226 | ||
227 | q->low_mark = q->n_window / 4; | |
228 | if (q->low_mark < 4) | |
229 | q->low_mark = 4; | |
230 | ||
231 | q->high_mark = q->n_window / 8; | |
232 | if (q->high_mark < 2) | |
233 | q->high_mark = 2; | |
234 | ||
fc4b6853 | 235 | q->write_ptr = q->read_ptr = 0; |
b481de9c ZY |
236 | |
237 | return 0; | |
238 | } | |
239 | ||
6440adb5 CB |
240 | /** |
241 | * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
242 | */ | |
bb8c093b CH |
243 | static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv, |
244 | struct iwl3945_tx_queue *txq, u32 id) | |
b481de9c ZY |
245 | { |
246 | struct pci_dev *dev = priv->pci_dev; | |
247 | ||
6440adb5 CB |
248 | /* Driver private data, only for Tx (not command) queues, |
249 | * not shared with device. */ | |
b481de9c ZY |
250 | if (id != IWL_CMD_QUEUE_NUM) { |
251 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
252 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
253 | if (!txq->txb) { | |
01ebd063 | 254 | IWL_ERROR("kmalloc for auxiliary BD " |
b481de9c ZY |
255 | "structures failed\n"); |
256 | goto error; | |
257 | } | |
258 | } else | |
259 | txq->txb = NULL; | |
260 | ||
6440adb5 CB |
261 | /* Circular buffer of transmit frame descriptors (TFDs), |
262 | * shared with device */ | |
b481de9c ZY |
263 | txq->bd = pci_alloc_consistent(dev, |
264 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX, | |
265 | &txq->q.dma_addr); | |
266 | ||
267 | if (!txq->bd) { | |
268 | IWL_ERROR("pci_alloc_consistent(%zd) failed\n", | |
269 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX); | |
270 | goto error; | |
271 | } | |
272 | txq->q.id = id; | |
273 | ||
274 | return 0; | |
275 | ||
276 | error: | |
3ac7f146 TW |
277 | kfree(txq->txb); |
278 | txq->txb = NULL; | |
b481de9c ZY |
279 | |
280 | return -ENOMEM; | |
281 | } | |
282 | ||
6440adb5 CB |
283 | /** |
284 | * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue | |
285 | */ | |
bb8c093b CH |
286 | int iwl3945_tx_queue_init(struct iwl3945_priv *priv, |
287 | struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id) | |
b481de9c ZY |
288 | { |
289 | struct pci_dev *dev = priv->pci_dev; | |
290 | int len; | |
291 | int rc = 0; | |
292 | ||
6440adb5 CB |
293 | /* |
294 | * Alloc buffer array for commands (Tx or other types of commands). | |
295 | * For the command queue (#4), allocate command space + one big | |
296 | * command for scan, since scan command is very huge; the system will | |
297 | * not have two scans at the same time, so only one is needed. | |
298 | * For data Tx queues (all other queues), no super-size command | |
299 | * space is needed. | |
300 | */ | |
bb8c093b | 301 | len = sizeof(struct iwl3945_cmd) * slots_num; |
b481de9c ZY |
302 | if (txq_id == IWL_CMD_QUEUE_NUM) |
303 | len += IWL_MAX_SCAN_SIZE; | |
304 | txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd); | |
305 | if (!txq->cmd) | |
306 | return -ENOMEM; | |
307 | ||
6440adb5 | 308 | /* Alloc driver data array and TFD circular buffer */ |
bb8c093b | 309 | rc = iwl3945_tx_queue_alloc(priv, txq, txq_id); |
b481de9c ZY |
310 | if (rc) { |
311 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); | |
312 | ||
313 | return -ENOMEM; | |
314 | } | |
315 | txq->need_update = 0; | |
316 | ||
317 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
c54b679d | 318 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ |
b481de9c | 319 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); |
6440adb5 CB |
320 | |
321 | /* Initialize queue high/low-water, head/tail indexes */ | |
bb8c093b | 322 | iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
b481de9c | 323 | |
6440adb5 | 324 | /* Tell device where to find queue, enable DMA channel. */ |
bb8c093b | 325 | iwl3945_hw_tx_queue_init(priv, txq); |
b481de9c ZY |
326 | |
327 | return 0; | |
328 | } | |
329 | ||
330 | /** | |
bb8c093b | 331 | * iwl3945_tx_queue_free - Deallocate DMA queue. |
b481de9c ZY |
332 | * @txq: Transmit queue to deallocate. |
333 | * | |
334 | * Empty queue by removing and destroying all BD's. | |
6440adb5 CB |
335 | * Free all buffers. |
336 | * 0-fill, but do not free "txq" descriptor structure. | |
b481de9c | 337 | */ |
bb8c093b | 338 | void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq) |
b481de9c | 339 | { |
bb8c093b | 340 | struct iwl3945_queue *q = &txq->q; |
b481de9c ZY |
341 | struct pci_dev *dev = priv->pci_dev; |
342 | int len; | |
343 | ||
344 | if (q->n_bd == 0) | |
345 | return; | |
346 | ||
347 | /* first, empty all BD's */ | |
fc4b6853 | 348 | for (; q->write_ptr != q->read_ptr; |
c54b679d | 349 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) |
bb8c093b | 350 | iwl3945_hw_txq_free_tfd(priv, txq); |
b481de9c | 351 | |
bb8c093b | 352 | len = sizeof(struct iwl3945_cmd) * q->n_window; |
b481de9c ZY |
353 | if (q->id == IWL_CMD_QUEUE_NUM) |
354 | len += IWL_MAX_SCAN_SIZE; | |
355 | ||
6440adb5 | 356 | /* De-alloc array of command/tx buffers */ |
b481de9c ZY |
357 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); |
358 | ||
6440adb5 | 359 | /* De-alloc circular buffer of TFDs */ |
b481de9c | 360 | if (txq->q.n_bd) |
bb8c093b | 361 | pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) * |
b481de9c ZY |
362 | txq->q.n_bd, txq->bd, txq->q.dma_addr); |
363 | ||
6440adb5 | 364 | /* De-alloc array of per-TFD driver data */ |
3ac7f146 TW |
365 | kfree(txq->txb); |
366 | txq->txb = NULL; | |
b481de9c | 367 | |
6440adb5 | 368 | /* 0-fill queue descriptor structure */ |
b481de9c ZY |
369 | memset(txq, 0, sizeof(*txq)); |
370 | } | |
371 | ||
bb8c093b | 372 | const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
b481de9c ZY |
373 | |
374 | /*************** STATION TABLE MANAGEMENT **** | |
9fbab516 | 375 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
376 | * the functionality provided here |
377 | */ | |
378 | ||
379 | /**************************************************************/ | |
01ebd063 | 380 | #if 0 /* temporary disable till we add real remove station */ |
6440adb5 CB |
381 | /** |
382 | * iwl3945_remove_station - Remove driver's knowledge of station. | |
383 | * | |
384 | * NOTE: This does not remove station from device's station table. | |
385 | */ | |
bb8c093b | 386 | static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap) |
b481de9c ZY |
387 | { |
388 | int index = IWL_INVALID_STATION; | |
389 | int i; | |
390 | unsigned long flags; | |
391 | ||
392 | spin_lock_irqsave(&priv->sta_lock, flags); | |
393 | ||
394 | if (is_ap) | |
395 | index = IWL_AP_ID; | |
396 | else if (is_broadcast_ether_addr(addr)) | |
397 | index = priv->hw_setting.bcast_sta_id; | |
398 | else | |
399 | for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) | |
400 | if (priv->stations[i].used && | |
401 | !compare_ether_addr(priv->stations[i].sta.sta.addr, | |
402 | addr)) { | |
403 | index = i; | |
404 | break; | |
405 | } | |
406 | ||
407 | if (unlikely(index == IWL_INVALID_STATION)) | |
408 | goto out; | |
409 | ||
410 | if (priv->stations[index].used) { | |
411 | priv->stations[index].used = 0; | |
412 | priv->num_stations--; | |
413 | } | |
414 | ||
415 | BUG_ON(priv->num_stations < 0); | |
416 | ||
417 | out: | |
418 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
419 | return 0; | |
420 | } | |
556f8db7 | 421 | #endif |
6440adb5 CB |
422 | |
423 | /** | |
424 | * iwl3945_clear_stations_table - Clear the driver's station table | |
425 | * | |
426 | * NOTE: This does not clear or otherwise alter the device's station table. | |
427 | */ | |
bb8c093b | 428 | static void iwl3945_clear_stations_table(struct iwl3945_priv *priv) |
b481de9c ZY |
429 | { |
430 | unsigned long flags; | |
431 | ||
432 | spin_lock_irqsave(&priv->sta_lock, flags); | |
433 | ||
434 | priv->num_stations = 0; | |
435 | memset(priv->stations, 0, sizeof(priv->stations)); | |
436 | ||
437 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
438 | } | |
439 | ||
6440adb5 CB |
440 | /** |
441 | * iwl3945_add_station - Add station to station tables in driver and device | |
442 | */ | |
bb8c093b | 443 | u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags) |
b481de9c ZY |
444 | { |
445 | int i; | |
446 | int index = IWL_INVALID_STATION; | |
bb8c093b | 447 | struct iwl3945_station_entry *station; |
b481de9c | 448 | unsigned long flags_spin; |
0795af57 | 449 | DECLARE_MAC_BUF(mac); |
c14c521e | 450 | u8 rate; |
b481de9c ZY |
451 | |
452 | spin_lock_irqsave(&priv->sta_lock, flags_spin); | |
453 | if (is_ap) | |
454 | index = IWL_AP_ID; | |
455 | else if (is_broadcast_ether_addr(addr)) | |
456 | index = priv->hw_setting.bcast_sta_id; | |
457 | else | |
458 | for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) { | |
459 | if (!compare_ether_addr(priv->stations[i].sta.sta.addr, | |
460 | addr)) { | |
461 | index = i; | |
462 | break; | |
463 | } | |
464 | ||
465 | if (!priv->stations[i].used && | |
466 | index == IWL_INVALID_STATION) | |
467 | index = i; | |
468 | } | |
469 | ||
01ebd063 | 470 | /* These two conditions has the same outcome but keep them separate |
b481de9c ZY |
471 | since they have different meaning */ |
472 | if (unlikely(index == IWL_INVALID_STATION)) { | |
473 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
474 | return index; | |
475 | } | |
476 | ||
477 | if (priv->stations[index].used && | |
478 | !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) { | |
479 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
480 | return index; | |
481 | } | |
482 | ||
0795af57 | 483 | IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr)); |
b481de9c ZY |
484 | station = &priv->stations[index]; |
485 | station->used = 1; | |
486 | priv->num_stations++; | |
487 | ||
6440adb5 | 488 | /* Set up the REPLY_ADD_STA command to send to device */ |
bb8c093b | 489 | memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd)); |
b481de9c ZY |
490 | memcpy(station->sta.sta.addr, addr, ETH_ALEN); |
491 | station->sta.mode = 0; | |
492 | station->sta.sta.sta_id = index; | |
493 | station->sta.station_flags = 0; | |
494 | ||
8318d78a | 495 | if (priv->band == IEEE80211_BAND_5GHZ) |
69946333 TW |
496 | rate = IWL_RATE_6M_PLCP; |
497 | else | |
498 | rate = IWL_RATE_1M_PLCP; | |
c14c521e ZY |
499 | |
500 | /* Turn on both antennas for the station... */ | |
501 | station->sta.rate_n_flags = | |
bb8c093b | 502 | iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK); |
c14c521e ZY |
503 | station->current_rate.rate_n_flags = |
504 | le16_to_cpu(station->sta.rate_n_flags); | |
505 | ||
b481de9c | 506 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); |
6440adb5 CB |
507 | |
508 | /* Add station to device's station table */ | |
bb8c093b | 509 | iwl3945_send_add_station(priv, &station->sta, flags); |
b481de9c ZY |
510 | return index; |
511 | ||
512 | } | |
513 | ||
514 | /*************** DRIVER STATUS FUNCTIONS *****/ | |
515 | ||
bb8c093b | 516 | static inline int iwl3945_is_ready(struct iwl3945_priv *priv) |
b481de9c ZY |
517 | { |
518 | /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are | |
519 | * set but EXIT_PENDING is not */ | |
520 | return test_bit(STATUS_READY, &priv->status) && | |
521 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) && | |
522 | !test_bit(STATUS_EXIT_PENDING, &priv->status); | |
523 | } | |
524 | ||
bb8c093b | 525 | static inline int iwl3945_is_alive(struct iwl3945_priv *priv) |
b481de9c ZY |
526 | { |
527 | return test_bit(STATUS_ALIVE, &priv->status); | |
528 | } | |
529 | ||
bb8c093b | 530 | static inline int iwl3945_is_init(struct iwl3945_priv *priv) |
b481de9c ZY |
531 | { |
532 | return test_bit(STATUS_INIT, &priv->status); | |
533 | } | |
534 | ||
80fcc9e2 AG |
535 | static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv) |
536 | { | |
537 | return test_bit(STATUS_RF_KILL_SW, &priv->status); | |
538 | } | |
539 | ||
540 | static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv) | |
541 | { | |
542 | return test_bit(STATUS_RF_KILL_HW, &priv->status); | |
543 | } | |
544 | ||
bb8c093b | 545 | static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv) |
b481de9c | 546 | { |
80fcc9e2 AG |
547 | return iwl3945_is_rfkill_hw(priv) || |
548 | iwl3945_is_rfkill_sw(priv); | |
b481de9c ZY |
549 | } |
550 | ||
bb8c093b | 551 | static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv) |
b481de9c ZY |
552 | { |
553 | ||
bb8c093b | 554 | if (iwl3945_is_rfkill(priv)) |
b481de9c ZY |
555 | return 0; |
556 | ||
bb8c093b | 557 | return iwl3945_is_ready(priv); |
b481de9c ZY |
558 | } |
559 | ||
560 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
561 | ||
562 | #define IWL_CMD(x) case x : return #x | |
563 | ||
564 | static const char *get_cmd_string(u8 cmd) | |
565 | { | |
566 | switch (cmd) { | |
567 | IWL_CMD(REPLY_ALIVE); | |
568 | IWL_CMD(REPLY_ERROR); | |
569 | IWL_CMD(REPLY_RXON); | |
570 | IWL_CMD(REPLY_RXON_ASSOC); | |
571 | IWL_CMD(REPLY_QOS_PARAM); | |
572 | IWL_CMD(REPLY_RXON_TIMING); | |
573 | IWL_CMD(REPLY_ADD_STA); | |
574 | IWL_CMD(REPLY_REMOVE_STA); | |
575 | IWL_CMD(REPLY_REMOVE_ALL_STA); | |
576 | IWL_CMD(REPLY_3945_RX); | |
577 | IWL_CMD(REPLY_TX); | |
578 | IWL_CMD(REPLY_RATE_SCALE); | |
579 | IWL_CMD(REPLY_LEDS_CMD); | |
580 | IWL_CMD(REPLY_TX_LINK_QUALITY_CMD); | |
581 | IWL_CMD(RADAR_NOTIFICATION); | |
582 | IWL_CMD(REPLY_QUIET_CMD); | |
583 | IWL_CMD(REPLY_CHANNEL_SWITCH); | |
584 | IWL_CMD(CHANNEL_SWITCH_NOTIFICATION); | |
585 | IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD); | |
586 | IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION); | |
587 | IWL_CMD(POWER_TABLE_CMD); | |
588 | IWL_CMD(PM_SLEEP_NOTIFICATION); | |
589 | IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC); | |
590 | IWL_CMD(REPLY_SCAN_CMD); | |
591 | IWL_CMD(REPLY_SCAN_ABORT_CMD); | |
592 | IWL_CMD(SCAN_START_NOTIFICATION); | |
593 | IWL_CMD(SCAN_RESULTS_NOTIFICATION); | |
594 | IWL_CMD(SCAN_COMPLETE_NOTIFICATION); | |
595 | IWL_CMD(BEACON_NOTIFICATION); | |
596 | IWL_CMD(REPLY_TX_BEACON); | |
597 | IWL_CMD(WHO_IS_AWAKE_NOTIFICATION); | |
598 | IWL_CMD(QUIET_NOTIFICATION); | |
599 | IWL_CMD(REPLY_TX_PWR_TABLE_CMD); | |
600 | IWL_CMD(MEASURE_ABORT_NOTIFICATION); | |
601 | IWL_CMD(REPLY_BT_CONFIG); | |
602 | IWL_CMD(REPLY_STATISTICS_CMD); | |
603 | IWL_CMD(STATISTICS_NOTIFICATION); | |
604 | IWL_CMD(REPLY_CARD_STATE_CMD); | |
605 | IWL_CMD(CARD_STATE_NOTIFICATION); | |
606 | IWL_CMD(MISSED_BEACONS_NOTIFICATION); | |
607 | default: | |
608 | return "UNKNOWN"; | |
609 | ||
610 | } | |
611 | } | |
612 | ||
613 | #define HOST_COMPLETE_TIMEOUT (HZ / 2) | |
614 | ||
615 | /** | |
bb8c093b | 616 | * iwl3945_enqueue_hcmd - enqueue a uCode command |
b481de9c ZY |
617 | * @priv: device private data point |
618 | * @cmd: a point to the ucode command structure | |
619 | * | |
620 | * The function returns < 0 values to indicate the operation is | |
621 | * failed. On success, it turns the index (> 0) of command in the | |
622 | * command queue. | |
623 | */ | |
bb8c093b | 624 | static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c | 625 | { |
bb8c093b CH |
626 | struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; |
627 | struct iwl3945_queue *q = &txq->q; | |
628 | struct iwl3945_tfd_frame *tfd; | |
b481de9c | 629 | u32 *control_flags; |
bb8c093b | 630 | struct iwl3945_cmd *out_cmd; |
b481de9c ZY |
631 | u32 idx; |
632 | u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
633 | dma_addr_t phys_addr; | |
634 | int pad; | |
635 | u16 count; | |
636 | int ret; | |
637 | unsigned long flags; | |
638 | ||
639 | /* If any of the command structures end up being larger than | |
640 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
641 | * we will need to increase the size of the TFD entries */ | |
642 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
643 | !(cmd->meta.flags & CMD_SIZE_HUGE)); | |
644 | ||
c342a1b9 GG |
645 | |
646 | if (iwl3945_is_rfkill(priv)) { | |
647 | IWL_DEBUG_INFO("Not sending command - RF KILL"); | |
648 | return -EIO; | |
649 | } | |
650 | ||
bb8c093b | 651 | if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) { |
b481de9c ZY |
652 | IWL_ERROR("No space for Tx\n"); |
653 | return -ENOSPC; | |
654 | } | |
655 | ||
656 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
657 | ||
fc4b6853 | 658 | tfd = &txq->bd[q->write_ptr]; |
b481de9c ZY |
659 | memset(tfd, 0, sizeof(*tfd)); |
660 | ||
661 | control_flags = (u32 *) tfd; | |
662 | ||
fc4b6853 | 663 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); |
b481de9c ZY |
664 | out_cmd = &txq->cmd[idx]; |
665 | ||
666 | out_cmd->hdr.cmd = cmd->id; | |
667 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); | |
668 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
669 | ||
670 | /* At this point, the out_cmd now has all of the incoming cmd | |
671 | * information */ | |
672 | ||
673 | out_cmd->hdr.flags = 0; | |
674 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
fc4b6853 | 675 | INDEX_TO_SEQ(q->write_ptr)); |
b481de9c ZY |
676 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) |
677 | out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME); | |
678 | ||
679 | phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx + | |
bb8c093b CH |
680 | offsetof(struct iwl3945_cmd, hdr); |
681 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size); | |
b481de9c ZY |
682 | |
683 | pad = U32_PAD(cmd->len); | |
684 | count = TFD_CTL_COUNT_GET(*control_flags); | |
685 | *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad); | |
686 | ||
687 | IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, " | |
688 | "%d bytes at %d[%d]:%d\n", | |
689 | get_cmd_string(out_cmd->hdr.cmd), | |
690 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), | |
fc4b6853 | 691 | fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM); |
b481de9c ZY |
692 | |
693 | txq->need_update = 1; | |
6440adb5 CB |
694 | |
695 | /* Increment and update queue's write index */ | |
c54b679d | 696 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
bb8c093b | 697 | ret = iwl3945_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
698 | |
699 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
700 | return ret ? ret : idx; | |
701 | } | |
702 | ||
bb8c093b | 703 | static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c ZY |
704 | { |
705 | int ret; | |
706 | ||
707 | BUG_ON(!(cmd->meta.flags & CMD_ASYNC)); | |
708 | ||
709 | /* An asynchronous command can not expect an SKB to be set. */ | |
710 | BUG_ON(cmd->meta.flags & CMD_WANT_SKB); | |
711 | ||
712 | /* An asynchronous command MUST have a callback. */ | |
713 | BUG_ON(!cmd->meta.u.callback); | |
714 | ||
715 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
716 | return -EBUSY; | |
717 | ||
bb8c093b | 718 | ret = iwl3945_enqueue_hcmd(priv, cmd); |
b481de9c | 719 | if (ret < 0) { |
bb8c093b | 720 | IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n", |
b481de9c ZY |
721 | get_cmd_string(cmd->id), ret); |
722 | return ret; | |
723 | } | |
724 | return 0; | |
725 | } | |
726 | ||
bb8c093b | 727 | static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c ZY |
728 | { |
729 | int cmd_idx; | |
730 | int ret; | |
b481de9c ZY |
731 | |
732 | BUG_ON(cmd->meta.flags & CMD_ASYNC); | |
733 | ||
734 | /* A synchronous command can not have a callback set. */ | |
735 | BUG_ON(cmd->meta.u.callback != NULL); | |
736 | ||
e5472978 | 737 | if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) { |
b481de9c ZY |
738 | IWL_ERROR("Error sending %s: Already sending a host command\n", |
739 | get_cmd_string(cmd->id)); | |
e5472978 TW |
740 | ret = -EBUSY; |
741 | goto out; | |
b481de9c ZY |
742 | } |
743 | ||
744 | set_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
745 | ||
746 | if (cmd->meta.flags & CMD_WANT_SKB) | |
747 | cmd->meta.source = &cmd->meta; | |
748 | ||
bb8c093b | 749 | cmd_idx = iwl3945_enqueue_hcmd(priv, cmd); |
b481de9c ZY |
750 | if (cmd_idx < 0) { |
751 | ret = cmd_idx; | |
bb8c093b | 752 | IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n", |
b481de9c ZY |
753 | get_cmd_string(cmd->id), ret); |
754 | goto out; | |
755 | } | |
756 | ||
757 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
758 | !test_bit(STATUS_HCMD_ACTIVE, &priv->status), | |
759 | HOST_COMPLETE_TIMEOUT); | |
760 | if (!ret) { | |
761 | if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) { | |
762 | IWL_ERROR("Error sending %s: time out after %dms.\n", | |
763 | get_cmd_string(cmd->id), | |
764 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
765 | ||
766 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
767 | ret = -ETIMEDOUT; | |
768 | goto cancel; | |
769 | } | |
770 | } | |
771 | ||
772 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
773 | IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n", | |
774 | get_cmd_string(cmd->id)); | |
775 | ret = -ECANCELED; | |
776 | goto fail; | |
777 | } | |
778 | if (test_bit(STATUS_FW_ERROR, &priv->status)) { | |
779 | IWL_DEBUG_INFO("Command %s failed: FW Error\n", | |
780 | get_cmd_string(cmd->id)); | |
781 | ret = -EIO; | |
782 | goto fail; | |
783 | } | |
784 | if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) { | |
785 | IWL_ERROR("Error: Response NULL in '%s'\n", | |
786 | get_cmd_string(cmd->id)); | |
787 | ret = -EIO; | |
788 | goto out; | |
789 | } | |
790 | ||
791 | ret = 0; | |
792 | goto out; | |
793 | ||
794 | cancel: | |
795 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
bb8c093b | 796 | struct iwl3945_cmd *qcmd; |
b481de9c ZY |
797 | |
798 | /* Cancel the CMD_WANT_SKB flag for the cmd in the | |
799 | * TX cmd queue. Otherwise in case the cmd comes | |
800 | * in later, it will possibly set an invalid | |
801 | * address (cmd->meta.source). */ | |
802 | qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx]; | |
803 | qcmd->meta.flags &= ~CMD_WANT_SKB; | |
804 | } | |
805 | fail: | |
806 | if (cmd->meta.u.skb) { | |
807 | dev_kfree_skb_any(cmd->meta.u.skb); | |
808 | cmd->meta.u.skb = NULL; | |
809 | } | |
810 | out: | |
e5472978 | 811 | clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status); |
b481de9c ZY |
812 | return ret; |
813 | } | |
814 | ||
bb8c093b | 815 | int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c | 816 | { |
b481de9c | 817 | if (cmd->meta.flags & CMD_ASYNC) |
bb8c093b | 818 | return iwl3945_send_cmd_async(priv, cmd); |
b481de9c | 819 | |
bb8c093b | 820 | return iwl3945_send_cmd_sync(priv, cmd); |
b481de9c ZY |
821 | } |
822 | ||
bb8c093b | 823 | int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data) |
b481de9c | 824 | { |
bb8c093b | 825 | struct iwl3945_host_cmd cmd = { |
b481de9c ZY |
826 | .id = id, |
827 | .len = len, | |
828 | .data = data, | |
829 | }; | |
830 | ||
bb8c093b | 831 | return iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
832 | } |
833 | ||
bb8c093b | 834 | static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val) |
b481de9c | 835 | { |
bb8c093b | 836 | struct iwl3945_host_cmd cmd = { |
b481de9c ZY |
837 | .id = id, |
838 | .len = sizeof(val), | |
839 | .data = &val, | |
840 | }; | |
841 | ||
bb8c093b | 842 | return iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
843 | } |
844 | ||
bb8c093b | 845 | int iwl3945_send_statistics_request(struct iwl3945_priv *priv) |
b481de9c | 846 | { |
bb8c093b | 847 | return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0); |
b481de9c ZY |
848 | } |
849 | ||
b481de9c | 850 | /** |
bb8c093b | 851 | * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON |
8318d78a JB |
852 | * @band: 2.4 or 5 GHz band |
853 | * @channel: Any channel valid for the requested band | |
b481de9c | 854 | |
8318d78a | 855 | * In addition to setting the staging RXON, priv->band is also set. |
b481de9c ZY |
856 | * |
857 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields | |
8318d78a | 858 | * in the staging RXON flag structure based on the band |
b481de9c | 859 | */ |
8318d78a JB |
860 | static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv, |
861 | enum ieee80211_band band, | |
862 | u16 channel) | |
b481de9c | 863 | { |
8318d78a | 864 | if (!iwl3945_get_channel_info(priv, band, channel)) { |
b481de9c | 865 | IWL_DEBUG_INFO("Could not set channel to %d [%d]\n", |
8318d78a | 866 | channel, band); |
b481de9c ZY |
867 | return -EINVAL; |
868 | } | |
869 | ||
870 | if ((le16_to_cpu(priv->staging_rxon.channel) == channel) && | |
8318d78a | 871 | (priv->band == band)) |
b481de9c ZY |
872 | return 0; |
873 | ||
874 | priv->staging_rxon.channel = cpu_to_le16(channel); | |
8318d78a | 875 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
876 | priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK; |
877 | else | |
878 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
879 | ||
8318d78a | 880 | priv->band = band; |
b481de9c | 881 | |
8318d78a | 882 | IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band); |
b481de9c ZY |
883 | |
884 | return 0; | |
885 | } | |
886 | ||
887 | /** | |
bb8c093b | 888 | * iwl3945_check_rxon_cmd - validate RXON structure is valid |
b481de9c ZY |
889 | * |
890 | * NOTE: This is really only useful during development and can eventually | |
891 | * be #ifdef'd out once the driver is stable and folks aren't actively | |
892 | * making changes | |
893 | */ | |
bb8c093b | 894 | static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon) |
b481de9c ZY |
895 | { |
896 | int error = 0; | |
897 | int counter = 1; | |
898 | ||
899 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
900 | error |= le32_to_cpu(rxon->flags & | |
901 | (RXON_FLG_TGJ_NARROW_BAND_MSK | | |
902 | RXON_FLG_RADAR_DETECT_MSK)); | |
903 | if (error) | |
904 | IWL_WARNING("check 24G fields %d | %d\n", | |
905 | counter++, error); | |
906 | } else { | |
907 | error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ? | |
908 | 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK); | |
909 | if (error) | |
910 | IWL_WARNING("check 52 fields %d | %d\n", | |
911 | counter++, error); | |
912 | error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK); | |
913 | if (error) | |
914 | IWL_WARNING("check 52 CCK %d | %d\n", | |
915 | counter++, error); | |
916 | } | |
917 | error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1; | |
918 | if (error) | |
919 | IWL_WARNING("check mac addr %d | %d\n", counter++, error); | |
920 | ||
921 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
922 | error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) && | |
923 | ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0)); | |
924 | if (error) | |
925 | IWL_WARNING("check basic rate %d | %d\n", counter++, error); | |
926 | ||
927 | error |= (le16_to_cpu(rxon->assoc_id) > 2007); | |
928 | if (error) | |
929 | IWL_WARNING("check assoc id %d | %d\n", counter++, error); | |
930 | ||
931 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) | |
932 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)); | |
933 | if (error) | |
934 | IWL_WARNING("check CCK and short slot %d | %d\n", | |
935 | counter++, error); | |
936 | ||
937 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) | |
938 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)); | |
939 | if (error) | |
940 | IWL_WARNING("check CCK & auto detect %d | %d\n", | |
941 | counter++, error); | |
942 | ||
943 | error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | | |
944 | RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK); | |
945 | if (error) | |
946 | IWL_WARNING("check TGG and auto detect %d | %d\n", | |
947 | counter++, error); | |
948 | ||
949 | if ((rxon->flags & RXON_FLG_DIS_DIV_MSK)) | |
950 | error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK | | |
951 | RXON_FLG_ANT_A_MSK)) == 0); | |
952 | if (error) | |
953 | IWL_WARNING("check antenna %d %d\n", counter++, error); | |
954 | ||
955 | if (error) | |
956 | IWL_WARNING("Tuning to channel %d\n", | |
957 | le16_to_cpu(rxon->channel)); | |
958 | ||
959 | if (error) { | |
bb8c093b | 960 | IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n"); |
b481de9c ZY |
961 | return -1; |
962 | } | |
963 | return 0; | |
964 | } | |
965 | ||
966 | /** | |
9fbab516 | 967 | * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed |
01ebd063 | 968 | * @priv: staging_rxon is compared to active_rxon |
b481de9c | 969 | * |
9fbab516 BC |
970 | * If the RXON structure is changing enough to require a new tune, |
971 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
972 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
b481de9c | 973 | */ |
bb8c093b | 974 | static int iwl3945_full_rxon_required(struct iwl3945_priv *priv) |
b481de9c ZY |
975 | { |
976 | ||
977 | /* These items are only settable from the full RXON command */ | |
5d1e2325 | 978 | if (!(iwl3945_is_associated(priv)) || |
b481de9c ZY |
979 | compare_ether_addr(priv->staging_rxon.bssid_addr, |
980 | priv->active_rxon.bssid_addr) || | |
981 | compare_ether_addr(priv->staging_rxon.node_addr, | |
982 | priv->active_rxon.node_addr) || | |
983 | compare_ether_addr(priv->staging_rxon.wlap_bssid_addr, | |
984 | priv->active_rxon.wlap_bssid_addr) || | |
985 | (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) || | |
986 | (priv->staging_rxon.channel != priv->active_rxon.channel) || | |
987 | (priv->staging_rxon.air_propagation != | |
988 | priv->active_rxon.air_propagation) || | |
989 | (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id)) | |
990 | return 1; | |
991 | ||
992 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
993 | * be updated with the RXON_ASSOC command -- however only some | |
994 | * flag transitions are allowed using RXON_ASSOC */ | |
995 | ||
996 | /* Check if we are not switching bands */ | |
997 | if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) != | |
998 | (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)) | |
999 | return 1; | |
1000 | ||
1001 | /* Check if we are switching association toggle */ | |
1002 | if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) != | |
1003 | (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) | |
1004 | return 1; | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
bb8c093b | 1009 | static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv) |
b481de9c ZY |
1010 | { |
1011 | int rc = 0; | |
bb8c093b CH |
1012 | struct iwl3945_rx_packet *res = NULL; |
1013 | struct iwl3945_rxon_assoc_cmd rxon_assoc; | |
1014 | struct iwl3945_host_cmd cmd = { | |
b481de9c ZY |
1015 | .id = REPLY_RXON_ASSOC, |
1016 | .len = sizeof(rxon_assoc), | |
1017 | .meta.flags = CMD_WANT_SKB, | |
1018 | .data = &rxon_assoc, | |
1019 | }; | |
bb8c093b CH |
1020 | const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon; |
1021 | const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon; | |
b481de9c ZY |
1022 | |
1023 | if ((rxon1->flags == rxon2->flags) && | |
1024 | (rxon1->filter_flags == rxon2->filter_flags) && | |
1025 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
1026 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
1027 | IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); | |
1028 | return 0; | |
1029 | } | |
1030 | ||
1031 | rxon_assoc.flags = priv->staging_rxon.flags; | |
1032 | rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; | |
1033 | rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; | |
1034 | rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; | |
1035 | rxon_assoc.reserved = 0; | |
1036 | ||
bb8c093b | 1037 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
1038 | if (rc) |
1039 | return rc; | |
1040 | ||
bb8c093b | 1041 | res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1042 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1043 | IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n"); | |
1044 | rc = -EIO; | |
1045 | } | |
1046 | ||
1047 | priv->alloc_rxb_skb--; | |
1048 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1049 | ||
1050 | return rc; | |
1051 | } | |
1052 | ||
1053 | /** | |
bb8c093b | 1054 | * iwl3945_commit_rxon - commit staging_rxon to hardware |
b481de9c | 1055 | * |
01ebd063 | 1056 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
1057 | * the active_rxon structure is updated with the new data. This |
1058 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
1059 | * a HW tune is required based on the RXON structure changes. | |
1060 | */ | |
bb8c093b | 1061 | static int iwl3945_commit_rxon(struct iwl3945_priv *priv) |
b481de9c ZY |
1062 | { |
1063 | /* cast away the const for active_rxon in this function */ | |
bb8c093b | 1064 | struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
b481de9c | 1065 | int rc = 0; |
0795af57 | 1066 | DECLARE_MAC_BUF(mac); |
b481de9c | 1067 | |
bb8c093b | 1068 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
1069 | return -1; |
1070 | ||
1071 | /* always get timestamp with Rx frame */ | |
1072 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
1073 | ||
1074 | /* select antenna */ | |
1075 | priv->staging_rxon.flags &= | |
1076 | ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK); | |
1077 | priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv); | |
1078 | ||
bb8c093b | 1079 | rc = iwl3945_check_rxon_cmd(&priv->staging_rxon); |
b481de9c ZY |
1080 | if (rc) { |
1081 | IWL_ERROR("Invalid RXON configuration. Not committing.\n"); | |
1082 | return -EINVAL; | |
1083 | } | |
1084 | ||
1085 | /* If we don't need to send a full RXON, we can use | |
bb8c093b | 1086 | * iwl3945_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 1087 | * and other flags for the current radio configuration. */ |
bb8c093b CH |
1088 | if (!iwl3945_full_rxon_required(priv)) { |
1089 | rc = iwl3945_send_rxon_assoc(priv); | |
b481de9c ZY |
1090 | if (rc) { |
1091 | IWL_ERROR("Error setting RXON_ASSOC " | |
1092 | "configuration (%d).\n", rc); | |
1093 | return rc; | |
1094 | } | |
1095 | ||
1096 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | /* If we are currently associated and the new config requires | |
1102 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
1103 | * we must clear the associated from the active configuration | |
1104 | * before we apply the new config */ | |
bb8c093b | 1105 | if (iwl3945_is_associated(priv) && |
b481de9c ZY |
1106 | (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) { |
1107 | IWL_DEBUG_INFO("Toggling associated bit on current RXON\n"); | |
1108 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
1109 | ||
bb8c093b CH |
1110 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON, |
1111 | sizeof(struct iwl3945_rxon_cmd), | |
b481de9c ZY |
1112 | &priv->active_rxon); |
1113 | ||
1114 | /* If the mask clearing failed then we set | |
1115 | * active_rxon back to what it was previously */ | |
1116 | if (rc) { | |
1117 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; | |
1118 | IWL_ERROR("Error clearing ASSOC_MSK on current " | |
1119 | "configuration (%d).\n", rc); | |
1120 | return rc; | |
1121 | } | |
b481de9c ZY |
1122 | } |
1123 | ||
1124 | IWL_DEBUG_INFO("Sending RXON\n" | |
1125 | "* with%s RXON_FILTER_ASSOC_MSK\n" | |
1126 | "* channel = %d\n" | |
0795af57 | 1127 | "* bssid = %s\n", |
b481de9c ZY |
1128 | ((priv->staging_rxon.filter_flags & |
1129 | RXON_FILTER_ASSOC_MSK) ? "" : "out"), | |
1130 | le16_to_cpu(priv->staging_rxon.channel), | |
0795af57 | 1131 | print_mac(mac, priv->staging_rxon.bssid_addr)); |
b481de9c ZY |
1132 | |
1133 | /* Apply the new configuration */ | |
bb8c093b CH |
1134 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON, |
1135 | sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon); | |
b481de9c ZY |
1136 | if (rc) { |
1137 | IWL_ERROR("Error setting new configuration (%d).\n", rc); | |
1138 | return rc; | |
1139 | } | |
1140 | ||
1141 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
1142 | ||
bb8c093b | 1143 | iwl3945_clear_stations_table(priv); |
556f8db7 | 1144 | |
b481de9c ZY |
1145 | /* If we issue a new RXON command which required a tune then we must |
1146 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
bb8c093b | 1147 | rc = iwl3945_hw_reg_send_txpower(priv); |
b481de9c ZY |
1148 | if (rc) { |
1149 | IWL_ERROR("Error setting Tx power (%d).\n", rc); | |
1150 | return rc; | |
1151 | } | |
1152 | ||
1153 | /* Add the broadcast address so we can send broadcast frames */ | |
bb8c093b | 1154 | if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) == |
b481de9c ZY |
1155 | IWL_INVALID_STATION) { |
1156 | IWL_ERROR("Error adding BROADCAST address for transmit.\n"); | |
1157 | return -EIO; | |
1158 | } | |
1159 | ||
1160 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
1161 | * add the IWL_AP_ID to the station rate table */ | |
bb8c093b | 1162 | if (iwl3945_is_associated(priv) && |
05c914fe | 1163 | (priv->iw_mode == NL80211_IFTYPE_STATION)) |
bb8c093b | 1164 | if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0) |
b481de9c ZY |
1165 | == IWL_INVALID_STATION) { |
1166 | IWL_ERROR("Error adding AP address for transmit.\n"); | |
1167 | return -EIO; | |
1168 | } | |
1169 | ||
8318d78a | 1170 | /* Init the hardware's rate fallback order based on the band */ |
b481de9c ZY |
1171 | rc = iwl3945_init_hw_rate_table(priv); |
1172 | if (rc) { | |
1173 | IWL_ERROR("Error setting HW rate table: %02X\n", rc); | |
1174 | return -EIO; | |
1175 | } | |
1176 | ||
1177 | return 0; | |
1178 | } | |
1179 | ||
bb8c093b | 1180 | static int iwl3945_send_bt_config(struct iwl3945_priv *priv) |
b481de9c | 1181 | { |
bb8c093b | 1182 | struct iwl3945_bt_cmd bt_cmd = { |
b481de9c ZY |
1183 | .flags = 3, |
1184 | .lead_time = 0xAA, | |
1185 | .max_kill = 1, | |
1186 | .kill_ack_mask = 0, | |
1187 | .kill_cts_mask = 0, | |
1188 | }; | |
1189 | ||
bb8c093b CH |
1190 | return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG, |
1191 | sizeof(struct iwl3945_bt_cmd), &bt_cmd); | |
b481de9c ZY |
1192 | } |
1193 | ||
bb8c093b | 1194 | static int iwl3945_send_scan_abort(struct iwl3945_priv *priv) |
b481de9c ZY |
1195 | { |
1196 | int rc = 0; | |
bb8c093b CH |
1197 | struct iwl3945_rx_packet *res; |
1198 | struct iwl3945_host_cmd cmd = { | |
b481de9c ZY |
1199 | .id = REPLY_SCAN_ABORT_CMD, |
1200 | .meta.flags = CMD_WANT_SKB, | |
1201 | }; | |
1202 | ||
1203 | /* If there isn't a scan actively going on in the hardware | |
1204 | * then we are in between scan bands and not actually | |
1205 | * actively scanning, so don't send the abort command */ | |
1206 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
1207 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1208 | return 0; | |
1209 | } | |
1210 | ||
bb8c093b | 1211 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
1212 | if (rc) { |
1213 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1214 | return rc; | |
1215 | } | |
1216 | ||
bb8c093b | 1217 | res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1218 | if (res->u.status != CAN_ABORT_STATUS) { |
1219 | /* The scan abort will return 1 for success or | |
1220 | * 2 for "failure". A failure condition can be | |
1221 | * due to simply not being in an active scan which | |
1222 | * can occur if we send the scan abort before we | |
1223 | * the microcode has notified us that a scan is | |
1224 | * completed. */ | |
1225 | IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status); | |
1226 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1227 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
1228 | } | |
1229 | ||
1230 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1231 | ||
1232 | return rc; | |
1233 | } | |
1234 | ||
bb8c093b CH |
1235 | static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv, |
1236 | struct iwl3945_cmd *cmd, | |
b481de9c ZY |
1237 | struct sk_buff *skb) |
1238 | { | |
1239 | return 1; | |
1240 | } | |
1241 | ||
1242 | /* | |
1243 | * CARD_STATE_CMD | |
1244 | * | |
9fbab516 | 1245 | * Use: Sets the device's internal card state to enable, disable, or halt |
b481de9c ZY |
1246 | * |
1247 | * When in the 'enable' state the card operates as normal. | |
1248 | * When in the 'disable' state, the card enters into a low power mode. | |
1249 | * When in the 'halt' state, the card is shut down and must be fully | |
1250 | * restarted to come back on. | |
1251 | */ | |
bb8c093b | 1252 | static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag) |
b481de9c | 1253 | { |
bb8c093b | 1254 | struct iwl3945_host_cmd cmd = { |
b481de9c ZY |
1255 | .id = REPLY_CARD_STATE_CMD, |
1256 | .len = sizeof(u32), | |
1257 | .data = &flags, | |
1258 | .meta.flags = meta_flag, | |
1259 | }; | |
1260 | ||
1261 | if (meta_flag & CMD_ASYNC) | |
bb8c093b | 1262 | cmd.meta.u.callback = iwl3945_card_state_sync_callback; |
b481de9c | 1263 | |
bb8c093b | 1264 | return iwl3945_send_cmd(priv, &cmd); |
b481de9c ZY |
1265 | } |
1266 | ||
bb8c093b CH |
1267 | static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv, |
1268 | struct iwl3945_cmd *cmd, struct sk_buff *skb) | |
b481de9c | 1269 | { |
bb8c093b | 1270 | struct iwl3945_rx_packet *res = NULL; |
b481de9c ZY |
1271 | |
1272 | if (!skb) { | |
1273 | IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n"); | |
1274 | return 1; | |
1275 | } | |
1276 | ||
bb8c093b | 1277 | res = (struct iwl3945_rx_packet *)skb->data; |
b481de9c ZY |
1278 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1279 | IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n", | |
1280 | res->hdr.flags); | |
1281 | return 1; | |
1282 | } | |
1283 | ||
1284 | switch (res->u.add_sta.status) { | |
1285 | case ADD_STA_SUCCESS_MSK: | |
1286 | break; | |
1287 | default: | |
1288 | break; | |
1289 | } | |
1290 | ||
1291 | /* We didn't cache the SKB; let the caller free it */ | |
1292 | return 1; | |
1293 | } | |
1294 | ||
bb8c093b CH |
1295 | int iwl3945_send_add_station(struct iwl3945_priv *priv, |
1296 | struct iwl3945_addsta_cmd *sta, u8 flags) | |
b481de9c | 1297 | { |
bb8c093b | 1298 | struct iwl3945_rx_packet *res = NULL; |
b481de9c | 1299 | int rc = 0; |
bb8c093b | 1300 | struct iwl3945_host_cmd cmd = { |
b481de9c | 1301 | .id = REPLY_ADD_STA, |
bb8c093b | 1302 | .len = sizeof(struct iwl3945_addsta_cmd), |
b481de9c ZY |
1303 | .meta.flags = flags, |
1304 | .data = sta, | |
1305 | }; | |
1306 | ||
1307 | if (flags & CMD_ASYNC) | |
bb8c093b | 1308 | cmd.meta.u.callback = iwl3945_add_sta_sync_callback; |
b481de9c ZY |
1309 | else |
1310 | cmd.meta.flags |= CMD_WANT_SKB; | |
1311 | ||
bb8c093b | 1312 | rc = iwl3945_send_cmd(priv, &cmd); |
b481de9c ZY |
1313 | |
1314 | if (rc || (flags & CMD_ASYNC)) | |
1315 | return rc; | |
1316 | ||
bb8c093b | 1317 | res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1318 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1319 | IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n", | |
1320 | res->hdr.flags); | |
1321 | rc = -EIO; | |
1322 | } | |
1323 | ||
1324 | if (rc == 0) { | |
1325 | switch (res->u.add_sta.status) { | |
1326 | case ADD_STA_SUCCESS_MSK: | |
1327 | IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n"); | |
1328 | break; | |
1329 | default: | |
1330 | rc = -EIO; | |
1331 | IWL_WARNING("REPLY_ADD_STA failed\n"); | |
1332 | break; | |
1333 | } | |
1334 | } | |
1335 | ||
1336 | priv->alloc_rxb_skb--; | |
1337 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1338 | ||
1339 | return rc; | |
1340 | } | |
1341 | ||
bb8c093b | 1342 | static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv, |
b481de9c ZY |
1343 | struct ieee80211_key_conf *keyconf, |
1344 | u8 sta_id) | |
1345 | { | |
1346 | unsigned long flags; | |
1347 | __le16 key_flags = 0; | |
1348 | ||
1349 | switch (keyconf->alg) { | |
1350 | case ALG_CCMP: | |
1351 | key_flags |= STA_KEY_FLG_CCMP; | |
1352 | key_flags |= cpu_to_le16( | |
1353 | keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
1354 | key_flags &= ~STA_KEY_FLG_INVALID; | |
1355 | break; | |
1356 | case ALG_TKIP: | |
1357 | case ALG_WEP: | |
b481de9c ZY |
1358 | default: |
1359 | return -EINVAL; | |
1360 | } | |
1361 | spin_lock_irqsave(&priv->sta_lock, flags); | |
1362 | priv->stations[sta_id].keyinfo.alg = keyconf->alg; | |
1363 | priv->stations[sta_id].keyinfo.keylen = keyconf->keylen; | |
1364 | memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, | |
1365 | keyconf->keylen); | |
1366 | ||
1367 | memcpy(priv->stations[sta_id].sta.key.key, keyconf->key, | |
1368 | keyconf->keylen); | |
1369 | priv->stations[sta_id].sta.key.key_flags = key_flags; | |
1370 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
1371 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
1372 | ||
1373 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1374 | ||
1375 | IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n"); | |
bb8c093b | 1376 | iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0); |
b481de9c ZY |
1377 | return 0; |
1378 | } | |
1379 | ||
bb8c093b | 1380 | static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id) |
b481de9c ZY |
1381 | { |
1382 | unsigned long flags; | |
1383 | ||
1384 | spin_lock_irqsave(&priv->sta_lock, flags); | |
bb8c093b CH |
1385 | memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key)); |
1386 | memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo)); | |
b481de9c ZY |
1387 | priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC; |
1388 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
1389 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
1390 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1391 | ||
1392 | IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n"); | |
bb8c093b | 1393 | iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0); |
b481de9c ZY |
1394 | return 0; |
1395 | } | |
1396 | ||
bb8c093b | 1397 | static void iwl3945_clear_free_frames(struct iwl3945_priv *priv) |
b481de9c ZY |
1398 | { |
1399 | struct list_head *element; | |
1400 | ||
1401 | IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n", | |
1402 | priv->frames_count); | |
1403 | ||
1404 | while (!list_empty(&priv->free_frames)) { | |
1405 | element = priv->free_frames.next; | |
1406 | list_del(element); | |
bb8c093b | 1407 | kfree(list_entry(element, struct iwl3945_frame, list)); |
b481de9c ZY |
1408 | priv->frames_count--; |
1409 | } | |
1410 | ||
1411 | if (priv->frames_count) { | |
1412 | IWL_WARNING("%d frames still in use. Did we lose one?\n", | |
1413 | priv->frames_count); | |
1414 | priv->frames_count = 0; | |
1415 | } | |
1416 | } | |
1417 | ||
bb8c093b | 1418 | static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv) |
b481de9c | 1419 | { |
bb8c093b | 1420 | struct iwl3945_frame *frame; |
b481de9c ZY |
1421 | struct list_head *element; |
1422 | if (list_empty(&priv->free_frames)) { | |
1423 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
1424 | if (!frame) { | |
1425 | IWL_ERROR("Could not allocate frame!\n"); | |
1426 | return NULL; | |
1427 | } | |
1428 | ||
1429 | priv->frames_count++; | |
1430 | return frame; | |
1431 | } | |
1432 | ||
1433 | element = priv->free_frames.next; | |
1434 | list_del(element); | |
bb8c093b | 1435 | return list_entry(element, struct iwl3945_frame, list); |
b481de9c ZY |
1436 | } |
1437 | ||
bb8c093b | 1438 | static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame) |
b481de9c ZY |
1439 | { |
1440 | memset(frame, 0, sizeof(*frame)); | |
1441 | list_add(&frame->list, &priv->free_frames); | |
1442 | } | |
1443 | ||
bb8c093b | 1444 | unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv, |
b481de9c ZY |
1445 | struct ieee80211_hdr *hdr, |
1446 | const u8 *dest, int left) | |
1447 | { | |
1448 | ||
bb8c093b | 1449 | if (!iwl3945_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
1450 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
1451 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
1452 | return 0; |
1453 | ||
1454 | if (priv->ibss_beacon->len > left) | |
1455 | return 0; | |
1456 | ||
1457 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
1458 | ||
1459 | return priv->ibss_beacon->len; | |
1460 | } | |
1461 | ||
bb8c093b | 1462 | static u8 iwl3945_rate_get_lowest_plcp(int rate_mask) |
b481de9c ZY |
1463 | { |
1464 | u8 i; | |
1465 | ||
1466 | for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID; | |
bb8c093b | 1467 | i = iwl3945_rates[i].next_ieee) { |
b481de9c | 1468 | if (rate_mask & (1 << i)) |
bb8c093b | 1469 | return iwl3945_rates[i].plcp; |
b481de9c ZY |
1470 | } |
1471 | ||
1472 | return IWL_RATE_INVALID; | |
1473 | } | |
1474 | ||
bb8c093b | 1475 | static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv) |
b481de9c | 1476 | { |
bb8c093b | 1477 | struct iwl3945_frame *frame; |
b481de9c ZY |
1478 | unsigned int frame_size; |
1479 | int rc; | |
1480 | u8 rate; | |
1481 | ||
bb8c093b | 1482 | frame = iwl3945_get_free_frame(priv); |
b481de9c ZY |
1483 | |
1484 | if (!frame) { | |
1485 | IWL_ERROR("Could not obtain free frame buffer for beacon " | |
1486 | "command.\n"); | |
1487 | return -ENOMEM; | |
1488 | } | |
1489 | ||
1490 | if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) { | |
bb8c093b | 1491 | rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & |
b481de9c ZY |
1492 | 0xFF0); |
1493 | if (rate == IWL_INVALID_RATE) | |
1494 | rate = IWL_RATE_6M_PLCP; | |
1495 | } else { | |
bb8c093b | 1496 | rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF); |
b481de9c ZY |
1497 | if (rate == IWL_INVALID_RATE) |
1498 | rate = IWL_RATE_1M_PLCP; | |
1499 | } | |
1500 | ||
bb8c093b | 1501 | frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 1502 | |
bb8c093b | 1503 | rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
1504 | &frame->u.cmd[0]); |
1505 | ||
bb8c093b | 1506 | iwl3945_free_frame(priv, frame); |
b481de9c ZY |
1507 | |
1508 | return rc; | |
1509 | } | |
1510 | ||
1511 | /****************************************************************************** | |
1512 | * | |
1513 | * EEPROM related functions | |
1514 | * | |
1515 | ******************************************************************************/ | |
1516 | ||
bb8c093b | 1517 | static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac) |
b481de9c ZY |
1518 | { |
1519 | memcpy(mac, priv->eeprom.mac_address, 6); | |
1520 | } | |
1521 | ||
74a3a250 RC |
1522 | /* |
1523 | * Clear the OWNER_MSK, to establish driver (instead of uCode running on | |
1524 | * embedded controller) as EEPROM reader; each read is a series of pulses | |
1525 | * to/from the EEPROM chip, not a single event, so even reads could conflict | |
1526 | * if they weren't arbitrated by some ownership mechanism. Here, the driver | |
1527 | * simply claims ownership, which should be safe when this function is called | |
1528 | * (i.e. before loading uCode!). | |
1529 | */ | |
1530 | static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv) | |
1531 | { | |
1532 | _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK); | |
1533 | return 0; | |
1534 | } | |
1535 | ||
b481de9c | 1536 | /** |
bb8c093b | 1537 | * iwl3945_eeprom_init - read EEPROM contents |
b481de9c | 1538 | * |
6440adb5 | 1539 | * Load the EEPROM contents from adapter into priv->eeprom |
b481de9c ZY |
1540 | * |
1541 | * NOTE: This routine uses the non-debug IO access functions. | |
1542 | */ | |
bb8c093b | 1543 | int iwl3945_eeprom_init(struct iwl3945_priv *priv) |
b481de9c | 1544 | { |
58ff6d4d | 1545 | u16 *e = (u16 *)&priv->eeprom; |
bb8c093b | 1546 | u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP); |
b481de9c ZY |
1547 | u32 r; |
1548 | int sz = sizeof(priv->eeprom); | |
1549 | int rc; | |
1550 | int i; | |
1551 | u16 addr; | |
1552 | ||
1553 | /* The EEPROM structure has several padding buffers within it | |
1554 | * and when adding new EEPROM maps is subject to programmer errors | |
1555 | * which may be very difficult to identify without explicitly | |
1556 | * checking the resulting size of the eeprom map. */ | |
1557 | BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE); | |
1558 | ||
1559 | if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) { | |
6f147926 | 1560 | IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp); |
b481de9c ZY |
1561 | return -ENOENT; |
1562 | } | |
1563 | ||
6440adb5 | 1564 | /* Make sure driver (instead of uCode) is allowed to read EEPROM */ |
bb8c093b | 1565 | rc = iwl3945_eeprom_acquire_semaphore(priv); |
b481de9c | 1566 | if (rc < 0) { |
91e17473 | 1567 | IWL_ERROR("Failed to acquire EEPROM semaphore.\n"); |
b481de9c ZY |
1568 | return -ENOENT; |
1569 | } | |
1570 | ||
1571 | /* eeprom is an array of 16bit values */ | |
1572 | for (addr = 0; addr < sz; addr += sizeof(u16)) { | |
bb8c093b CH |
1573 | _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1); |
1574 | _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD); | |
b481de9c ZY |
1575 | |
1576 | for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT; | |
1577 | i += IWL_EEPROM_ACCESS_DELAY) { | |
bb8c093b | 1578 | r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG); |
b481de9c ZY |
1579 | if (r & CSR_EEPROM_REG_READ_VALID_MSK) |
1580 | break; | |
1581 | udelay(IWL_EEPROM_ACCESS_DELAY); | |
1582 | } | |
1583 | ||
1584 | if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) { | |
6f147926 | 1585 | IWL_ERROR("Time out reading EEPROM[%d]\n", addr); |
b481de9c ZY |
1586 | return -ETIMEDOUT; |
1587 | } | |
58ff6d4d | 1588 | e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16)); |
b481de9c ZY |
1589 | } |
1590 | ||
1591 | return 0; | |
1592 | } | |
1593 | ||
bb8c093b | 1594 | static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv) |
b481de9c ZY |
1595 | { |
1596 | if (priv->hw_setting.shared_virt) | |
1597 | pci_free_consistent(priv->pci_dev, | |
bb8c093b | 1598 | sizeof(struct iwl3945_shared), |
b481de9c ZY |
1599 | priv->hw_setting.shared_virt, |
1600 | priv->hw_setting.shared_phys); | |
1601 | } | |
1602 | ||
1603 | /** | |
bb8c093b | 1604 | * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field |
b481de9c ZY |
1605 | * |
1606 | * return : set the bit for each supported rate insert in ie | |
1607 | */ | |
bb8c093b | 1608 | static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate, |
c7c46676 | 1609 | u16 basic_rate, int *left) |
b481de9c ZY |
1610 | { |
1611 | u16 ret_rates = 0, bit; | |
1612 | int i; | |
c7c46676 TW |
1613 | u8 *cnt = ie; |
1614 | u8 *rates = ie + 1; | |
b481de9c ZY |
1615 | |
1616 | for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) { | |
1617 | if (bit & supported_rate) { | |
1618 | ret_rates |= bit; | |
bb8c093b | 1619 | rates[*cnt] = iwl3945_rates[i].ieee | |
c7c46676 TW |
1620 | ((bit & basic_rate) ? 0x80 : 0x00); |
1621 | (*cnt)++; | |
1622 | (*left)--; | |
1623 | if ((*left <= 0) || | |
1624 | (*cnt >= IWL_SUPPORTED_RATES_IE_LEN)) | |
b481de9c ZY |
1625 | break; |
1626 | } | |
1627 | } | |
1628 | ||
1629 | return ret_rates; | |
1630 | } | |
1631 | ||
1632 | /** | |
bb8c093b | 1633 | * iwl3945_fill_probe_req - fill in all required fields and IE for probe request |
b481de9c | 1634 | */ |
bb8c093b | 1635 | static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv, |
b481de9c ZY |
1636 | struct ieee80211_mgmt *frame, |
1637 | int left, int is_direct) | |
1638 | { | |
1639 | int len = 0; | |
1640 | u8 *pos = NULL; | |
c7c46676 | 1641 | u16 active_rates, ret_rates, cck_rates; |
b481de9c ZY |
1642 | |
1643 | /* Make sure there is enough space for the probe request, | |
1644 | * two mandatory IEs and the data */ | |
1645 | left -= 24; | |
1646 | if (left < 0) | |
1647 | return 0; | |
1648 | len += 24; | |
1649 | ||
1650 | frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ); | |
bb8c093b | 1651 | memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN); |
b481de9c | 1652 | memcpy(frame->sa, priv->mac_addr, ETH_ALEN); |
bb8c093b | 1653 | memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN); |
b481de9c ZY |
1654 | frame->seq_ctrl = 0; |
1655 | ||
1656 | /* fill in our indirect SSID IE */ | |
1657 | /* ...next IE... */ | |
1658 | ||
1659 | left -= 2; | |
1660 | if (left < 0) | |
1661 | return 0; | |
1662 | len += 2; | |
1663 | pos = &(frame->u.probe_req.variable[0]); | |
1664 | *pos++ = WLAN_EID_SSID; | |
1665 | *pos++ = 0; | |
1666 | ||
1667 | /* fill in our direct SSID IE... */ | |
1668 | if (is_direct) { | |
1669 | /* ...next IE... */ | |
1670 | left -= 2 + priv->essid_len; | |
1671 | if (left < 0) | |
1672 | return 0; | |
1673 | /* ... fill it in... */ | |
1674 | *pos++ = WLAN_EID_SSID; | |
1675 | *pos++ = priv->essid_len; | |
1676 | memcpy(pos, priv->essid, priv->essid_len); | |
1677 | pos += priv->essid_len; | |
1678 | len += 2 + priv->essid_len; | |
1679 | } | |
1680 | ||
1681 | /* fill in supported rate */ | |
1682 | /* ...next IE... */ | |
1683 | left -= 2; | |
1684 | if (left < 0) | |
1685 | return 0; | |
c7c46676 | 1686 | |
b481de9c ZY |
1687 | /* ... fill it in... */ |
1688 | *pos++ = WLAN_EID_SUPP_RATES; | |
1689 | *pos = 0; | |
c7c46676 TW |
1690 | |
1691 | priv->active_rate = priv->rates_mask; | |
1692 | active_rates = priv->active_rate; | |
b481de9c ZY |
1693 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; |
1694 | ||
c7c46676 | 1695 | cck_rates = IWL_CCK_RATES_MASK & active_rates; |
bb8c093b | 1696 | ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates, |
c7c46676 TW |
1697 | priv->active_rate_basic, &left); |
1698 | active_rates &= ~ret_rates; | |
1699 | ||
bb8c093b | 1700 | ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates, |
c7c46676 TW |
1701 | priv->active_rate_basic, &left); |
1702 | active_rates &= ~ret_rates; | |
1703 | ||
b481de9c ZY |
1704 | len += 2 + *pos; |
1705 | pos += (*pos) + 1; | |
c7c46676 | 1706 | if (active_rates == 0) |
b481de9c ZY |
1707 | goto fill_end; |
1708 | ||
1709 | /* fill in supported extended rate */ | |
1710 | /* ...next IE... */ | |
1711 | left -= 2; | |
1712 | if (left < 0) | |
1713 | return 0; | |
1714 | /* ... fill it in... */ | |
1715 | *pos++ = WLAN_EID_EXT_SUPP_RATES; | |
1716 | *pos = 0; | |
bb8c093b | 1717 | iwl3945_supported_rate_to_ie(pos, active_rates, |
c7c46676 | 1718 | priv->active_rate_basic, &left); |
b481de9c ZY |
1719 | if (*pos > 0) |
1720 | len += 2 + *pos; | |
1721 | ||
1722 | fill_end: | |
1723 | return (u16)len; | |
1724 | } | |
1725 | ||
1726 | /* | |
1727 | * QoS support | |
1728 | */ | |
bb8c093b CH |
1729 | static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv, |
1730 | struct iwl3945_qosparam_cmd *qos) | |
b481de9c ZY |
1731 | { |
1732 | ||
bb8c093b CH |
1733 | return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM, |
1734 | sizeof(struct iwl3945_qosparam_cmd), qos); | |
b481de9c ZY |
1735 | } |
1736 | ||
bb8c093b | 1737 | static void iwl3945_reset_qos(struct iwl3945_priv *priv) |
b481de9c ZY |
1738 | { |
1739 | u16 cw_min = 15; | |
1740 | u16 cw_max = 1023; | |
1741 | u8 aifs = 2; | |
1742 | u8 is_legacy = 0; | |
1743 | unsigned long flags; | |
1744 | int i; | |
1745 | ||
1746 | spin_lock_irqsave(&priv->lock, flags); | |
1747 | priv->qos_data.qos_active = 0; | |
1748 | ||
05c914fe | 1749 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) { |
b481de9c ZY |
1750 | if (priv->qos_data.qos_enable) |
1751 | priv->qos_data.qos_active = 1; | |
1752 | if (!(priv->active_rate & 0xfff0)) { | |
1753 | cw_min = 31; | |
1754 | is_legacy = 1; | |
1755 | } | |
05c914fe | 1756 | } else if (priv->iw_mode == NL80211_IFTYPE_AP) { |
b481de9c ZY |
1757 | if (priv->qos_data.qos_enable) |
1758 | priv->qos_data.qos_active = 1; | |
1759 | } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) { | |
1760 | cw_min = 31; | |
1761 | is_legacy = 1; | |
1762 | } | |
1763 | ||
1764 | if (priv->qos_data.qos_active) | |
1765 | aifs = 3; | |
1766 | ||
1767 | priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min); | |
1768 | priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max); | |
1769 | priv->qos_data.def_qos_parm.ac[0].aifsn = aifs; | |
1770 | priv->qos_data.def_qos_parm.ac[0].edca_txop = 0; | |
1771 | priv->qos_data.def_qos_parm.ac[0].reserved1 = 0; | |
1772 | ||
1773 | if (priv->qos_data.qos_active) { | |
1774 | i = 1; | |
1775 | priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min); | |
1776 | priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max); | |
1777 | priv->qos_data.def_qos_parm.ac[i].aifsn = 7; | |
1778 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
1779 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1780 | ||
1781 | i = 2; | |
1782 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
1783 | cpu_to_le16((cw_min + 1) / 2 - 1); | |
1784 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
1785 | cpu_to_le16(cw_max); | |
1786 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; | |
1787 | if (is_legacy) | |
1788 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1789 | cpu_to_le16(6016); | |
1790 | else | |
1791 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1792 | cpu_to_le16(3008); | |
1793 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1794 | ||
1795 | i = 3; | |
1796 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
1797 | cpu_to_le16((cw_min + 1) / 4 - 1); | |
1798 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
1799 | cpu_to_le16((cw_max + 1) / 2 - 1); | |
1800 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; | |
1801 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1802 | if (is_legacy) | |
1803 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1804 | cpu_to_le16(3264); | |
1805 | else | |
1806 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1807 | cpu_to_le16(1504); | |
1808 | } else { | |
1809 | for (i = 1; i < 4; i++) { | |
1810 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
1811 | cpu_to_le16(cw_min); | |
1812 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
1813 | cpu_to_le16(cw_max); | |
1814 | priv->qos_data.def_qos_parm.ac[i].aifsn = aifs; | |
1815 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
1816 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1817 | } | |
1818 | } | |
1819 | IWL_DEBUG_QOS("set QoS to default \n"); | |
1820 | ||
1821 | spin_unlock_irqrestore(&priv->lock, flags); | |
1822 | } | |
1823 | ||
bb8c093b | 1824 | static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force) |
b481de9c ZY |
1825 | { |
1826 | unsigned long flags; | |
1827 | ||
b481de9c ZY |
1828 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
1829 | return; | |
1830 | ||
1831 | if (!priv->qos_data.qos_enable) | |
1832 | return; | |
1833 | ||
1834 | spin_lock_irqsave(&priv->lock, flags); | |
1835 | priv->qos_data.def_qos_parm.qos_flags = 0; | |
1836 | ||
1837 | if (priv->qos_data.qos_cap.q_AP.queue_request && | |
1838 | !priv->qos_data.qos_cap.q_AP.txop_request) | |
1839 | priv->qos_data.def_qos_parm.qos_flags |= | |
1840 | QOS_PARAM_FLG_TXOP_TYPE_MSK; | |
1841 | ||
1842 | if (priv->qos_data.qos_active) | |
1843 | priv->qos_data.def_qos_parm.qos_flags |= | |
1844 | QOS_PARAM_FLG_UPDATE_EDCA_MSK; | |
1845 | ||
1846 | spin_unlock_irqrestore(&priv->lock, flags); | |
1847 | ||
bb8c093b | 1848 | if (force || iwl3945_is_associated(priv)) { |
b481de9c ZY |
1849 | IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n", |
1850 | priv->qos_data.qos_active); | |
1851 | ||
bb8c093b | 1852 | iwl3945_send_qos_params_command(priv, |
b481de9c ZY |
1853 | &(priv->qos_data.def_qos_parm)); |
1854 | } | |
1855 | } | |
1856 | ||
b481de9c ZY |
1857 | /* |
1858 | * Power management (not Tx power!) functions | |
1859 | */ | |
1860 | #define MSEC_TO_USEC 1024 | |
1861 | ||
1862 | #define NOSLP __constant_cpu_to_le32(0) | |
1863 | #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK | |
1864 | #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC) | |
1865 | #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \ | |
1866 | __constant_cpu_to_le32(X1), \ | |
1867 | __constant_cpu_to_le32(X2), \ | |
1868 | __constant_cpu_to_le32(X3), \ | |
1869 | __constant_cpu_to_le32(X4)} | |
1870 | ||
1871 | ||
1872 | /* default power management (not Tx power) table values */ | |
1873 | /* for tim 0-10 */ | |
bb8c093b | 1874 | static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = { |
b481de9c ZY |
1875 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1876 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0}, | |
1877 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0}, | |
1878 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0}, | |
1879 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1}, | |
1880 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1} | |
1881 | }; | |
1882 | ||
1883 | /* for tim > 10 */ | |
bb8c093b | 1884 | static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = { |
b481de9c ZY |
1885 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1886 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), | |
1887 | SLP_VEC(1, 2, 3, 4, 0xFF)}, 0}, | |
1888 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), | |
1889 | SLP_VEC(2, 4, 6, 7, 0xFF)}, 0}, | |
1890 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), | |
1891 | SLP_VEC(2, 6, 9, 9, 0xFF)}, 0}, | |
1892 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0}, | |
1893 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), | |
1894 | SLP_VEC(4, 7, 10, 10, 0xFF)}, 0} | |
1895 | }; | |
1896 | ||
bb8c093b | 1897 | int iwl3945_power_init_handle(struct iwl3945_priv *priv) |
b481de9c ZY |
1898 | { |
1899 | int rc = 0, i; | |
bb8c093b CH |
1900 | struct iwl3945_power_mgr *pow_data; |
1901 | int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC; | |
b481de9c ZY |
1902 | u16 pci_pm; |
1903 | ||
1904 | IWL_DEBUG_POWER("Initialize power \n"); | |
1905 | ||
1906 | pow_data = &(priv->power_data); | |
1907 | ||
1908 | memset(pow_data, 0, sizeof(*pow_data)); | |
1909 | ||
1910 | pow_data->active_index = IWL_POWER_RANGE_0; | |
1911 | pow_data->dtim_val = 0xffff; | |
1912 | ||
1913 | memcpy(&pow_data->pwr_range_0[0], &range_0[0], size); | |
1914 | memcpy(&pow_data->pwr_range_1[0], &range_1[0], size); | |
1915 | ||
1916 | rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm); | |
1917 | if (rc != 0) | |
1918 | return 0; | |
1919 | else { | |
bb8c093b | 1920 | struct iwl3945_powertable_cmd *cmd; |
b481de9c ZY |
1921 | |
1922 | IWL_DEBUG_POWER("adjust power command flags\n"); | |
1923 | ||
1924 | for (i = 0; i < IWL_POWER_AC; i++) { | |
1925 | cmd = &pow_data->pwr_range_0[i].cmd; | |
1926 | ||
1927 | if (pci_pm & 0x1) | |
1928 | cmd->flags &= ~IWL_POWER_PCI_PM_MSK; | |
1929 | else | |
1930 | cmd->flags |= IWL_POWER_PCI_PM_MSK; | |
1931 | } | |
1932 | } | |
1933 | return rc; | |
1934 | } | |
1935 | ||
bb8c093b CH |
1936 | static int iwl3945_update_power_cmd(struct iwl3945_priv *priv, |
1937 | struct iwl3945_powertable_cmd *cmd, u32 mode) | |
b481de9c ZY |
1938 | { |
1939 | int rc = 0, i; | |
1940 | u8 skip; | |
1941 | u32 max_sleep = 0; | |
bb8c093b | 1942 | struct iwl3945_power_vec_entry *range; |
b481de9c | 1943 | u8 period = 0; |
bb8c093b | 1944 | struct iwl3945_power_mgr *pow_data; |
b481de9c ZY |
1945 | |
1946 | if (mode > IWL_POWER_INDEX_5) { | |
1947 | IWL_DEBUG_POWER("Error invalid power mode \n"); | |
1948 | return -1; | |
1949 | } | |
1950 | pow_data = &(priv->power_data); | |
1951 | ||
1952 | if (pow_data->active_index == IWL_POWER_RANGE_0) | |
1953 | range = &pow_data->pwr_range_0[0]; | |
1954 | else | |
1955 | range = &pow_data->pwr_range_1[1]; | |
1956 | ||
bb8c093b | 1957 | memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd)); |
b481de9c ZY |
1958 | |
1959 | #ifdef IWL_MAC80211_DISABLE | |
1960 | if (priv->assoc_network != NULL) { | |
1961 | unsigned long flags; | |
1962 | ||
1963 | period = priv->assoc_network->tim.tim_period; | |
1964 | } | |
1965 | #endif /*IWL_MAC80211_DISABLE */ | |
1966 | skip = range[mode].no_dtim; | |
1967 | ||
1968 | if (period == 0) { | |
1969 | period = 1; | |
1970 | skip = 0; | |
1971 | } | |
1972 | ||
1973 | if (skip == 0) { | |
1974 | max_sleep = period; | |
1975 | cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
1976 | } else { | |
1977 | __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]; | |
1978 | max_sleep = (le32_to_cpu(slp_itrvl) / period) * period; | |
1979 | cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
1980 | } | |
1981 | ||
1982 | for (i = 0; i < IWL_POWER_VEC_SIZE; i++) { | |
1983 | if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep) | |
1984 | cmd->sleep_interval[i] = cpu_to_le32(max_sleep); | |
1985 | } | |
1986 | ||
1987 | IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags); | |
1988 | IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout)); | |
1989 | IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout)); | |
1990 | IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n", | |
1991 | le32_to_cpu(cmd->sleep_interval[0]), | |
1992 | le32_to_cpu(cmd->sleep_interval[1]), | |
1993 | le32_to_cpu(cmd->sleep_interval[2]), | |
1994 | le32_to_cpu(cmd->sleep_interval[3]), | |
1995 | le32_to_cpu(cmd->sleep_interval[4])); | |
1996 | ||
1997 | return rc; | |
1998 | } | |
1999 | ||
bb8c093b | 2000 | static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode) |
b481de9c | 2001 | { |
9a62f73b | 2002 | u32 uninitialized_var(final_mode); |
b481de9c | 2003 | int rc; |
bb8c093b | 2004 | struct iwl3945_powertable_cmd cmd; |
b481de9c ZY |
2005 | |
2006 | /* If on battery, set to 3, | |
01ebd063 | 2007 | * if plugged into AC power, set to CAM ("continuously aware mode"), |
b481de9c ZY |
2008 | * else user level */ |
2009 | switch (mode) { | |
2010 | case IWL_POWER_BATTERY: | |
2011 | final_mode = IWL_POWER_INDEX_3; | |
2012 | break; | |
2013 | case IWL_POWER_AC: | |
2014 | final_mode = IWL_POWER_MODE_CAM; | |
2015 | break; | |
2016 | default: | |
2017 | final_mode = mode; | |
2018 | break; | |
2019 | } | |
2020 | ||
bb8c093b | 2021 | iwl3945_update_power_cmd(priv, &cmd, final_mode); |
b481de9c | 2022 | |
bb8c093b | 2023 | rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd); |
b481de9c ZY |
2024 | |
2025 | if (final_mode == IWL_POWER_MODE_CAM) | |
2026 | clear_bit(STATUS_POWER_PMI, &priv->status); | |
2027 | else | |
2028 | set_bit(STATUS_POWER_PMI, &priv->status); | |
2029 | ||
2030 | return rc; | |
2031 | } | |
2032 | ||
b481de9c | 2033 | /** |
bb8c093b | 2034 | * iwl3945_scan_cancel - Cancel any currently executing HW scan |
b481de9c ZY |
2035 | * |
2036 | * NOTE: priv->mutex is not required before calling this function | |
2037 | */ | |
bb8c093b | 2038 | static int iwl3945_scan_cancel(struct iwl3945_priv *priv) |
b481de9c ZY |
2039 | { |
2040 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
2041 | clear_bit(STATUS_SCANNING, &priv->status); | |
2042 | return 0; | |
2043 | } | |
2044 | ||
2045 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
2046 | if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
2047 | IWL_DEBUG_SCAN("Queuing scan abort.\n"); | |
2048 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
2049 | queue_work(priv->workqueue, &priv->abort_scan); | |
2050 | ||
2051 | } else | |
2052 | IWL_DEBUG_SCAN("Scan abort already in progress.\n"); | |
2053 | ||
2054 | return test_bit(STATUS_SCANNING, &priv->status); | |
2055 | } | |
2056 | ||
2057 | return 0; | |
2058 | } | |
2059 | ||
2060 | /** | |
bb8c093b | 2061 | * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan |
b481de9c ZY |
2062 | * @ms: amount of time to wait (in milliseconds) for scan to abort |
2063 | * | |
2064 | * NOTE: priv->mutex must be held before calling this function | |
2065 | */ | |
bb8c093b | 2066 | static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms) |
b481de9c ZY |
2067 | { |
2068 | unsigned long now = jiffies; | |
2069 | int ret; | |
2070 | ||
bb8c093b | 2071 | ret = iwl3945_scan_cancel(priv); |
b481de9c ZY |
2072 | if (ret && ms) { |
2073 | mutex_unlock(&priv->mutex); | |
2074 | while (!time_after(jiffies, now + msecs_to_jiffies(ms)) && | |
2075 | test_bit(STATUS_SCANNING, &priv->status)) | |
2076 | msleep(1); | |
2077 | mutex_lock(&priv->mutex); | |
2078 | ||
2079 | return test_bit(STATUS_SCANNING, &priv->status); | |
2080 | } | |
2081 | ||
2082 | return ret; | |
2083 | } | |
2084 | ||
b481de9c ZY |
2085 | #define MAX_UCODE_BEACON_INTERVAL 1024 |
2086 | #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA) | |
2087 | ||
bb8c093b | 2088 | static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val) |
b481de9c ZY |
2089 | { |
2090 | u16 new_val = 0; | |
2091 | u16 beacon_factor = 0; | |
2092 | ||
2093 | beacon_factor = | |
2094 | (beacon_val + MAX_UCODE_BEACON_INTERVAL) | |
2095 | / MAX_UCODE_BEACON_INTERVAL; | |
2096 | new_val = beacon_val / beacon_factor; | |
2097 | ||
2098 | return cpu_to_le16(new_val); | |
2099 | } | |
2100 | ||
bb8c093b | 2101 | static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv) |
b481de9c ZY |
2102 | { |
2103 | u64 interval_tm_unit; | |
2104 | u64 tsf, result; | |
2105 | unsigned long flags; | |
2106 | struct ieee80211_conf *conf = NULL; | |
2107 | u16 beacon_int = 0; | |
2108 | ||
2109 | conf = ieee80211_get_hw_conf(priv->hw); | |
2110 | ||
2111 | spin_lock_irqsave(&priv->lock, flags); | |
2112 | priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1); | |
2113 | priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0); | |
2114 | ||
2115 | priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL; | |
2116 | ||
2117 | tsf = priv->timestamp1; | |
2118 | tsf = ((tsf << 32) | priv->timestamp0); | |
2119 | ||
2120 | beacon_int = priv->beacon_int; | |
2121 | spin_unlock_irqrestore(&priv->lock, flags); | |
2122 | ||
05c914fe | 2123 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
b481de9c ZY |
2124 | if (beacon_int == 0) { |
2125 | priv->rxon_timing.beacon_interval = cpu_to_le16(100); | |
2126 | priv->rxon_timing.beacon_init_val = cpu_to_le32(102400); | |
2127 | } else { | |
2128 | priv->rxon_timing.beacon_interval = | |
2129 | cpu_to_le16(beacon_int); | |
2130 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 2131 | iwl3945_adjust_beacon_interval( |
b481de9c ZY |
2132 | le16_to_cpu(priv->rxon_timing.beacon_interval)); |
2133 | } | |
2134 | ||
2135 | priv->rxon_timing.atim_window = 0; | |
2136 | } else { | |
2137 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 2138 | iwl3945_adjust_beacon_interval(conf->beacon_int); |
b481de9c ZY |
2139 | /* TODO: we need to get atim_window from upper stack |
2140 | * for now we set to 0 */ | |
2141 | priv->rxon_timing.atim_window = 0; | |
2142 | } | |
2143 | ||
2144 | interval_tm_unit = | |
2145 | (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024); | |
2146 | result = do_div(tsf, interval_tm_unit); | |
2147 | priv->rxon_timing.beacon_init_val = | |
2148 | cpu_to_le32((u32) ((u64) interval_tm_unit - result)); | |
2149 | ||
2150 | IWL_DEBUG_ASSOC | |
2151 | ("beacon interval %d beacon timer %d beacon tim %d\n", | |
2152 | le16_to_cpu(priv->rxon_timing.beacon_interval), | |
2153 | le32_to_cpu(priv->rxon_timing.beacon_init_val), | |
2154 | le16_to_cpu(priv->rxon_timing.atim_window)); | |
2155 | } | |
2156 | ||
bb8c093b | 2157 | static int iwl3945_scan_initiate(struct iwl3945_priv *priv) |
b481de9c | 2158 | { |
05c914fe | 2159 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
b481de9c ZY |
2160 | IWL_ERROR("APs don't scan.\n"); |
2161 | return 0; | |
2162 | } | |
2163 | ||
bb8c093b | 2164 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
2165 | IWL_DEBUG_SCAN("Aborting scan due to not ready.\n"); |
2166 | return -EIO; | |
2167 | } | |
2168 | ||
2169 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
2170 | IWL_DEBUG_SCAN("Scan already in progress.\n"); | |
2171 | return -EAGAIN; | |
2172 | } | |
2173 | ||
2174 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
2175 | IWL_DEBUG_SCAN("Scan request while abort pending. " | |
2176 | "Queuing.\n"); | |
2177 | return -EAGAIN; | |
2178 | } | |
2179 | ||
2180 | IWL_DEBUG_INFO("Starting scan...\n"); | |
66b5004d RR |
2181 | if (priv->cfg->sku & IWL_SKU_G) |
2182 | priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ); | |
2183 | if (priv->cfg->sku & IWL_SKU_A) | |
2184 | priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ); | |
b481de9c ZY |
2185 | set_bit(STATUS_SCANNING, &priv->status); |
2186 | priv->scan_start = jiffies; | |
2187 | priv->scan_pass_start = priv->scan_start; | |
2188 | ||
2189 | queue_work(priv->workqueue, &priv->request_scan); | |
2190 | ||
2191 | return 0; | |
2192 | } | |
2193 | ||
bb8c093b | 2194 | static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt) |
b481de9c | 2195 | { |
bb8c093b | 2196 | struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon; |
b481de9c ZY |
2197 | |
2198 | if (hw_decrypt) | |
2199 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
2200 | else | |
2201 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
2202 | ||
2203 | return 0; | |
2204 | } | |
2205 | ||
8318d78a JB |
2206 | static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv, |
2207 | enum ieee80211_band band) | |
b481de9c | 2208 | { |
8318d78a | 2209 | if (band == IEEE80211_BAND_5GHZ) { |
b481de9c ZY |
2210 | priv->staging_rxon.flags &= |
2211 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK | |
2212 | | RXON_FLG_CCK_MSK); | |
2213 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2214 | } else { | |
bb8c093b | 2215 | /* Copied from iwl3945_bg_post_associate() */ |
b481de9c ZY |
2216 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
2217 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2218 | else | |
2219 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2220 | ||
05c914fe | 2221 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2222 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
2223 | ||
2224 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
2225 | priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
2226 | priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK; | |
2227 | } | |
2228 | } | |
2229 | ||
2230 | /* | |
01ebd063 | 2231 | * initialize rxon structure with default values from eeprom |
b481de9c | 2232 | */ |
bb8c093b | 2233 | static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv) |
b481de9c | 2234 | { |
bb8c093b | 2235 | const struct iwl3945_channel_info *ch_info; |
b481de9c ZY |
2236 | |
2237 | memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon)); | |
2238 | ||
2239 | switch (priv->iw_mode) { | |
05c914fe | 2240 | case NL80211_IFTYPE_AP: |
b481de9c ZY |
2241 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP; |
2242 | break; | |
2243 | ||
05c914fe | 2244 | case NL80211_IFTYPE_STATION: |
b481de9c ZY |
2245 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS; |
2246 | priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; | |
2247 | break; | |
2248 | ||
05c914fe | 2249 | case NL80211_IFTYPE_ADHOC: |
b481de9c ZY |
2250 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS; |
2251 | priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK; | |
2252 | priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
2253 | RXON_FILTER_ACCEPT_GRP_MSK; | |
2254 | break; | |
2255 | ||
05c914fe | 2256 | case NL80211_IFTYPE_MONITOR: |
b481de9c ZY |
2257 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER; |
2258 | priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK | | |
2259 | RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK; | |
2260 | break; | |
69dc5d9d TW |
2261 | default: |
2262 | IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode); | |
2263 | break; | |
b481de9c ZY |
2264 | } |
2265 | ||
2266 | #if 0 | |
2267 | /* TODO: Figure out when short_preamble would be set and cache from | |
2268 | * that */ | |
2269 | if (!hw_to_local(priv->hw)->short_preamble) | |
2270 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2271 | else | |
2272 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2273 | #endif | |
2274 | ||
8318d78a | 2275 | ch_info = iwl3945_get_channel_info(priv, priv->band, |
25b3f57c | 2276 | le16_to_cpu(priv->active_rxon.channel)); |
b481de9c ZY |
2277 | |
2278 | if (!ch_info) | |
2279 | ch_info = &priv->channel_info[0]; | |
2280 | ||
2281 | /* | |
2282 | * in some case A channels are all non IBSS | |
2283 | * in this case force B/G channel | |
2284 | */ | |
05c914fe | 2285 | if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) && |
b481de9c ZY |
2286 | !(is_channel_ibss(ch_info))) |
2287 | ch_info = &priv->channel_info[0]; | |
2288 | ||
2289 | priv->staging_rxon.channel = cpu_to_le16(ch_info->channel); | |
2290 | if (is_channel_a_band(ch_info)) | |
8318d78a | 2291 | priv->band = IEEE80211_BAND_5GHZ; |
b481de9c | 2292 | else |
8318d78a | 2293 | priv->band = IEEE80211_BAND_2GHZ; |
b481de9c | 2294 | |
8318d78a | 2295 | iwl3945_set_flags_for_phymode(priv, priv->band); |
b481de9c ZY |
2296 | |
2297 | priv->staging_rxon.ofdm_basic_rates = | |
2298 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
2299 | priv->staging_rxon.cck_basic_rates = | |
2300 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
2301 | } | |
2302 | ||
bb8c093b | 2303 | static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode) |
b481de9c | 2304 | { |
05c914fe | 2305 | if (mode == NL80211_IFTYPE_ADHOC) { |
bb8c093b | 2306 | const struct iwl3945_channel_info *ch_info; |
b481de9c | 2307 | |
bb8c093b | 2308 | ch_info = iwl3945_get_channel_info(priv, |
8318d78a | 2309 | priv->band, |
b481de9c ZY |
2310 | le16_to_cpu(priv->staging_rxon.channel)); |
2311 | ||
2312 | if (!ch_info || !is_channel_ibss(ch_info)) { | |
2313 | IWL_ERROR("channel %d not IBSS channel\n", | |
2314 | le16_to_cpu(priv->staging_rxon.channel)); | |
2315 | return -EINVAL; | |
2316 | } | |
2317 | } | |
2318 | ||
b481de9c ZY |
2319 | priv->iw_mode = mode; |
2320 | ||
bb8c093b | 2321 | iwl3945_connection_init_rx_config(priv); |
b481de9c ZY |
2322 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
2323 | ||
bb8c093b | 2324 | iwl3945_clear_stations_table(priv); |
b481de9c | 2325 | |
fde3571f MA |
2326 | /* dont commit rxon if rf-kill is on*/ |
2327 | if (!iwl3945_is_ready_rf(priv)) | |
2328 | return -EAGAIN; | |
2329 | ||
2330 | cancel_delayed_work(&priv->scan_check); | |
2331 | if (iwl3945_scan_cancel_timeout(priv, 100)) { | |
2332 | IWL_WARNING("Aborted scan still in progress after 100ms\n"); | |
2333 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
2334 | return -EAGAIN; | |
2335 | } | |
2336 | ||
bb8c093b | 2337 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
2338 | |
2339 | return 0; | |
2340 | } | |
2341 | ||
bb8c093b | 2342 | static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv, |
e039fa4a | 2343 | struct ieee80211_tx_info *info, |
bb8c093b | 2344 | struct iwl3945_cmd *cmd, |
b481de9c ZY |
2345 | struct sk_buff *skb_frag, |
2346 | int last_frag) | |
2347 | { | |
1c014420 | 2348 | struct iwl3945_hw_key *keyinfo = |
e039fa4a | 2349 | &priv->stations[info->control.hw_key->hw_key_idx].keyinfo; |
b481de9c ZY |
2350 | |
2351 | switch (keyinfo->alg) { | |
2352 | case ALG_CCMP: | |
2353 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM; | |
2354 | memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen); | |
2355 | IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n"); | |
2356 | break; | |
2357 | ||
2358 | case ALG_TKIP: | |
2359 | #if 0 | |
2360 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP; | |
2361 | ||
2362 | if (last_frag) | |
2363 | memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8, | |
2364 | 8); | |
2365 | else | |
2366 | memset(cmd->cmd.tx.tkip_mic.byte, 0, 8); | |
2367 | #endif | |
2368 | break; | |
2369 | ||
2370 | case ALG_WEP: | |
2371 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP | | |
e039fa4a | 2372 | (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT; |
b481de9c ZY |
2373 | |
2374 | if (keyinfo->keylen == 13) | |
2375 | cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128; | |
2376 | ||
2377 | memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen); | |
2378 | ||
2379 | IWL_DEBUG_TX("Configuring packet for WEP encryption " | |
e039fa4a | 2380 | "with key %d\n", info->control.hw_key->hw_key_idx); |
b481de9c ZY |
2381 | break; |
2382 | ||
b481de9c ZY |
2383 | default: |
2384 | printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg); | |
2385 | break; | |
2386 | } | |
2387 | } | |
2388 | ||
2389 | /* | |
2390 | * handle build REPLY_TX command notification. | |
2391 | */ | |
bb8c093b CH |
2392 | static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv, |
2393 | struct iwl3945_cmd *cmd, | |
e039fa4a | 2394 | struct ieee80211_tx_info *info, |
b481de9c ZY |
2395 | struct ieee80211_hdr *hdr, |
2396 | int is_unicast, u8 std_id) | |
2397 | { | |
fd7c8a40 | 2398 | __le16 fc = hdr->frame_control; |
b481de9c ZY |
2399 | __le32 tx_flags = cmd->cmd.tx.tx_flags; |
2400 | ||
2401 | cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
e039fa4a | 2402 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
b481de9c | 2403 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 2404 | if (ieee80211_is_mgmt(fc)) |
b481de9c | 2405 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 2406 | if (ieee80211_is_probe_resp(fc) && |
b481de9c ZY |
2407 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
2408 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
2409 | } else { | |
2410 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
2411 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2412 | } | |
2413 | ||
2414 | cmd->cmd.tx.sta_id = std_id; | |
8b7b1e05 | 2415 | if (ieee80211_has_morefrags(fc)) |
b481de9c ZY |
2416 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
2417 | ||
fd7c8a40 HH |
2418 | if (ieee80211_is_data_qos(fc)) { |
2419 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
54dbb525 | 2420 | cmd->cmd.tx.tid_tspec = qc[0] & 0xf; |
b481de9c | 2421 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 2422 | } else { |
b481de9c | 2423 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 2424 | } |
b481de9c | 2425 | |
e039fa4a | 2426 | if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) { |
b481de9c ZY |
2427 | tx_flags |= TX_CMD_FLG_RTS_MSK; |
2428 | tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
e039fa4a | 2429 | } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) { |
b481de9c ZY |
2430 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; |
2431 | tx_flags |= TX_CMD_FLG_CTS_MSK; | |
2432 | } | |
2433 | ||
2434 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
2435 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
2436 | ||
2437 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
2438 | if (ieee80211_is_mgmt(fc)) { |
2439 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
bc434dd2 | 2440 | cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3); |
b481de9c | 2441 | else |
bc434dd2 | 2442 | cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2); |
ab53d8af | 2443 | } else { |
b481de9c | 2444 | cmd->cmd.tx.timeout.pm_frame_timeout = 0; |
ab53d8af MA |
2445 | #ifdef CONFIG_IWL3945_LEDS |
2446 | priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len); | |
2447 | #endif | |
2448 | } | |
b481de9c ZY |
2449 | |
2450 | cmd->cmd.tx.driver_txop = 0; | |
2451 | cmd->cmd.tx.tx_flags = tx_flags; | |
2452 | cmd->cmd.tx.next_frame_len = 0; | |
2453 | } | |
2454 | ||
6440adb5 CB |
2455 | /** |
2456 | * iwl3945_get_sta_id - Find station's index within station table | |
2457 | */ | |
bb8c093b | 2458 | static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr) |
b481de9c ZY |
2459 | { |
2460 | int sta_id; | |
2461 | u16 fc = le16_to_cpu(hdr->frame_control); | |
2462 | ||
6440adb5 | 2463 | /* If this frame is broadcast or management, use broadcast station id */ |
b481de9c ZY |
2464 | if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) || |
2465 | is_multicast_ether_addr(hdr->addr1)) | |
2466 | return priv->hw_setting.bcast_sta_id; | |
2467 | ||
2468 | switch (priv->iw_mode) { | |
2469 | ||
6440adb5 CB |
2470 | /* If we are a client station in a BSS network, use the special |
2471 | * AP station entry (that's the only station we communicate with) */ | |
05c914fe | 2472 | case NL80211_IFTYPE_STATION: |
b481de9c ZY |
2473 | return IWL_AP_ID; |
2474 | ||
2475 | /* If we are an AP, then find the station, or use BCAST */ | |
05c914fe | 2476 | case NL80211_IFTYPE_AP: |
bb8c093b | 2477 | sta_id = iwl3945_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2478 | if (sta_id != IWL_INVALID_STATION) |
2479 | return sta_id; | |
2480 | return priv->hw_setting.bcast_sta_id; | |
2481 | ||
6440adb5 CB |
2482 | /* If this frame is going out to an IBSS network, find the station, |
2483 | * or create a new station table entry */ | |
05c914fe | 2484 | case NL80211_IFTYPE_ADHOC: { |
0795af57 JP |
2485 | DECLARE_MAC_BUF(mac); |
2486 | ||
6440adb5 | 2487 | /* Create new station table entry */ |
bb8c093b | 2488 | sta_id = iwl3945_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2489 | if (sta_id != IWL_INVALID_STATION) |
2490 | return sta_id; | |
2491 | ||
bb8c093b | 2492 | sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC); |
b481de9c ZY |
2493 | |
2494 | if (sta_id != IWL_INVALID_STATION) | |
2495 | return sta_id; | |
2496 | ||
0795af57 | 2497 | IWL_DEBUG_DROP("Station %s not in station map. " |
b481de9c | 2498 | "Defaulting to broadcast...\n", |
0795af57 | 2499 | print_mac(mac, hdr->addr1)); |
bb8c093b | 2500 | iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr)); |
b481de9c | 2501 | return priv->hw_setting.bcast_sta_id; |
0795af57 | 2502 | } |
914233d6 SG |
2503 | /* If we are in monitor mode, use BCAST. This is required for |
2504 | * packet injection. */ | |
05c914fe | 2505 | case NL80211_IFTYPE_MONITOR: |
914233d6 SG |
2506 | return priv->hw_setting.bcast_sta_id; |
2507 | ||
b481de9c | 2508 | default: |
6f147926 | 2509 | IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode); |
b481de9c ZY |
2510 | return priv->hw_setting.bcast_sta_id; |
2511 | } | |
2512 | } | |
2513 | ||
2514 | /* | |
2515 | * start REPLY_TX command process | |
2516 | */ | |
e039fa4a | 2517 | static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb) |
b481de9c ZY |
2518 | { |
2519 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 2520 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bb8c093b | 2521 | struct iwl3945_tfd_frame *tfd; |
b481de9c | 2522 | u32 *control_flags; |
e2530083 | 2523 | int txq_id = skb_get_queue_mapping(skb); |
bb8c093b CH |
2524 | struct iwl3945_tx_queue *txq = NULL; |
2525 | struct iwl3945_queue *q = NULL; | |
b481de9c ZY |
2526 | dma_addr_t phys_addr; |
2527 | dma_addr_t txcmd_phys; | |
bb8c093b | 2528 | struct iwl3945_cmd *out_cmd = NULL; |
54dbb525 TW |
2529 | u16 len, idx, len_org, hdr_len; |
2530 | u8 id; | |
2531 | u8 unicast; | |
b481de9c | 2532 | u8 sta_id; |
54dbb525 | 2533 | u8 tid = 0; |
b481de9c | 2534 | u16 seq_number = 0; |
fd7c8a40 | 2535 | __le16 fc; |
b481de9c | 2536 | u8 wait_write_ptr = 0; |
54dbb525 | 2537 | u8 *qc = NULL; |
b481de9c ZY |
2538 | unsigned long flags; |
2539 | int rc; | |
2540 | ||
2541 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 2542 | if (iwl3945_is_rfkill(priv)) { |
b481de9c ZY |
2543 | IWL_DEBUG_DROP("Dropping - RF KILL\n"); |
2544 | goto drop_unlock; | |
2545 | } | |
2546 | ||
e039fa4a | 2547 | if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) { |
b481de9c ZY |
2548 | IWL_ERROR("ERROR: No TX rate available.\n"); |
2549 | goto drop_unlock; | |
2550 | } | |
2551 | ||
2552 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
2553 | id = 0; | |
2554 | ||
fd7c8a40 | 2555 | fc = hdr->frame_control; |
b481de9c | 2556 | |
c8b0e6e1 | 2557 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
2558 | if (ieee80211_is_auth(fc)) |
2559 | IWL_DEBUG_TX("Sending AUTH frame\n"); | |
fd7c8a40 | 2560 | else if (ieee80211_is_assoc_req(fc)) |
b481de9c | 2561 | IWL_DEBUG_TX("Sending ASSOC frame\n"); |
fd7c8a40 | 2562 | else if (ieee80211_is_reassoc_req(fc)) |
b481de9c ZY |
2563 | IWL_DEBUG_TX("Sending REASSOC frame\n"); |
2564 | #endif | |
2565 | ||
7878a5a4 | 2566 | /* drop all data frame if we are not associated */ |
914233d6 | 2567 | if (ieee80211_is_data(fc) && |
05c914fe | 2568 | (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */ |
914233d6 | 2569 | (!iwl3945_is_associated(priv) || |
05c914fe | 2570 | ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) { |
bb8c093b | 2571 | IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n"); |
b481de9c ZY |
2572 | goto drop_unlock; |
2573 | } | |
2574 | ||
2575 | spin_unlock_irqrestore(&priv->lock, flags); | |
2576 | ||
7294ec95 | 2577 | hdr_len = ieee80211_hdrlen(fc); |
6440adb5 CB |
2578 | |
2579 | /* Find (or create) index into station table for destination station */ | |
bb8c093b | 2580 | sta_id = iwl3945_get_sta_id(priv, hdr); |
b481de9c | 2581 | if (sta_id == IWL_INVALID_STATION) { |
0795af57 JP |
2582 | DECLARE_MAC_BUF(mac); |
2583 | ||
2584 | IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n", | |
2585 | print_mac(mac, hdr->addr1)); | |
b481de9c ZY |
2586 | goto drop; |
2587 | } | |
2588 | ||
2589 | IWL_DEBUG_RATE("station Id %d\n", sta_id); | |
2590 | ||
fd7c8a40 HH |
2591 | if (ieee80211_is_data_qos(fc)) { |
2592 | qc = ieee80211_get_qos_ctl(hdr); | |
7294ec95 | 2593 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
b481de9c ZY |
2594 | seq_number = priv->stations[sta_id].tid[tid].seq_number & |
2595 | IEEE80211_SCTL_SEQ; | |
2596 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
2597 | (hdr->seq_ctrl & | |
2598 | __constant_cpu_to_le16(IEEE80211_SCTL_FRAG)); | |
2599 | seq_number += 0x10; | |
2600 | } | |
6440adb5 CB |
2601 | |
2602 | /* Descriptor for chosen Tx queue */ | |
b481de9c ZY |
2603 | txq = &priv->txq[txq_id]; |
2604 | q = &txq->q; | |
2605 | ||
2606 | spin_lock_irqsave(&priv->lock, flags); | |
2607 | ||
6440adb5 | 2608 | /* Set up first empty TFD within this queue's circular TFD buffer */ |
fc4b6853 | 2609 | tfd = &txq->bd[q->write_ptr]; |
b481de9c ZY |
2610 | memset(tfd, 0, sizeof(*tfd)); |
2611 | control_flags = (u32 *) tfd; | |
fc4b6853 | 2612 | idx = get_cmd_index(q, q->write_ptr, 0); |
b481de9c | 2613 | |
6440adb5 | 2614 | /* Set up driver data for this TFD */ |
bb8c093b | 2615 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info)); |
fc4b6853 | 2616 | txq->txb[q->write_ptr].skb[0] = skb; |
6440adb5 CB |
2617 | |
2618 | /* Init first empty entry in queue's array of Tx/cmd buffers */ | |
b481de9c ZY |
2619 | out_cmd = &txq->cmd[idx]; |
2620 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
2621 | memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx)); | |
6440adb5 CB |
2622 | |
2623 | /* | |
2624 | * Set up the Tx-command (not MAC!) header. | |
2625 | * Store the chosen Tx queue and TFD index within the sequence field; | |
2626 | * after Tx, uCode's Tx response will return this value so driver can | |
2627 | * locate the frame within the tx queue and do post-tx processing. | |
2628 | */ | |
b481de9c ZY |
2629 | out_cmd->hdr.cmd = REPLY_TX; |
2630 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
fc4b6853 | 2631 | INDEX_TO_SEQ(q->write_ptr))); |
6440adb5 CB |
2632 | |
2633 | /* Copy MAC header from skb into command buffer */ | |
b481de9c ZY |
2634 | memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len); |
2635 | ||
6440adb5 CB |
2636 | /* |
2637 | * Use the first empty entry in this queue's command buffer array | |
2638 | * to contain the Tx command and MAC header concatenated together | |
2639 | * (payload data will be in another buffer). | |
2640 | * Size of this varies, due to varying MAC header length. | |
2641 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
2642 | * of the MAC header (device reads on dword boundaries). | |
2643 | * We'll tell device about this padding later. | |
2644 | */ | |
b481de9c | 2645 | len = priv->hw_setting.tx_cmd_len + |
bb8c093b | 2646 | sizeof(struct iwl3945_cmd_header) + hdr_len; |
b481de9c ZY |
2647 | |
2648 | len_org = len; | |
2649 | len = (len + 3) & ~3; | |
2650 | ||
2651 | if (len_org != len) | |
2652 | len_org = 1; | |
2653 | else | |
2654 | len_org = 0; | |
2655 | ||
6440adb5 CB |
2656 | /* Physical address of this Tx command's header (not MAC header!), |
2657 | * within command buffer array. */ | |
bb8c093b CH |
2658 | txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx + |
2659 | offsetof(struct iwl3945_cmd, hdr); | |
b481de9c | 2660 | |
6440adb5 CB |
2661 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
2662 | * first entry */ | |
bb8c093b | 2663 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len); |
b481de9c | 2664 | |
d0f09804 | 2665 | if (info->control.hw_key) |
e039fa4a | 2666 | iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0); |
b481de9c | 2667 | |
6440adb5 CB |
2668 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
2669 | * if any (802.11 null frames have no payload). */ | |
b481de9c ZY |
2670 | len = skb->len - hdr_len; |
2671 | if (len) { | |
2672 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
2673 | len, PCI_DMA_TODEVICE); | |
bb8c093b | 2674 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len); |
b481de9c ZY |
2675 | } |
2676 | ||
b481de9c | 2677 | if (!len) |
6440adb5 | 2678 | /* If there is no payload, then we use only one Tx buffer */ |
b481de9c ZY |
2679 | *control_flags = TFD_CTL_COUNT_SET(1); |
2680 | else | |
6440adb5 CB |
2681 | /* Else use 2 buffers. |
2682 | * Tell 3945 about any padding after MAC header */ | |
b481de9c ZY |
2683 | *control_flags = TFD_CTL_COUNT_SET(2) | |
2684 | TFD_CTL_PAD_SET(U32_PAD(len)); | |
2685 | ||
6440adb5 | 2686 | /* Total # bytes to be transmitted */ |
b481de9c ZY |
2687 | len = (u16)skb->len; |
2688 | out_cmd->cmd.tx.len = cpu_to_le16(len); | |
2689 | ||
2690 | /* TODO need this for burst mode later on */ | |
e039fa4a | 2691 | iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id); |
b481de9c ZY |
2692 | |
2693 | /* set is_hcca to 0; it probably will never be implemented */ | |
e039fa4a | 2694 | iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0); |
b481de9c ZY |
2695 | |
2696 | out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK; | |
2697 | out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK; | |
2698 | ||
8b7b1e05 | 2699 | if (!ieee80211_has_morefrags(hdr->frame_control)) { |
b481de9c | 2700 | txq->need_update = 1; |
3ac7f146 | 2701 | if (qc) |
b481de9c | 2702 | priv->stations[sta_id].tid[tid].seq_number = seq_number; |
b481de9c ZY |
2703 | } else { |
2704 | wait_write_ptr = 1; | |
2705 | txq->need_update = 0; | |
2706 | } | |
2707 | ||
bb8c093b | 2708 | iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload, |
b481de9c ZY |
2709 | sizeof(out_cmd->cmd.tx)); |
2710 | ||
bb8c093b | 2711 | iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr, |
7294ec95 | 2712 | ieee80211_hdrlen(fc)); |
b481de9c | 2713 | |
6440adb5 | 2714 | /* Tell device the write index *just past* this latest filled TFD */ |
c54b679d | 2715 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
bb8c093b | 2716 | rc = iwl3945_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
2717 | spin_unlock_irqrestore(&priv->lock, flags); |
2718 | ||
2719 | if (rc) | |
2720 | return rc; | |
2721 | ||
bb8c093b | 2722 | if ((iwl3945_queue_space(q) < q->high_mark) |
b481de9c ZY |
2723 | && priv->mac80211_registered) { |
2724 | if (wait_write_ptr) { | |
2725 | spin_lock_irqsave(&priv->lock, flags); | |
2726 | txq->need_update = 1; | |
bb8c093b | 2727 | iwl3945_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
2728 | spin_unlock_irqrestore(&priv->lock, flags); |
2729 | } | |
2730 | ||
e2530083 | 2731 | ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb)); |
b481de9c ZY |
2732 | } |
2733 | ||
2734 | return 0; | |
2735 | ||
2736 | drop_unlock: | |
2737 | spin_unlock_irqrestore(&priv->lock, flags); | |
2738 | drop: | |
2739 | return -1; | |
2740 | } | |
2741 | ||
bb8c093b | 2742 | static void iwl3945_set_rate(struct iwl3945_priv *priv) |
b481de9c | 2743 | { |
8318d78a | 2744 | const struct ieee80211_supported_band *sband = NULL; |
b481de9c ZY |
2745 | struct ieee80211_rate *rate; |
2746 | int i; | |
2747 | ||
8318d78a JB |
2748 | sband = iwl3945_get_band(priv, priv->band); |
2749 | if (!sband) { | |
c4ba9621 SA |
2750 | IWL_ERROR("Failed to set rate: unable to get hw mode\n"); |
2751 | return; | |
2752 | } | |
b481de9c ZY |
2753 | |
2754 | priv->active_rate = 0; | |
2755 | priv->active_rate_basic = 0; | |
2756 | ||
8318d78a JB |
2757 | IWL_DEBUG_RATE("Setting rates for %s GHz\n", |
2758 | sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5"); | |
2759 | ||
2760 | for (i = 0; i < sband->n_bitrates; i++) { | |
2761 | rate = &sband->bitrates[i]; | |
2762 | if ((rate->hw_value < IWL_RATE_COUNT) && | |
2763 | !(rate->flags & IEEE80211_CHAN_DISABLED)) { | |
2764 | IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n", | |
2765 | rate->hw_value, iwl3945_rates[rate->hw_value].plcp); | |
2766 | priv->active_rate |= (1 << rate->hw_value); | |
2767 | } | |
b481de9c ZY |
2768 | } |
2769 | ||
2770 | IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n", | |
2771 | priv->active_rate, priv->active_rate_basic); | |
2772 | ||
2773 | /* | |
2774 | * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK) | |
2775 | * otherwise set it to the default of all CCK rates and 6, 12, 24 for | |
2776 | * OFDM | |
2777 | */ | |
2778 | if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK) | |
2779 | priv->staging_rxon.cck_basic_rates = | |
2780 | ((priv->active_rate_basic & | |
2781 | IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF; | |
2782 | else | |
2783 | priv->staging_rxon.cck_basic_rates = | |
2784 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
2785 | ||
2786 | if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK) | |
2787 | priv->staging_rxon.ofdm_basic_rates = | |
2788 | ((priv->active_rate_basic & | |
2789 | (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >> | |
2790 | IWL_FIRST_OFDM_RATE) & 0xFF; | |
2791 | else | |
2792 | priv->staging_rxon.ofdm_basic_rates = | |
2793 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
2794 | } | |
2795 | ||
bb8c093b | 2796 | static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio) |
b481de9c ZY |
2797 | { |
2798 | unsigned long flags; | |
2799 | ||
2800 | if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status)) | |
2801 | return; | |
2802 | ||
2803 | IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n", | |
2804 | disable_radio ? "OFF" : "ON"); | |
2805 | ||
2806 | if (disable_radio) { | |
bb8c093b | 2807 | iwl3945_scan_cancel(priv); |
b481de9c | 2808 | /* FIXME: This is a workaround for AP */ |
05c914fe | 2809 | if (priv->iw_mode != NL80211_IFTYPE_AP) { |
b481de9c | 2810 | spin_lock_irqsave(&priv->lock, flags); |
bb8c093b | 2811 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
2812 | CSR_UCODE_SW_BIT_RFKILL); |
2813 | spin_unlock_irqrestore(&priv->lock, flags); | |
bb8c093b | 2814 | iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0); |
b481de9c ZY |
2815 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
2816 | } | |
2817 | return; | |
2818 | } | |
2819 | ||
2820 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 2821 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
b481de9c ZY |
2822 | |
2823 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
2824 | spin_unlock_irqrestore(&priv->lock, flags); | |
2825 | ||
2826 | /* wake up ucode */ | |
2827 | msleep(10); | |
2828 | ||
2829 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b CH |
2830 | iwl3945_read32(priv, CSR_UCODE_DRV_GP1); |
2831 | if (!iwl3945_grab_nic_access(priv)) | |
2832 | iwl3945_release_nic_access(priv); | |
b481de9c ZY |
2833 | spin_unlock_irqrestore(&priv->lock, flags); |
2834 | ||
2835 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
2836 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
2837 | "disabled by HW switch\n"); | |
2838 | return; | |
2839 | } | |
2840 | ||
808e72a0 ZY |
2841 | if (priv->is_open) |
2842 | queue_work(priv->workqueue, &priv->restart); | |
b481de9c ZY |
2843 | return; |
2844 | } | |
2845 | ||
bb8c093b | 2846 | void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb, |
b481de9c ZY |
2847 | u32 decrypt_res, struct ieee80211_rx_status *stats) |
2848 | { | |
2849 | u16 fc = | |
2850 | le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control); | |
2851 | ||
2852 | if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) | |
2853 | return; | |
2854 | ||
2855 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
2856 | return; | |
2857 | ||
2858 | IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res); | |
2859 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { | |
2860 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
2861 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2862 | RX_RES_STATUS_BAD_ICV_MIC) | |
2863 | stats->flag |= RX_FLAG_MMIC_ERROR; | |
2864 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
2865 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
2866 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2867 | RX_RES_STATUS_DECRYPT_OK) { | |
2868 | IWL_DEBUG_RX("hw decrypt successfully!!!\n"); | |
2869 | stats->flag |= RX_FLAG_DECRYPTED; | |
2870 | } | |
2871 | break; | |
2872 | ||
2873 | default: | |
2874 | break; | |
2875 | } | |
2876 | } | |
2877 | ||
c8b0e6e1 | 2878 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
2879 | |
2880 | #include "iwl-spectrum.h" | |
2881 | ||
2882 | #define BEACON_TIME_MASK_LOW 0x00FFFFFF | |
2883 | #define BEACON_TIME_MASK_HIGH 0xFF000000 | |
2884 | #define TIME_UNIT 1024 | |
2885 | ||
2886 | /* | |
2887 | * extended beacon time format | |
2888 | * time in usec will be changed into a 32-bit value in 8:24 format | |
2889 | * the high 1 byte is the beacon counts | |
2890 | * the lower 3 bytes is the time in usec within one beacon interval | |
2891 | */ | |
2892 | ||
bb8c093b | 2893 | static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval) |
b481de9c ZY |
2894 | { |
2895 | u32 quot; | |
2896 | u32 rem; | |
2897 | u32 interval = beacon_interval * 1024; | |
2898 | ||
2899 | if (!interval || !usec) | |
2900 | return 0; | |
2901 | ||
2902 | quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24); | |
2903 | rem = (usec % interval) & BEACON_TIME_MASK_LOW; | |
2904 | ||
2905 | return (quot << 24) + rem; | |
2906 | } | |
2907 | ||
2908 | /* base is usually what we get from ucode with each received frame, | |
2909 | * the same as HW timer counter counting down | |
2910 | */ | |
2911 | ||
bb8c093b | 2912 | static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval) |
b481de9c ZY |
2913 | { |
2914 | u32 base_low = base & BEACON_TIME_MASK_LOW; | |
2915 | u32 addon_low = addon & BEACON_TIME_MASK_LOW; | |
2916 | u32 interval = beacon_interval * TIME_UNIT; | |
2917 | u32 res = (base & BEACON_TIME_MASK_HIGH) + | |
2918 | (addon & BEACON_TIME_MASK_HIGH); | |
2919 | ||
2920 | if (base_low > addon_low) | |
2921 | res += base_low - addon_low; | |
2922 | else if (base_low < addon_low) { | |
2923 | res += interval + base_low - addon_low; | |
2924 | res += (1 << 24); | |
2925 | } else | |
2926 | res += (1 << 24); | |
2927 | ||
2928 | return cpu_to_le32(res); | |
2929 | } | |
2930 | ||
bb8c093b | 2931 | static int iwl3945_get_measurement(struct iwl3945_priv *priv, |
b481de9c ZY |
2932 | struct ieee80211_measurement_params *params, |
2933 | u8 type) | |
2934 | { | |
bb8c093b CH |
2935 | struct iwl3945_spectrum_cmd spectrum; |
2936 | struct iwl3945_rx_packet *res; | |
2937 | struct iwl3945_host_cmd cmd = { | |
b481de9c ZY |
2938 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
2939 | .data = (void *)&spectrum, | |
2940 | .meta.flags = CMD_WANT_SKB, | |
2941 | }; | |
2942 | u32 add_time = le64_to_cpu(params->start_time); | |
2943 | int rc; | |
2944 | int spectrum_resp_status; | |
2945 | int duration = le16_to_cpu(params->duration); | |
2946 | ||
bb8c093b | 2947 | if (iwl3945_is_associated(priv)) |
b481de9c | 2948 | add_time = |
bb8c093b | 2949 | iwl3945_usecs_to_beacons( |
b481de9c ZY |
2950 | le64_to_cpu(params->start_time) - priv->last_tsf, |
2951 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
2952 | ||
2953 | memset(&spectrum, 0, sizeof(spectrum)); | |
2954 | ||
2955 | spectrum.channel_count = cpu_to_le16(1); | |
2956 | spectrum.flags = | |
2957 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
2958 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
2959 | cmd.len = sizeof(spectrum); | |
2960 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
2961 | ||
bb8c093b | 2962 | if (iwl3945_is_associated(priv)) |
b481de9c | 2963 | spectrum.start_time = |
bb8c093b | 2964 | iwl3945_add_beacon_time(priv->last_beacon_time, |
b481de9c ZY |
2965 | add_time, |
2966 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
2967 | else | |
2968 | spectrum.start_time = 0; | |
2969 | ||
2970 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
2971 | spectrum.channels[0].channel = params->channel; | |
2972 | spectrum.channels[0].type = type; | |
2973 | if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK) | |
2974 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | | |
2975 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
2976 | ||
bb8c093b | 2977 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
2978 | if (rc) |
2979 | return rc; | |
2980 | ||
bb8c093b | 2981 | res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
2982 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
2983 | IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n"); | |
2984 | rc = -EIO; | |
2985 | } | |
2986 | ||
2987 | spectrum_resp_status = le16_to_cpu(res->u.spectrum.status); | |
2988 | switch (spectrum_resp_status) { | |
2989 | case 0: /* Command will be handled */ | |
2990 | if (res->u.spectrum.id != 0xff) { | |
bc434dd2 IS |
2991 | IWL_DEBUG_INFO("Replaced existing measurement: %d\n", |
2992 | res->u.spectrum.id); | |
b481de9c ZY |
2993 | priv->measurement_status &= ~MEASUREMENT_READY; |
2994 | } | |
2995 | priv->measurement_status |= MEASUREMENT_ACTIVE; | |
2996 | rc = 0; | |
2997 | break; | |
2998 | ||
2999 | case 1: /* Command will not be handled */ | |
3000 | rc = -EAGAIN; | |
3001 | break; | |
3002 | } | |
3003 | ||
3004 | dev_kfree_skb_any(cmd.meta.u.skb); | |
3005 | ||
3006 | return rc; | |
3007 | } | |
3008 | #endif | |
3009 | ||
bb8c093b CH |
3010 | static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv, |
3011 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3012 | { |
bb8c093b CH |
3013 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3014 | struct iwl3945_alive_resp *palive; | |
b481de9c ZY |
3015 | struct delayed_work *pwork; |
3016 | ||
3017 | palive = &pkt->u.alive_frame; | |
3018 | ||
3019 | IWL_DEBUG_INFO("Alive ucode status 0x%08X revision " | |
3020 | "0x%01X 0x%01X\n", | |
3021 | palive->is_valid, palive->ver_type, | |
3022 | palive->ver_subtype); | |
3023 | ||
3024 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
3025 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
3026 | memcpy(&priv->card_alive_init, | |
3027 | &pkt->u.alive_frame, | |
bb8c093b | 3028 | sizeof(struct iwl3945_init_alive_resp)); |
b481de9c ZY |
3029 | pwork = &priv->init_alive_start; |
3030 | } else { | |
3031 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
3032 | memcpy(&priv->card_alive, &pkt->u.alive_frame, | |
bb8c093b | 3033 | sizeof(struct iwl3945_alive_resp)); |
b481de9c | 3034 | pwork = &priv->alive_start; |
bb8c093b | 3035 | iwl3945_disable_events(priv); |
b481de9c ZY |
3036 | } |
3037 | ||
3038 | /* We delay the ALIVE response by 5ms to | |
3039 | * give the HW RF Kill time to activate... */ | |
3040 | if (palive->is_valid == UCODE_VALID_OK) | |
3041 | queue_delayed_work(priv->workqueue, pwork, | |
3042 | msecs_to_jiffies(5)); | |
3043 | else | |
3044 | IWL_WARNING("uCode did not respond OK.\n"); | |
3045 | } | |
3046 | ||
bb8c093b CH |
3047 | static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv, |
3048 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3049 | { |
bb8c093b | 3050 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3051 | |
3052 | IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); | |
3053 | return; | |
3054 | } | |
3055 | ||
bb8c093b CH |
3056 | static void iwl3945_rx_reply_error(struct iwl3945_priv *priv, |
3057 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3058 | { |
bb8c093b | 3059 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3060 | |
3061 | IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) " | |
3062 | "seq 0x%04X ser 0x%08X\n", | |
3063 | le32_to_cpu(pkt->u.err_resp.error_type), | |
3064 | get_cmd_string(pkt->u.err_resp.cmd_id), | |
3065 | pkt->u.err_resp.cmd_id, | |
3066 | le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num), | |
3067 | le32_to_cpu(pkt->u.err_resp.error_info)); | |
3068 | } | |
3069 | ||
3070 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x | |
3071 | ||
bb8c093b | 3072 | static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb) |
b481de9c | 3073 | { |
bb8c093b CH |
3074 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3075 | struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon; | |
3076 | struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif); | |
b481de9c ZY |
3077 | IWL_DEBUG_11H("CSA notif: channel %d, status %d\n", |
3078 | le16_to_cpu(csa->channel), le32_to_cpu(csa->status)); | |
3079 | rxon->channel = csa->channel; | |
3080 | priv->staging_rxon.channel = csa->channel; | |
3081 | } | |
3082 | ||
bb8c093b CH |
3083 | static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv, |
3084 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3085 | { |
c8b0e6e1 | 3086 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
bb8c093b CH |
3087 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3088 | struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif); | |
b481de9c ZY |
3089 | |
3090 | if (!report->state) { | |
3091 | IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO, | |
3092 | "Spectrum Measure Notification: Start\n"); | |
3093 | return; | |
3094 | } | |
3095 | ||
3096 | memcpy(&priv->measure_report, report, sizeof(*report)); | |
3097 | priv->measurement_status |= MEASUREMENT_READY; | |
3098 | #endif | |
3099 | } | |
3100 | ||
bb8c093b CH |
3101 | static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv, |
3102 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3103 | { |
c8b0e6e1 | 3104 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
3105 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3106 | struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif); | |
b481de9c ZY |
3107 | IWL_DEBUG_RX("sleep mode: %d, src: %d\n", |
3108 | sleep->pm_sleep_mode, sleep->pm_wakeup_src); | |
3109 | #endif | |
3110 | } | |
3111 | ||
bb8c093b CH |
3112 | static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv, |
3113 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3114 | { |
bb8c093b | 3115 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3116 | IWL_DEBUG_RADIO("Dumping %d bytes of unhandled " |
3117 | "notification for %s:\n", | |
3118 | le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd)); | |
bb8c093b | 3119 | iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len)); |
b481de9c ZY |
3120 | } |
3121 | ||
bb8c093b | 3122 | static void iwl3945_bg_beacon_update(struct work_struct *work) |
b481de9c | 3123 | { |
bb8c093b CH |
3124 | struct iwl3945_priv *priv = |
3125 | container_of(work, struct iwl3945_priv, beacon_update); | |
b481de9c ZY |
3126 | struct sk_buff *beacon; |
3127 | ||
3128 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 3129 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
3130 | |
3131 | if (!beacon) { | |
3132 | IWL_ERROR("update beacon failed\n"); | |
3133 | return; | |
3134 | } | |
3135 | ||
3136 | mutex_lock(&priv->mutex); | |
3137 | /* new beacon skb is allocated every time; dispose previous.*/ | |
3138 | if (priv->ibss_beacon) | |
3139 | dev_kfree_skb(priv->ibss_beacon); | |
3140 | ||
3141 | priv->ibss_beacon = beacon; | |
3142 | mutex_unlock(&priv->mutex); | |
3143 | ||
bb8c093b | 3144 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
3145 | } |
3146 | ||
bb8c093b CH |
3147 | static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv, |
3148 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3149 | { |
c8b0e6e1 | 3150 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
3151 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3152 | struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status); | |
b481de9c ZY |
3153 | u8 rate = beacon->beacon_notify_hdr.rate; |
3154 | ||
3155 | IWL_DEBUG_RX("beacon status %x retries %d iss %d " | |
3156 | "tsf %d %d rate %d\n", | |
3157 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
3158 | beacon->beacon_notify_hdr.failure_frame, | |
3159 | le32_to_cpu(beacon->ibss_mgr_status), | |
3160 | le32_to_cpu(beacon->high_tsf), | |
3161 | le32_to_cpu(beacon->low_tsf), rate); | |
3162 | #endif | |
3163 | ||
05c914fe | 3164 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
3165 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
3166 | queue_work(priv->workqueue, &priv->beacon_update); | |
3167 | } | |
3168 | ||
3169 | /* Service response to REPLY_SCAN_CMD (0x80) */ | |
bb8c093b CH |
3170 | static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv, |
3171 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3172 | { |
c8b0e6e1 | 3173 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
3174 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3175 | struct iwl3945_scanreq_notification *notif = | |
3176 | (struct iwl3945_scanreq_notification *)pkt->u.raw; | |
b481de9c ZY |
3177 | |
3178 | IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status); | |
3179 | #endif | |
3180 | } | |
3181 | ||
3182 | /* Service SCAN_START_NOTIFICATION (0x82) */ | |
bb8c093b CH |
3183 | static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv, |
3184 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3185 | { |
bb8c093b CH |
3186 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3187 | struct iwl3945_scanstart_notification *notif = | |
3188 | (struct iwl3945_scanstart_notification *)pkt->u.raw; | |
b481de9c ZY |
3189 | priv->scan_start_tsf = le32_to_cpu(notif->tsf_low); |
3190 | IWL_DEBUG_SCAN("Scan start: " | |
3191 | "%d [802.11%s] " | |
3192 | "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", | |
3193 | notif->channel, | |
3194 | notif->band ? "bg" : "a", | |
3195 | notif->tsf_high, | |
3196 | notif->tsf_low, notif->status, notif->beacon_timer); | |
3197 | } | |
3198 | ||
3199 | /* Service SCAN_RESULTS_NOTIFICATION (0x83) */ | |
bb8c093b CH |
3200 | static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv, |
3201 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3202 | { |
bb8c093b CH |
3203 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3204 | struct iwl3945_scanresults_notification *notif = | |
3205 | (struct iwl3945_scanresults_notification *)pkt->u.raw; | |
b481de9c ZY |
3206 | |
3207 | IWL_DEBUG_SCAN("Scan ch.res: " | |
3208 | "%d [802.11%s] " | |
3209 | "(TSF: 0x%08X:%08X) - %d " | |
3210 | "elapsed=%lu usec (%dms since last)\n", | |
3211 | notif->channel, | |
3212 | notif->band ? "bg" : "a", | |
3213 | le32_to_cpu(notif->tsf_high), | |
3214 | le32_to_cpu(notif->tsf_low), | |
3215 | le32_to_cpu(notif->statistics[0]), | |
3216 | le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf, | |
3217 | jiffies_to_msecs(elapsed_jiffies | |
3218 | (priv->last_scan_jiffies, jiffies))); | |
3219 | ||
3220 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 3221 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
3222 | } |
3223 | ||
3224 | /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */ | |
bb8c093b CH |
3225 | static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv, |
3226 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3227 | { |
bb8c093b CH |
3228 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3229 | struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw; | |
b481de9c ZY |
3230 | |
3231 | IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n", | |
3232 | scan_notif->scanned_channels, | |
3233 | scan_notif->tsf_low, | |
3234 | scan_notif->tsf_high, scan_notif->status); | |
3235 | ||
3236 | /* The HW is no longer scanning */ | |
3237 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
3238 | ||
3239 | /* The scan completion notification came in, so kill that timer... */ | |
3240 | cancel_delayed_work(&priv->scan_check); | |
3241 | ||
3242 | IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n", | |
66b5004d RR |
3243 | (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ? |
3244 | "2.4" : "5.2", | |
b481de9c ZY |
3245 | jiffies_to_msecs(elapsed_jiffies |
3246 | (priv->scan_pass_start, jiffies))); | |
3247 | ||
66b5004d RR |
3248 | /* Remove this scanned band from the list of pending |
3249 | * bands to scan, band G precedes A in order of scanning | |
3250 | * as seen in iwl3945_bg_request_scan */ | |
3251 | if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) | |
3252 | priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ); | |
3253 | else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) | |
3254 | priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ); | |
b481de9c ZY |
3255 | |
3256 | /* If a request to abort was given, or the scan did not succeed | |
3257 | * then we reset the scan state machine and terminate, | |
3258 | * re-queuing another scan if one has been requested */ | |
3259 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
3260 | IWL_DEBUG_INFO("Aborted scan completed.\n"); | |
3261 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
3262 | } else { | |
3263 | /* If there are more bands on this scan pass reschedule */ | |
3264 | if (priv->scan_bands > 0) | |
3265 | goto reschedule; | |
3266 | } | |
3267 | ||
3268 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 3269 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
3270 | IWL_DEBUG_INFO("Setting scan to off\n"); |
3271 | ||
3272 | clear_bit(STATUS_SCANNING, &priv->status); | |
3273 | ||
3274 | IWL_DEBUG_INFO("Scan took %dms\n", | |
3275 | jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies))); | |
3276 | ||
3277 | queue_work(priv->workqueue, &priv->scan_completed); | |
3278 | ||
3279 | return; | |
3280 | ||
3281 | reschedule: | |
3282 | priv->scan_pass_start = jiffies; | |
3283 | queue_work(priv->workqueue, &priv->request_scan); | |
3284 | } | |
3285 | ||
3286 | /* Handle notification from uCode that card's power state is changing | |
3287 | * due to software, hardware, or critical temperature RFKILL */ | |
bb8c093b CH |
3288 | static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv, |
3289 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3290 | { |
bb8c093b | 3291 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3292 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
3293 | unsigned long status = priv->status; | |
3294 | ||
3295 | IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n", | |
3296 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
3297 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
3298 | ||
bb8c093b | 3299 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
3300 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
3301 | ||
3302 | if (flags & HW_CARD_DISABLED) | |
3303 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
3304 | else | |
3305 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3306 | ||
3307 | ||
3308 | if (flags & SW_CARD_DISABLED) | |
3309 | set_bit(STATUS_RF_KILL_SW, &priv->status); | |
3310 | else | |
3311 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
3312 | ||
bb8c093b | 3313 | iwl3945_scan_cancel(priv); |
b481de9c ZY |
3314 | |
3315 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
3316 | test_bit(STATUS_RF_KILL_HW, &priv->status)) || | |
3317 | (test_bit(STATUS_RF_KILL_SW, &status) != | |
3318 | test_bit(STATUS_RF_KILL_SW, &priv->status))) | |
3319 | queue_work(priv->workqueue, &priv->rf_kill); | |
3320 | else | |
3321 | wake_up_interruptible(&priv->wait_command_queue); | |
3322 | } | |
3323 | ||
3324 | /** | |
bb8c093b | 3325 | * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
3326 | * |
3327 | * Setup the RX handlers for each of the reply types sent from the uCode | |
3328 | * to the host. | |
3329 | * | |
3330 | * This function chains into the hardware specific files for them to setup | |
3331 | * any hardware specific handlers as well. | |
3332 | */ | |
bb8c093b | 3333 | static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv) |
b481de9c | 3334 | { |
bb8c093b CH |
3335 | priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive; |
3336 | priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta; | |
3337 | priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error; | |
3338 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa; | |
b481de9c | 3339 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
bb8c093b CH |
3340 | iwl3945_rx_spectrum_measure_notif; |
3341 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif; | |
b481de9c | 3342 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
bb8c093b CH |
3343 | iwl3945_rx_pm_debug_statistics_notif; |
3344 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif; | |
b481de9c | 3345 | |
9fbab516 BC |
3346 | /* |
3347 | * The same handler is used for both the REPLY to a discrete | |
3348 | * statistics request from the host as well as for the periodic | |
3349 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 3350 | */ |
bb8c093b CH |
3351 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics; |
3352 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics; | |
b481de9c | 3353 | |
bb8c093b CH |
3354 | priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan; |
3355 | priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif; | |
b481de9c | 3356 | priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] = |
bb8c093b | 3357 | iwl3945_rx_scan_results_notif; |
b481de9c | 3358 | priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] = |
bb8c093b CH |
3359 | iwl3945_rx_scan_complete_notif; |
3360 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif; | |
b481de9c | 3361 | |
9fbab516 | 3362 | /* Set up hardware specific Rx handlers */ |
bb8c093b | 3363 | iwl3945_hw_rx_handler_setup(priv); |
b481de9c ZY |
3364 | } |
3365 | ||
91c066f2 TW |
3366 | /** |
3367 | * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries | |
3368 | * When FW advances 'R' index, all entries between old and new 'R' index | |
3369 | * need to be reclaimed. | |
3370 | */ | |
3371 | static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv, | |
3372 | int txq_id, int index) | |
3373 | { | |
3374 | struct iwl3945_tx_queue *txq = &priv->txq[txq_id]; | |
3375 | struct iwl3945_queue *q = &txq->q; | |
3376 | int nfreed = 0; | |
3377 | ||
3378 | if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) { | |
3379 | IWL_ERROR("Read index for DMA queue txq id (%d), index %d, " | |
3380 | "is out of range [0-%d] %d %d.\n", txq_id, | |
3381 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
3382 | return; | |
3383 | } | |
3384 | ||
3385 | for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index; | |
3386 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
3387 | if (nfreed > 1) { | |
3388 | IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index, | |
3389 | q->write_ptr, q->read_ptr); | |
3390 | queue_work(priv->workqueue, &priv->restart); | |
3391 | break; | |
3392 | } | |
3393 | nfreed++; | |
3394 | } | |
3395 | } | |
3396 | ||
3397 | ||
b481de9c | 3398 | /** |
bb8c093b | 3399 | * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them |
b481de9c ZY |
3400 | * @rxb: Rx buffer to reclaim |
3401 | * | |
3402 | * If an Rx buffer has an async callback associated with it the callback | |
3403 | * will be executed. The attached skb (if present) will only be freed | |
3404 | * if the callback returns 1 | |
3405 | */ | |
bb8c093b CH |
3406 | static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv, |
3407 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3408 | { |
bb8c093b | 3409 | struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data; |
b481de9c ZY |
3410 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
3411 | int txq_id = SEQ_TO_QUEUE(sequence); | |
3412 | int index = SEQ_TO_INDEX(sequence); | |
3413 | int huge = sequence & SEQ_HUGE_FRAME; | |
3414 | int cmd_index; | |
bb8c093b | 3415 | struct iwl3945_cmd *cmd; |
b481de9c | 3416 | |
b481de9c ZY |
3417 | BUG_ON(txq_id != IWL_CMD_QUEUE_NUM); |
3418 | ||
3419 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); | |
3420 | cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; | |
3421 | ||
3422 | /* Input error checking is done when commands are added to queue. */ | |
3423 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
3424 | cmd->meta.source->u.skb = rxb->skb; | |
3425 | rxb->skb = NULL; | |
3426 | } else if (cmd->meta.u.callback && | |
3427 | !cmd->meta.u.callback(priv, cmd, rxb->skb)) | |
3428 | rxb->skb = NULL; | |
3429 | ||
91c066f2 | 3430 | iwl3945_cmd_queue_reclaim(priv, txq_id, index); |
b481de9c ZY |
3431 | |
3432 | if (!(cmd->meta.flags & CMD_ASYNC)) { | |
3433 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
3434 | wake_up_interruptible(&priv->wait_command_queue); | |
3435 | } | |
3436 | } | |
3437 | ||
3438 | /************************** RX-FUNCTIONS ****************************/ | |
3439 | /* | |
3440 | * Rx theory of operation | |
3441 | * | |
3442 | * The host allocates 32 DMA target addresses and passes the host address | |
3443 | * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is | |
3444 | * 0 to 31 | |
3445 | * | |
3446 | * Rx Queue Indexes | |
3447 | * The host/firmware share two index registers for managing the Rx buffers. | |
3448 | * | |
3449 | * The READ index maps to the first position that the firmware may be writing | |
3450 | * to -- the driver can read up to (but not including) this position and get | |
3451 | * good data. | |
3452 | * The READ index is managed by the firmware once the card is enabled. | |
3453 | * | |
3454 | * The WRITE index maps to the last position the driver has read from -- the | |
3455 | * position preceding WRITE is the last slot the firmware can place a packet. | |
3456 | * | |
3457 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
3458 | * WRITE = READ. | |
3459 | * | |
9fbab516 | 3460 | * During initialization, the host sets up the READ queue position to the first |
b481de9c ZY |
3461 | * INDEX position, and WRITE to the last (READ - 1 wrapped) |
3462 | * | |
9fbab516 | 3463 | * When the firmware places a packet in a buffer, it will advance the READ index |
b481de9c ZY |
3464 | * and fire the RX interrupt. The driver can then query the READ index and |
3465 | * process as many packets as possible, moving the WRITE index forward as it | |
3466 | * resets the Rx queue buffers with new memory. | |
3467 | * | |
3468 | * The management in the driver is as follows: | |
3469 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
3470 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
01ebd063 | 3471 | * to replenish the iwl->rxq->rx_free. |
bb8c093b | 3472 | * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the |
b481de9c ZY |
3473 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
3474 | * 'processed' and 'read' driver indexes as well) | |
3475 | * + A received packet is processed and handed to the kernel network stack, | |
3476 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
3477 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
3478 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
3479 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
3480 | * were enough free buffers and RX_STALLED is set it is cleared. | |
3481 | * | |
3482 | * | |
3483 | * Driver sequence: | |
3484 | * | |
9fbab516 BC |
3485 | * iwl3945_rx_queue_alloc() Allocates rx_free |
3486 | * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
bb8c093b | 3487 | * iwl3945_rx_queue_restock |
9fbab516 | 3488 | * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx |
b481de9c ZY |
3489 | * queue, updates firmware pointers, and updates |
3490 | * the WRITE index. If insufficient rx_free buffers | |
bb8c093b | 3491 | * are available, schedules iwl3945_rx_replenish |
b481de9c ZY |
3492 | * |
3493 | * -- enable interrupts -- | |
9fbab516 | 3494 | * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the |
b481de9c ZY |
3495 | * READ INDEX, detaching the SKB from the pool. |
3496 | * Moves the packet buffer from queue to rx_used. | |
bb8c093b | 3497 | * Calls iwl3945_rx_queue_restock to refill any empty |
b481de9c ZY |
3498 | * slots. |
3499 | * ... | |
3500 | * | |
3501 | */ | |
3502 | ||
3503 | /** | |
bb8c093b | 3504 | * iwl3945_rx_queue_space - Return number of free slots available in queue. |
b481de9c | 3505 | */ |
bb8c093b | 3506 | static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q) |
b481de9c ZY |
3507 | { |
3508 | int s = q->read - q->write; | |
3509 | if (s <= 0) | |
3510 | s += RX_QUEUE_SIZE; | |
3511 | /* keep some buffer to not confuse full and empty queue */ | |
3512 | s -= 2; | |
3513 | if (s < 0) | |
3514 | s = 0; | |
3515 | return s; | |
3516 | } | |
3517 | ||
3518 | /** | |
bb8c093b | 3519 | * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue |
b481de9c | 3520 | */ |
bb8c093b | 3521 | int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q) |
b481de9c ZY |
3522 | { |
3523 | u32 reg = 0; | |
3524 | int rc = 0; | |
3525 | unsigned long flags; | |
3526 | ||
3527 | spin_lock_irqsave(&q->lock, flags); | |
3528 | ||
3529 | if (q->need_update == 0) | |
3530 | goto exit_unlock; | |
3531 | ||
6440adb5 | 3532 | /* If power-saving is in use, make sure device is awake */ |
b481de9c | 3533 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { |
bb8c093b | 3534 | reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1); |
b481de9c ZY |
3535 | |
3536 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
bb8c093b | 3537 | iwl3945_set_bit(priv, CSR_GP_CNTRL, |
b481de9c ZY |
3538 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
3539 | goto exit_unlock; | |
3540 | } | |
3541 | ||
bb8c093b | 3542 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
3543 | if (rc) |
3544 | goto exit_unlock; | |
3545 | ||
6440adb5 | 3546 | /* Device expects a multiple of 8 */ |
bb8c093b | 3547 | iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, |
b481de9c | 3548 | q->write & ~0x7); |
bb8c093b | 3549 | iwl3945_release_nic_access(priv); |
6440adb5 CB |
3550 | |
3551 | /* Else device is assumed to be awake */ | |
b481de9c | 3552 | } else |
6440adb5 | 3553 | /* Device expects a multiple of 8 */ |
bb8c093b | 3554 | iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7); |
b481de9c ZY |
3555 | |
3556 | ||
3557 | q->need_update = 0; | |
3558 | ||
3559 | exit_unlock: | |
3560 | spin_unlock_irqrestore(&q->lock, flags); | |
3561 | return rc; | |
3562 | } | |
3563 | ||
3564 | /** | |
9fbab516 | 3565 | * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
b481de9c | 3566 | */ |
bb8c093b | 3567 | static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv, |
b481de9c ZY |
3568 | dma_addr_t dma_addr) |
3569 | { | |
3570 | return cpu_to_le32((u32)dma_addr); | |
3571 | } | |
3572 | ||
3573 | /** | |
bb8c093b | 3574 | * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool |
b481de9c | 3575 | * |
9fbab516 | 3576 | * If there are slots in the RX queue that need to be restocked, |
b481de9c | 3577 | * and we have free pre-allocated buffers, fill the ranks as much |
9fbab516 | 3578 | * as we can, pulling from rx_free. |
b481de9c ZY |
3579 | * |
3580 | * This moves the 'write' index forward to catch up with 'processed', and | |
3581 | * also updates the memory address in the firmware to reference the new | |
3582 | * target buffer. | |
3583 | */ | |
bb8c093b | 3584 | static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv) |
b481de9c | 3585 | { |
bb8c093b | 3586 | struct iwl3945_rx_queue *rxq = &priv->rxq; |
b481de9c | 3587 | struct list_head *element; |
bb8c093b | 3588 | struct iwl3945_rx_mem_buffer *rxb; |
b481de9c ZY |
3589 | unsigned long flags; |
3590 | int write, rc; | |
3591 | ||
3592 | spin_lock_irqsave(&rxq->lock, flags); | |
3593 | write = rxq->write & ~0x7; | |
bb8c093b | 3594 | while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
6440adb5 | 3595 | /* Get next free Rx buffer, remove from free list */ |
b481de9c | 3596 | element = rxq->rx_free.next; |
bb8c093b | 3597 | rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list); |
b481de9c | 3598 | list_del(element); |
6440adb5 CB |
3599 | |
3600 | /* Point to Rx buffer via next RBD in circular buffer */ | |
bb8c093b | 3601 | rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr); |
b481de9c ZY |
3602 | rxq->queue[rxq->write] = rxb; |
3603 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
3604 | rxq->free_count--; | |
3605 | } | |
3606 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3607 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
3608 | * refill it */ | |
3609 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
3610 | queue_work(priv->workqueue, &priv->rx_replenish); | |
3611 | ||
3612 | ||
6440adb5 CB |
3613 | /* If we've added more space for the firmware to place data, tell it. |
3614 | * Increment device's write pointer in multiples of 8. */ | |
b481de9c ZY |
3615 | if ((write != (rxq->write & ~0x7)) |
3616 | || (abs(rxq->write - rxq->read) > 7)) { | |
3617 | spin_lock_irqsave(&rxq->lock, flags); | |
3618 | rxq->need_update = 1; | |
3619 | spin_unlock_irqrestore(&rxq->lock, flags); | |
bb8c093b | 3620 | rc = iwl3945_rx_queue_update_write_ptr(priv, rxq); |
b481de9c ZY |
3621 | if (rc) |
3622 | return rc; | |
3623 | } | |
3624 | ||
3625 | return 0; | |
3626 | } | |
3627 | ||
3628 | /** | |
bb8c093b | 3629 | * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free |
b481de9c ZY |
3630 | * |
3631 | * When moving to rx_free an SKB is allocated for the slot. | |
3632 | * | |
bb8c093b | 3633 | * Also restock the Rx queue via iwl3945_rx_queue_restock. |
01ebd063 | 3634 | * This is called as a scheduled work item (except for during initialization) |
b481de9c | 3635 | */ |
5c0eef96 | 3636 | static void iwl3945_rx_allocate(struct iwl3945_priv *priv) |
b481de9c | 3637 | { |
bb8c093b | 3638 | struct iwl3945_rx_queue *rxq = &priv->rxq; |
b481de9c | 3639 | struct list_head *element; |
bb8c093b | 3640 | struct iwl3945_rx_mem_buffer *rxb; |
b481de9c ZY |
3641 | unsigned long flags; |
3642 | spin_lock_irqsave(&rxq->lock, flags); | |
3643 | while (!list_empty(&rxq->rx_used)) { | |
3644 | element = rxq->rx_used.next; | |
bb8c093b | 3645 | rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list); |
6440adb5 CB |
3646 | |
3647 | /* Alloc a new receive buffer */ | |
b481de9c ZY |
3648 | rxb->skb = |
3649 | alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC); | |
3650 | if (!rxb->skb) { | |
3651 | if (net_ratelimit()) | |
3652 | printk(KERN_CRIT DRV_NAME | |
3653 | ": Can not allocate SKB buffers\n"); | |
3654 | /* We don't reschedule replenish work here -- we will | |
3655 | * call the restock method and if it still needs | |
3656 | * more buffers it will schedule replenish */ | |
3657 | break; | |
3658 | } | |
12342c47 ZY |
3659 | |
3660 | /* If radiotap head is required, reserve some headroom here. | |
3661 | * The physical head count is a variable rx_stats->phy_count. | |
3662 | * We reserve 4 bytes here. Plus these extra bytes, the | |
3663 | * headroom of the physical head should be enough for the | |
3664 | * radiotap head that iwl3945 supported. See iwl3945_rt. | |
3665 | */ | |
3666 | skb_reserve(rxb->skb, 4); | |
3667 | ||
b481de9c ZY |
3668 | priv->alloc_rxb_skb++; |
3669 | list_del(element); | |
6440adb5 CB |
3670 | |
3671 | /* Get physical address of RB/SKB */ | |
b481de9c ZY |
3672 | rxb->dma_addr = |
3673 | pci_map_single(priv->pci_dev, rxb->skb->data, | |
3674 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
3675 | list_add_tail(&rxb->list, &rxq->rx_free); | |
3676 | rxq->free_count++; | |
3677 | } | |
3678 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5c0eef96 MA |
3679 | } |
3680 | ||
3681 | /* | |
3682 | * this should be called while priv->lock is locked | |
3683 | */ | |
4fd1f841 | 3684 | static void __iwl3945_rx_replenish(void *data) |
5c0eef96 MA |
3685 | { |
3686 | struct iwl3945_priv *priv = data; | |
3687 | ||
3688 | iwl3945_rx_allocate(priv); | |
3689 | iwl3945_rx_queue_restock(priv); | |
3690 | } | |
3691 | ||
3692 | ||
3693 | void iwl3945_rx_replenish(void *data) | |
3694 | { | |
3695 | struct iwl3945_priv *priv = data; | |
3696 | unsigned long flags; | |
3697 | ||
3698 | iwl3945_rx_allocate(priv); | |
b481de9c ZY |
3699 | |
3700 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 3701 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
3702 | spin_unlock_irqrestore(&priv->lock, flags); |
3703 | } | |
3704 | ||
3705 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. | |
9fbab516 | 3706 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL |
b481de9c ZY |
3707 | * This free routine walks the list of POOL entries and if SKB is set to |
3708 | * non NULL it is unmapped and freed | |
3709 | */ | |
bb8c093b | 3710 | static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq) |
b481de9c ZY |
3711 | { |
3712 | int i; | |
3713 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
3714 | if (rxq->pool[i].skb != NULL) { | |
3715 | pci_unmap_single(priv->pci_dev, | |
3716 | rxq->pool[i].dma_addr, | |
3717 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
3718 | dev_kfree_skb(rxq->pool[i].skb); | |
3719 | } | |
3720 | } | |
3721 | ||
3722 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
3723 | rxq->dma_addr); | |
3724 | rxq->bd = NULL; | |
3725 | } | |
3726 | ||
bb8c093b | 3727 | int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv) |
b481de9c | 3728 | { |
bb8c093b | 3729 | struct iwl3945_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
3730 | struct pci_dev *dev = priv->pci_dev; |
3731 | int i; | |
3732 | ||
3733 | spin_lock_init(&rxq->lock); | |
3734 | INIT_LIST_HEAD(&rxq->rx_free); | |
3735 | INIT_LIST_HEAD(&rxq->rx_used); | |
6440adb5 CB |
3736 | |
3737 | /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */ | |
b481de9c ZY |
3738 | rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr); |
3739 | if (!rxq->bd) | |
3740 | return -ENOMEM; | |
6440adb5 | 3741 | |
b481de9c ZY |
3742 | /* Fill the rx_used queue with _all_ of the Rx buffers */ |
3743 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) | |
3744 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
6440adb5 | 3745 | |
b481de9c ZY |
3746 | /* Set us so that we have processed and used all buffers, but have |
3747 | * not restocked the Rx queue with fresh buffers */ | |
3748 | rxq->read = rxq->write = 0; | |
3749 | rxq->free_count = 0; | |
3750 | rxq->need_update = 0; | |
3751 | return 0; | |
3752 | } | |
3753 | ||
bb8c093b | 3754 | void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq) |
b481de9c ZY |
3755 | { |
3756 | unsigned long flags; | |
3757 | int i; | |
3758 | spin_lock_irqsave(&rxq->lock, flags); | |
3759 | INIT_LIST_HEAD(&rxq->rx_free); | |
3760 | INIT_LIST_HEAD(&rxq->rx_used); | |
3761 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
3762 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
3763 | /* In the reset function, these buffers may have been allocated | |
3764 | * to an SKB, so we need to unmap and free potential storage */ | |
3765 | if (rxq->pool[i].skb != NULL) { | |
3766 | pci_unmap_single(priv->pci_dev, | |
3767 | rxq->pool[i].dma_addr, | |
3768 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
3769 | priv->alloc_rxb_skb--; | |
3770 | dev_kfree_skb(rxq->pool[i].skb); | |
3771 | rxq->pool[i].skb = NULL; | |
3772 | } | |
3773 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
3774 | } | |
3775 | ||
3776 | /* Set us so that we have processed and used all buffers, but have | |
3777 | * not restocked the Rx queue with fresh buffers */ | |
3778 | rxq->read = rxq->write = 0; | |
3779 | rxq->free_count = 0; | |
3780 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3781 | } | |
3782 | ||
3783 | /* Convert linear signal-to-noise ratio into dB */ | |
3784 | static u8 ratio2dB[100] = { | |
3785 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
3786 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
3787 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
3788 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
3789 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
3790 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
3791 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
3792 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
3793 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
3794 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
3795 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
3796 | }; | |
3797 | ||
3798 | /* Calculates a relative dB value from a ratio of linear | |
3799 | * (i.e. not dB) signal levels. | |
3800 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
bb8c093b | 3801 | int iwl3945_calc_db_from_ratio(int sig_ratio) |
b481de9c | 3802 | { |
221c80cf AB |
3803 | /* 1000:1 or higher just report as 60 dB */ |
3804 | if (sig_ratio >= 1000) | |
b481de9c ZY |
3805 | return 60; |
3806 | ||
221c80cf | 3807 | /* 100:1 or higher, divide by 10 and use table, |
b481de9c | 3808 | * add 20 dB to make up for divide by 10 */ |
221c80cf | 3809 | if (sig_ratio >= 100) |
3ac7f146 | 3810 | return 20 + (int)ratio2dB[sig_ratio/10]; |
b481de9c ZY |
3811 | |
3812 | /* We shouldn't see this */ | |
3813 | if (sig_ratio < 1) | |
3814 | return 0; | |
3815 | ||
3816 | /* Use table for ratios 1:1 - 99:1 */ | |
3817 | return (int)ratio2dB[sig_ratio]; | |
3818 | } | |
3819 | ||
3820 | #define PERFECT_RSSI (-20) /* dBm */ | |
3821 | #define WORST_RSSI (-95) /* dBm */ | |
3822 | #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI) | |
3823 | ||
3824 | /* Calculate an indication of rx signal quality (a percentage, not dBm!). | |
3825 | * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info | |
3826 | * about formulas used below. */ | |
bb8c093b | 3827 | int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm) |
b481de9c ZY |
3828 | { |
3829 | int sig_qual; | |
3830 | int degradation = PERFECT_RSSI - rssi_dbm; | |
3831 | ||
3832 | /* If we get a noise measurement, use signal-to-noise ratio (SNR) | |
3833 | * as indicator; formula is (signal dbm - noise dbm). | |
3834 | * SNR at or above 40 is a great signal (100%). | |
3835 | * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator. | |
3836 | * Weakest usable signal is usually 10 - 15 dB SNR. */ | |
3837 | if (noise_dbm) { | |
3838 | if (rssi_dbm - noise_dbm >= 40) | |
3839 | return 100; | |
3840 | else if (rssi_dbm < noise_dbm) | |
3841 | return 0; | |
3842 | sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2; | |
3843 | ||
3844 | /* Else use just the signal level. | |
3845 | * This formula is a least squares fit of data points collected and | |
3846 | * compared with a reference system that had a percentage (%) display | |
3847 | * for signal quality. */ | |
3848 | } else | |
3849 | sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation * | |
3850 | (15 * RSSI_RANGE + 62 * degradation)) / | |
3851 | (RSSI_RANGE * RSSI_RANGE); | |
3852 | ||
3853 | if (sig_qual > 100) | |
3854 | sig_qual = 100; | |
3855 | else if (sig_qual < 1) | |
3856 | sig_qual = 0; | |
3857 | ||
3858 | return sig_qual; | |
3859 | } | |
3860 | ||
3861 | /** | |
9fbab516 | 3862 | * iwl3945_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
3863 | * |
3864 | * Uses the priv->rx_handlers callback function array to invoke | |
3865 | * the appropriate handlers, including command responses, | |
3866 | * frame-received notifications, and other notifications. | |
3867 | */ | |
bb8c093b | 3868 | static void iwl3945_rx_handle(struct iwl3945_priv *priv) |
b481de9c | 3869 | { |
bb8c093b CH |
3870 | struct iwl3945_rx_mem_buffer *rxb; |
3871 | struct iwl3945_rx_packet *pkt; | |
3872 | struct iwl3945_rx_queue *rxq = &priv->rxq; | |
b481de9c ZY |
3873 | u32 r, i; |
3874 | int reclaim; | |
3875 | unsigned long flags; | |
5c0eef96 | 3876 | u8 fill_rx = 0; |
d68ab680 | 3877 | u32 count = 8; |
b481de9c | 3878 | |
6440adb5 CB |
3879 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
3880 | * buffer that the driver may process (last buffer filled by ucode). */ | |
bb8c093b | 3881 | r = iwl3945_hw_get_rx_read(priv); |
b481de9c ZY |
3882 | i = rxq->read; |
3883 | ||
5c0eef96 MA |
3884 | if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2)) |
3885 | fill_rx = 1; | |
b481de9c ZY |
3886 | /* Rx interrupt, but nothing sent from uCode */ |
3887 | if (i == r) | |
3888 | IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i); | |
3889 | ||
3890 | while (i != r) { | |
3891 | rxb = rxq->queue[i]; | |
3892 | ||
9fbab516 | 3893 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
3894 | * then a bug has been introduced in the queue refilling |
3895 | * routines -- catch it here */ | |
3896 | BUG_ON(rxb == NULL); | |
3897 | ||
3898 | rxq->queue[i] = NULL; | |
3899 | ||
3900 | pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr, | |
3901 | IWL_RX_BUF_SIZE, | |
3902 | PCI_DMA_FROMDEVICE); | |
bb8c093b | 3903 | pkt = (struct iwl3945_rx_packet *)rxb->skb->data; |
b481de9c ZY |
3904 | |
3905 | /* Reclaim a command buffer only if this packet is a response | |
3906 | * to a (driver-originated) command. | |
3907 | * If the packet (e.g. Rx frame) originated from uCode, | |
3908 | * there is no command buffer to reclaim. | |
3909 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
3910 | * but apparently a few don't get set; catch them here. */ | |
3911 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
3912 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
3913 | (pkt->hdr.cmd != REPLY_TX); | |
3914 | ||
3915 | /* Based on type of command response or notification, | |
3916 | * handle those that need handling via function in | |
bb8c093b | 3917 | * rx_handlers table. See iwl3945_setup_rx_handlers() */ |
b481de9c ZY |
3918 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
3919 | IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR, | |
3920 | "r = %d, i = %d, %s, 0x%02x\n", r, i, | |
3921 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
3922 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); | |
3923 | } else { | |
3924 | /* No handling needed */ | |
3925 | IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR, | |
3926 | "r %d i %d No handler needed for %s, 0x%02x\n", | |
3927 | r, i, get_cmd_string(pkt->hdr.cmd), | |
3928 | pkt->hdr.cmd); | |
3929 | } | |
3930 | ||
3931 | if (reclaim) { | |
9fbab516 BC |
3932 | /* Invoke any callbacks, transfer the skb to caller, and |
3933 | * fire off the (possibly) blocking iwl3945_send_cmd() | |
b481de9c ZY |
3934 | * as we reclaim the driver command queue */ |
3935 | if (rxb && rxb->skb) | |
bb8c093b | 3936 | iwl3945_tx_cmd_complete(priv, rxb); |
b481de9c ZY |
3937 | else |
3938 | IWL_WARNING("Claim null rxb?\n"); | |
3939 | } | |
3940 | ||
3941 | /* For now we just don't re-use anything. We can tweak this | |
3942 | * later to try and re-use notification packets and SKBs that | |
3943 | * fail to Rx correctly */ | |
3944 | if (rxb->skb != NULL) { | |
3945 | priv->alloc_rxb_skb--; | |
3946 | dev_kfree_skb_any(rxb->skb); | |
3947 | rxb->skb = NULL; | |
3948 | } | |
3949 | ||
3950 | pci_unmap_single(priv->pci_dev, rxb->dma_addr, | |
3951 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
3952 | spin_lock_irqsave(&rxq->lock, flags); | |
3953 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
3954 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3955 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
3956 | /* If there are a lot of unused frames, |
3957 | * restock the Rx queue so ucode won't assert. */ | |
3958 | if (fill_rx) { | |
3959 | count++; | |
3960 | if (count >= 8) { | |
3961 | priv->rxq.read = i; | |
3962 | __iwl3945_rx_replenish(priv); | |
3963 | count = 0; | |
3964 | } | |
3965 | } | |
b481de9c ZY |
3966 | } |
3967 | ||
3968 | /* Backtrack one entry */ | |
3969 | priv->rxq.read = i; | |
bb8c093b | 3970 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
3971 | } |
3972 | ||
6440adb5 CB |
3973 | /** |
3974 | * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware | |
3975 | */ | |
bb8c093b CH |
3976 | static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv, |
3977 | struct iwl3945_tx_queue *txq) | |
b481de9c ZY |
3978 | { |
3979 | u32 reg = 0; | |
3980 | int rc = 0; | |
3981 | int txq_id = txq->q.id; | |
3982 | ||
3983 | if (txq->need_update == 0) | |
3984 | return rc; | |
3985 | ||
3986 | /* if we're trying to save power */ | |
3987 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
3988 | /* wake up nic if it's powered down ... | |
3989 | * uCode will wake up, and interrupt us again, so next | |
3990 | * time we'll skip this part. */ | |
bb8c093b | 3991 | reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1); |
b481de9c ZY |
3992 | |
3993 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
3994 | IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg); | |
bb8c093b | 3995 | iwl3945_set_bit(priv, CSR_GP_CNTRL, |
b481de9c ZY |
3996 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
3997 | return rc; | |
3998 | } | |
3999 | ||
4000 | /* restore this queue's parameters in nic hardware. */ | |
bb8c093b | 4001 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
4002 | if (rc) |
4003 | return rc; | |
bb8c093b | 4004 | iwl3945_write_direct32(priv, HBUS_TARG_WRPTR, |
fc4b6853 | 4005 | txq->q.write_ptr | (txq_id << 8)); |
bb8c093b | 4006 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4007 | |
4008 | /* else not in power-save mode, uCode will never sleep when we're | |
4009 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
4010 | } else | |
bb8c093b | 4011 | iwl3945_write32(priv, HBUS_TARG_WRPTR, |
fc4b6853 | 4012 | txq->q.write_ptr | (txq_id << 8)); |
b481de9c ZY |
4013 | |
4014 | txq->need_update = 0; | |
4015 | ||
4016 | return rc; | |
4017 | } | |
4018 | ||
c8b0e6e1 | 4019 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 4020 | static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon) |
b481de9c | 4021 | { |
0795af57 JP |
4022 | DECLARE_MAC_BUF(mac); |
4023 | ||
b481de9c | 4024 | IWL_DEBUG_RADIO("RX CONFIG:\n"); |
bb8c093b | 4025 | iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
b481de9c ZY |
4026 | IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
4027 | IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
4028 | IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n", | |
4029 | le32_to_cpu(rxon->filter_flags)); | |
4030 | IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type); | |
4031 | IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n", | |
4032 | rxon->ofdm_basic_rates); | |
4033 | IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); | |
0795af57 JP |
4034 | IWL_DEBUG_RADIO("u8[6] node_addr: %s\n", |
4035 | print_mac(mac, rxon->node_addr)); | |
4036 | IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n", | |
4037 | print_mac(mac, rxon->bssid_addr)); | |
b481de9c ZY |
4038 | IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); |
4039 | } | |
4040 | #endif | |
4041 | ||
bb8c093b | 4042 | static void iwl3945_enable_interrupts(struct iwl3945_priv *priv) |
b481de9c ZY |
4043 | { |
4044 | IWL_DEBUG_ISR("Enabling interrupts\n"); | |
4045 | set_bit(STATUS_INT_ENABLED, &priv->status); | |
bb8c093b | 4046 | iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK); |
b481de9c ZY |
4047 | } |
4048 | ||
0359facc MA |
4049 | |
4050 | /* call this function to flush any scheduled tasklet */ | |
4051 | static inline void iwl_synchronize_irq(struct iwl3945_priv *priv) | |
4052 | { | |
4053 | /* wait to make sure we flush pedding tasklet*/ | |
4054 | synchronize_irq(priv->pci_dev->irq); | |
4055 | tasklet_kill(&priv->irq_tasklet); | |
4056 | } | |
4057 | ||
4058 | ||
bb8c093b | 4059 | static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv) |
b481de9c ZY |
4060 | { |
4061 | clear_bit(STATUS_INT_ENABLED, &priv->status); | |
4062 | ||
4063 | /* disable interrupts from uCode/NIC to host */ | |
bb8c093b | 4064 | iwl3945_write32(priv, CSR_INT_MASK, 0x00000000); |
b481de9c ZY |
4065 | |
4066 | /* acknowledge/clear/reset any interrupts still pending | |
4067 | * from uCode or flow handler (Rx/Tx DMA) */ | |
bb8c093b CH |
4068 | iwl3945_write32(priv, CSR_INT, 0xffffffff); |
4069 | iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff); | |
b481de9c ZY |
4070 | IWL_DEBUG_ISR("Disabled interrupts\n"); |
4071 | } | |
4072 | ||
4073 | static const char *desc_lookup(int i) | |
4074 | { | |
4075 | switch (i) { | |
4076 | case 1: | |
4077 | return "FAIL"; | |
4078 | case 2: | |
4079 | return "BAD_PARAM"; | |
4080 | case 3: | |
4081 | return "BAD_CHECKSUM"; | |
4082 | case 4: | |
4083 | return "NMI_INTERRUPT"; | |
4084 | case 5: | |
4085 | return "SYSASSERT"; | |
4086 | case 6: | |
4087 | return "FATAL_ERROR"; | |
4088 | } | |
4089 | ||
4090 | return "UNKNOWN"; | |
4091 | } | |
4092 | ||
4093 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
4094 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
4095 | ||
bb8c093b | 4096 | static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv) |
b481de9c ZY |
4097 | { |
4098 | u32 i; | |
4099 | u32 desc, time, count, base, data1; | |
4100 | u32 blink1, blink2, ilink1, ilink2; | |
4101 | int rc; | |
4102 | ||
4103 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
4104 | ||
bb8c093b | 4105 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
b481de9c ZY |
4106 | IWL_ERROR("Not valid error log pointer 0x%08X\n", base); |
4107 | return; | |
4108 | } | |
4109 | ||
bb8c093b | 4110 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
4111 | if (rc) { |
4112 | IWL_WARNING("Can not read from adapter at this time.\n"); | |
4113 | return; | |
4114 | } | |
4115 | ||
bb8c093b | 4116 | count = iwl3945_read_targ_mem(priv, base); |
b481de9c ZY |
4117 | |
4118 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
4119 | IWL_ERROR("Start IWL Error Log Dump:\n"); | |
2acae16e | 4120 | IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count); |
b481de9c ZY |
4121 | } |
4122 | ||
4123 | IWL_ERROR("Desc Time asrtPC blink2 " | |
4124 | "ilink1 nmiPC Line\n"); | |
4125 | for (i = ERROR_START_OFFSET; | |
4126 | i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET; | |
4127 | i += ERROR_ELEM_SIZE) { | |
bb8c093b | 4128 | desc = iwl3945_read_targ_mem(priv, base + i); |
b481de9c | 4129 | time = |
bb8c093b | 4130 | iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32)); |
b481de9c | 4131 | blink1 = |
bb8c093b | 4132 | iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32)); |
b481de9c | 4133 | blink2 = |
bb8c093b | 4134 | iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32)); |
b481de9c | 4135 | ilink1 = |
bb8c093b | 4136 | iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32)); |
b481de9c | 4137 | ilink2 = |
bb8c093b | 4138 | iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32)); |
b481de9c | 4139 | data1 = |
bb8c093b | 4140 | iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32)); |
b481de9c ZY |
4141 | |
4142 | IWL_ERROR | |
4143 | ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n", | |
4144 | desc_lookup(desc), desc, time, blink1, blink2, | |
4145 | ilink1, ilink2, data1); | |
4146 | } | |
4147 | ||
bb8c093b | 4148 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4149 | |
4150 | } | |
4151 | ||
f58177b9 | 4152 | #define EVENT_START_OFFSET (6 * sizeof(u32)) |
b481de9c ZY |
4153 | |
4154 | /** | |
bb8c093b | 4155 | * iwl3945_print_event_log - Dump error event log to syslog |
b481de9c | 4156 | * |
bb8c093b | 4157 | * NOTE: Must be called with iwl3945_grab_nic_access() already obtained! |
b481de9c | 4158 | */ |
bb8c093b | 4159 | static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx, |
b481de9c ZY |
4160 | u32 num_events, u32 mode) |
4161 | { | |
4162 | u32 i; | |
4163 | u32 base; /* SRAM byte address of event log header */ | |
4164 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
4165 | u32 ptr; /* SRAM byte address of log data */ | |
4166 | u32 ev, time, data; /* event log data */ | |
4167 | ||
4168 | if (num_events == 0) | |
4169 | return; | |
4170 | ||
4171 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
4172 | ||
4173 | if (mode == 0) | |
4174 | event_size = 2 * sizeof(u32); | |
4175 | else | |
4176 | event_size = 3 * sizeof(u32); | |
4177 | ||
4178 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
4179 | ||
4180 | /* "time" is actually "data" for mode 0 (no timestamp). | |
4181 | * place event id # at far right for easier visual parsing. */ | |
4182 | for (i = 0; i < num_events; i++) { | |
bb8c093b | 4183 | ev = iwl3945_read_targ_mem(priv, ptr); |
b481de9c | 4184 | ptr += sizeof(u32); |
bb8c093b | 4185 | time = iwl3945_read_targ_mem(priv, ptr); |
b481de9c ZY |
4186 | ptr += sizeof(u32); |
4187 | if (mode == 0) | |
4188 | IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */ | |
4189 | else { | |
bb8c093b | 4190 | data = iwl3945_read_targ_mem(priv, ptr); |
b481de9c ZY |
4191 | ptr += sizeof(u32); |
4192 | IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev); | |
4193 | } | |
4194 | } | |
4195 | } | |
4196 | ||
bb8c093b | 4197 | static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv) |
b481de9c ZY |
4198 | { |
4199 | int rc; | |
4200 | u32 base; /* SRAM byte address of event log header */ | |
4201 | u32 capacity; /* event log capacity in # entries */ | |
4202 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
4203 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
4204 | u32 next_entry; /* index of next entry to be written by uCode */ | |
4205 | u32 size; /* # entries that we'll print */ | |
4206 | ||
4207 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
bb8c093b | 4208 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
b481de9c ZY |
4209 | IWL_ERROR("Invalid event log pointer 0x%08X\n", base); |
4210 | return; | |
4211 | } | |
4212 | ||
bb8c093b | 4213 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
4214 | if (rc) { |
4215 | IWL_WARNING("Can not read from adapter at this time.\n"); | |
4216 | return; | |
4217 | } | |
4218 | ||
4219 | /* event log header */ | |
bb8c093b CH |
4220 | capacity = iwl3945_read_targ_mem(priv, base); |
4221 | mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
4222 | num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
4223 | next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
b481de9c ZY |
4224 | |
4225 | size = num_wraps ? capacity : next_entry; | |
4226 | ||
4227 | /* bail out if nothing in log */ | |
4228 | if (size == 0) { | |
583fab37 | 4229 | IWL_ERROR("Start IWL Event Log Dump: nothing in log\n"); |
bb8c093b | 4230 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4231 | return; |
4232 | } | |
4233 | ||
583fab37 | 4234 | IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n", |
b481de9c ZY |
4235 | size, num_wraps); |
4236 | ||
4237 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
4238 | * i.e the next one that uCode would fill. */ | |
4239 | if (num_wraps) | |
bb8c093b | 4240 | iwl3945_print_event_log(priv, next_entry, |
b481de9c ZY |
4241 | capacity - next_entry, mode); |
4242 | ||
4243 | /* (then/else) start at top of log */ | |
bb8c093b | 4244 | iwl3945_print_event_log(priv, 0, next_entry, mode); |
b481de9c | 4245 | |
bb8c093b | 4246 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4247 | } |
4248 | ||
4249 | /** | |
bb8c093b | 4250 | * iwl3945_irq_handle_error - called for HW or SW error interrupt from card |
b481de9c | 4251 | */ |
bb8c093b | 4252 | static void iwl3945_irq_handle_error(struct iwl3945_priv *priv) |
b481de9c | 4253 | { |
bb8c093b | 4254 | /* Set the FW error flag -- cleared on iwl3945_down */ |
b481de9c ZY |
4255 | set_bit(STATUS_FW_ERROR, &priv->status); |
4256 | ||
4257 | /* Cancel currently queued command. */ | |
4258 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
4259 | ||
c8b0e6e1 | 4260 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
4261 | if (iwl3945_debug_level & IWL_DL_FW_ERRORS) { |
4262 | iwl3945_dump_nic_error_log(priv); | |
4263 | iwl3945_dump_nic_event_log(priv); | |
4264 | iwl3945_print_rx_config_cmd(&priv->staging_rxon); | |
b481de9c ZY |
4265 | } |
4266 | #endif | |
4267 | ||
4268 | wake_up_interruptible(&priv->wait_command_queue); | |
4269 | ||
4270 | /* Keep the restart process from trying to send host | |
4271 | * commands by clearing the INIT status bit */ | |
4272 | clear_bit(STATUS_READY, &priv->status); | |
4273 | ||
4274 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
4275 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS, | |
4276 | "Restarting adapter due to uCode error.\n"); | |
4277 | ||
bb8c093b | 4278 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
4279 | memcpy(&priv->recovery_rxon, &priv->active_rxon, |
4280 | sizeof(priv->recovery_rxon)); | |
4281 | priv->error_recovering = 1; | |
4282 | } | |
4283 | queue_work(priv->workqueue, &priv->restart); | |
4284 | } | |
4285 | } | |
4286 | ||
bb8c093b | 4287 | static void iwl3945_error_recovery(struct iwl3945_priv *priv) |
b481de9c ZY |
4288 | { |
4289 | unsigned long flags; | |
4290 | ||
4291 | memcpy(&priv->staging_rxon, &priv->recovery_rxon, | |
4292 | sizeof(priv->staging_rxon)); | |
4293 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 4294 | iwl3945_commit_rxon(priv); |
b481de9c | 4295 | |
bb8c093b | 4296 | iwl3945_add_station(priv, priv->bssid, 1, 0); |
b481de9c ZY |
4297 | |
4298 | spin_lock_irqsave(&priv->lock, flags); | |
4299 | priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id); | |
4300 | priv->error_recovering = 0; | |
4301 | spin_unlock_irqrestore(&priv->lock, flags); | |
4302 | } | |
4303 | ||
bb8c093b | 4304 | static void iwl3945_irq_tasklet(struct iwl3945_priv *priv) |
b481de9c ZY |
4305 | { |
4306 | u32 inta, handled = 0; | |
4307 | u32 inta_fh; | |
4308 | unsigned long flags; | |
c8b0e6e1 | 4309 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
4310 | u32 inta_mask; |
4311 | #endif | |
4312 | ||
4313 | spin_lock_irqsave(&priv->lock, flags); | |
4314 | ||
4315 | /* Ack/clear/reset pending uCode interrupts. | |
4316 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
4317 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
bb8c093b CH |
4318 | inta = iwl3945_read32(priv, CSR_INT); |
4319 | iwl3945_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
4320 | |
4321 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
4322 | * Any new interrupts that happen after this, either while we're | |
4323 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
bb8c093b CH |
4324 | inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS); |
4325 | iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 4326 | |
c8b0e6e1 | 4327 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 4328 | if (iwl3945_debug_level & IWL_DL_ISR) { |
9fbab516 BC |
4329 | /* just for debug */ |
4330 | inta_mask = iwl3945_read32(priv, CSR_INT_MASK); | |
b481de9c ZY |
4331 | IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
4332 | inta, inta_mask, inta_fh); | |
4333 | } | |
4334 | #endif | |
4335 | ||
4336 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
4337 | * atomic, make sure that inta covers all the interrupts that | |
4338 | * we've discovered, even if FH interrupt came in just after | |
4339 | * reading CSR_INT. */ | |
6f83eaa1 | 4340 | if (inta_fh & CSR39_FH_INT_RX_MASK) |
b481de9c | 4341 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 4342 | if (inta_fh & CSR39_FH_INT_TX_MASK) |
b481de9c ZY |
4343 | inta |= CSR_INT_BIT_FH_TX; |
4344 | ||
4345 | /* Now service all interrupt bits discovered above. */ | |
4346 | if (inta & CSR_INT_BIT_HW_ERR) { | |
4347 | IWL_ERROR("Microcode HW error detected. Restarting.\n"); | |
4348 | ||
4349 | /* Tell the device to stop sending interrupts */ | |
bb8c093b | 4350 | iwl3945_disable_interrupts(priv); |
b481de9c | 4351 | |
bb8c093b | 4352 | iwl3945_irq_handle_error(priv); |
b481de9c ZY |
4353 | |
4354 | handled |= CSR_INT_BIT_HW_ERR; | |
4355 | ||
4356 | spin_unlock_irqrestore(&priv->lock, flags); | |
4357 | ||
4358 | return; | |
4359 | } | |
4360 | ||
c8b0e6e1 | 4361 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 4362 | if (iwl3945_debug_level & (IWL_DL_ISR)) { |
b481de9c | 4363 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
25c03d8e JP |
4364 | if (inta & CSR_INT_BIT_SCD) |
4365 | IWL_DEBUG_ISR("Scheduler finished to transmit " | |
4366 | "the frame/frames.\n"); | |
b481de9c ZY |
4367 | |
4368 | /* Alive notification via Rx interrupt will do the real work */ | |
4369 | if (inta & CSR_INT_BIT_ALIVE) | |
4370 | IWL_DEBUG_ISR("Alive interrupt\n"); | |
4371 | } | |
4372 | #endif | |
4373 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 4374 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c ZY |
4375 | |
4376 | /* HW RF KILL switch toggled (4965 only) */ | |
4377 | if (inta & CSR_INT_BIT_RF_KILL) { | |
4378 | int hw_rf_kill = 0; | |
bb8c093b | 4379 | if (!(iwl3945_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
4380 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
4381 | hw_rf_kill = 1; | |
4382 | ||
4383 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR, | |
4384 | "RF_KILL bit toggled to %s.\n", | |
4385 | hw_rf_kill ? "disable radio":"enable radio"); | |
4386 | ||
4387 | /* Queue restart only if RF_KILL switch was set to "kill" | |
4388 | * when we loaded driver, and is now set to "enable". | |
4389 | * After we're Alive, RF_KILL gets handled by | |
3230455d | 4390 | * iwl3945_rx_card_state_notif() */ |
53e49093 ZY |
4391 | if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) { |
4392 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
b481de9c | 4393 | queue_work(priv->workqueue, &priv->restart); |
53e49093 | 4394 | } |
b481de9c ZY |
4395 | |
4396 | handled |= CSR_INT_BIT_RF_KILL; | |
4397 | } | |
4398 | ||
4399 | /* Chip got too hot and stopped itself (4965 only) */ | |
4400 | if (inta & CSR_INT_BIT_CT_KILL) { | |
4401 | IWL_ERROR("Microcode CT kill error detected.\n"); | |
4402 | handled |= CSR_INT_BIT_CT_KILL; | |
4403 | } | |
4404 | ||
4405 | /* Error detected by uCode */ | |
4406 | if (inta & CSR_INT_BIT_SW_ERR) { | |
4407 | IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n", | |
4408 | inta); | |
bb8c093b | 4409 | iwl3945_irq_handle_error(priv); |
b481de9c ZY |
4410 | handled |= CSR_INT_BIT_SW_ERR; |
4411 | } | |
4412 | ||
4413 | /* uCode wakes up after power-down sleep */ | |
4414 | if (inta & CSR_INT_BIT_WAKEUP) { | |
4415 | IWL_DEBUG_ISR("Wakeup interrupt\n"); | |
bb8c093b CH |
4416 | iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq); |
4417 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]); | |
4418 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]); | |
4419 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]); | |
4420 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]); | |
4421 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]); | |
4422 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c ZY |
4423 | |
4424 | handled |= CSR_INT_BIT_WAKEUP; | |
4425 | } | |
4426 | ||
4427 | /* All uCode command responses, including Tx command responses, | |
4428 | * Rx "responses" (frame-received notification), and other | |
4429 | * notifications from uCode come through here*/ | |
4430 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
bb8c093b | 4431 | iwl3945_rx_handle(priv); |
b481de9c ZY |
4432 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
4433 | } | |
4434 | ||
4435 | if (inta & CSR_INT_BIT_FH_TX) { | |
4436 | IWL_DEBUG_ISR("Tx interrupt\n"); | |
4437 | ||
bb8c093b CH |
4438 | iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); |
4439 | if (!iwl3945_grab_nic_access(priv)) { | |
4440 | iwl3945_write_direct32(priv, | |
b481de9c ZY |
4441 | FH_TCSR_CREDIT |
4442 | (ALM_FH_SRVC_CHNL), 0x0); | |
bb8c093b | 4443 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4444 | } |
4445 | handled |= CSR_INT_BIT_FH_TX; | |
4446 | } | |
4447 | ||
4448 | if (inta & ~handled) | |
4449 | IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
4450 | ||
4451 | if (inta & ~CSR_INI_SET_MASK) { | |
4452 | IWL_WARNING("Disabled INTA bits 0x%08x were pending\n", | |
4453 | inta & ~CSR_INI_SET_MASK); | |
4454 | IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh); | |
4455 | } | |
4456 | ||
4457 | /* Re-enable all interrupts */ | |
0359facc MA |
4458 | /* only Re-enable if disabled by irq */ |
4459 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
4460 | iwl3945_enable_interrupts(priv); | |
b481de9c | 4461 | |
c8b0e6e1 | 4462 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
4463 | if (iwl3945_debug_level & (IWL_DL_ISR)) { |
4464 | inta = iwl3945_read32(priv, CSR_INT); | |
4465 | inta_mask = iwl3945_read32(priv, CSR_INT_MASK); | |
4466 | inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
4467 | IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
4468 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | |
4469 | } | |
4470 | #endif | |
4471 | spin_unlock_irqrestore(&priv->lock, flags); | |
4472 | } | |
4473 | ||
bb8c093b | 4474 | static irqreturn_t iwl3945_isr(int irq, void *data) |
b481de9c | 4475 | { |
bb8c093b | 4476 | struct iwl3945_priv *priv = data; |
b481de9c ZY |
4477 | u32 inta, inta_mask; |
4478 | u32 inta_fh; | |
4479 | if (!priv) | |
4480 | return IRQ_NONE; | |
4481 | ||
4482 | spin_lock(&priv->lock); | |
4483 | ||
4484 | /* Disable (but don't clear!) interrupts here to avoid | |
4485 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
4486 | * If we have something to service, the tasklet will re-enable ints. | |
4487 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
bb8c093b CH |
4488 | inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */ |
4489 | iwl3945_write32(priv, CSR_INT_MASK, 0x00000000); | |
b481de9c ZY |
4490 | |
4491 | /* Discover which interrupts are active/pending */ | |
bb8c093b CH |
4492 | inta = iwl3945_read32(priv, CSR_INT); |
4493 | inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
4494 | |
4495 | /* Ignore interrupt if there's nothing in NIC to service. | |
4496 | * This may be due to IRQ shared with another device, | |
4497 | * or due to sporadic interrupts thrown from our NIC. */ | |
4498 | if (!inta && !inta_fh) { | |
4499 | IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n"); | |
4500 | goto none; | |
4501 | } | |
4502 | ||
4503 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
4504 | /* Hardware disappeared */ | |
4505 | IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta); | |
cb4da1a3 | 4506 | goto unplugged; |
b481de9c ZY |
4507 | } |
4508 | ||
4509 | IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | |
4510 | inta, inta_mask, inta_fh); | |
4511 | ||
25c03d8e JP |
4512 | inta &= ~CSR_INT_BIT_SCD; |
4513 | ||
bb8c093b | 4514 | /* iwl3945_irq_tasklet() will service interrupts and re-enable them */ |
25c03d8e JP |
4515 | if (likely(inta || inta_fh)) |
4516 | tasklet_schedule(&priv->irq_tasklet); | |
cb4da1a3 | 4517 | unplugged: |
b481de9c ZY |
4518 | spin_unlock(&priv->lock); |
4519 | ||
4520 | return IRQ_HANDLED; | |
4521 | ||
4522 | none: | |
4523 | /* re-enable interrupts here since we don't have anything to service. */ | |
0359facc MA |
4524 | /* only Re-enable if disabled by irq */ |
4525 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
4526 | iwl3945_enable_interrupts(priv); | |
b481de9c ZY |
4527 | spin_unlock(&priv->lock); |
4528 | return IRQ_NONE; | |
4529 | } | |
4530 | ||
4531 | /************************** EEPROM BANDS **************************** | |
4532 | * | |
bb8c093b | 4533 | * The iwl3945_eeprom_band definitions below provide the mapping from the |
b481de9c ZY |
4534 | * EEPROM contents to the specific channel number supported for each |
4535 | * band. | |
4536 | * | |
bb8c093b | 4537 | * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3 |
b481de9c ZY |
4538 | * definition below maps to physical channel 42 in the 5.2GHz spectrum. |
4539 | * The specific geography and calibration information for that channel | |
4540 | * is contained in the eeprom map itself. | |
4541 | * | |
4542 | * During init, we copy the eeprom information and channel map | |
4543 | * information into priv->channel_info_24/52 and priv->channel_map_24/52 | |
4544 | * | |
4545 | * channel_map_24/52 provides the index in the channel_info array for a | |
4546 | * given channel. We have to have two separate maps as there is channel | |
4547 | * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and | |
4548 | * band_2 | |
4549 | * | |
4550 | * A value of 0xff stored in the channel_map indicates that the channel | |
4551 | * is not supported by the hardware at all. | |
4552 | * | |
4553 | * A value of 0xfe in the channel_map indicates that the channel is not | |
4554 | * valid for Tx with the current hardware. This means that | |
4555 | * while the system can tune and receive on a given channel, it may not | |
4556 | * be able to associate or transmit any frames on that | |
4557 | * channel. There is no corresponding channel information for that | |
4558 | * entry. | |
4559 | * | |
4560 | *********************************************************************/ | |
4561 | ||
4562 | /* 2.4 GHz */ | |
bb8c093b | 4563 | static const u8 iwl3945_eeprom_band_1[14] = { |
b481de9c ZY |
4564 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 |
4565 | }; | |
4566 | ||
4567 | /* 5.2 GHz bands */ | |
9fbab516 | 4568 | static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */ |
b481de9c ZY |
4569 | 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 |
4570 | }; | |
4571 | ||
9fbab516 | 4572 | static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */ |
b481de9c ZY |
4573 | 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 |
4574 | }; | |
4575 | ||
bb8c093b | 4576 | static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */ |
b481de9c ZY |
4577 | 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 |
4578 | }; | |
4579 | ||
bb8c093b | 4580 | static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */ |
b481de9c ZY |
4581 | 145, 149, 153, 157, 161, 165 |
4582 | }; | |
4583 | ||
bb8c093b | 4584 | static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band, |
b481de9c | 4585 | int *eeprom_ch_count, |
bb8c093b | 4586 | const struct iwl3945_eeprom_channel |
b481de9c ZY |
4587 | **eeprom_ch_info, |
4588 | const u8 **eeprom_ch_index) | |
4589 | { | |
4590 | switch (band) { | |
4591 | case 1: /* 2.4GHz band */ | |
bb8c093b | 4592 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1); |
b481de9c | 4593 | *eeprom_ch_info = priv->eeprom.band_1_channels; |
bb8c093b | 4594 | *eeprom_ch_index = iwl3945_eeprom_band_1; |
b481de9c | 4595 | break; |
9fbab516 | 4596 | case 2: /* 4.9GHz band */ |
bb8c093b | 4597 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2); |
b481de9c | 4598 | *eeprom_ch_info = priv->eeprom.band_2_channels; |
bb8c093b | 4599 | *eeprom_ch_index = iwl3945_eeprom_band_2; |
b481de9c ZY |
4600 | break; |
4601 | case 3: /* 5.2GHz band */ | |
bb8c093b | 4602 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3); |
b481de9c | 4603 | *eeprom_ch_info = priv->eeprom.band_3_channels; |
bb8c093b | 4604 | *eeprom_ch_index = iwl3945_eeprom_band_3; |
b481de9c | 4605 | break; |
9fbab516 | 4606 | case 4: /* 5.5GHz band */ |
bb8c093b | 4607 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4); |
b481de9c | 4608 | *eeprom_ch_info = priv->eeprom.band_4_channels; |
bb8c093b | 4609 | *eeprom_ch_index = iwl3945_eeprom_band_4; |
b481de9c | 4610 | break; |
9fbab516 | 4611 | case 5: /* 5.7GHz band */ |
bb8c093b | 4612 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5); |
b481de9c | 4613 | *eeprom_ch_info = priv->eeprom.band_5_channels; |
bb8c093b | 4614 | *eeprom_ch_index = iwl3945_eeprom_band_5; |
b481de9c ZY |
4615 | break; |
4616 | default: | |
4617 | BUG(); | |
4618 | return; | |
4619 | } | |
4620 | } | |
4621 | ||
6440adb5 CB |
4622 | /** |
4623 | * iwl3945_get_channel_info - Find driver's private channel info | |
4624 | * | |
4625 | * Based on band and channel number. | |
4626 | */ | |
bb8c093b | 4627 | const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv, |
8318d78a | 4628 | enum ieee80211_band band, u16 channel) |
b481de9c ZY |
4629 | { |
4630 | int i; | |
4631 | ||
8318d78a JB |
4632 | switch (band) { |
4633 | case IEEE80211_BAND_5GHZ: | |
b481de9c ZY |
4634 | for (i = 14; i < priv->channel_count; i++) { |
4635 | if (priv->channel_info[i].channel == channel) | |
4636 | return &priv->channel_info[i]; | |
4637 | } | |
4638 | break; | |
4639 | ||
8318d78a | 4640 | case IEEE80211_BAND_2GHZ: |
b481de9c ZY |
4641 | if (channel >= 1 && channel <= 14) |
4642 | return &priv->channel_info[channel - 1]; | |
4643 | break; | |
8318d78a JB |
4644 | case IEEE80211_NUM_BANDS: |
4645 | WARN_ON(1); | |
b481de9c ZY |
4646 | } |
4647 | ||
4648 | return NULL; | |
4649 | } | |
4650 | ||
4651 | #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \ | |
4652 | ? # x " " : "") | |
4653 | ||
6440adb5 CB |
4654 | /** |
4655 | * iwl3945_init_channel_map - Set up driver's info for all possible channels | |
4656 | */ | |
bb8c093b | 4657 | static int iwl3945_init_channel_map(struct iwl3945_priv *priv) |
b481de9c ZY |
4658 | { |
4659 | int eeprom_ch_count = 0; | |
4660 | const u8 *eeprom_ch_index = NULL; | |
bb8c093b | 4661 | const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL; |
b481de9c | 4662 | int band, ch; |
bb8c093b | 4663 | struct iwl3945_channel_info *ch_info; |
b481de9c ZY |
4664 | |
4665 | if (priv->channel_count) { | |
4666 | IWL_DEBUG_INFO("Channel map already initialized.\n"); | |
4667 | return 0; | |
4668 | } | |
4669 | ||
4670 | if (priv->eeprom.version < 0x2f) { | |
4671 | IWL_WARNING("Unsupported EEPROM version: 0x%04X\n", | |
4672 | priv->eeprom.version); | |
4673 | return -EINVAL; | |
4674 | } | |
4675 | ||
4676 | IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n"); | |
4677 | ||
4678 | priv->channel_count = | |
bb8c093b CH |
4679 | ARRAY_SIZE(iwl3945_eeprom_band_1) + |
4680 | ARRAY_SIZE(iwl3945_eeprom_band_2) + | |
4681 | ARRAY_SIZE(iwl3945_eeprom_band_3) + | |
4682 | ARRAY_SIZE(iwl3945_eeprom_band_4) + | |
4683 | ARRAY_SIZE(iwl3945_eeprom_band_5); | |
b481de9c ZY |
4684 | |
4685 | IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count); | |
4686 | ||
bb8c093b | 4687 | priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) * |
b481de9c ZY |
4688 | priv->channel_count, GFP_KERNEL); |
4689 | if (!priv->channel_info) { | |
4690 | IWL_ERROR("Could not allocate channel_info\n"); | |
4691 | priv->channel_count = 0; | |
4692 | return -ENOMEM; | |
4693 | } | |
4694 | ||
4695 | ch_info = priv->channel_info; | |
4696 | ||
4697 | /* Loop through the 5 EEPROM bands adding them in order to the | |
4698 | * channel map we maintain (that contains additional information than | |
4699 | * what just in the EEPROM) */ | |
4700 | for (band = 1; band <= 5; band++) { | |
4701 | ||
bb8c093b | 4702 | iwl3945_init_band_reference(priv, band, &eeprom_ch_count, |
b481de9c ZY |
4703 | &eeprom_ch_info, &eeprom_ch_index); |
4704 | ||
4705 | /* Loop through each band adding each of the channels */ | |
4706 | for (ch = 0; ch < eeprom_ch_count; ch++) { | |
4707 | ch_info->channel = eeprom_ch_index[ch]; | |
8318d78a JB |
4708 | ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ : |
4709 | IEEE80211_BAND_5GHZ; | |
b481de9c ZY |
4710 | |
4711 | /* permanently store EEPROM's channel regulatory flags | |
4712 | * and max power in channel info database. */ | |
4713 | ch_info->eeprom = eeprom_ch_info[ch]; | |
4714 | ||
4715 | /* Copy the run-time flags so they are there even on | |
4716 | * invalid channels */ | |
4717 | ch_info->flags = eeprom_ch_info[ch].flags; | |
4718 | ||
4719 | if (!(is_channel_valid(ch_info))) { | |
4720 | IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - " | |
4721 | "No traffic\n", | |
4722 | ch_info->channel, | |
4723 | ch_info->flags, | |
4724 | is_channel_a_band(ch_info) ? | |
4725 | "5.2" : "2.4"); | |
4726 | ch_info++; | |
4727 | continue; | |
4728 | } | |
4729 | ||
4730 | /* Initialize regulatory-based run-time data */ | |
4731 | ch_info->max_power_avg = ch_info->curr_txpow = | |
4732 | eeprom_ch_info[ch].max_power_avg; | |
4733 | ch_info->scan_power = eeprom_ch_info[ch].max_power_avg; | |
4734 | ch_info->min_power = 0; | |
4735 | ||
fe7c4040 | 4736 | IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x" |
b481de9c ZY |
4737 | " %ddBm): Ad-Hoc %ssupported\n", |
4738 | ch_info->channel, | |
4739 | is_channel_a_band(ch_info) ? | |
4740 | "5.2" : "2.4", | |
8211ef78 | 4741 | CHECK_AND_PRINT(VALID), |
b481de9c ZY |
4742 | CHECK_AND_PRINT(IBSS), |
4743 | CHECK_AND_PRINT(ACTIVE), | |
4744 | CHECK_AND_PRINT(RADAR), | |
4745 | CHECK_AND_PRINT(WIDE), | |
b481de9c ZY |
4746 | CHECK_AND_PRINT(DFS), |
4747 | eeprom_ch_info[ch].flags, | |
4748 | eeprom_ch_info[ch].max_power_avg, | |
4749 | ((eeprom_ch_info[ch]. | |
4750 | flags & EEPROM_CHANNEL_IBSS) | |
4751 | && !(eeprom_ch_info[ch]. | |
4752 | flags & EEPROM_CHANNEL_RADAR)) | |
4753 | ? "" : "not "); | |
4754 | ||
4755 | /* Set the user_txpower_limit to the highest power | |
4756 | * supported by any channel */ | |
4757 | if (eeprom_ch_info[ch].max_power_avg > | |
4758 | priv->user_txpower_limit) | |
4759 | priv->user_txpower_limit = | |
4760 | eeprom_ch_info[ch].max_power_avg; | |
4761 | ||
4762 | ch_info++; | |
4763 | } | |
4764 | } | |
4765 | ||
6440adb5 | 4766 | /* Set up txpower settings in driver for all channels */ |
b481de9c ZY |
4767 | if (iwl3945_txpower_set_from_eeprom(priv)) |
4768 | return -EIO; | |
4769 | ||
4770 | return 0; | |
4771 | } | |
4772 | ||
849e0dce RC |
4773 | /* |
4774 | * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map | |
4775 | */ | |
4776 | static void iwl3945_free_channel_map(struct iwl3945_priv *priv) | |
4777 | { | |
4778 | kfree(priv->channel_info); | |
4779 | priv->channel_count = 0; | |
4780 | } | |
4781 | ||
b481de9c ZY |
4782 | /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after |
4783 | * sending probe req. This should be set long enough to hear probe responses | |
4784 | * from more than one AP. */ | |
f9340520 AK |
4785 | #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */ |
4786 | #define IWL_ACTIVE_DWELL_TIME_52 (20) | |
4787 | ||
4788 | #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3) | |
4789 | #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2) | |
b481de9c ZY |
4790 | |
4791 | /* For faster active scanning, scan will move to the next channel if fewer than | |
4792 | * PLCP_QUIET_THRESH packets are heard on this channel within | |
4793 | * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell | |
4794 | * time if it's a quiet channel (nothing responded to our probe, and there's | |
4795 | * no other traffic). | |
4796 | * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */ | |
4797 | #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */ | |
f9340520 | 4798 | #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */ |
b481de9c ZY |
4799 | |
4800 | /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. | |
4801 | * Must be set longer than active dwell time. | |
4802 | * For the most reliable scan, set > AP beacon interval (typically 100msec). */ | |
4803 | #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */ | |
4804 | #define IWL_PASSIVE_DWELL_TIME_52 (10) | |
4805 | #define IWL_PASSIVE_DWELL_BASE (100) | |
4806 | #define IWL_CHANNEL_TUNE_TIME 5 | |
4807 | ||
f9340520 AK |
4808 | #define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1)))) |
4809 | ||
8318d78a | 4810 | static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv, |
f9340520 AK |
4811 | enum ieee80211_band band, |
4812 | u8 n_probes) | |
b481de9c | 4813 | { |
8318d78a | 4814 | if (band == IEEE80211_BAND_5GHZ) |
f9340520 AK |
4815 | return IWL_ACTIVE_DWELL_TIME_52 + |
4816 | IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1); | |
b481de9c | 4817 | else |
f9340520 AK |
4818 | return IWL_ACTIVE_DWELL_TIME_24 + |
4819 | IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1); | |
b481de9c ZY |
4820 | } |
4821 | ||
8318d78a JB |
4822 | static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv, |
4823 | enum ieee80211_band band) | |
b481de9c | 4824 | { |
8318d78a | 4825 | u16 passive = (band == IEEE80211_BAND_2GHZ) ? |
b481de9c ZY |
4826 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 : |
4827 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52; | |
4828 | ||
bb8c093b | 4829 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
4830 | /* If we're associated, we clamp the maximum passive |
4831 | * dwell time to be 98% of the beacon interval (minus | |
4832 | * 2 * channel tune time) */ | |
4833 | passive = priv->beacon_int; | |
4834 | if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive) | |
4835 | passive = IWL_PASSIVE_DWELL_BASE; | |
4836 | passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2; | |
4837 | } | |
4838 | ||
b481de9c ZY |
4839 | return passive; |
4840 | } | |
4841 | ||
8318d78a JB |
4842 | static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv, |
4843 | enum ieee80211_band band, | |
f9340520 | 4844 | u8 is_active, u8 n_probes, |
bb8c093b | 4845 | struct iwl3945_scan_channel *scan_ch) |
b481de9c ZY |
4846 | { |
4847 | const struct ieee80211_channel *channels = NULL; | |
8318d78a | 4848 | const struct ieee80211_supported_band *sband; |
bb8c093b | 4849 | const struct iwl3945_channel_info *ch_info; |
b481de9c ZY |
4850 | u16 passive_dwell = 0; |
4851 | u16 active_dwell = 0; | |
4852 | int added, i; | |
4853 | ||
8318d78a JB |
4854 | sband = iwl3945_get_band(priv, band); |
4855 | if (!sband) | |
b481de9c ZY |
4856 | return 0; |
4857 | ||
8318d78a | 4858 | channels = sband->channels; |
b481de9c | 4859 | |
f9340520 | 4860 | active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes); |
8318d78a | 4861 | passive_dwell = iwl3945_get_passive_dwell_time(priv, band); |
b481de9c | 4862 | |
8f4807a1 AK |
4863 | if (passive_dwell <= active_dwell) |
4864 | passive_dwell = active_dwell + 1; | |
4865 | ||
8318d78a | 4866 | for (i = 0, added = 0; i < sband->n_channels; i++) { |
182e2e66 JB |
4867 | if (channels[i].flags & IEEE80211_CHAN_DISABLED) |
4868 | continue; | |
4869 | ||
8318d78a | 4870 | scan_ch->channel = channels[i].hw_value; |
b481de9c | 4871 | |
8318d78a | 4872 | ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel); |
b481de9c | 4873 | if (!is_channel_valid(ch_info)) { |
66b5004d | 4874 | IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n", |
b481de9c ZY |
4875 | scan_ch->channel); |
4876 | continue; | |
4877 | } | |
4878 | ||
4879 | if (!is_active || is_channel_passive(ch_info) || | |
8318d78a | 4880 | (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) |
b481de9c ZY |
4881 | scan_ch->type = 0; /* passive */ |
4882 | else | |
4883 | scan_ch->type = 1; /* active */ | |
4884 | ||
f9340520 AK |
4885 | if ((scan_ch->type & 1) && n_probes) |
4886 | scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes); | |
b481de9c | 4887 | |
b481de9c ZY |
4888 | scan_ch->active_dwell = cpu_to_le16(active_dwell); |
4889 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
4890 | ||
9fbab516 | 4891 | /* Set txpower levels to defaults */ |
b481de9c ZY |
4892 | scan_ch->tpc.dsp_atten = 110; |
4893 | /* scan_pwr_info->tpc.dsp_atten; */ | |
4894 | ||
4895 | /*scan_pwr_info->tpc.tx_gain; */ | |
8318d78a | 4896 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
4897 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; |
4898 | else { | |
4899 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
4900 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
9fbab516 | 4901 | * power level: |
8a1b0245 | 4902 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; |
b481de9c ZY |
4903 | */ |
4904 | } | |
4905 | ||
4906 | IWL_DEBUG_SCAN("Scanning %d [%s %d]\n", | |
4907 | scan_ch->channel, | |
4908 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
4909 | (scan_ch->type & 1) ? | |
4910 | active_dwell : passive_dwell); | |
4911 | ||
4912 | scan_ch++; | |
4913 | added++; | |
4914 | } | |
4915 | ||
4916 | IWL_DEBUG_SCAN("total channels to scan %d \n", added); | |
4917 | return added; | |
4918 | } | |
4919 | ||
bb8c093b | 4920 | static void iwl3945_init_hw_rates(struct iwl3945_priv *priv, |
b481de9c ZY |
4921 | struct ieee80211_rate *rates) |
4922 | { | |
4923 | int i; | |
4924 | ||
4925 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
8318d78a JB |
4926 | rates[i].bitrate = iwl3945_rates[i].ieee * 5; |
4927 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
4928 | rates[i].hw_value_short = i; | |
4929 | rates[i].flags = 0; | |
4930 | if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { | |
b481de9c | 4931 | /* |
8318d78a | 4932 | * If CCK != 1M then set short preamble rate flag. |
b481de9c | 4933 | */ |
bb8c093b | 4934 | rates[i].flags |= (iwl3945_rates[i].plcp == 10) ? |
8318d78a | 4935 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
b481de9c | 4936 | } |
b481de9c ZY |
4937 | } |
4938 | } | |
4939 | ||
4940 | /** | |
bb8c093b | 4941 | * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom |
b481de9c | 4942 | */ |
bb8c093b | 4943 | static int iwl3945_init_geos(struct iwl3945_priv *priv) |
b481de9c | 4944 | { |
bb8c093b | 4945 | struct iwl3945_channel_info *ch; |
8211ef78 | 4946 | struct ieee80211_supported_band *sband; |
b481de9c ZY |
4947 | struct ieee80211_channel *channels; |
4948 | struct ieee80211_channel *geo_ch; | |
4949 | struct ieee80211_rate *rates; | |
4950 | int i = 0; | |
b481de9c | 4951 | |
8318d78a JB |
4952 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || |
4953 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
b481de9c ZY |
4954 | IWL_DEBUG_INFO("Geography modes already initialized.\n"); |
4955 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
4956 | return 0; | |
4957 | } | |
4958 | ||
b481de9c ZY |
4959 | channels = kzalloc(sizeof(struct ieee80211_channel) * |
4960 | priv->channel_count, GFP_KERNEL); | |
8318d78a | 4961 | if (!channels) |
b481de9c | 4962 | return -ENOMEM; |
b481de9c | 4963 | |
8211ef78 | 4964 | rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)), |
b481de9c ZY |
4965 | GFP_KERNEL); |
4966 | if (!rates) { | |
b481de9c ZY |
4967 | kfree(channels); |
4968 | return -ENOMEM; | |
4969 | } | |
4970 | ||
b481de9c | 4971 | /* 5.2GHz channels start after the 2.4GHz channels */ |
8211ef78 TW |
4972 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
4973 | sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)]; | |
4974 | /* just OFDM */ | |
4975 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
4976 | sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE; | |
4977 | ||
4978 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
4979 | sband->channels = channels; | |
4980 | /* OFDM & CCK */ | |
4981 | sband->bitrates = rates; | |
4982 | sband->n_bitrates = IWL_RATE_COUNT; | |
b481de9c ZY |
4983 | |
4984 | priv->ieee_channels = channels; | |
4985 | priv->ieee_rates = rates; | |
4986 | ||
bb8c093b | 4987 | iwl3945_init_hw_rates(priv, rates); |
b481de9c | 4988 | |
8211ef78 | 4989 | for (i = 0; i < priv->channel_count; i++) { |
b481de9c ZY |
4990 | ch = &priv->channel_info[i]; |
4991 | ||
8211ef78 TW |
4992 | /* FIXME: might be removed if scan is OK*/ |
4993 | if (!is_channel_valid(ch)) | |
b481de9c | 4994 | continue; |
b481de9c ZY |
4995 | |
4996 | if (is_channel_a_band(ch)) | |
8211ef78 | 4997 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
8318d78a | 4998 | else |
8211ef78 | 4999 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; |
b481de9c | 5000 | |
8211ef78 TW |
5001 | geo_ch = &sband->channels[sband->n_channels++]; |
5002 | ||
5003 | geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel); | |
8318d78a JB |
5004 | geo_ch->max_power = ch->max_power_avg; |
5005 | geo_ch->max_antenna_gain = 0xff; | |
7b72304d | 5006 | geo_ch->hw_value = ch->channel; |
b481de9c ZY |
5007 | |
5008 | if (is_channel_valid(ch)) { | |
8318d78a JB |
5009 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) |
5010 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
b481de9c | 5011 | |
8318d78a JB |
5012 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) |
5013 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
b481de9c ZY |
5014 | |
5015 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
8318d78a | 5016 | geo_ch->flags |= IEEE80211_CHAN_RADAR; |
b481de9c ZY |
5017 | |
5018 | if (ch->max_power_avg > priv->max_channel_txpower_limit) | |
5019 | priv->max_channel_txpower_limit = | |
5020 | ch->max_power_avg; | |
8211ef78 | 5021 | } else { |
8318d78a | 5022 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; |
8211ef78 TW |
5023 | } |
5024 | ||
5025 | /* Save flags for reg domain usage */ | |
5026 | geo_ch->orig_flags = geo_ch->flags; | |
5027 | ||
5028 | IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n", | |
5029 | ch->channel, geo_ch->center_freq, | |
5030 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
5031 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
5032 | "restricted" : "valid", | |
5033 | geo_ch->flags); | |
b481de9c ZY |
5034 | } |
5035 | ||
82b9a121 TW |
5036 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && |
5037 | priv->cfg->sku & IWL_SKU_A) { | |
b481de9c ZY |
5038 | printk(KERN_INFO DRV_NAME |
5039 | ": Incorrectly detected BG card as ABG. Please send " | |
5040 | "your PCI ID 0x%04X:0x%04X to maintainer.\n", | |
5041 | priv->pci_dev->device, priv->pci_dev->subsystem_device); | |
82b9a121 | 5042 | priv->cfg->sku &= ~IWL_SKU_A; |
b481de9c ZY |
5043 | } |
5044 | ||
5045 | printk(KERN_INFO DRV_NAME | |
5046 | ": Tunable channels: %d 802.11bg, %d 802.11a channels\n", | |
8318d78a JB |
5047 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
5048 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
b481de9c | 5049 | |
e0e0a67e JL |
5050 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
5051 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
5052 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
5053 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
5054 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
5055 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
b481de9c | 5056 | |
b481de9c ZY |
5057 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
5058 | ||
5059 | return 0; | |
5060 | } | |
5061 | ||
849e0dce RC |
5062 | /* |
5063 | * iwl3945_free_geos - undo allocations in iwl3945_init_geos | |
5064 | */ | |
5065 | static void iwl3945_free_geos(struct iwl3945_priv *priv) | |
5066 | { | |
849e0dce RC |
5067 | kfree(priv->ieee_channels); |
5068 | kfree(priv->ieee_rates); | |
5069 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
5070 | } | |
5071 | ||
b481de9c ZY |
5072 | /****************************************************************************** |
5073 | * | |
5074 | * uCode download functions | |
5075 | * | |
5076 | ******************************************************************************/ | |
5077 | ||
bb8c093b | 5078 | static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv) |
b481de9c | 5079 | { |
98c92211 TW |
5080 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
5081 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
5082 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
5083 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
5084 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
5085 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
5086 | } |
5087 | ||
5088 | /** | |
bb8c093b | 5089 | * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host, |
b481de9c ZY |
5090 | * looking at all data. |
5091 | */ | |
3ac7f146 | 5092 | static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
5093 | { |
5094 | u32 val; | |
5095 | u32 save_len = len; | |
5096 | int rc = 0; | |
5097 | u32 errcnt; | |
5098 | ||
5099 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
5100 | ||
bb8c093b | 5101 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5102 | if (rc) |
5103 | return rc; | |
5104 | ||
bb8c093b | 5105 | iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND); |
b481de9c ZY |
5106 | |
5107 | errcnt = 0; | |
5108 | for (; len > 0; len -= sizeof(u32), image++) { | |
5109 | /* read data comes through single port, auto-incr addr */ | |
5110 | /* NOTE: Use the debugless read so we don't flood kernel log | |
5111 | * if IWL_DL_IO is set */ | |
bb8c093b | 5112 | val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
5113 | if (val != le32_to_cpu(*image)) { |
5114 | IWL_ERROR("uCode INST section is invalid at " | |
5115 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
5116 | save_len - len, val, le32_to_cpu(*image)); | |
5117 | rc = -EIO; | |
5118 | errcnt++; | |
5119 | if (errcnt >= 20) | |
5120 | break; | |
5121 | } | |
5122 | } | |
5123 | ||
bb8c093b | 5124 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5125 | |
5126 | if (!errcnt) | |
bc434dd2 | 5127 | IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n"); |
b481de9c ZY |
5128 | |
5129 | return rc; | |
5130 | } | |
5131 | ||
5132 | ||
5133 | /** | |
bb8c093b | 5134 | * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host, |
b481de9c ZY |
5135 | * using sample data 100 bytes apart. If these sample points are good, |
5136 | * it's a pretty good bet that everything between them is good, too. | |
5137 | */ | |
bb8c093b | 5138 | static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
5139 | { |
5140 | u32 val; | |
5141 | int rc = 0; | |
5142 | u32 errcnt = 0; | |
5143 | u32 i; | |
5144 | ||
5145 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
5146 | ||
bb8c093b | 5147 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5148 | if (rc) |
5149 | return rc; | |
5150 | ||
5151 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
5152 | /* read data comes through single port, auto-incr addr */ | |
5153 | /* NOTE: Use the debugless read so we don't flood kernel log | |
5154 | * if IWL_DL_IO is set */ | |
bb8c093b | 5155 | iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
b481de9c | 5156 | i + RTC_INST_LOWER_BOUND); |
bb8c093b | 5157 | val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
5158 | if (val != le32_to_cpu(*image)) { |
5159 | #if 0 /* Enable this if you want to see details */ | |
5160 | IWL_ERROR("uCode INST section is invalid at " | |
5161 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
5162 | i, val, *image); | |
5163 | #endif | |
5164 | rc = -EIO; | |
5165 | errcnt++; | |
5166 | if (errcnt >= 3) | |
5167 | break; | |
5168 | } | |
5169 | } | |
5170 | ||
bb8c093b | 5171 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5172 | |
5173 | return rc; | |
5174 | } | |
5175 | ||
5176 | ||
5177 | /** | |
bb8c093b | 5178 | * iwl3945_verify_ucode - determine which instruction image is in SRAM, |
b481de9c ZY |
5179 | * and verify its contents |
5180 | */ | |
bb8c093b | 5181 | static int iwl3945_verify_ucode(struct iwl3945_priv *priv) |
b481de9c ZY |
5182 | { |
5183 | __le32 *image; | |
5184 | u32 len; | |
5185 | int rc = 0; | |
5186 | ||
5187 | /* Try bootstrap */ | |
5188 | image = (__le32 *)priv->ucode_boot.v_addr; | |
5189 | len = priv->ucode_boot.len; | |
bb8c093b | 5190 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5191 | if (rc == 0) { |
5192 | IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n"); | |
5193 | return 0; | |
5194 | } | |
5195 | ||
5196 | /* Try initialize */ | |
5197 | image = (__le32 *)priv->ucode_init.v_addr; | |
5198 | len = priv->ucode_init.len; | |
bb8c093b | 5199 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5200 | if (rc == 0) { |
5201 | IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n"); | |
5202 | return 0; | |
5203 | } | |
5204 | ||
5205 | /* Try runtime/protocol */ | |
5206 | image = (__le32 *)priv->ucode_code.v_addr; | |
5207 | len = priv->ucode_code.len; | |
bb8c093b | 5208 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5209 | if (rc == 0) { |
5210 | IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n"); | |
5211 | return 0; | |
5212 | } | |
5213 | ||
5214 | IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); | |
5215 | ||
9fbab516 BC |
5216 | /* Since nothing seems to match, show first several data entries in |
5217 | * instruction SRAM, so maybe visual inspection will give a clue. | |
5218 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
b481de9c ZY |
5219 | image = (__le32 *)priv->ucode_boot.v_addr; |
5220 | len = priv->ucode_boot.len; | |
bb8c093b | 5221 | rc = iwl3945_verify_inst_full(priv, image, len); |
b481de9c ZY |
5222 | |
5223 | return rc; | |
5224 | } | |
5225 | ||
5226 | ||
5227 | /* check contents of special bootstrap uCode SRAM */ | |
bb8c093b | 5228 | static int iwl3945_verify_bsm(struct iwl3945_priv *priv) |
b481de9c ZY |
5229 | { |
5230 | __le32 *image = priv->ucode_boot.v_addr; | |
5231 | u32 len = priv->ucode_boot.len; | |
5232 | u32 reg; | |
5233 | u32 val; | |
5234 | ||
5235 | IWL_DEBUG_INFO("Begin verify bsm\n"); | |
5236 | ||
5237 | /* verify BSM SRAM contents */ | |
bb8c093b | 5238 | val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG); |
b481de9c ZY |
5239 | for (reg = BSM_SRAM_LOWER_BOUND; |
5240 | reg < BSM_SRAM_LOWER_BOUND + len; | |
3ac7f146 | 5241 | reg += sizeof(u32), image++) { |
bb8c093b | 5242 | val = iwl3945_read_prph(priv, reg); |
b481de9c ZY |
5243 | if (val != le32_to_cpu(*image)) { |
5244 | IWL_ERROR("BSM uCode verification failed at " | |
5245 | "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", | |
5246 | BSM_SRAM_LOWER_BOUND, | |
5247 | reg - BSM_SRAM_LOWER_BOUND, len, | |
5248 | val, le32_to_cpu(*image)); | |
5249 | return -EIO; | |
5250 | } | |
5251 | } | |
5252 | ||
5253 | IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n"); | |
5254 | ||
5255 | return 0; | |
5256 | } | |
5257 | ||
5258 | /** | |
bb8c093b | 5259 | * iwl3945_load_bsm - Load bootstrap instructions |
b481de9c ZY |
5260 | * |
5261 | * BSM operation: | |
5262 | * | |
5263 | * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program | |
5264 | * in special SRAM that does not power down during RFKILL. When powering back | |
5265 | * up after power-saving sleeps (or during initial uCode load), the BSM loads | |
5266 | * the bootstrap program into the on-board processor, and starts it. | |
5267 | * | |
5268 | * The bootstrap program loads (via DMA) instructions and data for a new | |
5269 | * program from host DRAM locations indicated by the host driver in the | |
5270 | * BSM_DRAM_* registers. Once the new program is loaded, it starts | |
5271 | * automatically. | |
5272 | * | |
5273 | * When initializing the NIC, the host driver points the BSM to the | |
5274 | * "initialize" uCode image. This uCode sets up some internal data, then | |
5275 | * notifies host via "initialize alive" that it is complete. | |
5276 | * | |
5277 | * The host then replaces the BSM_DRAM_* pointer values to point to the | |
5278 | * normal runtime uCode instructions and a backup uCode data cache buffer | |
5279 | * (filled initially with starting data values for the on-board processor), | |
5280 | * then triggers the "initialize" uCode to load and launch the runtime uCode, | |
5281 | * which begins normal operation. | |
5282 | * | |
5283 | * When doing a power-save shutdown, runtime uCode saves data SRAM into | |
5284 | * the backup data cache in DRAM before SRAM is powered down. | |
5285 | * | |
5286 | * When powering back up, the BSM loads the bootstrap program. This reloads | |
5287 | * the runtime uCode instructions and the backup data cache into SRAM, | |
5288 | * and re-launches the runtime uCode from where it left off. | |
5289 | */ | |
bb8c093b | 5290 | static int iwl3945_load_bsm(struct iwl3945_priv *priv) |
b481de9c ZY |
5291 | { |
5292 | __le32 *image = priv->ucode_boot.v_addr; | |
5293 | u32 len = priv->ucode_boot.len; | |
5294 | dma_addr_t pinst; | |
5295 | dma_addr_t pdata; | |
5296 | u32 inst_len; | |
5297 | u32 data_len; | |
5298 | int rc; | |
5299 | int i; | |
5300 | u32 done; | |
5301 | u32 reg_offset; | |
5302 | ||
5303 | IWL_DEBUG_INFO("Begin load bsm\n"); | |
5304 | ||
5305 | /* make sure bootstrap program is no larger than BSM's SRAM size */ | |
5306 | if (len > IWL_MAX_BSM_SIZE) | |
5307 | return -EINVAL; | |
5308 | ||
5309 | /* Tell bootstrap uCode where to find the "Initialize" uCode | |
9fbab516 | 5310 | * in host DRAM ... host DRAM physical address bits 31:0 for 3945. |
bb8c093b | 5311 | * NOTE: iwl3945_initialize_alive_start() will replace these values, |
b481de9c ZY |
5312 | * after the "initialize" uCode has run, to point to |
5313 | * runtime/protocol instructions and backup data cache. */ | |
5314 | pinst = priv->ucode_init.p_addr; | |
5315 | pdata = priv->ucode_init_data.p_addr; | |
5316 | inst_len = priv->ucode_init.len; | |
5317 | data_len = priv->ucode_init_data.len; | |
5318 | ||
bb8c093b | 5319 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5320 | if (rc) |
5321 | return rc; | |
5322 | ||
bb8c093b CH |
5323 | iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
5324 | iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
5325 | iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); | |
5326 | iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); | |
b481de9c ZY |
5327 | |
5328 | /* Fill BSM memory with bootstrap instructions */ | |
5329 | for (reg_offset = BSM_SRAM_LOWER_BOUND; | |
5330 | reg_offset < BSM_SRAM_LOWER_BOUND + len; | |
5331 | reg_offset += sizeof(u32), image++) | |
bb8c093b | 5332 | _iwl3945_write_prph(priv, reg_offset, |
b481de9c ZY |
5333 | le32_to_cpu(*image)); |
5334 | ||
bb8c093b | 5335 | rc = iwl3945_verify_bsm(priv); |
b481de9c | 5336 | if (rc) { |
bb8c093b | 5337 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5338 | return rc; |
5339 | } | |
5340 | ||
5341 | /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ | |
bb8c093b CH |
5342 | iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0); |
5343 | iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG, | |
b481de9c | 5344 | RTC_INST_LOWER_BOUND); |
bb8c093b | 5345 | iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); |
b481de9c ZY |
5346 | |
5347 | /* Load bootstrap code into instruction SRAM now, | |
5348 | * to prepare to load "initialize" uCode */ | |
bb8c093b | 5349 | iwl3945_write_prph(priv, BSM_WR_CTRL_REG, |
b481de9c ZY |
5350 | BSM_WR_CTRL_REG_BIT_START); |
5351 | ||
5352 | /* Wait for load of bootstrap uCode to finish */ | |
5353 | for (i = 0; i < 100; i++) { | |
bb8c093b | 5354 | done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG); |
b481de9c ZY |
5355 | if (!(done & BSM_WR_CTRL_REG_BIT_START)) |
5356 | break; | |
5357 | udelay(10); | |
5358 | } | |
5359 | if (i < 100) | |
5360 | IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i); | |
5361 | else { | |
5362 | IWL_ERROR("BSM write did not complete!\n"); | |
5363 | return -EIO; | |
5364 | } | |
5365 | ||
5366 | /* Enable future boot loads whenever power management unit triggers it | |
5367 | * (e.g. when powering back up after power-save shutdown) */ | |
bb8c093b | 5368 | iwl3945_write_prph(priv, BSM_WR_CTRL_REG, |
b481de9c ZY |
5369 | BSM_WR_CTRL_REG_BIT_START_EN); |
5370 | ||
bb8c093b | 5371 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5372 | |
5373 | return 0; | |
5374 | } | |
5375 | ||
bb8c093b | 5376 | static void iwl3945_nic_start(struct iwl3945_priv *priv) |
b481de9c ZY |
5377 | { |
5378 | /* Remove all resets to allow NIC to operate */ | |
bb8c093b | 5379 | iwl3945_write32(priv, CSR_RESET, 0); |
b481de9c ZY |
5380 | } |
5381 | ||
5382 | /** | |
bb8c093b | 5383 | * iwl3945_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
5384 | * |
5385 | * Copy into buffers for card to fetch via bus-mastering | |
5386 | */ | |
bb8c093b | 5387 | static int iwl3945_read_ucode(struct iwl3945_priv *priv) |
b481de9c | 5388 | { |
bb8c093b | 5389 | struct iwl3945_ucode *ucode; |
90e759d1 | 5390 | int ret = 0; |
b481de9c ZY |
5391 | const struct firmware *ucode_raw; |
5392 | /* firmware file name contains uCode/driver compatibility version */ | |
4bf775cd | 5393 | const char *name = priv->cfg->fw_name; |
b481de9c ZY |
5394 | u8 *src; |
5395 | size_t len; | |
5396 | u32 ver, inst_size, data_size, init_size, init_data_size, boot_size; | |
5397 | ||
5398 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
5399 | * request_firmware() is synchronous, file is in memory on return. */ | |
90e759d1 TW |
5400 | ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev); |
5401 | if (ret < 0) { | |
5402 | IWL_ERROR("%s firmware file req failed: Reason %d\n", | |
5403 | name, ret); | |
b481de9c ZY |
5404 | goto error; |
5405 | } | |
5406 | ||
5407 | IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n", | |
5408 | name, ucode_raw->size); | |
5409 | ||
5410 | /* Make sure that we got at least our header! */ | |
5411 | if (ucode_raw->size < sizeof(*ucode)) { | |
5412 | IWL_ERROR("File size way too small!\n"); | |
90e759d1 | 5413 | ret = -EINVAL; |
b481de9c ZY |
5414 | goto err_release; |
5415 | } | |
5416 | ||
5417 | /* Data from ucode file: header followed by uCode images */ | |
5418 | ucode = (void *)ucode_raw->data; | |
5419 | ||
5420 | ver = le32_to_cpu(ucode->ver); | |
5421 | inst_size = le32_to_cpu(ucode->inst_size); | |
5422 | data_size = le32_to_cpu(ucode->data_size); | |
5423 | init_size = le32_to_cpu(ucode->init_size); | |
5424 | init_data_size = le32_to_cpu(ucode->init_data_size); | |
5425 | boot_size = le32_to_cpu(ucode->boot_size); | |
5426 | ||
5427 | IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver); | |
bc434dd2 IS |
5428 | IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size); |
5429 | IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size); | |
5430 | IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size); | |
5431 | IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size); | |
5432 | IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size); | |
b481de9c ZY |
5433 | |
5434 | /* Verify size of file vs. image size info in file's header */ | |
5435 | if (ucode_raw->size < sizeof(*ucode) + | |
5436 | inst_size + data_size + init_size + | |
5437 | init_data_size + boot_size) { | |
5438 | ||
5439 | IWL_DEBUG_INFO("uCode file size %d too small\n", | |
5440 | (int)ucode_raw->size); | |
90e759d1 | 5441 | ret = -EINVAL; |
b481de9c ZY |
5442 | goto err_release; |
5443 | } | |
5444 | ||
5445 | /* Verify that uCode images will fit in card's SRAM */ | |
5446 | if (inst_size > IWL_MAX_INST_SIZE) { | |
90e759d1 TW |
5447 | IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n", |
5448 | inst_size); | |
5449 | ret = -EINVAL; | |
b481de9c ZY |
5450 | goto err_release; |
5451 | } | |
5452 | ||
5453 | if (data_size > IWL_MAX_DATA_SIZE) { | |
90e759d1 TW |
5454 | IWL_DEBUG_INFO("uCode data len %d too large to fit in\n", |
5455 | data_size); | |
5456 | ret = -EINVAL; | |
b481de9c ZY |
5457 | goto err_release; |
5458 | } | |
5459 | if (init_size > IWL_MAX_INST_SIZE) { | |
90e759d1 TW |
5460 | IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n", |
5461 | init_size); | |
5462 | ret = -EINVAL; | |
b481de9c ZY |
5463 | goto err_release; |
5464 | } | |
5465 | if (init_data_size > IWL_MAX_DATA_SIZE) { | |
90e759d1 TW |
5466 | IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n", |
5467 | init_data_size); | |
5468 | ret = -EINVAL; | |
b481de9c ZY |
5469 | goto err_release; |
5470 | } | |
5471 | if (boot_size > IWL_MAX_BSM_SIZE) { | |
90e759d1 TW |
5472 | IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n", |
5473 | boot_size); | |
5474 | ret = -EINVAL; | |
b481de9c ZY |
5475 | goto err_release; |
5476 | } | |
5477 | ||
5478 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
5479 | ||
5480 | /* Runtime instructions and 2 copies of data: | |
5481 | * 1) unmodified from disk | |
5482 | * 2) backup cache for save/restore during power-downs */ | |
5483 | priv->ucode_code.len = inst_size; | |
98c92211 | 5484 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
5485 | |
5486 | priv->ucode_data.len = data_size; | |
98c92211 | 5487 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
5488 | |
5489 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 5490 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 5491 | |
90e759d1 TW |
5492 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
5493 | !priv->ucode_data_backup.v_addr) | |
5494 | goto err_pci_alloc; | |
b481de9c ZY |
5495 | |
5496 | /* Initialization instructions and data */ | |
90e759d1 TW |
5497 | if (init_size && init_data_size) { |
5498 | priv->ucode_init.len = init_size; | |
98c92211 | 5499 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
5500 | |
5501 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 5502 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
5503 | |
5504 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
5505 | goto err_pci_alloc; | |
5506 | } | |
b481de9c ZY |
5507 | |
5508 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
5509 | if (boot_size) { |
5510 | priv->ucode_boot.len = boot_size; | |
98c92211 | 5511 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 5512 | |
90e759d1 TW |
5513 | if (!priv->ucode_boot.v_addr) |
5514 | goto err_pci_alloc; | |
5515 | } | |
b481de9c ZY |
5516 | |
5517 | /* Copy images into buffers for card's bus-master reads ... */ | |
5518 | ||
5519 | /* Runtime instructions (first block of data in file) */ | |
5520 | src = &ucode->data[0]; | |
5521 | len = priv->ucode_code.len; | |
90e759d1 | 5522 | IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c ZY |
5523 | memcpy(priv->ucode_code.v_addr, src, len); |
5524 | IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", | |
5525 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); | |
5526 | ||
5527 | /* Runtime data (2nd block) | |
bb8c093b | 5528 | * NOTE: Copy into backup buffer will be done in iwl3945_up() */ |
b481de9c ZY |
5529 | src = &ucode->data[inst_size]; |
5530 | len = priv->ucode_data.len; | |
90e759d1 | 5531 | IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
5532 | memcpy(priv->ucode_data.v_addr, src, len); |
5533 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
5534 | ||
5535 | /* Initialization instructions (3rd block) */ | |
5536 | if (init_size) { | |
5537 | src = &ucode->data[inst_size + data_size]; | |
5538 | len = priv->ucode_init.len; | |
90e759d1 TW |
5539 | IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n", |
5540 | len); | |
b481de9c ZY |
5541 | memcpy(priv->ucode_init.v_addr, src, len); |
5542 | } | |
5543 | ||
5544 | /* Initialization data (4th block) */ | |
5545 | if (init_data_size) { | |
5546 | src = &ucode->data[inst_size + data_size + init_size]; | |
5547 | len = priv->ucode_init_data.len; | |
5548 | IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n", | |
5549 | (int)len); | |
5550 | memcpy(priv->ucode_init_data.v_addr, src, len); | |
5551 | } | |
5552 | ||
5553 | /* Bootstrap instructions (5th block) */ | |
5554 | src = &ucode->data[inst_size + data_size + init_size + init_data_size]; | |
5555 | len = priv->ucode_boot.len; | |
5556 | IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n", | |
5557 | (int)len); | |
5558 | memcpy(priv->ucode_boot.v_addr, src, len); | |
5559 | ||
5560 | /* We have our copies now, allow OS release its copies */ | |
5561 | release_firmware(ucode_raw); | |
5562 | return 0; | |
5563 | ||
5564 | err_pci_alloc: | |
5565 | IWL_ERROR("failed to allocate pci memory\n"); | |
90e759d1 | 5566 | ret = -ENOMEM; |
bb8c093b | 5567 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
5568 | |
5569 | err_release: | |
5570 | release_firmware(ucode_raw); | |
5571 | ||
5572 | error: | |
90e759d1 | 5573 | return ret; |
b481de9c ZY |
5574 | } |
5575 | ||
5576 | ||
5577 | /** | |
bb8c093b | 5578 | * iwl3945_set_ucode_ptrs - Set uCode address location |
b481de9c ZY |
5579 | * |
5580 | * Tell initialization uCode where to find runtime uCode. | |
5581 | * | |
5582 | * BSM registers initially contain pointers to initialization uCode. | |
5583 | * We need to replace them to load runtime uCode inst and data, | |
5584 | * and to save runtime data when powering down. | |
5585 | */ | |
bb8c093b | 5586 | static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv) |
b481de9c ZY |
5587 | { |
5588 | dma_addr_t pinst; | |
5589 | dma_addr_t pdata; | |
5590 | int rc = 0; | |
5591 | unsigned long flags; | |
5592 | ||
5593 | /* bits 31:0 for 3945 */ | |
5594 | pinst = priv->ucode_code.p_addr; | |
5595 | pdata = priv->ucode_data_backup.p_addr; | |
5596 | ||
5597 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 5598 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5599 | if (rc) { |
5600 | spin_unlock_irqrestore(&priv->lock, flags); | |
5601 | return rc; | |
5602 | } | |
5603 | ||
5604 | /* Tell bootstrap uCode where to find image to load */ | |
bb8c093b CH |
5605 | iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
5606 | iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
5607 | iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
b481de9c ZY |
5608 | priv->ucode_data.len); |
5609 | ||
5610 | /* Inst bytecount must be last to set up, bit 31 signals uCode | |
5611 | * that all new ptr/size info is in place */ | |
bb8c093b | 5612 | iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
b481de9c ZY |
5613 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
5614 | ||
bb8c093b | 5615 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5616 | |
5617 | spin_unlock_irqrestore(&priv->lock, flags); | |
5618 | ||
5619 | IWL_DEBUG_INFO("Runtime uCode pointers are set.\n"); | |
5620 | ||
5621 | return rc; | |
5622 | } | |
5623 | ||
5624 | /** | |
bb8c093b | 5625 | * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received |
b481de9c ZY |
5626 | * |
5627 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
5628 | * | |
b481de9c | 5629 | * Tell "initialize" uCode to go ahead and load the runtime uCode. |
9fbab516 | 5630 | */ |
bb8c093b | 5631 | static void iwl3945_init_alive_start(struct iwl3945_priv *priv) |
b481de9c ZY |
5632 | { |
5633 | /* Check alive response for "valid" sign from uCode */ | |
5634 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
5635 | /* We had an error bringing up the hardware, so take it | |
5636 | * all the way back down so we can try again */ | |
5637 | IWL_DEBUG_INFO("Initialize Alive failed.\n"); | |
5638 | goto restart; | |
5639 | } | |
5640 | ||
5641 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
5642 | * This is a paranoid check, because we would not have gotten the | |
5643 | * "initialize" alive if code weren't properly loaded. */ | |
bb8c093b | 5644 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
5645 | /* Runtime instruction load was bad; |
5646 | * take it all the way back down so we can try again */ | |
5647 | IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); | |
5648 | goto restart; | |
5649 | } | |
5650 | ||
5651 | /* Send pointers to protocol/runtime uCode image ... init code will | |
5652 | * load and launch runtime uCode, which will send us another "Alive" | |
5653 | * notification. */ | |
5654 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
bb8c093b | 5655 | if (iwl3945_set_ucode_ptrs(priv)) { |
b481de9c ZY |
5656 | /* Runtime instruction load won't happen; |
5657 | * take it all the way back down so we can try again */ | |
5658 | IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n"); | |
5659 | goto restart; | |
5660 | } | |
5661 | return; | |
5662 | ||
5663 | restart: | |
5664 | queue_work(priv->workqueue, &priv->restart); | |
5665 | } | |
5666 | ||
5667 | ||
5668 | /** | |
bb8c093b | 5669 | * iwl3945_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 5670 | * from protocol/runtime uCode (initialization uCode's |
bb8c093b | 5671 | * Alive gets handled by iwl3945_init_alive_start()). |
b481de9c | 5672 | */ |
bb8c093b | 5673 | static void iwl3945_alive_start(struct iwl3945_priv *priv) |
b481de9c ZY |
5674 | { |
5675 | int rc = 0; | |
5676 | int thermal_spin = 0; | |
5677 | u32 rfkill; | |
5678 | ||
5679 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
5680 | ||
5681 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
5682 | /* We had an error bringing up the hardware, so take it | |
5683 | * all the way back down so we can try again */ | |
5684 | IWL_DEBUG_INFO("Alive failed.\n"); | |
5685 | goto restart; | |
5686 | } | |
5687 | ||
5688 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
5689 | * This is a paranoid check, because we would not have gotten the | |
5690 | * "runtime" alive if code weren't properly loaded. */ | |
bb8c093b | 5691 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
5692 | /* Runtime instruction load was bad; |
5693 | * take it all the way back down so we can try again */ | |
5694 | IWL_DEBUG_INFO("Bad runtime uCode load.\n"); | |
5695 | goto restart; | |
5696 | } | |
5697 | ||
bb8c093b | 5698 | iwl3945_clear_stations_table(priv); |
b481de9c | 5699 | |
bb8c093b | 5700 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5701 | if (rc) { |
5702 | IWL_WARNING("Can not read rfkill status from adapter\n"); | |
5703 | return; | |
5704 | } | |
5705 | ||
bb8c093b | 5706 | rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG); |
b481de9c | 5707 | IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill); |
bb8c093b | 5708 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5709 | |
5710 | if (rfkill & 0x1) { | |
5711 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
5712 | /* if rfkill is not on, then wait for thermal | |
5713 | * sensor in adapter to kick in */ | |
bb8c093b | 5714 | while (iwl3945_hw_get_temperature(priv) == 0) { |
b481de9c ZY |
5715 | thermal_spin++; |
5716 | udelay(10); | |
5717 | } | |
5718 | ||
5719 | if (thermal_spin) | |
5720 | IWL_DEBUG_INFO("Thermal calibration took %dus\n", | |
5721 | thermal_spin * 10); | |
5722 | } else | |
5723 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
5724 | ||
9fbab516 | 5725 | /* After the ALIVE response, we can send commands to 3945 uCode */ |
b481de9c ZY |
5726 | set_bit(STATUS_ALIVE, &priv->status); |
5727 | ||
5728 | /* Clear out the uCode error bit if it is set */ | |
5729 | clear_bit(STATUS_FW_ERROR, &priv->status); | |
5730 | ||
bb8c093b | 5731 | if (iwl3945_is_rfkill(priv)) |
b481de9c ZY |
5732 | return; |
5733 | ||
36d6825b | 5734 | ieee80211_wake_queues(priv->hw); |
b481de9c ZY |
5735 | |
5736 | priv->active_rate = priv->rates_mask; | |
5737 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
5738 | ||
bb8c093b | 5739 | iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode)); |
b481de9c | 5740 | |
bb8c093b CH |
5741 | if (iwl3945_is_associated(priv)) { |
5742 | struct iwl3945_rxon_cmd *active_rxon = | |
5743 | (struct iwl3945_rxon_cmd *)(&priv->active_rxon); | |
b481de9c ZY |
5744 | |
5745 | memcpy(&priv->staging_rxon, &priv->active_rxon, | |
5746 | sizeof(priv->staging_rxon)); | |
5747 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
5748 | } else { | |
5749 | /* Initialize our rx_config data */ | |
bb8c093b | 5750 | iwl3945_connection_init_rx_config(priv); |
b481de9c ZY |
5751 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
5752 | } | |
5753 | ||
9fbab516 | 5754 | /* Configure Bluetooth device coexistence support */ |
bb8c093b | 5755 | iwl3945_send_bt_config(priv); |
b481de9c ZY |
5756 | |
5757 | /* Configure the adapter for unassociated operation */ | |
bb8c093b | 5758 | iwl3945_commit_rxon(priv); |
b481de9c | 5759 | |
b481de9c ZY |
5760 | iwl3945_reg_txpower_periodic(priv); |
5761 | ||
fe00b5a5 RC |
5762 | iwl3945_led_register(priv); |
5763 | ||
b481de9c | 5764 | IWL_DEBUG_INFO("ALIVE processing complete.\n"); |
a9f46786 | 5765 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 5766 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c ZY |
5767 | |
5768 | if (priv->error_recovering) | |
bb8c093b | 5769 | iwl3945_error_recovery(priv); |
b481de9c ZY |
5770 | |
5771 | return; | |
5772 | ||
5773 | restart: | |
5774 | queue_work(priv->workqueue, &priv->restart); | |
5775 | } | |
5776 | ||
bb8c093b | 5777 | static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv); |
b481de9c | 5778 | |
bb8c093b | 5779 | static void __iwl3945_down(struct iwl3945_priv *priv) |
b481de9c ZY |
5780 | { |
5781 | unsigned long flags; | |
5782 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
5783 | struct ieee80211_conf *conf = NULL; | |
5784 | ||
5785 | IWL_DEBUG_INFO(DRV_NAME " is going down\n"); | |
5786 | ||
5787 | conf = ieee80211_get_hw_conf(priv->hw); | |
5788 | ||
5789 | if (!exit_pending) | |
5790 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5791 | ||
ab53d8af | 5792 | iwl3945_led_unregister(priv); |
bb8c093b | 5793 | iwl3945_clear_stations_table(priv); |
b481de9c ZY |
5794 | |
5795 | /* Unblock any waiting calls */ | |
5796 | wake_up_interruptible_all(&priv->wait_command_queue); | |
5797 | ||
b481de9c ZY |
5798 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
5799 | * exiting the module */ | |
5800 | if (!exit_pending) | |
5801 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
5802 | ||
5803 | /* stop and reset the on-board processor */ | |
bb8c093b | 5804 | iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
5805 | |
5806 | /* tell the device to stop sending interrupts */ | |
0359facc | 5807 | spin_lock_irqsave(&priv->lock, flags); |
bb8c093b | 5808 | iwl3945_disable_interrupts(priv); |
0359facc MA |
5809 | spin_unlock_irqrestore(&priv->lock, flags); |
5810 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
5811 | |
5812 | if (priv->mac80211_registered) | |
5813 | ieee80211_stop_queues(priv->hw); | |
5814 | ||
bb8c093b | 5815 | /* If we have not previously called iwl3945_init() then |
b481de9c | 5816 | * clear all bits but the RF Kill and SUSPEND bits and return */ |
bb8c093b | 5817 | if (!iwl3945_is_init(priv)) { |
b481de9c ZY |
5818 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
5819 | STATUS_RF_KILL_HW | | |
5820 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
5821 | STATUS_RF_KILL_SW | | |
9788864e RC |
5822 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
5823 | STATUS_GEO_CONFIGURED | | |
b481de9c | 5824 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
ebef2008 AK |
5825 | STATUS_IN_SUSPEND | |
5826 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
5827 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
5828 | goto exit; |
5829 | } | |
5830 | ||
5831 | /* ...otherwise clear out all the status bits but the RF Kill and | |
5832 | * SUSPEND bits and continue taking the NIC down. */ | |
5833 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << | |
5834 | STATUS_RF_KILL_HW | | |
5835 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
5836 | STATUS_RF_KILL_SW | | |
9788864e RC |
5837 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
5838 | STATUS_GEO_CONFIGURED | | |
b481de9c ZY |
5839 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
5840 | STATUS_IN_SUSPEND | | |
5841 | test_bit(STATUS_FW_ERROR, &priv->status) << | |
ebef2008 AK |
5842 | STATUS_FW_ERROR | |
5843 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
5844 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
5845 | |
5846 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 5847 | iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
5848 | spin_unlock_irqrestore(&priv->lock, flags); |
5849 | ||
bb8c093b CH |
5850 | iwl3945_hw_txq_ctx_stop(priv); |
5851 | iwl3945_hw_rxq_stop(priv); | |
b481de9c ZY |
5852 | |
5853 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b CH |
5854 | if (!iwl3945_grab_nic_access(priv)) { |
5855 | iwl3945_write_prph(priv, APMG_CLK_DIS_REG, | |
b481de9c | 5856 | APMG_CLK_VAL_DMA_CLK_RQT); |
bb8c093b | 5857 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5858 | } |
5859 | spin_unlock_irqrestore(&priv->lock, flags); | |
5860 | ||
5861 | udelay(5); | |
5862 | ||
bb8c093b CH |
5863 | iwl3945_hw_nic_stop_master(priv); |
5864 | iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
5865 | iwl3945_hw_nic_reset(priv); | |
b481de9c ZY |
5866 | |
5867 | exit: | |
bb8c093b | 5868 | memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp)); |
b481de9c ZY |
5869 | |
5870 | if (priv->ibss_beacon) | |
5871 | dev_kfree_skb(priv->ibss_beacon); | |
5872 | priv->ibss_beacon = NULL; | |
5873 | ||
5874 | /* clear out any free frames */ | |
bb8c093b | 5875 | iwl3945_clear_free_frames(priv); |
b481de9c ZY |
5876 | } |
5877 | ||
bb8c093b | 5878 | static void iwl3945_down(struct iwl3945_priv *priv) |
b481de9c ZY |
5879 | { |
5880 | mutex_lock(&priv->mutex); | |
bb8c093b | 5881 | __iwl3945_down(priv); |
b481de9c | 5882 | mutex_unlock(&priv->mutex); |
b24d22b1 | 5883 | |
bb8c093b | 5884 | iwl3945_cancel_deferred_work(priv); |
b481de9c ZY |
5885 | } |
5886 | ||
5887 | #define MAX_HW_RESTARTS 5 | |
5888 | ||
bb8c093b | 5889 | static int __iwl3945_up(struct iwl3945_priv *priv) |
b481de9c ZY |
5890 | { |
5891 | int rc, i; | |
5892 | ||
5893 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
5894 | IWL_WARNING("Exit pending; will not bring the NIC up\n"); | |
5895 | return -EIO; | |
5896 | } | |
5897 | ||
5898 | if (test_bit(STATUS_RF_KILL_SW, &priv->status)) { | |
5899 | IWL_WARNING("Radio disabled by SW RF kill (module " | |
5900 | "parameter)\n"); | |
e655b9f0 ZY |
5901 | return -ENODEV; |
5902 | } | |
5903 | ||
e903fbd4 RC |
5904 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
5905 | IWL_ERROR("ucode not available for device bringup\n"); | |
5906 | return -EIO; | |
5907 | } | |
5908 | ||
e655b9f0 ZY |
5909 | /* If platform's RF_KILL switch is NOT set to KILL */ |
5910 | if (iwl3945_read32(priv, CSR_GP_CNTRL) & | |
5911 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
5912 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
5913 | else { | |
5914 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
5915 | if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) { | |
5916 | IWL_WARNING("Radio disabled by HW RF Kill switch\n"); | |
5917 | return -ENODEV; | |
5918 | } | |
b481de9c | 5919 | } |
80fcc9e2 | 5920 | |
bb8c093b | 5921 | iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 5922 | |
bb8c093b | 5923 | rc = iwl3945_hw_nic_init(priv); |
b481de9c ZY |
5924 | if (rc) { |
5925 | IWL_ERROR("Unable to int nic\n"); | |
5926 | return rc; | |
5927 | } | |
5928 | ||
5929 | /* make sure rfkill handshake bits are cleared */ | |
bb8c093b CH |
5930 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
5931 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
5932 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
5933 | ||
5934 | /* clear (again), then enable host interrupts */ | |
bb8c093b CH |
5935 | iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF); |
5936 | iwl3945_enable_interrupts(priv); | |
b481de9c ZY |
5937 | |
5938 | /* really make sure rfkill handshake bits are cleared */ | |
bb8c093b CH |
5939 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
5940 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
5941 | |
5942 | /* Copy original ucode data image from disk into backup cache. | |
5943 | * This will be used to initialize the on-board processor's | |
5944 | * data SRAM for a clean start when the runtime program first loads. */ | |
5945 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 5946 | priv->ucode_data.len); |
b481de9c | 5947 | |
e655b9f0 ZY |
5948 | /* We return success when we resume from suspend and rf_kill is on. */ |
5949 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
5950 | return 0; | |
5951 | ||
b481de9c ZY |
5952 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
5953 | ||
bb8c093b | 5954 | iwl3945_clear_stations_table(priv); |
b481de9c ZY |
5955 | |
5956 | /* load bootstrap state machine, | |
5957 | * load bootstrap program into processor's memory, | |
5958 | * prepare to load the "initialize" uCode */ | |
bb8c093b | 5959 | rc = iwl3945_load_bsm(priv); |
b481de9c ZY |
5960 | |
5961 | if (rc) { | |
5962 | IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc); | |
5963 | continue; | |
5964 | } | |
5965 | ||
5966 | /* start card; "initialize" will load runtime ucode */ | |
bb8c093b | 5967 | iwl3945_nic_start(priv); |
b481de9c | 5968 | |
b481de9c ZY |
5969 | IWL_DEBUG_INFO(DRV_NAME " is coming up\n"); |
5970 | ||
5971 | return 0; | |
5972 | } | |
5973 | ||
5974 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
bb8c093b | 5975 | __iwl3945_down(priv); |
ebef2008 | 5976 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
5977 | |
5978 | /* tried to restart and config the device for as long as our | |
5979 | * patience could withstand */ | |
5980 | IWL_ERROR("Unable to initialize device after %d attempts.\n", i); | |
5981 | return -EIO; | |
5982 | } | |
5983 | ||
5984 | ||
5985 | /***************************************************************************** | |
5986 | * | |
5987 | * Workqueue callbacks | |
5988 | * | |
5989 | *****************************************************************************/ | |
5990 | ||
bb8c093b | 5991 | static void iwl3945_bg_init_alive_start(struct work_struct *data) |
b481de9c | 5992 | { |
bb8c093b CH |
5993 | struct iwl3945_priv *priv = |
5994 | container_of(data, struct iwl3945_priv, init_alive_start.work); | |
b481de9c ZY |
5995 | |
5996 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5997 | return; | |
5998 | ||
5999 | mutex_lock(&priv->mutex); | |
bb8c093b | 6000 | iwl3945_init_alive_start(priv); |
b481de9c ZY |
6001 | mutex_unlock(&priv->mutex); |
6002 | } | |
6003 | ||
bb8c093b | 6004 | static void iwl3945_bg_alive_start(struct work_struct *data) |
b481de9c | 6005 | { |
bb8c093b CH |
6006 | struct iwl3945_priv *priv = |
6007 | container_of(data, struct iwl3945_priv, alive_start.work); | |
b481de9c ZY |
6008 | |
6009 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6010 | return; | |
6011 | ||
6012 | mutex_lock(&priv->mutex); | |
bb8c093b | 6013 | iwl3945_alive_start(priv); |
b481de9c | 6014 | mutex_unlock(&priv->mutex); |
d54bc4e3 | 6015 | ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC); |
b481de9c ZY |
6016 | } |
6017 | ||
bb8c093b | 6018 | static void iwl3945_bg_rf_kill(struct work_struct *work) |
b481de9c | 6019 | { |
bb8c093b | 6020 | struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill); |
b481de9c ZY |
6021 | |
6022 | wake_up_interruptible(&priv->wait_command_queue); | |
6023 | ||
6024 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6025 | return; | |
6026 | ||
6027 | mutex_lock(&priv->mutex); | |
6028 | ||
bb8c093b | 6029 | if (!iwl3945_is_rfkill(priv)) { |
b481de9c ZY |
6030 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL, |
6031 | "HW and/or SW RF Kill no longer active, restarting " | |
6032 | "device\n"); | |
6033 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6034 | queue_work(priv->workqueue, &priv->restart); | |
6035 | } else { | |
6036 | ||
6037 | if (!test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
6038 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
6039 | "disabled by SW switch\n"); | |
6040 | else | |
6041 | IWL_WARNING("Radio Frequency Kill Switch is On:\n" | |
6042 | "Kill switch must be turned off for " | |
6043 | "wireless networking to work.\n"); | |
6044 | } | |
ebef2008 | 6045 | |
b481de9c | 6046 | mutex_unlock(&priv->mutex); |
80fcc9e2 | 6047 | iwl3945_rfkill_set_hw_state(priv); |
b481de9c ZY |
6048 | } |
6049 | ||
5ec03976 AK |
6050 | static void iwl3945_bg_set_monitor(struct work_struct *work) |
6051 | { | |
6052 | struct iwl3945_priv *priv = container_of(work, | |
6053 | struct iwl3945_priv, set_monitor); | |
6054 | ||
6055 | IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n"); | |
6056 | ||
6057 | mutex_lock(&priv->mutex); | |
6058 | ||
6059 | if (!iwl3945_is_ready(priv)) | |
6060 | IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n"); | |
6061 | else | |
05c914fe | 6062 | if (iwl3945_set_mode(priv, NL80211_IFTYPE_MONITOR) != 0) |
5ec03976 AK |
6063 | IWL_ERROR("iwl3945_set_mode() failed\n"); |
6064 | ||
6065 | mutex_unlock(&priv->mutex); | |
6066 | } | |
6067 | ||
b481de9c ZY |
6068 | #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ) |
6069 | ||
bb8c093b | 6070 | static void iwl3945_bg_scan_check(struct work_struct *data) |
b481de9c | 6071 | { |
bb8c093b CH |
6072 | struct iwl3945_priv *priv = |
6073 | container_of(data, struct iwl3945_priv, scan_check.work); | |
b481de9c ZY |
6074 | |
6075 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6076 | return; | |
6077 | ||
6078 | mutex_lock(&priv->mutex); | |
6079 | if (test_bit(STATUS_SCANNING, &priv->status) || | |
6080 | test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
6081 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, | |
6082 | "Scan completion watchdog resetting adapter (%dms)\n", | |
6083 | jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG)); | |
15e869d8 | 6084 | |
b481de9c | 6085 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) |
bb8c093b | 6086 | iwl3945_send_scan_abort(priv); |
b481de9c ZY |
6087 | } |
6088 | mutex_unlock(&priv->mutex); | |
6089 | } | |
6090 | ||
bb8c093b | 6091 | static void iwl3945_bg_request_scan(struct work_struct *data) |
b481de9c | 6092 | { |
bb8c093b CH |
6093 | struct iwl3945_priv *priv = |
6094 | container_of(data, struct iwl3945_priv, request_scan); | |
6095 | struct iwl3945_host_cmd cmd = { | |
b481de9c | 6096 | .id = REPLY_SCAN_CMD, |
bb8c093b | 6097 | .len = sizeof(struct iwl3945_scan_cmd), |
b481de9c ZY |
6098 | .meta.flags = CMD_SIZE_HUGE, |
6099 | }; | |
6100 | int rc = 0; | |
bb8c093b | 6101 | struct iwl3945_scan_cmd *scan; |
b481de9c | 6102 | struct ieee80211_conf *conf = NULL; |
f9340520 | 6103 | u8 n_probes = 2; |
8318d78a | 6104 | enum ieee80211_band band; |
b481de9c ZY |
6105 | |
6106 | conf = ieee80211_get_hw_conf(priv->hw); | |
6107 | ||
6108 | mutex_lock(&priv->mutex); | |
6109 | ||
bb8c093b | 6110 | if (!iwl3945_is_ready(priv)) { |
b481de9c ZY |
6111 | IWL_WARNING("request scan called when driver not ready.\n"); |
6112 | goto done; | |
6113 | } | |
6114 | ||
6115 | /* Make sure the scan wasn't cancelled before this queued work | |
6116 | * was given the chance to run... */ | |
6117 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
6118 | goto done; | |
6119 | ||
6120 | /* This should never be called or scheduled if there is currently | |
6121 | * a scan active in the hardware. */ | |
6122 | if (test_bit(STATUS_SCAN_HW, &priv->status)) { | |
6123 | IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. " | |
6124 | "Ignoring second request.\n"); | |
6125 | rc = -EIO; | |
6126 | goto done; | |
6127 | } | |
6128 | ||
6129 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
6130 | IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n"); | |
6131 | goto done; | |
6132 | } | |
6133 | ||
6134 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
6135 | IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n"); | |
6136 | goto done; | |
6137 | } | |
6138 | ||
bb8c093b | 6139 | if (iwl3945_is_rfkill(priv)) { |
b481de9c ZY |
6140 | IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n"); |
6141 | goto done; | |
6142 | } | |
6143 | ||
6144 | if (!test_bit(STATUS_READY, &priv->status)) { | |
6145 | IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n"); | |
6146 | goto done; | |
6147 | } | |
6148 | ||
6149 | if (!priv->scan_bands) { | |
6150 | IWL_DEBUG_HC("Aborting scan due to no requested bands\n"); | |
6151 | goto done; | |
6152 | } | |
6153 | ||
6154 | if (!priv->scan) { | |
bb8c093b | 6155 | priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) + |
b481de9c ZY |
6156 | IWL_MAX_SCAN_SIZE, GFP_KERNEL); |
6157 | if (!priv->scan) { | |
6158 | rc = -ENOMEM; | |
6159 | goto done; | |
6160 | } | |
6161 | } | |
6162 | scan = priv->scan; | |
bb8c093b | 6163 | memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE); |
b481de9c ZY |
6164 | |
6165 | scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; | |
6166 | scan->quiet_time = IWL_ACTIVE_QUIET_TIME; | |
6167 | ||
bb8c093b | 6168 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
6169 | u16 interval = 0; |
6170 | u32 extra; | |
6171 | u32 suspend_time = 100; | |
6172 | u32 scan_suspend_time = 100; | |
6173 | unsigned long flags; | |
6174 | ||
6175 | IWL_DEBUG_INFO("Scanning while associated...\n"); | |
6176 | ||
6177 | spin_lock_irqsave(&priv->lock, flags); | |
6178 | interval = priv->beacon_int; | |
6179 | spin_unlock_irqrestore(&priv->lock, flags); | |
6180 | ||
6181 | scan->suspend_time = 0; | |
15e869d8 | 6182 | scan->max_out_time = cpu_to_le32(200 * 1024); |
b481de9c ZY |
6183 | if (!interval) |
6184 | interval = suspend_time; | |
6185 | /* | |
6186 | * suspend time format: | |
6187 | * 0-19: beacon interval in usec (time before exec.) | |
6188 | * 20-23: 0 | |
6189 | * 24-31: number of beacons (suspend between channels) | |
6190 | */ | |
6191 | ||
6192 | extra = (suspend_time / interval) << 24; | |
6193 | scan_suspend_time = 0xFF0FFFFF & | |
6194 | (extra | ((suspend_time % interval) * 1024)); | |
6195 | ||
6196 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
6197 | IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n", | |
6198 | scan_suspend_time, interval); | |
6199 | } | |
6200 | ||
6201 | /* We should add the ability for user to lock to PASSIVE ONLY */ | |
6202 | if (priv->one_direct_scan) { | |
6203 | IWL_DEBUG_SCAN | |
6204 | ("Kicking off one direct scan for '%s'\n", | |
bb8c093b | 6205 | iwl3945_escape_essid(priv->direct_ssid, |
b481de9c ZY |
6206 | priv->direct_ssid_len)); |
6207 | scan->direct_scan[0].id = WLAN_EID_SSID; | |
6208 | scan->direct_scan[0].len = priv->direct_ssid_len; | |
6209 | memcpy(scan->direct_scan[0].ssid, | |
6210 | priv->direct_ssid, priv->direct_ssid_len); | |
f9340520 | 6211 | n_probes++; |
bb8c093b | 6212 | } else if (!iwl3945_is_associated(priv) && priv->essid_len) { |
786b4557 BM |
6213 | IWL_DEBUG_SCAN |
6214 | ("Kicking off one direct scan for '%s' when not associated\n", | |
6215 | iwl3945_escape_essid(priv->essid, priv->essid_len)); | |
b481de9c ZY |
6216 | scan->direct_scan[0].id = WLAN_EID_SSID; |
6217 | scan->direct_scan[0].len = priv->essid_len; | |
6218 | memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len); | |
f9340520 AK |
6219 | n_probes++; |
6220 | } else | |
786b4557 | 6221 | IWL_DEBUG_SCAN("Kicking off one indirect scan.\n"); |
b481de9c ZY |
6222 | |
6223 | /* We don't build a direct scan probe request; the uCode will do | |
6224 | * that based on the direct_mask added to each channel entry */ | |
6225 | scan->tx_cmd.len = cpu_to_le16( | |
bb8c093b | 6226 | iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data, |
18904f58 | 6227 | IWL_MAX_SCAN_SIZE - sizeof(*scan), 0)); |
b481de9c ZY |
6228 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; |
6229 | scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id; | |
6230 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
6231 | ||
6232 | /* flags + rate selection */ | |
6233 | ||
66b5004d | 6234 | if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) { |
b481de9c ZY |
6235 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; |
6236 | scan->tx_cmd.rate = IWL_RATE_1M_PLCP; | |
6237 | scan->good_CRC_th = 0; | |
8318d78a | 6238 | band = IEEE80211_BAND_2GHZ; |
66b5004d | 6239 | } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) { |
b481de9c ZY |
6240 | scan->tx_cmd.rate = IWL_RATE_6M_PLCP; |
6241 | scan->good_CRC_th = IWL_GOOD_CRC_TH; | |
8318d78a | 6242 | band = IEEE80211_BAND_5GHZ; |
66b5004d | 6243 | } else { |
b481de9c ZY |
6244 | IWL_WARNING("Invalid scan band count\n"); |
6245 | goto done; | |
6246 | } | |
6247 | ||
6248 | /* select Rx antennas */ | |
6249 | scan->flags |= iwl3945_get_antenna_flags(priv); | |
6250 | ||
05c914fe | 6251 | if (priv->iw_mode == NL80211_IFTYPE_MONITOR) |
b481de9c ZY |
6252 | scan->filter_flags = RXON_FILTER_PROMISC_MSK; |
6253 | ||
f9340520 AK |
6254 | scan->channel_count = |
6255 | iwl3945_get_channels_for_scan(priv, band, 1, /* active */ | |
6256 | n_probes, | |
6257 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); | |
b481de9c | 6258 | |
14b54336 RC |
6259 | if (scan->channel_count == 0) { |
6260 | IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count); | |
6261 | goto done; | |
6262 | } | |
6263 | ||
b481de9c | 6264 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + |
bb8c093b | 6265 | scan->channel_count * sizeof(struct iwl3945_scan_channel); |
b481de9c ZY |
6266 | cmd.data = scan; |
6267 | scan->len = cpu_to_le16(cmd.len); | |
6268 | ||
6269 | set_bit(STATUS_SCAN_HW, &priv->status); | |
bb8c093b | 6270 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
6271 | if (rc) |
6272 | goto done; | |
6273 | ||
6274 | queue_delayed_work(priv->workqueue, &priv->scan_check, | |
6275 | IWL_SCAN_CHECK_WATCHDOG); | |
6276 | ||
6277 | mutex_unlock(&priv->mutex); | |
6278 | return; | |
6279 | ||
6280 | done: | |
2420ebc1 MA |
6281 | /* can not perform scan make sure we clear scanning |
6282 | * bits from status so next scan request can be performed. | |
6283 | * if we dont clear scanning status bit here all next scan | |
6284 | * will fail | |
6285 | */ | |
6286 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
6287 | clear_bit(STATUS_SCANNING, &priv->status); | |
6288 | ||
01ebd063 | 6289 | /* inform mac80211 scan aborted */ |
b481de9c ZY |
6290 | queue_work(priv->workqueue, &priv->scan_completed); |
6291 | mutex_unlock(&priv->mutex); | |
6292 | } | |
6293 | ||
bb8c093b | 6294 | static void iwl3945_bg_up(struct work_struct *data) |
b481de9c | 6295 | { |
bb8c093b | 6296 | struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up); |
b481de9c ZY |
6297 | |
6298 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6299 | return; | |
6300 | ||
6301 | mutex_lock(&priv->mutex); | |
bb8c093b | 6302 | __iwl3945_up(priv); |
b481de9c | 6303 | mutex_unlock(&priv->mutex); |
80fcc9e2 | 6304 | iwl3945_rfkill_set_hw_state(priv); |
b481de9c ZY |
6305 | } |
6306 | ||
bb8c093b | 6307 | static void iwl3945_bg_restart(struct work_struct *data) |
b481de9c | 6308 | { |
bb8c093b | 6309 | struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart); |
b481de9c ZY |
6310 | |
6311 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6312 | return; | |
6313 | ||
bb8c093b | 6314 | iwl3945_down(priv); |
b481de9c ZY |
6315 | queue_work(priv->workqueue, &priv->up); |
6316 | } | |
6317 | ||
bb8c093b | 6318 | static void iwl3945_bg_rx_replenish(struct work_struct *data) |
b481de9c | 6319 | { |
bb8c093b CH |
6320 | struct iwl3945_priv *priv = |
6321 | container_of(data, struct iwl3945_priv, rx_replenish); | |
b481de9c ZY |
6322 | |
6323 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6324 | return; | |
6325 | ||
6326 | mutex_lock(&priv->mutex); | |
bb8c093b | 6327 | iwl3945_rx_replenish(priv); |
b481de9c ZY |
6328 | mutex_unlock(&priv->mutex); |
6329 | } | |
6330 | ||
7878a5a4 MA |
6331 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
6332 | ||
cd56d331 | 6333 | static void iwl3945_post_associate(struct iwl3945_priv *priv) |
b481de9c | 6334 | { |
b481de9c ZY |
6335 | int rc = 0; |
6336 | struct ieee80211_conf *conf = NULL; | |
0795af57 | 6337 | DECLARE_MAC_BUF(mac); |
b481de9c | 6338 | |
05c914fe | 6339 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
3ac7f146 | 6340 | IWL_ERROR("%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
6341 | return; |
6342 | } | |
6343 | ||
6344 | ||
0795af57 JP |
6345 | IWL_DEBUG_ASSOC("Associated as %d to: %s\n", |
6346 | priv->assoc_id, | |
6347 | print_mac(mac, priv->active_rxon.bssid_addr)); | |
b481de9c ZY |
6348 | |
6349 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6350 | return; | |
6351 | ||
322a9811 | 6352 | if (!priv->vif || !priv->is_open) |
6ef89d0a | 6353 | return; |
322a9811 | 6354 | |
bb8c093b | 6355 | iwl3945_scan_cancel_timeout(priv, 200); |
15e869d8 | 6356 | |
b481de9c ZY |
6357 | conf = ieee80211_get_hw_conf(priv->hw); |
6358 | ||
6359 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6360 | iwl3945_commit_rxon(priv); |
b481de9c | 6361 | |
bb8c093b CH |
6362 | memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd)); |
6363 | iwl3945_setup_rxon_timing(priv); | |
6364 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING, | |
b481de9c ZY |
6365 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
6366 | if (rc) | |
6367 | IWL_WARNING("REPLY_RXON_TIMING failed - " | |
6368 | "Attempting to continue.\n"); | |
6369 | ||
6370 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
6371 | ||
6372 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
6373 | ||
6374 | IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n", | |
6375 | priv->assoc_id, priv->beacon_int); | |
6376 | ||
6377 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
6378 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
6379 | else | |
6380 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6381 | ||
6382 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
6383 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
6384 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
6385 | else | |
6386 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
6387 | ||
05c914fe | 6388 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
6389 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
6390 | ||
6391 | } | |
6392 | ||
bb8c093b | 6393 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6394 | |
6395 | switch (priv->iw_mode) { | |
05c914fe | 6396 | case NL80211_IFTYPE_STATION: |
bb8c093b | 6397 | iwl3945_rate_scale_init(priv->hw, IWL_AP_ID); |
b481de9c ZY |
6398 | break; |
6399 | ||
05c914fe | 6400 | case NL80211_IFTYPE_ADHOC: |
b481de9c ZY |
6401 | |
6402 | /* clear out the station table */ | |
bb8c093b | 6403 | iwl3945_clear_stations_table(priv); |
b481de9c | 6404 | |
bb8c093b CH |
6405 | iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0); |
6406 | iwl3945_add_station(priv, priv->bssid, 0, 0); | |
b481de9c | 6407 | iwl3945_sync_sta(priv, IWL_STA_ID, |
8318d78a | 6408 | (priv->band == IEEE80211_BAND_5GHZ) ? |
b481de9c ZY |
6409 | IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP, |
6410 | CMD_ASYNC); | |
bb8c093b CH |
6411 | iwl3945_rate_scale_init(priv->hw, IWL_STA_ID); |
6412 | iwl3945_send_beacon_cmd(priv); | |
b481de9c ZY |
6413 | |
6414 | break; | |
6415 | ||
6416 | default: | |
6417 | IWL_ERROR("%s Should not be called in %d mode\n", | |
3ac7f146 | 6418 | __func__, priv->iw_mode); |
b481de9c ZY |
6419 | break; |
6420 | } | |
6421 | ||
bb8c093b | 6422 | iwl3945_activate_qos(priv, 0); |
292ae174 | 6423 | |
7878a5a4 MA |
6424 | /* we have just associated, don't start scan too early */ |
6425 | priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN; | |
cd56d331 AK |
6426 | } |
6427 | ||
bb8c093b | 6428 | static void iwl3945_bg_abort_scan(struct work_struct *work) |
b481de9c | 6429 | { |
bb8c093b | 6430 | struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan); |
b481de9c | 6431 | |
bb8c093b | 6432 | if (!iwl3945_is_ready(priv)) |
b481de9c ZY |
6433 | return; |
6434 | ||
6435 | mutex_lock(&priv->mutex); | |
6436 | ||
6437 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
bb8c093b | 6438 | iwl3945_send_scan_abort(priv); |
b481de9c ZY |
6439 | |
6440 | mutex_unlock(&priv->mutex); | |
6441 | } | |
6442 | ||
76bb77e0 ZY |
6443 | static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf); |
6444 | ||
bb8c093b | 6445 | static void iwl3945_bg_scan_completed(struct work_struct *work) |
b481de9c | 6446 | { |
bb8c093b CH |
6447 | struct iwl3945_priv *priv = |
6448 | container_of(work, struct iwl3945_priv, scan_completed); | |
b481de9c ZY |
6449 | |
6450 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n"); | |
6451 | ||
6452 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6453 | return; | |
6454 | ||
a0646470 ZY |
6455 | if (test_bit(STATUS_CONF_PENDING, &priv->status)) |
6456 | iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw)); | |
76bb77e0 | 6457 | |
b481de9c ZY |
6458 | ieee80211_scan_completed(priv->hw); |
6459 | ||
6460 | /* Since setting the TXPOWER may have been deferred while | |
6461 | * performing the scan, fire one off */ | |
6462 | mutex_lock(&priv->mutex); | |
bb8c093b | 6463 | iwl3945_hw_reg_send_txpower(priv); |
b481de9c ZY |
6464 | mutex_unlock(&priv->mutex); |
6465 | } | |
6466 | ||
6467 | /***************************************************************************** | |
6468 | * | |
6469 | * mac80211 entry point functions | |
6470 | * | |
6471 | *****************************************************************************/ | |
6472 | ||
5a66926a ZY |
6473 | #define UCODE_READY_TIMEOUT (2 * HZ) |
6474 | ||
bb8c093b | 6475 | static int iwl3945_mac_start(struct ieee80211_hw *hw) |
b481de9c | 6476 | { |
bb8c093b | 6477 | struct iwl3945_priv *priv = hw->priv; |
5a66926a | 6478 | int ret; |
b481de9c ZY |
6479 | |
6480 | IWL_DEBUG_MAC80211("enter\n"); | |
6481 | ||
5a66926a ZY |
6482 | if (pci_enable_device(priv->pci_dev)) { |
6483 | IWL_ERROR("Fail to pci_enable_device\n"); | |
6484 | return -ENODEV; | |
6485 | } | |
6486 | pci_restore_state(priv->pci_dev); | |
6487 | pci_enable_msi(priv->pci_dev); | |
6488 | ||
6489 | ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED, | |
6490 | DRV_NAME, priv); | |
6491 | if (ret) { | |
6492 | IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq); | |
6493 | goto out_disable_msi; | |
6494 | } | |
6495 | ||
b481de9c ZY |
6496 | /* we should be verifying the device is ready to be opened */ |
6497 | mutex_lock(&priv->mutex); | |
6498 | ||
5a66926a ZY |
6499 | memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd)); |
6500 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... | |
6501 | * ucode filename and max sizes are card-specific. */ | |
6502 | ||
6503 | if (!priv->ucode_code.len) { | |
6504 | ret = iwl3945_read_ucode(priv); | |
6505 | if (ret) { | |
6506 | IWL_ERROR("Could not read microcode: %d\n", ret); | |
6507 | mutex_unlock(&priv->mutex); | |
6508 | goto out_release_irq; | |
6509 | } | |
6510 | } | |
b481de9c | 6511 | |
e655b9f0 | 6512 | ret = __iwl3945_up(priv); |
b481de9c ZY |
6513 | |
6514 | mutex_unlock(&priv->mutex); | |
5a66926a | 6515 | |
80fcc9e2 AG |
6516 | iwl3945_rfkill_set_hw_state(priv); |
6517 | ||
e655b9f0 ZY |
6518 | if (ret) |
6519 | goto out_release_irq; | |
6520 | ||
6521 | IWL_DEBUG_INFO("Start UP work.\n"); | |
6522 | ||
6523 | if (test_bit(STATUS_IN_SUSPEND, &priv->status)) | |
6524 | return 0; | |
6525 | ||
5a66926a ZY |
6526 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from |
6527 | * mac80211 will not be run successfully. */ | |
6528 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
6529 | test_bit(STATUS_READY, &priv->status), | |
6530 | UCODE_READY_TIMEOUT); | |
6531 | if (!ret) { | |
6532 | if (!test_bit(STATUS_READY, &priv->status)) { | |
6533 | IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n", | |
6534 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
6535 | ret = -ETIMEDOUT; | |
6536 | goto out_release_irq; | |
6537 | } | |
6538 | } | |
6539 | ||
e655b9f0 | 6540 | priv->is_open = 1; |
b481de9c ZY |
6541 | IWL_DEBUG_MAC80211("leave\n"); |
6542 | return 0; | |
5a66926a ZY |
6543 | |
6544 | out_release_irq: | |
6545 | free_irq(priv->pci_dev->irq, priv); | |
6546 | out_disable_msi: | |
6547 | pci_disable_msi(priv->pci_dev); | |
e655b9f0 ZY |
6548 | pci_disable_device(priv->pci_dev); |
6549 | priv->is_open = 0; | |
6550 | IWL_DEBUG_MAC80211("leave - failed\n"); | |
5a66926a | 6551 | return ret; |
b481de9c ZY |
6552 | } |
6553 | ||
bb8c093b | 6554 | static void iwl3945_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 6555 | { |
bb8c093b | 6556 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
6557 | |
6558 | IWL_DEBUG_MAC80211("enter\n"); | |
6ef89d0a | 6559 | |
e655b9f0 ZY |
6560 | if (!priv->is_open) { |
6561 | IWL_DEBUG_MAC80211("leave - skip\n"); | |
6562 | return; | |
6563 | } | |
6564 | ||
b481de9c | 6565 | priv->is_open = 0; |
5a66926a ZY |
6566 | |
6567 | if (iwl3945_is_ready_rf(priv)) { | |
e655b9f0 ZY |
6568 | /* stop mac, cancel any scan request and clear |
6569 | * RXON_FILTER_ASSOC_MSK BIT | |
6570 | */ | |
5a66926a ZY |
6571 | mutex_lock(&priv->mutex); |
6572 | iwl3945_scan_cancel_timeout(priv, 100); | |
fde3571f | 6573 | mutex_unlock(&priv->mutex); |
fde3571f MA |
6574 | } |
6575 | ||
5a66926a ZY |
6576 | iwl3945_down(priv); |
6577 | ||
6578 | flush_workqueue(priv->workqueue); | |
6579 | free_irq(priv->pci_dev->irq, priv); | |
6580 | pci_disable_msi(priv->pci_dev); | |
6581 | pci_save_state(priv->pci_dev); | |
6582 | pci_disable_device(priv->pci_dev); | |
6ef89d0a | 6583 | |
b481de9c | 6584 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
6585 | } |
6586 | ||
e039fa4a | 6587 | static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 6588 | { |
bb8c093b | 6589 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
6590 | |
6591 | IWL_DEBUG_MAC80211("enter\n"); | |
6592 | ||
b481de9c | 6593 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 6594 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 6595 | |
e039fa4a | 6596 | if (iwl3945_tx_skb(priv, skb)) |
b481de9c ZY |
6597 | dev_kfree_skb_any(skb); |
6598 | ||
6599 | IWL_DEBUG_MAC80211("leave\n"); | |
6600 | return 0; | |
6601 | } | |
6602 | ||
bb8c093b | 6603 | static int iwl3945_mac_add_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
6604 | struct ieee80211_if_init_conf *conf) |
6605 | { | |
bb8c093b | 6606 | struct iwl3945_priv *priv = hw->priv; |
b481de9c | 6607 | unsigned long flags; |
0795af57 | 6608 | DECLARE_MAC_BUF(mac); |
b481de9c | 6609 | |
32bfd35d | 6610 | IWL_DEBUG_MAC80211("enter: type %d\n", conf->type); |
b481de9c | 6611 | |
32bfd35d JB |
6612 | if (priv->vif) { |
6613 | IWL_DEBUG_MAC80211("leave - vif != NULL\n"); | |
864792e3 | 6614 | return -EOPNOTSUPP; |
b481de9c ZY |
6615 | } |
6616 | ||
6617 | spin_lock_irqsave(&priv->lock, flags); | |
32bfd35d | 6618 | priv->vif = conf->vif; |
b481de9c ZY |
6619 | |
6620 | spin_unlock_irqrestore(&priv->lock, flags); | |
6621 | ||
6622 | mutex_lock(&priv->mutex); | |
864792e3 TW |
6623 | |
6624 | if (conf->mac_addr) { | |
6625 | IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr)); | |
6626 | memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); | |
6627 | } | |
6628 | ||
5a66926a ZY |
6629 | if (iwl3945_is_ready(priv)) |
6630 | iwl3945_set_mode(priv, conf->type); | |
b481de9c | 6631 | |
b481de9c ZY |
6632 | mutex_unlock(&priv->mutex); |
6633 | ||
5a66926a | 6634 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
6635 | return 0; |
6636 | } | |
6637 | ||
6638 | /** | |
bb8c093b | 6639 | * iwl3945_mac_config - mac80211 config callback |
b481de9c ZY |
6640 | * |
6641 | * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to | |
6642 | * be set inappropriately and the driver currently sets the hardware up to | |
6643 | * use it whenever needed. | |
6644 | */ | |
bb8c093b | 6645 | static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) |
b481de9c | 6646 | { |
bb8c093b CH |
6647 | struct iwl3945_priv *priv = hw->priv; |
6648 | const struct iwl3945_channel_info *ch_info; | |
b481de9c | 6649 | unsigned long flags; |
76bb77e0 | 6650 | int ret = 0; |
b481de9c ZY |
6651 | |
6652 | mutex_lock(&priv->mutex); | |
8318d78a | 6653 | IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value); |
b481de9c | 6654 | |
bb8c093b | 6655 | if (!iwl3945_is_ready(priv)) { |
b481de9c | 6656 | IWL_DEBUG_MAC80211("leave - not ready\n"); |
76bb77e0 ZY |
6657 | ret = -EIO; |
6658 | goto out; | |
b481de9c ZY |
6659 | } |
6660 | ||
bb8c093b | 6661 | if (unlikely(!iwl3945_param_disable_hw_scan && |
b481de9c | 6662 | test_bit(STATUS_SCANNING, &priv->status))) { |
a0646470 ZY |
6663 | IWL_DEBUG_MAC80211("leave - scanning\n"); |
6664 | set_bit(STATUS_CONF_PENDING, &priv->status); | |
b481de9c | 6665 | mutex_unlock(&priv->mutex); |
a0646470 | 6666 | return 0; |
b481de9c ZY |
6667 | } |
6668 | ||
6669 | spin_lock_irqsave(&priv->lock, flags); | |
6670 | ||
8318d78a JB |
6671 | ch_info = iwl3945_get_channel_info(priv, conf->channel->band, |
6672 | conf->channel->hw_value); | |
b481de9c | 6673 | if (!is_channel_valid(ch_info)) { |
66b5004d | 6674 | IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n", |
8318d78a | 6675 | conf->channel->hw_value, conf->channel->band); |
b481de9c ZY |
6676 | IWL_DEBUG_MAC80211("leave - invalid channel\n"); |
6677 | spin_unlock_irqrestore(&priv->lock, flags); | |
76bb77e0 ZY |
6678 | ret = -EINVAL; |
6679 | goto out; | |
b481de9c ZY |
6680 | } |
6681 | ||
8318d78a | 6682 | iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value); |
b481de9c | 6683 | |
8318d78a | 6684 | iwl3945_set_flags_for_phymode(priv, conf->channel->band); |
b481de9c ZY |
6685 | |
6686 | /* The list of supported rates and rate mask can be different | |
6687 | * for each phymode; since the phymode may have changed, reset | |
6688 | * the rate mask to what mac80211 lists */ | |
bb8c093b | 6689 | iwl3945_set_rate(priv); |
b481de9c ZY |
6690 | |
6691 | spin_unlock_irqrestore(&priv->lock, flags); | |
6692 | ||
6693 | #ifdef IEEE80211_CONF_CHANNEL_SWITCH | |
6694 | if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) { | |
bb8c093b | 6695 | iwl3945_hw_channel_switch(priv, conf->channel); |
76bb77e0 | 6696 | goto out; |
b481de9c ZY |
6697 | } |
6698 | #endif | |
6699 | ||
bb8c093b | 6700 | iwl3945_radio_kill_sw(priv, !conf->radio_enabled); |
b481de9c ZY |
6701 | |
6702 | if (!conf->radio_enabled) { | |
6703 | IWL_DEBUG_MAC80211("leave - radio disabled\n"); | |
76bb77e0 | 6704 | goto out; |
b481de9c ZY |
6705 | } |
6706 | ||
bb8c093b | 6707 | if (iwl3945_is_rfkill(priv)) { |
b481de9c | 6708 | IWL_DEBUG_MAC80211("leave - RF kill\n"); |
76bb77e0 ZY |
6709 | ret = -EIO; |
6710 | goto out; | |
b481de9c ZY |
6711 | } |
6712 | ||
bb8c093b | 6713 | iwl3945_set_rate(priv); |
b481de9c ZY |
6714 | |
6715 | if (memcmp(&priv->active_rxon, | |
6716 | &priv->staging_rxon, sizeof(priv->staging_rxon))) | |
bb8c093b | 6717 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6718 | else |
6719 | IWL_DEBUG_INFO("No re-sending same RXON configuration.\n"); | |
6720 | ||
6721 | IWL_DEBUG_MAC80211("leave\n"); | |
6722 | ||
76bb77e0 | 6723 | out: |
a0646470 | 6724 | clear_bit(STATUS_CONF_PENDING, &priv->status); |
b481de9c | 6725 | mutex_unlock(&priv->mutex); |
76bb77e0 | 6726 | return ret; |
b481de9c ZY |
6727 | } |
6728 | ||
bb8c093b | 6729 | static void iwl3945_config_ap(struct iwl3945_priv *priv) |
b481de9c ZY |
6730 | { |
6731 | int rc = 0; | |
6732 | ||
d986bcd1 | 6733 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
6734 | return; |
6735 | ||
6736 | /* The following should be done only at AP bring up */ | |
5d1e2325 | 6737 | if (!(iwl3945_is_associated(priv))) { |
b481de9c ZY |
6738 | |
6739 | /* RXON - unassoc (to set timing command) */ | |
6740 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6741 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6742 | |
6743 | /* RXON Timing */ | |
bb8c093b CH |
6744 | memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd)); |
6745 | iwl3945_setup_rxon_timing(priv); | |
6746 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING, | |
b481de9c ZY |
6747 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
6748 | if (rc) | |
6749 | IWL_WARNING("REPLY_RXON_TIMING failed - " | |
6750 | "Attempting to continue.\n"); | |
6751 | ||
6752 | /* FIXME: what should be the assoc_id for AP? */ | |
6753 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
6754 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
6755 | priv->staging_rxon.flags |= | |
6756 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
6757 | else | |
6758 | priv->staging_rxon.flags &= | |
6759 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6760 | ||
6761 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
6762 | if (priv->assoc_capability & | |
6763 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
6764 | priv->staging_rxon.flags |= | |
6765 | RXON_FLG_SHORT_SLOT_MSK; | |
6766 | else | |
6767 | priv->staging_rxon.flags &= | |
6768 | ~RXON_FLG_SHORT_SLOT_MSK; | |
6769 | ||
05c914fe | 6770 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
6771 | priv->staging_rxon.flags &= |
6772 | ~RXON_FLG_SHORT_SLOT_MSK; | |
6773 | } | |
6774 | /* restore RXON assoc */ | |
6775 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
bb8c093b CH |
6776 | iwl3945_commit_rxon(priv); |
6777 | iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0); | |
556f8db7 | 6778 | } |
bb8c093b | 6779 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
6780 | |
6781 | /* FIXME - we need to add code here to detect a totally new | |
6782 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
6783 | * clear sta table, add BCAST sta... */ | |
6784 | } | |
6785 | ||
9d139c81 JB |
6786 | /* temporary */ |
6787 | static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb); | |
6788 | ||
32bfd35d JB |
6789 | static int iwl3945_mac_config_interface(struct ieee80211_hw *hw, |
6790 | struct ieee80211_vif *vif, | |
b481de9c ZY |
6791 | struct ieee80211_if_conf *conf) |
6792 | { | |
bb8c093b | 6793 | struct iwl3945_priv *priv = hw->priv; |
0795af57 | 6794 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
6795 | unsigned long flags; |
6796 | int rc; | |
6797 | ||
6798 | if (conf == NULL) | |
6799 | return -EIO; | |
6800 | ||
b716bb91 EG |
6801 | if (priv->vif != vif) { |
6802 | IWL_DEBUG_MAC80211("leave - priv->vif != vif\n"); | |
b716bb91 EG |
6803 | return 0; |
6804 | } | |
6805 | ||
9d139c81 | 6806 | /* handle this temporarily here */ |
05c914fe | 6807 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC && |
9d139c81 JB |
6808 | conf->changed & IEEE80211_IFCC_BEACON) { |
6809 | struct sk_buff *beacon = ieee80211_beacon_get(hw, vif); | |
6810 | if (!beacon) | |
6811 | return -ENOMEM; | |
6812 | rc = iwl3945_mac_beacon_update(hw, beacon); | |
6813 | if (rc) | |
6814 | return rc; | |
6815 | } | |
6816 | ||
4150c572 JB |
6817 | /* XXX: this MUST use conf->mac_addr */ |
6818 | ||
05c914fe | 6819 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
9d139c81 | 6820 | (!conf->ssid_len)) { |
b481de9c ZY |
6821 | IWL_DEBUG_MAC80211 |
6822 | ("Leaving in AP mode because HostAPD is not ready.\n"); | |
6823 | return 0; | |
6824 | } | |
6825 | ||
5a66926a ZY |
6826 | if (!iwl3945_is_alive(priv)) |
6827 | return -EAGAIN; | |
6828 | ||
b481de9c ZY |
6829 | mutex_lock(&priv->mutex); |
6830 | ||
b481de9c | 6831 | if (conf->bssid) |
0795af57 JP |
6832 | IWL_DEBUG_MAC80211("bssid: %s\n", |
6833 | print_mac(mac, conf->bssid)); | |
b481de9c | 6834 | |
4150c572 JB |
6835 | /* |
6836 | * very dubious code was here; the probe filtering flag is never set: | |
6837 | * | |
b481de9c ZY |
6838 | if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) && |
6839 | !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) { | |
4150c572 | 6840 | */ |
b481de9c | 6841 | |
05c914fe | 6842 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
b481de9c ZY |
6843 | if (!conf->bssid) { |
6844 | conf->bssid = priv->mac_addr; | |
6845 | memcpy(priv->bssid, priv->mac_addr, ETH_ALEN); | |
0795af57 JP |
6846 | IWL_DEBUG_MAC80211("bssid was set to: %s\n", |
6847 | print_mac(mac, conf->bssid)); | |
b481de9c ZY |
6848 | } |
6849 | if (priv->ibss_beacon) | |
6850 | dev_kfree_skb(priv->ibss_beacon); | |
6851 | ||
9d139c81 | 6852 | priv->ibss_beacon = ieee80211_beacon_get(hw, vif); |
b481de9c ZY |
6853 | } |
6854 | ||
fde3571f MA |
6855 | if (iwl3945_is_rfkill(priv)) |
6856 | goto done; | |
6857 | ||
b481de9c ZY |
6858 | if (conf->bssid && !is_zero_ether_addr(conf->bssid) && |
6859 | !is_multicast_ether_addr(conf->bssid)) { | |
6860 | /* If there is currently a HW scan going on in the background | |
6861 | * then we need to cancel it else the RXON below will fail. */ | |
bb8c093b | 6862 | if (iwl3945_scan_cancel_timeout(priv, 100)) { |
b481de9c ZY |
6863 | IWL_WARNING("Aborted scan still in progress " |
6864 | "after 100ms\n"); | |
6865 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
6866 | mutex_unlock(&priv->mutex); | |
6867 | return -EAGAIN; | |
6868 | } | |
6869 | memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN); | |
6870 | ||
6871 | /* TODO: Audit driver for usage of these members and see | |
6872 | * if mac80211 deprecates them (priv->bssid looks like it | |
6873 | * shouldn't be there, but I haven't scanned the IBSS code | |
6874 | * to verify) - jpk */ | |
6875 | memcpy(priv->bssid, conf->bssid, ETH_ALEN); | |
6876 | ||
05c914fe | 6877 | if (priv->iw_mode == NL80211_IFTYPE_AP) |
bb8c093b | 6878 | iwl3945_config_ap(priv); |
b481de9c | 6879 | else { |
bb8c093b | 6880 | rc = iwl3945_commit_rxon(priv); |
05c914fe | 6881 | if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc) |
bb8c093b | 6882 | iwl3945_add_station(priv, |
556f8db7 | 6883 | priv->active_rxon.bssid_addr, 1, 0); |
b481de9c ZY |
6884 | } |
6885 | ||
6886 | } else { | |
bb8c093b | 6887 | iwl3945_scan_cancel_timeout(priv, 100); |
b481de9c | 6888 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 6889 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6890 | } |
6891 | ||
fde3571f | 6892 | done: |
b481de9c ZY |
6893 | spin_lock_irqsave(&priv->lock, flags); |
6894 | if (!conf->ssid_len) | |
6895 | memset(priv->essid, 0, IW_ESSID_MAX_SIZE); | |
6896 | else | |
6897 | memcpy(priv->essid, conf->ssid, conf->ssid_len); | |
6898 | ||
6899 | priv->essid_len = conf->ssid_len; | |
6900 | spin_unlock_irqrestore(&priv->lock, flags); | |
6901 | ||
6902 | IWL_DEBUG_MAC80211("leave\n"); | |
6903 | mutex_unlock(&priv->mutex); | |
6904 | ||
6905 | return 0; | |
6906 | } | |
6907 | ||
bb8c093b | 6908 | static void iwl3945_configure_filter(struct ieee80211_hw *hw, |
4150c572 JB |
6909 | unsigned int changed_flags, |
6910 | unsigned int *total_flags, | |
6911 | int mc_count, struct dev_addr_list *mc_list) | |
6912 | { | |
5ec03976 | 6913 | struct iwl3945_priv *priv = hw->priv; |
25b3f57c RF |
6914 | |
6915 | if (changed_flags & (*total_flags) & FIF_OTHER_BSS) { | |
6916 | IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n", | |
05c914fe | 6917 | NL80211_IFTYPE_MONITOR, |
25b3f57c RF |
6918 | changed_flags, *total_flags); |
6919 | /* queue work 'cuz mac80211 is holding a lock which | |
6920 | * prevents us from issuing (synchronous) f/w cmds */ | |
6921 | queue_work(priv->workqueue, &priv->set_monitor); | |
5ec03976 | 6922 | } |
25b3f57c RF |
6923 | *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | |
6924 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; | |
4150c572 JB |
6925 | } |
6926 | ||
bb8c093b | 6927 | static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
6928 | struct ieee80211_if_init_conf *conf) |
6929 | { | |
bb8c093b | 6930 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
6931 | |
6932 | IWL_DEBUG_MAC80211("enter\n"); | |
6933 | ||
6934 | mutex_lock(&priv->mutex); | |
6ef89d0a | 6935 | |
fde3571f MA |
6936 | if (iwl3945_is_ready_rf(priv)) { |
6937 | iwl3945_scan_cancel_timeout(priv, 100); | |
fde3571f MA |
6938 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
6939 | iwl3945_commit_rxon(priv); | |
6940 | } | |
32bfd35d JB |
6941 | if (priv->vif == conf->vif) { |
6942 | priv->vif = NULL; | |
b481de9c ZY |
6943 | memset(priv->bssid, 0, ETH_ALEN); |
6944 | memset(priv->essid, 0, IW_ESSID_MAX_SIZE); | |
6945 | priv->essid_len = 0; | |
6946 | } | |
6947 | mutex_unlock(&priv->mutex); | |
6948 | ||
6949 | IWL_DEBUG_MAC80211("leave\n"); | |
b481de9c ZY |
6950 | } |
6951 | ||
cd56d331 AK |
6952 | #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) |
6953 | ||
6954 | static void iwl3945_bss_info_changed(struct ieee80211_hw *hw, | |
6955 | struct ieee80211_vif *vif, | |
6956 | struct ieee80211_bss_conf *bss_conf, | |
6957 | u32 changes) | |
6958 | { | |
6959 | struct iwl3945_priv *priv = hw->priv; | |
6960 | ||
6961 | IWL_DEBUG_MAC80211("changes = 0x%X\n", changes); | |
6962 | ||
6963 | if (changes & BSS_CHANGED_ERP_PREAMBLE) { | |
6964 | IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n", | |
6965 | bss_conf->use_short_preamble); | |
6966 | if (bss_conf->use_short_preamble) | |
6967 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
6968 | else | |
6969 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6970 | } | |
6971 | ||
6972 | if (changes & BSS_CHANGED_ERP_CTS_PROT) { | |
6973 | IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot); | |
6974 | if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ)) | |
6975 | priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK; | |
6976 | else | |
6977 | priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK; | |
6978 | } | |
6979 | ||
6980 | if (changes & BSS_CHANGED_ASSOC) { | |
6981 | IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc); | |
6982 | /* This should never happen as this function should | |
6983 | * never be called from interrupt context. */ | |
6984 | if (WARN_ON_ONCE(in_interrupt())) | |
6985 | return; | |
6986 | if (bss_conf->assoc) { | |
6987 | priv->assoc_id = bss_conf->aid; | |
6988 | priv->beacon_int = bss_conf->beacon_int; | |
6989 | priv->timestamp0 = bss_conf->timestamp & 0xFFFFFFFF; | |
6990 | priv->timestamp1 = (bss_conf->timestamp >> 32) & | |
6991 | 0xFFFFFFFF; | |
6992 | priv->assoc_capability = bss_conf->assoc_capability; | |
6993 | priv->next_scan_jiffies = jiffies + | |
6994 | IWL_DELAY_NEXT_SCAN_AFTER_ASSOC; | |
6995 | mutex_lock(&priv->mutex); | |
6996 | iwl3945_post_associate(priv); | |
6997 | mutex_unlock(&priv->mutex); | |
6998 | } else { | |
6999 | priv->assoc_id = 0; | |
7000 | IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc); | |
7001 | } | |
7002 | } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) { | |
7003 | IWL_DEBUG_MAC80211("Associated Changes %d\n", changes); | |
7004 | iwl3945_send_rxon_assoc(priv); | |
7005 | } | |
7006 | ||
7007 | } | |
7008 | ||
bb8c093b | 7009 | static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len) |
b481de9c ZY |
7010 | { |
7011 | int rc = 0; | |
7012 | unsigned long flags; | |
bb8c093b | 7013 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7014 | |
7015 | IWL_DEBUG_MAC80211("enter\n"); | |
7016 | ||
15e869d8 | 7017 | mutex_lock(&priv->mutex); |
b481de9c ZY |
7018 | spin_lock_irqsave(&priv->lock, flags); |
7019 | ||
bb8c093b | 7020 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
7021 | rc = -EIO; |
7022 | IWL_DEBUG_MAC80211("leave - not ready or exit pending\n"); | |
7023 | goto out_unlock; | |
7024 | } | |
7025 | ||
05c914fe | 7026 | if (priv->iw_mode == NL80211_IFTYPE_AP) { /* APs don't scan */ |
b481de9c ZY |
7027 | rc = -EIO; |
7028 | IWL_ERROR("ERROR: APs don't scan\n"); | |
7029 | goto out_unlock; | |
7030 | } | |
7031 | ||
7878a5a4 MA |
7032 | /* we don't schedule scan within next_scan_jiffies period */ |
7033 | if (priv->next_scan_jiffies && | |
7034 | time_after(priv->next_scan_jiffies, jiffies)) { | |
7035 | rc = -EAGAIN; | |
7036 | goto out_unlock; | |
7037 | } | |
15dbf1b7 BM |
7038 | /* if we just finished scan ask for delay for a broadcast scan */ |
7039 | if ((len == 0) && priv->last_scan_jiffies && | |
7040 | time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN, | |
7041 | jiffies)) { | |
b481de9c ZY |
7042 | rc = -EAGAIN; |
7043 | goto out_unlock; | |
7044 | } | |
7045 | if (len) { | |
7878a5a4 | 7046 | IWL_DEBUG_SCAN("direct scan for %s [%d]\n ", |
bb8c093b | 7047 | iwl3945_escape_essid(ssid, len), (int)len); |
b481de9c ZY |
7048 | |
7049 | priv->one_direct_scan = 1; | |
7050 | priv->direct_ssid_len = (u8) | |
7051 | min((u8) len, (u8) IW_ESSID_MAX_SIZE); | |
7052 | memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len); | |
6ef89d0a MA |
7053 | } else |
7054 | priv->one_direct_scan = 0; | |
b481de9c | 7055 | |
bb8c093b | 7056 | rc = iwl3945_scan_initiate(priv); |
b481de9c ZY |
7057 | |
7058 | IWL_DEBUG_MAC80211("leave\n"); | |
7059 | ||
7060 | out_unlock: | |
7061 | spin_unlock_irqrestore(&priv->lock, flags); | |
15e869d8 | 7062 | mutex_unlock(&priv->mutex); |
b481de9c ZY |
7063 | |
7064 | return rc; | |
7065 | } | |
7066 | ||
bb8c093b | 7067 | static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
b481de9c ZY |
7068 | const u8 *local_addr, const u8 *addr, |
7069 | struct ieee80211_key_conf *key) | |
7070 | { | |
bb8c093b | 7071 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7072 | int rc = 0; |
7073 | u8 sta_id; | |
7074 | ||
7075 | IWL_DEBUG_MAC80211("enter\n"); | |
7076 | ||
bb8c093b | 7077 | if (!iwl3945_param_hwcrypto) { |
b481de9c ZY |
7078 | IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n"); |
7079 | return -EOPNOTSUPP; | |
7080 | } | |
7081 | ||
7082 | if (is_zero_ether_addr(addr)) | |
7083 | /* only support pairwise keys */ | |
7084 | return -EOPNOTSUPP; | |
7085 | ||
bb8c093b | 7086 | sta_id = iwl3945_hw_find_station(priv, addr); |
b481de9c | 7087 | if (sta_id == IWL_INVALID_STATION) { |
0795af57 JP |
7088 | DECLARE_MAC_BUF(mac); |
7089 | ||
7090 | IWL_DEBUG_MAC80211("leave - %s not in station map.\n", | |
7091 | print_mac(mac, addr)); | |
b481de9c ZY |
7092 | return -EINVAL; |
7093 | } | |
7094 | ||
7095 | mutex_lock(&priv->mutex); | |
7096 | ||
bb8c093b | 7097 | iwl3945_scan_cancel_timeout(priv, 100); |
15e869d8 | 7098 | |
b481de9c ZY |
7099 | switch (cmd) { |
7100 | case SET_KEY: | |
bb8c093b | 7101 | rc = iwl3945_update_sta_key_info(priv, key, sta_id); |
b481de9c | 7102 | if (!rc) { |
bb8c093b CH |
7103 | iwl3945_set_rxon_hwcrypto(priv, 1); |
7104 | iwl3945_commit_rxon(priv); | |
b481de9c ZY |
7105 | key->hw_key_idx = sta_id; |
7106 | IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n"); | |
7107 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
7108 | } | |
7109 | break; | |
7110 | case DISABLE_KEY: | |
bb8c093b | 7111 | rc = iwl3945_clear_sta_key_info(priv, sta_id); |
b481de9c | 7112 | if (!rc) { |
bb8c093b CH |
7113 | iwl3945_set_rxon_hwcrypto(priv, 0); |
7114 | iwl3945_commit_rxon(priv); | |
b481de9c ZY |
7115 | IWL_DEBUG_MAC80211("disable hwcrypto key\n"); |
7116 | } | |
7117 | break; | |
7118 | default: | |
7119 | rc = -EINVAL; | |
7120 | } | |
7121 | ||
7122 | IWL_DEBUG_MAC80211("leave\n"); | |
7123 | mutex_unlock(&priv->mutex); | |
7124 | ||
7125 | return rc; | |
7126 | } | |
7127 | ||
e100bb64 | 7128 | static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue, |
b481de9c ZY |
7129 | const struct ieee80211_tx_queue_params *params) |
7130 | { | |
bb8c093b | 7131 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7132 | unsigned long flags; |
7133 | int q; | |
b481de9c ZY |
7134 | |
7135 | IWL_DEBUG_MAC80211("enter\n"); | |
7136 | ||
bb8c093b | 7137 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
7138 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7139 | return -EIO; | |
7140 | } | |
7141 | ||
7142 | if (queue >= AC_NUM) { | |
7143 | IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue); | |
7144 | return 0; | |
7145 | } | |
7146 | ||
b481de9c ZY |
7147 | if (!priv->qos_data.qos_enable) { |
7148 | priv->qos_data.qos_active = 0; | |
7149 | IWL_DEBUG_MAC80211("leave - qos not enabled\n"); | |
7150 | return 0; | |
7151 | } | |
7152 | q = AC_NUM - 1 - queue; | |
7153 | ||
7154 | spin_lock_irqsave(&priv->lock, flags); | |
7155 | ||
7156 | priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min); | |
7157 | priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max); | |
7158 | priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; | |
7159 | priv->qos_data.def_qos_parm.ac[q].edca_txop = | |
3330d7be | 7160 | cpu_to_le16((params->txop * 32)); |
b481de9c ZY |
7161 | |
7162 | priv->qos_data.def_qos_parm.ac[q].reserved1 = 0; | |
7163 | priv->qos_data.qos_active = 1; | |
7164 | ||
7165 | spin_unlock_irqrestore(&priv->lock, flags); | |
7166 | ||
7167 | mutex_lock(&priv->mutex); | |
05c914fe | 7168 | if (priv->iw_mode == NL80211_IFTYPE_AP) |
bb8c093b CH |
7169 | iwl3945_activate_qos(priv, 1); |
7170 | else if (priv->assoc_id && iwl3945_is_associated(priv)) | |
7171 | iwl3945_activate_qos(priv, 0); | |
b481de9c ZY |
7172 | |
7173 | mutex_unlock(&priv->mutex); | |
7174 | ||
b481de9c ZY |
7175 | IWL_DEBUG_MAC80211("leave\n"); |
7176 | return 0; | |
7177 | } | |
7178 | ||
bb8c093b | 7179 | static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
7180 | struct ieee80211_tx_queue_stats *stats) |
7181 | { | |
bb8c093b | 7182 | struct iwl3945_priv *priv = hw->priv; |
b481de9c | 7183 | int i, avail; |
bb8c093b CH |
7184 | struct iwl3945_tx_queue *txq; |
7185 | struct iwl3945_queue *q; | |
b481de9c ZY |
7186 | unsigned long flags; |
7187 | ||
7188 | IWL_DEBUG_MAC80211("enter\n"); | |
7189 | ||
bb8c093b | 7190 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
7191 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7192 | return -EIO; | |
7193 | } | |
7194 | ||
7195 | spin_lock_irqsave(&priv->lock, flags); | |
7196 | ||
7197 | for (i = 0; i < AC_NUM; i++) { | |
7198 | txq = &priv->txq[i]; | |
7199 | q = &txq->q; | |
bb8c093b | 7200 | avail = iwl3945_queue_space(q); |
b481de9c | 7201 | |
57ffc589 JB |
7202 | stats[i].len = q->n_window - avail; |
7203 | stats[i].limit = q->n_window - q->high_mark; | |
7204 | stats[i].count = q->n_window; | |
b481de9c ZY |
7205 | |
7206 | } | |
7207 | spin_unlock_irqrestore(&priv->lock, flags); | |
7208 | ||
7209 | IWL_DEBUG_MAC80211("leave\n"); | |
7210 | ||
7211 | return 0; | |
7212 | } | |
7213 | ||
bb8c093b | 7214 | static int iwl3945_mac_get_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
7215 | struct ieee80211_low_level_stats *stats) |
7216 | { | |
7217 | IWL_DEBUG_MAC80211("enter\n"); | |
7218 | IWL_DEBUG_MAC80211("leave\n"); | |
7219 | ||
7220 | return 0; | |
7221 | } | |
7222 | ||
bb8c093b | 7223 | static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw) |
b481de9c ZY |
7224 | { |
7225 | IWL_DEBUG_MAC80211("enter\n"); | |
7226 | IWL_DEBUG_MAC80211("leave\n"); | |
7227 | ||
7228 | return 0; | |
7229 | } | |
7230 | ||
bb8c093b | 7231 | static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw) |
b481de9c | 7232 | { |
bb8c093b | 7233 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7234 | unsigned long flags; |
7235 | ||
7236 | mutex_lock(&priv->mutex); | |
7237 | IWL_DEBUG_MAC80211("enter\n"); | |
7238 | ||
bb8c093b | 7239 | iwl3945_reset_qos(priv); |
292ae174 | 7240 | |
b481de9c ZY |
7241 | spin_lock_irqsave(&priv->lock, flags); |
7242 | priv->assoc_id = 0; | |
7243 | priv->assoc_capability = 0; | |
7244 | priv->call_post_assoc_from_beacon = 0; | |
7245 | ||
7246 | /* new association get rid of ibss beacon skb */ | |
7247 | if (priv->ibss_beacon) | |
7248 | dev_kfree_skb(priv->ibss_beacon); | |
7249 | ||
7250 | priv->ibss_beacon = NULL; | |
7251 | ||
7252 | priv->beacon_int = priv->hw->conf.beacon_int; | |
7253 | priv->timestamp1 = 0; | |
7254 | priv->timestamp0 = 0; | |
05c914fe | 7255 | if ((priv->iw_mode == NL80211_IFTYPE_STATION)) |
b481de9c ZY |
7256 | priv->beacon_int = 0; |
7257 | ||
7258 | spin_unlock_irqrestore(&priv->lock, flags); | |
7259 | ||
fde3571f MA |
7260 | if (!iwl3945_is_ready_rf(priv)) { |
7261 | IWL_DEBUG_MAC80211("leave - not ready\n"); | |
7262 | mutex_unlock(&priv->mutex); | |
7263 | return; | |
7264 | } | |
7265 | ||
15e869d8 MA |
7266 | /* we are restarting association process |
7267 | * clear RXON_FILTER_ASSOC_MSK bit | |
7268 | */ | |
05c914fe | 7269 | if (priv->iw_mode != NL80211_IFTYPE_AP) { |
bb8c093b | 7270 | iwl3945_scan_cancel_timeout(priv, 100); |
15e869d8 | 7271 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 7272 | iwl3945_commit_rxon(priv); |
15e869d8 MA |
7273 | } |
7274 | ||
b481de9c | 7275 | /* Per mac80211.h: This is only used in IBSS mode... */ |
05c914fe | 7276 | if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { |
15e869d8 | 7277 | |
b481de9c ZY |
7278 | IWL_DEBUG_MAC80211("leave - not in IBSS\n"); |
7279 | mutex_unlock(&priv->mutex); | |
7280 | return; | |
b481de9c ZY |
7281 | } |
7282 | ||
bb8c093b | 7283 | iwl3945_set_rate(priv); |
b481de9c ZY |
7284 | |
7285 | mutex_unlock(&priv->mutex); | |
7286 | ||
7287 | IWL_DEBUG_MAC80211("leave\n"); | |
7288 | ||
7289 | } | |
7290 | ||
e039fa4a | 7291 | static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 7292 | { |
bb8c093b | 7293 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7294 | unsigned long flags; |
7295 | ||
7296 | mutex_lock(&priv->mutex); | |
7297 | IWL_DEBUG_MAC80211("enter\n"); | |
7298 | ||
bb8c093b | 7299 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
7300 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7301 | mutex_unlock(&priv->mutex); | |
7302 | return -EIO; | |
7303 | } | |
7304 | ||
05c914fe | 7305 | if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { |
b481de9c ZY |
7306 | IWL_DEBUG_MAC80211("leave - not IBSS\n"); |
7307 | mutex_unlock(&priv->mutex); | |
7308 | return -EIO; | |
7309 | } | |
7310 | ||
7311 | spin_lock_irqsave(&priv->lock, flags); | |
7312 | ||
7313 | if (priv->ibss_beacon) | |
7314 | dev_kfree_skb(priv->ibss_beacon); | |
7315 | ||
7316 | priv->ibss_beacon = skb; | |
7317 | ||
7318 | priv->assoc_id = 0; | |
7319 | ||
7320 | IWL_DEBUG_MAC80211("leave\n"); | |
7321 | spin_unlock_irqrestore(&priv->lock, flags); | |
7322 | ||
bb8c093b | 7323 | iwl3945_reset_qos(priv); |
b481de9c | 7324 | |
dc4b1e7d | 7325 | iwl3945_post_associate(priv); |
b481de9c ZY |
7326 | |
7327 | mutex_unlock(&priv->mutex); | |
7328 | ||
7329 | return 0; | |
7330 | } | |
7331 | ||
7332 | /***************************************************************************** | |
7333 | * | |
7334 | * sysfs attributes | |
7335 | * | |
7336 | *****************************************************************************/ | |
7337 | ||
c8b0e6e1 | 7338 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
7339 | |
7340 | /* | |
7341 | * The following adds a new attribute to the sysfs representation | |
7342 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
7343 | * used for controlling the debug level. | |
7344 | * | |
7345 | * See the level definitions in iwl for details. | |
7346 | */ | |
7347 | ||
7348 | static ssize_t show_debug_level(struct device_driver *d, char *buf) | |
7349 | { | |
bb8c093b | 7350 | return sprintf(buf, "0x%08X\n", iwl3945_debug_level); |
b481de9c ZY |
7351 | } |
7352 | static ssize_t store_debug_level(struct device_driver *d, | |
7353 | const char *buf, size_t count) | |
7354 | { | |
7355 | char *p = (char *)buf; | |
7356 | u32 val; | |
7357 | ||
7358 | val = simple_strtoul(p, &p, 0); | |
7359 | if (p == buf) | |
7360 | printk(KERN_INFO DRV_NAME | |
7361 | ": %s is not in hex or decimal form.\n", buf); | |
7362 | else | |
bb8c093b | 7363 | iwl3945_debug_level = val; |
b481de9c ZY |
7364 | |
7365 | return strnlen(buf, count); | |
7366 | } | |
7367 | ||
7368 | static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO, | |
7369 | show_debug_level, store_debug_level); | |
7370 | ||
c8b0e6e1 | 7371 | #endif /* CONFIG_IWL3945_DEBUG */ |
b481de9c | 7372 | |
b481de9c ZY |
7373 | static ssize_t show_temperature(struct device *d, |
7374 | struct device_attribute *attr, char *buf) | |
7375 | { | |
bb8c093b | 7376 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c | 7377 | |
bb8c093b | 7378 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
7379 | return -EAGAIN; |
7380 | ||
bb8c093b | 7381 | return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv)); |
b481de9c ZY |
7382 | } |
7383 | ||
7384 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
7385 | ||
b481de9c ZY |
7386 | static ssize_t show_tx_power(struct device *d, |
7387 | struct device_attribute *attr, char *buf) | |
7388 | { | |
bb8c093b | 7389 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7390 | return sprintf(buf, "%d\n", priv->user_txpower_limit); |
7391 | } | |
7392 | ||
7393 | static ssize_t store_tx_power(struct device *d, | |
7394 | struct device_attribute *attr, | |
7395 | const char *buf, size_t count) | |
7396 | { | |
bb8c093b | 7397 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7398 | char *p = (char *)buf; |
7399 | u32 val; | |
7400 | ||
7401 | val = simple_strtoul(p, &p, 10); | |
7402 | if (p == buf) | |
7403 | printk(KERN_INFO DRV_NAME | |
7404 | ": %s is not in decimal form.\n", buf); | |
7405 | else | |
bb8c093b | 7406 | iwl3945_hw_reg_set_txpower(priv, val); |
b481de9c ZY |
7407 | |
7408 | return count; | |
7409 | } | |
7410 | ||
7411 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
7412 | ||
7413 | static ssize_t show_flags(struct device *d, | |
7414 | struct device_attribute *attr, char *buf) | |
7415 | { | |
bb8c093b | 7416 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7417 | |
7418 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); | |
7419 | } | |
7420 | ||
7421 | static ssize_t store_flags(struct device *d, | |
7422 | struct device_attribute *attr, | |
7423 | const char *buf, size_t count) | |
7424 | { | |
bb8c093b | 7425 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7426 | u32 flags = simple_strtoul(buf, NULL, 0); |
7427 | ||
7428 | mutex_lock(&priv->mutex); | |
7429 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { | |
7430 | /* Cancel any currently running scans... */ | |
bb8c093b | 7431 | if (iwl3945_scan_cancel_timeout(priv, 100)) |
b481de9c ZY |
7432 | IWL_WARNING("Could not cancel scan.\n"); |
7433 | else { | |
7434 | IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n", | |
7435 | flags); | |
7436 | priv->staging_rxon.flags = cpu_to_le32(flags); | |
bb8c093b | 7437 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
7438 | } |
7439 | } | |
7440 | mutex_unlock(&priv->mutex); | |
7441 | ||
7442 | return count; | |
7443 | } | |
7444 | ||
7445 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
7446 | ||
7447 | static ssize_t show_filter_flags(struct device *d, | |
7448 | struct device_attribute *attr, char *buf) | |
7449 | { | |
bb8c093b | 7450 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7451 | |
7452 | return sprintf(buf, "0x%04X\n", | |
7453 | le32_to_cpu(priv->active_rxon.filter_flags)); | |
7454 | } | |
7455 | ||
7456 | static ssize_t store_filter_flags(struct device *d, | |
7457 | struct device_attribute *attr, | |
7458 | const char *buf, size_t count) | |
7459 | { | |
bb8c093b | 7460 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7461 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
7462 | ||
7463 | mutex_lock(&priv->mutex); | |
7464 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { | |
7465 | /* Cancel any currently running scans... */ | |
bb8c093b | 7466 | if (iwl3945_scan_cancel_timeout(priv, 100)) |
b481de9c ZY |
7467 | IWL_WARNING("Could not cancel scan.\n"); |
7468 | else { | |
7469 | IWL_DEBUG_INFO("Committing rxon.filter_flags = " | |
7470 | "0x%04X\n", filter_flags); | |
7471 | priv->staging_rxon.filter_flags = | |
7472 | cpu_to_le32(filter_flags); | |
bb8c093b | 7473 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
7474 | } |
7475 | } | |
7476 | mutex_unlock(&priv->mutex); | |
7477 | ||
7478 | return count; | |
7479 | } | |
7480 | ||
7481 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
7482 | store_filter_flags); | |
7483 | ||
c8b0e6e1 | 7484 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
7485 | |
7486 | static ssize_t show_measurement(struct device *d, | |
7487 | struct device_attribute *attr, char *buf) | |
7488 | { | |
bb8c093b CH |
7489 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
7490 | struct iwl3945_spectrum_notification measure_report; | |
b481de9c | 7491 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
3ac7f146 | 7492 | u8 *data = (u8 *)&measure_report; |
b481de9c ZY |
7493 | unsigned long flags; |
7494 | ||
7495 | spin_lock_irqsave(&priv->lock, flags); | |
7496 | if (!(priv->measurement_status & MEASUREMENT_READY)) { | |
7497 | spin_unlock_irqrestore(&priv->lock, flags); | |
7498 | return 0; | |
7499 | } | |
7500 | memcpy(&measure_report, &priv->measure_report, size); | |
7501 | priv->measurement_status = 0; | |
7502 | spin_unlock_irqrestore(&priv->lock, flags); | |
7503 | ||
7504 | while (size && (PAGE_SIZE - len)) { | |
7505 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7506 | PAGE_SIZE - len, 1); | |
7507 | len = strlen(buf); | |
7508 | if (PAGE_SIZE - len) | |
7509 | buf[len++] = '\n'; | |
7510 | ||
7511 | ofs += 16; | |
7512 | size -= min(size, 16U); | |
7513 | } | |
7514 | ||
7515 | return len; | |
7516 | } | |
7517 | ||
7518 | static ssize_t store_measurement(struct device *d, | |
7519 | struct device_attribute *attr, | |
7520 | const char *buf, size_t count) | |
7521 | { | |
bb8c093b | 7522 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7523 | struct ieee80211_measurement_params params = { |
7524 | .channel = le16_to_cpu(priv->active_rxon.channel), | |
7525 | .start_time = cpu_to_le64(priv->last_tsf), | |
7526 | .duration = cpu_to_le16(1), | |
7527 | }; | |
7528 | u8 type = IWL_MEASURE_BASIC; | |
7529 | u8 buffer[32]; | |
7530 | u8 channel; | |
7531 | ||
7532 | if (count) { | |
7533 | char *p = buffer; | |
7534 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
7535 | channel = simple_strtoul(p, NULL, 0); | |
7536 | if (channel) | |
7537 | params.channel = channel; | |
7538 | ||
7539 | p = buffer; | |
7540 | while (*p && *p != ' ') | |
7541 | p++; | |
7542 | if (*p) | |
7543 | type = simple_strtoul(p + 1, NULL, 0); | |
7544 | } | |
7545 | ||
7546 | IWL_DEBUG_INFO("Invoking measurement of type %d on " | |
7547 | "channel %d (for '%s')\n", type, params.channel, buf); | |
bb8c093b | 7548 | iwl3945_get_measurement(priv, ¶ms, type); |
b481de9c ZY |
7549 | |
7550 | return count; | |
7551 | } | |
7552 | ||
7553 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
7554 | show_measurement, store_measurement); | |
c8b0e6e1 | 7555 | #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */ |
b481de9c | 7556 | |
b481de9c ZY |
7557 | static ssize_t store_retry_rate(struct device *d, |
7558 | struct device_attribute *attr, | |
7559 | const char *buf, size_t count) | |
7560 | { | |
bb8c093b | 7561 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7562 | |
7563 | priv->retry_rate = simple_strtoul(buf, NULL, 0); | |
7564 | if (priv->retry_rate <= 0) | |
7565 | priv->retry_rate = 1; | |
7566 | ||
7567 | return count; | |
7568 | } | |
7569 | ||
7570 | static ssize_t show_retry_rate(struct device *d, | |
7571 | struct device_attribute *attr, char *buf) | |
7572 | { | |
bb8c093b | 7573 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7574 | return sprintf(buf, "%d", priv->retry_rate); |
7575 | } | |
7576 | ||
7577 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate, | |
7578 | store_retry_rate); | |
7579 | ||
7580 | static ssize_t store_power_level(struct device *d, | |
7581 | struct device_attribute *attr, | |
7582 | const char *buf, size_t count) | |
7583 | { | |
bb8c093b | 7584 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7585 | int rc; |
7586 | int mode; | |
7587 | ||
7588 | mode = simple_strtoul(buf, NULL, 0); | |
7589 | mutex_lock(&priv->mutex); | |
7590 | ||
bb8c093b | 7591 | if (!iwl3945_is_ready(priv)) { |
b481de9c ZY |
7592 | rc = -EAGAIN; |
7593 | goto out; | |
7594 | } | |
7595 | ||
7596 | if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC)) | |
7597 | mode = IWL_POWER_AC; | |
7598 | else | |
7599 | mode |= IWL_POWER_ENABLED; | |
7600 | ||
7601 | if (mode != priv->power_mode) { | |
bb8c093b | 7602 | rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode)); |
b481de9c ZY |
7603 | if (rc) { |
7604 | IWL_DEBUG_MAC80211("failed setting power mode.\n"); | |
7605 | goto out; | |
7606 | } | |
7607 | priv->power_mode = mode; | |
7608 | } | |
7609 | ||
7610 | rc = count; | |
7611 | ||
7612 | out: | |
7613 | mutex_unlock(&priv->mutex); | |
7614 | return rc; | |
7615 | } | |
7616 | ||
7617 | #define MAX_WX_STRING 80 | |
7618 | ||
7619 | /* Values are in microsecond */ | |
7620 | static const s32 timeout_duration[] = { | |
7621 | 350000, | |
7622 | 250000, | |
7623 | 75000, | |
7624 | 37000, | |
7625 | 25000, | |
7626 | }; | |
7627 | static const s32 period_duration[] = { | |
7628 | 400000, | |
7629 | 700000, | |
7630 | 1000000, | |
7631 | 1000000, | |
7632 | 1000000 | |
7633 | }; | |
7634 | ||
7635 | static ssize_t show_power_level(struct device *d, | |
7636 | struct device_attribute *attr, char *buf) | |
7637 | { | |
bb8c093b | 7638 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7639 | int level = IWL_POWER_LEVEL(priv->power_mode); |
7640 | char *p = buf; | |
7641 | ||
7642 | p += sprintf(p, "%d ", level); | |
7643 | switch (level) { | |
7644 | case IWL_POWER_MODE_CAM: | |
7645 | case IWL_POWER_AC: | |
7646 | p += sprintf(p, "(AC)"); | |
7647 | break; | |
7648 | case IWL_POWER_BATTERY: | |
7649 | p += sprintf(p, "(BATTERY)"); | |
7650 | break; | |
7651 | default: | |
7652 | p += sprintf(p, | |
7653 | "(Timeout %dms, Period %dms)", | |
7654 | timeout_duration[level - 1] / 1000, | |
7655 | period_duration[level - 1] / 1000); | |
7656 | } | |
7657 | ||
7658 | if (!(priv->power_mode & IWL_POWER_ENABLED)) | |
7659 | p += sprintf(p, " OFF\n"); | |
7660 | else | |
7661 | p += sprintf(p, " \n"); | |
7662 | ||
3ac7f146 | 7663 | return p - buf + 1; |
b481de9c ZY |
7664 | |
7665 | } | |
7666 | ||
7667 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, | |
7668 | store_power_level); | |
7669 | ||
7670 | static ssize_t show_channels(struct device *d, | |
7671 | struct device_attribute *attr, char *buf) | |
7672 | { | |
8318d78a JB |
7673 | /* all this shit doesn't belong into sysfs anyway */ |
7674 | return 0; | |
b481de9c ZY |
7675 | } |
7676 | ||
7677 | static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); | |
7678 | ||
7679 | static ssize_t show_statistics(struct device *d, | |
7680 | struct device_attribute *attr, char *buf) | |
7681 | { | |
bb8c093b CH |
7682 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
7683 | u32 size = sizeof(struct iwl3945_notif_statistics); | |
b481de9c | 7684 | u32 len = 0, ofs = 0; |
3ac7f146 | 7685 | u8 *data = (u8 *)&priv->statistics; |
b481de9c ZY |
7686 | int rc = 0; |
7687 | ||
bb8c093b | 7688 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
7689 | return -EAGAIN; |
7690 | ||
7691 | mutex_lock(&priv->mutex); | |
bb8c093b | 7692 | rc = iwl3945_send_statistics_request(priv); |
b481de9c ZY |
7693 | mutex_unlock(&priv->mutex); |
7694 | ||
7695 | if (rc) { | |
7696 | len = sprintf(buf, | |
7697 | "Error sending statistics request: 0x%08X\n", rc); | |
7698 | return len; | |
7699 | } | |
7700 | ||
7701 | while (size && (PAGE_SIZE - len)) { | |
7702 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7703 | PAGE_SIZE - len, 1); | |
7704 | len = strlen(buf); | |
7705 | if (PAGE_SIZE - len) | |
7706 | buf[len++] = '\n'; | |
7707 | ||
7708 | ofs += 16; | |
7709 | size -= min(size, 16U); | |
7710 | } | |
7711 | ||
7712 | return len; | |
7713 | } | |
7714 | ||
7715 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
7716 | ||
7717 | static ssize_t show_antenna(struct device *d, | |
7718 | struct device_attribute *attr, char *buf) | |
7719 | { | |
bb8c093b | 7720 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c | 7721 | |
bb8c093b | 7722 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
7723 | return -EAGAIN; |
7724 | ||
7725 | return sprintf(buf, "%d\n", priv->antenna); | |
7726 | } | |
7727 | ||
7728 | static ssize_t store_antenna(struct device *d, | |
7729 | struct device_attribute *attr, | |
7730 | const char *buf, size_t count) | |
7731 | { | |
7732 | int ant; | |
bb8c093b | 7733 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7734 | |
7735 | if (count == 0) | |
7736 | return 0; | |
7737 | ||
7738 | if (sscanf(buf, "%1i", &ant) != 1) { | |
7739 | IWL_DEBUG_INFO("not in hex or decimal form.\n"); | |
7740 | return count; | |
7741 | } | |
7742 | ||
7743 | if ((ant >= 0) && (ant <= 2)) { | |
7744 | IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant); | |
bb8c093b | 7745 | priv->antenna = (enum iwl3945_antenna)ant; |
b481de9c ZY |
7746 | } else |
7747 | IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant); | |
7748 | ||
7749 | ||
7750 | return count; | |
7751 | } | |
7752 | ||
7753 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna); | |
7754 | ||
7755 | static ssize_t show_status(struct device *d, | |
7756 | struct device_attribute *attr, char *buf) | |
7757 | { | |
bb8c093b CH |
7758 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
7759 | if (!iwl3945_is_alive(priv)) | |
b481de9c ZY |
7760 | return -EAGAIN; |
7761 | return sprintf(buf, "0x%08x\n", (int)priv->status); | |
7762 | } | |
7763 | ||
7764 | static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); | |
7765 | ||
7766 | static ssize_t dump_error_log(struct device *d, | |
7767 | struct device_attribute *attr, | |
7768 | const char *buf, size_t count) | |
7769 | { | |
7770 | char *p = (char *)buf; | |
7771 | ||
7772 | if (p[0] == '1') | |
bb8c093b | 7773 | iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data); |
b481de9c ZY |
7774 | |
7775 | return strnlen(buf, count); | |
7776 | } | |
7777 | ||
7778 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | |
7779 | ||
7780 | static ssize_t dump_event_log(struct device *d, | |
7781 | struct device_attribute *attr, | |
7782 | const char *buf, size_t count) | |
7783 | { | |
7784 | char *p = (char *)buf; | |
7785 | ||
7786 | if (p[0] == '1') | |
bb8c093b | 7787 | iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data); |
b481de9c ZY |
7788 | |
7789 | return strnlen(buf, count); | |
7790 | } | |
7791 | ||
7792 | static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log); | |
7793 | ||
7794 | /***************************************************************************** | |
7795 | * | |
7796 | * driver setup and teardown | |
7797 | * | |
7798 | *****************************************************************************/ | |
7799 | ||
bb8c093b | 7800 | static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv) |
b481de9c ZY |
7801 | { |
7802 | priv->workqueue = create_workqueue(DRV_NAME); | |
7803 | ||
7804 | init_waitqueue_head(&priv->wait_command_queue); | |
7805 | ||
bb8c093b CH |
7806 | INIT_WORK(&priv->up, iwl3945_bg_up); |
7807 | INIT_WORK(&priv->restart, iwl3945_bg_restart); | |
7808 | INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish); | |
7809 | INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed); | |
7810 | INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan); | |
7811 | INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan); | |
7812 | INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill); | |
7813 | INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update); | |
5ec03976 | 7814 | INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor); |
bb8c093b CH |
7815 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start); |
7816 | INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start); | |
7817 | INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check); | |
7818 | ||
7819 | iwl3945_hw_setup_deferred_work(priv); | |
b481de9c ZY |
7820 | |
7821 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
bb8c093b | 7822 | iwl3945_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
7823 | } |
7824 | ||
bb8c093b | 7825 | static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv) |
b481de9c | 7826 | { |
bb8c093b | 7827 | iwl3945_hw_cancel_deferred_work(priv); |
b481de9c | 7828 | |
e47eb6ad | 7829 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
7830 | cancel_delayed_work(&priv->scan_check); |
7831 | cancel_delayed_work(&priv->alive_start); | |
b481de9c ZY |
7832 | cancel_work_sync(&priv->beacon_update); |
7833 | } | |
7834 | ||
bb8c093b | 7835 | static struct attribute *iwl3945_sysfs_entries[] = { |
b481de9c ZY |
7836 | &dev_attr_antenna.attr, |
7837 | &dev_attr_channels.attr, | |
7838 | &dev_attr_dump_errors.attr, | |
7839 | &dev_attr_dump_events.attr, | |
7840 | &dev_attr_flags.attr, | |
7841 | &dev_attr_filter_flags.attr, | |
c8b0e6e1 | 7842 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
7843 | &dev_attr_measurement.attr, |
7844 | #endif | |
7845 | &dev_attr_power_level.attr, | |
b481de9c | 7846 | &dev_attr_retry_rate.attr, |
b481de9c ZY |
7847 | &dev_attr_statistics.attr, |
7848 | &dev_attr_status.attr, | |
7849 | &dev_attr_temperature.attr, | |
b481de9c ZY |
7850 | &dev_attr_tx_power.attr, |
7851 | ||
7852 | NULL | |
7853 | }; | |
7854 | ||
bb8c093b | 7855 | static struct attribute_group iwl3945_attribute_group = { |
b481de9c | 7856 | .name = NULL, /* put in device directory */ |
bb8c093b | 7857 | .attrs = iwl3945_sysfs_entries, |
b481de9c ZY |
7858 | }; |
7859 | ||
bb8c093b CH |
7860 | static struct ieee80211_ops iwl3945_hw_ops = { |
7861 | .tx = iwl3945_mac_tx, | |
7862 | .start = iwl3945_mac_start, | |
7863 | .stop = iwl3945_mac_stop, | |
7864 | .add_interface = iwl3945_mac_add_interface, | |
7865 | .remove_interface = iwl3945_mac_remove_interface, | |
7866 | .config = iwl3945_mac_config, | |
7867 | .config_interface = iwl3945_mac_config_interface, | |
7868 | .configure_filter = iwl3945_configure_filter, | |
7869 | .set_key = iwl3945_mac_set_key, | |
7870 | .get_stats = iwl3945_mac_get_stats, | |
7871 | .get_tx_stats = iwl3945_mac_get_tx_stats, | |
7872 | .conf_tx = iwl3945_mac_conf_tx, | |
7873 | .get_tsf = iwl3945_mac_get_tsf, | |
7874 | .reset_tsf = iwl3945_mac_reset_tsf, | |
cd56d331 | 7875 | .bss_info_changed = iwl3945_bss_info_changed, |
bb8c093b | 7876 | .hw_scan = iwl3945_mac_hw_scan |
b481de9c ZY |
7877 | }; |
7878 | ||
bb8c093b | 7879 | static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
7880 | { |
7881 | int err = 0; | |
bb8c093b | 7882 | struct iwl3945_priv *priv; |
b481de9c | 7883 | struct ieee80211_hw *hw; |
82b9a121 | 7884 | struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data); |
0359facc | 7885 | unsigned long flags; |
5a66926a | 7886 | DECLARE_MAC_BUF(mac); |
b481de9c | 7887 | |
6440adb5 CB |
7888 | /* Disabling hardware scan means that mac80211 will perform scans |
7889 | * "the hard way", rather than using device's scan. */ | |
bb8c093b | 7890 | if (iwl3945_param_disable_hw_scan) { |
b481de9c | 7891 | IWL_DEBUG_INFO("Disabling hw_scan\n"); |
bb8c093b | 7892 | iwl3945_hw_ops.hw_scan = NULL; |
b481de9c ZY |
7893 | } |
7894 | ||
dfe7d458 | 7895 | if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) || |
bb8c093b | 7896 | (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) { |
b481de9c | 7897 | IWL_ERROR("invalid queues_num, should be between %d and %d\n", |
dfe7d458 | 7898 | IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES); |
b481de9c ZY |
7899 | err = -EINVAL; |
7900 | goto out; | |
7901 | } | |
7902 | ||
7903 | /* mac80211 allocates memory for this device instance, including | |
7904 | * space for this driver's private structure */ | |
bb8c093b | 7905 | hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops); |
b481de9c ZY |
7906 | if (hw == NULL) { |
7907 | IWL_ERROR("Can not allocate network device\n"); | |
7908 | err = -ENOMEM; | |
7909 | goto out; | |
7910 | } | |
7911 | SET_IEEE80211_DEV(hw, &pdev->dev); | |
7912 | ||
f51359a8 | 7913 | hw->rate_control_algorithm = "iwl-3945-rs"; |
4b7679a5 | 7914 | hw->sta_data_size = sizeof(struct iwl3945_sta_priv); |
f51359a8 | 7915 | |
b481de9c ZY |
7916 | IWL_DEBUG_INFO("*** LOAD DRIVER ***\n"); |
7917 | priv = hw->priv; | |
7918 | priv->hw = hw; | |
7919 | ||
7920 | priv->pci_dev = pdev; | |
82b9a121 | 7921 | priv->cfg = cfg; |
6440adb5 CB |
7922 | |
7923 | /* Select antenna (may be helpful if only one antenna is connected) */ | |
bb8c093b | 7924 | priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna; |
c8b0e6e1 | 7925 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 7926 | iwl3945_debug_level = iwl3945_param_debug; |
b481de9c ZY |
7927 | atomic_set(&priv->restrict_refcnt, 0); |
7928 | #endif | |
7929 | priv->retry_rate = 1; | |
7930 | ||
7931 | priv->ibss_beacon = NULL; | |
7932 | ||
566bfe5a | 7933 | /* Tell mac80211 our characteristics */ |
605a0bd6 | 7934 | hw->flags = IEEE80211_HW_SIGNAL_DBM | |
566bfe5a | 7935 | IEEE80211_HW_NOISE_DBM; |
b481de9c | 7936 | |
f59ac048 LR |
7937 | hw->wiphy->interface_modes = |
7938 | BIT(NL80211_IFTYPE_AP) | | |
7939 | BIT(NL80211_IFTYPE_STATION) | | |
7940 | BIT(NL80211_IFTYPE_ADHOC); | |
7941 | ||
6440adb5 | 7942 | /* 4 EDCA QOS priorities */ |
b481de9c ZY |
7943 | hw->queues = 4; |
7944 | ||
7945 | spin_lock_init(&priv->lock); | |
7946 | spin_lock_init(&priv->power_data.lock); | |
7947 | spin_lock_init(&priv->sta_lock); | |
7948 | spin_lock_init(&priv->hcmd_lock); | |
7949 | ||
b481de9c ZY |
7950 | INIT_LIST_HEAD(&priv->free_frames); |
7951 | ||
7952 | mutex_init(&priv->mutex); | |
7953 | if (pci_enable_device(pdev)) { | |
7954 | err = -ENODEV; | |
7955 | goto out_ieee80211_free_hw; | |
7956 | } | |
7957 | ||
7958 | pci_set_master(pdev); | |
7959 | ||
6440adb5 | 7960 | /* Clear the driver's (not device's) station table */ |
bb8c093b | 7961 | iwl3945_clear_stations_table(priv); |
b481de9c ZY |
7962 | |
7963 | priv->data_retry_limit = -1; | |
7964 | priv->ieee_channels = NULL; | |
7965 | priv->ieee_rates = NULL; | |
8318d78a | 7966 | priv->band = IEEE80211_BAND_2GHZ; |
b481de9c ZY |
7967 | |
7968 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
7969 | if (!err) | |
7970 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
7971 | if (err) { | |
7972 | printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n"); | |
7973 | goto out_pci_disable_device; | |
7974 | } | |
7975 | ||
7976 | pci_set_drvdata(pdev, priv); | |
7977 | err = pci_request_regions(pdev, DRV_NAME); | |
7978 | if (err) | |
7979 | goto out_pci_disable_device; | |
6440adb5 | 7980 | |
b481de9c ZY |
7981 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
7982 | * PCI Tx retries from interfering with C3 CPU state */ | |
7983 | pci_write_config_byte(pdev, 0x41, 0x00); | |
6440adb5 | 7984 | |
b481de9c ZY |
7985 | priv->hw_base = pci_iomap(pdev, 0, 0); |
7986 | if (!priv->hw_base) { | |
7987 | err = -ENODEV; | |
7988 | goto out_pci_release_regions; | |
7989 | } | |
7990 | ||
7991 | IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n", | |
7992 | (unsigned long long) pci_resource_len(pdev, 0)); | |
7993 | IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base); | |
7994 | ||
7995 | /* Initialize module parameter values here */ | |
7996 | ||
6440adb5 | 7997 | /* Disable radio (SW RF KILL) via parameter when loading driver */ |
bb8c093b | 7998 | if (iwl3945_param_disable) { |
b481de9c ZY |
7999 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
8000 | IWL_DEBUG_INFO("Radio disabled.\n"); | |
8001 | } | |
8002 | ||
05c914fe | 8003 | priv->iw_mode = NL80211_IFTYPE_STATION; |
b481de9c | 8004 | |
b481de9c | 8005 | printk(KERN_INFO DRV_NAME |
82b9a121 | 8006 | ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name); |
b481de9c ZY |
8007 | |
8008 | /* Device-specific setup */ | |
bb8c093b | 8009 | if (iwl3945_hw_set_hw_setting(priv)) { |
b481de9c | 8010 | IWL_ERROR("failed to set hw settings\n"); |
b481de9c ZY |
8011 | goto out_iounmap; |
8012 | } | |
8013 | ||
bb8c093b | 8014 | if (iwl3945_param_qos_enable) |
b481de9c ZY |
8015 | priv->qos_data.qos_enable = 1; |
8016 | ||
bb8c093b | 8017 | iwl3945_reset_qos(priv); |
b481de9c ZY |
8018 | |
8019 | priv->qos_data.qos_active = 0; | |
8020 | priv->qos_data.qos_cap.val = 0; | |
b481de9c | 8021 | |
8318d78a | 8022 | iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6); |
bb8c093b CH |
8023 | iwl3945_setup_deferred_work(priv); |
8024 | iwl3945_setup_rx_handlers(priv); | |
b481de9c ZY |
8025 | |
8026 | priv->rates_mask = IWL_RATES_MASK; | |
8027 | /* If power management is turned on, default to AC mode */ | |
8028 | priv->power_mode = IWL_POWER_AC; | |
8029 | priv->user_txpower_limit = IWL_DEFAULT_TX_POWER; | |
8030 | ||
0359facc | 8031 | spin_lock_irqsave(&priv->lock, flags); |
bb8c093b | 8032 | iwl3945_disable_interrupts(priv); |
0359facc | 8033 | spin_unlock_irqrestore(&priv->lock, flags); |
49df2b33 | 8034 | |
bb8c093b | 8035 | err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c ZY |
8036 | if (err) { |
8037 | IWL_ERROR("failed to create sysfs device attributes\n"); | |
b481de9c ZY |
8038 | goto out_release_irq; |
8039 | } | |
8040 | ||
5a66926a ZY |
8041 | /* nic init */ |
8042 | iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
3ac7f146 TW |
8043 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
8044 | ||
8045 | iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
8046 | err = iwl3945_poll_bit(priv, CSR_GP_CNTRL, | |
8047 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
8048 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
8049 | if (err < 0) { | |
8050 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
5a66926a | 8051 | goto out_remove_sysfs; |
3ac7f146 | 8052 | } |
5a66926a ZY |
8053 | /* Read the EEPROM */ |
8054 | err = iwl3945_eeprom_init(priv); | |
b481de9c | 8055 | if (err) { |
5a66926a ZY |
8056 | IWL_ERROR("Unable to init EEPROM\n"); |
8057 | goto out_remove_sysfs; | |
b481de9c | 8058 | } |
5a66926a ZY |
8059 | /* MAC Address location in EEPROM same for 3945/4965 */ |
8060 | get_eeprom_mac(priv, priv->mac_addr); | |
8061 | IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr)); | |
8062 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); | |
b481de9c | 8063 | |
849e0dce RC |
8064 | err = iwl3945_init_channel_map(priv); |
8065 | if (err) { | |
8066 | IWL_ERROR("initializing regulatory failed: %d\n", err); | |
8067 | goto out_remove_sysfs; | |
8068 | } | |
8069 | ||
8070 | err = iwl3945_init_geos(priv); | |
8071 | if (err) { | |
8072 | IWL_ERROR("initializing geos failed: %d\n", err); | |
8073 | goto out_free_channel_map; | |
8074 | } | |
849e0dce | 8075 | |
5a66926a ZY |
8076 | err = ieee80211_register_hw(priv->hw); |
8077 | if (err) { | |
8078 | IWL_ERROR("Failed to register network device (error %d)\n", err); | |
849e0dce | 8079 | goto out_free_geos; |
5a66926a | 8080 | } |
b481de9c | 8081 | |
5a66926a ZY |
8082 | priv->hw->conf.beacon_int = 100; |
8083 | priv->mac80211_registered = 1; | |
8084 | pci_save_state(pdev); | |
8085 | pci_disable_device(pdev); | |
b481de9c | 8086 | |
ebef2008 AK |
8087 | err = iwl3945_rfkill_init(priv); |
8088 | if (err) | |
8089 | IWL_ERROR("Unable to initialize RFKILL system. " | |
8090 | "Ignoring error: %d\n", err); | |
8091 | ||
b481de9c ZY |
8092 | return 0; |
8093 | ||
849e0dce RC |
8094 | out_free_geos: |
8095 | iwl3945_free_geos(priv); | |
8096 | out_free_channel_map: | |
8097 | iwl3945_free_channel_map(priv); | |
5a66926a | 8098 | out_remove_sysfs: |
bb8c093b | 8099 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c ZY |
8100 | |
8101 | out_release_irq: | |
b481de9c ZY |
8102 | destroy_workqueue(priv->workqueue); |
8103 | priv->workqueue = NULL; | |
bb8c093b | 8104 | iwl3945_unset_hw_setting(priv); |
b481de9c ZY |
8105 | |
8106 | out_iounmap: | |
8107 | pci_iounmap(pdev, priv->hw_base); | |
8108 | out_pci_release_regions: | |
8109 | pci_release_regions(pdev); | |
8110 | out_pci_disable_device: | |
8111 | pci_disable_device(pdev); | |
8112 | pci_set_drvdata(pdev, NULL); | |
8113 | out_ieee80211_free_hw: | |
8114 | ieee80211_free_hw(priv->hw); | |
8115 | out: | |
8116 | return err; | |
8117 | } | |
8118 | ||
c83dbf68 | 8119 | static void __devexit iwl3945_pci_remove(struct pci_dev *pdev) |
b481de9c | 8120 | { |
bb8c093b | 8121 | struct iwl3945_priv *priv = pci_get_drvdata(pdev); |
0359facc | 8122 | unsigned long flags; |
b481de9c ZY |
8123 | |
8124 | if (!priv) | |
8125 | return; | |
8126 | ||
8127 | IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n"); | |
8128 | ||
b481de9c | 8129 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
b24d22b1 | 8130 | |
bb8c093b | 8131 | iwl3945_down(priv); |
b481de9c | 8132 | |
0359facc MA |
8133 | /* make sure we flush any pending irq or |
8134 | * tasklet for the driver | |
8135 | */ | |
8136 | spin_lock_irqsave(&priv->lock, flags); | |
8137 | iwl3945_disable_interrupts(priv); | |
8138 | spin_unlock_irqrestore(&priv->lock, flags); | |
8139 | ||
8140 | iwl_synchronize_irq(priv); | |
8141 | ||
bb8c093b | 8142 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 8143 | |
ebef2008 | 8144 | iwl3945_rfkill_unregister(priv); |
bb8c093b | 8145 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
8146 | |
8147 | if (priv->rxq.bd) | |
bb8c093b CH |
8148 | iwl3945_rx_queue_free(priv, &priv->rxq); |
8149 | iwl3945_hw_txq_ctx_free(priv); | |
b481de9c | 8150 | |
bb8c093b CH |
8151 | iwl3945_unset_hw_setting(priv); |
8152 | iwl3945_clear_stations_table(priv); | |
b481de9c | 8153 | |
3ac7f146 | 8154 | if (priv->mac80211_registered) |
b481de9c | 8155 | ieee80211_unregister_hw(priv->hw); |
b481de9c | 8156 | |
6ef89d0a MA |
8157 | /*netif_stop_queue(dev); */ |
8158 | flush_workqueue(priv->workqueue); | |
8159 | ||
bb8c093b | 8160 | /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes |
b481de9c ZY |
8161 | * priv->workqueue... so we can't take down the workqueue |
8162 | * until now... */ | |
8163 | destroy_workqueue(priv->workqueue); | |
8164 | priv->workqueue = NULL; | |
8165 | ||
b481de9c ZY |
8166 | pci_iounmap(pdev, priv->hw_base); |
8167 | pci_release_regions(pdev); | |
8168 | pci_disable_device(pdev); | |
8169 | pci_set_drvdata(pdev, NULL); | |
8170 | ||
849e0dce RC |
8171 | iwl3945_free_channel_map(priv); |
8172 | iwl3945_free_geos(priv); | |
261415f7 | 8173 | kfree(priv->scan); |
b481de9c ZY |
8174 | if (priv->ibss_beacon) |
8175 | dev_kfree_skb(priv->ibss_beacon); | |
8176 | ||
8177 | ieee80211_free_hw(priv->hw); | |
8178 | } | |
8179 | ||
8180 | #ifdef CONFIG_PM | |
8181 | ||
bb8c093b | 8182 | static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
b481de9c | 8183 | { |
bb8c093b | 8184 | struct iwl3945_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 8185 | |
e655b9f0 ZY |
8186 | if (priv->is_open) { |
8187 | set_bit(STATUS_IN_SUSPEND, &priv->status); | |
8188 | iwl3945_mac_stop(priv->hw); | |
8189 | priv->is_open = 1; | |
8190 | } | |
b481de9c | 8191 | |
b481de9c ZY |
8192 | pci_set_power_state(pdev, PCI_D3hot); |
8193 | ||
b481de9c ZY |
8194 | return 0; |
8195 | } | |
8196 | ||
bb8c093b | 8197 | static int iwl3945_pci_resume(struct pci_dev *pdev) |
b481de9c | 8198 | { |
bb8c093b | 8199 | struct iwl3945_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 8200 | |
b481de9c | 8201 | pci_set_power_state(pdev, PCI_D0); |
b481de9c | 8202 | |
e655b9f0 ZY |
8203 | if (priv->is_open) |
8204 | iwl3945_mac_start(priv->hw); | |
b481de9c | 8205 | |
e655b9f0 | 8206 | clear_bit(STATUS_IN_SUSPEND, &priv->status); |
b481de9c ZY |
8207 | return 0; |
8208 | } | |
8209 | ||
8210 | #endif /* CONFIG_PM */ | |
8211 | ||
ebef2008 | 8212 | /*************** RFKILL FUNCTIONS **********/ |
80fcc9e2 | 8213 | #ifdef CONFIG_IWL3945_RFKILL |
ebef2008 AK |
8214 | /* software rf-kill from user */ |
8215 | static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state) | |
8216 | { | |
8217 | struct iwl3945_priv *priv = data; | |
8218 | int err = 0; | |
8219 | ||
80fcc9e2 | 8220 | if (!priv->rfkill) |
ebef2008 AK |
8221 | return 0; |
8222 | ||
8223 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
8224 | return 0; | |
8225 | ||
8226 | IWL_DEBUG_RF_KILL("we recieved soft RFKILL set to state %d\n", state); | |
8227 | mutex_lock(&priv->mutex); | |
8228 | ||
8229 | switch (state) { | |
acdfe9b4 | 8230 | case RFKILL_STATE_UNBLOCKED: |
80fcc9e2 | 8231 | if (iwl3945_is_rfkill_hw(priv)) { |
ebef2008 | 8232 | err = -EBUSY; |
80fcc9e2 AG |
8233 | goto out_unlock; |
8234 | } | |
8235 | iwl3945_radio_kill_sw(priv, 0); | |
ebef2008 | 8236 | break; |
acdfe9b4 | 8237 | case RFKILL_STATE_SOFT_BLOCKED: |
ebef2008 | 8238 | iwl3945_radio_kill_sw(priv, 1); |
ebef2008 | 8239 | break; |
acdfe9b4 ZY |
8240 | default: |
8241 | IWL_WARNING("we recieved unexpected RFKILL state %d\n", state); | |
8242 | break; | |
ebef2008 | 8243 | } |
80fcc9e2 | 8244 | out_unlock: |
ebef2008 AK |
8245 | mutex_unlock(&priv->mutex); |
8246 | ||
8247 | return err; | |
8248 | } | |
8249 | ||
8250 | int iwl3945_rfkill_init(struct iwl3945_priv *priv) | |
8251 | { | |
8252 | struct device *device = wiphy_dev(priv->hw->wiphy); | |
8253 | int ret = 0; | |
8254 | ||
8255 | BUG_ON(device == NULL); | |
8256 | ||
8257 | IWL_DEBUG_RF_KILL("Initializing RFKILL.\n"); | |
80fcc9e2 AG |
8258 | priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN); |
8259 | if (!priv->rfkill) { | |
ebef2008 AK |
8260 | IWL_ERROR("Unable to allocate rfkill device.\n"); |
8261 | ret = -ENOMEM; | |
8262 | goto error; | |
8263 | } | |
8264 | ||
80fcc9e2 AG |
8265 | priv->rfkill->name = priv->cfg->name; |
8266 | priv->rfkill->data = priv; | |
8267 | priv->rfkill->state = RFKILL_STATE_UNBLOCKED; | |
8268 | priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill; | |
8269 | priv->rfkill->user_claim_unsupported = 1; | |
ebef2008 | 8270 | |
80fcc9e2 AG |
8271 | priv->rfkill->dev.class->suspend = NULL; |
8272 | priv->rfkill->dev.class->resume = NULL; | |
ebef2008 | 8273 | |
80fcc9e2 | 8274 | ret = rfkill_register(priv->rfkill); |
ebef2008 AK |
8275 | if (ret) { |
8276 | IWL_ERROR("Unable to register rfkill: %d\n", ret); | |
80fcc9e2 | 8277 | goto freed_rfkill; |
ebef2008 AK |
8278 | } |
8279 | ||
8280 | IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n"); | |
8281 | return ret; | |
8282 | ||
ebef2008 | 8283 | freed_rfkill: |
80fcc9e2 AG |
8284 | if (priv->rfkill != NULL) |
8285 | rfkill_free(priv->rfkill); | |
8286 | priv->rfkill = NULL; | |
ebef2008 AK |
8287 | |
8288 | error: | |
8289 | IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n"); | |
8290 | return ret; | |
8291 | } | |
8292 | ||
8293 | void iwl3945_rfkill_unregister(struct iwl3945_priv *priv) | |
8294 | { | |
80fcc9e2 AG |
8295 | if (priv->rfkill) |
8296 | rfkill_unregister(priv->rfkill); | |
ebef2008 | 8297 | |
80fcc9e2 | 8298 | priv->rfkill = NULL; |
ebef2008 AK |
8299 | } |
8300 | ||
8301 | /* set rf-kill to the right state. */ | |
8302 | void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv) | |
8303 | { | |
8304 | ||
80fcc9e2 AG |
8305 | if (!priv->rfkill) |
8306 | return; | |
8307 | ||
8308 | if (iwl3945_is_rfkill_hw(priv)) { | |
8309 | rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED); | |
ebef2008 | 8310 | return; |
80fcc9e2 | 8311 | } |
ebef2008 | 8312 | |
80fcc9e2 AG |
8313 | if (!iwl3945_is_rfkill_sw(priv)) |
8314 | rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED); | |
ebef2008 | 8315 | else |
80fcc9e2 | 8316 | rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED); |
ebef2008 AK |
8317 | } |
8318 | #endif | |
8319 | ||
b481de9c ZY |
8320 | /***************************************************************************** |
8321 | * | |
8322 | * driver and module entry point | |
8323 | * | |
8324 | *****************************************************************************/ | |
8325 | ||
bb8c093b | 8326 | static struct pci_driver iwl3945_driver = { |
b481de9c | 8327 | .name = DRV_NAME, |
bb8c093b CH |
8328 | .id_table = iwl3945_hw_card_ids, |
8329 | .probe = iwl3945_pci_probe, | |
8330 | .remove = __devexit_p(iwl3945_pci_remove), | |
b481de9c | 8331 | #ifdef CONFIG_PM |
bb8c093b CH |
8332 | .suspend = iwl3945_pci_suspend, |
8333 | .resume = iwl3945_pci_resume, | |
b481de9c ZY |
8334 | #endif |
8335 | }; | |
8336 | ||
bb8c093b | 8337 | static int __init iwl3945_init(void) |
b481de9c ZY |
8338 | { |
8339 | ||
8340 | int ret; | |
8341 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
8342 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 RC |
8343 | |
8344 | ret = iwl3945_rate_control_register(); | |
8345 | if (ret) { | |
8346 | IWL_ERROR("Unable to register rate control algorithm: %d\n", ret); | |
8347 | return ret; | |
8348 | } | |
8349 | ||
bb8c093b | 8350 | ret = pci_register_driver(&iwl3945_driver); |
b481de9c ZY |
8351 | if (ret) { |
8352 | IWL_ERROR("Unable to initialize PCI module\n"); | |
897e1cf2 | 8353 | goto error_register; |
b481de9c | 8354 | } |
c8b0e6e1 | 8355 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 8356 | ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level); |
b481de9c ZY |
8357 | if (ret) { |
8358 | IWL_ERROR("Unable to create driver sysfs file\n"); | |
897e1cf2 | 8359 | goto error_debug; |
b481de9c ZY |
8360 | } |
8361 | #endif | |
8362 | ||
8363 | return ret; | |
897e1cf2 RC |
8364 | |
8365 | #ifdef CONFIG_IWL3945_DEBUG | |
8366 | error_debug: | |
8367 | pci_unregister_driver(&iwl3945_driver); | |
8368 | #endif | |
8369 | error_register: | |
8370 | iwl3945_rate_control_unregister(); | |
8371 | return ret; | |
b481de9c ZY |
8372 | } |
8373 | ||
bb8c093b | 8374 | static void __exit iwl3945_exit(void) |
b481de9c | 8375 | { |
c8b0e6e1 | 8376 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 8377 | driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level); |
b481de9c | 8378 | #endif |
bb8c093b | 8379 | pci_unregister_driver(&iwl3945_driver); |
897e1cf2 | 8380 | iwl3945_rate_control_unregister(); |
b481de9c ZY |
8381 | } |
8382 | ||
25cb6cad ZY |
8383 | MODULE_FIRMWARE("iwlwifi-3945" IWL3945_UCODE_API ".ucode"); |
8384 | ||
bb8c093b | 8385 | module_param_named(antenna, iwl3945_param_antenna, int, 0444); |
b481de9c | 8386 | MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])"); |
bb8c093b | 8387 | module_param_named(disable, iwl3945_param_disable, int, 0444); |
b481de9c | 8388 | MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])"); |
bb8c093b | 8389 | module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444); |
b481de9c ZY |
8390 | MODULE_PARM_DESC(hwcrypto, |
8391 | "using hardware crypto engine (default 0 [software])\n"); | |
bb8c093b | 8392 | module_param_named(debug, iwl3945_param_debug, int, 0444); |
b481de9c | 8393 | MODULE_PARM_DESC(debug, "debug output mask"); |
bb8c093b | 8394 | module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444); |
b481de9c ZY |
8395 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); |
8396 | ||
bb8c093b | 8397 | module_param_named(queues_num, iwl3945_param_queues_num, int, 0444); |
b481de9c ZY |
8398 | MODULE_PARM_DESC(queues_num, "number of hw queues."); |
8399 | ||
8400 | /* QoS */ | |
bb8c093b | 8401 | module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444); |
b481de9c ZY |
8402 | MODULE_PARM_DESC(qos_enable, "enable all QoS functionality"); |
8403 | ||
bb8c093b CH |
8404 | module_exit(iwl3945_exit); |
8405 | module_init(iwl3945_init); |