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wireless: escape_ssid should handle non-printables
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
ZY		 32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
b481de9c
ZY		 40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
7e272fcf 44#include <net/lib80211.h>
b481de9c
ZY		 45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
82b9a121 49#include "iwl-3945-core.h"
b481de9c
ZY		 50#include "iwl-3945.h"
51#include "iwl-helpers.h"
52
c8b0e6e1 53#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 54u32 iwl3945_debug_level;
b481de9c
ZY		 55#endif
56
bb8c093b
CH		 57static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
58 struct iwl3945_tx_queue *txq);
416e1438 59
b481de9c
ZY		 60/******************************************************************************
61 *
62 * module boiler plate
63 *
64 ******************************************************************************/
65
66/* module parameters */
6440adb5
CB		 67static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
68static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
69static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 70static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
6440adb5
CB		 71int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
72static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
dfe7d458 73int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
b481de9c
ZY		 74
75/*
76 * module name, copyright, version, etc.
77 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
78 */
79
80#define DRV_DESCRIPTION \
81"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
82
c8b0e6e1 83#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 84#define VD "d"
85#else
86#define VD
87#endif
88
c8b0e6e1 89#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 90#define VS "s"
91#else
92#define VS
93#endif
94
b9e0b449 95#define IWLWIFI_VERSION "1.2.26k" VD VS
eb7ae89c 96#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
b481de9c
ZY		 97#define DRV_VERSION IWLWIFI_VERSION
98
b481de9c
ZY		 99
100MODULE_DESCRIPTION(DRV_DESCRIPTION);
101MODULE_VERSION(DRV_VERSION);
102MODULE_AUTHOR(DRV_COPYRIGHT);
103MODULE_LICENSE("GPL");
104
8318d78a
JB		 105static const struct ieee80211_supported_band *iwl3945_get_band(
106 struct iwl3945_priv *priv, enum ieee80211_band band)
b481de9c 107{
8318d78a 108 return priv->hw->wiphy->bands[band];
b481de9c
ZY		 109}
110
b481de9c
ZY		 111/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
112 * DMA services
113 *
114 * Theory of operation
115 *
6440adb5
CB		 116 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
117 * of buffer descriptors, each of which points to one or more data buffers for
118 * the device to read from or fill. Driver and device exchange status of each
119 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
120 * entries in each circular buffer, to protect against confusing empty and full
121 * queue states.
122 *
123 * The device reads or writes the data in the queues via the device's several
124 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 125 *
126 * For Tx queue, there are low mark and high mark limits. If, after queuing
127 * the packet for Tx, free space become < low mark, Tx queue stopped. When
128 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
129 * Tx queue resumed.
130 *
6440adb5
CB		 131 * The 3945 operates with six queues: One receive queue, one transmit queue
132 * (#4) for sending commands to the device firmware, and four transmit queues
133 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
ZY		 134 ***************************************************/
135
c54b679d 136int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 137{
fc4b6853 138 int s = q->read_ptr - q->write_ptr;
b481de9c 139
fc4b6853 140 if (q->read_ptr > q->write_ptr)
b481de9c
ZY		 141 s -= q->n_bd;
142
143 if (s <= 0)
144 s += q->n_window;
145 /* keep some reserve to not confuse empty and full situations */
146 s -= 2;
147 if (s < 0)
148 s = 0;
149 return s;
150}
151
c54b679d 152int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 153{
fc4b6853
TW		 154 return q->write_ptr > q->read_ptr ?
155 (i >= q->read_ptr && i < q->write_ptr) :
156 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 157}
158
c54b679d 159
bb8c093b 160static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 161{
6440adb5 162 /* This is for scan command, the big buffer at end of command array */
b481de9c 163 if (is_huge)
6440adb5 164 return q->n_window; /* must be power of 2 */
b481de9c 165
6440adb5 166 /* Otherwise, use normal size buffers */
b481de9c
ZY		 167 return index & (q->n_window - 1);
168}
169
6440adb5
CB		 170/**
171 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
172 */
bb8c093b 173static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
b481de9c
ZY		 174 int count, int slots_num, u32 id)
175{
176 q->n_bd = count;
177 q->n_window = slots_num;
178 q->id = id;
179
c54b679d
TW		 180 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
181 * and iwl_queue_dec_wrap are broken. */
b481de9c
ZY		 182 BUG_ON(!is_power_of_2(count));
183
184 /* slots_num must be power-of-two size, otherwise
185 * get_cmd_index is broken. */
186 BUG_ON(!is_power_of_2(slots_num));
187
188 q->low_mark = q->n_window / 4;
189 if (q->low_mark < 4)
190 q->low_mark = 4;
191
192 q->high_mark = q->n_window / 8;
193 if (q->high_mark < 2)
194 q->high_mark = 2;
195
fc4b6853 196 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 197
198 return 0;
199}
200
6440adb5
CB		 201/**
202 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
203 */
bb8c093b
CH		 204static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
205 struct iwl3945_tx_queue *txq, u32 id)
b481de9c
ZY		 206{
207 struct pci_dev *dev = priv->pci_dev;
208
6440adb5
CB		 209 /* Driver private data, only for Tx (not command) queues,
210 * not shared with device. */
b481de9c
ZY		 211 if (id != IWL_CMD_QUEUE_NUM) {
212 txq->txb = kmalloc(sizeof(txq->txb[0]) *
213 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
214 if (!txq->txb) {
01ebd063 215 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
ZY		 216 "structures failed\n");
217 goto error;
218 }
219 } else
220 txq->txb = NULL;
221
6440adb5
CB		 222 /* Circular buffer of transmit frame descriptors (TFDs),
223 * shared with device */
b481de9c
ZY		 224 txq->bd = pci_alloc_consistent(dev,
225 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
226 &txq->q.dma_addr);
227
228 if (!txq->bd) {
229 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
230 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
231 goto error;
232 }
233 txq->q.id = id;
234
235 return 0;
236
237 error:
3ac7f146
TW		 238 kfree(txq->txb);
239 txq->txb = NULL;
b481de9c
ZY		 240
241 return -ENOMEM;
242}
243
6440adb5
CB		 244/**
245 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
246 */
bb8c093b
CH		 247int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
248 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY		 249{
250 struct pci_dev *dev = priv->pci_dev;
251 int len;
252 int rc = 0;
253
6440adb5
CB		 254 /*
255 * Alloc buffer array for commands (Tx or other types of commands).
256 * For the command queue (#4), allocate command space + one big
257 * command for scan, since scan command is very huge; the system will
258 * not have two scans at the same time, so only one is needed.
259 * For data Tx queues (all other queues), no super-size command
260 * space is needed.
261 */
bb8c093b 262 len = sizeof(struct iwl3945_cmd) * slots_num;
b481de9c
ZY		 263 if (txq_id == IWL_CMD_QUEUE_NUM)
264 len += IWL_MAX_SCAN_SIZE;
265 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
266 if (!txq->cmd)
267 return -ENOMEM;
268
6440adb5 269 /* Alloc driver data array and TFD circular buffer */
bb8c093b 270 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY		 271 if (rc) {
272 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
273
274 return -ENOMEM;
275 }
276 txq->need_update = 0;
277
278 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 279 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 280 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
CB		 281
282 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 283 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 284
6440adb5 285 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 286 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 287
288 return 0;
289}
290
291/**
bb8c093b 292 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 293 * @txq: Transmit queue to deallocate.
294 *
295 * Empty queue by removing and destroying all BD's.
6440adb5
CB		 296 * Free all buffers.
297 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 298 */
bb8c093b 299void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 300{
bb8c093b 301 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY		 302 struct pci_dev *dev = priv->pci_dev;
303 int len;
304
305 if (q->n_bd == 0)
306 return;
307
308 /* first, empty all BD's */
fc4b6853 309 for (; q->write_ptr != q->read_ptr;
c54b679d 310 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 311 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 312
bb8c093b 313 len = sizeof(struct iwl3945_cmd) * q->n_window;
b481de9c
ZY		 314 if (q->id == IWL_CMD_QUEUE_NUM)
315 len += IWL_MAX_SCAN_SIZE;
316
6440adb5 317 /* De-alloc array of command/tx buffers */
b481de9c
ZY		 318 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
319
6440adb5 320 /* De-alloc circular buffer of TFDs */
b481de9c 321 if (txq->q.n_bd)
bb8c093b 322 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
ZY		 323 txq->q.n_bd, txq->bd, txq->q.dma_addr);
324
6440adb5 325 /* De-alloc array of per-TFD driver data */
3ac7f146
TW		 326 kfree(txq->txb);
327 txq->txb = NULL;
b481de9c 328
6440adb5 329 /* 0-fill queue descriptor structure */
b481de9c
ZY		 330 memset(txq, 0, sizeof(*txq));
331}
332
bb8c093b 333const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
ZY		 334
335/*************** STATION TABLE MANAGEMENT ****
9fbab516 336 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 337 * the functionality provided here
338 */
339
340/**************************************************************/
01ebd063 341#if 0 /* temporary disable till we add real remove station */
6440adb5
CB		 342/**
343 * iwl3945_remove_station - Remove driver's knowledge of station.
344 *
345 * NOTE: This does not remove station from device's station table.
346 */
bb8c093b 347static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 348{
349 int index = IWL_INVALID_STATION;
350 int i;
351 unsigned long flags;
352
353 spin_lock_irqsave(&priv->sta_lock, flags);
354
355 if (is_ap)
356 index = IWL_AP_ID;
357 else if (is_broadcast_ether_addr(addr))
358 index = priv->hw_setting.bcast_sta_id;
359 else
360 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
361 if (priv->stations[i].used &&
362 !compare_ether_addr(priv->stations[i].sta.sta.addr,
363 addr)) {
364 index = i;
365 break;
366 }
367
368 if (unlikely(index == IWL_INVALID_STATION))
369 goto out;
370
371 if (priv->stations[index].used) {
372 priv->stations[index].used = 0;
373 priv->num_stations--;
374 }
375
376 BUG_ON(priv->num_stations < 0);
377
378out:
379 spin_unlock_irqrestore(&priv->sta_lock, flags);
380 return 0;
381}
556f8db7 382#endif
6440adb5
CB		 383
384/**
385 * iwl3945_clear_stations_table - Clear the driver's station table
386 *
387 * NOTE: This does not clear or otherwise alter the device's station table.
388 */
bb8c093b 389static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
b481de9c
ZY		 390{
391 unsigned long flags;
392
393 spin_lock_irqsave(&priv->sta_lock, flags);
394
395 priv->num_stations = 0;
396 memset(priv->stations, 0, sizeof(priv->stations));
397
398 spin_unlock_irqrestore(&priv->sta_lock, flags);
399}
400
6440adb5
CB		 401/**
402 * iwl3945_add_station - Add station to station tables in driver and device
403 */
bb8c093b 404u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY		 405{
406 int i;
407 int index = IWL_INVALID_STATION;
bb8c093b 408 struct iwl3945_station_entry *station;
b481de9c 409 unsigned long flags_spin;
c14c521e 410 u8 rate;
b481de9c
ZY		 411
412 spin_lock_irqsave(&priv->sta_lock, flags_spin);
413 if (is_ap)
414 index = IWL_AP_ID;
415 else if (is_broadcast_ether_addr(addr))
416 index = priv->hw_setting.bcast_sta_id;
417 else
418 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
419 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
420 addr)) {
421 index = i;
422 break;
423 }
424
425 if (!priv->stations[i].used &&
426 index == IWL_INVALID_STATION)
427 index = i;
428 }
429
01ebd063 430 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY		 431 since they have different meaning */
432 if (unlikely(index == IWL_INVALID_STATION)) {
433 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
434 return index;
435 }
436
437 if (priv->stations[index].used &&
438 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
439 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
440 return index;
441 }
442
e174961c 443 IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
b481de9c
ZY		 444 station = &priv->stations[index];
445 station->used = 1;
446 priv->num_stations++;
447
6440adb5 448 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 449 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY		 450 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
451 station->sta.mode = 0;
452 station->sta.sta.sta_id = index;
453 station->sta.station_flags = 0;
454
8318d78a 455 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW		 456 rate = IWL_RATE_6M_PLCP;
457 else
458 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY		 459
460 /* Turn on both antennas for the station... */
461 station->sta.rate_n_flags =
bb8c093b 462 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e
ZY		 463 station->current_rate.rate_n_flags =
464 le16_to_cpu(station->sta.rate_n_flags);
465
b481de9c 466 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB		 467
468 /* Add station to device's station table */
bb8c093b 469 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 470 return index;
471
472}
473
474/*************** DRIVER STATUS FUNCTIONS *****/
475
bb8c093b 476static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
ZY		 477{
478 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
479 * set but EXIT_PENDING is not */
480 return test_bit(STATUS_READY, &priv->status) &&
481 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
482 !test_bit(STATUS_EXIT_PENDING, &priv->status);
483}
484
bb8c093b 485static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
ZY		 486{
487 return test_bit(STATUS_ALIVE, &priv->status);
488}
489
bb8c093b 490static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY		 491{
492 return test_bit(STATUS_INIT, &priv->status);
493}
494
80fcc9e2
AG		 495static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
496{
497 return test_bit(STATUS_RF_KILL_SW, &priv->status);
498}
499
500static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
501{
502 return test_bit(STATUS_RF_KILL_HW, &priv->status);
503}
504
bb8c093b 505static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c 506{
80fcc9e2
AG		 507 return iwl3945_is_rfkill_hw(priv) ||
508 iwl3945_is_rfkill_sw(priv);
b481de9c
ZY		 509}
510
bb8c093b 511static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY		 512{
513
bb8c093b 514 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 515 return 0;
516
bb8c093b 517 return iwl3945_is_ready(priv);
b481de9c
ZY		 518}
519
520/*************** HOST COMMAND QUEUE FUNCTIONS *****/
521
522#define IWL_CMD(x) case x : return #x
523
524static const char *get_cmd_string(u8 cmd)
525{
526 switch (cmd) {
527 IWL_CMD(REPLY_ALIVE);
528 IWL_CMD(REPLY_ERROR);
529 IWL_CMD(REPLY_RXON);
530 IWL_CMD(REPLY_RXON_ASSOC);
531 IWL_CMD(REPLY_QOS_PARAM);
532 IWL_CMD(REPLY_RXON_TIMING);
533 IWL_CMD(REPLY_ADD_STA);
534 IWL_CMD(REPLY_REMOVE_STA);
535 IWL_CMD(REPLY_REMOVE_ALL_STA);
536 IWL_CMD(REPLY_3945_RX);
537 IWL_CMD(REPLY_TX);
538 IWL_CMD(REPLY_RATE_SCALE);
539 IWL_CMD(REPLY_LEDS_CMD);
540 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
541 IWL_CMD(RADAR_NOTIFICATION);
542 IWL_CMD(REPLY_QUIET_CMD);
543 IWL_CMD(REPLY_CHANNEL_SWITCH);
544 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
545 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
546 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
547 IWL_CMD(POWER_TABLE_CMD);
548 IWL_CMD(PM_SLEEP_NOTIFICATION);
549 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
550 IWL_CMD(REPLY_SCAN_CMD);
551 IWL_CMD(REPLY_SCAN_ABORT_CMD);
552 IWL_CMD(SCAN_START_NOTIFICATION);
553 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
554 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
555 IWL_CMD(BEACON_NOTIFICATION);
556 IWL_CMD(REPLY_TX_BEACON);
557 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
558 IWL_CMD(QUIET_NOTIFICATION);
559 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
560 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
561 IWL_CMD(REPLY_BT_CONFIG);
562 IWL_CMD(REPLY_STATISTICS_CMD);
563 IWL_CMD(STATISTICS_NOTIFICATION);
564 IWL_CMD(REPLY_CARD_STATE_CMD);
565 IWL_CMD(CARD_STATE_NOTIFICATION);
566 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
567 default:
568 return "UNKNOWN";
569
570 }
571}
572
573#define HOST_COMPLETE_TIMEOUT (HZ / 2)
574
575/**
bb8c093b 576 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 577 * @priv: device private data point
578 * @cmd: a point to the ucode command structure
579 *
580 * The function returns < 0 values to indicate the operation is
581 * failed. On success, it turns the index (> 0) of command in the
582 * command queue.
583 */
bb8c093b 584static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 585{
bb8c093b
CH		 586 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
587 struct iwl3945_queue *q = &txq->q;
588 struct iwl3945_tfd_frame *tfd;
b481de9c 589 u32 *control_flags;
bb8c093b 590 struct iwl3945_cmd *out_cmd;
b481de9c
ZY		 591 u32 idx;
592 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
593 dma_addr_t phys_addr;
594 int pad;
595 u16 count;
596 int ret;
597 unsigned long flags;
598
599 /* If any of the command structures end up being larger than
600 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
601 * we will need to increase the size of the TFD entries */
602 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
603 !(cmd->meta.flags & CMD_SIZE_HUGE));
604
c342a1b9
GG		 605
606 if (iwl3945_is_rfkill(priv)) {
607 IWL_DEBUG_INFO("Not sending command - RF KILL");
608 return -EIO;
609 }
610
bb8c093b 611 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY		 612 IWL_ERROR("No space for Tx\n");
613 return -ENOSPC;
614 }
615
616 spin_lock_irqsave(&priv->hcmd_lock, flags);
617
fc4b6853 618 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 619 memset(tfd, 0, sizeof(*tfd));
620
621 control_flags = (u32 *) tfd;
622
fc4b6853 623 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY		 624 out_cmd = &txq->cmd[idx];
625
626 out_cmd->hdr.cmd = cmd->id;
627 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
628 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
629
630 /* At this point, the out_cmd now has all of the incoming cmd
631 * information */
632
633 out_cmd->hdr.flags = 0;
634 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 635 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY		 636 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
637 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
638
639 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH		 640 offsetof(struct iwl3945_cmd, hdr);
641 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 642
643 pad = U32_PAD(cmd->len);
644 count = TFD_CTL_COUNT_GET(*control_flags);
645 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
646
647 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
648 "%d bytes at %d[%d]:%d\n",
649 get_cmd_string(out_cmd->hdr.cmd),
650 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 651 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 652
653 txq->need_update = 1;
6440adb5
CB		 654
655 /* Increment and update queue's write index */
c54b679d 656 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 657 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 658
659 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
660 return ret ? ret : idx;
661}
662
bb8c093b 663static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 664{
665 int ret;
666
667 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
668
669 /* An asynchronous command can not expect an SKB to be set. */
670 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
671
672 /* An asynchronous command MUST have a callback. */
673 BUG_ON(!cmd->meta.u.callback);
674
675 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
676 return -EBUSY;
677
bb8c093b 678 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 679 if (ret < 0) {
bb8c093b 680 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 681 get_cmd_string(cmd->id), ret);
682 return ret;
683 }
684 return 0;
685}
686
bb8c093b 687static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 688{
689 int cmd_idx;
690 int ret;
b481de9c
ZY		 691
692 BUG_ON(cmd->meta.flags & CMD_ASYNC);
693
694 /* A synchronous command can not have a callback set. */
695 BUG_ON(cmd->meta.u.callback != NULL);
696
e5472978 697 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
b481de9c
ZY		 698 IWL_ERROR("Error sending %s: Already sending a host command\n",
699 get_cmd_string(cmd->id));
e5472978
TW		 700 ret = -EBUSY;
701 goto out;
b481de9c
ZY		 702 }
703
704 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
705
706 if (cmd->meta.flags & CMD_WANT_SKB)
707 cmd->meta.source = &cmd->meta;
708
bb8c093b 709 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY		 710 if (cmd_idx < 0) {
711 ret = cmd_idx;
bb8c093b 712 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 713 get_cmd_string(cmd->id), ret);
714 goto out;
715 }
716
717 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
718 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
719 HOST_COMPLETE_TIMEOUT);
720 if (!ret) {
721 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
722 IWL_ERROR("Error sending %s: time out after %dms.\n",
723 get_cmd_string(cmd->id),
724 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
725
726 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
727 ret = -ETIMEDOUT;
728 goto cancel;
729 }
730 }
731
732 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
733 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
734 get_cmd_string(cmd->id));
735 ret = -ECANCELED;
736 goto fail;
737 }
738 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
739 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
740 get_cmd_string(cmd->id));
741 ret = -EIO;
742 goto fail;
743 }
744 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
745 IWL_ERROR("Error: Response NULL in '%s'\n",
746 get_cmd_string(cmd->id));
747 ret = -EIO;
748 goto out;
749 }
750
751 ret = 0;
752 goto out;
753
754cancel:
755 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 756 struct iwl3945_cmd *qcmd;
b481de9c
ZY		 757
758 /* Cancel the CMD_WANT_SKB flag for the cmd in the
759 * TX cmd queue. Otherwise in case the cmd comes
760 * in later, it will possibly set an invalid
761 * address (cmd->meta.source). */
762 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
763 qcmd->meta.flags &= ~CMD_WANT_SKB;
764 }
765fail:
766 if (cmd->meta.u.skb) {
767 dev_kfree_skb_any(cmd->meta.u.skb);
768 cmd->meta.u.skb = NULL;
769 }
770out:
e5472978 771 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
b481de9c
ZY		 772 return ret;
773}
774
bb8c093b 775int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 776{
b481de9c 777 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 778 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 779
bb8c093b 780 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY		 781}
782
bb8c093b 783int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 784{
bb8c093b 785 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 786 .id = id,
787 .len = len,
788 .data = data,
789 };
790
bb8c093b 791 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 792}
793
bb8c093b 794static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 795{
bb8c093b 796 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 797 .id = id,
798 .len = sizeof(val),
799 .data = &val,
800 };
801
bb8c093b 802 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 803}
804
bb8c093b 805int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 806{
bb8c093b 807 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY		 808}
809
b481de9c 810/**
bb8c093b 811 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB		 812 * @band: 2.4 or 5 GHz band
813 * @channel: Any channel valid for the requested band
b481de9c 814
8318d78a 815 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY		 816 *
817 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 818 * in the staging RXON flag structure based on the band
b481de9c 819 */
8318d78a
JB		 820static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
821 enum ieee80211_band band,
822 u16 channel)
b481de9c 823{
8318d78a 824 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 825 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 826 channel, band);
b481de9c
ZY		 827 return -EINVAL;
828 }
829
830 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
8318d78a 831 (priv->band == band))
b481de9c
ZY		 832 return 0;
833
834 priv->staging_rxon.channel = cpu_to_le16(channel);
8318d78a 835 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 836 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
837 else
838 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
839
8318d78a 840 priv->band = band;
b481de9c 841
8318d78a 842 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY		 843
844 return 0;
845}
846
847/**
bb8c093b 848 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 849 *
850 * NOTE: This is really only useful during development and can eventually
851 * be #ifdef'd out once the driver is stable and folks aren't actively
852 * making changes
853 */
bb8c093b 854static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 855{
856 int error = 0;
857 int counter = 1;
858
859 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
860 error |= le32_to_cpu(rxon->flags &
861 (RXON_FLG_TGJ_NARROW_BAND_MSK |
862 RXON_FLG_RADAR_DETECT_MSK));
863 if (error)
864 IWL_WARNING("check 24G fields %d | %d\n",
865 counter++, error);
866 } else {
867 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
868 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
869 if (error)
870 IWL_WARNING("check 52 fields %d | %d\n",
871 counter++, error);
872 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
873 if (error)
874 IWL_WARNING("check 52 CCK %d | %d\n",
875 counter++, error);
876 }
877 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
878 if (error)
879 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
880
881 /* make sure basic rates 6Mbps and 1Mbps are supported */
882 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
883 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
884 if (error)
885 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
886
887 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
888 if (error)
889 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
890
891 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
892 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
893 if (error)
894 IWL_WARNING("check CCK and short slot %d | %d\n",
895 counter++, error);
896
897 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
898 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
899 if (error)
900 IWL_WARNING("check CCK & auto detect %d | %d\n",
901 counter++, error);
902
903 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
904 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
905 if (error)
906 IWL_WARNING("check TGG and auto detect %d | %d\n",
907 counter++, error);
908
909 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
910 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
911 RXON_FLG_ANT_A_MSK)) == 0);
912 if (error)
913 IWL_WARNING("check antenna %d %d\n", counter++, error);
914
915 if (error)
916 IWL_WARNING("Tuning to channel %d\n",
917 le16_to_cpu(rxon->channel));
918
919 if (error) {
bb8c093b 920 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY		 921 return -1;
922 }
923 return 0;
924}
925
926/**
9fbab516 927 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 928 * @priv: staging_rxon is compared to active_rxon
b481de9c 929 *
9fbab516
BC		 930 * If the RXON structure is changing enough to require a new tune,
931 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
932 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 933 */
bb8c093b 934static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY		 935{
936
937 /* These items are only settable from the full RXON command */
5d1e2325 938 if (!(iwl3945_is_associated(priv)) ||
b481de9c
ZY		 939 compare_ether_addr(priv->staging_rxon.bssid_addr,
940 priv->active_rxon.bssid_addr) ||
941 compare_ether_addr(priv->staging_rxon.node_addr,
942 priv->active_rxon.node_addr) ||
943 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
944 priv->active_rxon.wlap_bssid_addr) ||
945 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
946 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
947 (priv->staging_rxon.air_propagation !=
948 priv->active_rxon.air_propagation) ||
949 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
950 return 1;
951
952 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
953 * be updated with the RXON_ASSOC command -- however only some
954 * flag transitions are allowed using RXON_ASSOC */
955
956 /* Check if we are not switching bands */
957 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
958 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
959 return 1;
960
961 /* Check if we are switching association toggle */
962 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
963 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
964 return 1;
965
966 return 0;
967}
968
bb8c093b 969static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY		 970{
971 int rc = 0;
bb8c093b
CH		 972 struct iwl3945_rx_packet *res = NULL;
973 struct iwl3945_rxon_assoc_cmd rxon_assoc;
974 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 975 .id = REPLY_RXON_ASSOC,
976 .len = sizeof(rxon_assoc),
977 .meta.flags = CMD_WANT_SKB,
978 .data = &rxon_assoc,
979 };
bb8c093b
CH		 980 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
981 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY		 982
983 if ((rxon1->flags == rxon2->flags) &&
984 (rxon1->filter_flags == rxon2->filter_flags) &&
985 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
986 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
987 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
988 return 0;
989 }
990
991 rxon_assoc.flags = priv->staging_rxon.flags;
992 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
993 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
994 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
995 rxon_assoc.reserved = 0;
996
bb8c093b 997 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 998 if (rc)
999 return rc;
1000
bb8c093b 1001 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1002 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1003 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1004 rc = -EIO;
1005 }
1006
1007 priv->alloc_rxb_skb--;
1008 dev_kfree_skb_any(cmd.meta.u.skb);
1009
1010 return rc;
1011}
1012
1013/**
bb8c093b 1014 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1015 *
01ebd063 1016 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 1017 * the active_rxon structure is updated with the new data. This
1018 * function correctly transitions out of the RXON_ASSOC_MSK state if
1019 * a HW tune is required based on the RXON structure changes.
1020 */
bb8c093b 1021static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY		 1022{
1023 /* cast away the const for active_rxon in this function */
bb8c093b 1024 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c
ZY		 1025 int rc = 0;
1026
bb8c093b 1027 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 1028 return -1;
1029
1030 /* always get timestamp with Rx frame */
1031 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1032
1033 /* select antenna */
1034 priv->staging_rxon.flags &=
1035 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1036 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1037
bb8c093b 1038 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY		 1039 if (rc) {
1040 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1041 return -EINVAL;
1042 }
1043
1044 /* If we don't need to send a full RXON, we can use
bb8c093b 1045 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1046 * and other flags for the current radio configuration. */
bb8c093b
CH		 1047 if (!iwl3945_full_rxon_required(priv)) {
1048 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY		 1049 if (rc) {
1050 IWL_ERROR("Error setting RXON_ASSOC "
1051 "configuration (%d).\n", rc);
1052 return rc;
1053 }
1054
1055 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1056
1057 return 0;
1058 }
1059
1060 /* If we are currently associated and the new config requires
1061 * an RXON_ASSOC and the new config wants the associated mask enabled,
1062 * we must clear the associated from the active configuration
1063 * before we apply the new config */
bb8c093b 1064 if (iwl3945_is_associated(priv) &&
b481de9c
ZY		 1065 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1066 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1067 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1068
bb8c093b
CH		 1069 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1070 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY		 1071 &priv->active_rxon);
1072
1073 /* If the mask clearing failed then we set
1074 * active_rxon back to what it was previously */
1075 if (rc) {
1076 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1077 IWL_ERROR("Error clearing ASSOC_MSK on current "
1078 "configuration (%d).\n", rc);
1079 return rc;
1080 }
b481de9c
ZY		 1081 }
1082
1083 IWL_DEBUG_INFO("Sending RXON\n"
1084 "* with%s RXON_FILTER_ASSOC_MSK\n"
1085 "* channel = %d\n"
e174961c 1086 "* bssid = %pM\n",
b481de9c
ZY		 1087 ((priv->staging_rxon.filter_flags &
1088 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1089 le16_to_cpu(priv->staging_rxon.channel),
e174961c 1090 priv->staging_rxon.bssid_addr);
b481de9c
ZY		 1091
1092 /* Apply the new configuration */
bb8c093b
CH		 1093 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1094 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY		 1095 if (rc) {
1096 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1097 return rc;
1098 }
1099
1100 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1101
bb8c093b 1102 iwl3945_clear_stations_table(priv);
556f8db7 1103
b481de9c
ZY		 1104 /* If we issue a new RXON command which required a tune then we must
1105 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1106 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1107 if (rc) {
1108 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1109 return rc;
1110 }
1111
1112 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1113 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY		 1114 IWL_INVALID_STATION) {
1115 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1116 return -EIO;
1117 }
1118
1119 /* If we have set the ASSOC_MSK and we are in BSS mode then
1120 * add the IWL_AP_ID to the station rate table */
bb8c093b 1121 if (iwl3945_is_associated(priv) &&
05c914fe 1122 (priv->iw_mode == NL80211_IFTYPE_STATION))
bb8c093b 1123 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY		 1124 == IWL_INVALID_STATION) {
1125 IWL_ERROR("Error adding AP address for transmit.\n");
1126 return -EIO;
1127 }
1128
8318d78a 1129 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY		 1130 rc = iwl3945_init_hw_rate_table(priv);
1131 if (rc) {
1132 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1133 return -EIO;
1134 }
1135
1136 return 0;
1137}
1138
bb8c093b 1139static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1140{
bb8c093b 1141 struct iwl3945_bt_cmd bt_cmd = {
b481de9c
ZY		 1142 .flags = 3,
1143 .lead_time = 0xAA,
1144 .max_kill = 1,
1145 .kill_ack_mask = 0,
1146 .kill_cts_mask = 0,
1147 };
1148
bb8c093b
CH		 1149 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1150 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
b481de9c
ZY		 1151}
1152
bb8c093b 1153static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY		 1154{
1155 int rc = 0;
bb8c093b
CH		 1156 struct iwl3945_rx_packet *res;
1157 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1158 .id = REPLY_SCAN_ABORT_CMD,
1159 .meta.flags = CMD_WANT_SKB,
1160 };
1161
1162 /* If there isn't a scan actively going on in the hardware
1163 * then we are in between scan bands and not actually
1164 * actively scanning, so don't send the abort command */
1165 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1166 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1167 return 0;
1168 }
1169
bb8c093b 1170 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1171 if (rc) {
1172 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1173 return rc;
1174 }
1175
bb8c093b 1176 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1177 if (res->u.status != CAN_ABORT_STATUS) {
1178 /* The scan abort will return 1 for success or
1179 * 2 for "failure". A failure condition can be
1180 * due to simply not being in an active scan which
1181 * can occur if we send the scan abort before we
1182 * the microcode has notified us that a scan is
1183 * completed. */
1184 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1185 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1186 clear_bit(STATUS_SCAN_HW, &priv->status);
1187 }
1188
1189 dev_kfree_skb_any(cmd.meta.u.skb);
1190
1191 return rc;
1192}
1193
bb8c093b
CH		 1194static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1195 struct iwl3945_cmd *cmd,
b481de9c
ZY		 1196 struct sk_buff *skb)
1197{
1198 return 1;
1199}
1200
1201/*
1202 * CARD_STATE_CMD
1203 *
9fbab516 1204 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY		 1205 *
1206 * When in the 'enable' state the card operates as normal.
1207 * When in the 'disable' state, the card enters into a low power mode.
1208 * When in the 'halt' state, the card is shut down and must be fully
1209 * restarted to come back on.
1210 */
bb8c093b 1211static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1212{
bb8c093b 1213 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1214 .id = REPLY_CARD_STATE_CMD,
1215 .len = sizeof(u32),
1216 .data = &flags,
1217 .meta.flags = meta_flag,
1218 };
1219
1220 if (meta_flag & CMD_ASYNC)
bb8c093b 1221 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1222
bb8c093b 1223 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1224}
1225
bb8c093b
CH		 1226static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1227 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1228{
bb8c093b 1229 struct iwl3945_rx_packet *res = NULL;
b481de9c
ZY		 1230
1231 if (!skb) {
1232 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1233 return 1;
1234 }
1235
bb8c093b 1236 res = (struct iwl3945_rx_packet *)skb->data;
b481de9c
ZY		 1237 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1238 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1239 res->hdr.flags);
1240 return 1;
1241 }
1242
1243 switch (res->u.add_sta.status) {
1244 case ADD_STA_SUCCESS_MSK:
1245 break;
1246 default:
1247 break;
1248 }
1249
1250 /* We didn't cache the SKB; let the caller free it */
1251 return 1;
1252}
1253
bb8c093b
CH		 1254int iwl3945_send_add_station(struct iwl3945_priv *priv,
1255 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1256{
bb8c093b 1257 struct iwl3945_rx_packet *res = NULL;
b481de9c 1258 int rc = 0;
bb8c093b 1259 struct iwl3945_host_cmd cmd = {
b481de9c 1260 .id = REPLY_ADD_STA,
bb8c093b 1261 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY		 1262 .meta.flags = flags,
1263 .data = sta,
1264 };
1265
1266 if (flags & CMD_ASYNC)
bb8c093b 1267 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY		 1268 else
1269 cmd.meta.flags |= CMD_WANT_SKB;
1270
bb8c093b 1271 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1272
1273 if (rc || (flags & CMD_ASYNC))
1274 return rc;
1275
bb8c093b 1276 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1277 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1278 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1279 res->hdr.flags);
1280 rc = -EIO;
1281 }
1282
1283 if (rc == 0) {
1284 switch (res->u.add_sta.status) {
1285 case ADD_STA_SUCCESS_MSK:
1286 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1287 break;
1288 default:
1289 rc = -EIO;
1290 IWL_WARNING("REPLY_ADD_STA failed\n");
1291 break;
1292 }
1293 }
1294
1295 priv->alloc_rxb_skb--;
1296 dev_kfree_skb_any(cmd.meta.u.skb);
1297
1298 return rc;
1299}
1300
bb8c093b 1301static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY		 1302 struct ieee80211_key_conf *keyconf,
1303 u8 sta_id)
1304{
1305 unsigned long flags;
1306 __le16 key_flags = 0;
1307
1308 switch (keyconf->alg) {
1309 case ALG_CCMP:
1310 key_flags |= STA_KEY_FLG_CCMP;
1311 key_flags |= cpu_to_le16(
1312 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1313 key_flags &= ~STA_KEY_FLG_INVALID;
1314 break;
1315 case ALG_TKIP:
1316 case ALG_WEP:
b481de9c
ZY		 1317 default:
1318 return -EINVAL;
1319 }
1320 spin_lock_irqsave(&priv->sta_lock, flags);
1321 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1322 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1323 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1324 keyconf->keylen);
1325
1326 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1327 keyconf->keylen);
1328 priv->stations[sta_id].sta.key.key_flags = key_flags;
1329 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1330 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1331
1332 spin_unlock_irqrestore(&priv->sta_lock, flags);
1333
1334 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1335 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1336 return 0;
1337}
1338
bb8c093b 1339static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY		 1340{
1341 unsigned long flags;
1342
1343 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH		 1344 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1345 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
b481de9c
ZY		 1346 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1347 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1348 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1349 spin_unlock_irqrestore(&priv->sta_lock, flags);
1350
1351 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1352 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1353 return 0;
1354}
1355
bb8c093b 1356static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY		 1357{
1358 struct list_head *element;
1359
1360 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1361 priv->frames_count);
1362
1363 while (!list_empty(&priv->free_frames)) {
1364 element = priv->free_frames.next;
1365 list_del(element);
bb8c093b 1366 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY		 1367 priv->frames_count--;
1368 }
1369
1370 if (priv->frames_count) {
1371 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1372 priv->frames_count);
1373 priv->frames_count = 0;
1374 }
1375}
1376
bb8c093b 1377static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1378{
bb8c093b 1379 struct iwl3945_frame *frame;
b481de9c
ZY		 1380 struct list_head *element;
1381 if (list_empty(&priv->free_frames)) {
1382 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1383 if (!frame) {
1384 IWL_ERROR("Could not allocate frame!\n");
1385 return NULL;
1386 }
1387
1388 priv->frames_count++;
1389 return frame;
1390 }
1391
1392 element = priv->free_frames.next;
1393 list_del(element);
bb8c093b 1394 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY		 1395}
1396
bb8c093b 1397static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY		 1398{
1399 memset(frame, 0, sizeof(*frame));
1400 list_add(&frame->list, &priv->free_frames);
1401}
1402
bb8c093b 1403unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c
ZY		 1404 struct ieee80211_hdr *hdr,
1405 const u8 *dest, int left)
1406{
1407
bb8c093b 1408 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB		 1409 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
1410 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY		 1411 return 0;
1412
1413 if (priv->ibss_beacon->len > left)
1414 return 0;
1415
1416 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1417
1418 return priv->ibss_beacon->len;
1419}
1420
bb8c093b 1421static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY		 1422{
1423 u8 i;
1424
1425 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1426 i = iwl3945_rates[i].next_ieee) {
b481de9c 1427 if (rate_mask & (1 << i))
bb8c093b 1428 return iwl3945_rates[i].plcp;
b481de9c
ZY		 1429 }
1430
1431 return IWL_RATE_INVALID;
1432}
1433
bb8c093b 1434static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1435{
bb8c093b 1436 struct iwl3945_frame *frame;
b481de9c
ZY		 1437 unsigned int frame_size;
1438 int rc;
1439 u8 rate;
1440
bb8c093b 1441 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY		 1442
1443 if (!frame) {
1444 IWL_ERROR("Could not obtain free frame buffer for beacon "
1445 "command.\n");
1446 return -ENOMEM;
1447 }
1448
1449 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1450 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY		 1451 0xFF0);
1452 if (rate == IWL_INVALID_RATE)
1453 rate = IWL_RATE_6M_PLCP;
1454 } else {
bb8c093b 1455 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY		 1456 if (rate == IWL_INVALID_RATE)
1457 rate = IWL_RATE_1M_PLCP;
1458 }
1459
bb8c093b 1460 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1461
bb8c093b 1462 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1463 &frame->u.cmd[0]);
1464
bb8c093b 1465 iwl3945_free_frame(priv, frame);
b481de9c
ZY		 1466
1467 return rc;
1468}
1469
1470/******************************************************************************
1471 *
1472 * EEPROM related functions
1473 *
1474 ******************************************************************************/
1475
bb8c093b 1476static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY		 1477{
1478 memcpy(mac, priv->eeprom.mac_address, 6);
1479}
1480
74a3a250
RC		 1481/*
1482 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1483 * embedded controller) as EEPROM reader; each read is a series of pulses
1484 * to/from the EEPROM chip, not a single event, so even reads could conflict
1485 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1486 * simply claims ownership, which should be safe when this function is called
1487 * (i.e. before loading uCode!).
1488 */
1489static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1490{
1491 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1492 return 0;
1493}
1494
b481de9c 1495/**
bb8c093b 1496 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1497 *
6440adb5 1498 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY		 1499 *
1500 * NOTE: This routine uses the non-debug IO access functions.
1501 */
bb8c093b 1502int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c 1503{
58ff6d4d 1504 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1505 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c
ZY		 1506 u32 r;
1507 int sz = sizeof(priv->eeprom);
1508 int rc;
1509 int i;
1510 u16 addr;
1511
1512 /* The EEPROM structure has several padding buffers within it
1513 * and when adding new EEPROM maps is subject to programmer errors
1514 * which may be very difficult to identify without explicitly
1515 * checking the resulting size of the eeprom map. */
1516 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1517
1518 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
6f147926 1519 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
b481de9c
ZY		 1520 return -ENOENT;
1521 }
1522
6440adb5 1523 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
bb8c093b 1524 rc = iwl3945_eeprom_acquire_semaphore(priv);
b481de9c 1525 if (rc < 0) {
91e17473 1526 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY		 1527 return -ENOENT;
1528 }
1529
1530 /* eeprom is an array of 16bit values */
1531 for (addr = 0; addr < sz; addr += sizeof(u16)) {
bb8c093b
CH		 1532 _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
1533 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
b481de9c
ZY		 1534
1535 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1536 i += IWL_EEPROM_ACCESS_DELAY) {
bb8c093b 1537 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
b481de9c
ZY		 1538 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1539 break;
1540 udelay(IWL_EEPROM_ACCESS_DELAY);
1541 }
1542
1543 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
6f147926 1544 IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
b481de9c
ZY		 1545 return -ETIMEDOUT;
1546 }
58ff6d4d 1547 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY		 1548 }
1549
1550 return 0;
1551}
1552
bb8c093b 1553static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 1554{
1555 if (priv->hw_setting.shared_virt)
1556 pci_free_consistent(priv->pci_dev,
bb8c093b 1557 sizeof(struct iwl3945_shared),
b481de9c
ZY		 1558 priv->hw_setting.shared_virt,
1559 priv->hw_setting.shared_phys);
1560}
1561
1562/**
bb8c093b 1563 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1564 *
1565 * return : set the bit for each supported rate insert in ie
1566 */
bb8c093b 1567static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1568 u16 basic_rate, int *left)
b481de9c
ZY		 1569{
1570 u16 ret_rates = 0, bit;
1571 int i;
c7c46676
TW		 1572 u8 *cnt = ie;
1573 u8 *rates = ie + 1;
b481de9c
ZY		 1574
1575 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1576 if (bit & supported_rate) {
1577 ret_rates |= bit;
bb8c093b 1578 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW		 1579 ((bit & basic_rate) ? 0x80 : 0x00);
1580 (*cnt)++;
1581 (*left)--;
1582 if ((*left <= 0) ||
1583 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1584 break;
1585 }
1586 }
1587
1588 return ret_rates;
1589}
1590
1591/**
bb8c093b 1592 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1593 */
bb8c093b 1594static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c
ZY		 1595 struct ieee80211_mgmt *frame,
1596 int left, int is_direct)
1597{
1598 int len = 0;
1599 u8 *pos = NULL;
c7c46676 1600 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY		 1601
1602 /* Make sure there is enough space for the probe request,
1603 * two mandatory IEs and the data */
1604 left -= 24;
1605 if (left < 0)
1606 return 0;
1607 len += 24;
1608
1609 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1610 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1611 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1612 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY		 1613 frame->seq_ctrl = 0;
1614
1615 /* fill in our indirect SSID IE */
1616 /* ...next IE... */
1617
1618 left -= 2;
1619 if (left < 0)
1620 return 0;
1621 len += 2;
1622 pos = &(frame->u.probe_req.variable[0]);
1623 *pos++ = WLAN_EID_SSID;
1624 *pos++ = 0;
1625
1626 /* fill in our direct SSID IE... */
1627 if (is_direct) {
1628 /* ...next IE... */
1629 left -= 2 + priv->essid_len;
1630 if (left < 0)
1631 return 0;
1632 /* ... fill it in... */
1633 *pos++ = WLAN_EID_SSID;
1634 *pos++ = priv->essid_len;
1635 memcpy(pos, priv->essid, priv->essid_len);
1636 pos += priv->essid_len;
1637 len += 2 + priv->essid_len;
1638 }
1639
1640 /* fill in supported rate */
1641 /* ...next IE... */
1642 left -= 2;
1643 if (left < 0)
1644 return 0;
c7c46676 1645
b481de9c
ZY		 1646 /* ... fill it in... */
1647 *pos++ = WLAN_EID_SUPP_RATES;
1648 *pos = 0;
c7c46676
TW		 1649
1650 priv->active_rate = priv->rates_mask;
1651 active_rates = priv->active_rate;
b481de9c
ZY		 1652 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1653
c7c46676 1654 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1655 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW		 1656 priv->active_rate_basic, &left);
1657 active_rates &= ~ret_rates;
1658
bb8c093b 1659 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW		 1660 priv->active_rate_basic, &left);
1661 active_rates &= ~ret_rates;
1662
b481de9c
ZY		 1663 len += 2 + *pos;
1664 pos += (*pos) + 1;
c7c46676 1665 if (active_rates == 0)
b481de9c
ZY		 1666 goto fill_end;
1667
1668 /* fill in supported extended rate */
1669 /* ...next IE... */
1670 left -= 2;
1671 if (left < 0)
1672 return 0;
1673 /* ... fill it in... */
1674 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1675 *pos = 0;
bb8c093b 1676 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1677 priv->active_rate_basic, &left);
b481de9c
ZY		 1678 if (*pos > 0)
1679 len += 2 + *pos;
1680
1681 fill_end:
1682 return (u16)len;
1683}
1684
1685/*
1686 * QoS support
1687*/
bb8c093b
CH		 1688static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1689 struct iwl3945_qosparam_cmd *qos)
b481de9c
ZY		 1690{
1691
bb8c093b
CH		 1692 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1693 sizeof(struct iwl3945_qosparam_cmd), qos);
b481de9c
ZY		 1694}
1695
bb8c093b 1696static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY		 1697{
1698 u16 cw_min = 15;
1699 u16 cw_max = 1023;
1700 u8 aifs = 2;
1701 u8 is_legacy = 0;
1702 unsigned long flags;
1703 int i;
1704
1705 spin_lock_irqsave(&priv->lock, flags);
1706 priv->qos_data.qos_active = 0;
1707
05c914fe 1708 if (priv->iw_mode == NL80211_IFTYPE_ADHOC) {
b481de9c
ZY		 1709 if (priv->qos_data.qos_enable)
1710 priv->qos_data.qos_active = 1;
1711 if (!(priv->active_rate & 0xfff0)) {
1712 cw_min = 31;
1713 is_legacy = 1;
1714 }
05c914fe 1715 } else if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY		 1716 if (priv->qos_data.qos_enable)
1717 priv->qos_data.qos_active = 1;
1718 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1719 cw_min = 31;
1720 is_legacy = 1;
1721 }
1722
1723 if (priv->qos_data.qos_active)
1724 aifs = 3;
1725
1726 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1727 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1728 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1729 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1730 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1731
1732 if (priv->qos_data.qos_active) {
1733 i = 1;
1734 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1735 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1736 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1737 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1738 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1739
1740 i = 2;
1741 priv->qos_data.def_qos_parm.ac[i].cw_min =
1742 cpu_to_le16((cw_min + 1) / 2 - 1);
1743 priv->qos_data.def_qos_parm.ac[i].cw_max =
1744 cpu_to_le16(cw_max);
1745 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1746 if (is_legacy)
1747 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1748 cpu_to_le16(6016);
1749 else
1750 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1751 cpu_to_le16(3008);
1752 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1753
1754 i = 3;
1755 priv->qos_data.def_qos_parm.ac[i].cw_min =
1756 cpu_to_le16((cw_min + 1) / 4 - 1);
1757 priv->qos_data.def_qos_parm.ac[i].cw_max =
1758 cpu_to_le16((cw_max + 1) / 2 - 1);
1759 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1760 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1761 if (is_legacy)
1762 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1763 cpu_to_le16(3264);
1764 else
1765 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1766 cpu_to_le16(1504);
1767 } else {
1768 for (i = 1; i < 4; i++) {
1769 priv->qos_data.def_qos_parm.ac[i].cw_min =
1770 cpu_to_le16(cw_min);
1771 priv->qos_data.def_qos_parm.ac[i].cw_max =
1772 cpu_to_le16(cw_max);
1773 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1774 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1775 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1776 }
1777 }
1778 IWL_DEBUG_QOS("set QoS to default \n");
1779
1780 spin_unlock_irqrestore(&priv->lock, flags);
1781}
1782
bb8c093b 1783static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY		 1784{
1785 unsigned long flags;
1786
b481de9c
ZY		 1787 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1788 return;
1789
1790 if (!priv->qos_data.qos_enable)
1791 return;
1792
1793 spin_lock_irqsave(&priv->lock, flags);
1794 priv->qos_data.def_qos_parm.qos_flags = 0;
1795
1796 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1797 !priv->qos_data.qos_cap.q_AP.txop_request)
1798 priv->qos_data.def_qos_parm.qos_flags |=
1799 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1800
1801 if (priv->qos_data.qos_active)
1802 priv->qos_data.def_qos_parm.qos_flags |=
1803 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1804
1805 spin_unlock_irqrestore(&priv->lock, flags);
1806
bb8c093b 1807 if (force || iwl3945_is_associated(priv)) {
b481de9c
ZY		 1808 IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
1809 priv->qos_data.qos_active);
1810
bb8c093b 1811 iwl3945_send_qos_params_command(priv,
b481de9c
ZY		 1812 &(priv->qos_data.def_qos_parm));
1813 }
1814}
1815
b481de9c
ZY		 1816/*
1817 * Power management (not Tx power!) functions
1818 */
1819#define MSEC_TO_USEC 1024
1820
1821#define NOSLP __constant_cpu_to_le32(0)
1822#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
1823#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1824#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1825 __constant_cpu_to_le32(X1), \
1826 __constant_cpu_to_le32(X2), \
1827 __constant_cpu_to_le32(X3), \
1828 __constant_cpu_to_le32(X4)}
1829
1830
1831/* default power management (not Tx power) table values */
1832/* for tim 0-10 */
bb8c093b 1833static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY		 1834 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1835 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1836 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1837 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1838 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1839 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1840};
1841
1842/* for tim > 10 */
bb8c093b 1843static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY		 1844 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1845 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1846 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1847 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1848 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1849 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1850 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1851 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1852 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1853 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1854};
1855
bb8c093b 1856int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY		 1857{
1858 int rc = 0, i;
bb8c093b
CH		 1859 struct iwl3945_power_mgr *pow_data;
1860 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY		 1861 u16 pci_pm;
1862
1863 IWL_DEBUG_POWER("Initialize power \n");
1864
1865 pow_data = &(priv->power_data);
1866
1867 memset(pow_data, 0, sizeof(*pow_data));
1868
1869 pow_data->active_index = IWL_POWER_RANGE_0;
1870 pow_data->dtim_val = 0xffff;
1871
1872 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1873 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1874
1875 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1876 if (rc != 0)
1877 return 0;
1878 else {
bb8c093b 1879 struct iwl3945_powertable_cmd *cmd;
b481de9c
ZY		 1880
1881 IWL_DEBUG_POWER("adjust power command flags\n");
1882
1883 for (i = 0; i < IWL_POWER_AC; i++) {
1884 cmd = &pow_data->pwr_range_0[i].cmd;
1885
1886 if (pci_pm & 0x1)
1887 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1888 else
1889 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1890 }
1891 }
1892 return rc;
1893}
1894
bb8c093b
CH		 1895static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
1896 struct iwl3945_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 1897{
1898 int rc = 0, i;
1899 u8 skip;
1900 u32 max_sleep = 0;
bb8c093b 1901 struct iwl3945_power_vec_entry *range;
b481de9c 1902 u8 period = 0;
bb8c093b 1903 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY		 1904
1905 if (mode > IWL_POWER_INDEX_5) {
1906 IWL_DEBUG_POWER("Error invalid power mode \n");
1907 return -1;
1908 }
1909 pow_data = &(priv->power_data);
1910
1911 if (pow_data->active_index == IWL_POWER_RANGE_0)
1912 range = &pow_data->pwr_range_0[0];
1913 else
1914 range = &pow_data->pwr_range_1[1];
1915
bb8c093b 1916 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY		 1917
1918#ifdef IWL_MAC80211_DISABLE
1919 if (priv->assoc_network != NULL) {
1920 unsigned long flags;
1921
1922 period = priv->assoc_network->tim.tim_period;
1923 }
1924#endif /*IWL_MAC80211_DISABLE */
1925 skip = range[mode].no_dtim;
1926
1927 if (period == 0) {
1928 period = 1;
1929 skip = 0;
1930 }
1931
1932 if (skip == 0) {
1933 max_sleep = period;
1934 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1935 } else {
1936 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1937 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1938 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1939 }
1940
1941 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1942 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1943 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1944 }
1945
1946 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1947 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1948 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1949 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1950 le32_to_cpu(cmd->sleep_interval[0]),
1951 le32_to_cpu(cmd->sleep_interval[1]),
1952 le32_to_cpu(cmd->sleep_interval[2]),
1953 le32_to_cpu(cmd->sleep_interval[3]),
1954 le32_to_cpu(cmd->sleep_interval[4]));
1955
1956 return rc;
1957}
1958
bb8c093b 1959static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 1960{
9a62f73b 1961 u32 uninitialized_var(final_mode);
b481de9c 1962 int rc;
bb8c093b 1963 struct iwl3945_powertable_cmd cmd;
b481de9c
ZY		 1964
1965 /* If on battery, set to 3,
01ebd063 1966 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 1967 * else user level */
1968 switch (mode) {
1969 case IWL_POWER_BATTERY:
1970 final_mode = IWL_POWER_INDEX_3;
1971 break;
1972 case IWL_POWER_AC:
1973 final_mode = IWL_POWER_MODE_CAM;
1974 break;
1975 default:
1976 final_mode = mode;
1977 break;
1978 }
1979
bb8c093b 1980 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 1981
bb8c093b 1982 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 1983
1984 if (final_mode == IWL_POWER_MODE_CAM)
1985 clear_bit(STATUS_POWER_PMI, &priv->status);
1986 else
1987 set_bit(STATUS_POWER_PMI, &priv->status);
1988
1989 return rc;
1990}
1991
b481de9c 1992/**
bb8c093b 1993 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 1994 *
1995 * NOTE: priv->mutex is not required before calling this function
1996 */
bb8c093b 1997static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY		 1998{
1999 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2000 clear_bit(STATUS_SCANNING, &priv->status);
2001 return 0;
2002 }
2003
2004 if (test_bit(STATUS_SCANNING, &priv->status)) {
2005 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2006 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2007 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2008 queue_work(priv->workqueue, &priv->abort_scan);
2009
2010 } else
2011 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2012
2013 return test_bit(STATUS_SCANNING, &priv->status);
2014 }
2015
2016 return 0;
2017}
2018
2019/**
bb8c093b 2020 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 2021 * @ms: amount of time to wait (in milliseconds) for scan to abort
2022 *
2023 * NOTE: priv->mutex must be held before calling this function
2024 */
bb8c093b 2025static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY		 2026{
2027 unsigned long now = jiffies;
2028 int ret;
2029
bb8c093b 2030 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY		 2031 if (ret && ms) {
2032 mutex_unlock(&priv->mutex);
2033 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2034 test_bit(STATUS_SCANNING, &priv->status))
2035 msleep(1);
2036 mutex_lock(&priv->mutex);
2037
2038 return test_bit(STATUS_SCANNING, &priv->status);
2039 }
2040
2041 return ret;
2042}
2043
b481de9c
ZY		 2044#define MAX_UCODE_BEACON_INTERVAL 1024
2045#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2046
bb8c093b 2047static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 2048{
2049 u16 new_val = 0;
2050 u16 beacon_factor = 0;
2051
2052 beacon_factor =
2053 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2054 / MAX_UCODE_BEACON_INTERVAL;
2055 new_val = beacon_val / beacon_factor;
2056
2057 return cpu_to_le16(new_val);
2058}
2059
bb8c093b 2060static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY		 2061{
2062 u64 interval_tm_unit;
2063 u64 tsf, result;
2064 unsigned long flags;
2065 struct ieee80211_conf *conf = NULL;
2066 u16 beacon_int = 0;
2067
2068 conf = ieee80211_get_hw_conf(priv->hw);
2069
2070 spin_lock_irqsave(&priv->lock, flags);
2071 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2072 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2073
2074 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2075
2076 tsf = priv->timestamp1;
2077 tsf = ((tsf << 32) | priv->timestamp0);
2078
2079 beacon_int = priv->beacon_int;
2080 spin_unlock_irqrestore(&priv->lock, flags);
2081
05c914fe 2082 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
b481de9c
ZY		 2083 if (beacon_int == 0) {
2084 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2085 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2086 } else {
2087 priv->rxon_timing.beacon_interval =
2088 cpu_to_le16(beacon_int);
2089 priv->rxon_timing.beacon_interval =
bb8c093b 2090 iwl3945_adjust_beacon_interval(
b481de9c
ZY		 2091 le16_to_cpu(priv->rxon_timing.beacon_interval));
2092 }
2093
2094 priv->rxon_timing.atim_window = 0;
2095 } else {
2096 priv->rxon_timing.beacon_interval =
bb8c093b 2097 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 2098 /* TODO: we need to get atim_window from upper stack
2099 * for now we set to 0 */
2100 priv->rxon_timing.atim_window = 0;
2101 }
2102
2103 interval_tm_unit =
2104 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2105 result = do_div(tsf, interval_tm_unit);
2106 priv->rxon_timing.beacon_init_val =
2107 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2108
2109 IWL_DEBUG_ASSOC
2110 ("beacon interval %d beacon timer %d beacon tim %d\n",
2111 le16_to_cpu(priv->rxon_timing.beacon_interval),
2112 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2113 le16_to_cpu(priv->rxon_timing.atim_window));
2114}
2115
bb8c093b 2116static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c 2117{
05c914fe 2118 if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY		 2119 IWL_ERROR("APs don't scan.\n");
2120 return 0;
2121 }
2122
bb8c093b 2123 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 2124 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2125 return -EIO;
2126 }
2127
2128 if (test_bit(STATUS_SCANNING, &priv->status)) {
2129 IWL_DEBUG_SCAN("Scan already in progress.\n");
2130 return -EAGAIN;
2131 }
2132
2133 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2134 IWL_DEBUG_SCAN("Scan request while abort pending. "
2135 "Queuing.\n");
2136 return -EAGAIN;
2137 }
2138
2139 IWL_DEBUG_INFO("Starting scan...\n");
66b5004d
RR		 2140 if (priv->cfg->sku & IWL_SKU_G)
2141 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
2142 if (priv->cfg->sku & IWL_SKU_A)
2143 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 2144 set_bit(STATUS_SCANNING, &priv->status);
2145 priv->scan_start = jiffies;
2146 priv->scan_pass_start = priv->scan_start;
2147
2148 queue_work(priv->workqueue, &priv->request_scan);
2149
2150 return 0;
2151}
2152
bb8c093b 2153static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2154{
bb8c093b 2155 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 2156
2157 if (hw_decrypt)
2158 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2159 else
2160 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2161
2162 return 0;
2163}
2164
8318d78a
JB		 2165static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2166 enum ieee80211_band band)
b481de9c 2167{
8318d78a 2168 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY		 2169 priv->staging_rxon.flags &=
2170 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2171 | RXON_FLG_CCK_MSK);
2172 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2173 } else {
bb8c093b 2174 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY		 2175 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2176 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2177 else
2178 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2179
05c914fe 2180 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 2181 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2182
2183 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2184 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2185 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2186 }
2187}
2188
2189/*
01ebd063 2190 * initialize rxon structure with default values from eeprom
b481de9c 2191 */
bb8c093b 2192static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
b481de9c 2193{
bb8c093b 2194 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 2195
2196 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2197
2198 switch (priv->iw_mode) {
05c914fe 2199 case NL80211_IFTYPE_AP:
b481de9c
ZY		 2200 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2201 break;
2202
05c914fe 2203 case NL80211_IFTYPE_STATION:
b481de9c
ZY		 2204 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2205 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2206 break;
2207
05c914fe 2208 case NL80211_IFTYPE_ADHOC:
b481de9c
ZY		 2209 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2210 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2211 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2212 RXON_FILTER_ACCEPT_GRP_MSK;
2213 break;
2214
05c914fe 2215 case NL80211_IFTYPE_MONITOR:
b481de9c
ZY		 2216 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2217 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2218 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2219 break;
69dc5d9d
TW		 2220 default:
2221 IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
2222 break;
b481de9c
ZY		 2223 }
2224
2225#if 0
2226 /* TODO: Figure out when short_preamble would be set and cache from
2227 * that */
2228 if (!hw_to_local(priv->hw)->short_preamble)
2229 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2230 else
2231 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2232#endif
2233
8318d78a 2234 ch_info = iwl3945_get_channel_info(priv, priv->band,
25b3f57c 2235 le16_to_cpu(priv->active_rxon.channel));
b481de9c
ZY		 2236
2237 if (!ch_info)
2238 ch_info = &priv->channel_info[0];
2239
2240 /*
2241 * in some case A channels are all non IBSS
2242 * in this case force B/G channel
2243 */
05c914fe 2244 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
b481de9c
ZY		 2245 !(is_channel_ibss(ch_info)))
2246 ch_info = &priv->channel_info[0];
2247
2248 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2249 if (is_channel_a_band(ch_info))
8318d78a 2250 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 2251 else
8318d78a 2252 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 2253
8318d78a 2254 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY		 2255
2256 priv->staging_rxon.ofdm_basic_rates =
2257 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2258 priv->staging_rxon.cck_basic_rates =
2259 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2260}
2261
bb8c093b 2262static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2263{
05c914fe 2264 if (mode == NL80211_IFTYPE_ADHOC) {
bb8c093b 2265 const struct iwl3945_channel_info *ch_info;
b481de9c 2266
bb8c093b 2267 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2268 priv->band,
b481de9c
ZY		 2269 le16_to_cpu(priv->staging_rxon.channel));
2270
2271 if (!ch_info || !is_channel_ibss(ch_info)) {
2272 IWL_ERROR("channel %d not IBSS channel\n",
2273 le16_to_cpu(priv->staging_rxon.channel));
2274 return -EINVAL;
2275 }
2276 }
2277
b481de9c
ZY		 2278 priv->iw_mode = mode;
2279
bb8c093b 2280 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 2281 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2282
bb8c093b 2283 iwl3945_clear_stations_table(priv);
b481de9c 2284
fde3571f
MA		 2285 /* dont commit rxon if rf-kill is on*/
2286 if (!iwl3945_is_ready_rf(priv))
2287 return -EAGAIN;
2288
2289 cancel_delayed_work(&priv->scan_check);
2290 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2291 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2292 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2293 return -EAGAIN;
2294 }
2295
bb8c093b 2296 iwl3945_commit_rxon(priv);
b481de9c
ZY		 2297
2298 return 0;
2299}
2300
bb8c093b 2301static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
e039fa4a 2302 struct ieee80211_tx_info *info,
bb8c093b 2303 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2304 struct sk_buff *skb_frag,
2305 int last_frag)
2306{
1c014420 2307 struct iwl3945_hw_key *keyinfo =
e039fa4a 2308 &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
b481de9c
ZY		 2309
2310 switch (keyinfo->alg) {
2311 case ALG_CCMP:
2312 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2313 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2314 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2315 break;
2316
2317 case ALG_TKIP:
2318#if 0
2319 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2320
2321 if (last_frag)
2322 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2323 8);
2324 else
2325 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2326#endif
2327 break;
2328
2329 case ALG_WEP:
2330 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 2331 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY		 2332
2333 if (keyinfo->keylen == 13)
2334 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2335
2336 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2337
2338 IWL_DEBUG_TX("Configuring packet for WEP encryption "
e039fa4a 2339 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY		 2340 break;
2341
b481de9c
ZY		 2342 default:
2343 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2344 break;
2345 }
2346}
2347
2348/*
2349 * handle build REPLY_TX command notification.
2350 */
bb8c093b
CH		 2351static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2352 struct iwl3945_cmd *cmd,
e039fa4a 2353 struct ieee80211_tx_info *info,
b481de9c
ZY		 2354 struct ieee80211_hdr *hdr,
2355 int is_unicast, u8 std_id)
2356{
fd7c8a40 2357 __le16 fc = hdr->frame_control;
b481de9c 2358 __le32 tx_flags = cmd->cmd.tx.tx_flags;
e6a9854b 2359 u8 rc_flags = info->control.rates[0].flags;
b481de9c
ZY		 2360
2361 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 2362 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 2363 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 2364 if (ieee80211_is_mgmt(fc))
b481de9c 2365 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 2366 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY		 2367 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2368 tx_flags |= TX_CMD_FLG_TSF_MSK;
2369 } else {
2370 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2371 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2372 }
2373
2374 cmd->cmd.tx.sta_id = std_id;
8b7b1e05 2375 if (ieee80211_has_morefrags(fc))
b481de9c
ZY		 2376 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2377
fd7c8a40
HH		 2378 if (ieee80211_is_data_qos(fc)) {
2379 u8 *qc = ieee80211_get_qos_ctl(hdr);
54dbb525 2380 cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
b481de9c 2381 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2382 } else {
b481de9c 2383 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2384 }
b481de9c 2385
e6a9854b 2386 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
b481de9c
ZY		 2387 tx_flags |= TX_CMD_FLG_RTS_MSK;
2388 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 2389 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
b481de9c
ZY		 2390 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2391 tx_flags |= TX_CMD_FLG_CTS_MSK;
2392 }
2393
2394 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2395 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2396
2397 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH		 2398 if (ieee80211_is_mgmt(fc)) {
2399 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
bc434dd2 2400 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2401 else
bc434dd2 2402 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2403 } else {
b481de9c 2404 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
ab53d8af
MA		 2405#ifdef CONFIG_IWL3945_LEDS
2406 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2407#endif
2408 }
b481de9c
ZY		 2409
2410 cmd->cmd.tx.driver_txop = 0;
2411 cmd->cmd.tx.tx_flags = tx_flags;
2412 cmd->cmd.tx.next_frame_len = 0;
2413}
2414
6440adb5
CB		 2415/**
2416 * iwl3945_get_sta_id - Find station's index within station table
2417 */
bb8c093b 2418static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY		 2419{
2420 int sta_id;
2421 u16 fc = le16_to_cpu(hdr->frame_control);
2422
6440adb5 2423 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2424 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2425 is_multicast_ether_addr(hdr->addr1))
2426 return priv->hw_setting.bcast_sta_id;
2427
2428 switch (priv->iw_mode) {
2429
6440adb5
CB		 2430 /* If we are a client station in a BSS network, use the special
2431 * AP station entry (that's the only station we communicate with) */
05c914fe 2432 case NL80211_IFTYPE_STATION:
b481de9c
ZY		 2433 return IWL_AP_ID;
2434
2435 /* If we are an AP, then find the station, or use BCAST */
05c914fe 2436 case NL80211_IFTYPE_AP:
bb8c093b 2437 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2438 if (sta_id != IWL_INVALID_STATION)
2439 return sta_id;
2440 return priv->hw_setting.bcast_sta_id;
2441
6440adb5
CB		 2442 /* If this frame is going out to an IBSS network, find the station,
2443 * or create a new station table entry */
05c914fe 2444 case NL80211_IFTYPE_ADHOC: {
6440adb5 2445 /* Create new station table entry */
bb8c093b 2446 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2447 if (sta_id != IWL_INVALID_STATION)
2448 return sta_id;
2449
bb8c093b 2450 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY		 2451
2452 if (sta_id != IWL_INVALID_STATION)
2453 return sta_id;
2454
e174961c 2455 IWL_DEBUG_DROP("Station %pM not in station map. "
b481de9c 2456 "Defaulting to broadcast...\n",
e174961c 2457 hdr->addr1);
bb8c093b 2458 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2459 return priv->hw_setting.bcast_sta_id;
0795af57 2460 }
914233d6
SG		 2461 /* If we are in monitor mode, use BCAST. This is required for
2462 * packet injection. */
05c914fe 2463 case NL80211_IFTYPE_MONITOR:
914233d6
SG		 2464 return priv->hw_setting.bcast_sta_id;
2465
b481de9c 2466 default:
6f147926 2467 IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
b481de9c
ZY		 2468 return priv->hw_setting.bcast_sta_id;
2469 }
2470}
2471
2472/*
2473 * start REPLY_TX command process
2474 */
e039fa4a 2475static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
b481de9c
ZY		 2476{
2477 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 2478 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bb8c093b 2479 struct iwl3945_tfd_frame *tfd;
b481de9c 2480 u32 *control_flags;
e2530083 2481 int txq_id = skb_get_queue_mapping(skb);
bb8c093b
CH		 2482 struct iwl3945_tx_queue *txq = NULL;
2483 struct iwl3945_queue *q = NULL;
b481de9c
ZY		 2484 dma_addr_t phys_addr;
2485 dma_addr_t txcmd_phys;
bb8c093b 2486 struct iwl3945_cmd *out_cmd = NULL;
54dbb525
TW		 2487 u16 len, idx, len_org, hdr_len;
2488 u8 id;
2489 u8 unicast;
b481de9c 2490 u8 sta_id;
54dbb525 2491 u8 tid = 0;
b481de9c 2492 u16 seq_number = 0;
fd7c8a40 2493 __le16 fc;
b481de9c 2494 u8 wait_write_ptr = 0;
54dbb525 2495 u8 *qc = NULL;
b481de9c
ZY		 2496 unsigned long flags;
2497 int rc;
2498
2499 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2500 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 2501 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2502 goto drop_unlock;
2503 }
2504
e039fa4a 2505 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY		 2506 IWL_ERROR("ERROR: No TX rate available.\n");
2507 goto drop_unlock;
2508 }
2509
2510 unicast = !is_multicast_ether_addr(hdr->addr1);
2511 id = 0;
2512
fd7c8a40 2513 fc = hdr->frame_control;
b481de9c 2514
c8b0e6e1 2515#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 2516 if (ieee80211_is_auth(fc))
2517 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 2518 else if (ieee80211_is_assoc_req(fc))
b481de9c 2519 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 2520 else if (ieee80211_is_reassoc_req(fc))
b481de9c
ZY		 2521 IWL_DEBUG_TX("Sending REASSOC frame\n");
2522#endif
2523
7878a5a4 2524 /* drop all data frame if we are not associated */
914233d6 2525 if (ieee80211_is_data(fc) &&
05c914fe 2526 (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
914233d6 2527 (!iwl3945_is_associated(priv) ||
05c914fe 2528 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
bb8c093b 2529 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY		 2530 goto drop_unlock;
2531 }
2532
2533 spin_unlock_irqrestore(&priv->lock, flags);
2534
7294ec95 2535 hdr_len = ieee80211_hdrlen(fc);
6440adb5
CB		 2536
2537 /* Find (or create) index into station table for destination station */
bb8c093b 2538 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2539 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 2540 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
2541 hdr->addr1);
b481de9c
ZY		 2542 goto drop;
2543 }
2544
2545 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2546
fd7c8a40
HH		 2547 if (ieee80211_is_data_qos(fc)) {
2548 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 2549 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
b481de9c
ZY		 2550 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2551 IEEE80211_SCTL_SEQ;
2552 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2553 (hdr->seq_ctrl &
2554 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2555 seq_number += 0x10;
2556 }
6440adb5
CB		 2557
2558 /* Descriptor for chosen Tx queue */
b481de9c
ZY		 2559 txq = &priv->txq[txq_id];
2560 q = &txq->q;
2561
2562 spin_lock_irqsave(&priv->lock, flags);
2563
6440adb5 2564 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2565 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 2566 memset(tfd, 0, sizeof(*tfd));
2567 control_flags = (u32 *) tfd;
fc4b6853 2568 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2569
6440adb5 2570 /* Set up driver data for this TFD */
bb8c093b 2571 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853 2572 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB		 2573
2574 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY		 2575 out_cmd = &txq->cmd[idx];
2576 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2577 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB		 2578
2579 /*
2580 * Set up the Tx-command (not MAC!) header.
2581 * Store the chosen Tx queue and TFD index within the sequence field;
2582 * after Tx, uCode's Tx response will return this value so driver can
2583 * locate the frame within the tx queue and do post-tx processing.
2584 */
b481de9c
ZY		 2585 out_cmd->hdr.cmd = REPLY_TX;
2586 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2587 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB		 2588
2589 /* Copy MAC header from skb into command buffer */
b481de9c
ZY		 2590 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2591
6440adb5
CB		 2592 /*
2593 * Use the first empty entry in this queue's command buffer array
2594 * to contain the Tx command and MAC header concatenated together
2595 * (payload data will be in another buffer).
2596 * Size of this varies, due to varying MAC header length.
2597 * If end is not dword aligned, we'll have 2 extra bytes at the end
2598 * of the MAC header (device reads on dword boundaries).
2599 * We'll tell device about this padding later.
2600 */
b481de9c 2601 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2602 sizeof(struct iwl3945_cmd_header) + hdr_len;
b481de9c
ZY		 2603
2604 len_org = len;
2605 len = (len + 3) & ~3;
2606
2607 if (len_org != len)
2608 len_org = 1;
2609 else
2610 len_org = 0;
2611
6440adb5
CB		 2612 /* Physical address of this Tx command's header (not MAC header!),
2613 * within command buffer array. */
bb8c093b
CH		 2614 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2615 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2616
6440adb5
CB		 2617 /* Add buffer containing Tx command and MAC(!) header to TFD's
2618 * first entry */
bb8c093b 2619 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c 2620
d0f09804 2621 if (info->control.hw_key)
e039fa4a 2622 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
b481de9c 2623
6440adb5
CB		 2624 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2625 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 2626 len = skb->len - hdr_len;
2627 if (len) {
2628 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2629 len, PCI_DMA_TODEVICE);
bb8c093b 2630 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 2631 }
2632
b481de9c 2633 if (!len)
6440adb5 2634 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY		 2635 *control_flags = TFD_CTL_COUNT_SET(1);
2636 else
6440adb5
CB		 2637 /* Else use 2 buffers.
2638 * Tell 3945 about any padding after MAC header */
b481de9c
ZY		 2639 *control_flags = TFD_CTL_COUNT_SET(2) |
2640 TFD_CTL_PAD_SET(U32_PAD(len));
2641
6440adb5 2642 /* Total # bytes to be transmitted */
b481de9c
ZY		 2643 len = (u16)skb->len;
2644 out_cmd->cmd.tx.len = cpu_to_le16(len);
2645
2646 /* TODO need this for burst mode later on */
e039fa4a 2647 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
b481de9c
ZY		 2648
2649 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 2650 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
b481de9c
ZY		 2651
2652 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2653 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2654
8b7b1e05 2655 if (!ieee80211_has_morefrags(hdr->frame_control)) {
b481de9c 2656 txq->need_update = 1;
3ac7f146 2657 if (qc)
b481de9c 2658 priv->stations[sta_id].tid[tid].seq_number = seq_number;
b481de9c
ZY		 2659 } else {
2660 wait_write_ptr = 1;
2661 txq->need_update = 0;
2662 }
2663
bb8c093b 2664 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY		 2665 sizeof(out_cmd->cmd.tx));
2666
bb8c093b 2667 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
7294ec95 2668 ieee80211_hdrlen(fc));
b481de9c 2669
6440adb5 2670 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2671 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2672 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2673 spin_unlock_irqrestore(&priv->lock, flags);
2674
2675 if (rc)
2676 return rc;
2677
bb8c093b 2678 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY		 2679 && priv->mac80211_registered) {
2680 if (wait_write_ptr) {
2681 spin_lock_irqsave(&priv->lock, flags);
2682 txq->need_update = 1;
bb8c093b 2683 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2684 spin_unlock_irqrestore(&priv->lock, flags);
2685 }
2686
e2530083 2687 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
b481de9c
ZY		 2688 }
2689
2690 return 0;
2691
2692drop_unlock:
2693 spin_unlock_irqrestore(&priv->lock, flags);
2694drop:
2695 return -1;
2696}
2697
bb8c093b 2698static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c 2699{
8318d78a 2700 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY		 2701 struct ieee80211_rate *rate;
2702 int i;
2703
8318d78a
JB		 2704 sband = iwl3945_get_band(priv, priv->band);
2705 if (!sband) {
c4ba9621
SA		 2706 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2707 return;
2708 }
b481de9c
ZY		 2709
2710 priv->active_rate = 0;
2711 priv->active_rate_basic = 0;
2712
8318d78a
JB		 2713 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2714 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2715
2716 for (i = 0; i < sband->n_bitrates; i++) {
2717 rate = &sband->bitrates[i];
2718 if ((rate->hw_value < IWL_RATE_COUNT) &&
2719 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2720 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2721 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2722 priv->active_rate |= (1 << rate->hw_value);
2723 }
b481de9c
ZY		 2724 }
2725
2726 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2727 priv->active_rate, priv->active_rate_basic);
2728
2729 /*
2730 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2731 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2732 * OFDM
2733 */
2734 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2735 priv->staging_rxon.cck_basic_rates =
2736 ((priv->active_rate_basic &
2737 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2738 else
2739 priv->staging_rxon.cck_basic_rates =
2740 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2741
2742 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2743 priv->staging_rxon.ofdm_basic_rates =
2744 ((priv->active_rate_basic &
2745 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2746 IWL_FIRST_OFDM_RATE) & 0xFF;
2747 else
2748 priv->staging_rxon.ofdm_basic_rates =
2749 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2750}
2751
bb8c093b 2752static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY		 2753{
2754 unsigned long flags;
2755
2756 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2757 return;
2758
2759 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2760 disable_radio ? "OFF" : "ON");
2761
2762 if (disable_radio) {
bb8c093b 2763 iwl3945_scan_cancel(priv);
b481de9c 2764 /* FIXME: This is a workaround for AP */
05c914fe 2765 if (priv->iw_mode != NL80211_IFTYPE_AP) {
b481de9c 2766 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2767 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 2768 CSR_UCODE_SW_BIT_RFKILL);
2769 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 2770 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY		 2771 set_bit(STATUS_RF_KILL_SW, &priv->status);
2772 }
2773 return;
2774 }
2775
2776 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2777 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2778
2779 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2780 spin_unlock_irqrestore(&priv->lock, flags);
2781
2782 /* wake up ucode */
2783 msleep(10);
2784
2785 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 2786 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
2787 if (!iwl3945_grab_nic_access(priv))
2788 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2789 spin_unlock_irqrestore(&priv->lock, flags);
2790
2791 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2792 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2793 "disabled by HW switch\n");
2794 return;
2795 }
2796
808e72a0
ZY		 2797 if (priv->is_open)
2798 queue_work(priv->workqueue, &priv->restart);
b481de9c
ZY		 2799 return;
2800}
2801
bb8c093b 2802void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 2803 u32 decrypt_res, struct ieee80211_rx_status *stats)
2804{
2805 u16 fc =
2806 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2807
2808 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2809 return;
2810
2811 if (!(fc & IEEE80211_FCTL_PROTECTED))
2812 return;
2813
2814 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2815 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2816 case RX_RES_STATUS_SEC_TYPE_TKIP:
2817 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2818 RX_RES_STATUS_BAD_ICV_MIC)
2819 stats->flag |= RX_FLAG_MMIC_ERROR;
2820 case RX_RES_STATUS_SEC_TYPE_WEP:
2821 case RX_RES_STATUS_SEC_TYPE_CCMP:
2822 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2823 RX_RES_STATUS_DECRYPT_OK) {
2824 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2825 stats->flag |= RX_FLAG_DECRYPTED;
2826 }
2827 break;
2828
2829 default:
2830 break;
2831 }
2832}
2833
c8b0e6e1 2834#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 2835
2836#include "iwl-spectrum.h"
2837
2838#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2839#define BEACON_TIME_MASK_HIGH 0xFF000000
2840#define TIME_UNIT 1024
2841
2842/*
2843 * extended beacon time format
2844 * time in usec will be changed into a 32-bit value in 8:24 format
2845 * the high 1 byte is the beacon counts
2846 * the lower 3 bytes is the time in usec within one beacon interval
2847 */
2848
bb8c093b 2849static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 2850{
2851 u32 quot;
2852 u32 rem;
2853 u32 interval = beacon_interval * 1024;
2854
2855 if (!interval || !usec)
2856 return 0;
2857
2858 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
2859 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
2860
2861 return (quot << 24) + rem;
2862}
2863
2864/* base is usually what we get from ucode with each received frame,
2865 * the same as HW timer counter counting down
2866 */
2867
bb8c093b 2868static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 2869{
2870 u32 base_low = base & BEACON_TIME_MASK_LOW;
2871 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
2872 u32 interval = beacon_interval * TIME_UNIT;
2873 u32 res = (base & BEACON_TIME_MASK_HIGH) +
2874 (addon & BEACON_TIME_MASK_HIGH);
2875
2876 if (base_low > addon_low)
2877 res += base_low - addon_low;
2878 else if (base_low < addon_low) {
2879 res += interval + base_low - addon_low;
2880 res += (1 << 24);
2881 } else
2882 res += (1 << 24);
2883
2884 return cpu_to_le32(res);
2885}
2886
bb8c093b 2887static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY		 2888 struct ieee80211_measurement_params *params,
2889 u8 type)
2890{
bb8c093b
CH		 2891 struct iwl3945_spectrum_cmd spectrum;
2892 struct iwl3945_rx_packet *res;
2893 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 2894 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
2895 .data = (void *)&spectrum,
2896 .meta.flags = CMD_WANT_SKB,
2897 };
2898 u32 add_time = le64_to_cpu(params->start_time);
2899 int rc;
2900 int spectrum_resp_status;
2901 int duration = le16_to_cpu(params->duration);
2902
bb8c093b 2903 if (iwl3945_is_associated(priv))
b481de9c 2904 add_time =
bb8c093b 2905 iwl3945_usecs_to_beacons(
b481de9c
ZY		 2906 le64_to_cpu(params->start_time) - priv->last_tsf,
2907 le16_to_cpu(priv->rxon_timing.beacon_interval));
2908
2909 memset(&spectrum, 0, sizeof(spectrum));
2910
2911 spectrum.channel_count = cpu_to_le16(1);
2912 spectrum.flags =
2913 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
2914 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
2915 cmd.len = sizeof(spectrum);
2916 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
2917
bb8c093b 2918 if (iwl3945_is_associated(priv))
b481de9c 2919 spectrum.start_time =
bb8c093b 2920 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 2921 add_time,
2922 le16_to_cpu(priv->rxon_timing.beacon_interval));
2923 else
2924 spectrum.start_time = 0;
2925
2926 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
2927 spectrum.channels[0].channel = params->channel;
2928 spectrum.channels[0].type = type;
2929 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
2930 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
2931 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
2932
bb8c093b 2933 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 2934 if (rc)
2935 return rc;
2936
bb8c093b 2937 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 2938 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
2939 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
2940 rc = -EIO;
2941 }
2942
2943 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
2944 switch (spectrum_resp_status) {
2945 case 0: /* Command will be handled */
2946 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS		 2947 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
2948 res->u.spectrum.id);
b481de9c
ZY		 2949 priv->measurement_status &= ~MEASUREMENT_READY;
2950 }
2951 priv->measurement_status |= MEASUREMENT_ACTIVE;
2952 rc = 0;
2953 break;
2954
2955 case 1: /* Command will not be handled */
2956 rc = -EAGAIN;
2957 break;
2958 }
2959
2960 dev_kfree_skb_any(cmd.meta.u.skb);
2961
2962 return rc;
2963}
2964#endif
2965
bb8c093b
CH		 2966static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
2967 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 2968{
bb8c093b
CH		 2969 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
2970 struct iwl3945_alive_resp *palive;
b481de9c
ZY		 2971 struct delayed_work *pwork;
2972
2973 palive = &pkt->u.alive_frame;
2974
2975 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
2976 "0x%01X 0x%01X\n",
2977 palive->is_valid, palive->ver_type,
2978 palive->ver_subtype);
2979
2980 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
2981 IWL_DEBUG_INFO("Initialization Alive received.\n");
2982 memcpy(&priv->card_alive_init,
2983 &pkt->u.alive_frame,
bb8c093b 2984 sizeof(struct iwl3945_init_alive_resp));
b481de9c
ZY		 2985 pwork = &priv->init_alive_start;
2986 } else {
2987 IWL_DEBUG_INFO("Runtime Alive received.\n");
2988 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 2989 sizeof(struct iwl3945_alive_resp));
b481de9c 2990 pwork = &priv->alive_start;
bb8c093b 2991 iwl3945_disable_events(priv);
b481de9c
ZY		 2992 }
2993
2994 /* We delay the ALIVE response by 5ms to
2995 * give the HW RF Kill time to activate... */
2996 if (palive->is_valid == UCODE_VALID_OK)
2997 queue_delayed_work(priv->workqueue, pwork,
2998 msecs_to_jiffies(5));
2999 else
3000 IWL_WARNING("uCode did not respond OK.\n");
3001}
3002
bb8c093b
CH		 3003static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
3004 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3005{
bb8c093b 3006 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3007
3008 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3009 return;
3010}
3011
bb8c093b
CH		 3012static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
3013 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3014{
bb8c093b 3015 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3016
3017 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3018 "seq 0x%04X ser 0x%08X\n",
3019 le32_to_cpu(pkt->u.err_resp.error_type),
3020 get_cmd_string(pkt->u.err_resp.cmd_id),
3021 pkt->u.err_resp.cmd_id,
3022 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3023 le32_to_cpu(pkt->u.err_resp.error_info));
3024}
3025
3026#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3027
bb8c093b 3028static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3029{
bb8c093b
CH		 3030 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3031 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3032 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 3033 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3034 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3035 rxon->channel = csa->channel;
3036 priv->staging_rxon.channel = csa->channel;
3037}
3038
bb8c093b
CH		 3039static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3040 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3041{
c8b0e6e1 3042#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
bb8c093b
CH		 3043 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3044 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 3045
3046 if (!report->state) {
3047 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3048 "Spectrum Measure Notification: Start\n");
3049 return;
3050 }
3051
3052 memcpy(&priv->measure_report, report, sizeof(*report));
3053 priv->measurement_status |= MEASUREMENT_READY;
3054#endif
3055}
3056
bb8c093b
CH		 3057static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3058 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3059{
c8b0e6e1 3060#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3061 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3062 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 3063 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3064 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3065#endif
3066}
3067
bb8c093b
CH		 3068static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3069 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3070{
bb8c093b 3071 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3072 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3073 "notification for %s:\n",
3074 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3075 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 3076}
3077
bb8c093b 3078static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3079{
bb8c093b
CH		 3080 struct iwl3945_priv *priv =
3081 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY		 3082 struct sk_buff *beacon;
3083
3084 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 3085 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 3086
3087 if (!beacon) {
3088 IWL_ERROR("update beacon failed\n");
3089 return;
3090 }
3091
3092 mutex_lock(&priv->mutex);
3093 /* new beacon skb is allocated every time; dispose previous.*/
3094 if (priv->ibss_beacon)
3095 dev_kfree_skb(priv->ibss_beacon);
3096
3097 priv->ibss_beacon = beacon;
3098 mutex_unlock(&priv->mutex);
3099
bb8c093b 3100 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 3101}
3102
bb8c093b
CH		 3103static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3104 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3105{
c8b0e6e1 3106#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3107 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3108 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY		 3109 u8 rate = beacon->beacon_notify_hdr.rate;
3110
3111 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3112 "tsf %d %d rate %d\n",
3113 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3114 beacon->beacon_notify_hdr.failure_frame,
3115 le32_to_cpu(beacon->ibss_mgr_status),
3116 le32_to_cpu(beacon->high_tsf),
3117 le32_to_cpu(beacon->low_tsf), rate);
3118#endif
3119
05c914fe 3120 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY		 3121 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3122 queue_work(priv->workqueue, &priv->beacon_update);
3123}
3124
3125/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH		 3126static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3127 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3128{
c8b0e6e1 3129#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3130 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3131 struct iwl3945_scanreq_notification *notif =
3132 (struct iwl3945_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 3133
3134 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3135#endif
3136}
3137
3138/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH		 3139static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3140 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3141{
bb8c093b
CH		 3142 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3143 struct iwl3945_scanstart_notification *notif =
3144 (struct iwl3945_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 3145 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3146 IWL_DEBUG_SCAN("Scan start: "
3147 "%d [802.11%s] "
3148 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3149 notif->channel,
3150 notif->band ? "bg" : "a",
3151 notif->tsf_high,
3152 notif->tsf_low, notif->status, notif->beacon_timer);
3153}
3154
3155/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH		 3156static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3157 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3158{
bb8c093b
CH		 3159 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3160 struct iwl3945_scanresults_notification *notif =
3161 (struct iwl3945_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 3162
3163 IWL_DEBUG_SCAN("Scan ch.res: "
3164 "%d [802.11%s] "
3165 "(TSF: 0x%08X:%08X) - %d "
3166 "elapsed=%lu usec (%dms since last)\n",
3167 notif->channel,
3168 notif->band ? "bg" : "a",
3169 le32_to_cpu(notif->tsf_high),
3170 le32_to_cpu(notif->tsf_low),
3171 le32_to_cpu(notif->statistics[0]),
3172 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3173 jiffies_to_msecs(elapsed_jiffies
3174 (priv->last_scan_jiffies, jiffies)));
3175
3176 priv->last_scan_jiffies = jiffies;
7878a5a4 3177 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3178}
3179
3180/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH		 3181static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3182 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3183{
bb8c093b
CH		 3184 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3185 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 3186
3187 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3188 scan_notif->scanned_channels,
3189 scan_notif->tsf_low,
3190 scan_notif->tsf_high, scan_notif->status);
3191
3192 /* The HW is no longer scanning */
3193 clear_bit(STATUS_SCAN_HW, &priv->status);
3194
3195 /* The scan completion notification came in, so kill that timer... */
3196 cancel_delayed_work(&priv->scan_check);
3197
3198 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
66b5004d
RR		 3199 (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
3200 "2.4" : "5.2",
b481de9c
ZY		 3201 jiffies_to_msecs(elapsed_jiffies
3202 (priv->scan_pass_start, jiffies)));
3203
66b5004d
RR		 3204 /* Remove this scanned band from the list of pending
3205 * bands to scan, band G precedes A in order of scanning
3206 * as seen in iwl3945_bg_request_scan */
3207 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
3208 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
3209 else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
3210 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 3211
3212 /* If a request to abort was given, or the scan did not succeed
3213 * then we reset the scan state machine and terminate,
3214 * re-queuing another scan if one has been requested */
3215 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3216 IWL_DEBUG_INFO("Aborted scan completed.\n");
3217 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3218 } else {
3219 /* If there are more bands on this scan pass reschedule */
3220 if (priv->scan_bands > 0)
3221 goto reschedule;
3222 }
3223
3224 priv->last_scan_jiffies = jiffies;
7878a5a4 3225 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3226 IWL_DEBUG_INFO("Setting scan to off\n");
3227
3228 clear_bit(STATUS_SCANNING, &priv->status);
3229
3230 IWL_DEBUG_INFO("Scan took %dms\n",
3231 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3232
3233 queue_work(priv->workqueue, &priv->scan_completed);
3234
3235 return;
3236
3237reschedule:
3238 priv->scan_pass_start = jiffies;
3239 queue_work(priv->workqueue, &priv->request_scan);
3240}
3241
3242/* Handle notification from uCode that card's power state is changing
3243 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH		 3244static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3245 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3246{
bb8c093b 3247 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3248 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3249 unsigned long status = priv->status;
3250
3251 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3252 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3253 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3254
bb8c093b 3255 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3256 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3257
3258 if (flags & HW_CARD_DISABLED)
3259 set_bit(STATUS_RF_KILL_HW, &priv->status);
3260 else
3261 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3262
3263
3264 if (flags & SW_CARD_DISABLED)
3265 set_bit(STATUS_RF_KILL_SW, &priv->status);
3266 else
3267 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3268
bb8c093b 3269 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3270
3271 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3272 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3273 (test_bit(STATUS_RF_KILL_SW, &status) !=
3274 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3275 queue_work(priv->workqueue, &priv->rf_kill);
3276 else
3277 wake_up_interruptible(&priv->wait_command_queue);
3278}
3279
3280/**
bb8c093b 3281 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 3282 *
3283 * Setup the RX handlers for each of the reply types sent from the uCode
3284 * to the host.
3285 *
3286 * This function chains into the hardware specific files for them to setup
3287 * any hardware specific handlers as well.
3288 */
bb8c093b 3289static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3290{
bb8c093b
CH		 3291 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3292 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3293 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3294 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3295 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 3296 iwl3945_rx_spectrum_measure_notif;
3297 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3298 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 3299 iwl3945_rx_pm_debug_statistics_notif;
3300 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3301
9fbab516
BC		 3302 /*
3303 * The same handler is used for both the REPLY to a discrete
3304 * statistics request from the host as well as for the periodic
3305 * statistics notifications (after received beacons) from the uCode.
b481de9c 3306 */
bb8c093b
CH		 3307 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3308 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3309
bb8c093b
CH		 3310 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3311 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3312 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3313 iwl3945_rx_scan_results_notif;
b481de9c 3314 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 3315 iwl3945_rx_scan_complete_notif;
3316 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 3317
9fbab516 3318 /* Set up hardware specific Rx handlers */
bb8c093b 3319 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY		 3320}
3321
91c066f2
TW		 3322/**
3323 * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3324 * When FW advances 'R' index, all entries between old and new 'R' index
3325 * need to be reclaimed.
3326 */
3327static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
3328 int txq_id, int index)
3329{
3330 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3331 struct iwl3945_queue *q = &txq->q;
3332 int nfreed = 0;
3333
3334 if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
3335 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3336 "is out of range [0-%d] %d %d.\n", txq_id,
3337 index, q->n_bd, q->write_ptr, q->read_ptr);
3338 return;
3339 }
3340
3341 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3342 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3343 if (nfreed > 1) {
3344 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
3345 q->write_ptr, q->read_ptr);
3346 queue_work(priv->workqueue, &priv->restart);
3347 break;
3348 }
3349 nfreed++;
3350 }
3351}
3352
3353
b481de9c 3354/**
bb8c093b 3355 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 3356 * @rxb: Rx buffer to reclaim
3357 *
3358 * If an Rx buffer has an async callback associated with it the callback
3359 * will be executed. The attached skb (if present) will only be freed
3360 * if the callback returns 1
3361 */
bb8c093b
CH		 3362static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3363 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3364{
bb8c093b 3365 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3366 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3367 int txq_id = SEQ_TO_QUEUE(sequence);
3368 int index = SEQ_TO_INDEX(sequence);
3369 int huge = sequence & SEQ_HUGE_FRAME;
3370 int cmd_index;
bb8c093b 3371 struct iwl3945_cmd *cmd;
b481de9c 3372
b481de9c
ZY		 3373 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3374
3375 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3376 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3377
3378 /* Input error checking is done when commands are added to queue. */
3379 if (cmd->meta.flags & CMD_WANT_SKB) {
3380 cmd->meta.source->u.skb = rxb->skb;
3381 rxb->skb = NULL;
3382 } else if (cmd->meta.u.callback &&
3383 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3384 rxb->skb = NULL;
3385
91c066f2 3386 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3387
3388 if (!(cmd->meta.flags & CMD_ASYNC)) {
3389 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3390 wake_up_interruptible(&priv->wait_command_queue);
3391 }
3392}
3393
3394/************************** RX-FUNCTIONS ****************************/
3395/*
3396 * Rx theory of operation
3397 *
3398 * The host allocates 32 DMA target addresses and passes the host address
3399 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3400 * 0 to 31
3401 *
3402 * Rx Queue Indexes
3403 * The host/firmware share two index registers for managing the Rx buffers.
3404 *
3405 * The READ index maps to the first position that the firmware may be writing
3406 * to -- the driver can read up to (but not including) this position and get
3407 * good data.
3408 * The READ index is managed by the firmware once the card is enabled.
3409 *
3410 * The WRITE index maps to the last position the driver has read from -- the
3411 * position preceding WRITE is the last slot the firmware can place a packet.
3412 *
3413 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3414 * WRITE = READ.
3415 *
9fbab516 3416 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 3417 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3418 *
9fbab516 3419 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 3420 * and fire the RX interrupt. The driver can then query the READ index and
3421 * process as many packets as possible, moving the WRITE index forward as it
3422 * resets the Rx queue buffers with new memory.
3423 *
3424 * The management in the driver is as follows:
3425 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3426 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3427 * to replenish the iwl->rxq->rx_free.
bb8c093b 3428 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 3429 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3430 * 'processed' and 'read' driver indexes as well)
3431 * + A received packet is processed and handed to the kernel network stack,
3432 * detached from the iwl->rxq. The driver 'processed' index is updated.
3433 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3434 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3435 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3436 * were enough free buffers and RX_STALLED is set it is cleared.
3437 *
3438 *
3439 * Driver sequence:
3440 *
9fbab516
BC		 3441 * iwl3945_rx_queue_alloc() Allocates rx_free
3442 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3443 * iwl3945_rx_queue_restock
9fbab516 3444 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 3445 * queue, updates firmware pointers, and updates
3446 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3447 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY		 3448 *
3449 * -- enable interrupts --
9fbab516 3450 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY		 3451 * READ INDEX, detaching the SKB from the pool.
3452 * Moves the packet buffer from queue to rx_used.
bb8c093b 3453 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY		 3454 * slots.
3455 * ...
3456 *
3457 */
3458
3459/**
bb8c093b 3460 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3461 */
bb8c093b 3462static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY		 3463{
3464 int s = q->read - q->write;
3465 if (s <= 0)
3466 s += RX_QUEUE_SIZE;
3467 /* keep some buffer to not confuse full and empty queue */
3468 s -= 2;
3469 if (s < 0)
3470 s = 0;
3471 return s;
3472}
3473
3474/**
bb8c093b 3475 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3476 */
bb8c093b 3477int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY		 3478{
3479 u32 reg = 0;
3480 int rc = 0;
3481 unsigned long flags;
3482
3483 spin_lock_irqsave(&q->lock, flags);
3484
3485 if (q->need_update == 0)
3486 goto exit_unlock;
3487
6440adb5 3488 /* If power-saving is in use, make sure device is awake */
b481de9c 3489 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 3490 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3491
3492 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 3493 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3494 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3495 goto exit_unlock;
3496 }
3497
bb8c093b 3498 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3499 if (rc)
3500 goto exit_unlock;
3501
6440adb5 3502 /* Device expects a multiple of 8 */
bb8c093b 3503 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 3504 q->write & ~0x7);
bb8c093b 3505 iwl3945_release_nic_access(priv);
6440adb5
CB		 3506
3507 /* Else device is assumed to be awake */
b481de9c 3508 } else
6440adb5 3509 /* Device expects a multiple of 8 */
bb8c093b 3510 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 3511
3512
3513 q->need_update = 0;
3514
3515 exit_unlock:
3516 spin_unlock_irqrestore(&q->lock, flags);
3517 return rc;
3518}
3519
3520/**
9fbab516 3521 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3522 */
bb8c093b 3523static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY		 3524 dma_addr_t dma_addr)
3525{
3526 return cpu_to_le32((u32)dma_addr);
3527}
3528
3529/**
bb8c093b 3530 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3531 *
9fbab516 3532 * If there are slots in the RX queue that need to be restocked,
b481de9c 3533 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3534 * as we can, pulling from rx_free.
b481de9c
ZY		 3535 *
3536 * This moves the 'write' index forward to catch up with 'processed', and
3537 * also updates the memory address in the firmware to reference the new
3538 * target buffer.
3539 */
bb8c093b 3540static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 3541{
bb8c093b 3542 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3543 struct list_head *element;
bb8c093b 3544 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3545 unsigned long flags;
3546 int write, rc;
3547
3548 spin_lock_irqsave(&rxq->lock, flags);
3549 write = rxq->write & ~0x7;
bb8c093b 3550 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3551 /* Get next free Rx buffer, remove from free list */
b481de9c 3552 element = rxq->rx_free.next;
bb8c093b 3553 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 3554 list_del(element);
6440adb5
CB		 3555
3556 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 3557 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY		 3558 rxq->queue[rxq->write] = rxb;
3559 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3560 rxq->free_count--;
3561 }
3562 spin_unlock_irqrestore(&rxq->lock, flags);
3563 /* If the pre-allocated buffer pool is dropping low, schedule to
3564 * refill it */
3565 if (rxq->free_count <= RX_LOW_WATERMARK)
3566 queue_work(priv->workqueue, &priv->rx_replenish);
3567
3568
6440adb5
CB		 3569 /* If we've added more space for the firmware to place data, tell it.
3570 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 3571 if ((write != (rxq->write & ~0x7))
3572 || (abs(rxq->write - rxq->read) > 7)) {
3573 spin_lock_irqsave(&rxq->lock, flags);
3574 rxq->need_update = 1;
3575 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 3576 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 3577 if (rc)
3578 return rc;
3579 }
3580
3581 return 0;
3582}
3583
3584/**
bb8c093b 3585 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 3586 *
3587 * When moving to rx_free an SKB is allocated for the slot.
3588 *
bb8c093b 3589 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 3590 * This is called as a scheduled work item (except for during initialization)
b481de9c 3591 */
5c0eef96 3592static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
b481de9c 3593{
bb8c093b 3594 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3595 struct list_head *element;
bb8c093b 3596 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3597 unsigned long flags;
3598 spin_lock_irqsave(&rxq->lock, flags);
3599 while (!list_empty(&rxq->rx_used)) {
3600 element = rxq->rx_used.next;
bb8c093b 3601 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
CB		 3602
3603 /* Alloc a new receive buffer */
b481de9c
ZY		 3604 rxb->skb =
3605 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3606 if (!rxb->skb) {
3607 if (net_ratelimit())
3608 printk(KERN_CRIT DRV_NAME
3609 ": Can not allocate SKB buffers\n");
3610 /* We don't reschedule replenish work here -- we will
3611 * call the restock method and if it still needs
3612 * more buffers it will schedule replenish */
3613 break;
3614 }
12342c47
ZY		 3615
3616 /* If radiotap head is required, reserve some headroom here.
3617 * The physical head count is a variable rx_stats->phy_count.
3618 * We reserve 4 bytes here. Plus these extra bytes, the
3619 * headroom of the physical head should be enough for the
3620 * radiotap head that iwl3945 supported. See iwl3945_rt.
3621 */
3622 skb_reserve(rxb->skb, 4);
3623
b481de9c
ZY		 3624 priv->alloc_rxb_skb++;
3625 list_del(element);
6440adb5
CB		 3626
3627 /* Get physical address of RB/SKB */
b481de9c
ZY		 3628 rxb->dma_addr =
3629 pci_map_single(priv->pci_dev, rxb->skb->data,
3630 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3631 list_add_tail(&rxb->list, &rxq->rx_free);
3632 rxq->free_count++;
3633 }
3634 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA		 3635}
3636
3637/*
3638 * this should be called while priv->lock is locked
3639 */
4fd1f841 3640static void __iwl3945_rx_replenish(void *data)
5c0eef96
MA		 3641{
3642 struct iwl3945_priv *priv = data;
3643
3644 iwl3945_rx_allocate(priv);
3645 iwl3945_rx_queue_restock(priv);
3646}
3647
3648
3649void iwl3945_rx_replenish(void *data)
3650{
3651 struct iwl3945_priv *priv = data;
3652 unsigned long flags;
3653
3654 iwl3945_rx_allocate(priv);
b481de9c
ZY		 3655
3656 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3657 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3658 spin_unlock_irqrestore(&priv->lock, flags);
3659}
3660
3661/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 3662 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY		 3663 * This free routine walks the list of POOL entries and if SKB is set to
3664 * non NULL it is unmapped and freed
3665 */
bb8c093b 3666static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3667{
3668 int i;
3669 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3670 if (rxq->pool[i].skb != NULL) {
3671 pci_unmap_single(priv->pci_dev,
3672 rxq->pool[i].dma_addr,
3673 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3674 dev_kfree_skb(rxq->pool[i].skb);
3675 }
3676 }
3677
3678 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3679 rxq->dma_addr);
3680 rxq->bd = NULL;
3681}
3682
bb8c093b 3683int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 3684{
bb8c093b 3685 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3686 struct pci_dev *dev = priv->pci_dev;
3687 int i;
3688
3689 spin_lock_init(&rxq->lock);
3690 INIT_LIST_HEAD(&rxq->rx_free);
3691 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB		 3692
3693 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY		 3694 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3695 if (!rxq->bd)
3696 return -ENOMEM;
6440adb5 3697
b481de9c
ZY		 3698 /* Fill the rx_used queue with _all_ of the Rx buffers */
3699 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3700 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 3701
b481de9c
ZY		 3702 /* Set us so that we have processed and used all buffers, but have
3703 * not restocked the Rx queue with fresh buffers */
3704 rxq->read = rxq->write = 0;
3705 rxq->free_count = 0;
3706 rxq->need_update = 0;
3707 return 0;
3708}
3709
bb8c093b 3710void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3711{
3712 unsigned long flags;
3713 int i;
3714 spin_lock_irqsave(&rxq->lock, flags);
3715 INIT_LIST_HEAD(&rxq->rx_free);
3716 INIT_LIST_HEAD(&rxq->rx_used);
3717 /* Fill the rx_used queue with _all_ of the Rx buffers */
3718 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3719 /* In the reset function, these buffers may have been allocated
3720 * to an SKB, so we need to unmap and free potential storage */
3721 if (rxq->pool[i].skb != NULL) {
3722 pci_unmap_single(priv->pci_dev,
3723 rxq->pool[i].dma_addr,
3724 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3725 priv->alloc_rxb_skb--;
3726 dev_kfree_skb(rxq->pool[i].skb);
3727 rxq->pool[i].skb = NULL;
3728 }
3729 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3730 }
3731
3732 /* Set us so that we have processed and used all buffers, but have
3733 * not restocked the Rx queue with fresh buffers */
3734 rxq->read = rxq->write = 0;
3735 rxq->free_count = 0;
3736 spin_unlock_irqrestore(&rxq->lock, flags);
3737}
3738
3739/* Convert linear signal-to-noise ratio into dB */
3740static u8 ratio2dB[100] = {
3741/* 0 1 2 3 4 5 6 7 8 9 */
3742 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3743 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3744 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3745 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3746 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3747 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3748 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3749 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3750 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3751 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3752};
3753
3754/* Calculates a relative dB value from a ratio of linear
3755 * (i.e. not dB) signal levels.
3756 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 3757int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 3758{
221c80cf
AB		 3759 /* 1000:1 or higher just report as 60 dB */
3760 if (sig_ratio >= 1000)
b481de9c
ZY		 3761 return 60;
3762
221c80cf 3763 /* 100:1 or higher, divide by 10 and use table,
b481de9c 3764 * add 20 dB to make up for divide by 10 */
221c80cf 3765 if (sig_ratio >= 100)
3ac7f146 3766 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY		 3767
3768 /* We shouldn't see this */
3769 if (sig_ratio < 1)
3770 return 0;
3771
3772 /* Use table for ratios 1:1 - 99:1 */
3773 return (int)ratio2dB[sig_ratio];
3774}
3775
3776#define PERFECT_RSSI (-20) /* dBm */
3777#define WORST_RSSI (-95) /* dBm */
3778#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3779
3780/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3781 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3782 * about formulas used below. */
bb8c093b 3783int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 3784{
3785 int sig_qual;
3786 int degradation = PERFECT_RSSI - rssi_dbm;
3787
3788 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3789 * as indicator; formula is (signal dbm - noise dbm).
3790 * SNR at or above 40 is a great signal (100%).
3791 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3792 * Weakest usable signal is usually 10 - 15 dB SNR. */
3793 if (noise_dbm) {
3794 if (rssi_dbm - noise_dbm >= 40)
3795 return 100;
3796 else if (rssi_dbm < noise_dbm)
3797 return 0;
3798 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3799
3800 /* Else use just the signal level.
3801 * This formula is a least squares fit of data points collected and
3802 * compared with a reference system that had a percentage (%) display
3803 * for signal quality. */
3804 } else
3805 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3806 (15 * RSSI_RANGE + 62 * degradation)) /
3807 (RSSI_RANGE * RSSI_RANGE);
3808
3809 if (sig_qual > 100)
3810 sig_qual = 100;
3811 else if (sig_qual < 1)
3812 sig_qual = 0;
3813
3814 return sig_qual;
3815}
3816
3817/**
9fbab516 3818 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 3819 *
3820 * Uses the priv->rx_handlers callback function array to invoke
3821 * the appropriate handlers, including command responses,
3822 * frame-received notifications, and other notifications.
3823 */
bb8c093b 3824static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 3825{
bb8c093b
CH		 3826 struct iwl3945_rx_mem_buffer *rxb;
3827 struct iwl3945_rx_packet *pkt;
3828 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3829 u32 r, i;
3830 int reclaim;
3831 unsigned long flags;
5c0eef96 3832 u8 fill_rx = 0;
d68ab680 3833 u32 count = 8;
b481de9c 3834
6440adb5
CB		 3835 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3836 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 3837 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY		 3838 i = rxq->read;
3839
5c0eef96
MA		 3840 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3841 fill_rx = 1;
b481de9c
ZY		 3842 /* Rx interrupt, but nothing sent from uCode */
3843 if (i == r)
3844 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3845
3846 while (i != r) {
3847 rxb = rxq->queue[i];
3848
9fbab516 3849 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 3850 * then a bug has been introduced in the queue refilling
3851 * routines -- catch it here */
3852 BUG_ON(rxb == NULL);
3853
3854 rxq->queue[i] = NULL;
3855
3856 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
3857 IWL_RX_BUF_SIZE,
3858 PCI_DMA_FROMDEVICE);
bb8c093b 3859 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3860
3861 /* Reclaim a command buffer only if this packet is a response
3862 * to a (driver-originated) command.
3863 * If the packet (e.g. Rx frame) originated from uCode,
3864 * there is no command buffer to reclaim.
3865 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
3866 * but apparently a few don't get set; catch them here. */
3867 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
3868 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
3869 (pkt->hdr.cmd != REPLY_TX);
3870
3871 /* Based on type of command response or notification,
3872 * handle those that need handling via function in
bb8c093b 3873 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY		 3874 if (priv->rx_handlers[pkt->hdr.cmd]) {
3875 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3876 "r = %d, i = %d, %s, 0x%02x\n", r, i,
3877 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3878 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
3879 } else {
3880 /* No handling needed */
3881 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3882 "r %d i %d No handler needed for %s, 0x%02x\n",
3883 r, i, get_cmd_string(pkt->hdr.cmd),
3884 pkt->hdr.cmd);
3885 }
3886
3887 if (reclaim) {
9fbab516
BC		 3888 /* Invoke any callbacks, transfer the skb to caller, and
3889 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY		 3890 * as we reclaim the driver command queue */
3891 if (rxb && rxb->skb)
bb8c093b 3892 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY		 3893 else
3894 IWL_WARNING("Claim null rxb?\n");
3895 }
3896
3897 /* For now we just don't re-use anything. We can tweak this
3898 * later to try and re-use notification packets and SKBs that
3899 * fail to Rx correctly */
3900 if (rxb->skb != NULL) {
3901 priv->alloc_rxb_skb--;
3902 dev_kfree_skb_any(rxb->skb);
3903 rxb->skb = NULL;
3904 }
3905
3906 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
3907 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3908 spin_lock_irqsave(&rxq->lock, flags);
3909 list_add_tail(&rxb->list, &priv->rxq.rx_used);
3910 spin_unlock_irqrestore(&rxq->lock, flags);
3911 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 3912 /* If there are a lot of unused frames,
3913 * restock the Rx queue so ucode won't assert. */
3914 if (fill_rx) {
3915 count++;
3916 if (count >= 8) {
3917 priv->rxq.read = i;
3918 __iwl3945_rx_replenish(priv);
3919 count = 0;
3920 }
3921 }
b481de9c
ZY		 3922 }
3923
3924 /* Backtrack one entry */
3925 priv->rxq.read = i;
bb8c093b 3926 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3927}
3928
6440adb5
CB		 3929/**
3930 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
3931 */
bb8c093b
CH		 3932static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
3933 struct iwl3945_tx_queue *txq)
b481de9c
ZY		 3934{
3935 u32 reg = 0;
3936 int rc = 0;
3937 int txq_id = txq->q.id;
3938
3939 if (txq->need_update == 0)
3940 return rc;
3941
3942 /* if we're trying to save power */
3943 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3944 /* wake up nic if it's powered down ...
3945 * uCode will wake up, and interrupt us again, so next
3946 * time we'll skip this part. */
bb8c093b 3947 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3948
3949 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3950 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 3951 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3952 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3953 return rc;
3954 }
3955
3956 /* restore this queue's parameters in nic hardware. */
bb8c093b 3957 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3958 if (rc)
3959 return rc;
bb8c093b 3960 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 3961 txq->q.write_ptr | (txq_id << 8));
bb8c093b 3962 iwl3945_release_nic_access(priv);
b481de9c
ZY		 3963
3964 /* else not in power-save mode, uCode will never sleep when we're
3965 * trying to tx (during RFKILL, we're not trying to tx). */
3966 } else
bb8c093b 3967 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 3968 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 3969
3970 txq->need_update = 0;
3971
3972 return rc;
3973}
3974
c8b0e6e1 3975#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 3976static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 3977{
3978 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 3979 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 3980 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
3981 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
3982 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
3983 le32_to_cpu(rxon->filter_flags));
3984 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
3985 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
3986 rxon->ofdm_basic_rates);
3987 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
e174961c
JB		 3988 IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
3989 IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
b481de9c
ZY		 3990 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
3991}
3992#endif
3993
bb8c093b 3994static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 3995{
3996 IWL_DEBUG_ISR("Enabling interrupts\n");
3997 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 3998 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 3999}
4000
0359facc
MA		 4001
4002/* call this function to flush any scheduled tasklet */
4003static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
4004{
4005 /* wait to make sure we flush pedding tasklet*/
4006 synchronize_irq(priv->pci_dev->irq);
4007 tasklet_kill(&priv->irq_tasklet);
4008}
4009
4010
bb8c093b 4011static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4012{
4013 clear_bit(STATUS_INT_ENABLED, &priv->status);
4014
4015 /* disable interrupts from uCode/NIC to host */
bb8c093b 4016 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4017
4018 /* acknowledge/clear/reset any interrupts still pending
4019 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH		 4020 iwl3945_write32(priv, CSR_INT, 0xffffffff);
4021 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 4022 IWL_DEBUG_ISR("Disabled interrupts\n");
4023}
4024
4025static const char *desc_lookup(int i)
4026{
4027 switch (i) {
4028 case 1:
4029 return "FAIL";
4030 case 2:
4031 return "BAD_PARAM";
4032 case 3:
4033 return "BAD_CHECKSUM";
4034 case 4:
4035 return "NMI_INTERRUPT";
4036 case 5:
4037 return "SYSASSERT";
4038 case 6:
4039 return "FATAL_ERROR";
4040 }
4041
4042 return "UNKNOWN";
4043}
4044
4045#define ERROR_START_OFFSET (1 * sizeof(u32))
4046#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4047
bb8c093b 4048static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4049{
4050 u32 i;
4051 u32 desc, time, count, base, data1;
4052 u32 blink1, blink2, ilink1, ilink2;
4053 int rc;
4054
4055 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4056
bb8c093b 4057 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4058 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4059 return;
4060 }
4061
bb8c093b 4062 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4063 if (rc) {
4064 IWL_WARNING("Can not read from adapter at this time.\n");
4065 return;
4066 }
4067
bb8c093b 4068 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY		 4069
4070 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4071 IWL_ERROR("Start IWL Error Log Dump:\n");
2acae16e 4072 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
b481de9c
ZY		 4073 }
4074
4075 IWL_ERROR("Desc Time asrtPC blink2 "
4076 "ilink1 nmiPC Line\n");
4077 for (i = ERROR_START_OFFSET;
4078 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4079 i += ERROR_ELEM_SIZE) {
bb8c093b 4080 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4081 time =
bb8c093b 4082 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4083 blink1 =
bb8c093b 4084 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4085 blink2 =
bb8c093b 4086 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4087 ilink1 =
bb8c093b 4088 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4089 ilink2 =
bb8c093b 4090 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4091 data1 =
bb8c093b 4092 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY		 4093
4094 IWL_ERROR
4095 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4096 desc_lookup(desc), desc, time, blink1, blink2,
4097 ilink1, ilink2, data1);
4098 }
4099
bb8c093b 4100 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4101
4102}
4103
f58177b9 4104#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY		 4105
4106/**
bb8c093b 4107 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4108 *
bb8c093b 4109 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4110 */
bb8c093b 4111static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY		 4112 u32 num_events, u32 mode)
4113{
4114 u32 i;
4115 u32 base; /* SRAM byte address of event log header */
4116 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4117 u32 ptr; /* SRAM byte address of log data */
4118 u32 ev, time, data; /* event log data */
4119
4120 if (num_events == 0)
4121 return;
4122
4123 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4124
4125 if (mode == 0)
4126 event_size = 2 * sizeof(u32);
4127 else
4128 event_size = 3 * sizeof(u32);
4129
4130 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4131
4132 /* "time" is actually "data" for mode 0 (no timestamp).
4133 * place event id # at far right for easier visual parsing. */
4134 for (i = 0; i < num_events; i++) {
bb8c093b 4135 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4136 ptr += sizeof(u32);
bb8c093b 4137 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4138 ptr += sizeof(u32);
4139 if (mode == 0)
4140 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4141 else {
bb8c093b 4142 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4143 ptr += sizeof(u32);
4144 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4145 }
4146 }
4147}
4148
bb8c093b 4149static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4150{
4151 int rc;
4152 u32 base; /* SRAM byte address of event log header */
4153 u32 capacity; /* event log capacity in # entries */
4154 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4155 u32 num_wraps; /* # times uCode wrapped to top of log */
4156 u32 next_entry; /* index of next entry to be written by uCode */
4157 u32 size; /* # entries that we'll print */
4158
4159 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4160 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4161 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4162 return;
4163 }
4164
bb8c093b 4165 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4166 if (rc) {
4167 IWL_WARNING("Can not read from adapter at this time.\n");
4168 return;
4169 }
4170
4171 /* event log header */
bb8c093b
CH		 4172 capacity = iwl3945_read_targ_mem(priv, base);
4173 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4174 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4175 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 4176
4177 size = num_wraps ? capacity : next_entry;
4178
4179 /* bail out if nothing in log */
4180 if (size == 0) {
583fab37 4181 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4182 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4183 return;
4184 }
4185
583fab37 4186 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 4187 size, num_wraps);
4188
4189 /* if uCode has wrapped back to top of log, start at the oldest entry,
4190 * i.e the next one that uCode would fill. */
4191 if (num_wraps)
bb8c093b 4192 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY		 4193 capacity - next_entry, mode);
4194
4195 /* (then/else) start at top of log */
bb8c093b 4196 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4197
bb8c093b 4198 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4199}
4200
4201/**
bb8c093b 4202 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4203 */
bb8c093b 4204static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4205{
bb8c093b 4206 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY		 4207 set_bit(STATUS_FW_ERROR, &priv->status);
4208
4209 /* Cancel currently queued command. */
4210 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4211
c8b0e6e1 4212#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4213 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4214 iwl3945_dump_nic_error_log(priv);
4215 iwl3945_dump_nic_event_log(priv);
4216 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY		 4217 }
4218#endif
4219
4220 wake_up_interruptible(&priv->wait_command_queue);
4221
4222 /* Keep the restart process from trying to send host
4223 * commands by clearing the INIT status bit */
4224 clear_bit(STATUS_READY, &priv->status);
4225
4226 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4227 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4228 "Restarting adapter due to uCode error.\n");
4229
bb8c093b 4230 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4231 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4232 sizeof(priv->recovery_rxon));
4233 priv->error_recovering = 1;
4234 }
4235 queue_work(priv->workqueue, &priv->restart);
4236 }
4237}
4238
bb8c093b 4239static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY		 4240{
4241 unsigned long flags;
4242
4243 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4244 sizeof(priv->staging_rxon));
4245 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4246 iwl3945_commit_rxon(priv);
b481de9c 4247
bb8c093b 4248 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY		 4249
4250 spin_lock_irqsave(&priv->lock, flags);
4251 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4252 priv->error_recovering = 0;
4253 spin_unlock_irqrestore(&priv->lock, flags);
4254}
4255
bb8c093b 4256static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY		 4257{
4258 u32 inta, handled = 0;
4259 u32 inta_fh;
4260 unsigned long flags;
c8b0e6e1 4261#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 4262 u32 inta_mask;
4263#endif
4264
4265 spin_lock_irqsave(&priv->lock, flags);
4266
4267 /* Ack/clear/reset pending uCode interrupts.
4268 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4269 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH		 4270 inta = iwl3945_read32(priv, CSR_INT);
4271 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY		 4272
4273 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4274 * Any new interrupts that happen after this, either while we're
4275 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH		 4276 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4277 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4278
c8b0e6e1 4279#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4280 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC		 4281 /* just for debug */
4282 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 4283 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4284 inta, inta_mask, inta_fh);
4285 }
4286#endif
4287
4288 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4289 * atomic, make sure that inta covers all the interrupts that
4290 * we've discovered, even if FH interrupt came in just after
4291 * reading CSR_INT. */
6f83eaa1 4292 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 4293 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 4294 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY		 4295 inta |= CSR_INT_BIT_FH_TX;
4296
4297 /* Now service all interrupt bits discovered above. */
4298 if (inta & CSR_INT_BIT_HW_ERR) {
4299 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4300
4301 /* Tell the device to stop sending interrupts */
bb8c093b 4302 iwl3945_disable_interrupts(priv);
b481de9c 4303
bb8c093b 4304 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4305
4306 handled |= CSR_INT_BIT_HW_ERR;
4307
4308 spin_unlock_irqrestore(&priv->lock, flags);
4309
4310 return;
4311 }
4312
c8b0e6e1 4313#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4314 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c 4315 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP		 4316 if (inta & CSR_INT_BIT_SCD)
4317 IWL_DEBUG_ISR("Scheduler finished to transmit "
4318 "the frame/frames.\n");
b481de9c
ZY		 4319
4320 /* Alive notification via Rx interrupt will do the real work */
4321 if (inta & CSR_INT_BIT_ALIVE)
4322 IWL_DEBUG_ISR("Alive interrupt\n");
4323 }
4324#endif
4325 /* Safely ignore these bits for debug checks below */
25c03d8e 4326 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c
ZY		 4327
4328 /* HW RF KILL switch toggled (4965 only) */
4329 if (inta & CSR_INT_BIT_RF_KILL) {
4330 int hw_rf_kill = 0;
bb8c093b 4331 if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 4332 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4333 hw_rf_kill = 1;
4334
4335 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4336 "RF_KILL bit toggled to %s.\n",
4337 hw_rf_kill ? "disable radio":"enable radio");
4338
4339 /* Queue restart only if RF_KILL switch was set to "kill"
4340 * when we loaded driver, and is now set to "enable".
4341 * After we're Alive, RF_KILL gets handled by
3230455d 4342 * iwl3945_rx_card_state_notif() */
53e49093
ZY		 4343 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4344 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 4345 queue_work(priv->workqueue, &priv->restart);
53e49093 4346 }
b481de9c
ZY		 4347
4348 handled |= CSR_INT_BIT_RF_KILL;
4349 }
4350
4351 /* Chip got too hot and stopped itself (4965 only) */
4352 if (inta & CSR_INT_BIT_CT_KILL) {
4353 IWL_ERROR("Microcode CT kill error detected.\n");
4354 handled |= CSR_INT_BIT_CT_KILL;
4355 }
4356
4357 /* Error detected by uCode */
4358 if (inta & CSR_INT_BIT_SW_ERR) {
4359 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4360 inta);
bb8c093b 4361 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4362 handled |= CSR_INT_BIT_SW_ERR;
4363 }
4364
4365 /* uCode wakes up after power-down sleep */
4366 if (inta & CSR_INT_BIT_WAKEUP) {
4367 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH		 4368 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4369 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4370 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4371 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4372 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4373 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4374 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 4375
4376 handled |= CSR_INT_BIT_WAKEUP;
4377 }
4378
4379 /* All uCode command responses, including Tx command responses,
4380 * Rx "responses" (frame-received notification), and other
4381 * notifications from uCode come through here*/
4382 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4383 iwl3945_rx_handle(priv);
b481de9c
ZY		 4384 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4385 }
4386
4387 if (inta & CSR_INT_BIT_FH_TX) {
4388 IWL_DEBUG_ISR("Tx interrupt\n");
4389
bb8c093b
CH		 4390 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4391 if (!iwl3945_grab_nic_access(priv)) {
4392 iwl3945_write_direct32(priv,
b481de9c
ZY		 4393 FH_TCSR_CREDIT
4394 (ALM_FH_SRVC_CHNL), 0x0);
bb8c093b 4395 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4396 }
4397 handled |= CSR_INT_BIT_FH_TX;
4398 }
4399
4400 if (inta & ~handled)
4401 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4402
4403 if (inta & ~CSR_INI_SET_MASK) {
4404 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4405 inta & ~CSR_INI_SET_MASK);
4406 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4407 }
4408
4409 /* Re-enable all interrupts */
0359facc
MA		 4410 /* only Re-enable if disabled by irq */
4411 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4412 iwl3945_enable_interrupts(priv);
b481de9c 4413
c8b0e6e1 4414#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4415 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4416 inta = iwl3945_read32(priv, CSR_INT);
4417 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4418 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4419 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4420 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4421 }
4422#endif
4423 spin_unlock_irqrestore(&priv->lock, flags);
4424}
4425
bb8c093b 4426static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4427{
bb8c093b 4428 struct iwl3945_priv *priv = data;
b481de9c
ZY		 4429 u32 inta, inta_mask;
4430 u32 inta_fh;
4431 if (!priv)
4432 return IRQ_NONE;
4433
4434 spin_lock(&priv->lock);
4435
4436 /* Disable (but don't clear!) interrupts here to avoid
4437 * back-to-back ISRs and sporadic interrupts from our NIC.
4438 * If we have something to service, the tasklet will re-enable ints.
4439 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH		 4440 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4441 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4442
4443 /* Discover which interrupts are active/pending */
bb8c093b
CH		 4444 inta = iwl3945_read32(priv, CSR_INT);
4445 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4446
4447 /* Ignore interrupt if there's nothing in NIC to service.
4448 * This may be due to IRQ shared with another device,
4449 * or due to sporadic interrupts thrown from our NIC. */
4450 if (!inta && !inta_fh) {
4451 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4452 goto none;
4453 }
4454
4455 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4456 /* Hardware disappeared */
4457 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
cb4da1a3 4458 goto unplugged;
b481de9c
ZY		 4459 }
4460
4461 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4462 inta, inta_mask, inta_fh);
4463
25c03d8e
JP		 4464 inta &= ~CSR_INT_BIT_SCD;
4465
bb8c093b 4466 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP		 4467 if (likely(inta || inta_fh))
4468 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4469unplugged:
b481de9c
ZY		 4470 spin_unlock(&priv->lock);
4471
4472 return IRQ_HANDLED;
4473
4474 none:
4475 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA		 4476 /* only Re-enable if disabled by irq */
4477 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4478 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 4479 spin_unlock(&priv->lock);
4480 return IRQ_NONE;
4481}
4482
4483/************************** EEPROM BANDS ****************************
4484 *
bb8c093b 4485 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY		 4486 * EEPROM contents to the specific channel number supported for each
4487 * band.
4488 *
bb8c093b 4489 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY		 4490 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4491 * The specific geography and calibration information for that channel
4492 * is contained in the eeprom map itself.
4493 *
4494 * During init, we copy the eeprom information and channel map
4495 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4496 *
4497 * channel_map_24/52 provides the index in the channel_info array for a
4498 * given channel. We have to have two separate maps as there is channel
4499 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4500 * band_2
4501 *
4502 * A value of 0xff stored in the channel_map indicates that the channel
4503 * is not supported by the hardware at all.
4504 *
4505 * A value of 0xfe in the channel_map indicates that the channel is not
4506 * valid for Tx with the current hardware. This means that
4507 * while the system can tune and receive on a given channel, it may not
4508 * be able to associate or transmit any frames on that
4509 * channel. There is no corresponding channel information for that
4510 * entry.
4511 *
4512 *********************************************************************/
4513
4514/* 2.4 GHz */
bb8c093b 4515static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY		 4516 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4517};
4518
4519/* 5.2 GHz bands */
9fbab516 4520static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY		 4521 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4522};
4523
9fbab516 4524static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY		 4525 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4526};
4527
bb8c093b 4528static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY		 4529 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4530};
4531
bb8c093b 4532static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY		 4533 145, 149, 153, 157, 161, 165
4534};
4535
bb8c093b 4536static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 4537 int *eeprom_ch_count,
bb8c093b 4538 const struct iwl3945_eeprom_channel
b481de9c
ZY		 4539 **eeprom_ch_info,
4540 const u8 **eeprom_ch_index)
4541{
4542 switch (band) {
4543 case 1: /* 2.4GHz band */
bb8c093b 4544 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 4545 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 4546 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4547 break;
9fbab516 4548 case 2: /* 4.9GHz band */
bb8c093b 4549 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 4550 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 4551 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY		 4552 break;
4553 case 3: /* 5.2GHz band */
bb8c093b 4554 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 4555 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 4556 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4557 break;
9fbab516 4558 case 4: /* 5.5GHz band */
bb8c093b 4559 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 4560 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 4561 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4562 break;
9fbab516 4563 case 5: /* 5.7GHz band */
bb8c093b 4564 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 4565 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 4566 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY		 4567 break;
4568 default:
4569 BUG();
4570 return;
4571 }
4572}
4573
6440adb5
CB		 4574/**
4575 * iwl3945_get_channel_info - Find driver's private channel info
4576 *
4577 * Based on band and channel number.
4578 */
bb8c093b 4579const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
8318d78a 4580 enum ieee80211_band band, u16 channel)
b481de9c
ZY		 4581{
4582 int i;
4583
8318d78a
JB		 4584 switch (band) {
4585 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 4586 for (i = 14; i < priv->channel_count; i++) {
4587 if (priv->channel_info[i].channel == channel)
4588 return &priv->channel_info[i];
4589 }
4590 break;
4591
8318d78a 4592 case IEEE80211_BAND_2GHZ:
b481de9c
ZY		 4593 if (channel >= 1 && channel <= 14)
4594 return &priv->channel_info[channel - 1];
4595 break;
8318d78a
JB		 4596 case IEEE80211_NUM_BANDS:
4597 WARN_ON(1);
b481de9c
ZY		 4598 }
4599
4600 return NULL;
4601}
4602
4603#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4604 ? # x " " : "")
4605
6440adb5
CB		 4606/**
4607 * iwl3945_init_channel_map - Set up driver's info for all possible channels
4608 */
bb8c093b 4609static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY		 4610{
4611 int eeprom_ch_count = 0;
4612 const u8 *eeprom_ch_index = NULL;
bb8c093b 4613 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 4614 int band, ch;
bb8c093b 4615 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4616
4617 if (priv->channel_count) {
4618 IWL_DEBUG_INFO("Channel map already initialized.\n");
4619 return 0;
4620 }
4621
4622 if (priv->eeprom.version < 0x2f) {
4623 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
4624 priv->eeprom.version);
4625 return -EINVAL;
4626 }
4627
4628 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4629
4630 priv->channel_count =
bb8c093b
CH		 4631 ARRAY_SIZE(iwl3945_eeprom_band_1) +
4632 ARRAY_SIZE(iwl3945_eeprom_band_2) +
4633 ARRAY_SIZE(iwl3945_eeprom_band_3) +
4634 ARRAY_SIZE(iwl3945_eeprom_band_4) +
4635 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY		 4636
4637 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4638
bb8c093b 4639 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY		 4640 priv->channel_count, GFP_KERNEL);
4641 if (!priv->channel_info) {
4642 IWL_ERROR("Could not allocate channel_info\n");
4643 priv->channel_count = 0;
4644 return -ENOMEM;
4645 }
4646
4647 ch_info = priv->channel_info;
4648
4649 /* Loop through the 5 EEPROM bands adding them in order to the
4650 * channel map we maintain (that contains additional information than
4651 * what just in the EEPROM) */
4652 for (band = 1; band <= 5; band++) {
4653
bb8c093b 4654 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 4655 &eeprom_ch_info, &eeprom_ch_index);
4656
4657 /* Loop through each band adding each of the channels */
4658 for (ch = 0; ch < eeprom_ch_count; ch++) {
4659 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB		 4660 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4661 IEEE80211_BAND_5GHZ;
b481de9c
ZY		 4662
4663 /* permanently store EEPROM's channel regulatory flags
4664 * and max power in channel info database. */
4665 ch_info->eeprom = eeprom_ch_info[ch];
4666
4667 /* Copy the run-time flags so they are there even on
4668 * invalid channels */
4669 ch_info->flags = eeprom_ch_info[ch].flags;
4670
4671 if (!(is_channel_valid(ch_info))) {
4672 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4673 "No traffic\n",
4674 ch_info->channel,
4675 ch_info->flags,
4676 is_channel_a_band(ch_info) ?
4677 "5.2" : "2.4");
4678 ch_info++;
4679 continue;
4680 }
4681
4682 /* Initialize regulatory-based run-time data */
4683 ch_info->max_power_avg = ch_info->curr_txpow =
4684 eeprom_ch_info[ch].max_power_avg;
4685 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4686 ch_info->min_power = 0;
4687
fe7c4040 4688 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
b481de9c
ZY		 4689 " %ddBm): Ad-Hoc %ssupported\n",
4690 ch_info->channel,
4691 is_channel_a_band(ch_info) ?
4692 "5.2" : "2.4",
8211ef78 4693 CHECK_AND_PRINT(VALID),
b481de9c
ZY		 4694 CHECK_AND_PRINT(IBSS),
4695 CHECK_AND_PRINT(ACTIVE),
4696 CHECK_AND_PRINT(RADAR),
4697 CHECK_AND_PRINT(WIDE),
b481de9c
ZY		 4698 CHECK_AND_PRINT(DFS),
4699 eeprom_ch_info[ch].flags,
4700 eeprom_ch_info[ch].max_power_avg,
4701 ((eeprom_ch_info[ch].
4702 flags & EEPROM_CHANNEL_IBSS)
4703 && !(eeprom_ch_info[ch].
4704 flags & EEPROM_CHANNEL_RADAR))
4705 ? "" : "not ");
4706
4707 /* Set the user_txpower_limit to the highest power
4708 * supported by any channel */
4709 if (eeprom_ch_info[ch].max_power_avg >
4710 priv->user_txpower_limit)
4711 priv->user_txpower_limit =
4712 eeprom_ch_info[ch].max_power_avg;
4713
4714 ch_info++;
4715 }
4716 }
4717
6440adb5 4718 /* Set up txpower settings in driver for all channels */
b481de9c
ZY		 4719 if (iwl3945_txpower_set_from_eeprom(priv))
4720 return -EIO;
4721
4722 return 0;
4723}
4724
849e0dce
RC		 4725/*
4726 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4727 */
4728static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
4729{
4730 kfree(priv->channel_info);
4731 priv->channel_count = 0;
4732}
4733
b481de9c
ZY		 4734/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4735 * sending probe req. This should be set long enough to hear probe responses
4736 * from more than one AP. */
f9340520
AK		 4737#define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
4738#define IWL_ACTIVE_DWELL_TIME_52 (20)
4739
4740#define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
4741#define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
b481de9c
ZY		 4742
4743/* For faster active scanning, scan will move to the next channel if fewer than
4744 * PLCP_QUIET_THRESH packets are heard on this channel within
4745 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4746 * time if it's a quiet channel (nothing responded to our probe, and there's
4747 * no other traffic).
4748 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4749#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
f9340520 4750#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
b481de9c
ZY		 4751
4752/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4753 * Must be set longer than active dwell time.
4754 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4755#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4756#define IWL_PASSIVE_DWELL_TIME_52 (10)
4757#define IWL_PASSIVE_DWELL_BASE (100)
4758#define IWL_CHANNEL_TUNE_TIME 5
4759
f9340520
AK		 4760#define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
4761
8318d78a 4762static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
f9340520
AK		 4763 enum ieee80211_band band,
4764 u8 n_probes)
b481de9c 4765{
8318d78a 4766 if (band == IEEE80211_BAND_5GHZ)
f9340520
AK		 4767 return IWL_ACTIVE_DWELL_TIME_52 +
4768 IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
b481de9c 4769 else
f9340520
AK		 4770 return IWL_ACTIVE_DWELL_TIME_24 +
4771 IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
b481de9c
ZY		 4772}
4773
8318d78a
JB		 4774static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
4775 enum ieee80211_band band)
b481de9c 4776{
8318d78a 4777 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY		 4778 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4779 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4780
bb8c093b 4781 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4782 /* If we're associated, we clamp the maximum passive
4783 * dwell time to be 98% of the beacon interval (minus
4784 * 2 * channel tune time) */
4785 passive = priv->beacon_int;
4786 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4787 passive = IWL_PASSIVE_DWELL_BASE;
4788 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4789 }
4790
b481de9c
ZY		 4791 return passive;
4792}
4793
8318d78a
JB		 4794static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
4795 enum ieee80211_band band,
f9340520 4796 u8 is_active, u8 n_probes,
bb8c093b 4797 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY		 4798{
4799 const struct ieee80211_channel *channels = NULL;
8318d78a 4800 const struct ieee80211_supported_band *sband;
bb8c093b 4801 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4802 u16 passive_dwell = 0;
4803 u16 active_dwell = 0;
4804 int added, i;
4805
8318d78a
JB		 4806 sband = iwl3945_get_band(priv, band);
4807 if (!sband)
b481de9c
ZY		 4808 return 0;
4809
8318d78a 4810 channels = sband->channels;
b481de9c 4811
f9340520 4812 active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
8318d78a 4813 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 4814
8f4807a1
AK		 4815 if (passive_dwell <= active_dwell)
4816 passive_dwell = active_dwell + 1;
4817
8318d78a 4818 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB		 4819 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4820 continue;
4821
8318d78a 4822 scan_ch->channel = channels[i].hw_value;
b481de9c 4823
8318d78a 4824 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c 4825 if (!is_channel_valid(ch_info)) {
66b5004d 4826 IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
b481de9c
ZY		 4827 scan_ch->channel);
4828 continue;
4829 }
4830
4831 if (!is_active || is_channel_passive(ch_info) ||
8318d78a 4832 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
b481de9c
ZY		 4833 scan_ch->type = 0; /* passive */
4834 else
4835 scan_ch->type = 1; /* active */
4836
f9340520
AK		 4837 if ((scan_ch->type & 1) && n_probes)
4838 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
b481de9c 4839
b481de9c
ZY		 4840 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4841 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4842
9fbab516 4843 /* Set txpower levels to defaults */
b481de9c
ZY		 4844 scan_ch->tpc.dsp_atten = 110;
4845 /* scan_pwr_info->tpc.dsp_atten; */
4846
4847 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 4848 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4849 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4850 else {
4851 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4852 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 4853 * power level:
8a1b0245 4854 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY		 4855 */
4856 }
4857
4858 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
4859 scan_ch->channel,
4860 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
4861 (scan_ch->type & 1) ?
4862 active_dwell : passive_dwell);
4863
4864 scan_ch++;
4865 added++;
4866 }
4867
4868 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
4869 return added;
4870}
4871
bb8c093b 4872static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY		 4873 struct ieee80211_rate *rates)
4874{
4875 int i;
4876
4877 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB		 4878 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
4879 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4880 rates[i].hw_value_short = i;
4881 rates[i].flags = 0;
4882 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 4883 /*
8318d78a 4884 * If CCK != 1M then set short preamble rate flag.
b481de9c 4885 */
bb8c093b 4886 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 4887 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 4888 }
b481de9c
ZY		 4889 }
4890}
4891
4892/**
bb8c093b 4893 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 4894 */
bb8c093b 4895static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 4896{
bb8c093b 4897 struct iwl3945_channel_info *ch;
8211ef78 4898 struct ieee80211_supported_band *sband;
b481de9c
ZY		 4899 struct ieee80211_channel *channels;
4900 struct ieee80211_channel *geo_ch;
4901 struct ieee80211_rate *rates;
4902 int i = 0;
b481de9c 4903
8318d78a
JB		 4904 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
4905 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY		 4906 IWL_DEBUG_INFO("Geography modes already initialized.\n");
4907 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4908 return 0;
4909 }
4910
b481de9c
ZY		 4911 channels = kzalloc(sizeof(struct ieee80211_channel) *
4912 priv->channel_count, GFP_KERNEL);
8318d78a 4913 if (!channels)
b481de9c 4914 return -ENOMEM;
b481de9c 4915
8211ef78 4916 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY		 4917 GFP_KERNEL);
4918 if (!rates) {
b481de9c
ZY		 4919 kfree(channels);
4920 return -ENOMEM;
4921 }
4922
b481de9c 4923 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW		 4924 sband = &priv->bands[IEEE80211_BAND_5GHZ];
4925 sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
4926 /* just OFDM */
4927 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
4928 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
4929
4930 sband = &priv->bands[IEEE80211_BAND_2GHZ];
4931 sband->channels = channels;
4932 /* OFDM & CCK */
4933 sband->bitrates = rates;
4934 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c
ZY		 4935
4936 priv->ieee_channels = channels;
4937 priv->ieee_rates = rates;
4938
bb8c093b 4939 iwl3945_init_hw_rates(priv, rates);
b481de9c 4940
8211ef78 4941 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY		 4942 ch = &priv->channel_info[i];
4943
8211ef78
TW		 4944 /* FIXME: might be removed if scan is OK*/
4945 if (!is_channel_valid(ch))
b481de9c 4946 continue;
b481de9c
ZY		 4947
4948 if (is_channel_a_band(ch))
8211ef78 4949 sband = &priv->bands[IEEE80211_BAND_5GHZ];
8318d78a 4950 else
8211ef78 4951 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 4952
8211ef78
TW		 4953 geo_ch = &sband->channels[sband->n_channels++];
4954
4955 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB		 4956 geo_ch->max_power = ch->max_power_avg;
4957 geo_ch->max_antenna_gain = 0xff;
7b72304d 4958 geo_ch->hw_value = ch->channel;
b481de9c
ZY		 4959
4960 if (is_channel_valid(ch)) {
8318d78a
JB		 4961 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
4962 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 4963
8318d78a
JB		 4964 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
4965 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY		 4966
4967 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 4968 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY		 4969
4970 if (ch->max_power_avg > priv->max_channel_txpower_limit)
4971 priv->max_channel_txpower_limit =
4972 ch->max_power_avg;
8211ef78 4973 } else {
8318d78a 4974 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW		 4975 }
4976
4977 /* Save flags for reg domain usage */
4978 geo_ch->orig_flags = geo_ch->flags;
4979
4980 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
4981 ch->channel, geo_ch->center_freq,
4982 is_channel_a_band(ch) ? "5.2" : "2.4",
4983 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
4984 "restricted" : "valid",
4985 geo_ch->flags);
b481de9c
ZY		 4986 }
4987
82b9a121
TW		 4988 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
4989 priv->cfg->sku & IWL_SKU_A) {
b481de9c
ZY		 4990 printk(KERN_INFO DRV_NAME
4991 ": Incorrectly detected BG card as ABG. Please send "
4992 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
4993 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 4994 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY		 4995 }
4996
4997 printk(KERN_INFO DRV_NAME
4998 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB		 4999 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
5000 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 5001
e0e0a67e
JL		 5002 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
5003 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
5004 &priv->bands[IEEE80211_BAND_2GHZ];
5005 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
5006 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
5007 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 5008
b481de9c
ZY		 5009 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5010
5011 return 0;
5012}
5013
849e0dce
RC		 5014/*
5015 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
5016 */
5017static void iwl3945_free_geos(struct iwl3945_priv *priv)
5018{
849e0dce
RC		 5019 kfree(priv->ieee_channels);
5020 kfree(priv->ieee_rates);
5021 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5022}
5023
b481de9c
ZY		 5024/******************************************************************************
5025 *
5026 * uCode download functions
5027 *
5028 ******************************************************************************/
5029
bb8c093b 5030static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c 5031{
98c92211
TW		 5032 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5033 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5034 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5035 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5036 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5037 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 5038}
5039
5040/**
bb8c093b 5041 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5042 * looking at all data.
5043 */
3ac7f146 5044static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5045{
5046 u32 val;
5047 u32 save_len = len;
5048 int rc = 0;
5049 u32 errcnt;
5050
5051 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5052
bb8c093b 5053 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5054 if (rc)
5055 return rc;
5056
bb8c093b 5057 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY		 5058
5059 errcnt = 0;
5060 for (; len > 0; len -= sizeof(u32), image++) {
5061 /* read data comes through single port, auto-incr addr */
5062 /* NOTE: Use the debugless read so we don't flood kernel log
5063 * if IWL_DL_IO is set */
bb8c093b 5064 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5065 if (val != le32_to_cpu(*image)) {
5066 IWL_ERROR("uCode INST section is invalid at "
5067 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5068 save_len - len, val, le32_to_cpu(*image));
5069 rc = -EIO;
5070 errcnt++;
5071 if (errcnt >= 20)
5072 break;
5073 }
5074 }
5075
bb8c093b 5076 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5077
5078 if (!errcnt)
bc434dd2 5079 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY		 5080
5081 return rc;
5082}
5083
5084
5085/**
bb8c093b 5086 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5087 * using sample data 100 bytes apart. If these sample points are good,
5088 * it's a pretty good bet that everything between them is good, too.
5089 */
bb8c093b 5090static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5091{
5092 u32 val;
5093 int rc = 0;
5094 u32 errcnt = 0;
5095 u32 i;
5096
5097 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5098
bb8c093b 5099 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5100 if (rc)
5101 return rc;
5102
5103 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5104 /* read data comes through single port, auto-incr addr */
5105 /* NOTE: Use the debugless read so we don't flood kernel log
5106 * if IWL_DL_IO is set */
bb8c093b 5107 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5108 i + RTC_INST_LOWER_BOUND);
bb8c093b 5109 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5110 if (val != le32_to_cpu(*image)) {
5111#if 0 /* Enable this if you want to see details */
5112 IWL_ERROR("uCode INST section is invalid at "
5113 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5114 i, val, *image);
5115#endif
5116 rc = -EIO;
5117 errcnt++;
5118 if (errcnt >= 3)
5119 break;
5120 }
5121 }
5122
bb8c093b 5123 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5124
5125 return rc;
5126}
5127
5128
5129/**
bb8c093b 5130 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 5131 * and verify its contents
5132 */
bb8c093b 5133static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY		 5134{
5135 __le32 *image;
5136 u32 len;
5137 int rc = 0;
5138
5139 /* Try bootstrap */
5140 image = (__le32 *)priv->ucode_boot.v_addr;
5141 len = priv->ucode_boot.len;
bb8c093b 5142 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5143 if (rc == 0) {
5144 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5145 return 0;
5146 }
5147
5148 /* Try initialize */
5149 image = (__le32 *)priv->ucode_init.v_addr;
5150 len = priv->ucode_init.len;
bb8c093b 5151 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5152 if (rc == 0) {
5153 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5154 return 0;
5155 }
5156
5157 /* Try runtime/protocol */
5158 image = (__le32 *)priv->ucode_code.v_addr;
5159 len = priv->ucode_code.len;
bb8c093b 5160 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5161 if (rc == 0) {
5162 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5163 return 0;
5164 }
5165
5166 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5167
9fbab516
BC		 5168 /* Since nothing seems to match, show first several data entries in
5169 * instruction SRAM, so maybe visual inspection will give a clue.
5170 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 5171 image = (__le32 *)priv->ucode_boot.v_addr;
5172 len = priv->ucode_boot.len;
bb8c093b 5173 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY		 5174
5175 return rc;
5176}
5177
5178
5179/* check contents of special bootstrap uCode SRAM */
bb8c093b 5180static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5181{
5182 __le32 *image = priv->ucode_boot.v_addr;
5183 u32 len = priv->ucode_boot.len;
5184 u32 reg;
5185 u32 val;
5186
5187 IWL_DEBUG_INFO("Begin verify bsm\n");
5188
5189 /* verify BSM SRAM contents */
bb8c093b 5190 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY		 5191 for (reg = BSM_SRAM_LOWER_BOUND;
5192 reg < BSM_SRAM_LOWER_BOUND + len;
3ac7f146 5193 reg += sizeof(u32), image++) {
bb8c093b 5194 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY		 5195 if (val != le32_to_cpu(*image)) {
5196 IWL_ERROR("BSM uCode verification failed at "
5197 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5198 BSM_SRAM_LOWER_BOUND,
5199 reg - BSM_SRAM_LOWER_BOUND, len,
5200 val, le32_to_cpu(*image));
5201 return -EIO;
5202 }
5203 }
5204
5205 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5206
5207 return 0;
5208}
5209
5210/**
bb8c093b 5211 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY		 5212 *
5213 * BSM operation:
5214 *
5215 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5216 * in special SRAM that does not power down during RFKILL. When powering back
5217 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5218 * the bootstrap program into the on-board processor, and starts it.
5219 *
5220 * The bootstrap program loads (via DMA) instructions and data for a new
5221 * program from host DRAM locations indicated by the host driver in the
5222 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5223 * automatically.
5224 *
5225 * When initializing the NIC, the host driver points the BSM to the
5226 * "initialize" uCode image. This uCode sets up some internal data, then
5227 * notifies host via "initialize alive" that it is complete.
5228 *
5229 * The host then replaces the BSM_DRAM_* pointer values to point to the
5230 * normal runtime uCode instructions and a backup uCode data cache buffer
5231 * (filled initially with starting data values for the on-board processor),
5232 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5233 * which begins normal operation.
5234 *
5235 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5236 * the backup data cache in DRAM before SRAM is powered down.
5237 *
5238 * When powering back up, the BSM loads the bootstrap program. This reloads
5239 * the runtime uCode instructions and the backup data cache into SRAM,
5240 * and re-launches the runtime uCode from where it left off.
5241 */
bb8c093b 5242static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5243{
5244 __le32 *image = priv->ucode_boot.v_addr;
5245 u32 len = priv->ucode_boot.len;
5246 dma_addr_t pinst;
5247 dma_addr_t pdata;
5248 u32 inst_len;
5249 u32 data_len;
5250 int rc;
5251 int i;
5252 u32 done;
5253 u32 reg_offset;
5254
5255 IWL_DEBUG_INFO("Begin load bsm\n");
5256
5257 /* make sure bootstrap program is no larger than BSM's SRAM size */
5258 if (len > IWL_MAX_BSM_SIZE)
5259 return -EINVAL;
5260
5261 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5262 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5263 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY		 5264 * after the "initialize" uCode has run, to point to
5265 * runtime/protocol instructions and backup data cache. */
5266 pinst = priv->ucode_init.p_addr;
5267 pdata = priv->ucode_init_data.p_addr;
5268 inst_len = priv->ucode_init.len;
5269 data_len = priv->ucode_init_data.len;
5270
bb8c093b 5271 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5272 if (rc)
5273 return rc;
5274
bb8c093b
CH		 5275 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5276 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5277 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5278 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY		 5279
5280 /* Fill BSM memory with bootstrap instructions */
5281 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5282 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5283 reg_offset += sizeof(u32), image++)
bb8c093b 5284 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY		 5285 le32_to_cpu(*image));
5286
bb8c093b 5287 rc = iwl3945_verify_bsm(priv);
b481de9c 5288 if (rc) {
bb8c093b 5289 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5290 return rc;
5291 }
5292
5293 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH		 5294 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5295 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5296 RTC_INST_LOWER_BOUND);
bb8c093b 5297 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY		 5298
5299 /* Load bootstrap code into instruction SRAM now,
5300 * to prepare to load "initialize" uCode */
bb8c093b 5301 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5302 BSM_WR_CTRL_REG_BIT_START);
5303
5304 /* Wait for load of bootstrap uCode to finish */
5305 for (i = 0; i < 100; i++) {
bb8c093b 5306 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY		 5307 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5308 break;
5309 udelay(10);
5310 }
5311 if (i < 100)
5312 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5313 else {
5314 IWL_ERROR("BSM write did not complete!\n");
5315 return -EIO;
5316 }
5317
5318 /* Enable future boot loads whenever power management unit triggers it
5319 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5320 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5321 BSM_WR_CTRL_REG_BIT_START_EN);
5322
bb8c093b 5323 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5324
5325 return 0;
5326}
5327
bb8c093b 5328static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5329{
5330 /* Remove all resets to allow NIC to operate */
bb8c093b 5331 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 5332}
5333
5334/**
bb8c093b 5335 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 5336 *
5337 * Copy into buffers for card to fetch via bus-mastering
5338 */
bb8c093b 5339static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5340{
bb8c093b 5341 struct iwl3945_ucode *ucode;
90e759d1 5342 int ret = 0;
b481de9c
ZY		 5343 const struct firmware *ucode_raw;
5344 /* firmware file name contains uCode/driver compatibility version */
4bf775cd 5345 const char *name = priv->cfg->fw_name;
b481de9c
ZY		 5346 u8 *src;
5347 size_t len;
5348 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
5349
5350 /* Ask kernel firmware_class module to get the boot firmware off disk.
5351 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW		 5352 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
5353 if (ret < 0) {
5354 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5355 name, ret);
b481de9c
ZY		 5356 goto error;
5357 }
5358
5359 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5360 name, ucode_raw->size);
5361
5362 /* Make sure that we got at least our header! */
5363 if (ucode_raw->size < sizeof(*ucode)) {
5364 IWL_ERROR("File size way too small!\n");
90e759d1 5365 ret = -EINVAL;
b481de9c
ZY		 5366 goto err_release;
5367 }
5368
5369 /* Data from ucode file: header followed by uCode images */
5370 ucode = (void *)ucode_raw->data;
5371
5372 ver = le32_to_cpu(ucode->ver);
5373 inst_size = le32_to_cpu(ucode->inst_size);
5374 data_size = le32_to_cpu(ucode->data_size);
5375 init_size = le32_to_cpu(ucode->init_size);
5376 init_data_size = le32_to_cpu(ucode->init_data_size);
5377 boot_size = le32_to_cpu(ucode->boot_size);
5378
5379 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
bc434dd2
IS		 5380 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5381 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5382 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5383 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5384 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c
ZY		 5385
5386 /* Verify size of file vs. image size info in file's header */
5387 if (ucode_raw->size < sizeof(*ucode) +
5388 inst_size + data_size + init_size +
5389 init_data_size + boot_size) {
5390
5391 IWL_DEBUG_INFO("uCode file size %d too small\n",
5392 (int)ucode_raw->size);
90e759d1 5393 ret = -EINVAL;
b481de9c
ZY		 5394 goto err_release;
5395 }
5396
5397 /* Verify that uCode images will fit in card's SRAM */
5398 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5399 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5400 inst_size);
5401 ret = -EINVAL;
b481de9c
ZY		 5402 goto err_release;
5403 }
5404
5405 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5406 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5407 data_size);
5408 ret = -EINVAL;
b481de9c
ZY		 5409 goto err_release;
5410 }
5411 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5412 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5413 init_size);
5414 ret = -EINVAL;
b481de9c
ZY		 5415 goto err_release;
5416 }
5417 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5418 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5419 init_data_size);
5420 ret = -EINVAL;
b481de9c
ZY		 5421 goto err_release;
5422 }
5423 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW		 5424 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5425 boot_size);
5426 ret = -EINVAL;
b481de9c
ZY		 5427 goto err_release;
5428 }
5429
5430 /* Allocate ucode buffers for card's bus-master loading ... */
5431
5432 /* Runtime instructions and 2 copies of data:
5433 * 1) unmodified from disk
5434 * 2) backup cache for save/restore during power-downs */
5435 priv->ucode_code.len = inst_size;
98c92211 5436 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 5437
5438 priv->ucode_data.len = data_size;
98c92211 5439 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 5440
5441 priv->ucode_data_backup.len = data_size;
98c92211 5442 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5443
90e759d1
TW		 5444 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5445 !priv->ucode_data_backup.v_addr)
5446 goto err_pci_alloc;
b481de9c
ZY		 5447
5448 /* Initialization instructions and data */
90e759d1
TW		 5449 if (init_size && init_data_size) {
5450 priv->ucode_init.len = init_size;
98c92211 5451 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 5452
5453 priv->ucode_init_data.len = init_data_size;
98c92211 5454 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 5455
5456 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5457 goto err_pci_alloc;
5458 }
b481de9c
ZY		 5459
5460 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 5461 if (boot_size) {
5462 priv->ucode_boot.len = boot_size;
98c92211 5463 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5464
90e759d1
TW		 5465 if (!priv->ucode_boot.v_addr)
5466 goto err_pci_alloc;
5467 }
b481de9c
ZY		 5468
5469 /* Copy images into buffers for card's bus-master reads ... */
5470
5471 /* Runtime instructions (first block of data in file) */
5472 src = &ucode->data[0];
5473 len = priv->ucode_code.len;
90e759d1 5474 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 5475 memcpy(priv->ucode_code.v_addr, src, len);
5476 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5477 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5478
5479 /* Runtime data (2nd block)
bb8c093b 5480 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY		 5481 src = &ucode->data[inst_size];
5482 len = priv->ucode_data.len;
90e759d1 5483 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 5484 memcpy(priv->ucode_data.v_addr, src, len);
5485 memcpy(priv->ucode_data_backup.v_addr, src, len);
5486
5487 /* Initialization instructions (3rd block) */
5488 if (init_size) {
5489 src = &ucode->data[inst_size + data_size];
5490 len = priv->ucode_init.len;
90e759d1
TW		 5491 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5492 len);
b481de9c
ZY		 5493 memcpy(priv->ucode_init.v_addr, src, len);
5494 }
5495
5496 /* Initialization data (4th block) */
5497 if (init_data_size) {
5498 src = &ucode->data[inst_size + data_size + init_size];
5499 len = priv->ucode_init_data.len;
5500 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5501 (int)len);
5502 memcpy(priv->ucode_init_data.v_addr, src, len);
5503 }
5504
5505 /* Bootstrap instructions (5th block) */
5506 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5507 len = priv->ucode_boot.len;
5508 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5509 (int)len);
5510 memcpy(priv->ucode_boot.v_addr, src, len);
5511
5512 /* We have our copies now, allow OS release its copies */
5513 release_firmware(ucode_raw);
5514 return 0;
5515
5516 err_pci_alloc:
5517 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 5518 ret = -ENOMEM;
bb8c093b 5519 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 5520
5521 err_release:
5522 release_firmware(ucode_raw);
5523
5524 error:
90e759d1 5525 return ret;
b481de9c
ZY		 5526}
5527
5528
5529/**
bb8c093b 5530 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 5531 *
5532 * Tell initialization uCode where to find runtime uCode.
5533 *
5534 * BSM registers initially contain pointers to initialization uCode.
5535 * We need to replace them to load runtime uCode inst and data,
5536 * and to save runtime data when powering down.
5537 */
bb8c093b 5538static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY		 5539{
5540 dma_addr_t pinst;
5541 dma_addr_t pdata;
5542 int rc = 0;
5543 unsigned long flags;
5544
5545 /* bits 31:0 for 3945 */
5546 pinst = priv->ucode_code.p_addr;
5547 pdata = priv->ucode_data_backup.p_addr;
5548
5549 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5550 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5551 if (rc) {
5552 spin_unlock_irqrestore(&priv->lock, flags);
5553 return rc;
5554 }
5555
5556 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH		 5557 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5558 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5559 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 5560 priv->ucode_data.len);
5561
5562 /* Inst bytecount must be last to set up, bit 31 signals uCode
5563 * that all new ptr/size info is in place */
bb8c093b 5564 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 5565 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5566
bb8c093b 5567 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5568
5569 spin_unlock_irqrestore(&priv->lock, flags);
5570
5571 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5572
5573 return rc;
5574}
5575
5576/**
bb8c093b 5577 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 5578 *
5579 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5580 *
b481de9c 5581 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 5582 */
bb8c093b 5583static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5584{
5585 /* Check alive response for "valid" sign from uCode */
5586 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5587 /* We had an error bringing up the hardware, so take it
5588 * all the way back down so we can try again */
5589 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5590 goto restart;
5591 }
5592
5593 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5594 * This is a paranoid check, because we would not have gotten the
5595 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5596 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5597 /* Runtime instruction load was bad;
5598 * take it all the way back down so we can try again */
5599 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5600 goto restart;
5601 }
5602
5603 /* Send pointers to protocol/runtime uCode image ... init code will
5604 * load and launch runtime uCode, which will send us another "Alive"
5605 * notification. */
5606 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5607 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY		 5608 /* Runtime instruction load won't happen;
5609 * take it all the way back down so we can try again */
5610 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5611 goto restart;
5612 }
5613 return;
5614
5615 restart:
5616 queue_work(priv->workqueue, &priv->restart);
5617}
5618
5619
5620/**
bb8c093b 5621 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 5622 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5623 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 5624 */
bb8c093b 5625static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5626{
5627 int rc = 0;
5628 int thermal_spin = 0;
5629 u32 rfkill;
5630
5631 IWL_DEBUG_INFO("Runtime Alive received.\n");
5632
5633 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5634 /* We had an error bringing up the hardware, so take it
5635 * all the way back down so we can try again */
5636 IWL_DEBUG_INFO("Alive failed.\n");
5637 goto restart;
5638 }
5639
5640 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5641 * This is a paranoid check, because we would not have gotten the
5642 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5643 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5644 /* Runtime instruction load was bad;
5645 * take it all the way back down so we can try again */
5646 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5647 goto restart;
5648 }
5649
bb8c093b 5650 iwl3945_clear_stations_table(priv);
b481de9c 5651
bb8c093b 5652 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5653 if (rc) {
5654 IWL_WARNING("Can not read rfkill status from adapter\n");
5655 return;
5656 }
5657
bb8c093b 5658 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 5659 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 5660 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5661
5662 if (rfkill & 0x1) {
5663 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5664 /* if rfkill is not on, then wait for thermal
5665 * sensor in adapter to kick in */
bb8c093b 5666 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY		 5667 thermal_spin++;
5668 udelay(10);
5669 }
5670
5671 if (thermal_spin)
5672 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5673 thermal_spin * 10);
5674 } else
5675 set_bit(STATUS_RF_KILL_HW, &priv->status);
5676
9fbab516 5677 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY		 5678 set_bit(STATUS_ALIVE, &priv->status);
5679
5680 /* Clear out the uCode error bit if it is set */
5681 clear_bit(STATUS_FW_ERROR, &priv->status);
5682
bb8c093b 5683 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 5684 return;
5685
36d6825b 5686 ieee80211_wake_queues(priv->hw);
b481de9c
ZY		 5687
5688 priv->active_rate = priv->rates_mask;
5689 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5690
bb8c093b 5691 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5692
bb8c093b
CH		 5693 if (iwl3945_is_associated(priv)) {
5694 struct iwl3945_rxon_cmd *active_rxon =
5695 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY		 5696
5697 memcpy(&priv->staging_rxon, &priv->active_rxon,
5698 sizeof(priv->staging_rxon));
5699 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5700 } else {
5701 /* Initialize our rx_config data */
bb8c093b 5702 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 5703 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
5704 }
5705
9fbab516 5706 /* Configure Bluetooth device coexistence support */
bb8c093b 5707 iwl3945_send_bt_config(priv);
b481de9c
ZY		 5708
5709 /* Configure the adapter for unassociated operation */
bb8c093b 5710 iwl3945_commit_rxon(priv);
b481de9c 5711
b481de9c
ZY		 5712 iwl3945_reg_txpower_periodic(priv);
5713
fe00b5a5
RC		 5714 iwl3945_led_register(priv);
5715
b481de9c 5716 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5717 set_bit(STATUS_READY, &priv->status);
5a66926a 5718 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 5719
5720 if (priv->error_recovering)
bb8c093b 5721 iwl3945_error_recovery(priv);
b481de9c 5722
84363e6e 5723 ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
b481de9c
ZY		 5724 return;
5725
5726 restart:
5727 queue_work(priv->workqueue, &priv->restart);
5728}
5729
bb8c093b 5730static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 5731
bb8c093b 5732static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5733{
5734 unsigned long flags;
5735 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5736 struct ieee80211_conf *conf = NULL;
5737
5738 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5739
5740 conf = ieee80211_get_hw_conf(priv->hw);
5741
5742 if (!exit_pending)
5743 set_bit(STATUS_EXIT_PENDING, &priv->status);
5744
ab53d8af 5745 iwl3945_led_unregister(priv);
bb8c093b 5746 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5747
5748 /* Unblock any waiting calls */
5749 wake_up_interruptible_all(&priv->wait_command_queue);
5750
b481de9c
ZY		 5751 /* Wipe out the EXIT_PENDING status bit if we are not actually
5752 * exiting the module */
5753 if (!exit_pending)
5754 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5755
5756 /* stop and reset the on-board processor */
bb8c093b 5757 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 5758
5759 /* tell the device to stop sending interrupts */
0359facc 5760 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5761 iwl3945_disable_interrupts(priv);
0359facc
MA		 5762 spin_unlock_irqrestore(&priv->lock, flags);
5763 iwl_synchronize_irq(priv);
b481de9c
ZY		 5764
5765 if (priv->mac80211_registered)
5766 ieee80211_stop_queues(priv->hw);
5767
bb8c093b 5768 /* If we have not previously called iwl3945_init() then
b481de9c 5769 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 5770 if (!iwl3945_is_init(priv)) {
b481de9c
ZY		 5771 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5772 STATUS_RF_KILL_HW |
5773 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5774 STATUS_RF_KILL_SW |
9788864e
RC		 5775 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5776 STATUS_GEO_CONFIGURED |
b481de9c 5777 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
ebef2008
AK		 5778 STATUS_IN_SUSPEND |
5779 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5780 STATUS_EXIT_PENDING;
b481de9c
ZY		 5781 goto exit;
5782 }
5783
5784 /* ...otherwise clear out all the status bits but the RF Kill and
5785 * SUSPEND bits and continue taking the NIC down. */
5786 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5787 STATUS_RF_KILL_HW |
5788 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5789 STATUS_RF_KILL_SW |
9788864e
RC		 5790 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5791 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5792 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5793 STATUS_IN_SUSPEND |
5794 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK		 5795 STATUS_FW_ERROR |
5796 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5797 STATUS_EXIT_PENDING;
b481de9c
ZY		 5798
5799 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5800 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 5801 spin_unlock_irqrestore(&priv->lock, flags);
5802
bb8c093b
CH		 5803 iwl3945_hw_txq_ctx_stop(priv);
5804 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY		 5805
5806 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 5807 if (!iwl3945_grab_nic_access(priv)) {
5808 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5809 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 5810 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5811 }
5812 spin_unlock_irqrestore(&priv->lock, flags);
5813
5814 udelay(5);
5815
bb8c093b
CH		 5816 iwl3945_hw_nic_stop_master(priv);
5817 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
5818 iwl3945_hw_nic_reset(priv);
b481de9c
ZY		 5819
5820 exit:
bb8c093b 5821 memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
b481de9c
ZY		 5822
5823 if (priv->ibss_beacon)
5824 dev_kfree_skb(priv->ibss_beacon);
5825 priv->ibss_beacon = NULL;
5826
5827 /* clear out any free frames */
bb8c093b 5828 iwl3945_clear_free_frames(priv);
b481de9c
ZY		 5829}
5830
bb8c093b 5831static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5832{
5833 mutex_lock(&priv->mutex);
bb8c093b 5834 __iwl3945_down(priv);
b481de9c 5835 mutex_unlock(&priv->mutex);
b24d22b1 5836
bb8c093b 5837 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY		 5838}
5839
5840#define MAX_HW_RESTARTS 5
5841
bb8c093b 5842static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c
ZY		 5843{
5844 int rc, i;
5845
5846 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5847 IWL_WARNING("Exit pending; will not bring the NIC up\n");
5848 return -EIO;
5849 }
5850
5851 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
5852 IWL_WARNING("Radio disabled by SW RF kill (module "
5853 "parameter)\n");
e655b9f0
ZY		 5854 return -ENODEV;
5855 }
5856
e903fbd4
RC		 5857 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
5858 IWL_ERROR("ucode not available for device bringup\n");
5859 return -EIO;
5860 }
5861
e655b9f0
ZY		 5862 /* If platform's RF_KILL switch is NOT set to KILL */
5863 if (iwl3945_read32(priv, CSR_GP_CNTRL) &
5864 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5865 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5866 else {
5867 set_bit(STATUS_RF_KILL_HW, &priv->status);
5868 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
5869 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
5870 return -ENODEV;
5871 }
b481de9c 5872 }
80fcc9e2 5873
bb8c093b 5874 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 5875
bb8c093b 5876 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY		 5877 if (rc) {
5878 IWL_ERROR("Unable to int nic\n");
5879 return rc;
5880 }
5881
5882 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH		 5883 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5884 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 5885 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5886
5887 /* clear (again), then enable host interrupts */
bb8c093b
CH		 5888 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
5889 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 5890
5891 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH		 5892 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5893 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 5894
5895 /* Copy original ucode data image from disk into backup cache.
5896 * This will be used to initialize the on-board processor's
5897 * data SRAM for a clean start when the runtime program first loads. */
5898 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 5899 priv->ucode_data.len);
b481de9c 5900
e655b9f0
ZY		 5901 /* We return success when we resume from suspend and rf_kill is on. */
5902 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
5903 return 0;
5904
b481de9c
ZY		 5905 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5906
bb8c093b 5907 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5908
5909 /* load bootstrap state machine,
5910 * load bootstrap program into processor's memory,
5911 * prepare to load the "initialize" uCode */
bb8c093b 5912 rc = iwl3945_load_bsm(priv);
b481de9c
ZY		 5913
5914 if (rc) {
5915 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
5916 continue;
5917 }
5918
5919 /* start card; "initialize" will load runtime ucode */
bb8c093b 5920 iwl3945_nic_start(priv);
b481de9c 5921
b481de9c
ZY		 5922 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
5923
5924 return 0;
5925 }
5926
5927 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 5928 __iwl3945_down(priv);
ebef2008 5929 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 5930
5931 /* tried to restart and config the device for as long as our
5932 * patience could withstand */
5933 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
5934 return -EIO;
5935}
5936
5937
5938/*****************************************************************************
5939 *
5940 * Workqueue callbacks
5941 *
5942 *****************************************************************************/
5943
bb8c093b 5944static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 5945{
bb8c093b
CH		 5946 struct iwl3945_priv *priv =
5947 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY		 5948
5949 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5950 return;
5951
5952 mutex_lock(&priv->mutex);
bb8c093b 5953 iwl3945_init_alive_start(priv);
b481de9c
ZY		 5954 mutex_unlock(&priv->mutex);
5955}
5956
bb8c093b 5957static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 5958{
bb8c093b
CH		 5959 struct iwl3945_priv *priv =
5960 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY		 5961
5962 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5963 return;
5964
5965 mutex_lock(&priv->mutex);
bb8c093b 5966 iwl3945_alive_start(priv);
b481de9c
ZY		 5967 mutex_unlock(&priv->mutex);
5968}
5969
bb8c093b 5970static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 5971{
bb8c093b 5972 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY		 5973
5974 wake_up_interruptible(&priv->wait_command_queue);
5975
5976 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5977 return;
5978
5979 mutex_lock(&priv->mutex);
5980
bb8c093b 5981 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 5982 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
5983 "HW and/or SW RF Kill no longer active, restarting "
5984 "device\n");
5985 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
5986 queue_work(priv->workqueue, &priv->restart);
5987 } else {
5988
5989 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
5990 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
5991 "disabled by SW switch\n");
5992 else
5993 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
5994 "Kill switch must be turned off for "
5995 "wireless networking to work.\n");
5996 }
ebef2008 5997
b481de9c 5998 mutex_unlock(&priv->mutex);
80fcc9e2 5999 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 6000}
6001
5ec03976
AK		 6002static void iwl3945_bg_set_monitor(struct work_struct *work)
6003{
6004 struct iwl3945_priv *priv = container_of(work,
6005 struct iwl3945_priv, set_monitor);
6006
6007 IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
6008
6009 mutex_lock(&priv->mutex);
6010
6011 if (!iwl3945_is_ready(priv))
6012 IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
6013 else
05c914fe 6014 if (iwl3945_set_mode(priv, NL80211_IFTYPE_MONITOR) != 0)
5ec03976
AK		 6015 IWL_ERROR("iwl3945_set_mode() failed\n");
6016
6017 mutex_unlock(&priv->mutex);
6018}
6019
b481de9c
ZY		 6020#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6021
bb8c093b 6022static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6023{
bb8c093b
CH		 6024 struct iwl3945_priv *priv =
6025 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY		 6026
6027 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6028 return;
6029
6030 mutex_lock(&priv->mutex);
6031 if (test_bit(STATUS_SCANNING, &priv->status) ||
6032 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6033 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6034 "Scan completion watchdog resetting adapter (%dms)\n",
6035 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6036
b481de9c 6037 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6038 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6039 }
6040 mutex_unlock(&priv->mutex);
6041}
6042
bb8c093b 6043static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6044{
bb8c093b
CH		 6045 struct iwl3945_priv *priv =
6046 container_of(data, struct iwl3945_priv, request_scan);
6047 struct iwl3945_host_cmd cmd = {
b481de9c 6048 .id = REPLY_SCAN_CMD,
bb8c093b 6049 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY		 6050 .meta.flags = CMD_SIZE_HUGE,
6051 };
6052 int rc = 0;
bb8c093b 6053 struct iwl3945_scan_cmd *scan;
b481de9c 6054 struct ieee80211_conf *conf = NULL;
f9340520 6055 u8 n_probes = 2;
8318d78a 6056 enum ieee80211_band band;
b481de9c
ZY		 6057
6058 conf = ieee80211_get_hw_conf(priv->hw);
6059
6060 mutex_lock(&priv->mutex);
6061
bb8c093b 6062 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 6063 IWL_WARNING("request scan called when driver not ready.\n");
6064 goto done;
6065 }
6066
6067 /* Make sure the scan wasn't cancelled before this queued work
6068 * was given the chance to run... */
6069 if (!test_bit(STATUS_SCANNING, &priv->status))
6070 goto done;
6071
6072 /* This should never be called or scheduled if there is currently
6073 * a scan active in the hardware. */
6074 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6075 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6076 "Ignoring second request.\n");
6077 rc = -EIO;
6078 goto done;
6079 }
6080
6081 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6082 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6083 goto done;
6084 }
6085
6086 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6087 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6088 goto done;
6089 }
6090
bb8c093b 6091 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6092 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6093 goto done;
6094 }
6095
6096 if (!test_bit(STATUS_READY, &priv->status)) {
6097 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6098 goto done;
6099 }
6100
6101 if (!priv->scan_bands) {
6102 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6103 goto done;
6104 }
6105
6106 if (!priv->scan) {
bb8c093b 6107 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY		 6108 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6109 if (!priv->scan) {
6110 rc = -ENOMEM;
6111 goto done;
6112 }
6113 }
6114 scan = priv->scan;
bb8c093b 6115 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 6116
6117 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6118 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6119
bb8c093b 6120 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 6121 u16 interval = 0;
6122 u32 extra;
6123 u32 suspend_time = 100;
6124 u32 scan_suspend_time = 100;
6125 unsigned long flags;
6126
6127 IWL_DEBUG_INFO("Scanning while associated...\n");
6128
6129 spin_lock_irqsave(&priv->lock, flags);
6130 interval = priv->beacon_int;
6131 spin_unlock_irqrestore(&priv->lock, flags);
6132
6133 scan->suspend_time = 0;
15e869d8 6134 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 6135 if (!interval)
6136 interval = suspend_time;
6137 /*
6138 * suspend time format:
6139 * 0-19: beacon interval in usec (time before exec.)
6140 * 20-23: 0
6141 * 24-31: number of beacons (suspend between channels)
6142 */
6143
6144 extra = (suspend_time / interval) << 24;
6145 scan_suspend_time = 0xFF0FFFFF &
6146 (extra | ((suspend_time % interval) * 1024));
6147
6148 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6149 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6150 scan_suspend_time, interval);
6151 }
6152
6153 /* We should add the ability for user to lock to PASSIVE ONLY */
6154 if (priv->one_direct_scan) {
6155 IWL_DEBUG_SCAN
6156 ("Kicking off one direct scan for '%s'\n",
7e272fcf 6157 escape_ssid(priv->direct_ssid, priv->direct_ssid_len));
b481de9c
ZY		 6158 scan->direct_scan[0].id = WLAN_EID_SSID;
6159 scan->direct_scan[0].len = priv->direct_ssid_len;
6160 memcpy(scan->direct_scan[0].ssid,
6161 priv->direct_ssid, priv->direct_ssid_len);
f9340520 6162 n_probes++;
bb8c093b 6163 } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
786b4557
BM		 6164 IWL_DEBUG_SCAN
6165 ("Kicking off one direct scan for '%s' when not associated\n",
7e272fcf 6166 escape_ssid(priv->essid, priv->essid_len));
b481de9c
ZY		 6167 scan->direct_scan[0].id = WLAN_EID_SSID;
6168 scan->direct_scan[0].len = priv->essid_len;
6169 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
f9340520
AK		 6170 n_probes++;
6171 } else
786b4557 6172 IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
b481de9c
ZY		 6173
6174 /* We don't build a direct scan probe request; the uCode will do
6175 * that based on the direct_mask added to each channel entry */
6176 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6177 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
18904f58 6178 IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
b481de9c
ZY		 6179 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6180 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6181 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6182
6183 /* flags + rate selection */
6184
66b5004d 6185 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY		 6186 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6187 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6188 scan->good_CRC_th = 0;
8318d78a 6189 band = IEEE80211_BAND_2GHZ;
66b5004d 6190 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c
ZY		 6191 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6192 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6193 band = IEEE80211_BAND_5GHZ;
66b5004d 6194 } else {
b481de9c
ZY		 6195 IWL_WARNING("Invalid scan band count\n");
6196 goto done;
6197 }
6198
6199 /* select Rx antennas */
6200 scan->flags |= iwl3945_get_antenna_flags(priv);
6201
05c914fe 6202 if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
b481de9c
ZY		 6203 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6204
f9340520
AK		 6205 scan->channel_count =
6206 iwl3945_get_channels_for_scan(priv, band, 1, /* active */
6207 n_probes,
6208 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c
ZY		 6209
6210 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6211 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY		 6212 cmd.data = scan;
6213 scan->len = cpu_to_le16(cmd.len);
6214
6215 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6216 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 6217 if (rc)
6218 goto done;
6219
6220 queue_delayed_work(priv->workqueue, &priv->scan_check,
6221 IWL_SCAN_CHECK_WATCHDOG);
6222
6223 mutex_unlock(&priv->mutex);
6224 return;
6225
6226 done:
01ebd063 6227 /* inform mac80211 scan aborted */
b481de9c
ZY		 6228 queue_work(priv->workqueue, &priv->scan_completed);
6229 mutex_unlock(&priv->mutex);
6230}
6231
bb8c093b 6232static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6233{
bb8c093b 6234 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY		 6235
6236 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6237 return;
6238
6239 mutex_lock(&priv->mutex);
bb8c093b 6240 __iwl3945_up(priv);
b481de9c 6241 mutex_unlock(&priv->mutex);
80fcc9e2 6242 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 6243}
6244
bb8c093b 6245static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6246{
bb8c093b 6247 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY		 6248
6249 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6250 return;
6251
bb8c093b 6252 iwl3945_down(priv);
b481de9c
ZY		 6253 queue_work(priv->workqueue, &priv->up);
6254}
6255
bb8c093b 6256static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6257{
bb8c093b
CH		 6258 struct iwl3945_priv *priv =
6259 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY		 6260
6261 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6262 return;
6263
6264 mutex_lock(&priv->mutex);
bb8c093b 6265 iwl3945_rx_replenish(priv);
b481de9c
ZY		 6266 mutex_unlock(&priv->mutex);
6267}
6268
7878a5a4
MA		 6269#define IWL_DELAY_NEXT_SCAN (HZ*2)
6270
cd56d331 6271static void iwl3945_post_associate(struct iwl3945_priv *priv)
b481de9c 6272{
b481de9c
ZY		 6273 int rc = 0;
6274 struct ieee80211_conf *conf = NULL;
6275
05c914fe 6276 if (priv->iw_mode == NL80211_IFTYPE_AP) {
3ac7f146 6277 IWL_ERROR("%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 6278 return;
6279 }
6280
6281
e174961c
JB		 6282 IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
6283 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY		 6284
6285 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6286 return;
6287
322a9811 6288 if (!priv->vif || !priv->is_open)
6ef89d0a 6289 return;
322a9811 6290
bb8c093b 6291 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6292
b481de9c
ZY		 6293 conf = ieee80211_get_hw_conf(priv->hw);
6294
6295 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6296 iwl3945_commit_rxon(priv);
b481de9c 6297
bb8c093b
CH		 6298 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6299 iwl3945_setup_rxon_timing(priv);
6300 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6301 sizeof(priv->rxon_timing), &priv->rxon_timing);
6302 if (rc)
6303 IWL_WARNING("REPLY_RXON_TIMING failed - "
6304 "Attempting to continue.\n");
6305
6306 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6307
6308 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6309
6310 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6311 priv->assoc_id, priv->beacon_int);
6312
6313 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6314 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6315 else
6316 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6317
6318 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6319 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6320 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6321 else
6322 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6323
05c914fe 6324 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 6325 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6326
6327 }
6328
bb8c093b 6329 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6330
6331 switch (priv->iw_mode) {
05c914fe 6332 case NL80211_IFTYPE_STATION:
bb8c093b 6333 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 6334 break;
6335
05c914fe 6336 case NL80211_IFTYPE_ADHOC:
b481de9c
ZY		 6337
6338 /* clear out the station table */
bb8c093b 6339 iwl3945_clear_stations_table(priv);
b481de9c 6340
bb8c093b
CH		 6341 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
6342 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 6343 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 6344 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY		 6345 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6346 CMD_ASYNC);
bb8c093b
CH		 6347 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6348 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6349
6350 break;
6351
6352 default:
6353 IWL_ERROR("%s Should not be called in %d mode\n",
3ac7f146 6354 __func__, priv->iw_mode);
b481de9c
ZY		 6355 break;
6356 }
6357
bb8c093b 6358 iwl3945_activate_qos(priv, 0);
292ae174 6359
7878a5a4
MA		 6360 /* we have just associated, don't start scan too early */
6361 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK		 6362}
6363
bb8c093b 6364static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6365{
bb8c093b 6366 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6367
bb8c093b 6368 if (!iwl3945_is_ready(priv))
b481de9c
ZY		 6369 return;
6370
6371 mutex_lock(&priv->mutex);
6372
6373 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6374 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6375
6376 mutex_unlock(&priv->mutex);
6377}
6378
e8975581 6379static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
76bb77e0 6380
bb8c093b 6381static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6382{
bb8c093b
CH		 6383 struct iwl3945_priv *priv =
6384 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY		 6385
6386 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6387
6388 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6389 return;
6390
a0646470 6391 if (test_bit(STATUS_CONF_PENDING, &priv->status))
e8975581 6392 iwl3945_mac_config(priv->hw, 0);
76bb77e0 6393
b481de9c
ZY		 6394 ieee80211_scan_completed(priv->hw);
6395
6396 /* Since setting the TXPOWER may have been deferred while
6397 * performing the scan, fire one off */
6398 mutex_lock(&priv->mutex);
bb8c093b 6399 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 6400 mutex_unlock(&priv->mutex);
6401}
6402
6403/*****************************************************************************
6404 *
6405 * mac80211 entry point functions
6406 *
6407 *****************************************************************************/
6408
5a66926a
ZY		 6409#define UCODE_READY_TIMEOUT (2 * HZ)
6410
bb8c093b 6411static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6412{
bb8c093b 6413 struct iwl3945_priv *priv = hw->priv;
5a66926a 6414 int ret;
b481de9c
ZY		 6415
6416 IWL_DEBUG_MAC80211("enter\n");
6417
5a66926a
ZY		 6418 if (pci_enable_device(priv->pci_dev)) {
6419 IWL_ERROR("Fail to pci_enable_device\n");
6420 return -ENODEV;
6421 }
6422 pci_restore_state(priv->pci_dev);
6423 pci_enable_msi(priv->pci_dev);
6424
6425 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6426 DRV_NAME, priv);
6427 if (ret) {
6428 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6429 goto out_disable_msi;
6430 }
6431
b481de9c
ZY		 6432 /* we should be verifying the device is ready to be opened */
6433 mutex_lock(&priv->mutex);
6434
5a66926a
ZY		 6435 memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
6436 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6437 * ucode filename and max sizes are card-specific. */
6438
6439 if (!priv->ucode_code.len) {
6440 ret = iwl3945_read_ucode(priv);
6441 if (ret) {
6442 IWL_ERROR("Could not read microcode: %d\n", ret);
6443 mutex_unlock(&priv->mutex);
6444 goto out_release_irq;
6445 }
6446 }
b481de9c 6447
e655b9f0 6448 ret = __iwl3945_up(priv);
b481de9c
ZY		 6449
6450 mutex_unlock(&priv->mutex);
5a66926a 6451
80fcc9e2
AG		 6452 iwl3945_rfkill_set_hw_state(priv);
6453
e655b9f0
ZY		 6454 if (ret)
6455 goto out_release_irq;
6456
6457 IWL_DEBUG_INFO("Start UP work.\n");
6458
6459 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6460 return 0;
6461
5a66926a
ZY		 6462 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6463 * mac80211 will not be run successfully. */
6464 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6465 test_bit(STATUS_READY, &priv->status),
6466 UCODE_READY_TIMEOUT);
6467 if (!ret) {
6468 if (!test_bit(STATUS_READY, &priv->status)) {
6469 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6470 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6471 ret = -ETIMEDOUT;
6472 goto out_release_irq;
6473 }
6474 }
6475
e655b9f0 6476 priv->is_open = 1;
b481de9c
ZY		 6477 IWL_DEBUG_MAC80211("leave\n");
6478 return 0;
5a66926a
ZY		 6479
6480out_release_irq:
6481 free_irq(priv->pci_dev->irq, priv);
6482out_disable_msi:
6483 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY		 6484 pci_disable_device(priv->pci_dev);
6485 priv->is_open = 0;
6486 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6487 return ret;
b481de9c
ZY		 6488}
6489
bb8c093b 6490static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6491{
bb8c093b 6492 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6493
6494 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6495
e655b9f0
ZY		 6496 if (!priv->is_open) {
6497 IWL_DEBUG_MAC80211("leave - skip\n");
6498 return;
6499 }
6500
b481de9c 6501 priv->is_open = 0;
5a66926a
ZY		 6502
6503 if (iwl3945_is_ready_rf(priv)) {
e655b9f0
ZY		 6504 /* stop mac, cancel any scan request and clear
6505 * RXON_FILTER_ASSOC_MSK BIT
6506 */
5a66926a
ZY		 6507 mutex_lock(&priv->mutex);
6508 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f 6509 mutex_unlock(&priv->mutex);
fde3571f
MA		 6510 }
6511
5a66926a
ZY		 6512 iwl3945_down(priv);
6513
6514 flush_workqueue(priv->workqueue);
6515 free_irq(priv->pci_dev->irq, priv);
6516 pci_disable_msi(priv->pci_dev);
6517 pci_save_state(priv->pci_dev);
6518 pci_disable_device(priv->pci_dev);
6ef89d0a 6519
b481de9c 6520 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6521}
6522
e039fa4a 6523static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6524{
bb8c093b 6525 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6526
6527 IWL_DEBUG_MAC80211("enter\n");
6528
b481de9c 6529 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 6530 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 6531
e039fa4a 6532 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY		 6533 dev_kfree_skb_any(skb);
6534
6535 IWL_DEBUG_MAC80211("leave\n");
6536 return 0;
6537}
6538
bb8c093b 6539static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6540 struct ieee80211_if_init_conf *conf)
6541{
bb8c093b 6542 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6543 unsigned long flags;
6544
32bfd35d 6545 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6546
32bfd35d
JB		 6547 if (priv->vif) {
6548 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6549 return -EOPNOTSUPP;
b481de9c
ZY		 6550 }
6551
6552 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6553 priv->vif = conf->vif;
b481de9c
ZY		 6554
6555 spin_unlock_irqrestore(&priv->lock, flags);
6556
6557 mutex_lock(&priv->mutex);
864792e3
TW		 6558
6559 if (conf->mac_addr) {
e174961c 6560 IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
864792e3
TW		 6561 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6562 }
6563
5a66926a
ZY		 6564 if (iwl3945_is_ready(priv))
6565 iwl3945_set_mode(priv, conf->type);
b481de9c 6566
b481de9c
ZY		 6567 mutex_unlock(&priv->mutex);
6568
5a66926a 6569 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6570 return 0;
6571}
6572
6573/**
bb8c093b 6574 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY		 6575 *
6576 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6577 * be set inappropriately and the driver currently sets the hardware up to
6578 * use it whenever needed.
6579 */
e8975581 6580static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
b481de9c 6581{
bb8c093b
CH		 6582 struct iwl3945_priv *priv = hw->priv;
6583 const struct iwl3945_channel_info *ch_info;
e8975581 6584 struct ieee80211_conf *conf = &hw->conf;
b481de9c 6585 unsigned long flags;
76bb77e0 6586 int ret = 0;
b481de9c
ZY		 6587
6588 mutex_lock(&priv->mutex);
8318d78a 6589 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6590
bb8c093b 6591 if (!iwl3945_is_ready(priv)) {
b481de9c 6592 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY		 6593 ret = -EIO;
6594 goto out;
b481de9c
ZY		 6595 }
6596
bb8c093b 6597 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c 6598 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY		 6599 IWL_DEBUG_MAC80211("leave - scanning\n");
6600 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6601 mutex_unlock(&priv->mutex);
a0646470 6602 return 0;
b481de9c
ZY		 6603 }
6604
6605 spin_lock_irqsave(&priv->lock, flags);
6606
8318d78a
JB		 6607 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
6608 conf->channel->hw_value);
b481de9c 6609 if (!is_channel_valid(ch_info)) {
66b5004d 6610 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
8318d78a 6611 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY		 6612 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6613 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY		 6614 ret = -EINVAL;
6615 goto out;
b481de9c
ZY		 6616 }
6617
8318d78a 6618 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 6619
8318d78a 6620 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY		 6621
6622 /* The list of supported rates and rate mask can be different
6623 * for each phymode; since the phymode may have changed, reset
6624 * the rate mask to what mac80211 lists */
bb8c093b 6625 iwl3945_set_rate(priv);
b481de9c
ZY		 6626
6627 spin_unlock_irqrestore(&priv->lock, flags);
6628
6629#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6630 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6631 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 6632 goto out;
b481de9c
ZY		 6633 }
6634#endif
6635
bb8c093b 6636 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 6637
6638 if (!conf->radio_enabled) {
6639 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6640 goto out;
b481de9c
ZY		 6641 }
6642
bb8c093b 6643 if (iwl3945_is_rfkill(priv)) {
b481de9c 6644 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY		 6645 ret = -EIO;
6646 goto out;
b481de9c
ZY		 6647 }
6648
bb8c093b 6649 iwl3945_set_rate(priv);
b481de9c
ZY		 6650
6651 if (memcmp(&priv->active_rxon,
6652 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 6653 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6654 else
6655 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6656
6657 IWL_DEBUG_MAC80211("leave\n");
6658
76bb77e0 6659out:
a0646470 6660 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6661 mutex_unlock(&priv->mutex);
76bb77e0 6662 return ret;
b481de9c
ZY		 6663}
6664
bb8c093b 6665static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY		 6666{
6667 int rc = 0;
6668
d986bcd1 6669 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 6670 return;
6671
6672 /* The following should be done only at AP bring up */
5d1e2325 6673 if (!(iwl3945_is_associated(priv))) {
b481de9c
ZY		 6674
6675 /* RXON - unassoc (to set timing command) */
6676 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6677 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6678
6679 /* RXON Timing */
bb8c093b
CH		 6680 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6681 iwl3945_setup_rxon_timing(priv);
6682 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6683 sizeof(priv->rxon_timing), &priv->rxon_timing);
6684 if (rc)
6685 IWL_WARNING("REPLY_RXON_TIMING failed - "
6686 "Attempting to continue.\n");
6687
6688 /* FIXME: what should be the assoc_id for AP? */
6689 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6690 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6691 priv->staging_rxon.flags |=
6692 RXON_FLG_SHORT_PREAMBLE_MSK;
6693 else
6694 priv->staging_rxon.flags &=
6695 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6696
6697 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6698 if (priv->assoc_capability &
6699 WLAN_CAPABILITY_SHORT_SLOT_TIME)
6700 priv->staging_rxon.flags |=
6701 RXON_FLG_SHORT_SLOT_MSK;
6702 else
6703 priv->staging_rxon.flags &=
6704 ~RXON_FLG_SHORT_SLOT_MSK;
6705
05c914fe 6706 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 6707 priv->staging_rxon.flags &=
6708 ~RXON_FLG_SHORT_SLOT_MSK;
6709 }
6710 /* restore RXON assoc */
6711 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH		 6712 iwl3945_commit_rxon(priv);
6713 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 6714 }
bb8c093b 6715 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6716
6717 /* FIXME - we need to add code here to detect a totally new
6718 * configuration, reset the AP, unassoc, rxon timing, assoc,
6719 * clear sta table, add BCAST sta... */
6720}
6721
9d139c81
JB		 6722/* temporary */
6723static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb);
6724
32bfd35d
JB		 6725static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6726 struct ieee80211_vif *vif,
b481de9c
ZY		 6727 struct ieee80211_if_conf *conf)
6728{
bb8c093b 6729 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6730 unsigned long flags;
6731 int rc;
6732
6733 if (conf == NULL)
6734 return -EIO;
6735
b716bb91
EG		 6736 if (priv->vif != vif) {
6737 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b716bb91
EG		 6738 return 0;
6739 }
6740
9d139c81 6741 /* handle this temporarily here */
05c914fe 6742 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
9d139c81
JB		 6743 conf->changed & IEEE80211_IFCC_BEACON) {
6744 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
6745 if (!beacon)
6746 return -ENOMEM;
6747 rc = iwl3945_mac_beacon_update(hw, beacon);
6748 if (rc)
6749 return rc;
6750 }
6751
4150c572
JB		 6752 /* XXX: this MUST use conf->mac_addr */
6753
05c914fe 6754 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
9d139c81 6755 (!conf->ssid_len)) {
b481de9c
ZY		 6756 IWL_DEBUG_MAC80211
6757 ("Leaving in AP mode because HostAPD is not ready.\n");
6758 return 0;
6759 }
6760
5a66926a
ZY		 6761 if (!iwl3945_is_alive(priv))
6762 return -EAGAIN;
6763
b481de9c
ZY		 6764 mutex_lock(&priv->mutex);
6765
b481de9c 6766 if (conf->bssid)
e174961c 6767 IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
b481de9c 6768
4150c572
JB		 6769/*
6770 * very dubious code was here; the probe filtering flag is never set:
6771 *
b481de9c
ZY		 6772 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6773 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6774 */
b481de9c 6775
05c914fe 6776 if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY		 6777 if (!conf->bssid) {
6778 conf->bssid = priv->mac_addr;
6779 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
e174961c
JB		 6780 IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
6781 conf->bssid);
b481de9c
ZY		 6782 }
6783 if (priv->ibss_beacon)
6784 dev_kfree_skb(priv->ibss_beacon);
6785
9d139c81 6786 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
b481de9c
ZY		 6787 }
6788
fde3571f
MA		 6789 if (iwl3945_is_rfkill(priv))
6790 goto done;
6791
b481de9c
ZY		 6792 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6793 !is_multicast_ether_addr(conf->bssid)) {
6794 /* If there is currently a HW scan going on in the background
6795 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6796 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 6797 IWL_WARNING("Aborted scan still in progress "
6798 "after 100ms\n");
6799 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6800 mutex_unlock(&priv->mutex);
6801 return -EAGAIN;
6802 }
6803 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
6804
6805 /* TODO: Audit driver for usage of these members and see
6806 * if mac80211 deprecates them (priv->bssid looks like it
6807 * shouldn't be there, but I haven't scanned the IBSS code
6808 * to verify) - jpk */
6809 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6810
05c914fe 6811 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b 6812 iwl3945_config_ap(priv);
b481de9c 6813 else {
bb8c093b 6814 rc = iwl3945_commit_rxon(priv);
05c914fe 6815 if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
bb8c093b 6816 iwl3945_add_station(priv,
556f8db7 6817 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY		 6818 }
6819
6820 } else {
bb8c093b 6821 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 6822 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6823 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6824 }
6825
fde3571f 6826 done:
b481de9c
ZY		 6827 spin_lock_irqsave(&priv->lock, flags);
6828 if (!conf->ssid_len)
6829 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
6830 else
6831 memcpy(priv->essid, conf->ssid, conf->ssid_len);
6832
6833 priv->essid_len = conf->ssid_len;
6834 spin_unlock_irqrestore(&priv->lock, flags);
6835
6836 IWL_DEBUG_MAC80211("leave\n");
6837 mutex_unlock(&priv->mutex);
6838
6839 return 0;
6840}
6841
bb8c093b 6842static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 6843 unsigned int changed_flags,
6844 unsigned int *total_flags,
6845 int mc_count, struct dev_addr_list *mc_list)
6846{
5ec03976 6847 struct iwl3945_priv *priv = hw->priv;
25b3f57c
RF		 6848
6849 if (changed_flags & (*total_flags) & FIF_OTHER_BSS) {
6850 IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
05c914fe 6851 NL80211_IFTYPE_MONITOR,
25b3f57c
RF		 6852 changed_flags, *total_flags);
6853 /* queue work 'cuz mac80211 is holding a lock which
6854 * prevents us from issuing (synchronous) f/w cmds */
6855 queue_work(priv->workqueue, &priv->set_monitor);
5ec03976 6856 }
25b3f57c
RF		 6857 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI |
6858 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4150c572
JB		 6859}
6860
bb8c093b 6861static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6862 struct ieee80211_if_init_conf *conf)
6863{
bb8c093b 6864 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6865
6866 IWL_DEBUG_MAC80211("enter\n");
6867
6868 mutex_lock(&priv->mutex);
6ef89d0a 6869
fde3571f
MA		 6870 if (iwl3945_is_ready_rf(priv)) {
6871 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f
MA		 6872 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6873 iwl3945_commit_rxon(priv);
6874 }
32bfd35d
JB		 6875 if (priv->vif == conf->vif) {
6876 priv->vif = NULL;
b481de9c
ZY		 6877 memset(priv->bssid, 0, ETH_ALEN);
6878 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
6879 priv->essid_len = 0;
6880 }
6881 mutex_unlock(&priv->mutex);
6882
6883 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6884}
6885
cd56d331
AK		 6886#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
6887
6888static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
6889 struct ieee80211_vif *vif,
6890 struct ieee80211_bss_conf *bss_conf,
6891 u32 changes)
6892{
6893 struct iwl3945_priv *priv = hw->priv;
6894
6895 IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
6896
6897 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
6898 IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
6899 bss_conf->use_short_preamble);
6900 if (bss_conf->use_short_preamble)
6901 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6902 else
6903 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6904 }
6905
6906 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
6907 IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
6908 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
6909 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
6910 else
6911 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
6912 }
6913
6914 if (changes & BSS_CHANGED_ASSOC) {
6915 IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
6916 /* This should never happen as this function should
6917 * never be called from interrupt context. */
6918 if (WARN_ON_ONCE(in_interrupt()))
6919 return;
6920 if (bss_conf->assoc) {
6921 priv->assoc_id = bss_conf->aid;
6922 priv->beacon_int = bss_conf->beacon_int;
6923 priv->timestamp0 = bss_conf->timestamp & 0xFFFFFFFF;
6924 priv->timestamp1 = (bss_conf->timestamp >> 32) &
6925 0xFFFFFFFF;
6926 priv->assoc_capability = bss_conf->assoc_capability;
6927 priv->next_scan_jiffies = jiffies +
6928 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
6929 mutex_lock(&priv->mutex);
6930 iwl3945_post_associate(priv);
6931 mutex_unlock(&priv->mutex);
6932 } else {
6933 priv->assoc_id = 0;
6934 IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
6935 }
6936 } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
6937 IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
6938 iwl3945_send_rxon_assoc(priv);
6939 }
6940
6941}
6942
bb8c093b 6943static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 6944{
6945 int rc = 0;
6946 unsigned long flags;
bb8c093b 6947 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6948
6949 IWL_DEBUG_MAC80211("enter\n");
6950
15e869d8 6951 mutex_lock(&priv->mutex);
b481de9c
ZY		 6952 spin_lock_irqsave(&priv->lock, flags);
6953
bb8c093b 6954 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 6955 rc = -EIO;
6956 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
6957 goto out_unlock;
6958 }
6959
05c914fe 6960 if (priv->iw_mode == NL80211_IFTYPE_AP) { /* APs don't scan */
b481de9c
ZY		 6961 rc = -EIO;
6962 IWL_ERROR("ERROR: APs don't scan\n");
6963 goto out_unlock;
6964 }
6965
7878a5a4
MA		 6966 /* we don't schedule scan within next_scan_jiffies period */
6967 if (priv->next_scan_jiffies &&
6968 time_after(priv->next_scan_jiffies, jiffies)) {
6969 rc = -EAGAIN;
6970 goto out_unlock;
6971 }
15dbf1b7
BM		 6972 /* if we just finished scan ask for delay for a broadcast scan */
6973 if ((len == 0) && priv->last_scan_jiffies &&
6974 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
6975 jiffies)) {
b481de9c
ZY		 6976 rc = -EAGAIN;
6977 goto out_unlock;
6978 }
6979 if (len) {
7878a5a4 6980 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
7e272fcf 6981 escape_ssid(ssid, len), (int)len);
b481de9c
ZY		 6982
6983 priv->one_direct_scan = 1;
6984 priv->direct_ssid_len = (u8)
6985 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
6986 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA		 6987 } else
6988 priv->one_direct_scan = 0;
b481de9c 6989
bb8c093b 6990 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY		 6991
6992 IWL_DEBUG_MAC80211("leave\n");
6993
6994out_unlock:
6995 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 6996 mutex_unlock(&priv->mutex);
b481de9c
ZY		 6997
6998 return rc;
6999}
7000
bb8c093b 7001static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 7002 const u8 *local_addr, const u8 *addr,
7003 struct ieee80211_key_conf *key)
7004{
bb8c093b 7005 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7006 int rc = 0;
7007 u8 sta_id;
7008
7009 IWL_DEBUG_MAC80211("enter\n");
7010
bb8c093b 7011 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY		 7012 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7013 return -EOPNOTSUPP;
7014 }
7015
7016 if (is_zero_ether_addr(addr))
7017 /* only support pairwise keys */
7018 return -EOPNOTSUPP;
7019
bb8c093b 7020 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7021 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 7022 IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
7023 addr);
b481de9c
ZY		 7024 return -EINVAL;
7025 }
7026
7027 mutex_lock(&priv->mutex);
7028
bb8c093b 7029 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7030
b481de9c
ZY		 7031 switch (cmd) {
7032 case SET_KEY:
bb8c093b 7033 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7034 if (!rc) {
bb8c093b
CH		 7035 iwl3945_set_rxon_hwcrypto(priv, 1);
7036 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7037 key->hw_key_idx = sta_id;
7038 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7039 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7040 }
7041 break;
7042 case DISABLE_KEY:
bb8c093b 7043 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7044 if (!rc) {
bb8c093b
CH		 7045 iwl3945_set_rxon_hwcrypto(priv, 0);
7046 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7047 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7048 }
7049 break;
7050 default:
7051 rc = -EINVAL;
7052 }
7053
7054 IWL_DEBUG_MAC80211("leave\n");
7055 mutex_unlock(&priv->mutex);
7056
7057 return rc;
7058}
7059
e100bb64 7060static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
b481de9c
ZY		 7061 const struct ieee80211_tx_queue_params *params)
7062{
bb8c093b 7063 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7064 unsigned long flags;
7065 int q;
b481de9c
ZY		 7066
7067 IWL_DEBUG_MAC80211("enter\n");
7068
bb8c093b 7069 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7070 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7071 return -EIO;
7072 }
7073
7074 if (queue >= AC_NUM) {
7075 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7076 return 0;
7077 }
7078
b481de9c
ZY		 7079 if (!priv->qos_data.qos_enable) {
7080 priv->qos_data.qos_active = 0;
7081 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7082 return 0;
7083 }
7084 q = AC_NUM - 1 - queue;
7085
7086 spin_lock_irqsave(&priv->lock, flags);
7087
7088 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7089 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7090 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7091 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 7092 cpu_to_le16((params->txop * 32));
b481de9c
ZY		 7093
7094 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7095 priv->qos_data.qos_active = 1;
7096
7097 spin_unlock_irqrestore(&priv->lock, flags);
7098
7099 mutex_lock(&priv->mutex);
05c914fe 7100 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b
CH		 7101 iwl3945_activate_qos(priv, 1);
7102 else if (priv->assoc_id && iwl3945_is_associated(priv))
7103 iwl3945_activate_qos(priv, 0);
b481de9c
ZY		 7104
7105 mutex_unlock(&priv->mutex);
7106
b481de9c
ZY		 7107 IWL_DEBUG_MAC80211("leave\n");
7108 return 0;
7109}
7110
bb8c093b 7111static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7112 struct ieee80211_tx_queue_stats *stats)
7113{
bb8c093b 7114 struct iwl3945_priv *priv = hw->priv;
b481de9c 7115 int i, avail;
bb8c093b
CH		 7116 struct iwl3945_tx_queue *txq;
7117 struct iwl3945_queue *q;
b481de9c
ZY		 7118 unsigned long flags;
7119
7120 IWL_DEBUG_MAC80211("enter\n");
7121
bb8c093b 7122 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7123 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7124 return -EIO;
7125 }
7126
7127 spin_lock_irqsave(&priv->lock, flags);
7128
7129 for (i = 0; i < AC_NUM; i++) {
7130 txq = &priv->txq[i];
7131 q = &txq->q;
bb8c093b 7132 avail = iwl3945_queue_space(q);
b481de9c 7133
57ffc589
JB		 7134 stats[i].len = q->n_window - avail;
7135 stats[i].limit = q->n_window - q->high_mark;
7136 stats[i].count = q->n_window;
b481de9c
ZY		 7137
7138 }
7139 spin_unlock_irqrestore(&priv->lock, flags);
7140
7141 IWL_DEBUG_MAC80211("leave\n");
7142
7143 return 0;
7144}
7145
bb8c093b 7146static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7147 struct ieee80211_low_level_stats *stats)
7148{
7149 IWL_DEBUG_MAC80211("enter\n");
7150 IWL_DEBUG_MAC80211("leave\n");
7151
7152 return 0;
7153}
7154
bb8c093b 7155static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY		 7156{
7157 IWL_DEBUG_MAC80211("enter\n");
7158 IWL_DEBUG_MAC80211("leave\n");
7159
7160 return 0;
7161}
7162
bb8c093b 7163static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7164{
bb8c093b 7165 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7166 unsigned long flags;
7167
7168 mutex_lock(&priv->mutex);
7169 IWL_DEBUG_MAC80211("enter\n");
7170
bb8c093b 7171 iwl3945_reset_qos(priv);
292ae174 7172
b481de9c
ZY		 7173 spin_lock_irqsave(&priv->lock, flags);
7174 priv->assoc_id = 0;
7175 priv->assoc_capability = 0;
7176 priv->call_post_assoc_from_beacon = 0;
7177
7178 /* new association get rid of ibss beacon skb */
7179 if (priv->ibss_beacon)
7180 dev_kfree_skb(priv->ibss_beacon);
7181
7182 priv->ibss_beacon = NULL;
7183
7184 priv->beacon_int = priv->hw->conf.beacon_int;
7185 priv->timestamp1 = 0;
7186 priv->timestamp0 = 0;
05c914fe 7187 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
b481de9c
ZY		 7188 priv->beacon_int = 0;
7189
7190 spin_unlock_irqrestore(&priv->lock, flags);
7191
fde3571f
MA		 7192 if (!iwl3945_is_ready_rf(priv)) {
7193 IWL_DEBUG_MAC80211("leave - not ready\n");
7194 mutex_unlock(&priv->mutex);
7195 return;
7196 }
7197
15e869d8
MA		 7198 /* we are restarting association process
7199 * clear RXON_FILTER_ASSOC_MSK bit
7200 */
05c914fe 7201 if (priv->iw_mode != NL80211_IFTYPE_AP) {
bb8c093b 7202 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7203 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7204 iwl3945_commit_rxon(priv);
15e869d8
MA		 7205 }
7206
b481de9c 7207 /* Per mac80211.h: This is only used in IBSS mode... */
05c914fe 7208 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
15e869d8 7209
b481de9c
ZY		 7210 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7211 mutex_unlock(&priv->mutex);
7212 return;
b481de9c
ZY		 7213 }
7214
bb8c093b 7215 iwl3945_set_rate(priv);
b481de9c
ZY		 7216
7217 mutex_unlock(&priv->mutex);
7218
7219 IWL_DEBUG_MAC80211("leave\n");
7220
7221}
7222
e039fa4a 7223static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 7224{
bb8c093b 7225 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7226 unsigned long flags;
7227
7228 mutex_lock(&priv->mutex);
7229 IWL_DEBUG_MAC80211("enter\n");
7230
bb8c093b 7231 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7232 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7233 mutex_unlock(&priv->mutex);
7234 return -EIO;
7235 }
7236
05c914fe 7237 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
b481de9c
ZY		 7238 IWL_DEBUG_MAC80211("leave - not IBSS\n");
7239 mutex_unlock(&priv->mutex);
7240 return -EIO;
7241 }
7242
7243 spin_lock_irqsave(&priv->lock, flags);
7244
7245 if (priv->ibss_beacon)
7246 dev_kfree_skb(priv->ibss_beacon);
7247
7248 priv->ibss_beacon = skb;
7249
7250 priv->assoc_id = 0;
7251
7252 IWL_DEBUG_MAC80211("leave\n");
7253 spin_unlock_irqrestore(&priv->lock, flags);
7254
bb8c093b 7255 iwl3945_reset_qos(priv);
b481de9c 7256
dc4b1e7d 7257 iwl3945_post_associate(priv);
b481de9c
ZY		 7258
7259 mutex_unlock(&priv->mutex);
7260
7261 return 0;
7262}
7263
7264/*****************************************************************************
7265 *
7266 * sysfs attributes
7267 *
7268 *****************************************************************************/
7269
c8b0e6e1 7270#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 7271
7272/*
7273 * The following adds a new attribute to the sysfs representation
7274 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7275 * used for controlling the debug level.
7276 *
7277 * See the level definitions in iwl for details.
7278 */
7279
7280static ssize_t show_debug_level(struct device_driver *d, char *buf)
7281{
bb8c093b 7282 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY		 7283}
7284static ssize_t store_debug_level(struct device_driver *d,
7285 const char *buf, size_t count)
7286{
7287 char *p = (char *)buf;
7288 u32 val;
7289
7290 val = simple_strtoul(p, &p, 0);
7291 if (p == buf)
7292 printk(KERN_INFO DRV_NAME
7293 ": %s is not in hex or decimal form.\n", buf);
7294 else
bb8c093b 7295 iwl3945_debug_level = val;
b481de9c
ZY		 7296
7297 return strnlen(buf, count);
7298}
7299
7300static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7301 show_debug_level, store_debug_level);
7302
c8b0e6e1 7303#endif /* CONFIG_IWL3945_DEBUG */
b481de9c 7304
b481de9c
ZY		 7305static ssize_t show_temperature(struct device *d,
7306 struct device_attribute *attr, char *buf)
7307{
bb8c093b 7308 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7309
bb8c093b 7310 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7311 return -EAGAIN;
7312
bb8c093b 7313 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY		 7314}
7315
7316static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7317
b481de9c
ZY		 7318static ssize_t show_tx_power(struct device *d,
7319 struct device_attribute *attr, char *buf)
7320{
bb8c093b 7321 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7322 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7323}
7324
7325static ssize_t store_tx_power(struct device *d,
7326 struct device_attribute *attr,
7327 const char *buf, size_t count)
7328{
bb8c093b 7329 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7330 char *p = (char *)buf;
7331 u32 val;
7332
7333 val = simple_strtoul(p, &p, 10);
7334 if (p == buf)
7335 printk(KERN_INFO DRV_NAME
7336 ": %s is not in decimal form.\n", buf);
7337 else
bb8c093b 7338 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 7339
7340 return count;
7341}
7342
7343static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7344
7345static ssize_t show_flags(struct device *d,
7346 struct device_attribute *attr, char *buf)
7347{
bb8c093b 7348 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7349
7350 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7351}
7352
7353static ssize_t store_flags(struct device *d,
7354 struct device_attribute *attr,
7355 const char *buf, size_t count)
7356{
bb8c093b 7357 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7358 u32 flags = simple_strtoul(buf, NULL, 0);
7359
7360 mutex_lock(&priv->mutex);
7361 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7362 /* Cancel any currently running scans... */
bb8c093b 7363 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7364 IWL_WARNING("Could not cancel scan.\n");
7365 else {
7366 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7367 flags);
7368 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7369 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7370 }
7371 }
7372 mutex_unlock(&priv->mutex);
7373
7374 return count;
7375}
7376
7377static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7378
7379static ssize_t show_filter_flags(struct device *d,
7380 struct device_attribute *attr, char *buf)
7381{
bb8c093b 7382 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7383
7384 return sprintf(buf, "0x%04X\n",
7385 le32_to_cpu(priv->active_rxon.filter_flags));
7386}
7387
7388static ssize_t store_filter_flags(struct device *d,
7389 struct device_attribute *attr,
7390 const char *buf, size_t count)
7391{
bb8c093b 7392 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7393 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7394
7395 mutex_lock(&priv->mutex);
7396 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7397 /* Cancel any currently running scans... */
bb8c093b 7398 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7399 IWL_WARNING("Could not cancel scan.\n");
7400 else {
7401 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7402 "0x%04X\n", filter_flags);
7403 priv->staging_rxon.filter_flags =
7404 cpu_to_le32(filter_flags);
bb8c093b 7405 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7406 }
7407 }
7408 mutex_unlock(&priv->mutex);
7409
7410 return count;
7411}
7412
7413static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7414 store_filter_flags);
7415
c8b0e6e1 7416#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7417
7418static ssize_t show_measurement(struct device *d,
7419 struct device_attribute *attr, char *buf)
7420{
bb8c093b
CH		 7421 struct iwl3945_priv *priv = dev_get_drvdata(d);
7422 struct iwl3945_spectrum_notification measure_report;
b481de9c 7423 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 7424 u8 *data = (u8 *)&measure_report;
b481de9c
ZY		 7425 unsigned long flags;
7426
7427 spin_lock_irqsave(&priv->lock, flags);
7428 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7429 spin_unlock_irqrestore(&priv->lock, flags);
7430 return 0;
7431 }
7432 memcpy(&measure_report, &priv->measure_report, size);
7433 priv->measurement_status = 0;
7434 spin_unlock_irqrestore(&priv->lock, flags);
7435
7436 while (size && (PAGE_SIZE - len)) {
7437 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7438 PAGE_SIZE - len, 1);
7439 len = strlen(buf);
7440 if (PAGE_SIZE - len)
7441 buf[len++] = '\n';
7442
7443 ofs += 16;
7444 size -= min(size, 16U);
7445 }
7446
7447 return len;
7448}
7449
7450static ssize_t store_measurement(struct device *d,
7451 struct device_attribute *attr,
7452 const char *buf, size_t count)
7453{
bb8c093b 7454 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7455 struct ieee80211_measurement_params params = {
7456 .channel = le16_to_cpu(priv->active_rxon.channel),
7457 .start_time = cpu_to_le64(priv->last_tsf),
7458 .duration = cpu_to_le16(1),
7459 };
7460 u8 type = IWL_MEASURE_BASIC;
7461 u8 buffer[32];
7462 u8 channel;
7463
7464 if (count) {
7465 char *p = buffer;
7466 strncpy(buffer, buf, min(sizeof(buffer), count));
7467 channel = simple_strtoul(p, NULL, 0);
7468 if (channel)
7469 params.channel = channel;
7470
7471 p = buffer;
7472 while (*p && *p != ' ')
7473 p++;
7474 if (*p)
7475 type = simple_strtoul(p + 1, NULL, 0);
7476 }
7477
7478 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7479 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7480 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY		 7481
7482 return count;
7483}
7484
7485static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7486 show_measurement, store_measurement);
c8b0e6e1 7487#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 7488
b481de9c
ZY		 7489static ssize_t store_retry_rate(struct device *d,
7490 struct device_attribute *attr,
7491 const char *buf, size_t count)
7492{
bb8c093b 7493 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7494
7495 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7496 if (priv->retry_rate <= 0)
7497 priv->retry_rate = 1;
7498
7499 return count;
7500}
7501
7502static ssize_t show_retry_rate(struct device *d,
7503 struct device_attribute *attr, char *buf)
7504{
bb8c093b 7505 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7506 return sprintf(buf, "%d", priv->retry_rate);
7507}
7508
7509static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7510 store_retry_rate);
7511
7512static ssize_t store_power_level(struct device *d,
7513 struct device_attribute *attr,
7514 const char *buf, size_t count)
7515{
bb8c093b 7516 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7517 int rc;
7518 int mode;
7519
7520 mode = simple_strtoul(buf, NULL, 0);
7521 mutex_lock(&priv->mutex);
7522
bb8c093b 7523 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 7524 rc = -EAGAIN;
7525 goto out;
7526 }
7527
7528 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
7529 mode = IWL_POWER_AC;
7530 else
7531 mode |= IWL_POWER_ENABLED;
7532
7533 if (mode != priv->power_mode) {
bb8c093b 7534 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 7535 if (rc) {
7536 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7537 goto out;
7538 }
7539 priv->power_mode = mode;
7540 }
7541
7542 rc = count;
7543
7544 out:
7545 mutex_unlock(&priv->mutex);
7546 return rc;
7547}
7548
7549#define MAX_WX_STRING 80
7550
7551/* Values are in microsecond */
7552static const s32 timeout_duration[] = {
7553 350000,
7554 250000,
7555 75000,
7556 37000,
7557 25000,
7558};
7559static const s32 period_duration[] = {
7560 400000,
7561 700000,
7562 1000000,
7563 1000000,
7564 1000000
7565};
7566
7567static ssize_t show_power_level(struct device *d,
7568 struct device_attribute *attr, char *buf)
7569{
bb8c093b 7570 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7571 int level = IWL_POWER_LEVEL(priv->power_mode);
7572 char *p = buf;
7573
7574 p += sprintf(p, "%d ", level);
7575 switch (level) {
7576 case IWL_POWER_MODE_CAM:
7577 case IWL_POWER_AC:
7578 p += sprintf(p, "(AC)");
7579 break;
7580 case IWL_POWER_BATTERY:
7581 p += sprintf(p, "(BATTERY)");
7582 break;
7583 default:
7584 p += sprintf(p,
7585 "(Timeout %dms, Period %dms)",
7586 timeout_duration[level - 1] / 1000,
7587 period_duration[level - 1] / 1000);
7588 }
7589
7590 if (!(priv->power_mode & IWL_POWER_ENABLED))
7591 p += sprintf(p, " OFF\n");
7592 else
7593 p += sprintf(p, " \n");
7594
3ac7f146 7595 return p - buf + 1;
b481de9c
ZY		 7596
7597}
7598
7599static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7600 store_power_level);
7601
7602static ssize_t show_channels(struct device *d,
7603 struct device_attribute *attr, char *buf)
7604{
8318d78a
JB		 7605 /* all this shit doesn't belong into sysfs anyway */
7606 return 0;
b481de9c
ZY		 7607}
7608
7609static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7610
7611static ssize_t show_statistics(struct device *d,
7612 struct device_attribute *attr, char *buf)
7613{
bb8c093b
CH		 7614 struct iwl3945_priv *priv = dev_get_drvdata(d);
7615 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 7616 u32 len = 0, ofs = 0;
3ac7f146 7617 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY		 7618 int rc = 0;
7619
bb8c093b 7620 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7621 return -EAGAIN;
7622
7623 mutex_lock(&priv->mutex);
bb8c093b 7624 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY		 7625 mutex_unlock(&priv->mutex);
7626
7627 if (rc) {
7628 len = sprintf(buf,
7629 "Error sending statistics request: 0x%08X\n", rc);
7630 return len;
7631 }
7632
7633 while (size && (PAGE_SIZE - len)) {
7634 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7635 PAGE_SIZE - len, 1);
7636 len = strlen(buf);
7637 if (PAGE_SIZE - len)
7638 buf[len++] = '\n';
7639
7640 ofs += 16;
7641 size -= min(size, 16U);
7642 }
7643
7644 return len;
7645}
7646
7647static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7648
7649static ssize_t show_antenna(struct device *d,
7650 struct device_attribute *attr, char *buf)
7651{
bb8c093b 7652 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 7653
bb8c093b 7654 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7655 return -EAGAIN;
7656
7657 return sprintf(buf, "%d\n", priv->antenna);
7658}
7659
7660static ssize_t store_antenna(struct device *d,
7661 struct device_attribute *attr,
7662 const char *buf, size_t count)
7663{
7664 int ant;
bb8c093b 7665 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7666
7667 if (count == 0)
7668 return 0;
7669
7670 if (sscanf(buf, "%1i", &ant) != 1) {
7671 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7672 return count;
7673 }
7674
7675 if ((ant >= 0) && (ant <= 2)) {
7676 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7677 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY		 7678 } else
7679 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7680
7681
7682 return count;
7683}
7684
7685static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7686
7687static ssize_t show_status(struct device *d,
7688 struct device_attribute *attr, char *buf)
7689{
bb8c093b
CH		 7690 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
7691 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7692 return -EAGAIN;
7693 return sprintf(buf, "0x%08x\n", (int)priv->status);
7694}
7695
7696static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7697
7698static ssize_t dump_error_log(struct device *d,
7699 struct device_attribute *attr,
7700 const char *buf, size_t count)
7701{
7702 char *p = (char *)buf;
7703
7704 if (p[0] == '1')
bb8c093b 7705 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7706
7707 return strnlen(buf, count);
7708}
7709
7710static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7711
7712static ssize_t dump_event_log(struct device *d,
7713 struct device_attribute *attr,
7714 const char *buf, size_t count)
7715{
7716 char *p = (char *)buf;
7717
7718 if (p[0] == '1')
bb8c093b 7719 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7720
7721 return strnlen(buf, count);
7722}
7723
7724static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7725
7726/*****************************************************************************
7727 *
7728 * driver setup and teardown
7729 *
7730 *****************************************************************************/
7731
bb8c093b 7732static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 7733{
7734 priv->workqueue = create_workqueue(DRV_NAME);
7735
7736 init_waitqueue_head(&priv->wait_command_queue);
7737
bb8c093b
CH		 7738 INIT_WORK(&priv->up, iwl3945_bg_up);
7739 INIT_WORK(&priv->restart, iwl3945_bg_restart);
7740 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
7741 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
7742 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
7743 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7744 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7745 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
5ec03976 7746 INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor);
bb8c093b
CH		 7747 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7748 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
7749 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
7750
7751 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY		 7752
7753 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7754 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 7755}
7756
bb8c093b 7757static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 7758{
bb8c093b 7759 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 7760
e47eb6ad 7761 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 7762 cancel_delayed_work(&priv->scan_check);
7763 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY		 7764 cancel_work_sync(&priv->beacon_update);
7765}
7766
bb8c093b 7767static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY		 7768 &dev_attr_antenna.attr,
7769 &dev_attr_channels.attr,
7770 &dev_attr_dump_errors.attr,
7771 &dev_attr_dump_events.attr,
7772 &dev_attr_flags.attr,
7773 &dev_attr_filter_flags.attr,
c8b0e6e1 7774#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7775 &dev_attr_measurement.attr,
7776#endif
7777 &dev_attr_power_level.attr,
b481de9c 7778 &dev_attr_retry_rate.attr,
b481de9c
ZY		 7779 &dev_attr_statistics.attr,
7780 &dev_attr_status.attr,
7781 &dev_attr_temperature.attr,
b481de9c
ZY		 7782 &dev_attr_tx_power.attr,
7783
7784 NULL
7785};
7786
bb8c093b 7787static struct attribute_group iwl3945_attribute_group = {
b481de9c 7788 .name = NULL, /* put in device directory */
bb8c093b 7789 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY		 7790};
7791
bb8c093b
CH		 7792static struct ieee80211_ops iwl3945_hw_ops = {
7793 .tx = iwl3945_mac_tx,
7794 .start = iwl3945_mac_start,
7795 .stop = iwl3945_mac_stop,
7796 .add_interface = iwl3945_mac_add_interface,
7797 .remove_interface = iwl3945_mac_remove_interface,
7798 .config = iwl3945_mac_config,
7799 .config_interface = iwl3945_mac_config_interface,
7800 .configure_filter = iwl3945_configure_filter,
7801 .set_key = iwl3945_mac_set_key,
7802 .get_stats = iwl3945_mac_get_stats,
7803 .get_tx_stats = iwl3945_mac_get_tx_stats,
7804 .conf_tx = iwl3945_mac_conf_tx,
7805 .get_tsf = iwl3945_mac_get_tsf,
7806 .reset_tsf = iwl3945_mac_reset_tsf,
cd56d331 7807 .bss_info_changed = iwl3945_bss_info_changed,
bb8c093b 7808 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY		 7809};
7810
bb8c093b 7811static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 7812{
7813 int err = 0;
bb8c093b 7814 struct iwl3945_priv *priv;
b481de9c 7815 struct ieee80211_hw *hw;
82b9a121 7816 struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
0359facc 7817 unsigned long flags;
b481de9c 7818
6440adb5
CB		 7819 /* Disabling hardware scan means that mac80211 will perform scans
7820 * "the hard way", rather than using device's scan. */
bb8c093b 7821 if (iwl3945_param_disable_hw_scan) {
b481de9c 7822 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 7823 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY		 7824 }
7825
dfe7d458 7826 if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
bb8c093b 7827 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c 7828 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
dfe7d458 7829 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
b481de9c
ZY		 7830 err = -EINVAL;
7831 goto out;
7832 }
7833
7834 /* mac80211 allocates memory for this device instance, including
7835 * space for this driver's private structure */
bb8c093b 7836 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY		 7837 if (hw == NULL) {
7838 IWL_ERROR("Can not allocate network device\n");
7839 err = -ENOMEM;
7840 goto out;
7841 }
7842 SET_IEEE80211_DEV(hw, &pdev->dev);
7843
f51359a8 7844 hw->rate_control_algorithm = "iwl-3945-rs";
4b7679a5 7845 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
f51359a8 7846
b481de9c
ZY		 7847 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
7848 priv = hw->priv;
7849 priv->hw = hw;
7850
7851 priv->pci_dev = pdev;
82b9a121 7852 priv->cfg = cfg;
6440adb5
CB		 7853
7854 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 7855 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 7856#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 7857 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY		 7858 atomic_set(&priv->restrict_refcnt, 0);
7859#endif
7860 priv->retry_rate = 1;
7861
7862 priv->ibss_beacon = NULL;
7863
566bfe5a 7864 /* Tell mac80211 our characteristics */
605a0bd6 7865 hw->flags = IEEE80211_HW_SIGNAL_DBM |
566bfe5a 7866 IEEE80211_HW_NOISE_DBM;
b481de9c 7867
f59ac048
LR		 7868 hw->wiphy->interface_modes =
7869 BIT(NL80211_IFTYPE_AP) |
7870 BIT(NL80211_IFTYPE_STATION) |
7871 BIT(NL80211_IFTYPE_ADHOC);
7872
6440adb5 7873 /* 4 EDCA QOS priorities */
b481de9c
ZY		 7874 hw->queues = 4;
7875
7876 spin_lock_init(&priv->lock);
7877 spin_lock_init(&priv->power_data.lock);
7878 spin_lock_init(&priv->sta_lock);
7879 spin_lock_init(&priv->hcmd_lock);
7880
b481de9c
ZY		 7881 INIT_LIST_HEAD(&priv->free_frames);
7882
7883 mutex_init(&priv->mutex);
7884 if (pci_enable_device(pdev)) {
7885 err = -ENODEV;
7886 goto out_ieee80211_free_hw;
7887 }
7888
7889 pci_set_master(pdev);
7890
6440adb5 7891 /* Clear the driver's (not device's) station table */
bb8c093b 7892 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 7893
7894 priv->data_retry_limit = -1;
7895 priv->ieee_channels = NULL;
7896 priv->ieee_rates = NULL;
8318d78a 7897 priv->band = IEEE80211_BAND_2GHZ;
b481de9c
ZY		 7898
7899 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
7900 if (!err)
7901 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
7902 if (err) {
7903 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
7904 goto out_pci_disable_device;
7905 }
7906
7907 pci_set_drvdata(pdev, priv);
7908 err = pci_request_regions(pdev, DRV_NAME);
7909 if (err)
7910 goto out_pci_disable_device;
6440adb5 7911
b481de9c
ZY		 7912 /* We disable the RETRY_TIMEOUT register (0x41) to keep
7913 * PCI Tx retries from interfering with C3 CPU state */
7914 pci_write_config_byte(pdev, 0x41, 0x00);
6440adb5 7915
b481de9c
ZY		 7916 priv->hw_base = pci_iomap(pdev, 0, 0);
7917 if (!priv->hw_base) {
7918 err = -ENODEV;
7919 goto out_pci_release_regions;
7920 }
7921
7922 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
7923 (unsigned long long) pci_resource_len(pdev, 0));
7924 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
7925
7926 /* Initialize module parameter values here */
7927
6440adb5 7928 /* Disable radio (SW RF KILL) via parameter when loading driver */
bb8c093b 7929 if (iwl3945_param_disable) {
b481de9c
ZY		 7930 set_bit(STATUS_RF_KILL_SW, &priv->status);
7931 IWL_DEBUG_INFO("Radio disabled.\n");
7932 }
7933
05c914fe 7934 priv->iw_mode = NL80211_IFTYPE_STATION;
b481de9c 7935
b481de9c 7936 printk(KERN_INFO DRV_NAME
82b9a121 7937 ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
b481de9c
ZY		 7938
7939 /* Device-specific setup */
bb8c093b 7940 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c 7941 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY		 7942 goto out_iounmap;
7943 }
7944
bb8c093b 7945 if (iwl3945_param_qos_enable)
b481de9c
ZY		 7946 priv->qos_data.qos_enable = 1;
7947
bb8c093b 7948 iwl3945_reset_qos(priv);
b481de9c
ZY		 7949
7950 priv->qos_data.qos_active = 0;
7951 priv->qos_data.qos_cap.val = 0;
b481de9c 7952
8318d78a 7953 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
bb8c093b
CH		 7954 iwl3945_setup_deferred_work(priv);
7955 iwl3945_setup_rx_handlers(priv);
b481de9c
ZY		 7956
7957 priv->rates_mask = IWL_RATES_MASK;
7958 /* If power management is turned on, default to AC mode */
7959 priv->power_mode = IWL_POWER_AC;
7960 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
7961
0359facc 7962 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 7963 iwl3945_disable_interrupts(priv);
0359facc 7964 spin_unlock_irqrestore(&priv->lock, flags);
49df2b33 7965
bb8c093b 7966 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 7967 if (err) {
7968 IWL_ERROR("failed to create sysfs device attributes\n");
b481de9c
ZY		 7969 goto out_release_irq;
7970 }
7971
5a66926a
ZY		 7972 /* nic init */
7973 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
3ac7f146
TW		 7974 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
7975
7976 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
7977 err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
7978 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
7979 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
7980 if (err < 0) {
7981 IWL_DEBUG_INFO("Failed to init the card\n");
5a66926a 7982 goto out_remove_sysfs;
3ac7f146 7983 }
5a66926a
ZY		 7984 /* Read the EEPROM */
7985 err = iwl3945_eeprom_init(priv);
b481de9c 7986 if (err) {
5a66926a
ZY		 7987 IWL_ERROR("Unable to init EEPROM\n");
7988 goto out_remove_sysfs;
b481de9c 7989 }
5a66926a
ZY		 7990 /* MAC Address location in EEPROM same for 3945/4965 */
7991 get_eeprom_mac(priv, priv->mac_addr);
e174961c 7992 IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
5a66926a 7993 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 7994
849e0dce
RC		 7995 err = iwl3945_init_channel_map(priv);
7996 if (err) {
7997 IWL_ERROR("initializing regulatory failed: %d\n", err);
7998 goto out_remove_sysfs;
7999 }
8000
8001 err = iwl3945_init_geos(priv);
8002 if (err) {
8003 IWL_ERROR("initializing geos failed: %d\n", err);
8004 goto out_free_channel_map;
8005 }
849e0dce 8006
5a66926a
ZY		 8007 err = ieee80211_register_hw(priv->hw);
8008 if (err) {
8009 IWL_ERROR("Failed to register network device (error %d)\n", err);
849e0dce 8010 goto out_free_geos;
5a66926a 8011 }
b481de9c 8012
5a66926a
ZY		 8013 priv->hw->conf.beacon_int = 100;
8014 priv->mac80211_registered = 1;
8015 pci_save_state(pdev);
8016 pci_disable_device(pdev);
b481de9c 8017
ebef2008
AK		 8018 err = iwl3945_rfkill_init(priv);
8019 if (err)
8020 IWL_ERROR("Unable to initialize RFKILL system. "
8021 "Ignoring error: %d\n", err);
8022
b481de9c
ZY		 8023 return 0;
8024
849e0dce
RC		 8025 out_free_geos:
8026 iwl3945_free_geos(priv);
8027 out_free_channel_map:
8028 iwl3945_free_channel_map(priv);
5a66926a 8029 out_remove_sysfs:
bb8c093b 8030 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8031
8032 out_release_irq:
b481de9c
ZY		 8033 destroy_workqueue(priv->workqueue);
8034 priv->workqueue = NULL;
bb8c093b 8035 iwl3945_unset_hw_setting(priv);
b481de9c
ZY		 8036
8037 out_iounmap:
8038 pci_iounmap(pdev, priv->hw_base);
8039 out_pci_release_regions:
8040 pci_release_regions(pdev);
8041 out_pci_disable_device:
8042 pci_disable_device(pdev);
8043 pci_set_drvdata(pdev, NULL);
8044 out_ieee80211_free_hw:
8045 ieee80211_free_hw(priv->hw);
8046 out:
8047 return err;
8048}
8049
c83dbf68 8050static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8051{
bb8c093b 8052 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
0359facc 8053 unsigned long flags;
b481de9c
ZY		 8054
8055 if (!priv)
8056 return;
8057
8058 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8059
b481de9c 8060 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8061
bb8c093b 8062 iwl3945_down(priv);
b481de9c 8063
0359facc
MA		 8064 /* make sure we flush any pending irq or
8065 * tasklet for the driver
8066 */
8067 spin_lock_irqsave(&priv->lock, flags);
8068 iwl3945_disable_interrupts(priv);
8069 spin_unlock_irqrestore(&priv->lock, flags);
8070
8071 iwl_synchronize_irq(priv);
8072
bb8c093b 8073 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8074
ebef2008 8075 iwl3945_rfkill_unregister(priv);
bb8c093b 8076 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 8077
8078 if (priv->rxq.bd)
bb8c093b
CH		 8079 iwl3945_rx_queue_free(priv, &priv->rxq);
8080 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8081
bb8c093b
CH		 8082 iwl3945_unset_hw_setting(priv);
8083 iwl3945_clear_stations_table(priv);
b481de9c 8084
3ac7f146 8085 if (priv->mac80211_registered)
b481de9c 8086 ieee80211_unregister_hw(priv->hw);
b481de9c 8087
6ef89d0a
MA		 8088 /*netif_stop_queue(dev); */
8089 flush_workqueue(priv->workqueue);
8090
bb8c093b 8091 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY		 8092 * priv->workqueue... so we can't take down the workqueue
8093 * until now... */
8094 destroy_workqueue(priv->workqueue);
8095 priv->workqueue = NULL;
8096
b481de9c
ZY		 8097 pci_iounmap(pdev, priv->hw_base);
8098 pci_release_regions(pdev);
8099 pci_disable_device(pdev);
8100 pci_set_drvdata(pdev, NULL);
8101
849e0dce
RC		 8102 iwl3945_free_channel_map(priv);
8103 iwl3945_free_geos(priv);
261415f7 8104 kfree(priv->scan);
b481de9c
ZY		 8105 if (priv->ibss_beacon)
8106 dev_kfree_skb(priv->ibss_beacon);
8107
8108 ieee80211_free_hw(priv->hw);
8109}
8110
8111#ifdef CONFIG_PM
8112
bb8c093b 8113static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8114{
bb8c093b 8115 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8116
e655b9f0
ZY		 8117 if (priv->is_open) {
8118 set_bit(STATUS_IN_SUSPEND, &priv->status);
8119 iwl3945_mac_stop(priv->hw);
8120 priv->is_open = 1;
8121 }
b481de9c 8122
b481de9c
ZY		 8123 pci_set_power_state(pdev, PCI_D3hot);
8124
b481de9c
ZY		 8125 return 0;
8126}
8127
bb8c093b 8128static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8129{
bb8c093b 8130 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8131
b481de9c 8132 pci_set_power_state(pdev, PCI_D0);
b481de9c 8133
e655b9f0
ZY		 8134 if (priv->is_open)
8135 iwl3945_mac_start(priv->hw);
b481de9c 8136
e655b9f0 8137 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 8138 return 0;
8139}
8140
8141#endif /* CONFIG_PM */
8142
ebef2008 8143/*************** RFKILL FUNCTIONS **********/
80fcc9e2 8144#ifdef CONFIG_IWL3945_RFKILL
ebef2008
AK		 8145/* software rf-kill from user */
8146static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
8147{
8148 struct iwl3945_priv *priv = data;
8149 int err = 0;
8150
80fcc9e2 8151 if (!priv->rfkill)
ebef2008
AK		 8152 return 0;
8153
8154 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
8155 return 0;
8156
8157 IWL_DEBUG_RF_KILL("we recieved soft RFKILL set to state %d\n", state);
8158 mutex_lock(&priv->mutex);
8159
8160 switch (state) {
acdfe9b4 8161 case RFKILL_STATE_UNBLOCKED:
80fcc9e2 8162 if (iwl3945_is_rfkill_hw(priv)) {
ebef2008 8163 err = -EBUSY;
80fcc9e2
AG		 8164 goto out_unlock;
8165 }
8166 iwl3945_radio_kill_sw(priv, 0);
ebef2008 8167 break;
acdfe9b4 8168 case RFKILL_STATE_SOFT_BLOCKED:
ebef2008 8169 iwl3945_radio_kill_sw(priv, 1);
ebef2008 8170 break;
acdfe9b4
ZY		 8171 default:
8172 IWL_WARNING("we recieved unexpected RFKILL state %d\n", state);
8173 break;
ebef2008 8174 }
80fcc9e2 8175out_unlock:
ebef2008
AK		 8176 mutex_unlock(&priv->mutex);
8177
8178 return err;
8179}
8180
8181int iwl3945_rfkill_init(struct iwl3945_priv *priv)
8182{
8183 struct device *device = wiphy_dev(priv->hw->wiphy);
8184 int ret = 0;
8185
8186 BUG_ON(device == NULL);
8187
8188 IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
80fcc9e2
AG		 8189 priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
8190 if (!priv->rfkill) {
ebef2008
AK		 8191 IWL_ERROR("Unable to allocate rfkill device.\n");
8192 ret = -ENOMEM;
8193 goto error;
8194 }
8195
80fcc9e2
AG		 8196 priv->rfkill->name = priv->cfg->name;
8197 priv->rfkill->data = priv;
8198 priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
8199 priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
8200 priv->rfkill->user_claim_unsupported = 1;
ebef2008 8201
80fcc9e2
AG		 8202 priv->rfkill->dev.class->suspend = NULL;
8203 priv->rfkill->dev.class->resume = NULL;
ebef2008 8204
80fcc9e2 8205 ret = rfkill_register(priv->rfkill);
ebef2008
AK		 8206 if (ret) {
8207 IWL_ERROR("Unable to register rfkill: %d\n", ret);
80fcc9e2 8208 goto freed_rfkill;
ebef2008
AK		 8209 }
8210
8211 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8212 return ret;
8213
ebef2008 8214freed_rfkill:
80fcc9e2
AG		 8215 if (priv->rfkill != NULL)
8216 rfkill_free(priv->rfkill);
8217 priv->rfkill = NULL;
ebef2008
AK		 8218
8219error:
8220 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8221 return ret;
8222}
8223
8224void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
8225{
80fcc9e2
AG		 8226 if (priv->rfkill)
8227 rfkill_unregister(priv->rfkill);
ebef2008 8228
80fcc9e2 8229 priv->rfkill = NULL;
ebef2008
AK		 8230}
8231
8232/* set rf-kill to the right state. */
8233void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
8234{
8235
80fcc9e2
AG		 8236 if (!priv->rfkill)
8237 return;
8238
8239 if (iwl3945_is_rfkill_hw(priv)) {
8240 rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
ebef2008 8241 return;
80fcc9e2 8242 }
ebef2008 8243
80fcc9e2
AG		 8244 if (!iwl3945_is_rfkill_sw(priv))
8245 rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
ebef2008 8246 else
80fcc9e2 8247 rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
ebef2008
AK		 8248}
8249#endif
8250
b481de9c
ZY		 8251/*****************************************************************************
8252 *
8253 * driver and module entry point
8254 *
8255 *****************************************************************************/
8256
bb8c093b 8257static struct pci_driver iwl3945_driver = {
b481de9c 8258 .name = DRV_NAME,
bb8c093b
CH		 8259 .id_table = iwl3945_hw_card_ids,
8260 .probe = iwl3945_pci_probe,
8261 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8262#ifdef CONFIG_PM
bb8c093b
CH		 8263 .suspend = iwl3945_pci_suspend,
8264 .resume = iwl3945_pci_resume,
b481de9c
ZY		 8265#endif
8266};
8267
bb8c093b 8268static int __init iwl3945_init(void)
b481de9c
ZY		 8269{
8270
8271 int ret;
8272 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8273 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC		 8274
8275 ret = iwl3945_rate_control_register();
8276 if (ret) {
8277 IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
8278 return ret;
8279 }
8280
bb8c093b 8281 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY		 8282 if (ret) {
8283 IWL_ERROR("Unable to initialize PCI module\n");
897e1cf2 8284 goto error_register;
b481de9c 8285 }
c8b0e6e1 8286#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8287 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY		 8288 if (ret) {
8289 IWL_ERROR("Unable to create driver sysfs file\n");
897e1cf2 8290 goto error_debug;
b481de9c
ZY		 8291 }
8292#endif
8293
8294 return ret;
897e1cf2
RC		 8295
8296#ifdef CONFIG_IWL3945_DEBUG
8297error_debug:
8298 pci_unregister_driver(&iwl3945_driver);
8299#endif
8300error_register:
8301 iwl3945_rate_control_unregister();
8302 return ret;
b481de9c
ZY		 8303}
8304
bb8c093b 8305static void __exit iwl3945_exit(void)
b481de9c 8306{
c8b0e6e1 8307#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8308 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8309#endif
bb8c093b 8310 pci_unregister_driver(&iwl3945_driver);
897e1cf2 8311 iwl3945_rate_control_unregister();
b481de9c
ZY		 8312}
8313
25cb6cad
ZY		 8314MODULE_FIRMWARE("iwlwifi-3945" IWL3945_UCODE_API ".ucode");
8315
bb8c093b 8316module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8317MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8318module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8319MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8320module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY		 8321MODULE_PARM_DESC(hwcrypto,
8322 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 8323module_param_named(debug, iwl3945_param_debug, int, 0444);
b481de9c 8324MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8325module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY		 8326MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8327
bb8c093b 8328module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY		 8329MODULE_PARM_DESC(queues_num, "number of hw queues.");
8330
8331/* QoS */
bb8c093b 8332module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
b481de9c
ZY		 8333MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
8334
bb8c093b
CH		 8335module_exit(iwl3945_exit);
8336module_init(iwl3945_init);
Linux kernel - Deliverables
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