projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iwlwifi: remove 4965 from common uCode API structures
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
ZY		 32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
b481de9c
ZY		 40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
7e272fcf 44#include <net/lib80211.h>
b481de9c
ZY		 45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
82b9a121 49#include "iwl-3945-core.h"
b481de9c
ZY		 50#include "iwl-3945.h"
51#include "iwl-helpers.h"
52
c8b0e6e1 53#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 54u32 iwl3945_debug_level;
b481de9c
ZY		 55#endif
56
bb8c093b
CH		 57static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
58 struct iwl3945_tx_queue *txq);
416e1438 59
b481de9c
ZY		 60/******************************************************************************
61 *
62 * module boiler plate
63 *
64 ******************************************************************************/
65
66/* module parameters */
6440adb5
CB		 67static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
68static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
69static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 70static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
6440adb5 71int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
dfe7d458 72int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
b481de9c
ZY		 73
74/*
75 * module name, copyright, version, etc.
76 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
77 */
78
79#define DRV_DESCRIPTION \
80"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
81
c8b0e6e1 82#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 83#define VD "d"
84#else
85#define VD
86#endif
87
c8b0e6e1 88#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 89#define VS "s"
90#else
91#define VS
92#endif
93
b9e0b449 94#define IWLWIFI_VERSION "1.2.26k" VD VS
eb7ae89c 95#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
b481de9c
ZY		 96#define DRV_VERSION IWLWIFI_VERSION
97
b481de9c
ZY		 98
99MODULE_DESCRIPTION(DRV_DESCRIPTION);
100MODULE_VERSION(DRV_VERSION);
101MODULE_AUTHOR(DRV_COPYRIGHT);
102MODULE_LICENSE("GPL");
103
8318d78a
JB		 104static const struct ieee80211_supported_band *iwl3945_get_band(
105 struct iwl3945_priv *priv, enum ieee80211_band band)
b481de9c 106{
8318d78a 107 return priv->hw->wiphy->bands[band];
b481de9c
ZY		 108}
109
b481de9c
ZY		 110/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
111 * DMA services
112 *
113 * Theory of operation
114 *
6440adb5
CB		 115 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
116 * of buffer descriptors, each of which points to one or more data buffers for
117 * the device to read from or fill. Driver and device exchange status of each
118 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
119 * entries in each circular buffer, to protect against confusing empty and full
120 * queue states.
121 *
122 * The device reads or writes the data in the queues via the device's several
123 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 124 *
125 * For Tx queue, there are low mark and high mark limits. If, after queuing
126 * the packet for Tx, free space become < low mark, Tx queue stopped. When
127 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
128 * Tx queue resumed.
129 *
6440adb5
CB		 130 * The 3945 operates with six queues: One receive queue, one transmit queue
131 * (#4) for sending commands to the device firmware, and four transmit queues
132 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
ZY		 133 ***************************************************/
134
c54b679d 135int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 136{
fc4b6853 137 int s = q->read_ptr - q->write_ptr;
b481de9c 138
fc4b6853 139 if (q->read_ptr > q->write_ptr)
b481de9c
ZY		 140 s -= q->n_bd;
141
142 if (s <= 0)
143 s += q->n_window;
144 /* keep some reserve to not confuse empty and full situations */
145 s -= 2;
146 if (s < 0)
147 s = 0;
148 return s;
149}
150
c54b679d 151int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 152{
fc4b6853
TW		 153 return q->write_ptr > q->read_ptr ?
154 (i >= q->read_ptr && i < q->write_ptr) :
155 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 156}
157
c54b679d 158
bb8c093b 159static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 160{
6440adb5 161 /* This is for scan command, the big buffer at end of command array */
b481de9c 162 if (is_huge)
6440adb5 163 return q->n_window; /* must be power of 2 */
b481de9c 164
6440adb5 165 /* Otherwise, use normal size buffers */
b481de9c
ZY		 166 return index & (q->n_window - 1);
167}
168
6440adb5
CB		 169/**
170 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
171 */
bb8c093b 172static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
b481de9c
ZY		 173 int count, int slots_num, u32 id)
174{
175 q->n_bd = count;
176 q->n_window = slots_num;
177 q->id = id;
178
c54b679d
TW		 179 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
180 * and iwl_queue_dec_wrap are broken. */
b481de9c
ZY		 181 BUG_ON(!is_power_of_2(count));
182
183 /* slots_num must be power-of-two size, otherwise
184 * get_cmd_index is broken. */
185 BUG_ON(!is_power_of_2(slots_num));
186
187 q->low_mark = q->n_window / 4;
188 if (q->low_mark < 4)
189 q->low_mark = 4;
190
191 q->high_mark = q->n_window / 8;
192 if (q->high_mark < 2)
193 q->high_mark = 2;
194
fc4b6853 195 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 196
197 return 0;
198}
199
6440adb5
CB		 200/**
201 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
202 */
bb8c093b
CH		 203static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
204 struct iwl3945_tx_queue *txq, u32 id)
b481de9c
ZY		 205{
206 struct pci_dev *dev = priv->pci_dev;
207
6440adb5
CB		 208 /* Driver private data, only for Tx (not command) queues,
209 * not shared with device. */
b481de9c
ZY		 210 if (id != IWL_CMD_QUEUE_NUM) {
211 txq->txb = kmalloc(sizeof(txq->txb[0]) *
212 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
213 if (!txq->txb) {
01ebd063 214 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
ZY		 215 "structures failed\n");
216 goto error;
217 }
218 } else
219 txq->txb = NULL;
220
6440adb5
CB		 221 /* Circular buffer of transmit frame descriptors (TFDs),
222 * shared with device */
b481de9c
ZY		 223 txq->bd = pci_alloc_consistent(dev,
224 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
225 &txq->q.dma_addr);
226
227 if (!txq->bd) {
228 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
229 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
230 goto error;
231 }
232 txq->q.id = id;
233
234 return 0;
235
236 error:
3ac7f146
TW		 237 kfree(txq->txb);
238 txq->txb = NULL;
b481de9c
ZY		 239
240 return -ENOMEM;
241}
242
6440adb5
CB		 243/**
244 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
245 */
bb8c093b
CH		 246int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
247 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY		 248{
249 struct pci_dev *dev = priv->pci_dev;
250 int len;
251 int rc = 0;
252
6440adb5
CB		 253 /*
254 * Alloc buffer array for commands (Tx or other types of commands).
255 * For the command queue (#4), allocate command space + one big
256 * command for scan, since scan command is very huge; the system will
257 * not have two scans at the same time, so only one is needed.
258 * For data Tx queues (all other queues), no super-size command
259 * space is needed.
260 */
bb8c093b 261 len = sizeof(struct iwl3945_cmd) * slots_num;
b481de9c
ZY		 262 if (txq_id == IWL_CMD_QUEUE_NUM)
263 len += IWL_MAX_SCAN_SIZE;
264 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
265 if (!txq->cmd)
266 return -ENOMEM;
267
6440adb5 268 /* Alloc driver data array and TFD circular buffer */
bb8c093b 269 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY		 270 if (rc) {
271 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
272
273 return -ENOMEM;
274 }
275 txq->need_update = 0;
276
277 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 278 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 279 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
CB		 280
281 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 282 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 283
6440adb5 284 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 285 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 286
287 return 0;
288}
289
290/**
bb8c093b 291 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 292 * @txq: Transmit queue to deallocate.
293 *
294 * Empty queue by removing and destroying all BD's.
6440adb5
CB		 295 * Free all buffers.
296 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 297 */
bb8c093b 298void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 299{
bb8c093b 300 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY		 301 struct pci_dev *dev = priv->pci_dev;
302 int len;
303
304 if (q->n_bd == 0)
305 return;
306
307 /* first, empty all BD's */
fc4b6853 308 for (; q->write_ptr != q->read_ptr;
c54b679d 309 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 310 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 311
bb8c093b 312 len = sizeof(struct iwl3945_cmd) * q->n_window;
b481de9c
ZY		 313 if (q->id == IWL_CMD_QUEUE_NUM)
314 len += IWL_MAX_SCAN_SIZE;
315
6440adb5 316 /* De-alloc array of command/tx buffers */
b481de9c
ZY		 317 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
318
6440adb5 319 /* De-alloc circular buffer of TFDs */
b481de9c 320 if (txq->q.n_bd)
bb8c093b 321 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
ZY		 322 txq->q.n_bd, txq->bd, txq->q.dma_addr);
323
6440adb5 324 /* De-alloc array of per-TFD driver data */
3ac7f146
TW		 325 kfree(txq->txb);
326 txq->txb = NULL;
b481de9c 327
6440adb5 328 /* 0-fill queue descriptor structure */
b481de9c
ZY		 329 memset(txq, 0, sizeof(*txq));
330}
331
bb8c093b 332const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
ZY		 333
334/*************** STATION TABLE MANAGEMENT ****
9fbab516 335 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 336 * the functionality provided here
337 */
338
339/**************************************************************/
01ebd063 340#if 0 /* temporary disable till we add real remove station */
6440adb5
CB		 341/**
342 * iwl3945_remove_station - Remove driver's knowledge of station.
343 *
344 * NOTE: This does not remove station from device's station table.
345 */
bb8c093b 346static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 347{
348 int index = IWL_INVALID_STATION;
349 int i;
350 unsigned long flags;
351
352 spin_lock_irqsave(&priv->sta_lock, flags);
353
354 if (is_ap)
355 index = IWL_AP_ID;
356 else if (is_broadcast_ether_addr(addr))
357 index = priv->hw_setting.bcast_sta_id;
358 else
359 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
360 if (priv->stations[i].used &&
361 !compare_ether_addr(priv->stations[i].sta.sta.addr,
362 addr)) {
363 index = i;
364 break;
365 }
366
367 if (unlikely(index == IWL_INVALID_STATION))
368 goto out;
369
370 if (priv->stations[index].used) {
371 priv->stations[index].used = 0;
372 priv->num_stations--;
373 }
374
375 BUG_ON(priv->num_stations < 0);
376
377out:
378 spin_unlock_irqrestore(&priv->sta_lock, flags);
379 return 0;
380}
556f8db7 381#endif
6440adb5
CB		 382
383/**
384 * iwl3945_clear_stations_table - Clear the driver's station table
385 *
386 * NOTE: This does not clear or otherwise alter the device's station table.
387 */
bb8c093b 388static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
b481de9c
ZY		 389{
390 unsigned long flags;
391
392 spin_lock_irqsave(&priv->sta_lock, flags);
393
394 priv->num_stations = 0;
395 memset(priv->stations, 0, sizeof(priv->stations));
396
397 spin_unlock_irqrestore(&priv->sta_lock, flags);
398}
399
6440adb5
CB		 400/**
401 * iwl3945_add_station - Add station to station tables in driver and device
402 */
bb8c093b 403u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY		 404{
405 int i;
406 int index = IWL_INVALID_STATION;
bb8c093b 407 struct iwl3945_station_entry *station;
b481de9c 408 unsigned long flags_spin;
c14c521e 409 u8 rate;
b481de9c
ZY		 410
411 spin_lock_irqsave(&priv->sta_lock, flags_spin);
412 if (is_ap)
413 index = IWL_AP_ID;
414 else if (is_broadcast_ether_addr(addr))
415 index = priv->hw_setting.bcast_sta_id;
416 else
417 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
418 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
419 addr)) {
420 index = i;
421 break;
422 }
423
424 if (!priv->stations[i].used &&
425 index == IWL_INVALID_STATION)
426 index = i;
427 }
428
01ebd063 429 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY		 430 since they have different meaning */
431 if (unlikely(index == IWL_INVALID_STATION)) {
432 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
433 return index;
434 }
435
436 if (priv->stations[index].used &&
437 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
438 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
439 return index;
440 }
441
e174961c 442 IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
b481de9c
ZY		 443 station = &priv->stations[index];
444 station->used = 1;
445 priv->num_stations++;
446
6440adb5 447 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 448 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY		 449 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
450 station->sta.mode = 0;
451 station->sta.sta.sta_id = index;
452 station->sta.station_flags = 0;
453
8318d78a 454 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW		 455 rate = IWL_RATE_6M_PLCP;
456 else
457 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY		 458
459 /* Turn on both antennas for the station... */
460 station->sta.rate_n_flags =
bb8c093b 461 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e
ZY		 462 station->current_rate.rate_n_flags =
463 le16_to_cpu(station->sta.rate_n_flags);
464
b481de9c 465 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB		 466
467 /* Add station to device's station table */
bb8c093b 468 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 469 return index;
470
471}
472
473/*************** DRIVER STATUS FUNCTIONS *****/
474
bb8c093b 475static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
ZY		 476{
477 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
478 * set but EXIT_PENDING is not */
479 return test_bit(STATUS_READY, &priv->status) &&
480 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
481 !test_bit(STATUS_EXIT_PENDING, &priv->status);
482}
483
bb8c093b 484static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
ZY		 485{
486 return test_bit(STATUS_ALIVE, &priv->status);
487}
488
bb8c093b 489static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY		 490{
491 return test_bit(STATUS_INIT, &priv->status);
492}
493
80fcc9e2
AG		 494static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
495{
496 return test_bit(STATUS_RF_KILL_SW, &priv->status);
497}
498
499static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
500{
501 return test_bit(STATUS_RF_KILL_HW, &priv->status);
502}
503
bb8c093b 504static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c 505{
80fcc9e2
AG		 506 return iwl3945_is_rfkill_hw(priv) ||
507 iwl3945_is_rfkill_sw(priv);
b481de9c
ZY		 508}
509
bb8c093b 510static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY		 511{
512
bb8c093b 513 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 514 return 0;
515
bb8c093b 516 return iwl3945_is_ready(priv);
b481de9c
ZY		 517}
518
519/*************** HOST COMMAND QUEUE FUNCTIONS *****/
520
c3056065 521#define IWL_CMD(x) case x: return #x
b481de9c
ZY		 522
523static const char *get_cmd_string(u8 cmd)
524{
525 switch (cmd) {
526 IWL_CMD(REPLY_ALIVE);
527 IWL_CMD(REPLY_ERROR);
528 IWL_CMD(REPLY_RXON);
529 IWL_CMD(REPLY_RXON_ASSOC);
530 IWL_CMD(REPLY_QOS_PARAM);
531 IWL_CMD(REPLY_RXON_TIMING);
532 IWL_CMD(REPLY_ADD_STA);
533 IWL_CMD(REPLY_REMOVE_STA);
534 IWL_CMD(REPLY_REMOVE_ALL_STA);
535 IWL_CMD(REPLY_3945_RX);
536 IWL_CMD(REPLY_TX);
537 IWL_CMD(REPLY_RATE_SCALE);
538 IWL_CMD(REPLY_LEDS_CMD);
539 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
540 IWL_CMD(RADAR_NOTIFICATION);
541 IWL_CMD(REPLY_QUIET_CMD);
542 IWL_CMD(REPLY_CHANNEL_SWITCH);
543 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
544 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
545 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
546 IWL_CMD(POWER_TABLE_CMD);
547 IWL_CMD(PM_SLEEP_NOTIFICATION);
548 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
549 IWL_CMD(REPLY_SCAN_CMD);
550 IWL_CMD(REPLY_SCAN_ABORT_CMD);
551 IWL_CMD(SCAN_START_NOTIFICATION);
552 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
553 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
554 IWL_CMD(BEACON_NOTIFICATION);
555 IWL_CMD(REPLY_TX_BEACON);
556 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
557 IWL_CMD(QUIET_NOTIFICATION);
558 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
559 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
560 IWL_CMD(REPLY_BT_CONFIG);
561 IWL_CMD(REPLY_STATISTICS_CMD);
562 IWL_CMD(STATISTICS_NOTIFICATION);
563 IWL_CMD(REPLY_CARD_STATE_CMD);
564 IWL_CMD(CARD_STATE_NOTIFICATION);
565 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
566 default:
567 return "UNKNOWN";
568
569 }
570}
571
572#define HOST_COMPLETE_TIMEOUT (HZ / 2)
573
574/**
bb8c093b 575 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 576 * @priv: device private data point
577 * @cmd: a point to the ucode command structure
578 *
579 * The function returns < 0 values to indicate the operation is
580 * failed. On success, it turns the index (> 0) of command in the
581 * command queue.
582 */
bb8c093b 583static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 584{
bb8c093b
CH		 585 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
586 struct iwl3945_queue *q = &txq->q;
587 struct iwl3945_tfd_frame *tfd;
b481de9c 588 u32 *control_flags;
bb8c093b 589 struct iwl3945_cmd *out_cmd;
b481de9c
ZY		 590 u32 idx;
591 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
592 dma_addr_t phys_addr;
593 int pad;
594 u16 count;
595 int ret;
596 unsigned long flags;
597
598 /* If any of the command structures end up being larger than
599 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
600 * we will need to increase the size of the TFD entries */
601 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
602 !(cmd->meta.flags & CMD_SIZE_HUGE));
603
c342a1b9
GG		 604
605 if (iwl3945_is_rfkill(priv)) {
606 IWL_DEBUG_INFO("Not sending command - RF KILL");
607 return -EIO;
608 }
609
bb8c093b 610 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY		 611 IWL_ERROR("No space for Tx\n");
612 return -ENOSPC;
613 }
614
615 spin_lock_irqsave(&priv->hcmd_lock, flags);
616
fc4b6853 617 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 618 memset(tfd, 0, sizeof(*tfd));
619
620 control_flags = (u32 *) tfd;
621
fc4b6853 622 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY		 623 out_cmd = &txq->cmd[idx];
624
625 out_cmd->hdr.cmd = cmd->id;
626 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
627 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
628
629 /* At this point, the out_cmd now has all of the incoming cmd
630 * information */
631
632 out_cmd->hdr.flags = 0;
633 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 634 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY		 635 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
636 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
637
638 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH		 639 offsetof(struct iwl3945_cmd, hdr);
640 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 641
642 pad = U32_PAD(cmd->len);
643 count = TFD_CTL_COUNT_GET(*control_flags);
644 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
645
646 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
647 "%d bytes at %d[%d]:%d\n",
648 get_cmd_string(out_cmd->hdr.cmd),
649 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 650 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 651
652 txq->need_update = 1;
6440adb5
CB		 653
654 /* Increment and update queue's write index */
c54b679d 655 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 656 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 657
658 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
659 return ret ? ret : idx;
660}
661
bb8c093b 662static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 663{
664 int ret;
665
666 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
667
668 /* An asynchronous command can not expect an SKB to be set. */
669 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
670
671 /* An asynchronous command MUST have a callback. */
672 BUG_ON(!cmd->meta.u.callback);
673
674 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
675 return -EBUSY;
676
bb8c093b 677 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 678 if (ret < 0) {
bb8c093b 679 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 680 get_cmd_string(cmd->id), ret);
681 return ret;
682 }
683 return 0;
684}
685
bb8c093b 686static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 687{
688 int cmd_idx;
689 int ret;
b481de9c
ZY		 690
691 BUG_ON(cmd->meta.flags & CMD_ASYNC);
692
693 /* A synchronous command can not have a callback set. */
694 BUG_ON(cmd->meta.u.callback != NULL);
695
e5472978 696 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
b481de9c
ZY		 697 IWL_ERROR("Error sending %s: Already sending a host command\n",
698 get_cmd_string(cmd->id));
e5472978
TW		 699 ret = -EBUSY;
700 goto out;
b481de9c
ZY		 701 }
702
703 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
704
705 if (cmd->meta.flags & CMD_WANT_SKB)
706 cmd->meta.source = &cmd->meta;
707
bb8c093b 708 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY		 709 if (cmd_idx < 0) {
710 ret = cmd_idx;
bb8c093b 711 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 712 get_cmd_string(cmd->id), ret);
713 goto out;
714 }
715
716 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
717 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
718 HOST_COMPLETE_TIMEOUT);
719 if (!ret) {
720 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
721 IWL_ERROR("Error sending %s: time out after %dms.\n",
722 get_cmd_string(cmd->id),
723 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
724
725 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
726 ret = -ETIMEDOUT;
727 goto cancel;
728 }
729 }
730
731 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
732 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
733 get_cmd_string(cmd->id));
734 ret = -ECANCELED;
735 goto fail;
736 }
737 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
738 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
739 get_cmd_string(cmd->id));
740 ret = -EIO;
741 goto fail;
742 }
743 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
744 IWL_ERROR("Error: Response NULL in '%s'\n",
745 get_cmd_string(cmd->id));
746 ret = -EIO;
747 goto out;
748 }
749
750 ret = 0;
751 goto out;
752
753cancel:
754 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 755 struct iwl3945_cmd *qcmd;
b481de9c
ZY		 756
757 /* Cancel the CMD_WANT_SKB flag for the cmd in the
758 * TX cmd queue. Otherwise in case the cmd comes
759 * in later, it will possibly set an invalid
760 * address (cmd->meta.source). */
761 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
762 qcmd->meta.flags &= ~CMD_WANT_SKB;
763 }
764fail:
765 if (cmd->meta.u.skb) {
766 dev_kfree_skb_any(cmd->meta.u.skb);
767 cmd->meta.u.skb = NULL;
768 }
769out:
e5472978 770 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
b481de9c
ZY		 771 return ret;
772}
773
bb8c093b 774int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 775{
b481de9c 776 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 777 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 778
bb8c093b 779 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY		 780}
781
bb8c093b 782int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 783{
bb8c093b 784 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 785 .id = id,
786 .len = len,
787 .data = data,
788 };
789
bb8c093b 790 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 791}
792
bb8c093b 793static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 794{
bb8c093b 795 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 796 .id = id,
797 .len = sizeof(val),
798 .data = &val,
799 };
800
bb8c093b 801 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 802}
803
bb8c093b 804int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 805{
bb8c093b 806 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY		 807}
808
b481de9c 809/**
bb8c093b 810 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB		 811 * @band: 2.4 or 5 GHz band
812 * @channel: Any channel valid for the requested band
b481de9c 813
8318d78a 814 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY		 815 *
816 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 817 * in the staging RXON flag structure based on the band
b481de9c 818 */
8318d78a
JB		 819static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
820 enum ieee80211_band band,
821 u16 channel)
b481de9c 822{
8318d78a 823 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 824 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 825 channel, band);
b481de9c
ZY		 826 return -EINVAL;
827 }
828
829 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
8318d78a 830 (priv->band == band))
b481de9c
ZY		 831 return 0;
832
833 priv->staging_rxon.channel = cpu_to_le16(channel);
8318d78a 834 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 835 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
836 else
837 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
838
8318d78a 839 priv->band = band;
b481de9c 840
8318d78a 841 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY		 842
843 return 0;
844}
845
846/**
bb8c093b 847 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 848 *
849 * NOTE: This is really only useful during development and can eventually
850 * be #ifdef'd out once the driver is stable and folks aren't actively
851 * making changes
852 */
bb8c093b 853static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 854{
855 int error = 0;
856 int counter = 1;
857
858 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
859 error |= le32_to_cpu(rxon->flags &
860 (RXON_FLG_TGJ_NARROW_BAND_MSK |
861 RXON_FLG_RADAR_DETECT_MSK));
862 if (error)
863 IWL_WARNING("check 24G fields %d | %d\n",
864 counter++, error);
865 } else {
866 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
867 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
868 if (error)
869 IWL_WARNING("check 52 fields %d | %d\n",
870 counter++, error);
871 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
872 if (error)
873 IWL_WARNING("check 52 CCK %d | %d\n",
874 counter++, error);
875 }
876 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
877 if (error)
878 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
879
880 /* make sure basic rates 6Mbps and 1Mbps are supported */
881 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
882 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
883 if (error)
884 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
885
886 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
887 if (error)
888 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
889
890 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
891 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
892 if (error)
893 IWL_WARNING("check CCK and short slot %d | %d\n",
894 counter++, error);
895
896 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
897 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
898 if (error)
899 IWL_WARNING("check CCK & auto detect %d | %d\n",
900 counter++, error);
901
902 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
903 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
904 if (error)
905 IWL_WARNING("check TGG and auto detect %d | %d\n",
906 counter++, error);
907
908 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
909 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
910 RXON_FLG_ANT_A_MSK)) == 0);
911 if (error)
912 IWL_WARNING("check antenna %d %d\n", counter++, error);
913
914 if (error)
915 IWL_WARNING("Tuning to channel %d\n",
916 le16_to_cpu(rxon->channel));
917
918 if (error) {
bb8c093b 919 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY		 920 return -1;
921 }
922 return 0;
923}
924
925/**
9fbab516 926 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 927 * @priv: staging_rxon is compared to active_rxon
b481de9c 928 *
9fbab516
BC		 929 * If the RXON structure is changing enough to require a new tune,
930 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
931 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 932 */
bb8c093b 933static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY		 934{
935
936 /* These items are only settable from the full RXON command */
5d1e2325 937 if (!(iwl3945_is_associated(priv)) ||
b481de9c
ZY		 938 compare_ether_addr(priv->staging_rxon.bssid_addr,
939 priv->active_rxon.bssid_addr) ||
940 compare_ether_addr(priv->staging_rxon.node_addr,
941 priv->active_rxon.node_addr) ||
942 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
943 priv->active_rxon.wlap_bssid_addr) ||
944 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
945 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
946 (priv->staging_rxon.air_propagation !=
947 priv->active_rxon.air_propagation) ||
948 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
949 return 1;
950
951 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
952 * be updated with the RXON_ASSOC command -- however only some
953 * flag transitions are allowed using RXON_ASSOC */
954
955 /* Check if we are not switching bands */
956 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
957 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
958 return 1;
959
960 /* Check if we are switching association toggle */
961 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
962 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
963 return 1;
964
965 return 0;
966}
967
bb8c093b 968static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY		 969{
970 int rc = 0;
bb8c093b
CH		 971 struct iwl3945_rx_packet *res = NULL;
972 struct iwl3945_rxon_assoc_cmd rxon_assoc;
973 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 974 .id = REPLY_RXON_ASSOC,
975 .len = sizeof(rxon_assoc),
976 .meta.flags = CMD_WANT_SKB,
977 .data = &rxon_assoc,
978 };
bb8c093b
CH		 979 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
980 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY		 981
982 if ((rxon1->flags == rxon2->flags) &&
983 (rxon1->filter_flags == rxon2->filter_flags) &&
984 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
985 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
986 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
987 return 0;
988 }
989
990 rxon_assoc.flags = priv->staging_rxon.flags;
991 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
992 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
993 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
994 rxon_assoc.reserved = 0;
995
bb8c093b 996 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 997 if (rc)
998 return rc;
999
bb8c093b 1000 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1001 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1002 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1003 rc = -EIO;
1004 }
1005
1006 priv->alloc_rxb_skb--;
1007 dev_kfree_skb_any(cmd.meta.u.skb);
1008
1009 return rc;
1010}
1011
1012/**
bb8c093b 1013 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1014 *
01ebd063 1015 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 1016 * the active_rxon structure is updated with the new data. This
1017 * function correctly transitions out of the RXON_ASSOC_MSK state if
1018 * a HW tune is required based on the RXON structure changes.
1019 */
bb8c093b 1020static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY		 1021{
1022 /* cast away the const for active_rxon in this function */
bb8c093b 1023 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c
ZY		 1024 int rc = 0;
1025
bb8c093b 1026 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 1027 return -1;
1028
1029 /* always get timestamp with Rx frame */
1030 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1031
1032 /* select antenna */
1033 priv->staging_rxon.flags &=
1034 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1035 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1036
bb8c093b 1037 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY		 1038 if (rc) {
1039 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1040 return -EINVAL;
1041 }
1042
1043 /* If we don't need to send a full RXON, we can use
bb8c093b 1044 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1045 * and other flags for the current radio configuration. */
bb8c093b
CH		 1046 if (!iwl3945_full_rxon_required(priv)) {
1047 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY		 1048 if (rc) {
1049 IWL_ERROR("Error setting RXON_ASSOC "
1050 "configuration (%d).\n", rc);
1051 return rc;
1052 }
1053
1054 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1055
1056 return 0;
1057 }
1058
1059 /* If we are currently associated and the new config requires
1060 * an RXON_ASSOC and the new config wants the associated mask enabled,
1061 * we must clear the associated from the active configuration
1062 * before we apply the new config */
bb8c093b 1063 if (iwl3945_is_associated(priv) &&
b481de9c
ZY		 1064 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1065 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1066 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1067
bb8c093b
CH		 1068 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1069 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY		 1070 &priv->active_rxon);
1071
1072 /* If the mask clearing failed then we set
1073 * active_rxon back to what it was previously */
1074 if (rc) {
1075 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1076 IWL_ERROR("Error clearing ASSOC_MSK on current "
1077 "configuration (%d).\n", rc);
1078 return rc;
1079 }
b481de9c
ZY		 1080 }
1081
1082 IWL_DEBUG_INFO("Sending RXON\n"
1083 "* with%s RXON_FILTER_ASSOC_MSK\n"
1084 "* channel = %d\n"
e174961c 1085 "* bssid = %pM\n",
b481de9c
ZY		 1086 ((priv->staging_rxon.filter_flags &
1087 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1088 le16_to_cpu(priv->staging_rxon.channel),
e174961c 1089 priv->staging_rxon.bssid_addr);
b481de9c
ZY		 1090
1091 /* Apply the new configuration */
bb8c093b
CH		 1092 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1093 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY		 1094 if (rc) {
1095 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1096 return rc;
1097 }
1098
1099 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1100
bb8c093b 1101 iwl3945_clear_stations_table(priv);
556f8db7 1102
b481de9c
ZY		 1103 /* If we issue a new RXON command which required a tune then we must
1104 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1105 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1106 if (rc) {
1107 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1108 return rc;
1109 }
1110
1111 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1112 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY		 1113 IWL_INVALID_STATION) {
1114 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1115 return -EIO;
1116 }
1117
1118 /* If we have set the ASSOC_MSK and we are in BSS mode then
1119 * add the IWL_AP_ID to the station rate table */
bb8c093b 1120 if (iwl3945_is_associated(priv) &&
05c914fe 1121 (priv->iw_mode == NL80211_IFTYPE_STATION))
bb8c093b 1122 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY		 1123 == IWL_INVALID_STATION) {
1124 IWL_ERROR("Error adding AP address for transmit.\n");
1125 return -EIO;
1126 }
1127
8318d78a 1128 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY		 1129 rc = iwl3945_init_hw_rate_table(priv);
1130 if (rc) {
1131 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1132 return -EIO;
1133 }
1134
1135 return 0;
1136}
1137
bb8c093b 1138static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1139{
bb8c093b 1140 struct iwl3945_bt_cmd bt_cmd = {
b481de9c
ZY		 1141 .flags = 3,
1142 .lead_time = 0xAA,
1143 .max_kill = 1,
1144 .kill_ack_mask = 0,
1145 .kill_cts_mask = 0,
1146 };
1147
bb8c093b
CH		 1148 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1149 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
b481de9c
ZY		 1150}
1151
bb8c093b 1152static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY		 1153{
1154 int rc = 0;
bb8c093b
CH		 1155 struct iwl3945_rx_packet *res;
1156 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1157 .id = REPLY_SCAN_ABORT_CMD,
1158 .meta.flags = CMD_WANT_SKB,
1159 };
1160
1161 /* If there isn't a scan actively going on in the hardware
1162 * then we are in between scan bands and not actually
1163 * actively scanning, so don't send the abort command */
1164 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1165 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1166 return 0;
1167 }
1168
bb8c093b 1169 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1170 if (rc) {
1171 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1172 return rc;
1173 }
1174
bb8c093b 1175 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1176 if (res->u.status != CAN_ABORT_STATUS) {
1177 /* The scan abort will return 1 for success or
1178 * 2 for "failure". A failure condition can be
1179 * due to simply not being in an active scan which
1180 * can occur if we send the scan abort before we
1181 * the microcode has notified us that a scan is
1182 * completed. */
1183 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1184 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1185 clear_bit(STATUS_SCAN_HW, &priv->status);
1186 }
1187
1188 dev_kfree_skb_any(cmd.meta.u.skb);
1189
1190 return rc;
1191}
1192
bb8c093b
CH		 1193static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1194 struct iwl3945_cmd *cmd,
b481de9c
ZY		 1195 struct sk_buff *skb)
1196{
1197 return 1;
1198}
1199
1200/*
1201 * CARD_STATE_CMD
1202 *
9fbab516 1203 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY		 1204 *
1205 * When in the 'enable' state the card operates as normal.
1206 * When in the 'disable' state, the card enters into a low power mode.
1207 * When in the 'halt' state, the card is shut down and must be fully
1208 * restarted to come back on.
1209 */
bb8c093b 1210static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1211{
bb8c093b 1212 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1213 .id = REPLY_CARD_STATE_CMD,
1214 .len = sizeof(u32),
1215 .data = &flags,
1216 .meta.flags = meta_flag,
1217 };
1218
1219 if (meta_flag & CMD_ASYNC)
bb8c093b 1220 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1221
bb8c093b 1222 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1223}
1224
bb8c093b
CH		 1225static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1226 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1227{
bb8c093b 1228 struct iwl3945_rx_packet *res = NULL;
b481de9c
ZY		 1229
1230 if (!skb) {
1231 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1232 return 1;
1233 }
1234
bb8c093b 1235 res = (struct iwl3945_rx_packet *)skb->data;
b481de9c
ZY		 1236 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1237 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1238 res->hdr.flags);
1239 return 1;
1240 }
1241
1242 switch (res->u.add_sta.status) {
1243 case ADD_STA_SUCCESS_MSK:
1244 break;
1245 default:
1246 break;
1247 }
1248
1249 /* We didn't cache the SKB; let the caller free it */
1250 return 1;
1251}
1252
bb8c093b
CH		 1253int iwl3945_send_add_station(struct iwl3945_priv *priv,
1254 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1255{
bb8c093b 1256 struct iwl3945_rx_packet *res = NULL;
b481de9c 1257 int rc = 0;
bb8c093b 1258 struct iwl3945_host_cmd cmd = {
b481de9c 1259 .id = REPLY_ADD_STA,
bb8c093b 1260 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY		 1261 .meta.flags = flags,
1262 .data = sta,
1263 };
1264
1265 if (flags & CMD_ASYNC)
bb8c093b 1266 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY		 1267 else
1268 cmd.meta.flags |= CMD_WANT_SKB;
1269
bb8c093b 1270 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1271
1272 if (rc || (flags & CMD_ASYNC))
1273 return rc;
1274
bb8c093b 1275 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1276 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1277 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1278 res->hdr.flags);
1279 rc = -EIO;
1280 }
1281
1282 if (rc == 0) {
1283 switch (res->u.add_sta.status) {
1284 case ADD_STA_SUCCESS_MSK:
1285 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1286 break;
1287 default:
1288 rc = -EIO;
1289 IWL_WARNING("REPLY_ADD_STA failed\n");
1290 break;
1291 }
1292 }
1293
1294 priv->alloc_rxb_skb--;
1295 dev_kfree_skb_any(cmd.meta.u.skb);
1296
1297 return rc;
1298}
1299
bb8c093b 1300static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY		 1301 struct ieee80211_key_conf *keyconf,
1302 u8 sta_id)
1303{
1304 unsigned long flags;
1305 __le16 key_flags = 0;
1306
1307 switch (keyconf->alg) {
1308 case ALG_CCMP:
1309 key_flags |= STA_KEY_FLG_CCMP;
1310 key_flags |= cpu_to_le16(
1311 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1312 key_flags &= ~STA_KEY_FLG_INVALID;
1313 break;
1314 case ALG_TKIP:
1315 case ALG_WEP:
b481de9c
ZY		 1316 default:
1317 return -EINVAL;
1318 }
1319 spin_lock_irqsave(&priv->sta_lock, flags);
1320 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1321 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1322 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1323 keyconf->keylen);
1324
1325 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1326 keyconf->keylen);
1327 priv->stations[sta_id].sta.key.key_flags = key_flags;
1328 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1329 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1330
1331 spin_unlock_irqrestore(&priv->sta_lock, flags);
1332
1333 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1334 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1335 return 0;
1336}
1337
bb8c093b 1338static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY		 1339{
1340 unsigned long flags;
1341
1342 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH		 1343 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1344 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
b481de9c
ZY		 1345 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1346 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1347 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1348 spin_unlock_irqrestore(&priv->sta_lock, flags);
1349
1350 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1351 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1352 return 0;
1353}
1354
bb8c093b 1355static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY		 1356{
1357 struct list_head *element;
1358
1359 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1360 priv->frames_count);
1361
1362 while (!list_empty(&priv->free_frames)) {
1363 element = priv->free_frames.next;
1364 list_del(element);
bb8c093b 1365 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY		 1366 priv->frames_count--;
1367 }
1368
1369 if (priv->frames_count) {
1370 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1371 priv->frames_count);
1372 priv->frames_count = 0;
1373 }
1374}
1375
bb8c093b 1376static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1377{
bb8c093b 1378 struct iwl3945_frame *frame;
b481de9c
ZY		 1379 struct list_head *element;
1380 if (list_empty(&priv->free_frames)) {
1381 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1382 if (!frame) {
1383 IWL_ERROR("Could not allocate frame!\n");
1384 return NULL;
1385 }
1386
1387 priv->frames_count++;
1388 return frame;
1389 }
1390
1391 element = priv->free_frames.next;
1392 list_del(element);
bb8c093b 1393 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY		 1394}
1395
bb8c093b 1396static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY		 1397{
1398 memset(frame, 0, sizeof(*frame));
1399 list_add(&frame->list, &priv->free_frames);
1400}
1401
bb8c093b 1402unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c
ZY		 1403 struct ieee80211_hdr *hdr,
1404 const u8 *dest, int left)
1405{
1406
bb8c093b 1407 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB		 1408 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
1409 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY		 1410 return 0;
1411
1412 if (priv->ibss_beacon->len > left)
1413 return 0;
1414
1415 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1416
1417 return priv->ibss_beacon->len;
1418}
1419
c24f0817 1420static u8 iwl3945_rate_get_lowest_plcp(struct iwl3945_priv *priv)
b481de9c
ZY		 1421{
1422 u8 i;
c24f0817
KA		 1423 int rate_mask;
1424
1425 /* Set rate mask*/
1426 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
dbce56a4 1427 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
c24f0817 1428 else
dbce56a4 1429 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
b481de9c
ZY		 1430
1431 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1432 i = iwl3945_rates[i].next_ieee) {
b481de9c 1433 if (rate_mask & (1 << i))
bb8c093b 1434 return iwl3945_rates[i].plcp;
b481de9c
ZY		 1435 }
1436
c24f0817
KA		 1437 /* No valid rate was found. Assign the lowest one */
1438 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
1439 return IWL_RATE_1M_PLCP;
1440 else
1441 return IWL_RATE_6M_PLCP;
b481de9c
ZY		 1442}
1443
bb8c093b 1444static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1445{
bb8c093b 1446 struct iwl3945_frame *frame;
b481de9c
ZY		 1447 unsigned int frame_size;
1448 int rc;
1449 u8 rate;
1450
bb8c093b 1451 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY		 1452
1453 if (!frame) {
1454 IWL_ERROR("Could not obtain free frame buffer for beacon "
1455 "command.\n");
1456 return -ENOMEM;
1457 }
1458
c24f0817 1459 rate = iwl3945_rate_get_lowest_plcp(priv);
b481de9c 1460
bb8c093b 1461 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1462
bb8c093b 1463 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1464 &frame->u.cmd[0]);
1465
bb8c093b 1466 iwl3945_free_frame(priv, frame);
b481de9c
ZY		 1467
1468 return rc;
1469}
1470
1471/******************************************************************************
1472 *
1473 * EEPROM related functions
1474 *
1475 ******************************************************************************/
1476
bb8c093b 1477static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY		 1478{
1479 memcpy(mac, priv->eeprom.mac_address, 6);
1480}
1481
74a3a250
RC		 1482/*
1483 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1484 * embedded controller) as EEPROM reader; each read is a series of pulses
1485 * to/from the EEPROM chip, not a single event, so even reads could conflict
1486 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1487 * simply claims ownership, which should be safe when this function is called
1488 * (i.e. before loading uCode!).
1489 */
1490static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1491{
1492 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1493 return 0;
1494}
1495
b481de9c 1496/**
bb8c093b 1497 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1498 *
6440adb5 1499 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY		 1500 *
1501 * NOTE: This routine uses the non-debug IO access functions.
1502 */
bb8c093b 1503int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c 1504{
58ff6d4d 1505 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1506 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c 1507 int sz = sizeof(priv->eeprom);
3d5717ad 1508 int ret;
b481de9c
ZY		 1509 u16 addr;
1510
1511 /* The EEPROM structure has several padding buffers within it
1512 * and when adding new EEPROM maps is subject to programmer errors
1513 * which may be very difficult to identify without explicitly
1514 * checking the resulting size of the eeprom map. */
1515 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1516
1517 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
6f147926 1518 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
b481de9c
ZY		 1519 return -ENOENT;
1520 }
1521
6440adb5 1522 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
3d5717ad
ZY		 1523 ret = iwl3945_eeprom_acquire_semaphore(priv);
1524 if (ret < 0) {
91e17473 1525 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY		 1526 return -ENOENT;
1527 }
1528
1529 /* eeprom is an array of 16bit values */
1530 for (addr = 0; addr < sz; addr += sizeof(u16)) {
3d5717ad 1531 u32 r;
b481de9c 1532
3d5717ad
ZY		 1533 _iwl3945_write32(priv, CSR_EEPROM_REG,
1534 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
1535 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
1536 ret = iwl3945_poll_direct_bit(priv, CSR_EEPROM_REG,
1537 CSR_EEPROM_REG_READ_VALID_MSK,
1538 IWL_EEPROM_ACCESS_TIMEOUT);
1539 if (ret < 0) {
6f147926 1540 IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
3d5717ad 1541 return ret;
b481de9c 1542 }
3d5717ad
ZY		 1543
1544 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
58ff6d4d 1545 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY		 1546 }
1547
1548 return 0;
1549}
1550
bb8c093b 1551static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 1552{
1553 if (priv->hw_setting.shared_virt)
1554 pci_free_consistent(priv->pci_dev,
bb8c093b 1555 sizeof(struct iwl3945_shared),
b481de9c
ZY		 1556 priv->hw_setting.shared_virt,
1557 priv->hw_setting.shared_phys);
1558}
1559
1560/**
bb8c093b 1561 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1562 *
1563 * return : set the bit for each supported rate insert in ie
1564 */
bb8c093b 1565static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1566 u16 basic_rate, int *left)
b481de9c
ZY		 1567{
1568 u16 ret_rates = 0, bit;
1569 int i;
c7c46676
TW		 1570 u8 *cnt = ie;
1571 u8 *rates = ie + 1;
b481de9c
ZY		 1572
1573 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1574 if (bit & supported_rate) {
1575 ret_rates |= bit;
bb8c093b 1576 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW		 1577 ((bit & basic_rate) ? 0x80 : 0x00);
1578 (*cnt)++;
1579 (*left)--;
1580 if ((*left <= 0) ||
1581 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1582 break;
1583 }
1584 }
1585
1586 return ret_rates;
1587}
1588
1589/**
bb8c093b 1590 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1591 */
bb8c093b 1592static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c 1593 struct ieee80211_mgmt *frame,
430cfe95 1594 int left)
b481de9c
ZY		 1595{
1596 int len = 0;
1597 u8 *pos = NULL;
c7c46676 1598 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY		 1599
1600 /* Make sure there is enough space for the probe request,
1601 * two mandatory IEs and the data */
1602 left -= 24;
1603 if (left < 0)
1604 return 0;
1605 len += 24;
1606
1607 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1608 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1609 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1610 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY		 1611 frame->seq_ctrl = 0;
1612
1613 /* fill in our indirect SSID IE */
1614 /* ...next IE... */
1615
1616 left -= 2;
1617 if (left < 0)
1618 return 0;
1619 len += 2;
1620 pos = &(frame->u.probe_req.variable[0]);
1621 *pos++ = WLAN_EID_SSID;
1622 *pos++ = 0;
1623
b481de9c
ZY		 1624 /* fill in supported rate */
1625 /* ...next IE... */
1626 left -= 2;
1627 if (left < 0)
1628 return 0;
c7c46676 1629
b481de9c
ZY		 1630 /* ... fill it in... */
1631 *pos++ = WLAN_EID_SUPP_RATES;
1632 *pos = 0;
c7c46676
TW		 1633
1634 priv->active_rate = priv->rates_mask;
1635 active_rates = priv->active_rate;
b481de9c
ZY		 1636 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1637
c7c46676 1638 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1639 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW		 1640 priv->active_rate_basic, &left);
1641 active_rates &= ~ret_rates;
1642
bb8c093b 1643 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW		 1644 priv->active_rate_basic, &left);
1645 active_rates &= ~ret_rates;
1646
b481de9c
ZY		 1647 len += 2 + *pos;
1648 pos += (*pos) + 1;
c7c46676 1649 if (active_rates == 0)
b481de9c
ZY		 1650 goto fill_end;
1651
1652 /* fill in supported extended rate */
1653 /* ...next IE... */
1654 left -= 2;
1655 if (left < 0)
1656 return 0;
1657 /* ... fill it in... */
1658 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1659 *pos = 0;
bb8c093b 1660 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1661 priv->active_rate_basic, &left);
b481de9c
ZY		 1662 if (*pos > 0)
1663 len += 2 + *pos;
1664
1665 fill_end:
1666 return (u16)len;
1667}
1668
1669/*
1670 * QoS support
1671*/
bb8c093b
CH		 1672static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1673 struct iwl3945_qosparam_cmd *qos)
b481de9c
ZY		 1674{
1675
bb8c093b
CH		 1676 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1677 sizeof(struct iwl3945_qosparam_cmd), qos);
b481de9c
ZY		 1678}
1679
bb8c093b 1680static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY		 1681{
1682 u16 cw_min = 15;
1683 u16 cw_max = 1023;
1684 u8 aifs = 2;
1685 u8 is_legacy = 0;
1686 unsigned long flags;
1687 int i;
1688
1689 spin_lock_irqsave(&priv->lock, flags);
1690 priv->qos_data.qos_active = 0;
1691
6d1ef1a3
WT		 1692 /* QoS always active in AP and ADHOC mode
1693 * In STA mode wait for association
1694 */
1695 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
1696 priv->iw_mode == NL80211_IFTYPE_AP)
1697 priv->qos_data.qos_active = 1;
1698 else
1699 priv->qos_data.qos_active = 0;
1700
1701
1702 /* check for legacy mode */
1703 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
1704 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
1705 (priv->iw_mode == NL80211_IFTYPE_STATION &&
1706 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
b481de9c
ZY		 1707 cw_min = 31;
1708 is_legacy = 1;
1709 }
1710
1711 if (priv->qos_data.qos_active)
1712 aifs = 3;
1713
1714 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1715 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1716 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1717 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1718 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1719
1720 if (priv->qos_data.qos_active) {
1721 i = 1;
1722 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1723 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1724 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1725 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1726 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1727
1728 i = 2;
1729 priv->qos_data.def_qos_parm.ac[i].cw_min =
1730 cpu_to_le16((cw_min + 1) / 2 - 1);
1731 priv->qos_data.def_qos_parm.ac[i].cw_max =
1732 cpu_to_le16(cw_max);
1733 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1734 if (is_legacy)
1735 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1736 cpu_to_le16(6016);
1737 else
1738 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1739 cpu_to_le16(3008);
1740 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1741
1742 i = 3;
1743 priv->qos_data.def_qos_parm.ac[i].cw_min =
1744 cpu_to_le16((cw_min + 1) / 4 - 1);
1745 priv->qos_data.def_qos_parm.ac[i].cw_max =
1746 cpu_to_le16((cw_max + 1) / 2 - 1);
1747 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1748 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1749 if (is_legacy)
1750 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1751 cpu_to_le16(3264);
1752 else
1753 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1754 cpu_to_le16(1504);
1755 } else {
1756 for (i = 1; i < 4; i++) {
1757 priv->qos_data.def_qos_parm.ac[i].cw_min =
1758 cpu_to_le16(cw_min);
1759 priv->qos_data.def_qos_parm.ac[i].cw_max =
1760 cpu_to_le16(cw_max);
1761 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1762 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1763 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1764 }
1765 }
1766 IWL_DEBUG_QOS("set QoS to default \n");
1767
1768 spin_unlock_irqrestore(&priv->lock, flags);
1769}
1770
bb8c093b 1771static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY		 1772{
1773 unsigned long flags;
1774
b481de9c
ZY		 1775 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1776 return;
1777
b481de9c
ZY		 1778 spin_lock_irqsave(&priv->lock, flags);
1779 priv->qos_data.def_qos_parm.qos_flags = 0;
1780
1781 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1782 !priv->qos_data.qos_cap.q_AP.txop_request)
1783 priv->qos_data.def_qos_parm.qos_flags |=
1784 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1785
1786 if (priv->qos_data.qos_active)
1787 priv->qos_data.def_qos_parm.qos_flags |=
1788 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1789
1790 spin_unlock_irqrestore(&priv->lock, flags);
1791
bb8c093b 1792 if (force || iwl3945_is_associated(priv)) {
a96a27f9 1793 IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
b481de9c
ZY		 1794 priv->qos_data.qos_active);
1795
bb8c093b 1796 iwl3945_send_qos_params_command(priv,
b481de9c
ZY		 1797 &(priv->qos_data.def_qos_parm));
1798 }
1799}
1800
b481de9c
ZY		 1801/*
1802 * Power management (not Tx power!) functions
1803 */
1804#define MSEC_TO_USEC 1024
1805
1806#define NOSLP __constant_cpu_to_le32(0)
1807#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
1808#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1809#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1810 __constant_cpu_to_le32(X1), \
1811 __constant_cpu_to_le32(X2), \
1812 __constant_cpu_to_le32(X3), \
1813 __constant_cpu_to_le32(X4)}
1814
1815
1816/* default power management (not Tx power) table values */
a96a27f9 1817/* for TIM 0-10 */
bb8c093b 1818static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY		 1819 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1820 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1821 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1822 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1823 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1824 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1825};
1826
a96a27f9 1827/* for TIM > 10 */
bb8c093b 1828static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY		 1829 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1830 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1831 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1832 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1833 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1834 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1835 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1836 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1837 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1838 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1839};
1840
bb8c093b 1841int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY		 1842{
1843 int rc = 0, i;
bb8c093b
CH		 1844 struct iwl3945_power_mgr *pow_data;
1845 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY		 1846 u16 pci_pm;
1847
1848 IWL_DEBUG_POWER("Initialize power \n");
1849
1850 pow_data = &(priv->power_data);
1851
1852 memset(pow_data, 0, sizeof(*pow_data));
1853
1854 pow_data->active_index = IWL_POWER_RANGE_0;
1855 pow_data->dtim_val = 0xffff;
1856
1857 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1858 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1859
1860 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1861 if (rc != 0)
1862 return 0;
1863 else {
bb8c093b 1864 struct iwl3945_powertable_cmd *cmd;
b481de9c
ZY		 1865
1866 IWL_DEBUG_POWER("adjust power command flags\n");
1867
1868 for (i = 0; i < IWL_POWER_AC; i++) {
1869 cmd = &pow_data->pwr_range_0[i].cmd;
1870
1871 if (pci_pm & 0x1)
1872 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1873 else
1874 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1875 }
1876 }
1877 return rc;
1878}
1879
bb8c093b
CH		 1880static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
1881 struct iwl3945_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 1882{
1883 int rc = 0, i;
1884 u8 skip;
1885 u32 max_sleep = 0;
bb8c093b 1886 struct iwl3945_power_vec_entry *range;
b481de9c 1887 u8 period = 0;
bb8c093b 1888 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY		 1889
1890 if (mode > IWL_POWER_INDEX_5) {
1891 IWL_DEBUG_POWER("Error invalid power mode \n");
1892 return -1;
1893 }
1894 pow_data = &(priv->power_data);
1895
1896 if (pow_data->active_index == IWL_POWER_RANGE_0)
1897 range = &pow_data->pwr_range_0[0];
1898 else
1899 range = &pow_data->pwr_range_1[1];
1900
bb8c093b 1901 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY		 1902
1903#ifdef IWL_MAC80211_DISABLE
1904 if (priv->assoc_network != NULL) {
1905 unsigned long flags;
1906
1907 period = priv->assoc_network->tim.tim_period;
1908 }
1909#endif /*IWL_MAC80211_DISABLE */
1910 skip = range[mode].no_dtim;
1911
1912 if (period == 0) {
1913 period = 1;
1914 skip = 0;
1915 }
1916
1917 if (skip == 0) {
1918 max_sleep = period;
1919 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1920 } else {
1921 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1922 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1923 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1924 }
1925
1926 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1927 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1928 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1929 }
1930
1931 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1932 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1933 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1934 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1935 le32_to_cpu(cmd->sleep_interval[0]),
1936 le32_to_cpu(cmd->sleep_interval[1]),
1937 le32_to_cpu(cmd->sleep_interval[2]),
1938 le32_to_cpu(cmd->sleep_interval[3]),
1939 le32_to_cpu(cmd->sleep_interval[4]));
1940
1941 return rc;
1942}
1943
bb8c093b 1944static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 1945{
9a62f73b 1946 u32 uninitialized_var(final_mode);
b481de9c 1947 int rc;
bb8c093b 1948 struct iwl3945_powertable_cmd cmd;
b481de9c
ZY		 1949
1950 /* If on battery, set to 3,
01ebd063 1951 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 1952 * else user level */
1953 switch (mode) {
1954 case IWL_POWER_BATTERY:
1955 final_mode = IWL_POWER_INDEX_3;
1956 break;
1957 case IWL_POWER_AC:
1958 final_mode = IWL_POWER_MODE_CAM;
1959 break;
1960 default:
1961 final_mode = mode;
1962 break;
1963 }
1964
bb8c093b 1965 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 1966
bb8c093b 1967 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 1968
1969 if (final_mode == IWL_POWER_MODE_CAM)
1970 clear_bit(STATUS_POWER_PMI, &priv->status);
1971 else
1972 set_bit(STATUS_POWER_PMI, &priv->status);
1973
1974 return rc;
1975}
1976
b481de9c 1977/**
bb8c093b 1978 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 1979 *
1980 * NOTE: priv->mutex is not required before calling this function
1981 */
bb8c093b 1982static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY		 1983{
1984 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1985 clear_bit(STATUS_SCANNING, &priv->status);
1986 return 0;
1987 }
1988
1989 if (test_bit(STATUS_SCANNING, &priv->status)) {
1990 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1991 IWL_DEBUG_SCAN("Queuing scan abort.\n");
1992 set_bit(STATUS_SCAN_ABORTING, &priv->status);
1993 queue_work(priv->workqueue, &priv->abort_scan);
1994
1995 } else
1996 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
1997
1998 return test_bit(STATUS_SCANNING, &priv->status);
1999 }
2000
2001 return 0;
2002}
2003
2004/**
bb8c093b 2005 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 2006 * @ms: amount of time to wait (in milliseconds) for scan to abort
2007 *
2008 * NOTE: priv->mutex must be held before calling this function
2009 */
bb8c093b 2010static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY		 2011{
2012 unsigned long now = jiffies;
2013 int ret;
2014
bb8c093b 2015 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY		 2016 if (ret && ms) {
2017 mutex_unlock(&priv->mutex);
2018 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2019 test_bit(STATUS_SCANNING, &priv->status))
2020 msleep(1);
2021 mutex_lock(&priv->mutex);
2022
2023 return test_bit(STATUS_SCANNING, &priv->status);
2024 }
2025
2026 return ret;
2027}
2028
b481de9c
ZY		 2029#define MAX_UCODE_BEACON_INTERVAL 1024
2030#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2031
bb8c093b 2032static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 2033{
2034 u16 new_val = 0;
2035 u16 beacon_factor = 0;
2036
2037 beacon_factor =
2038 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2039 / MAX_UCODE_BEACON_INTERVAL;
2040 new_val = beacon_val / beacon_factor;
2041
2042 return cpu_to_le16(new_val);
2043}
2044
bb8c093b 2045static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY		 2046{
2047 u64 interval_tm_unit;
2048 u64 tsf, result;
2049 unsigned long flags;
2050 struct ieee80211_conf *conf = NULL;
2051 u16 beacon_int = 0;
2052
2053 conf = ieee80211_get_hw_conf(priv->hw);
2054
2055 spin_lock_irqsave(&priv->lock, flags);
2056 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2057 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2058
2059 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2060
2061 tsf = priv->timestamp1;
2062 tsf = ((tsf << 32) | priv->timestamp0);
2063
2064 beacon_int = priv->beacon_int;
2065 spin_unlock_irqrestore(&priv->lock, flags);
2066
05c914fe 2067 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
b481de9c
ZY		 2068 if (beacon_int == 0) {
2069 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2070 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2071 } else {
2072 priv->rxon_timing.beacon_interval =
2073 cpu_to_le16(beacon_int);
2074 priv->rxon_timing.beacon_interval =
bb8c093b 2075 iwl3945_adjust_beacon_interval(
b481de9c
ZY		 2076 le16_to_cpu(priv->rxon_timing.beacon_interval));
2077 }
2078
2079 priv->rxon_timing.atim_window = 0;
2080 } else {
2081 priv->rxon_timing.beacon_interval =
bb8c093b 2082 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 2083 /* TODO: we need to get atim_window from upper stack
2084 * for now we set to 0 */
2085 priv->rxon_timing.atim_window = 0;
2086 }
2087
2088 interval_tm_unit =
2089 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2090 result = do_div(tsf, interval_tm_unit);
2091 priv->rxon_timing.beacon_init_val =
2092 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2093
2094 IWL_DEBUG_ASSOC
2095 ("beacon interval %d beacon timer %d beacon tim %d\n",
2096 le16_to_cpu(priv->rxon_timing.beacon_interval),
2097 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2098 le16_to_cpu(priv->rxon_timing.atim_window));
2099}
2100
bb8c093b 2101static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c 2102{
bb8c093b 2103 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 2104 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2105 return -EIO;
2106 }
2107
2108 if (test_bit(STATUS_SCANNING, &priv->status)) {
2109 IWL_DEBUG_SCAN("Scan already in progress.\n");
2110 return -EAGAIN;
2111 }
2112
2113 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2114 IWL_DEBUG_SCAN("Scan request while abort pending. "
2115 "Queuing.\n");
2116 return -EAGAIN;
2117 }
2118
2119 IWL_DEBUG_INFO("Starting scan...\n");
66b5004d
RR		 2120 if (priv->cfg->sku & IWL_SKU_G)
2121 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
2122 if (priv->cfg->sku & IWL_SKU_A)
2123 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 2124 set_bit(STATUS_SCANNING, &priv->status);
2125 priv->scan_start = jiffies;
2126 priv->scan_pass_start = priv->scan_start;
2127
2128 queue_work(priv->workqueue, &priv->request_scan);
2129
2130 return 0;
2131}
2132
bb8c093b 2133static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2134{
bb8c093b 2135 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 2136
2137 if (hw_decrypt)
2138 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2139 else
2140 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2141
2142 return 0;
2143}
2144
8318d78a
JB		 2145static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2146 enum ieee80211_band band)
b481de9c 2147{
8318d78a 2148 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY		 2149 priv->staging_rxon.flags &=
2150 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2151 | RXON_FLG_CCK_MSK);
2152 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2153 } else {
bb8c093b 2154 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY		 2155 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2156 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2157 else
2158 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2159
05c914fe 2160 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 2161 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2162
2163 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2164 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2165 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2166 }
2167}
2168
2169/*
01ebd063 2170 * initialize rxon structure with default values from eeprom
b481de9c 2171 */
60294de3
ZY		 2172static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv,
2173 int mode)
b481de9c 2174{
bb8c093b 2175 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 2176
2177 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2178
60294de3 2179 switch (mode) {
05c914fe 2180 case NL80211_IFTYPE_AP:
b481de9c
ZY		 2181 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2182 break;
2183
05c914fe 2184 case NL80211_IFTYPE_STATION:
b481de9c
ZY		 2185 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2186 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2187 break;
2188
05c914fe 2189 case NL80211_IFTYPE_ADHOC:
b481de9c
ZY		 2190 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2191 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2192 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2193 RXON_FILTER_ACCEPT_GRP_MSK;
2194 break;
2195
05c914fe 2196 case NL80211_IFTYPE_MONITOR:
b481de9c
ZY		 2197 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2198 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2199 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2200 break;
69dc5d9d 2201 default:
60294de3 2202 IWL_ERROR("Unsupported interface type %d\n", mode);
69dc5d9d 2203 break;
b481de9c
ZY		 2204 }
2205
2206#if 0
2207 /* TODO: Figure out when short_preamble would be set and cache from
2208 * that */
2209 if (!hw_to_local(priv->hw)->short_preamble)
2210 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2211 else
2212 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2213#endif
2214
8318d78a 2215 ch_info = iwl3945_get_channel_info(priv, priv->band,
25b3f57c 2216 le16_to_cpu(priv->active_rxon.channel));
b481de9c
ZY		 2217
2218 if (!ch_info)
2219 ch_info = &priv->channel_info[0];
2220
2221 /*
2222 * in some case A channels are all non IBSS
2223 * in this case force B/G channel
2224 */
60294de3 2225 if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
b481de9c
ZY		 2226 ch_info = &priv->channel_info[0];
2227
2228 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2229 if (is_channel_a_band(ch_info))
8318d78a 2230 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 2231 else
8318d78a 2232 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 2233
8318d78a 2234 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY		 2235
2236 priv->staging_rxon.ofdm_basic_rates =
2237 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2238 priv->staging_rxon.cck_basic_rates =
2239 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2240}
2241
bb8c093b 2242static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2243{
05c914fe 2244 if (mode == NL80211_IFTYPE_ADHOC) {
bb8c093b 2245 const struct iwl3945_channel_info *ch_info;
b481de9c 2246
bb8c093b 2247 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2248 priv->band,
b481de9c
ZY		 2249 le16_to_cpu(priv->staging_rxon.channel));
2250
2251 if (!ch_info || !is_channel_ibss(ch_info)) {
2252 IWL_ERROR("channel %d not IBSS channel\n",
2253 le16_to_cpu(priv->staging_rxon.channel));
2254 return -EINVAL;
2255 }
2256 }
2257
60294de3 2258 iwl3945_connection_init_rx_config(priv, mode);
b481de9c
ZY		 2259 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2260
bb8c093b 2261 iwl3945_clear_stations_table(priv);
b481de9c 2262
a96a27f9 2263 /* don't commit rxon if rf-kill is on*/
fde3571f
MA		 2264 if (!iwl3945_is_ready_rf(priv))
2265 return -EAGAIN;
2266
2267 cancel_delayed_work(&priv->scan_check);
2268 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2269 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2270 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2271 return -EAGAIN;
2272 }
2273
bb8c093b 2274 iwl3945_commit_rxon(priv);
b481de9c
ZY		 2275
2276 return 0;
2277}
2278
bb8c093b 2279static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
e039fa4a 2280 struct ieee80211_tx_info *info,
bb8c093b 2281 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2282 struct sk_buff *skb_frag,
2283 int last_frag)
2284{
1c014420 2285 struct iwl3945_hw_key *keyinfo =
e039fa4a 2286 &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
b481de9c
ZY		 2287
2288 switch (keyinfo->alg) {
2289 case ALG_CCMP:
2290 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2291 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
a96a27f9 2292 IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
b481de9c
ZY		 2293 break;
2294
2295 case ALG_TKIP:
2296#if 0
2297 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2298
2299 if (last_frag)
2300 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2301 8);
2302 else
2303 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2304#endif
2305 break;
2306
2307 case ALG_WEP:
2308 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 2309 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY		 2310
2311 if (keyinfo->keylen == 13)
2312 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2313
2314 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2315
2316 IWL_DEBUG_TX("Configuring packet for WEP encryption "
e039fa4a 2317 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY		 2318 break;
2319
b481de9c
ZY		 2320 default:
2321 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2322 break;
2323 }
2324}
2325
2326/*
2327 * handle build REPLY_TX command notification.
2328 */
bb8c093b
CH		 2329static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2330 struct iwl3945_cmd *cmd,
e039fa4a 2331 struct ieee80211_tx_info *info,
b481de9c
ZY		 2332 struct ieee80211_hdr *hdr,
2333 int is_unicast, u8 std_id)
2334{
fd7c8a40 2335 __le16 fc = hdr->frame_control;
b481de9c 2336 __le32 tx_flags = cmd->cmd.tx.tx_flags;
e6a9854b 2337 u8 rc_flags = info->control.rates[0].flags;
b481de9c
ZY		 2338
2339 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 2340 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 2341 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 2342 if (ieee80211_is_mgmt(fc))
b481de9c 2343 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 2344 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY		 2345 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2346 tx_flags |= TX_CMD_FLG_TSF_MSK;
2347 } else {
2348 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2349 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2350 }
2351
2352 cmd->cmd.tx.sta_id = std_id;
8b7b1e05 2353 if (ieee80211_has_morefrags(fc))
b481de9c
ZY		 2354 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2355
fd7c8a40
HH		 2356 if (ieee80211_is_data_qos(fc)) {
2357 u8 *qc = ieee80211_get_qos_ctl(hdr);
54dbb525 2358 cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
b481de9c 2359 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2360 } else {
b481de9c 2361 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2362 }
b481de9c 2363
e6a9854b 2364 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
b481de9c
ZY		 2365 tx_flags |= TX_CMD_FLG_RTS_MSK;
2366 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 2367 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
b481de9c
ZY		 2368 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2369 tx_flags |= TX_CMD_FLG_CTS_MSK;
2370 }
2371
2372 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2373 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2374
2375 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH		 2376 if (ieee80211_is_mgmt(fc)) {
2377 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
bc434dd2 2378 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2379 else
bc434dd2 2380 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2381 } else {
b481de9c 2382 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
ab53d8af
MA		 2383#ifdef CONFIG_IWL3945_LEDS
2384 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2385#endif
2386 }
b481de9c
ZY		 2387
2388 cmd->cmd.tx.driver_txop = 0;
2389 cmd->cmd.tx.tx_flags = tx_flags;
2390 cmd->cmd.tx.next_frame_len = 0;
2391}
2392
6440adb5
CB		 2393/**
2394 * iwl3945_get_sta_id - Find station's index within station table
2395 */
bb8c093b 2396static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY		 2397{
2398 int sta_id;
2399 u16 fc = le16_to_cpu(hdr->frame_control);
2400
6440adb5 2401 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2402 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2403 is_multicast_ether_addr(hdr->addr1))
2404 return priv->hw_setting.bcast_sta_id;
2405
2406 switch (priv->iw_mode) {
2407
6440adb5
CB		 2408 /* If we are a client station in a BSS network, use the special
2409 * AP station entry (that's the only station we communicate with) */
05c914fe 2410 case NL80211_IFTYPE_STATION:
b481de9c
ZY		 2411 return IWL_AP_ID;
2412
2413 /* If we are an AP, then find the station, or use BCAST */
05c914fe 2414 case NL80211_IFTYPE_AP:
bb8c093b 2415 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2416 if (sta_id != IWL_INVALID_STATION)
2417 return sta_id;
2418 return priv->hw_setting.bcast_sta_id;
2419
6440adb5
CB		 2420 /* If this frame is going out to an IBSS network, find the station,
2421 * or create a new station table entry */
05c914fe 2422 case NL80211_IFTYPE_ADHOC: {
6440adb5 2423 /* Create new station table entry */
bb8c093b 2424 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2425 if (sta_id != IWL_INVALID_STATION)
2426 return sta_id;
2427
bb8c093b 2428 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY		 2429
2430 if (sta_id != IWL_INVALID_STATION)
2431 return sta_id;
2432
e174961c 2433 IWL_DEBUG_DROP("Station %pM not in station map. "
b481de9c 2434 "Defaulting to broadcast...\n",
e174961c 2435 hdr->addr1);
bb8c093b 2436 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2437 return priv->hw_setting.bcast_sta_id;
0795af57 2438 }
914233d6
SG		 2439 /* If we are in monitor mode, use BCAST. This is required for
2440 * packet injection. */
05c914fe 2441 case NL80211_IFTYPE_MONITOR:
914233d6
SG		 2442 return priv->hw_setting.bcast_sta_id;
2443
b481de9c 2444 default:
6f147926 2445 IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
b481de9c
ZY		 2446 return priv->hw_setting.bcast_sta_id;
2447 }
2448}
2449
2450/*
2451 * start REPLY_TX command process
2452 */
e039fa4a 2453static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
b481de9c
ZY		 2454{
2455 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 2456 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bb8c093b 2457 struct iwl3945_tfd_frame *tfd;
b481de9c 2458 u32 *control_flags;
e2530083 2459 int txq_id = skb_get_queue_mapping(skb);
bb8c093b
CH		 2460 struct iwl3945_tx_queue *txq = NULL;
2461 struct iwl3945_queue *q = NULL;
b481de9c
ZY		 2462 dma_addr_t phys_addr;
2463 dma_addr_t txcmd_phys;
bb8c093b 2464 struct iwl3945_cmd *out_cmd = NULL;
54dbb525
TW		 2465 u16 len, idx, len_org, hdr_len;
2466 u8 id;
2467 u8 unicast;
b481de9c 2468 u8 sta_id;
54dbb525 2469 u8 tid = 0;
b481de9c 2470 u16 seq_number = 0;
fd7c8a40 2471 __le16 fc;
b481de9c 2472 u8 wait_write_ptr = 0;
54dbb525 2473 u8 *qc = NULL;
b481de9c
ZY		 2474 unsigned long flags;
2475 int rc;
2476
2477 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2478 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 2479 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2480 goto drop_unlock;
2481 }
2482
e039fa4a 2483 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY		 2484 IWL_ERROR("ERROR: No TX rate available.\n");
2485 goto drop_unlock;
2486 }
2487
2488 unicast = !is_multicast_ether_addr(hdr->addr1);
2489 id = 0;
2490
fd7c8a40 2491 fc = hdr->frame_control;
b481de9c 2492
c8b0e6e1 2493#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 2494 if (ieee80211_is_auth(fc))
2495 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 2496 else if (ieee80211_is_assoc_req(fc))
b481de9c 2497 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 2498 else if (ieee80211_is_reassoc_req(fc))
b481de9c
ZY		 2499 IWL_DEBUG_TX("Sending REASSOC frame\n");
2500#endif
2501
7878a5a4 2502 /* drop all data frame if we are not associated */
914233d6 2503 if (ieee80211_is_data(fc) &&
05c914fe 2504 (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
914233d6 2505 (!iwl3945_is_associated(priv) ||
05c914fe 2506 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
bb8c093b 2507 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY		 2508 goto drop_unlock;
2509 }
2510
2511 spin_unlock_irqrestore(&priv->lock, flags);
2512
7294ec95 2513 hdr_len = ieee80211_hdrlen(fc);
6440adb5
CB		 2514
2515 /* Find (or create) index into station table for destination station */
bb8c093b 2516 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2517 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 2518 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
2519 hdr->addr1);
b481de9c
ZY		 2520 goto drop;
2521 }
2522
2523 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2524
fd7c8a40
HH		 2525 if (ieee80211_is_data_qos(fc)) {
2526 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 2527 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
b481de9c
ZY		 2528 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2529 IEEE80211_SCTL_SEQ;
2530 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2531 (hdr->seq_ctrl &
2532 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2533 seq_number += 0x10;
2534 }
6440adb5
CB		 2535
2536 /* Descriptor for chosen Tx queue */
b481de9c
ZY		 2537 txq = &priv->txq[txq_id];
2538 q = &txq->q;
2539
2540 spin_lock_irqsave(&priv->lock, flags);
2541
6440adb5 2542 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2543 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 2544 memset(tfd, 0, sizeof(*tfd));
2545 control_flags = (u32 *) tfd;
fc4b6853 2546 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2547
6440adb5 2548 /* Set up driver data for this TFD */
bb8c093b 2549 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853 2550 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB		 2551
2552 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY		 2553 out_cmd = &txq->cmd[idx];
2554 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2555 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB		 2556
2557 /*
2558 * Set up the Tx-command (not MAC!) header.
2559 * Store the chosen Tx queue and TFD index within the sequence field;
2560 * after Tx, uCode's Tx response will return this value so driver can
2561 * locate the frame within the tx queue and do post-tx processing.
2562 */
b481de9c
ZY		 2563 out_cmd->hdr.cmd = REPLY_TX;
2564 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2565 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB		 2566
2567 /* Copy MAC header from skb into command buffer */
b481de9c
ZY		 2568 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2569
6440adb5
CB		 2570 /*
2571 * Use the first empty entry in this queue's command buffer array
2572 * to contain the Tx command and MAC header concatenated together
2573 * (payload data will be in another buffer).
2574 * Size of this varies, due to varying MAC header length.
2575 * If end is not dword aligned, we'll have 2 extra bytes at the end
2576 * of the MAC header (device reads on dword boundaries).
2577 * We'll tell device about this padding later.
2578 */
b481de9c 2579 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2580 sizeof(struct iwl3945_cmd_header) + hdr_len;
b481de9c
ZY		 2581
2582 len_org = len;
2583 len = (len + 3) & ~3;
2584
2585 if (len_org != len)
2586 len_org = 1;
2587 else
2588 len_org = 0;
2589
6440adb5
CB		 2590 /* Physical address of this Tx command's header (not MAC header!),
2591 * within command buffer array. */
bb8c093b
CH		 2592 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2593 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2594
6440adb5
CB		 2595 /* Add buffer containing Tx command and MAC(!) header to TFD's
2596 * first entry */
bb8c093b 2597 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c 2598
d0f09804 2599 if (info->control.hw_key)
e039fa4a 2600 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
b481de9c 2601
6440adb5
CB		 2602 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2603 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 2604 len = skb->len - hdr_len;
2605 if (len) {
2606 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2607 len, PCI_DMA_TODEVICE);
bb8c093b 2608 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 2609 }
2610
b481de9c 2611 if (!len)
6440adb5 2612 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY		 2613 *control_flags = TFD_CTL_COUNT_SET(1);
2614 else
6440adb5
CB		 2615 /* Else use 2 buffers.
2616 * Tell 3945 about any padding after MAC header */
b481de9c
ZY		 2617 *control_flags = TFD_CTL_COUNT_SET(2) |
2618 TFD_CTL_PAD_SET(U32_PAD(len));
2619
6440adb5 2620 /* Total # bytes to be transmitted */
b481de9c
ZY		 2621 len = (u16)skb->len;
2622 out_cmd->cmd.tx.len = cpu_to_le16(len);
2623
2624 /* TODO need this for burst mode later on */
e039fa4a 2625 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
b481de9c
ZY		 2626
2627 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 2628 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
b481de9c
ZY		 2629
2630 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2631 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2632
8b7b1e05 2633 if (!ieee80211_has_morefrags(hdr->frame_control)) {
b481de9c 2634 txq->need_update = 1;
3ac7f146 2635 if (qc)
b481de9c 2636 priv->stations[sta_id].tid[tid].seq_number = seq_number;
b481de9c
ZY		 2637 } else {
2638 wait_write_ptr = 1;
2639 txq->need_update = 0;
2640 }
2641
bb8c093b 2642 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY		 2643 sizeof(out_cmd->cmd.tx));
2644
bb8c093b 2645 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
7294ec95 2646 ieee80211_hdrlen(fc));
b481de9c 2647
6440adb5 2648 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2649 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2650 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2651 spin_unlock_irqrestore(&priv->lock, flags);
2652
2653 if (rc)
2654 return rc;
2655
bb8c093b 2656 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY		 2657 && priv->mac80211_registered) {
2658 if (wait_write_ptr) {
2659 spin_lock_irqsave(&priv->lock, flags);
2660 txq->need_update = 1;
bb8c093b 2661 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2662 spin_unlock_irqrestore(&priv->lock, flags);
2663 }
2664
e2530083 2665 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
b481de9c
ZY		 2666 }
2667
2668 return 0;
2669
2670drop_unlock:
2671 spin_unlock_irqrestore(&priv->lock, flags);
2672drop:
2673 return -1;
2674}
2675
bb8c093b 2676static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c 2677{
8318d78a 2678 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY		 2679 struct ieee80211_rate *rate;
2680 int i;
2681
8318d78a
JB		 2682 sband = iwl3945_get_band(priv, priv->band);
2683 if (!sband) {
c4ba9621
SA		 2684 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2685 return;
2686 }
b481de9c
ZY		 2687
2688 priv->active_rate = 0;
2689 priv->active_rate_basic = 0;
2690
8318d78a
JB		 2691 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2692 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2693
2694 for (i = 0; i < sband->n_bitrates; i++) {
2695 rate = &sband->bitrates[i];
2696 if ((rate->hw_value < IWL_RATE_COUNT) &&
2697 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2698 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2699 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2700 priv->active_rate |= (1 << rate->hw_value);
2701 }
b481de9c
ZY		 2702 }
2703
2704 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2705 priv->active_rate, priv->active_rate_basic);
2706
2707 /*
2708 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2709 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2710 * OFDM
2711 */
2712 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2713 priv->staging_rxon.cck_basic_rates =
2714 ((priv->active_rate_basic &
2715 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2716 else
2717 priv->staging_rxon.cck_basic_rates =
2718 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2719
2720 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2721 priv->staging_rxon.ofdm_basic_rates =
2722 ((priv->active_rate_basic &
2723 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2724 IWL_FIRST_OFDM_RATE) & 0xFF;
2725 else
2726 priv->staging_rxon.ofdm_basic_rates =
2727 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2728}
2729
bb8c093b 2730static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY		 2731{
2732 unsigned long flags;
2733
2734 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2735 return;
2736
2737 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2738 disable_radio ? "OFF" : "ON");
2739
2740 if (disable_radio) {
bb8c093b 2741 iwl3945_scan_cancel(priv);
b481de9c 2742 /* FIXME: This is a workaround for AP */
05c914fe 2743 if (priv->iw_mode != NL80211_IFTYPE_AP) {
b481de9c 2744 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2745 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 2746 CSR_UCODE_SW_BIT_RFKILL);
2747 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 2748 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY		 2749 set_bit(STATUS_RF_KILL_SW, &priv->status);
2750 }
2751 return;
2752 }
2753
2754 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2755 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2756
2757 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2758 spin_unlock_irqrestore(&priv->lock, flags);
2759
2760 /* wake up ucode */
2761 msleep(10);
2762
2763 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 2764 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
2765 if (!iwl3945_grab_nic_access(priv))
2766 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2767 spin_unlock_irqrestore(&priv->lock, flags);
2768
2769 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2770 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2771 "disabled by HW switch\n");
2772 return;
2773 }
2774
808e72a0
ZY		 2775 if (priv->is_open)
2776 queue_work(priv->workqueue, &priv->restart);
b481de9c
ZY		 2777 return;
2778}
2779
bb8c093b 2780void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 2781 u32 decrypt_res, struct ieee80211_rx_status *stats)
2782{
2783 u16 fc =
2784 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2785
2786 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2787 return;
2788
2789 if (!(fc & IEEE80211_FCTL_PROTECTED))
2790 return;
2791
2792 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2793 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2794 case RX_RES_STATUS_SEC_TYPE_TKIP:
2795 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2796 RX_RES_STATUS_BAD_ICV_MIC)
2797 stats->flag |= RX_FLAG_MMIC_ERROR;
2798 case RX_RES_STATUS_SEC_TYPE_WEP:
2799 case RX_RES_STATUS_SEC_TYPE_CCMP:
2800 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2801 RX_RES_STATUS_DECRYPT_OK) {
2802 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2803 stats->flag |= RX_FLAG_DECRYPTED;
2804 }
2805 break;
2806
2807 default:
2808 break;
2809 }
2810}
2811
c8b0e6e1 2812#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 2813
2814#include "iwl-spectrum.h"
2815
2816#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2817#define BEACON_TIME_MASK_HIGH 0xFF000000
2818#define TIME_UNIT 1024
2819
2820/*
2821 * extended beacon time format
2822 * time in usec will be changed into a 32-bit value in 8:24 format
2823 * the high 1 byte is the beacon counts
2824 * the lower 3 bytes is the time in usec within one beacon interval
2825 */
2826
bb8c093b 2827static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 2828{
2829 u32 quot;
2830 u32 rem;
2831 u32 interval = beacon_interval * 1024;
2832
2833 if (!interval || !usec)
2834 return 0;
2835
2836 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
2837 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
2838
2839 return (quot << 24) + rem;
2840}
2841
2842/* base is usually what we get from ucode with each received frame,
2843 * the same as HW timer counter counting down
2844 */
2845
bb8c093b 2846static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 2847{
2848 u32 base_low = base & BEACON_TIME_MASK_LOW;
2849 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
2850 u32 interval = beacon_interval * TIME_UNIT;
2851 u32 res = (base & BEACON_TIME_MASK_HIGH) +
2852 (addon & BEACON_TIME_MASK_HIGH);
2853
2854 if (base_low > addon_low)
2855 res += base_low - addon_low;
2856 else if (base_low < addon_low) {
2857 res += interval + base_low - addon_low;
2858 res += (1 << 24);
2859 } else
2860 res += (1 << 24);
2861
2862 return cpu_to_le32(res);
2863}
2864
bb8c093b 2865static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY		 2866 struct ieee80211_measurement_params *params,
2867 u8 type)
2868{
bb8c093b
CH		 2869 struct iwl3945_spectrum_cmd spectrum;
2870 struct iwl3945_rx_packet *res;
2871 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 2872 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
2873 .data = (void *)&spectrum,
2874 .meta.flags = CMD_WANT_SKB,
2875 };
2876 u32 add_time = le64_to_cpu(params->start_time);
2877 int rc;
2878 int spectrum_resp_status;
2879 int duration = le16_to_cpu(params->duration);
2880
bb8c093b 2881 if (iwl3945_is_associated(priv))
b481de9c 2882 add_time =
bb8c093b 2883 iwl3945_usecs_to_beacons(
b481de9c
ZY		 2884 le64_to_cpu(params->start_time) - priv->last_tsf,
2885 le16_to_cpu(priv->rxon_timing.beacon_interval));
2886
2887 memset(&spectrum, 0, sizeof(spectrum));
2888
2889 spectrum.channel_count = cpu_to_le16(1);
2890 spectrum.flags =
2891 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
2892 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
2893 cmd.len = sizeof(spectrum);
2894 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
2895
bb8c093b 2896 if (iwl3945_is_associated(priv))
b481de9c 2897 spectrum.start_time =
bb8c093b 2898 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 2899 add_time,
2900 le16_to_cpu(priv->rxon_timing.beacon_interval));
2901 else
2902 spectrum.start_time = 0;
2903
2904 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
2905 spectrum.channels[0].channel = params->channel;
2906 spectrum.channels[0].type = type;
2907 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
2908 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
2909 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
2910
bb8c093b 2911 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 2912 if (rc)
2913 return rc;
2914
bb8c093b 2915 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 2916 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
2917 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
2918 rc = -EIO;
2919 }
2920
2921 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
2922 switch (spectrum_resp_status) {
2923 case 0: /* Command will be handled */
2924 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS		 2925 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
2926 res->u.spectrum.id);
b481de9c
ZY		 2927 priv->measurement_status &= ~MEASUREMENT_READY;
2928 }
2929 priv->measurement_status |= MEASUREMENT_ACTIVE;
2930 rc = 0;
2931 break;
2932
2933 case 1: /* Command will not be handled */
2934 rc = -EAGAIN;
2935 break;
2936 }
2937
2938 dev_kfree_skb_any(cmd.meta.u.skb);
2939
2940 return rc;
2941}
2942#endif
2943
bb8c093b
CH		 2944static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
2945 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 2946{
bb8c093b
CH		 2947 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
2948 struct iwl3945_alive_resp *palive;
b481de9c
ZY		 2949 struct delayed_work *pwork;
2950
2951 palive = &pkt->u.alive_frame;
2952
2953 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
2954 "0x%01X 0x%01X\n",
2955 palive->is_valid, palive->ver_type,
2956 palive->ver_subtype);
2957
2958 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
2959 IWL_DEBUG_INFO("Initialization Alive received.\n");
2960 memcpy(&priv->card_alive_init,
2961 &pkt->u.alive_frame,
bb8c093b 2962 sizeof(struct iwl3945_init_alive_resp));
b481de9c
ZY		 2963 pwork = &priv->init_alive_start;
2964 } else {
2965 IWL_DEBUG_INFO("Runtime Alive received.\n");
2966 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 2967 sizeof(struct iwl3945_alive_resp));
b481de9c 2968 pwork = &priv->alive_start;
bb8c093b 2969 iwl3945_disable_events(priv);
b481de9c
ZY		 2970 }
2971
2972 /* We delay the ALIVE response by 5ms to
2973 * give the HW RF Kill time to activate... */
2974 if (palive->is_valid == UCODE_VALID_OK)
2975 queue_delayed_work(priv->workqueue, pwork,
2976 msecs_to_jiffies(5));
2977 else
2978 IWL_WARNING("uCode did not respond OK.\n");
2979}
2980
bb8c093b
CH		 2981static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
2982 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 2983{
bb8c093b 2984 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 2985
2986 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
2987 return;
2988}
2989
bb8c093b
CH		 2990static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
2991 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 2992{
bb8c093b 2993 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 2994
2995 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
2996 "seq 0x%04X ser 0x%08X\n",
2997 le32_to_cpu(pkt->u.err_resp.error_type),
2998 get_cmd_string(pkt->u.err_resp.cmd_id),
2999 pkt->u.err_resp.cmd_id,
3000 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3001 le32_to_cpu(pkt->u.err_resp.error_info));
3002}
3003
3004#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3005
bb8c093b 3006static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3007{
bb8c093b
CH		 3008 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3009 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3010 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 3011 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3012 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3013 rxon->channel = csa->channel;
3014 priv->staging_rxon.channel = csa->channel;
3015}
3016
bb8c093b
CH		 3017static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3018 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3019{
c8b0e6e1 3020#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
bb8c093b
CH		 3021 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3022 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 3023
3024 if (!report->state) {
3025 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3026 "Spectrum Measure Notification: Start\n");
3027 return;
3028 }
3029
3030 memcpy(&priv->measure_report, report, sizeof(*report));
3031 priv->measurement_status |= MEASUREMENT_READY;
3032#endif
3033}
3034
bb8c093b
CH		 3035static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3036 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3037{
c8b0e6e1 3038#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3039 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3040 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 3041 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3042 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3043#endif
3044}
3045
bb8c093b
CH		 3046static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3047 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3048{
bb8c093b 3049 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3050 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3051 "notification for %s:\n",
3052 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3053 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 3054}
3055
bb8c093b 3056static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3057{
bb8c093b
CH		 3058 struct iwl3945_priv *priv =
3059 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY		 3060 struct sk_buff *beacon;
3061
3062 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 3063 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 3064
3065 if (!beacon) {
3066 IWL_ERROR("update beacon failed\n");
3067 return;
3068 }
3069
3070 mutex_lock(&priv->mutex);
3071 /* new beacon skb is allocated every time; dispose previous.*/
3072 if (priv->ibss_beacon)
3073 dev_kfree_skb(priv->ibss_beacon);
3074
3075 priv->ibss_beacon = beacon;
3076 mutex_unlock(&priv->mutex);
3077
bb8c093b 3078 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 3079}
3080
bb8c093b
CH		 3081static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3082 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3083{
c8b0e6e1 3084#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3085 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3086 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY		 3087 u8 rate = beacon->beacon_notify_hdr.rate;
3088
3089 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3090 "tsf %d %d rate %d\n",
3091 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3092 beacon->beacon_notify_hdr.failure_frame,
3093 le32_to_cpu(beacon->ibss_mgr_status),
3094 le32_to_cpu(beacon->high_tsf),
3095 le32_to_cpu(beacon->low_tsf), rate);
3096#endif
3097
05c914fe 3098 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY		 3099 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3100 queue_work(priv->workqueue, &priv->beacon_update);
3101}
3102
3103/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH		 3104static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3105 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3106{
c8b0e6e1 3107#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3108 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3109 struct iwl3945_scanreq_notification *notif =
3110 (struct iwl3945_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 3111
3112 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3113#endif
3114}
3115
3116/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH		 3117static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3118 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3119{
bb8c093b
CH		 3120 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3121 struct iwl3945_scanstart_notification *notif =
3122 (struct iwl3945_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 3123 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3124 IWL_DEBUG_SCAN("Scan start: "
3125 "%d [802.11%s] "
3126 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3127 notif->channel,
3128 notif->band ? "bg" : "a",
3129 notif->tsf_high,
3130 notif->tsf_low, notif->status, notif->beacon_timer);
3131}
3132
3133/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH		 3134static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3135 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3136{
bb8c093b
CH		 3137 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3138 struct iwl3945_scanresults_notification *notif =
3139 (struct iwl3945_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 3140
3141 IWL_DEBUG_SCAN("Scan ch.res: "
3142 "%d [802.11%s] "
3143 "(TSF: 0x%08X:%08X) - %d "
3144 "elapsed=%lu usec (%dms since last)\n",
3145 notif->channel,
3146 notif->band ? "bg" : "a",
3147 le32_to_cpu(notif->tsf_high),
3148 le32_to_cpu(notif->tsf_low),
3149 le32_to_cpu(notif->statistics[0]),
3150 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3151 jiffies_to_msecs(elapsed_jiffies
3152 (priv->last_scan_jiffies, jiffies)));
3153
3154 priv->last_scan_jiffies = jiffies;
7878a5a4 3155 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3156}
3157
3158/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH		 3159static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3160 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3161{
bb8c093b
CH		 3162 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3163 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 3164
3165 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3166 scan_notif->scanned_channels,
3167 scan_notif->tsf_low,
3168 scan_notif->tsf_high, scan_notif->status);
3169
3170 /* The HW is no longer scanning */
3171 clear_bit(STATUS_SCAN_HW, &priv->status);
3172
3173 /* The scan completion notification came in, so kill that timer... */
3174 cancel_delayed_work(&priv->scan_check);
3175
3176 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
66b5004d
RR		 3177 (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
3178 "2.4" : "5.2",
b481de9c
ZY		 3179 jiffies_to_msecs(elapsed_jiffies
3180 (priv->scan_pass_start, jiffies)));
3181
66b5004d
RR		 3182 /* Remove this scanned band from the list of pending
3183 * bands to scan, band G precedes A in order of scanning
3184 * as seen in iwl3945_bg_request_scan */
3185 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
3186 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
3187 else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
3188 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 3189
3190 /* If a request to abort was given, or the scan did not succeed
3191 * then we reset the scan state machine and terminate,
3192 * re-queuing another scan if one has been requested */
3193 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3194 IWL_DEBUG_INFO("Aborted scan completed.\n");
3195 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3196 } else {
3197 /* If there are more bands on this scan pass reschedule */
3198 if (priv->scan_bands > 0)
3199 goto reschedule;
3200 }
3201
3202 priv->last_scan_jiffies = jiffies;
7878a5a4 3203 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3204 IWL_DEBUG_INFO("Setting scan to off\n");
3205
3206 clear_bit(STATUS_SCANNING, &priv->status);
3207
3208 IWL_DEBUG_INFO("Scan took %dms\n",
3209 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3210
3211 queue_work(priv->workqueue, &priv->scan_completed);
3212
3213 return;
3214
3215reschedule:
3216 priv->scan_pass_start = jiffies;
3217 queue_work(priv->workqueue, &priv->request_scan);
3218}
3219
3220/* Handle notification from uCode that card's power state is changing
3221 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH		 3222static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3223 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3224{
bb8c093b 3225 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3226 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3227 unsigned long status = priv->status;
3228
3229 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3230 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3231 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3232
bb8c093b 3233 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3234 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3235
3236 if (flags & HW_CARD_DISABLED)
3237 set_bit(STATUS_RF_KILL_HW, &priv->status);
3238 else
3239 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3240
3241
3242 if (flags & SW_CARD_DISABLED)
3243 set_bit(STATUS_RF_KILL_SW, &priv->status);
3244 else
3245 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3246
bb8c093b 3247 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3248
3249 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3250 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3251 (test_bit(STATUS_RF_KILL_SW, &status) !=
3252 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3253 queue_work(priv->workqueue, &priv->rf_kill);
3254 else
3255 wake_up_interruptible(&priv->wait_command_queue);
3256}
3257
3258/**
bb8c093b 3259 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 3260 *
3261 * Setup the RX handlers for each of the reply types sent from the uCode
3262 * to the host.
3263 *
3264 * This function chains into the hardware specific files for them to setup
3265 * any hardware specific handlers as well.
3266 */
bb8c093b 3267static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3268{
bb8c093b
CH		 3269 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3270 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3271 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3272 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3273 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 3274 iwl3945_rx_spectrum_measure_notif;
3275 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3276 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 3277 iwl3945_rx_pm_debug_statistics_notif;
3278 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3279
9fbab516
BC		 3280 /*
3281 * The same handler is used for both the REPLY to a discrete
3282 * statistics request from the host as well as for the periodic
3283 * statistics notifications (after received beacons) from the uCode.
b481de9c 3284 */
bb8c093b
CH		 3285 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3286 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3287
bb8c093b
CH		 3288 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3289 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3290 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3291 iwl3945_rx_scan_results_notif;
b481de9c 3292 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 3293 iwl3945_rx_scan_complete_notif;
3294 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 3295
9fbab516 3296 /* Set up hardware specific Rx handlers */
bb8c093b 3297 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY		 3298}
3299
91c066f2
TW		 3300/**
3301 * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3302 * When FW advances 'R' index, all entries between old and new 'R' index
3303 * need to be reclaimed.
3304 */
3305static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
3306 int txq_id, int index)
3307{
3308 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3309 struct iwl3945_queue *q = &txq->q;
3310 int nfreed = 0;
3311
3312 if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
3313 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3314 "is out of range [0-%d] %d %d.\n", txq_id,
3315 index, q->n_bd, q->write_ptr, q->read_ptr);
3316 return;
3317 }
3318
3319 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3320 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3321 if (nfreed > 1) {
3322 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
3323 q->write_ptr, q->read_ptr);
3324 queue_work(priv->workqueue, &priv->restart);
3325 break;
3326 }
3327 nfreed++;
3328 }
3329}
3330
3331
b481de9c 3332/**
bb8c093b 3333 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 3334 * @rxb: Rx buffer to reclaim
3335 *
3336 * If an Rx buffer has an async callback associated with it the callback
3337 * will be executed. The attached skb (if present) will only be freed
3338 * if the callback returns 1
3339 */
bb8c093b
CH		 3340static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3341 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3342{
bb8c093b 3343 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3344 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3345 int txq_id = SEQ_TO_QUEUE(sequence);
3346 int index = SEQ_TO_INDEX(sequence);
3347 int huge = sequence & SEQ_HUGE_FRAME;
3348 int cmd_index;
bb8c093b 3349 struct iwl3945_cmd *cmd;
b481de9c 3350
b481de9c
ZY		 3351 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3352
3353 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3354 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3355
3356 /* Input error checking is done when commands are added to queue. */
3357 if (cmd->meta.flags & CMD_WANT_SKB) {
3358 cmd->meta.source->u.skb = rxb->skb;
3359 rxb->skb = NULL;
3360 } else if (cmd->meta.u.callback &&
3361 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3362 rxb->skb = NULL;
3363
91c066f2 3364 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3365
3366 if (!(cmd->meta.flags & CMD_ASYNC)) {
3367 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3368 wake_up_interruptible(&priv->wait_command_queue);
3369 }
3370}
3371
3372/************************** RX-FUNCTIONS ****************************/
3373/*
3374 * Rx theory of operation
3375 *
3376 * The host allocates 32 DMA target addresses and passes the host address
3377 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3378 * 0 to 31
3379 *
3380 * Rx Queue Indexes
3381 * The host/firmware share two index registers for managing the Rx buffers.
3382 *
3383 * The READ index maps to the first position that the firmware may be writing
3384 * to -- the driver can read up to (but not including) this position and get
3385 * good data.
3386 * The READ index is managed by the firmware once the card is enabled.
3387 *
3388 * The WRITE index maps to the last position the driver has read from -- the
3389 * position preceding WRITE is the last slot the firmware can place a packet.
3390 *
3391 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3392 * WRITE = READ.
3393 *
9fbab516 3394 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 3395 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3396 *
9fbab516 3397 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 3398 * and fire the RX interrupt. The driver can then query the READ index and
3399 * process as many packets as possible, moving the WRITE index forward as it
3400 * resets the Rx queue buffers with new memory.
3401 *
3402 * The management in the driver is as follows:
3403 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3404 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3405 * to replenish the iwl->rxq->rx_free.
bb8c093b 3406 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 3407 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3408 * 'processed' and 'read' driver indexes as well)
3409 * + A received packet is processed and handed to the kernel network stack,
3410 * detached from the iwl->rxq. The driver 'processed' index is updated.
3411 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3412 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3413 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3414 * were enough free buffers and RX_STALLED is set it is cleared.
3415 *
3416 *
3417 * Driver sequence:
3418 *
9fbab516
BC		 3419 * iwl3945_rx_queue_alloc() Allocates rx_free
3420 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3421 * iwl3945_rx_queue_restock
9fbab516 3422 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 3423 * queue, updates firmware pointers, and updates
3424 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3425 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY		 3426 *
3427 * -- enable interrupts --
9fbab516 3428 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY		 3429 * READ INDEX, detaching the SKB from the pool.
3430 * Moves the packet buffer from queue to rx_used.
bb8c093b 3431 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY		 3432 * slots.
3433 * ...
3434 *
3435 */
3436
3437/**
bb8c093b 3438 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3439 */
bb8c093b 3440static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY		 3441{
3442 int s = q->read - q->write;
3443 if (s <= 0)
3444 s += RX_QUEUE_SIZE;
3445 /* keep some buffer to not confuse full and empty queue */
3446 s -= 2;
3447 if (s < 0)
3448 s = 0;
3449 return s;
3450}
3451
3452/**
bb8c093b 3453 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3454 */
bb8c093b 3455int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY		 3456{
3457 u32 reg = 0;
3458 int rc = 0;
3459 unsigned long flags;
3460
3461 spin_lock_irqsave(&q->lock, flags);
3462
3463 if (q->need_update == 0)
3464 goto exit_unlock;
3465
6440adb5 3466 /* If power-saving is in use, make sure device is awake */
b481de9c 3467 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 3468 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3469
3470 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 3471 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3472 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3473 goto exit_unlock;
3474 }
3475
bb8c093b 3476 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3477 if (rc)
3478 goto exit_unlock;
3479
6440adb5 3480 /* Device expects a multiple of 8 */
bb8c093b 3481 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 3482 q->write & ~0x7);
bb8c093b 3483 iwl3945_release_nic_access(priv);
6440adb5
CB		 3484
3485 /* Else device is assumed to be awake */
b481de9c 3486 } else
6440adb5 3487 /* Device expects a multiple of 8 */
bb8c093b 3488 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 3489
3490
3491 q->need_update = 0;
3492
3493 exit_unlock:
3494 spin_unlock_irqrestore(&q->lock, flags);
3495 return rc;
3496}
3497
3498/**
9fbab516 3499 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3500 */
bb8c093b 3501static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY		 3502 dma_addr_t dma_addr)
3503{
3504 return cpu_to_le32((u32)dma_addr);
3505}
3506
3507/**
bb8c093b 3508 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3509 *
9fbab516 3510 * If there are slots in the RX queue that need to be restocked,
b481de9c 3511 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3512 * as we can, pulling from rx_free.
b481de9c
ZY		 3513 *
3514 * This moves the 'write' index forward to catch up with 'processed', and
3515 * also updates the memory address in the firmware to reference the new
3516 * target buffer.
3517 */
bb8c093b 3518static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 3519{
bb8c093b 3520 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3521 struct list_head *element;
bb8c093b 3522 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3523 unsigned long flags;
3524 int write, rc;
3525
3526 spin_lock_irqsave(&rxq->lock, flags);
3527 write = rxq->write & ~0x7;
bb8c093b 3528 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3529 /* Get next free Rx buffer, remove from free list */
b481de9c 3530 element = rxq->rx_free.next;
bb8c093b 3531 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 3532 list_del(element);
6440adb5
CB		 3533
3534 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 3535 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY		 3536 rxq->queue[rxq->write] = rxb;
3537 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3538 rxq->free_count--;
3539 }
3540 spin_unlock_irqrestore(&rxq->lock, flags);
3541 /* If the pre-allocated buffer pool is dropping low, schedule to
3542 * refill it */
3543 if (rxq->free_count <= RX_LOW_WATERMARK)
3544 queue_work(priv->workqueue, &priv->rx_replenish);
3545
3546
6440adb5
CB		 3547 /* If we've added more space for the firmware to place data, tell it.
3548 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 3549 if ((write != (rxq->write & ~0x7))
3550 || (abs(rxq->write - rxq->read) > 7)) {
3551 spin_lock_irqsave(&rxq->lock, flags);
3552 rxq->need_update = 1;
3553 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 3554 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 3555 if (rc)
3556 return rc;
3557 }
3558
3559 return 0;
3560}
3561
3562/**
bb8c093b 3563 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 3564 *
3565 * When moving to rx_free an SKB is allocated for the slot.
3566 *
bb8c093b 3567 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 3568 * This is called as a scheduled work item (except for during initialization)
b481de9c 3569 */
5c0eef96 3570static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
b481de9c 3571{
bb8c093b 3572 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3573 struct list_head *element;
bb8c093b 3574 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3575 unsigned long flags;
3576 spin_lock_irqsave(&rxq->lock, flags);
3577 while (!list_empty(&rxq->rx_used)) {
3578 element = rxq->rx_used.next;
bb8c093b 3579 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
CB		 3580
3581 /* Alloc a new receive buffer */
b481de9c
ZY		 3582 rxb->skb =
3583 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3584 if (!rxb->skb) {
3585 if (net_ratelimit())
3586 printk(KERN_CRIT DRV_NAME
3587 ": Can not allocate SKB buffers\n");
3588 /* We don't reschedule replenish work here -- we will
3589 * call the restock method and if it still needs
3590 * more buffers it will schedule replenish */
3591 break;
3592 }
12342c47
ZY		 3593
3594 /* If radiotap head is required, reserve some headroom here.
3595 * The physical head count is a variable rx_stats->phy_count.
3596 * We reserve 4 bytes here. Plus these extra bytes, the
3597 * headroom of the physical head should be enough for the
3598 * radiotap head that iwl3945 supported. See iwl3945_rt.
3599 */
3600 skb_reserve(rxb->skb, 4);
3601
b481de9c
ZY		 3602 priv->alloc_rxb_skb++;
3603 list_del(element);
6440adb5
CB		 3604
3605 /* Get physical address of RB/SKB */
b481de9c
ZY		 3606 rxb->dma_addr =
3607 pci_map_single(priv->pci_dev, rxb->skb->data,
3608 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3609 list_add_tail(&rxb->list, &rxq->rx_free);
3610 rxq->free_count++;
3611 }
3612 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA		 3613}
3614
3615/*
3616 * this should be called while priv->lock is locked
3617 */
4fd1f841 3618static void __iwl3945_rx_replenish(void *data)
5c0eef96
MA		 3619{
3620 struct iwl3945_priv *priv = data;
3621
3622 iwl3945_rx_allocate(priv);
3623 iwl3945_rx_queue_restock(priv);
3624}
3625
3626
3627void iwl3945_rx_replenish(void *data)
3628{
3629 struct iwl3945_priv *priv = data;
3630 unsigned long flags;
3631
3632 iwl3945_rx_allocate(priv);
b481de9c
ZY		 3633
3634 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3635 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3636 spin_unlock_irqrestore(&priv->lock, flags);
3637}
3638
3639/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 3640 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY		 3641 * This free routine walks the list of POOL entries and if SKB is set to
3642 * non NULL it is unmapped and freed
3643 */
bb8c093b 3644static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3645{
3646 int i;
3647 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3648 if (rxq->pool[i].skb != NULL) {
3649 pci_unmap_single(priv->pci_dev,
3650 rxq->pool[i].dma_addr,
3651 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3652 dev_kfree_skb(rxq->pool[i].skb);
3653 }
3654 }
3655
3656 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3657 rxq->dma_addr);
3658 rxq->bd = NULL;
3659}
3660
bb8c093b 3661int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 3662{
bb8c093b 3663 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3664 struct pci_dev *dev = priv->pci_dev;
3665 int i;
3666
3667 spin_lock_init(&rxq->lock);
3668 INIT_LIST_HEAD(&rxq->rx_free);
3669 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB		 3670
3671 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY		 3672 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3673 if (!rxq->bd)
3674 return -ENOMEM;
6440adb5 3675
b481de9c
ZY		 3676 /* Fill the rx_used queue with _all_ of the Rx buffers */
3677 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3678 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 3679
b481de9c
ZY		 3680 /* Set us so that we have processed and used all buffers, but have
3681 * not restocked the Rx queue with fresh buffers */
3682 rxq->read = rxq->write = 0;
3683 rxq->free_count = 0;
3684 rxq->need_update = 0;
3685 return 0;
3686}
3687
bb8c093b 3688void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3689{
3690 unsigned long flags;
3691 int i;
3692 spin_lock_irqsave(&rxq->lock, flags);
3693 INIT_LIST_HEAD(&rxq->rx_free);
3694 INIT_LIST_HEAD(&rxq->rx_used);
3695 /* Fill the rx_used queue with _all_ of the Rx buffers */
3696 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3697 /* In the reset function, these buffers may have been allocated
3698 * to an SKB, so we need to unmap and free potential storage */
3699 if (rxq->pool[i].skb != NULL) {
3700 pci_unmap_single(priv->pci_dev,
3701 rxq->pool[i].dma_addr,
3702 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3703 priv->alloc_rxb_skb--;
3704 dev_kfree_skb(rxq->pool[i].skb);
3705 rxq->pool[i].skb = NULL;
3706 }
3707 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3708 }
3709
3710 /* Set us so that we have processed and used all buffers, but have
3711 * not restocked the Rx queue with fresh buffers */
3712 rxq->read = rxq->write = 0;
3713 rxq->free_count = 0;
3714 spin_unlock_irqrestore(&rxq->lock, flags);
3715}
3716
3717/* Convert linear signal-to-noise ratio into dB */
3718static u8 ratio2dB[100] = {
3719/* 0 1 2 3 4 5 6 7 8 9 */
3720 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3721 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3722 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3723 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3724 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3725 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3726 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3727 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3728 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3729 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3730};
3731
3732/* Calculates a relative dB value from a ratio of linear
3733 * (i.e. not dB) signal levels.
3734 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 3735int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 3736{
221c80cf
AB		 3737 /* 1000:1 or higher just report as 60 dB */
3738 if (sig_ratio >= 1000)
b481de9c
ZY		 3739 return 60;
3740
221c80cf 3741 /* 100:1 or higher, divide by 10 and use table,
b481de9c 3742 * add 20 dB to make up for divide by 10 */
221c80cf 3743 if (sig_ratio >= 100)
3ac7f146 3744 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY		 3745
3746 /* We shouldn't see this */
3747 if (sig_ratio < 1)
3748 return 0;
3749
3750 /* Use table for ratios 1:1 - 99:1 */
3751 return (int)ratio2dB[sig_ratio];
3752}
3753
3754#define PERFECT_RSSI (-20) /* dBm */
3755#define WORST_RSSI (-95) /* dBm */
3756#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3757
3758/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3759 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3760 * about formulas used below. */
bb8c093b 3761int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 3762{
3763 int sig_qual;
3764 int degradation = PERFECT_RSSI - rssi_dbm;
3765
3766 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3767 * as indicator; formula is (signal dbm - noise dbm).
3768 * SNR at or above 40 is a great signal (100%).
3769 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3770 * Weakest usable signal is usually 10 - 15 dB SNR. */
3771 if (noise_dbm) {
3772 if (rssi_dbm - noise_dbm >= 40)
3773 return 100;
3774 else if (rssi_dbm < noise_dbm)
3775 return 0;
3776 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3777
3778 /* Else use just the signal level.
3779 * This formula is a least squares fit of data points collected and
3780 * compared with a reference system that had a percentage (%) display
3781 * for signal quality. */
3782 } else
3783 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3784 (15 * RSSI_RANGE + 62 * degradation)) /
3785 (RSSI_RANGE * RSSI_RANGE);
3786
3787 if (sig_qual > 100)
3788 sig_qual = 100;
3789 else if (sig_qual < 1)
3790 sig_qual = 0;
3791
3792 return sig_qual;
3793}
3794
3795/**
9fbab516 3796 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 3797 *
3798 * Uses the priv->rx_handlers callback function array to invoke
3799 * the appropriate handlers, including command responses,
3800 * frame-received notifications, and other notifications.
3801 */
bb8c093b 3802static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 3803{
bb8c093b
CH		 3804 struct iwl3945_rx_mem_buffer *rxb;
3805 struct iwl3945_rx_packet *pkt;
3806 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3807 u32 r, i;
3808 int reclaim;
3809 unsigned long flags;
5c0eef96 3810 u8 fill_rx = 0;
d68ab680 3811 u32 count = 8;
b481de9c 3812
6440adb5
CB		 3813 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3814 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 3815 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY		 3816 i = rxq->read;
3817
5c0eef96
MA		 3818 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3819 fill_rx = 1;
b481de9c
ZY		 3820 /* Rx interrupt, but nothing sent from uCode */
3821 if (i == r)
3822 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3823
3824 while (i != r) {
3825 rxb = rxq->queue[i];
3826
9fbab516 3827 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 3828 * then a bug has been introduced in the queue refilling
3829 * routines -- catch it here */
3830 BUG_ON(rxb == NULL);
3831
3832 rxq->queue[i] = NULL;
3833
3834 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
3835 IWL_RX_BUF_SIZE,
3836 PCI_DMA_FROMDEVICE);
bb8c093b 3837 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3838
3839 /* Reclaim a command buffer only if this packet is a response
3840 * to a (driver-originated) command.
3841 * If the packet (e.g. Rx frame) originated from uCode,
3842 * there is no command buffer to reclaim.
3843 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
3844 * but apparently a few don't get set; catch them here. */
3845 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
3846 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
3847 (pkt->hdr.cmd != REPLY_TX);
3848
3849 /* Based on type of command response or notification,
3850 * handle those that need handling via function in
bb8c093b 3851 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY		 3852 if (priv->rx_handlers[pkt->hdr.cmd]) {
3853 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3854 "r = %d, i = %d, %s, 0x%02x\n", r, i,
3855 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3856 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
3857 } else {
3858 /* No handling needed */
3859 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3860 "r %d i %d No handler needed for %s, 0x%02x\n",
3861 r, i, get_cmd_string(pkt->hdr.cmd),
3862 pkt->hdr.cmd);
3863 }
3864
3865 if (reclaim) {
9fbab516
BC		 3866 /* Invoke any callbacks, transfer the skb to caller, and
3867 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY		 3868 * as we reclaim the driver command queue */
3869 if (rxb && rxb->skb)
bb8c093b 3870 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY		 3871 else
3872 IWL_WARNING("Claim null rxb?\n");
3873 }
3874
3875 /* For now we just don't re-use anything. We can tweak this
3876 * later to try and re-use notification packets and SKBs that
3877 * fail to Rx correctly */
3878 if (rxb->skb != NULL) {
3879 priv->alloc_rxb_skb--;
3880 dev_kfree_skb_any(rxb->skb);
3881 rxb->skb = NULL;
3882 }
3883
3884 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
3885 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3886 spin_lock_irqsave(&rxq->lock, flags);
3887 list_add_tail(&rxb->list, &priv->rxq.rx_used);
3888 spin_unlock_irqrestore(&rxq->lock, flags);
3889 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 3890 /* If there are a lot of unused frames,
3891 * restock the Rx queue so ucode won't assert. */
3892 if (fill_rx) {
3893 count++;
3894 if (count >= 8) {
3895 priv->rxq.read = i;
3896 __iwl3945_rx_replenish(priv);
3897 count = 0;
3898 }
3899 }
b481de9c
ZY		 3900 }
3901
3902 /* Backtrack one entry */
3903 priv->rxq.read = i;
bb8c093b 3904 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3905}
3906
6440adb5
CB		 3907/**
3908 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
3909 */
bb8c093b
CH		 3910static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
3911 struct iwl3945_tx_queue *txq)
b481de9c
ZY		 3912{
3913 u32 reg = 0;
3914 int rc = 0;
3915 int txq_id = txq->q.id;
3916
3917 if (txq->need_update == 0)
3918 return rc;
3919
3920 /* if we're trying to save power */
3921 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3922 /* wake up nic if it's powered down ...
3923 * uCode will wake up, and interrupt us again, so next
3924 * time we'll skip this part. */
bb8c093b 3925 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3926
3927 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3928 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 3929 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3930 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3931 return rc;
3932 }
3933
3934 /* restore this queue's parameters in nic hardware. */
bb8c093b 3935 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3936 if (rc)
3937 return rc;
bb8c093b 3938 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 3939 txq->q.write_ptr | (txq_id << 8));
bb8c093b 3940 iwl3945_release_nic_access(priv);
b481de9c
ZY		 3941
3942 /* else not in power-save mode, uCode will never sleep when we're
3943 * trying to tx (during RFKILL, we're not trying to tx). */
3944 } else
bb8c093b 3945 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 3946 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 3947
3948 txq->need_update = 0;
3949
3950 return rc;
3951}
3952
c8b0e6e1 3953#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 3954static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 3955{
3956 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 3957 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 3958 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
3959 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
3960 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
3961 le32_to_cpu(rxon->filter_flags));
3962 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
3963 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
3964 rxon->ofdm_basic_rates);
3965 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
e174961c
JB		 3966 IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
3967 IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
b481de9c
ZY		 3968 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
3969}
3970#endif
3971
bb8c093b 3972static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 3973{
3974 IWL_DEBUG_ISR("Enabling interrupts\n");
3975 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 3976 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 3977}
3978
0359facc
MA		 3979
3980/* call this function to flush any scheduled tasklet */
3981static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
3982{
a96a27f9 3983 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 3984 synchronize_irq(priv->pci_dev->irq);
3985 tasklet_kill(&priv->irq_tasklet);
3986}
3987
3988
bb8c093b 3989static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 3990{
3991 clear_bit(STATUS_INT_ENABLED, &priv->status);
3992
3993 /* disable interrupts from uCode/NIC to host */
bb8c093b 3994 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 3995
3996 /* acknowledge/clear/reset any interrupts still pending
3997 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH		 3998 iwl3945_write32(priv, CSR_INT, 0xffffffff);
3999 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 4000 IWL_DEBUG_ISR("Disabled interrupts\n");
4001}
4002
4003static const char *desc_lookup(int i)
4004{
4005 switch (i) {
4006 case 1:
4007 return "FAIL";
4008 case 2:
4009 return "BAD_PARAM";
4010 case 3:
4011 return "BAD_CHECKSUM";
4012 case 4:
4013 return "NMI_INTERRUPT";
4014 case 5:
4015 return "SYSASSERT";
4016 case 6:
4017 return "FATAL_ERROR";
4018 }
4019
4020 return "UNKNOWN";
4021}
4022
4023#define ERROR_START_OFFSET (1 * sizeof(u32))
4024#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4025
bb8c093b 4026static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4027{
4028 u32 i;
4029 u32 desc, time, count, base, data1;
4030 u32 blink1, blink2, ilink1, ilink2;
4031 int rc;
4032
4033 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4034
bb8c093b 4035 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4036 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4037 return;
4038 }
4039
bb8c093b 4040 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4041 if (rc) {
4042 IWL_WARNING("Can not read from adapter at this time.\n");
4043 return;
4044 }
4045
bb8c093b 4046 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY		 4047
4048 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4049 IWL_ERROR("Start IWL Error Log Dump:\n");
2acae16e 4050 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
b481de9c
ZY		 4051 }
4052
4053 IWL_ERROR("Desc Time asrtPC blink2 "
4054 "ilink1 nmiPC Line\n");
4055 for (i = ERROR_START_OFFSET;
4056 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4057 i += ERROR_ELEM_SIZE) {
bb8c093b 4058 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4059 time =
bb8c093b 4060 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4061 blink1 =
bb8c093b 4062 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4063 blink2 =
bb8c093b 4064 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4065 ilink1 =
bb8c093b 4066 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4067 ilink2 =
bb8c093b 4068 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4069 data1 =
bb8c093b 4070 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY		 4071
4072 IWL_ERROR
4073 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4074 desc_lookup(desc), desc, time, blink1, blink2,
4075 ilink1, ilink2, data1);
4076 }
4077
bb8c093b 4078 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4079
4080}
4081
f58177b9 4082#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY		 4083
4084/**
bb8c093b 4085 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4086 *
bb8c093b 4087 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4088 */
bb8c093b 4089static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY		 4090 u32 num_events, u32 mode)
4091{
4092 u32 i;
4093 u32 base; /* SRAM byte address of event log header */
4094 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4095 u32 ptr; /* SRAM byte address of log data */
4096 u32 ev, time, data; /* event log data */
4097
4098 if (num_events == 0)
4099 return;
4100
4101 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4102
4103 if (mode == 0)
4104 event_size = 2 * sizeof(u32);
4105 else
4106 event_size = 3 * sizeof(u32);
4107
4108 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4109
4110 /* "time" is actually "data" for mode 0 (no timestamp).
4111 * place event id # at far right for easier visual parsing. */
4112 for (i = 0; i < num_events; i++) {
bb8c093b 4113 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4114 ptr += sizeof(u32);
bb8c093b 4115 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4116 ptr += sizeof(u32);
4117 if (mode == 0)
4118 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4119 else {
bb8c093b 4120 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4121 ptr += sizeof(u32);
4122 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4123 }
4124 }
4125}
4126
bb8c093b 4127static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4128{
4129 int rc;
4130 u32 base; /* SRAM byte address of event log header */
4131 u32 capacity; /* event log capacity in # entries */
4132 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4133 u32 num_wraps; /* # times uCode wrapped to top of log */
4134 u32 next_entry; /* index of next entry to be written by uCode */
4135 u32 size; /* # entries that we'll print */
4136
4137 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4138 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4139 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4140 return;
4141 }
4142
bb8c093b 4143 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4144 if (rc) {
4145 IWL_WARNING("Can not read from adapter at this time.\n");
4146 return;
4147 }
4148
4149 /* event log header */
bb8c093b
CH		 4150 capacity = iwl3945_read_targ_mem(priv, base);
4151 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4152 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4153 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 4154
4155 size = num_wraps ? capacity : next_entry;
4156
4157 /* bail out if nothing in log */
4158 if (size == 0) {
583fab37 4159 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4160 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4161 return;
4162 }
4163
583fab37 4164 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 4165 size, num_wraps);
4166
4167 /* if uCode has wrapped back to top of log, start at the oldest entry,
4168 * i.e the next one that uCode would fill. */
4169 if (num_wraps)
bb8c093b 4170 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY		 4171 capacity - next_entry, mode);
4172
4173 /* (then/else) start at top of log */
bb8c093b 4174 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4175
bb8c093b 4176 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4177}
4178
4179/**
bb8c093b 4180 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4181 */
bb8c093b 4182static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4183{
bb8c093b 4184 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY		 4185 set_bit(STATUS_FW_ERROR, &priv->status);
4186
4187 /* Cancel currently queued command. */
4188 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4189
c8b0e6e1 4190#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4191 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4192 iwl3945_dump_nic_error_log(priv);
4193 iwl3945_dump_nic_event_log(priv);
4194 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY		 4195 }
4196#endif
4197
4198 wake_up_interruptible(&priv->wait_command_queue);
4199
4200 /* Keep the restart process from trying to send host
4201 * commands by clearing the INIT status bit */
4202 clear_bit(STATUS_READY, &priv->status);
4203
4204 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4205 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4206 "Restarting adapter due to uCode error.\n");
4207
bb8c093b 4208 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4209 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4210 sizeof(priv->recovery_rxon));
4211 priv->error_recovering = 1;
4212 }
4213 queue_work(priv->workqueue, &priv->restart);
4214 }
4215}
4216
bb8c093b 4217static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY		 4218{
4219 unsigned long flags;
4220
4221 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4222 sizeof(priv->staging_rxon));
4223 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4224 iwl3945_commit_rxon(priv);
b481de9c 4225
bb8c093b 4226 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY		 4227
4228 spin_lock_irqsave(&priv->lock, flags);
4229 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4230 priv->error_recovering = 0;
4231 spin_unlock_irqrestore(&priv->lock, flags);
4232}
4233
bb8c093b 4234static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY		 4235{
4236 u32 inta, handled = 0;
4237 u32 inta_fh;
4238 unsigned long flags;
c8b0e6e1 4239#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 4240 u32 inta_mask;
4241#endif
4242
4243 spin_lock_irqsave(&priv->lock, flags);
4244
4245 /* Ack/clear/reset pending uCode interrupts.
4246 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4247 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH		 4248 inta = iwl3945_read32(priv, CSR_INT);
4249 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY		 4250
4251 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4252 * Any new interrupts that happen after this, either while we're
4253 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH		 4254 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4255 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4256
c8b0e6e1 4257#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4258 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC		 4259 /* just for debug */
4260 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 4261 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4262 inta, inta_mask, inta_fh);
4263 }
4264#endif
4265
4266 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4267 * atomic, make sure that inta covers all the interrupts that
4268 * we've discovered, even if FH interrupt came in just after
4269 * reading CSR_INT. */
6f83eaa1 4270 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 4271 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 4272 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY		 4273 inta |= CSR_INT_BIT_FH_TX;
4274
4275 /* Now service all interrupt bits discovered above. */
4276 if (inta & CSR_INT_BIT_HW_ERR) {
4277 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4278
4279 /* Tell the device to stop sending interrupts */
bb8c093b 4280 iwl3945_disable_interrupts(priv);
b481de9c 4281
bb8c093b 4282 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4283
4284 handled |= CSR_INT_BIT_HW_ERR;
4285
4286 spin_unlock_irqrestore(&priv->lock, flags);
4287
4288 return;
4289 }
4290
c8b0e6e1 4291#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4292 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c 4293 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP		 4294 if (inta & CSR_INT_BIT_SCD)
4295 IWL_DEBUG_ISR("Scheduler finished to transmit "
4296 "the frame/frames.\n");
b481de9c
ZY		 4297
4298 /* Alive notification via Rx interrupt will do the real work */
4299 if (inta & CSR_INT_BIT_ALIVE)
4300 IWL_DEBUG_ISR("Alive interrupt\n");
4301 }
4302#endif
4303 /* Safely ignore these bits for debug checks below */
25c03d8e 4304 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 4305
b481de9c
ZY		 4306 /* Error detected by uCode */
4307 if (inta & CSR_INT_BIT_SW_ERR) {
4308 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4309 inta);
bb8c093b 4310 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4311 handled |= CSR_INT_BIT_SW_ERR;
4312 }
4313
4314 /* uCode wakes up after power-down sleep */
4315 if (inta & CSR_INT_BIT_WAKEUP) {
4316 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH		 4317 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4318 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4319 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4320 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4321 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4322 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4323 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 4324
4325 handled |= CSR_INT_BIT_WAKEUP;
4326 }
4327
4328 /* All uCode command responses, including Tx command responses,
4329 * Rx "responses" (frame-received notification), and other
4330 * notifications from uCode come through here*/
4331 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4332 iwl3945_rx_handle(priv);
b481de9c
ZY		 4333 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4334 }
4335
4336 if (inta & CSR_INT_BIT_FH_TX) {
4337 IWL_DEBUG_ISR("Tx interrupt\n");
4338
bb8c093b
CH		 4339 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4340 if (!iwl3945_grab_nic_access(priv)) {
4341 iwl3945_write_direct32(priv,
b481de9c
ZY		 4342 FH_TCSR_CREDIT
4343 (ALM_FH_SRVC_CHNL), 0x0);
bb8c093b 4344 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4345 }
4346 handled |= CSR_INT_BIT_FH_TX;
4347 }
4348
4349 if (inta & ~handled)
4350 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4351
4352 if (inta & ~CSR_INI_SET_MASK) {
4353 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4354 inta & ~CSR_INI_SET_MASK);
4355 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4356 }
4357
4358 /* Re-enable all interrupts */
0359facc
MA		 4359 /* only Re-enable if disabled by irq */
4360 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4361 iwl3945_enable_interrupts(priv);
b481de9c 4362
c8b0e6e1 4363#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4364 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4365 inta = iwl3945_read32(priv, CSR_INT);
4366 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4367 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4368 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4369 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4370 }
4371#endif
4372 spin_unlock_irqrestore(&priv->lock, flags);
4373}
4374
bb8c093b 4375static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4376{
bb8c093b 4377 struct iwl3945_priv *priv = data;
b481de9c
ZY		 4378 u32 inta, inta_mask;
4379 u32 inta_fh;
4380 if (!priv)
4381 return IRQ_NONE;
4382
4383 spin_lock(&priv->lock);
4384
4385 /* Disable (but don't clear!) interrupts here to avoid
4386 * back-to-back ISRs and sporadic interrupts from our NIC.
4387 * If we have something to service, the tasklet will re-enable ints.
4388 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH		 4389 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4390 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4391
4392 /* Discover which interrupts are active/pending */
bb8c093b
CH		 4393 inta = iwl3945_read32(priv, CSR_INT);
4394 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4395
4396 /* Ignore interrupt if there's nothing in NIC to service.
4397 * This may be due to IRQ shared with another device,
4398 * or due to sporadic interrupts thrown from our NIC. */
4399 if (!inta && !inta_fh) {
4400 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4401 goto none;
4402 }
4403
4404 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4405 /* Hardware disappeared */
99df630c 4406 IWL_WARNING("HARDWARE GONE?? INTA == 0x%08x\n", inta);
cb4da1a3 4407 goto unplugged;
b481de9c
ZY		 4408 }
4409
4410 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4411 inta, inta_mask, inta_fh);
4412
25c03d8e
JP		 4413 inta &= ~CSR_INT_BIT_SCD;
4414
bb8c093b 4415 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP		 4416 if (likely(inta || inta_fh))
4417 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4418unplugged:
b481de9c
ZY		 4419 spin_unlock(&priv->lock);
4420
4421 return IRQ_HANDLED;
4422
4423 none:
4424 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA		 4425 /* only Re-enable if disabled by irq */
4426 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4427 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 4428 spin_unlock(&priv->lock);
4429 return IRQ_NONE;
4430}
4431
4432/************************** EEPROM BANDS ****************************
4433 *
bb8c093b 4434 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY		 4435 * EEPROM contents to the specific channel number supported for each
4436 * band.
4437 *
bb8c093b 4438 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY		 4439 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4440 * The specific geography and calibration information for that channel
4441 * is contained in the eeprom map itself.
4442 *
4443 * During init, we copy the eeprom information and channel map
4444 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4445 *
4446 * channel_map_24/52 provides the index in the channel_info array for a
4447 * given channel. We have to have two separate maps as there is channel
4448 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4449 * band_2
4450 *
4451 * A value of 0xff stored in the channel_map indicates that the channel
4452 * is not supported by the hardware at all.
4453 *
4454 * A value of 0xfe in the channel_map indicates that the channel is not
4455 * valid for Tx with the current hardware. This means that
4456 * while the system can tune and receive on a given channel, it may not
4457 * be able to associate or transmit any frames on that
4458 * channel. There is no corresponding channel information for that
4459 * entry.
4460 *
4461 *********************************************************************/
4462
4463/* 2.4 GHz */
bb8c093b 4464static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY		 4465 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4466};
4467
4468/* 5.2 GHz bands */
9fbab516 4469static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY		 4470 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4471};
4472
9fbab516 4473static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY		 4474 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4475};
4476
bb8c093b 4477static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY		 4478 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4479};
4480
bb8c093b 4481static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY		 4482 145, 149, 153, 157, 161, 165
4483};
4484
bb8c093b 4485static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 4486 int *eeprom_ch_count,
bb8c093b 4487 const struct iwl3945_eeprom_channel
b481de9c
ZY		 4488 **eeprom_ch_info,
4489 const u8 **eeprom_ch_index)
4490{
4491 switch (band) {
4492 case 1: /* 2.4GHz band */
bb8c093b 4493 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 4494 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 4495 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4496 break;
9fbab516 4497 case 2: /* 4.9GHz band */
bb8c093b 4498 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 4499 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 4500 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY		 4501 break;
4502 case 3: /* 5.2GHz band */
bb8c093b 4503 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 4504 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 4505 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4506 break;
9fbab516 4507 case 4: /* 5.5GHz band */
bb8c093b 4508 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 4509 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 4510 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4511 break;
9fbab516 4512 case 5: /* 5.7GHz band */
bb8c093b 4513 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 4514 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 4515 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY		 4516 break;
4517 default:
4518 BUG();
4519 return;
4520 }
4521}
4522
6440adb5
CB		 4523/**
4524 * iwl3945_get_channel_info - Find driver's private channel info
4525 *
4526 * Based on band and channel number.
4527 */
bb8c093b 4528const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
8318d78a 4529 enum ieee80211_band band, u16 channel)
b481de9c
ZY		 4530{
4531 int i;
4532
8318d78a
JB		 4533 switch (band) {
4534 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 4535 for (i = 14; i < priv->channel_count; i++) {
4536 if (priv->channel_info[i].channel == channel)
4537 return &priv->channel_info[i];
4538 }
4539 break;
4540
8318d78a 4541 case IEEE80211_BAND_2GHZ:
b481de9c
ZY		 4542 if (channel >= 1 && channel <= 14)
4543 return &priv->channel_info[channel - 1];
4544 break;
8318d78a
JB		 4545 case IEEE80211_NUM_BANDS:
4546 WARN_ON(1);
b481de9c
ZY		 4547 }
4548
4549 return NULL;
4550}
4551
4552#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4553 ? # x " " : "")
4554
6440adb5
CB		 4555/**
4556 * iwl3945_init_channel_map - Set up driver's info for all possible channels
4557 */
bb8c093b 4558static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY		 4559{
4560 int eeprom_ch_count = 0;
4561 const u8 *eeprom_ch_index = NULL;
bb8c093b 4562 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 4563 int band, ch;
bb8c093b 4564 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4565
4566 if (priv->channel_count) {
4567 IWL_DEBUG_INFO("Channel map already initialized.\n");
4568 return 0;
4569 }
4570
4571 if (priv->eeprom.version < 0x2f) {
4572 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
4573 priv->eeprom.version);
4574 return -EINVAL;
4575 }
4576
4577 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4578
4579 priv->channel_count =
bb8c093b
CH		 4580 ARRAY_SIZE(iwl3945_eeprom_band_1) +
4581 ARRAY_SIZE(iwl3945_eeprom_band_2) +
4582 ARRAY_SIZE(iwl3945_eeprom_band_3) +
4583 ARRAY_SIZE(iwl3945_eeprom_band_4) +
4584 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY		 4585
4586 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4587
bb8c093b 4588 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY		 4589 priv->channel_count, GFP_KERNEL);
4590 if (!priv->channel_info) {
4591 IWL_ERROR("Could not allocate channel_info\n");
4592 priv->channel_count = 0;
4593 return -ENOMEM;
4594 }
4595
4596 ch_info = priv->channel_info;
4597
4598 /* Loop through the 5 EEPROM bands adding them in order to the
4599 * channel map we maintain (that contains additional information than
4600 * what just in the EEPROM) */
4601 for (band = 1; band <= 5; band++) {
4602
bb8c093b 4603 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 4604 &eeprom_ch_info, &eeprom_ch_index);
4605
4606 /* Loop through each band adding each of the channels */
4607 for (ch = 0; ch < eeprom_ch_count; ch++) {
4608 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB		 4609 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4610 IEEE80211_BAND_5GHZ;
b481de9c
ZY		 4611
4612 /* permanently store EEPROM's channel regulatory flags
4613 * and max power in channel info database. */
4614 ch_info->eeprom = eeprom_ch_info[ch];
4615
4616 /* Copy the run-time flags so they are there even on
4617 * invalid channels */
4618 ch_info->flags = eeprom_ch_info[ch].flags;
4619
4620 if (!(is_channel_valid(ch_info))) {
4621 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4622 "No traffic\n",
4623 ch_info->channel,
4624 ch_info->flags,
4625 is_channel_a_band(ch_info) ?
4626 "5.2" : "2.4");
4627 ch_info++;
4628 continue;
4629 }
4630
4631 /* Initialize regulatory-based run-time data */
4632 ch_info->max_power_avg = ch_info->curr_txpow =
4633 eeprom_ch_info[ch].max_power_avg;
4634 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4635 ch_info->min_power = 0;
4636
fe7c4040 4637 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
b481de9c
ZY		 4638 " %ddBm): Ad-Hoc %ssupported\n",
4639 ch_info->channel,
4640 is_channel_a_band(ch_info) ?
4641 "5.2" : "2.4",
8211ef78 4642 CHECK_AND_PRINT(VALID),
b481de9c
ZY		 4643 CHECK_AND_PRINT(IBSS),
4644 CHECK_AND_PRINT(ACTIVE),
4645 CHECK_AND_PRINT(RADAR),
4646 CHECK_AND_PRINT(WIDE),
b481de9c
ZY		 4647 CHECK_AND_PRINT(DFS),
4648 eeprom_ch_info[ch].flags,
4649 eeprom_ch_info[ch].max_power_avg,
4650 ((eeprom_ch_info[ch].
4651 flags & EEPROM_CHANNEL_IBSS)
4652 && !(eeprom_ch_info[ch].
4653 flags & EEPROM_CHANNEL_RADAR))
4654 ? "" : "not ");
4655
4656 /* Set the user_txpower_limit to the highest power
4657 * supported by any channel */
4658 if (eeprom_ch_info[ch].max_power_avg >
4659 priv->user_txpower_limit)
4660 priv->user_txpower_limit =
4661 eeprom_ch_info[ch].max_power_avg;
4662
4663 ch_info++;
4664 }
4665 }
4666
6440adb5 4667 /* Set up txpower settings in driver for all channels */
b481de9c
ZY		 4668 if (iwl3945_txpower_set_from_eeprom(priv))
4669 return -EIO;
4670
4671 return 0;
4672}
4673
849e0dce
RC		 4674/*
4675 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4676 */
4677static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
4678{
4679 kfree(priv->channel_info);
4680 priv->channel_count = 0;
4681}
4682
b481de9c
ZY		 4683/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4684 * sending probe req. This should be set long enough to hear probe responses
4685 * from more than one AP. */
f9340520
AK		 4686#define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
4687#define IWL_ACTIVE_DWELL_TIME_52 (20)
4688
4689#define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
4690#define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
b481de9c
ZY		 4691
4692/* For faster active scanning, scan will move to the next channel if fewer than
4693 * PLCP_QUIET_THRESH packets are heard on this channel within
4694 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4695 * time if it's a quiet channel (nothing responded to our probe, and there's
4696 * no other traffic).
4697 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4698#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
f9340520 4699#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
b481de9c
ZY		 4700
4701/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4702 * Must be set longer than active dwell time.
4703 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4704#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4705#define IWL_PASSIVE_DWELL_TIME_52 (10)
4706#define IWL_PASSIVE_DWELL_BASE (100)
4707#define IWL_CHANNEL_TUNE_TIME 5
4708
e720ce9d 4709#define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
f9340520 4710
8318d78a 4711static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
f9340520
AK		 4712 enum ieee80211_band band,
4713 u8 n_probes)
b481de9c 4714{
8318d78a 4715 if (band == IEEE80211_BAND_5GHZ)
f9340520
AK		 4716 return IWL_ACTIVE_DWELL_TIME_52 +
4717 IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
b481de9c 4718 else
f9340520
AK		 4719 return IWL_ACTIVE_DWELL_TIME_24 +
4720 IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
b481de9c
ZY		 4721}
4722
8318d78a
JB		 4723static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
4724 enum ieee80211_band band)
b481de9c 4725{
8318d78a 4726 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY		 4727 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4728 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4729
bb8c093b 4730 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4731 /* If we're associated, we clamp the maximum passive
4732 * dwell time to be 98% of the beacon interval (minus
4733 * 2 * channel tune time) */
4734 passive = priv->beacon_int;
4735 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4736 passive = IWL_PASSIVE_DWELL_BASE;
4737 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4738 }
4739
b481de9c
ZY		 4740 return passive;
4741}
4742
8318d78a
JB		 4743static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
4744 enum ieee80211_band band,
f9340520 4745 u8 is_active, u8 n_probes,
bb8c093b 4746 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY		 4747{
4748 const struct ieee80211_channel *channels = NULL;
8318d78a 4749 const struct ieee80211_supported_band *sband;
bb8c093b 4750 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4751 u16 passive_dwell = 0;
4752 u16 active_dwell = 0;
4753 int added, i;
4754
8318d78a
JB		 4755 sband = iwl3945_get_band(priv, band);
4756 if (!sband)
b481de9c
ZY		 4757 return 0;
4758
8318d78a 4759 channels = sband->channels;
b481de9c 4760
f9340520 4761 active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
8318d78a 4762 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 4763
8f4807a1
AK		 4764 if (passive_dwell <= active_dwell)
4765 passive_dwell = active_dwell + 1;
4766
8318d78a 4767 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB		 4768 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4769 continue;
4770
8318d78a 4771 scan_ch->channel = channels[i].hw_value;
b481de9c 4772
8318d78a 4773 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c 4774 if (!is_channel_valid(ch_info)) {
66b5004d 4775 IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
b481de9c
ZY		 4776 scan_ch->channel);
4777 continue;
4778 }
4779
011a0330
AK		 4780 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4781 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4782 /* If passive , set up for auto-switch
4783 * and use long active_dwell time.
4784 */
b481de9c 4785 if (!is_active || is_channel_passive(ch_info) ||
011a0330 4786 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 4787 scan_ch->type = 0; /* passive */
011a0330
AK		 4788 if (IWL_UCODE_API(priv->ucode_ver) == 1)
4789 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
4790 } else {
b481de9c 4791 scan_ch->type = 1; /* active */
011a0330 4792 }
b481de9c 4793
011a0330
AK		 4794 /* Set direct probe bits. These may be used both for active
4795 * scan channels (probes gets sent right away),
4796 * or for passive channels (probes get se sent only after
4797 * hearing clear Rx packet).*/
4798 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
4799 if (n_probes)
4800 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
4801 } else {
4802 /* uCode v1 does not allow setting direct probe bits on
4803 * passive channel. */
4804 if ((scan_ch->type & 1) && n_probes)
4805 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
4806 }
b481de9c 4807
9fbab516 4808 /* Set txpower levels to defaults */
b481de9c
ZY		 4809 scan_ch->tpc.dsp_atten = 110;
4810 /* scan_pwr_info->tpc.dsp_atten; */
4811
4812 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 4813 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4814 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4815 else {
4816 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4817 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 4818 * power level:
8a1b0245 4819 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY		 4820 */
4821 }
4822
4823 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
4824 scan_ch->channel,
4825 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
4826 (scan_ch->type & 1) ?
4827 active_dwell : passive_dwell);
4828
4829 scan_ch++;
4830 added++;
4831 }
4832
4833 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
4834 return added;
4835}
4836
bb8c093b 4837static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY		 4838 struct ieee80211_rate *rates)
4839{
4840 int i;
4841
4842 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB		 4843 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
4844 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4845 rates[i].hw_value_short = i;
4846 rates[i].flags = 0;
4847 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 4848 /*
8318d78a 4849 * If CCK != 1M then set short preamble rate flag.
b481de9c 4850 */
bb8c093b 4851 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 4852 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 4853 }
b481de9c
ZY		 4854 }
4855}
4856
4857/**
bb8c093b 4858 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 4859 */
bb8c093b 4860static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 4861{
bb8c093b 4862 struct iwl3945_channel_info *ch;
8211ef78 4863 struct ieee80211_supported_band *sband;
b481de9c
ZY		 4864 struct ieee80211_channel *channels;
4865 struct ieee80211_channel *geo_ch;
4866 struct ieee80211_rate *rates;
4867 int i = 0;
b481de9c 4868
8318d78a
JB		 4869 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
4870 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY		 4871 IWL_DEBUG_INFO("Geography modes already initialized.\n");
4872 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4873 return 0;
4874 }
4875
b481de9c
ZY		 4876 channels = kzalloc(sizeof(struct ieee80211_channel) *
4877 priv->channel_count, GFP_KERNEL);
8318d78a 4878 if (!channels)
b481de9c 4879 return -ENOMEM;
b481de9c 4880
8211ef78 4881 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY		 4882 GFP_KERNEL);
4883 if (!rates) {
b481de9c
ZY		 4884 kfree(channels);
4885 return -ENOMEM;
4886 }
4887
b481de9c 4888 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW		 4889 sband = &priv->bands[IEEE80211_BAND_5GHZ];
4890 sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
4891 /* just OFDM */
4892 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
4893 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
4894
4895 sband = &priv->bands[IEEE80211_BAND_2GHZ];
4896 sband->channels = channels;
4897 /* OFDM & CCK */
4898 sband->bitrates = rates;
4899 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c
ZY		 4900
4901 priv->ieee_channels = channels;
4902 priv->ieee_rates = rates;
4903
bb8c093b 4904 iwl3945_init_hw_rates(priv, rates);
b481de9c 4905
8211ef78 4906 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY		 4907 ch = &priv->channel_info[i];
4908
8211ef78
TW		 4909 /* FIXME: might be removed if scan is OK*/
4910 if (!is_channel_valid(ch))
b481de9c 4911 continue;
b481de9c
ZY		 4912
4913 if (is_channel_a_band(ch))
8211ef78 4914 sband = &priv->bands[IEEE80211_BAND_5GHZ];
8318d78a 4915 else
8211ef78 4916 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 4917
8211ef78
TW		 4918 geo_ch = &sband->channels[sband->n_channels++];
4919
4920 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB		 4921 geo_ch->max_power = ch->max_power_avg;
4922 geo_ch->max_antenna_gain = 0xff;
7b72304d 4923 geo_ch->hw_value = ch->channel;
b481de9c
ZY		 4924
4925 if (is_channel_valid(ch)) {
8318d78a
JB		 4926 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
4927 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 4928
8318d78a
JB		 4929 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
4930 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY		 4931
4932 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 4933 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY		 4934
4935 if (ch->max_power_avg > priv->max_channel_txpower_limit)
4936 priv->max_channel_txpower_limit =
4937 ch->max_power_avg;
8211ef78 4938 } else {
8318d78a 4939 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW		 4940 }
4941
4942 /* Save flags for reg domain usage */
4943 geo_ch->orig_flags = geo_ch->flags;
4944
4945 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
4946 ch->channel, geo_ch->center_freq,
4947 is_channel_a_band(ch) ? "5.2" : "2.4",
4948 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
4949 "restricted" : "valid",
4950 geo_ch->flags);
b481de9c
ZY		 4951 }
4952
82b9a121
TW		 4953 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
4954 priv->cfg->sku & IWL_SKU_A) {
b481de9c
ZY		 4955 printk(KERN_INFO DRV_NAME
4956 ": Incorrectly detected BG card as ABG. Please send "
4957 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
4958 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 4959 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY		 4960 }
4961
4962 printk(KERN_INFO DRV_NAME
4963 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB		 4964 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
4965 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 4966
e0e0a67e
JL		 4967 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
4968 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
4969 &priv->bands[IEEE80211_BAND_2GHZ];
4970 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
4971 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
4972 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 4973
b481de9c
ZY		 4974 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4975
4976 return 0;
4977}
4978
849e0dce
RC		 4979/*
4980 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
4981 */
4982static void iwl3945_free_geos(struct iwl3945_priv *priv)
4983{
849e0dce
RC		 4984 kfree(priv->ieee_channels);
4985 kfree(priv->ieee_rates);
4986 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
4987}
4988
b481de9c
ZY		 4989/******************************************************************************
4990 *
4991 * uCode download functions
4992 *
4993 ******************************************************************************/
4994
bb8c093b 4995static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c 4996{
98c92211
TW		 4997 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
4998 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
4999 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5000 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5001 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5002 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 5003}
5004
5005/**
bb8c093b 5006 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5007 * looking at all data.
5008 */
3ac7f146 5009static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5010{
5011 u32 val;
5012 u32 save_len = len;
5013 int rc = 0;
5014 u32 errcnt;
5015
5016 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5017
bb8c093b 5018 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5019 if (rc)
5020 return rc;
5021
bb8c093b 5022 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY		 5023
5024 errcnt = 0;
5025 for (; len > 0; len -= sizeof(u32), image++) {
5026 /* read data comes through single port, auto-incr addr */
5027 /* NOTE: Use the debugless read so we don't flood kernel log
5028 * if IWL_DL_IO is set */
bb8c093b 5029 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5030 if (val != le32_to_cpu(*image)) {
5031 IWL_ERROR("uCode INST section is invalid at "
5032 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5033 save_len - len, val, le32_to_cpu(*image));
5034 rc = -EIO;
5035 errcnt++;
5036 if (errcnt >= 20)
5037 break;
5038 }
5039 }
5040
bb8c093b 5041 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5042
5043 if (!errcnt)
bc434dd2 5044 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY		 5045
5046 return rc;
5047}
5048
5049
5050/**
bb8c093b 5051 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5052 * using sample data 100 bytes apart. If these sample points are good,
5053 * it's a pretty good bet that everything between them is good, too.
5054 */
bb8c093b 5055static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5056{
5057 u32 val;
5058 int rc = 0;
5059 u32 errcnt = 0;
5060 u32 i;
5061
5062 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5063
bb8c093b 5064 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5065 if (rc)
5066 return rc;
5067
5068 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5069 /* read data comes through single port, auto-incr addr */
5070 /* NOTE: Use the debugless read so we don't flood kernel log
5071 * if IWL_DL_IO is set */
bb8c093b 5072 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5073 i + RTC_INST_LOWER_BOUND);
bb8c093b 5074 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5075 if (val != le32_to_cpu(*image)) {
5076#if 0 /* Enable this if you want to see details */
5077 IWL_ERROR("uCode INST section is invalid at "
5078 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5079 i, val, *image);
5080#endif
5081 rc = -EIO;
5082 errcnt++;
5083 if (errcnt >= 3)
5084 break;
5085 }
5086 }
5087
bb8c093b 5088 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5089
5090 return rc;
5091}
5092
5093
5094/**
bb8c093b 5095 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 5096 * and verify its contents
5097 */
bb8c093b 5098static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY		 5099{
5100 __le32 *image;
5101 u32 len;
5102 int rc = 0;
5103
5104 /* Try bootstrap */
5105 image = (__le32 *)priv->ucode_boot.v_addr;
5106 len = priv->ucode_boot.len;
bb8c093b 5107 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5108 if (rc == 0) {
5109 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5110 return 0;
5111 }
5112
5113 /* Try initialize */
5114 image = (__le32 *)priv->ucode_init.v_addr;
5115 len = priv->ucode_init.len;
bb8c093b 5116 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5117 if (rc == 0) {
5118 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5119 return 0;
5120 }
5121
5122 /* Try runtime/protocol */
5123 image = (__le32 *)priv->ucode_code.v_addr;
5124 len = priv->ucode_code.len;
bb8c093b 5125 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5126 if (rc == 0) {
5127 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5128 return 0;
5129 }
5130
5131 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5132
9fbab516
BC		 5133 /* Since nothing seems to match, show first several data entries in
5134 * instruction SRAM, so maybe visual inspection will give a clue.
5135 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 5136 image = (__le32 *)priv->ucode_boot.v_addr;
5137 len = priv->ucode_boot.len;
bb8c093b 5138 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY		 5139
5140 return rc;
5141}
5142
5143
5144/* check contents of special bootstrap uCode SRAM */
bb8c093b 5145static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5146{
5147 __le32 *image = priv->ucode_boot.v_addr;
5148 u32 len = priv->ucode_boot.len;
5149 u32 reg;
5150 u32 val;
5151
5152 IWL_DEBUG_INFO("Begin verify bsm\n");
5153
5154 /* verify BSM SRAM contents */
bb8c093b 5155 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY		 5156 for (reg = BSM_SRAM_LOWER_BOUND;
5157 reg < BSM_SRAM_LOWER_BOUND + len;
3ac7f146 5158 reg += sizeof(u32), image++) {
bb8c093b 5159 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY		 5160 if (val != le32_to_cpu(*image)) {
5161 IWL_ERROR("BSM uCode verification failed at "
5162 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5163 BSM_SRAM_LOWER_BOUND,
5164 reg - BSM_SRAM_LOWER_BOUND, len,
5165 val, le32_to_cpu(*image));
5166 return -EIO;
5167 }
5168 }
5169
5170 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5171
5172 return 0;
5173}
5174
5175/**
bb8c093b 5176 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY		 5177 *
5178 * BSM operation:
5179 *
5180 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5181 * in special SRAM that does not power down during RFKILL. When powering back
5182 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5183 * the bootstrap program into the on-board processor, and starts it.
5184 *
5185 * The bootstrap program loads (via DMA) instructions and data for a new
5186 * program from host DRAM locations indicated by the host driver in the
5187 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5188 * automatically.
5189 *
5190 * When initializing the NIC, the host driver points the BSM to the
5191 * "initialize" uCode image. This uCode sets up some internal data, then
5192 * notifies host via "initialize alive" that it is complete.
5193 *
5194 * The host then replaces the BSM_DRAM_* pointer values to point to the
5195 * normal runtime uCode instructions and a backup uCode data cache buffer
5196 * (filled initially with starting data values for the on-board processor),
5197 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5198 * which begins normal operation.
5199 *
5200 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5201 * the backup data cache in DRAM before SRAM is powered down.
5202 *
5203 * When powering back up, the BSM loads the bootstrap program. This reloads
5204 * the runtime uCode instructions and the backup data cache into SRAM,
5205 * and re-launches the runtime uCode from where it left off.
5206 */
bb8c093b 5207static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5208{
5209 __le32 *image = priv->ucode_boot.v_addr;
5210 u32 len = priv->ucode_boot.len;
5211 dma_addr_t pinst;
5212 dma_addr_t pdata;
5213 u32 inst_len;
5214 u32 data_len;
5215 int rc;
5216 int i;
5217 u32 done;
5218 u32 reg_offset;
5219
5220 IWL_DEBUG_INFO("Begin load bsm\n");
5221
5222 /* make sure bootstrap program is no larger than BSM's SRAM size */
5223 if (len > IWL_MAX_BSM_SIZE)
5224 return -EINVAL;
5225
5226 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5227 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5228 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY		 5229 * after the "initialize" uCode has run, to point to
5230 * runtime/protocol instructions and backup data cache. */
5231 pinst = priv->ucode_init.p_addr;
5232 pdata = priv->ucode_init_data.p_addr;
5233 inst_len = priv->ucode_init.len;
5234 data_len = priv->ucode_init_data.len;
5235
bb8c093b 5236 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5237 if (rc)
5238 return rc;
5239
bb8c093b
CH		 5240 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5241 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5242 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5243 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY		 5244
5245 /* Fill BSM memory with bootstrap instructions */
5246 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5247 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5248 reg_offset += sizeof(u32), image++)
bb8c093b 5249 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY		 5250 le32_to_cpu(*image));
5251
bb8c093b 5252 rc = iwl3945_verify_bsm(priv);
b481de9c 5253 if (rc) {
bb8c093b 5254 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5255 return rc;
5256 }
5257
5258 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH		 5259 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5260 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5261 RTC_INST_LOWER_BOUND);
bb8c093b 5262 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY		 5263
5264 /* Load bootstrap code into instruction SRAM now,
5265 * to prepare to load "initialize" uCode */
bb8c093b 5266 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5267 BSM_WR_CTRL_REG_BIT_START);
5268
5269 /* Wait for load of bootstrap uCode to finish */
5270 for (i = 0; i < 100; i++) {
bb8c093b 5271 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY		 5272 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5273 break;
5274 udelay(10);
5275 }
5276 if (i < 100)
5277 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5278 else {
5279 IWL_ERROR("BSM write did not complete!\n");
5280 return -EIO;
5281 }
5282
5283 /* Enable future boot loads whenever power management unit triggers it
5284 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5285 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5286 BSM_WR_CTRL_REG_BIT_START_EN);
5287
bb8c093b 5288 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5289
5290 return 0;
5291}
5292
bb8c093b 5293static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5294{
5295 /* Remove all resets to allow NIC to operate */
bb8c093b 5296 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 5297}
5298
5299/**
bb8c093b 5300 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 5301 *
5302 * Copy into buffers for card to fetch via bus-mastering
5303 */
bb8c093b 5304static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5305{
bb8c093b 5306 struct iwl3945_ucode *ucode;
a0987a8d 5307 int ret = -EINVAL, index;
b481de9c
ZY		 5308 const struct firmware *ucode_raw;
5309 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC		 5310 const char *name_pre = priv->cfg->fw_name_pre;
5311 const unsigned int api_max = priv->cfg->ucode_api_max;
5312 const unsigned int api_min = priv->cfg->ucode_api_min;
5313 char buf[25];
b481de9c
ZY		 5314 u8 *src;
5315 size_t len;
a0987a8d 5316 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY		 5317
5318 /* Ask kernel firmware_class module to get the boot firmware off disk.
5319 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC		 5320 for (index = api_max; index >= api_min; index--) {
5321 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
5322 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
5323 if (ret < 0) {
5324 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5325 buf, ret);
5326 if (ret == -ENOENT)
5327 continue;
5328 else
5329 goto error;
5330 } else {
5331 if (index < api_max)
5332 IWL_ERROR("Loaded firmware %s, which is deprecated. Please use API v%u instead.\n",
5333 buf, api_max);
5334 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5335 buf, ucode_raw->size);
5336 break;
5337 }
b481de9c
ZY		 5338 }
5339
a0987a8d
RC		 5340 if (ret < 0)
5341 goto error;
b481de9c
ZY		 5342
5343 /* Make sure that we got at least our header! */
5344 if (ucode_raw->size < sizeof(*ucode)) {
5345 IWL_ERROR("File size way too small!\n");
90e759d1 5346 ret = -EINVAL;
b481de9c
ZY		 5347 goto err_release;
5348 }
5349
5350 /* Data from ucode file: header followed by uCode images */
5351 ucode = (void *)ucode_raw->data;
5352
c02b3acd 5353 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 5354 api_ver = IWL_UCODE_API(priv->ucode_ver);
b481de9c
ZY		 5355 inst_size = le32_to_cpu(ucode->inst_size);
5356 data_size = le32_to_cpu(ucode->data_size);
5357 init_size = le32_to_cpu(ucode->init_size);
5358 init_data_size = le32_to_cpu(ucode->init_data_size);
5359 boot_size = le32_to_cpu(ucode->boot_size);
5360
a0987a8d
RC		 5361 /* api_ver should match the api version forming part of the
5362 * firmware filename ... but we don't check for that and only rely
5363 * on the API version read from firware header from here on forward */
5364
5365 if (api_ver < api_min || api_ver > api_max) {
5366 IWL_ERROR("Driver unable to support your firmware API. "
5367 "Driver supports v%u, firmware is v%u.\n",
5368 api_max, api_ver);
5369 priv->ucode_ver = 0;
5370 ret = -EINVAL;
5371 goto err_release;
5372 }
5373 if (api_ver != api_max)
5374 IWL_ERROR("Firmware has old API version. Expected %u, "
5375 "got %u. New firmware can be obtained "
5376 "from http://www.intellinuxwireless.org.\n",
5377 api_max, api_ver);
5378
5379 printk(KERN_INFO DRV_NAME " loaded firmware version %u.%u.%u.%u\n",
c02b3acd
CR		 5380 IWL_UCODE_MAJOR(priv->ucode_ver),
5381 IWL_UCODE_MINOR(priv->ucode_ver),
5382 IWL_UCODE_API(priv->ucode_ver),
5383 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d
RC		 5384 IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
5385 priv->ucode_ver);
bc434dd2
IS		 5386 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5387 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5388 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5389 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5390 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c 5391
a0987a8d 5392
b481de9c
ZY		 5393 /* Verify size of file vs. image size info in file's header */
5394 if (ucode_raw->size < sizeof(*ucode) +
5395 inst_size + data_size + init_size +
5396 init_data_size + boot_size) {
5397
5398 IWL_DEBUG_INFO("uCode file size %d too small\n",
5399 (int)ucode_raw->size);
90e759d1 5400 ret = -EINVAL;
b481de9c
ZY		 5401 goto err_release;
5402 }
5403
5404 /* Verify that uCode images will fit in card's SRAM */
5405 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5406 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5407 inst_size);
5408 ret = -EINVAL;
b481de9c
ZY		 5409 goto err_release;
5410 }
5411
5412 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5413 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5414 data_size);
5415 ret = -EINVAL;
b481de9c
ZY		 5416 goto err_release;
5417 }
5418 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5419 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5420 init_size);
5421 ret = -EINVAL;
b481de9c
ZY		 5422 goto err_release;
5423 }
5424 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5425 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5426 init_data_size);
5427 ret = -EINVAL;
b481de9c
ZY		 5428 goto err_release;
5429 }
5430 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW		 5431 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5432 boot_size);
5433 ret = -EINVAL;
b481de9c
ZY		 5434 goto err_release;
5435 }
5436
5437 /* Allocate ucode buffers for card's bus-master loading ... */
5438
5439 /* Runtime instructions and 2 copies of data:
5440 * 1) unmodified from disk
5441 * 2) backup cache for save/restore during power-downs */
5442 priv->ucode_code.len = inst_size;
98c92211 5443 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 5444
5445 priv->ucode_data.len = data_size;
98c92211 5446 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 5447
5448 priv->ucode_data_backup.len = data_size;
98c92211 5449 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5450
90e759d1
TW		 5451 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5452 !priv->ucode_data_backup.v_addr)
5453 goto err_pci_alloc;
b481de9c
ZY		 5454
5455 /* Initialization instructions and data */
90e759d1
TW		 5456 if (init_size && init_data_size) {
5457 priv->ucode_init.len = init_size;
98c92211 5458 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 5459
5460 priv->ucode_init_data.len = init_data_size;
98c92211 5461 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 5462
5463 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5464 goto err_pci_alloc;
5465 }
b481de9c
ZY		 5466
5467 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 5468 if (boot_size) {
5469 priv->ucode_boot.len = boot_size;
98c92211 5470 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5471
90e759d1
TW		 5472 if (!priv->ucode_boot.v_addr)
5473 goto err_pci_alloc;
5474 }
b481de9c
ZY		 5475
5476 /* Copy images into buffers for card's bus-master reads ... */
5477
5478 /* Runtime instructions (first block of data in file) */
5479 src = &ucode->data[0];
5480 len = priv->ucode_code.len;
90e759d1 5481 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 5482 memcpy(priv->ucode_code.v_addr, src, len);
5483 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5484 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5485
5486 /* Runtime data (2nd block)
bb8c093b 5487 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY		 5488 src = &ucode->data[inst_size];
5489 len = priv->ucode_data.len;
90e759d1 5490 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 5491 memcpy(priv->ucode_data.v_addr, src, len);
5492 memcpy(priv->ucode_data_backup.v_addr, src, len);
5493
5494 /* Initialization instructions (3rd block) */
5495 if (init_size) {
5496 src = &ucode->data[inst_size + data_size];
5497 len = priv->ucode_init.len;
90e759d1
TW		 5498 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5499 len);
b481de9c
ZY		 5500 memcpy(priv->ucode_init.v_addr, src, len);
5501 }
5502
5503 /* Initialization data (4th block) */
5504 if (init_data_size) {
5505 src = &ucode->data[inst_size + data_size + init_size];
5506 len = priv->ucode_init_data.len;
5507 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5508 (int)len);
5509 memcpy(priv->ucode_init_data.v_addr, src, len);
5510 }
5511
5512 /* Bootstrap instructions (5th block) */
5513 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5514 len = priv->ucode_boot.len;
5515 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5516 (int)len);
5517 memcpy(priv->ucode_boot.v_addr, src, len);
5518
5519 /* We have our copies now, allow OS release its copies */
5520 release_firmware(ucode_raw);
5521 return 0;
5522
5523 err_pci_alloc:
5524 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 5525 ret = -ENOMEM;
bb8c093b 5526 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 5527
5528 err_release:
5529 release_firmware(ucode_raw);
5530
5531 error:
90e759d1 5532 return ret;
b481de9c
ZY		 5533}
5534
5535
5536/**
bb8c093b 5537 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 5538 *
5539 * Tell initialization uCode where to find runtime uCode.
5540 *
5541 * BSM registers initially contain pointers to initialization uCode.
5542 * We need to replace them to load runtime uCode inst and data,
5543 * and to save runtime data when powering down.
5544 */
bb8c093b 5545static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY		 5546{
5547 dma_addr_t pinst;
5548 dma_addr_t pdata;
5549 int rc = 0;
5550 unsigned long flags;
5551
5552 /* bits 31:0 for 3945 */
5553 pinst = priv->ucode_code.p_addr;
5554 pdata = priv->ucode_data_backup.p_addr;
5555
5556 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5557 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5558 if (rc) {
5559 spin_unlock_irqrestore(&priv->lock, flags);
5560 return rc;
5561 }
5562
5563 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH		 5564 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5565 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5566 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 5567 priv->ucode_data.len);
5568
a96a27f9 5569 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 5570 * that all new ptr/size info is in place */
bb8c093b 5571 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 5572 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5573
bb8c093b 5574 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5575
5576 spin_unlock_irqrestore(&priv->lock, flags);
5577
5578 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5579
5580 return rc;
5581}
5582
5583/**
bb8c093b 5584 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 5585 *
5586 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5587 *
b481de9c 5588 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 5589 */
bb8c093b 5590static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5591{
5592 /* Check alive response for "valid" sign from uCode */
5593 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5594 /* We had an error bringing up the hardware, so take it
5595 * all the way back down so we can try again */
5596 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5597 goto restart;
5598 }
5599
5600 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5601 * This is a paranoid check, because we would not have gotten the
5602 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5603 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5604 /* Runtime instruction load was bad;
5605 * take it all the way back down so we can try again */
5606 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5607 goto restart;
5608 }
5609
5610 /* Send pointers to protocol/runtime uCode image ... init code will
5611 * load and launch runtime uCode, which will send us another "Alive"
5612 * notification. */
5613 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5614 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY		 5615 /* Runtime instruction load won't happen;
5616 * take it all the way back down so we can try again */
5617 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5618 goto restart;
5619 }
5620 return;
5621
5622 restart:
5623 queue_work(priv->workqueue, &priv->restart);
5624}
5625
5626
9bdf5eca
MA		 5627/* temporary */
5628static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
5629 struct sk_buff *skb);
5630
b481de9c 5631/**
bb8c093b 5632 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 5633 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5634 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 5635 */
bb8c093b 5636static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5637{
5638 int rc = 0;
5639 int thermal_spin = 0;
5640 u32 rfkill;
5641
5642 IWL_DEBUG_INFO("Runtime Alive received.\n");
5643
5644 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5645 /* We had an error bringing up the hardware, so take it
5646 * all the way back down so we can try again */
5647 IWL_DEBUG_INFO("Alive failed.\n");
5648 goto restart;
5649 }
5650
5651 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5652 * This is a paranoid check, because we would not have gotten the
5653 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5654 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5655 /* Runtime instruction load was bad;
5656 * take it all the way back down so we can try again */
5657 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5658 goto restart;
5659 }
5660
bb8c093b 5661 iwl3945_clear_stations_table(priv);
b481de9c 5662
bb8c093b 5663 rc = iwl3945_grab_nic_access(priv);
b481de9c 5664 if (rc) {
a96a27f9 5665 IWL_WARNING("Can not read RFKILL status from adapter\n");
b481de9c
ZY		 5666 return;
5667 }
5668
bb8c093b 5669 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 5670 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 5671 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5672
5673 if (rfkill & 0x1) {
5674 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 5675 /* if RFKILL is not on, then wait for thermal
b481de9c 5676 * sensor in adapter to kick in */
bb8c093b 5677 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY		 5678 thermal_spin++;
5679 udelay(10);
5680 }
5681
5682 if (thermal_spin)
5683 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5684 thermal_spin * 10);
5685 } else
5686 set_bit(STATUS_RF_KILL_HW, &priv->status);
5687
9fbab516 5688 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY		 5689 set_bit(STATUS_ALIVE, &priv->status);
5690
5691 /* Clear out the uCode error bit if it is set */
5692 clear_bit(STATUS_FW_ERROR, &priv->status);
5693
bb8c093b 5694 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 5695 return;
5696
36d6825b 5697 ieee80211_wake_queues(priv->hw);
b481de9c
ZY		 5698
5699 priv->active_rate = priv->rates_mask;
5700 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5701
bb8c093b 5702 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5703
bb8c093b
CH		 5704 if (iwl3945_is_associated(priv)) {
5705 struct iwl3945_rxon_cmd *active_rxon =
5706 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY		 5707
5708 memcpy(&priv->staging_rxon, &priv->active_rxon,
5709 sizeof(priv->staging_rxon));
5710 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5711 } else {
5712 /* Initialize our rx_config data */
60294de3 5713 iwl3945_connection_init_rx_config(priv, priv->iw_mode);
b481de9c
ZY		 5714 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
5715 }
5716
9fbab516 5717 /* Configure Bluetooth device coexistence support */
bb8c093b 5718 iwl3945_send_bt_config(priv);
b481de9c
ZY		 5719
5720 /* Configure the adapter for unassociated operation */
bb8c093b 5721 iwl3945_commit_rxon(priv);
b481de9c 5722
b481de9c
ZY		 5723 iwl3945_reg_txpower_periodic(priv);
5724
fe00b5a5
RC		 5725 iwl3945_led_register(priv);
5726
b481de9c 5727 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5728 set_bit(STATUS_READY, &priv->status);
5a66926a 5729 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 5730
5731 if (priv->error_recovering)
bb8c093b 5732 iwl3945_error_recovery(priv);
b481de9c 5733
9bdf5eca
MA		 5734 /* reassociate for ADHOC mode */
5735 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
5736 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
5737 priv->vif);
5738 if (beacon)
5739 iwl3945_mac_beacon_update(priv->hw, beacon);
5740 }
5741
b481de9c
ZY		 5742 return;
5743
5744 restart:
5745 queue_work(priv->workqueue, &priv->restart);
5746}
5747
bb8c093b 5748static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 5749
bb8c093b 5750static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5751{
5752 unsigned long flags;
5753 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5754 struct ieee80211_conf *conf = NULL;
5755
5756 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5757
5758 conf = ieee80211_get_hw_conf(priv->hw);
5759
5760 if (!exit_pending)
5761 set_bit(STATUS_EXIT_PENDING, &priv->status);
5762
ab53d8af 5763 iwl3945_led_unregister(priv);
bb8c093b 5764 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5765
5766 /* Unblock any waiting calls */
5767 wake_up_interruptible_all(&priv->wait_command_queue);
5768
b481de9c
ZY		 5769 /* Wipe out the EXIT_PENDING status bit if we are not actually
5770 * exiting the module */
5771 if (!exit_pending)
5772 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5773
5774 /* stop and reset the on-board processor */
bb8c093b 5775 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 5776
5777 /* tell the device to stop sending interrupts */
0359facc 5778 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5779 iwl3945_disable_interrupts(priv);
0359facc
MA		 5780 spin_unlock_irqrestore(&priv->lock, flags);
5781 iwl_synchronize_irq(priv);
b481de9c
ZY		 5782
5783 if (priv->mac80211_registered)
5784 ieee80211_stop_queues(priv->hw);
5785
bb8c093b 5786 /* If we have not previously called iwl3945_init() then
b481de9c 5787 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 5788 if (!iwl3945_is_init(priv)) {
b481de9c
ZY		 5789 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5790 STATUS_RF_KILL_HW |
5791 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5792 STATUS_RF_KILL_SW |
9788864e
RC		 5793 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5794 STATUS_GEO_CONFIGURED |
b481de9c 5795 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
ebef2008
AK		 5796 STATUS_IN_SUSPEND |
5797 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5798 STATUS_EXIT_PENDING;
b481de9c
ZY		 5799 goto exit;
5800 }
5801
5802 /* ...otherwise clear out all the status bits but the RF Kill and
5803 * SUSPEND bits and continue taking the NIC down. */
5804 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5805 STATUS_RF_KILL_HW |
5806 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5807 STATUS_RF_KILL_SW |
9788864e
RC		 5808 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5809 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5810 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5811 STATUS_IN_SUSPEND |
5812 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK		 5813 STATUS_FW_ERROR |
5814 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5815 STATUS_EXIT_PENDING;
b481de9c
ZY		 5816
5817 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5818 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 5819 spin_unlock_irqrestore(&priv->lock, flags);
5820
bb8c093b
CH		 5821 iwl3945_hw_txq_ctx_stop(priv);
5822 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY		 5823
5824 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 5825 if (!iwl3945_grab_nic_access(priv)) {
5826 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5827 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 5828 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5829 }
5830 spin_unlock_irqrestore(&priv->lock, flags);
5831
5832 udelay(5);
5833
bb8c093b
CH		 5834 iwl3945_hw_nic_stop_master(priv);
5835 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
5836 iwl3945_hw_nic_reset(priv);
b481de9c
ZY		 5837
5838 exit:
bb8c093b 5839 memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
b481de9c
ZY		 5840
5841 if (priv->ibss_beacon)
5842 dev_kfree_skb(priv->ibss_beacon);
5843 priv->ibss_beacon = NULL;
5844
5845 /* clear out any free frames */
bb8c093b 5846 iwl3945_clear_free_frames(priv);
b481de9c
ZY		 5847}
5848
bb8c093b 5849static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5850{
5851 mutex_lock(&priv->mutex);
bb8c093b 5852 __iwl3945_down(priv);
b481de9c 5853 mutex_unlock(&priv->mutex);
b24d22b1 5854
bb8c093b 5855 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY		 5856}
5857
5858#define MAX_HW_RESTARTS 5
5859
bb8c093b 5860static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c
ZY		 5861{
5862 int rc, i;
5863
5864 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5865 IWL_WARNING("Exit pending; will not bring the NIC up\n");
5866 return -EIO;
5867 }
5868
5869 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
5870 IWL_WARNING("Radio disabled by SW RF kill (module "
5871 "parameter)\n");
e655b9f0
ZY		 5872 return -ENODEV;
5873 }
5874
e903fbd4 5875 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
a96a27f9 5876 IWL_ERROR("ucode not available for device bring up\n");
e903fbd4
RC		 5877 return -EIO;
5878 }
5879
e655b9f0
ZY		 5880 /* If platform's RF_KILL switch is NOT set to KILL */
5881 if (iwl3945_read32(priv, CSR_GP_CNTRL) &
5882 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5883 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5884 else {
5885 set_bit(STATUS_RF_KILL_HW, &priv->status);
5886 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
5887 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
5888 return -ENODEV;
5889 }
b481de9c 5890 }
80fcc9e2 5891
bb8c093b 5892 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 5893
bb8c093b 5894 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY		 5895 if (rc) {
5896 IWL_ERROR("Unable to int nic\n");
5897 return rc;
5898 }
5899
5900 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH		 5901 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5902 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 5903 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5904
5905 /* clear (again), then enable host interrupts */
bb8c093b
CH		 5906 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
5907 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 5908
5909 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH		 5910 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5911 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 5912
5913 /* Copy original ucode data image from disk into backup cache.
5914 * This will be used to initialize the on-board processor's
5915 * data SRAM for a clean start when the runtime program first loads. */
5916 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 5917 priv->ucode_data.len);
b481de9c 5918
e655b9f0
ZY		 5919 /* We return success when we resume from suspend and rf_kill is on. */
5920 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
5921 return 0;
5922
b481de9c
ZY		 5923 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5924
bb8c093b 5925 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5926
5927 /* load bootstrap state machine,
5928 * load bootstrap program into processor's memory,
5929 * prepare to load the "initialize" uCode */
bb8c093b 5930 rc = iwl3945_load_bsm(priv);
b481de9c
ZY		 5931
5932 if (rc) {
5933 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
5934 continue;
5935 }
5936
5937 /* start card; "initialize" will load runtime ucode */
bb8c093b 5938 iwl3945_nic_start(priv);
b481de9c 5939
b481de9c
ZY		 5940 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
5941
5942 return 0;
5943 }
5944
5945 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 5946 __iwl3945_down(priv);
ebef2008 5947 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 5948
5949 /* tried to restart and config the device for as long as our
5950 * patience could withstand */
5951 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
5952 return -EIO;
5953}
5954
5955
5956/*****************************************************************************
5957 *
5958 * Workqueue callbacks
5959 *
5960 *****************************************************************************/
5961
bb8c093b 5962static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 5963{
bb8c093b
CH		 5964 struct iwl3945_priv *priv =
5965 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY		 5966
5967 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5968 return;
5969
5970 mutex_lock(&priv->mutex);
bb8c093b 5971 iwl3945_init_alive_start(priv);
b481de9c
ZY		 5972 mutex_unlock(&priv->mutex);
5973}
5974
bb8c093b 5975static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 5976{
bb8c093b
CH		 5977 struct iwl3945_priv *priv =
5978 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY		 5979
5980 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5981 return;
5982
5983 mutex_lock(&priv->mutex);
bb8c093b 5984 iwl3945_alive_start(priv);
b481de9c
ZY		 5985 mutex_unlock(&priv->mutex);
5986}
5987
bb8c093b 5988static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 5989{
bb8c093b 5990 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY		 5991
5992 wake_up_interruptible(&priv->wait_command_queue);
5993
5994 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5995 return;
5996
5997 mutex_lock(&priv->mutex);
5998
bb8c093b 5999 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6000 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6001 "HW and/or SW RF Kill no longer active, restarting "
6002 "device\n");
6003 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6004 queue_work(priv->workqueue, &priv->restart);
6005 } else {
6006
6007 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6008 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6009 "disabled by SW switch\n");
6010 else
6011 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6012 "Kill switch must be turned off for "
6013 "wireless networking to work.\n");
6014 }
ebef2008 6015
b481de9c 6016 mutex_unlock(&priv->mutex);
80fcc9e2 6017 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 6018}
6019
6020#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6021
bb8c093b 6022static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6023{
bb8c093b
CH		 6024 struct iwl3945_priv *priv =
6025 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY		 6026
6027 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6028 return;
6029
6030 mutex_lock(&priv->mutex);
6031 if (test_bit(STATUS_SCANNING, &priv->status) ||
6032 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6033 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6034 "Scan completion watchdog resetting adapter (%dms)\n",
6035 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6036
b481de9c 6037 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6038 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6039 }
6040 mutex_unlock(&priv->mutex);
6041}
6042
bb8c093b 6043static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6044{
bb8c093b
CH		 6045 struct iwl3945_priv *priv =
6046 container_of(data, struct iwl3945_priv, request_scan);
6047 struct iwl3945_host_cmd cmd = {
b481de9c 6048 .id = REPLY_SCAN_CMD,
bb8c093b 6049 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY		 6050 .meta.flags = CMD_SIZE_HUGE,
6051 };
6052 int rc = 0;
bb8c093b 6053 struct iwl3945_scan_cmd *scan;
b481de9c 6054 struct ieee80211_conf *conf = NULL;
f9340520 6055 u8 n_probes = 2;
8318d78a 6056 enum ieee80211_band band;
9387b7ca 6057 DECLARE_SSID_BUF(ssid);
b481de9c
ZY		 6058
6059 conf = ieee80211_get_hw_conf(priv->hw);
6060
6061 mutex_lock(&priv->mutex);
6062
bb8c093b 6063 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 6064 IWL_WARNING("request scan called when driver not ready.\n");
6065 goto done;
6066 }
6067
a96a27f9 6068 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY		 6069 * was given the chance to run... */
6070 if (!test_bit(STATUS_SCANNING, &priv->status))
6071 goto done;
6072
6073 /* This should never be called or scheduled if there is currently
6074 * a scan active in the hardware. */
6075 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6076 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6077 "Ignoring second request.\n");
6078 rc = -EIO;
6079 goto done;
6080 }
6081
6082 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6083 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6084 goto done;
6085 }
6086
6087 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6088 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6089 goto done;
6090 }
6091
bb8c093b 6092 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6093 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6094 goto done;
6095 }
6096
6097 if (!test_bit(STATUS_READY, &priv->status)) {
6098 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6099 goto done;
6100 }
6101
6102 if (!priv->scan_bands) {
6103 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6104 goto done;
6105 }
6106
6107 if (!priv->scan) {
bb8c093b 6108 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY		 6109 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6110 if (!priv->scan) {
6111 rc = -ENOMEM;
6112 goto done;
6113 }
6114 }
6115 scan = priv->scan;
bb8c093b 6116 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 6117
6118 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6119 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6120
bb8c093b 6121 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 6122 u16 interval = 0;
6123 u32 extra;
6124 u32 suspend_time = 100;
6125 u32 scan_suspend_time = 100;
6126 unsigned long flags;
6127
6128 IWL_DEBUG_INFO("Scanning while associated...\n");
6129
6130 spin_lock_irqsave(&priv->lock, flags);
6131 interval = priv->beacon_int;
6132 spin_unlock_irqrestore(&priv->lock, flags);
6133
6134 scan->suspend_time = 0;
15e869d8 6135 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 6136 if (!interval)
6137 interval = suspend_time;
6138 /*
6139 * suspend time format:
6140 * 0-19: beacon interval in usec (time before exec.)
6141 * 20-23: 0
6142 * 24-31: number of beacons (suspend between channels)
6143 */
6144
6145 extra = (suspend_time / interval) << 24;
6146 scan_suspend_time = 0xFF0FFFFF &
6147 (extra | ((suspend_time % interval) * 1024));
6148
6149 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6150 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6151 scan_suspend_time, interval);
6152 }
6153
6154 /* We should add the ability for user to lock to PASSIVE ONLY */
6155 if (priv->one_direct_scan) {
6156 IWL_DEBUG_SCAN
6157 ("Kicking off one direct scan for '%s'\n",
9387b7ca
JL		 6158 print_ssid(ssid, priv->direct_ssid,
6159 priv->direct_ssid_len));
b481de9c
ZY		 6160 scan->direct_scan[0].id = WLAN_EID_SSID;
6161 scan->direct_scan[0].len = priv->direct_ssid_len;
6162 memcpy(scan->direct_scan[0].ssid,
6163 priv->direct_ssid, priv->direct_ssid_len);
f9340520 6164 n_probes++;
f9340520 6165 } else
786b4557 6166 IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
b481de9c
ZY		 6167
6168 /* We don't build a direct scan probe request; the uCode will do
6169 * that based on the direct_mask added to each channel entry */
6170 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6171 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
430cfe95 6172 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
b481de9c
ZY		 6173 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6174 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6175 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6176
6177 /* flags + rate selection */
6178
66b5004d 6179 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY		 6180 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6181 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6182 scan->good_CRC_th = 0;
8318d78a 6183 band = IEEE80211_BAND_2GHZ;
66b5004d 6184 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c
ZY		 6185 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6186 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6187 band = IEEE80211_BAND_5GHZ;
66b5004d 6188 } else {
b481de9c
ZY		 6189 IWL_WARNING("Invalid scan band count\n");
6190 goto done;
6191 }
6192
6193 /* select Rx antennas */
6194 scan->flags |= iwl3945_get_antenna_flags(priv);
6195
05c914fe 6196 if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
b481de9c
ZY		 6197 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6198
f9340520
AK		 6199 scan->channel_count =
6200 iwl3945_get_channels_for_scan(priv, band, 1, /* active */
6201 n_probes,
6202 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 6203
14b54336
RC		 6204 if (scan->channel_count == 0) {
6205 IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
6206 goto done;
6207 }
6208
b481de9c 6209 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6210 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY		 6211 cmd.data = scan;
6212 scan->len = cpu_to_le16(cmd.len);
6213
6214 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6215 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 6216 if (rc)
6217 goto done;
6218
6219 queue_delayed_work(priv->workqueue, &priv->scan_check,
6220 IWL_SCAN_CHECK_WATCHDOG);
6221
6222 mutex_unlock(&priv->mutex);
6223 return;
6224
6225 done:
2420ebc1
MA		 6226 /* can not perform scan make sure we clear scanning
6227 * bits from status so next scan request can be performed.
6228 * if we dont clear scanning status bit here all next scan
6229 * will fail
6230 */
6231 clear_bit(STATUS_SCAN_HW, &priv->status);
6232 clear_bit(STATUS_SCANNING, &priv->status);
6233
01ebd063 6234 /* inform mac80211 scan aborted */
b481de9c
ZY		 6235 queue_work(priv->workqueue, &priv->scan_completed);
6236 mutex_unlock(&priv->mutex);
6237}
6238
bb8c093b 6239static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6240{
bb8c093b 6241 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY		 6242
6243 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6244 return;
6245
6246 mutex_lock(&priv->mutex);
bb8c093b 6247 __iwl3945_up(priv);
b481de9c 6248 mutex_unlock(&priv->mutex);
80fcc9e2 6249 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 6250}
6251
bb8c093b 6252static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6253{
bb8c093b 6254 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY		 6255
6256 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6257 return;
6258
bb8c093b 6259 iwl3945_down(priv);
b481de9c
ZY		 6260 queue_work(priv->workqueue, &priv->up);
6261}
6262
bb8c093b 6263static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6264{
bb8c093b
CH		 6265 struct iwl3945_priv *priv =
6266 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY		 6267
6268 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6269 return;
6270
6271 mutex_lock(&priv->mutex);
bb8c093b 6272 iwl3945_rx_replenish(priv);
b481de9c
ZY		 6273 mutex_unlock(&priv->mutex);
6274}
6275
7878a5a4
MA		 6276#define IWL_DELAY_NEXT_SCAN (HZ*2)
6277
cd56d331 6278static void iwl3945_post_associate(struct iwl3945_priv *priv)
b481de9c 6279{
b481de9c
ZY		 6280 int rc = 0;
6281 struct ieee80211_conf *conf = NULL;
6282
05c914fe 6283 if (priv->iw_mode == NL80211_IFTYPE_AP) {
3ac7f146 6284 IWL_ERROR("%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 6285 return;
6286 }
6287
6288
e174961c
JB		 6289 IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
6290 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY		 6291
6292 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6293 return;
6294
322a9811 6295 if (!priv->vif || !priv->is_open)
6ef89d0a 6296 return;
322a9811 6297
bb8c093b 6298 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6299
b481de9c
ZY		 6300 conf = ieee80211_get_hw_conf(priv->hw);
6301
6302 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6303 iwl3945_commit_rxon(priv);
b481de9c 6304
bb8c093b
CH		 6305 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6306 iwl3945_setup_rxon_timing(priv);
6307 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6308 sizeof(priv->rxon_timing), &priv->rxon_timing);
6309 if (rc)
6310 IWL_WARNING("REPLY_RXON_TIMING failed - "
6311 "Attempting to continue.\n");
6312
6313 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6314
6315 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6316
6317 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6318 priv->assoc_id, priv->beacon_int);
6319
6320 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6321 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6322 else
6323 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6324
6325 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6326 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6327 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6328 else
6329 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6330
05c914fe 6331 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 6332 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6333
6334 }
6335
bb8c093b 6336 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6337
6338 switch (priv->iw_mode) {
05c914fe 6339 case NL80211_IFTYPE_STATION:
bb8c093b 6340 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 6341 break;
6342
05c914fe 6343 case NL80211_IFTYPE_ADHOC:
b481de9c 6344
ce546fd2 6345 priv->assoc_id = 1;
bb8c093b 6346 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 6347 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 6348 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY		 6349 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6350 CMD_ASYNC);
bb8c093b
CH		 6351 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6352 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6353
6354 break;
6355
6356 default:
6357 IWL_ERROR("%s Should not be called in %d mode\n",
3ac7f146 6358 __func__, priv->iw_mode);
b481de9c
ZY		 6359 break;
6360 }
6361
bb8c093b 6362 iwl3945_activate_qos(priv, 0);
292ae174 6363
7878a5a4
MA		 6364 /* we have just associated, don't start scan too early */
6365 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK		 6366}
6367
bb8c093b 6368static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6369{
bb8c093b 6370 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6371
bb8c093b 6372 if (!iwl3945_is_ready(priv))
b481de9c
ZY		 6373 return;
6374
6375 mutex_lock(&priv->mutex);
6376
6377 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6378 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6379
6380 mutex_unlock(&priv->mutex);
6381}
6382
e8975581 6383static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
76bb77e0 6384
bb8c093b 6385static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6386{
bb8c093b
CH		 6387 struct iwl3945_priv *priv =
6388 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY		 6389
6390 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6391
6392 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6393 return;
6394
a0646470 6395 if (test_bit(STATUS_CONF_PENDING, &priv->status))
e8975581 6396 iwl3945_mac_config(priv->hw, 0);
76bb77e0 6397
b481de9c
ZY		 6398 ieee80211_scan_completed(priv->hw);
6399
6400 /* Since setting the TXPOWER may have been deferred while
6401 * performing the scan, fire one off */
6402 mutex_lock(&priv->mutex);
bb8c093b 6403 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 6404 mutex_unlock(&priv->mutex);
6405}
6406
6407/*****************************************************************************
6408 *
6409 * mac80211 entry point functions
6410 *
6411 *****************************************************************************/
6412
5a66926a
ZY		 6413#define UCODE_READY_TIMEOUT (2 * HZ)
6414
bb8c093b 6415static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6416{
bb8c093b 6417 struct iwl3945_priv *priv = hw->priv;
5a66926a 6418 int ret;
b481de9c
ZY		 6419
6420 IWL_DEBUG_MAC80211("enter\n");
6421
5a66926a
ZY		 6422 if (pci_enable_device(priv->pci_dev)) {
6423 IWL_ERROR("Fail to pci_enable_device\n");
6424 return -ENODEV;
6425 }
6426 pci_restore_state(priv->pci_dev);
6427 pci_enable_msi(priv->pci_dev);
6428
6429 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6430 DRV_NAME, priv);
6431 if (ret) {
6432 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6433 goto out_disable_msi;
6434 }
6435
b481de9c
ZY		 6436 /* we should be verifying the device is ready to be opened */
6437 mutex_lock(&priv->mutex);
6438
5a66926a
ZY		 6439 memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
6440 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6441 * ucode filename and max sizes are card-specific. */
6442
6443 if (!priv->ucode_code.len) {
6444 ret = iwl3945_read_ucode(priv);
6445 if (ret) {
6446 IWL_ERROR("Could not read microcode: %d\n", ret);
6447 mutex_unlock(&priv->mutex);
6448 goto out_release_irq;
6449 }
6450 }
b481de9c 6451
e655b9f0 6452 ret = __iwl3945_up(priv);
b481de9c
ZY		 6453
6454 mutex_unlock(&priv->mutex);
5a66926a 6455
80fcc9e2
AG		 6456 iwl3945_rfkill_set_hw_state(priv);
6457
e655b9f0
ZY		 6458 if (ret)
6459 goto out_release_irq;
6460
6461 IWL_DEBUG_INFO("Start UP work.\n");
6462
6463 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6464 return 0;
6465
5a66926a
ZY		 6466 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6467 * mac80211 will not be run successfully. */
6468 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6469 test_bit(STATUS_READY, &priv->status),
6470 UCODE_READY_TIMEOUT);
6471 if (!ret) {
6472 if (!test_bit(STATUS_READY, &priv->status)) {
6473 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6474 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6475 ret = -ETIMEDOUT;
6476 goto out_release_irq;
6477 }
6478 }
6479
e655b9f0 6480 priv->is_open = 1;
b481de9c
ZY		 6481 IWL_DEBUG_MAC80211("leave\n");
6482 return 0;
5a66926a
ZY		 6483
6484out_release_irq:
6485 free_irq(priv->pci_dev->irq, priv);
6486out_disable_msi:
6487 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY		 6488 pci_disable_device(priv->pci_dev);
6489 priv->is_open = 0;
6490 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6491 return ret;
b481de9c
ZY		 6492}
6493
bb8c093b 6494static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6495{
bb8c093b 6496 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6497
6498 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6499
e655b9f0
ZY		 6500 if (!priv->is_open) {
6501 IWL_DEBUG_MAC80211("leave - skip\n");
6502 return;
6503 }
6504
b481de9c 6505 priv->is_open = 0;
5a66926a
ZY		 6506
6507 if (iwl3945_is_ready_rf(priv)) {
e655b9f0
ZY		 6508 /* stop mac, cancel any scan request and clear
6509 * RXON_FILTER_ASSOC_MSK BIT
6510 */
5a66926a
ZY		 6511 mutex_lock(&priv->mutex);
6512 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f 6513 mutex_unlock(&priv->mutex);
fde3571f
MA		 6514 }
6515
5a66926a
ZY		 6516 iwl3945_down(priv);
6517
6518 flush_workqueue(priv->workqueue);
6519 free_irq(priv->pci_dev->irq, priv);
6520 pci_disable_msi(priv->pci_dev);
6521 pci_save_state(priv->pci_dev);
6522 pci_disable_device(priv->pci_dev);
6ef89d0a 6523
b481de9c 6524 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6525}
6526
e039fa4a 6527static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6528{
bb8c093b 6529 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6530
6531 IWL_DEBUG_MAC80211("enter\n");
6532
b481de9c 6533 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 6534 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 6535
e039fa4a 6536 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY		 6537 dev_kfree_skb_any(skb);
6538
6539 IWL_DEBUG_MAC80211("leave\n");
6540 return 0;
6541}
6542
bb8c093b 6543static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6544 struct ieee80211_if_init_conf *conf)
6545{
bb8c093b 6546 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6547 unsigned long flags;
6548
32bfd35d 6549 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6550
32bfd35d
JB		 6551 if (priv->vif) {
6552 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6553 return -EOPNOTSUPP;
b481de9c
ZY		 6554 }
6555
6556 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6557 priv->vif = conf->vif;
60294de3 6558 priv->iw_mode = conf->type;
b481de9c
ZY		 6559
6560 spin_unlock_irqrestore(&priv->lock, flags);
6561
6562 mutex_lock(&priv->mutex);
864792e3
TW		 6563
6564 if (conf->mac_addr) {
e174961c 6565 IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
864792e3
TW		 6566 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6567 }
6568
5a66926a
ZY		 6569 if (iwl3945_is_ready(priv))
6570 iwl3945_set_mode(priv, conf->type);
b481de9c 6571
b481de9c
ZY		 6572 mutex_unlock(&priv->mutex);
6573
5a66926a 6574 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6575 return 0;
6576}
6577
6578/**
bb8c093b 6579 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY		 6580 *
6581 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6582 * be set inappropriately and the driver currently sets the hardware up to
6583 * use it whenever needed.
6584 */
e8975581 6585static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
b481de9c 6586{
bb8c093b
CH		 6587 struct iwl3945_priv *priv = hw->priv;
6588 const struct iwl3945_channel_info *ch_info;
e8975581 6589 struct ieee80211_conf *conf = &hw->conf;
b481de9c 6590 unsigned long flags;
76bb77e0 6591 int ret = 0;
b481de9c
ZY		 6592
6593 mutex_lock(&priv->mutex);
8318d78a 6594 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6595
bb8c093b 6596 if (!iwl3945_is_ready(priv)) {
b481de9c 6597 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY		 6598 ret = -EIO;
6599 goto out;
b481de9c
ZY		 6600 }
6601
bb8c093b 6602 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c 6603 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY		 6604 IWL_DEBUG_MAC80211("leave - scanning\n");
6605 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6606 mutex_unlock(&priv->mutex);
a0646470 6607 return 0;
b481de9c
ZY		 6608 }
6609
6610 spin_lock_irqsave(&priv->lock, flags);
6611
8318d78a
JB		 6612 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
6613 conf->channel->hw_value);
b481de9c 6614 if (!is_channel_valid(ch_info)) {
66b5004d 6615 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
8318d78a 6616 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY		 6617 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6618 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY		 6619 ret = -EINVAL;
6620 goto out;
b481de9c
ZY		 6621 }
6622
8318d78a 6623 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 6624
8318d78a 6625 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY		 6626
6627 /* The list of supported rates and rate mask can be different
6628 * for each phymode; since the phymode may have changed, reset
6629 * the rate mask to what mac80211 lists */
bb8c093b 6630 iwl3945_set_rate(priv);
b481de9c
ZY		 6631
6632 spin_unlock_irqrestore(&priv->lock, flags);
6633
6634#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6635 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6636 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 6637 goto out;
b481de9c
ZY		 6638 }
6639#endif
6640
bb8c093b 6641 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 6642
6643 if (!conf->radio_enabled) {
6644 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6645 goto out;
b481de9c
ZY		 6646 }
6647
bb8c093b 6648 if (iwl3945_is_rfkill(priv)) {
b481de9c 6649 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY		 6650 ret = -EIO;
6651 goto out;
b481de9c
ZY		 6652 }
6653
bb8c093b 6654 iwl3945_set_rate(priv);
b481de9c
ZY		 6655
6656 if (memcmp(&priv->active_rxon,
6657 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 6658 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6659 else
6660 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6661
6662 IWL_DEBUG_MAC80211("leave\n");
6663
76bb77e0 6664out:
a0646470 6665 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6666 mutex_unlock(&priv->mutex);
76bb77e0 6667 return ret;
b481de9c
ZY		 6668}
6669
bb8c093b 6670static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY		 6671{
6672 int rc = 0;
6673
d986bcd1 6674 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 6675 return;
6676
6677 /* The following should be done only at AP bring up */
5d1e2325 6678 if (!(iwl3945_is_associated(priv))) {
b481de9c
ZY		 6679
6680 /* RXON - unassoc (to set timing command) */
6681 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6682 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6683
6684 /* RXON Timing */
bb8c093b
CH		 6685 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6686 iwl3945_setup_rxon_timing(priv);
6687 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6688 sizeof(priv->rxon_timing), &priv->rxon_timing);
6689 if (rc)
6690 IWL_WARNING("REPLY_RXON_TIMING failed - "
6691 "Attempting to continue.\n");
6692
6693 /* FIXME: what should be the assoc_id for AP? */
6694 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6695 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6696 priv->staging_rxon.flags |=
6697 RXON_FLG_SHORT_PREAMBLE_MSK;
6698 else
6699 priv->staging_rxon.flags &=
6700 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6701
6702 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6703 if (priv->assoc_capability &
6704 WLAN_CAPABILITY_SHORT_SLOT_TIME)
6705 priv->staging_rxon.flags |=
6706 RXON_FLG_SHORT_SLOT_MSK;
6707 else
6708 priv->staging_rxon.flags &=
6709 ~RXON_FLG_SHORT_SLOT_MSK;
6710
05c914fe 6711 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 6712 priv->staging_rxon.flags &=
6713 ~RXON_FLG_SHORT_SLOT_MSK;
6714 }
6715 /* restore RXON assoc */
6716 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH		 6717 iwl3945_commit_rxon(priv);
6718 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 6719 }
bb8c093b 6720 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6721
6722 /* FIXME - we need to add code here to detect a totally new
6723 * configuration, reset the AP, unassoc, rxon timing, assoc,
6724 * clear sta table, add BCAST sta... */
6725}
6726
32bfd35d
JB		 6727static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6728 struct ieee80211_vif *vif,
b481de9c
ZY		 6729 struct ieee80211_if_conf *conf)
6730{
bb8c093b 6731 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6732 int rc;
6733
6734 if (conf == NULL)
6735 return -EIO;
6736
b716bb91
EG		 6737 if (priv->vif != vif) {
6738 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b716bb91
EG		 6739 return 0;
6740 }
6741
9d139c81 6742 /* handle this temporarily here */
05c914fe 6743 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
9d139c81
JB		 6744 conf->changed & IEEE80211_IFCC_BEACON) {
6745 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
6746 if (!beacon)
6747 return -ENOMEM;
9bdf5eca 6748 mutex_lock(&priv->mutex);
9d139c81 6749 rc = iwl3945_mac_beacon_update(hw, beacon);
9bdf5eca 6750 mutex_unlock(&priv->mutex);
9d139c81
JB		 6751 if (rc)
6752 return rc;
6753 }
6754
5a66926a
ZY		 6755 if (!iwl3945_is_alive(priv))
6756 return -EAGAIN;
6757
b481de9c
ZY		 6758 mutex_lock(&priv->mutex);
6759
b481de9c 6760 if (conf->bssid)
e174961c 6761 IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
b481de9c 6762
4150c572
JB		 6763/*
6764 * very dubious code was here; the probe filtering flag is never set:
6765 *
b481de9c
ZY		 6766 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6767 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6768 */
b481de9c 6769
05c914fe 6770 if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY		 6771 if (!conf->bssid) {
6772 conf->bssid = priv->mac_addr;
6773 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
e174961c
JB		 6774 IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
6775 conf->bssid);
b481de9c
ZY		 6776 }
6777 if (priv->ibss_beacon)
6778 dev_kfree_skb(priv->ibss_beacon);
6779
9d139c81 6780 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
b481de9c
ZY		 6781 }
6782
fde3571f
MA		 6783 if (iwl3945_is_rfkill(priv))
6784 goto done;
6785
b481de9c
ZY		 6786 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6787 !is_multicast_ether_addr(conf->bssid)) {
6788 /* If there is currently a HW scan going on in the background
6789 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6790 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 6791 IWL_WARNING("Aborted scan still in progress "
6792 "after 100ms\n");
6793 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6794 mutex_unlock(&priv->mutex);
6795 return -EAGAIN;
6796 }
6797 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
6798
6799 /* TODO: Audit driver for usage of these members and see
6800 * if mac80211 deprecates them (priv->bssid looks like it
6801 * shouldn't be there, but I haven't scanned the IBSS code
6802 * to verify) - jpk */
6803 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6804
05c914fe 6805 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b 6806 iwl3945_config_ap(priv);
b481de9c 6807 else {
bb8c093b 6808 rc = iwl3945_commit_rxon(priv);
05c914fe 6809 if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
bb8c093b 6810 iwl3945_add_station(priv,
556f8db7 6811 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY		 6812 }
6813
6814 } else {
bb8c093b 6815 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 6816 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6817 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6818 }
6819
fde3571f 6820 done:
b481de9c
ZY		 6821 IWL_DEBUG_MAC80211("leave\n");
6822 mutex_unlock(&priv->mutex);
6823
6824 return 0;
6825}
6826
bb8c093b 6827static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 6828 unsigned int changed_flags,
6829 unsigned int *total_flags,
6830 int mc_count, struct dev_addr_list *mc_list)
6831{
5ec03976 6832 struct iwl3945_priv *priv = hw->priv;
352bc8de 6833 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
25b3f57c 6834
352bc8de
ZY		 6835 IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
6836 changed_flags, *total_flags);
6837
6838 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
6839 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
6840 *filter_flags |= RXON_FILTER_PROMISC_MSK;
6841 else
6842 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
6843 }
6844 if (changed_flags & FIF_ALLMULTI) {
6845 if (*total_flags & FIF_ALLMULTI)
6846 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
6847 else
6848 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
6849 }
6850 if (changed_flags & FIF_CONTROL) {
6851 if (*total_flags & FIF_CONTROL)
6852 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
6853 else
6854 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
5ec03976 6855 }
352bc8de
ZY		 6856 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
6857 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
6858 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
6859 else
6860 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
6861 }
6862
6863 /* We avoid iwl_commit_rxon here to commit the new filter flags
6864 * since mac80211 will call ieee80211_hw_config immediately.
6865 * (mc_list is not supported at this time). Otherwise, we need to
6866 * queue a background iwl_commit_rxon work.
6867 */
6868
6869 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
25b3f57c 6870 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4150c572
JB		 6871}
6872
bb8c093b 6873static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6874 struct ieee80211_if_init_conf *conf)
6875{
bb8c093b 6876 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6877
6878 IWL_DEBUG_MAC80211("enter\n");
6879
6880 mutex_lock(&priv->mutex);
6ef89d0a 6881
fde3571f
MA		 6882 if (iwl3945_is_ready_rf(priv)) {
6883 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f
MA		 6884 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6885 iwl3945_commit_rxon(priv);
6886 }
32bfd35d
JB		 6887 if (priv->vif == conf->vif) {
6888 priv->vif = NULL;
b481de9c 6889 memset(priv->bssid, 0, ETH_ALEN);
b481de9c
ZY		 6890 }
6891 mutex_unlock(&priv->mutex);
6892
6893 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6894}
6895
cd56d331
AK		 6896#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
6897
6898static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
6899 struct ieee80211_vif *vif,
6900 struct ieee80211_bss_conf *bss_conf,
6901 u32 changes)
6902{
6903 struct iwl3945_priv *priv = hw->priv;
6904
6905 IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
6906
6907 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
6908 IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
6909 bss_conf->use_short_preamble);
6910 if (bss_conf->use_short_preamble)
6911 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6912 else
6913 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6914 }
6915
6916 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
6917 IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
6918 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
6919 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
6920 else
6921 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
6922 }
6923
6924 if (changes & BSS_CHANGED_ASSOC) {
6925 IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
6926 /* This should never happen as this function should
6927 * never be called from interrupt context. */
6928 if (WARN_ON_ONCE(in_interrupt()))
6929 return;
6930 if (bss_conf->assoc) {
6931 priv->assoc_id = bss_conf->aid;
6932 priv->beacon_int = bss_conf->beacon_int;
6933 priv->timestamp0 = bss_conf->timestamp & 0xFFFFFFFF;
6934 priv->timestamp1 = (bss_conf->timestamp >> 32) &
6935 0xFFFFFFFF;
6936 priv->assoc_capability = bss_conf->assoc_capability;
6937 priv->next_scan_jiffies = jiffies +
6938 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
6939 mutex_lock(&priv->mutex);
6940 iwl3945_post_associate(priv);
6941 mutex_unlock(&priv->mutex);
6942 } else {
6943 priv->assoc_id = 0;
6944 IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
6945 }
6946 } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
6947 IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
6948 iwl3945_send_rxon_assoc(priv);
6949 }
6950
6951}
6952
bb8c093b 6953static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 6954{
6955 int rc = 0;
6956 unsigned long flags;
bb8c093b 6957 struct iwl3945_priv *priv = hw->priv;
9387b7ca 6958 DECLARE_SSID_BUF(ssid_buf);
b481de9c
ZY		 6959
6960 IWL_DEBUG_MAC80211("enter\n");
6961
15e869d8 6962 mutex_lock(&priv->mutex);
b481de9c
ZY		 6963 spin_lock_irqsave(&priv->lock, flags);
6964
bb8c093b 6965 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 6966 rc = -EIO;
6967 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
6968 goto out_unlock;
6969 }
6970
7878a5a4
MA		 6971 /* we don't schedule scan within next_scan_jiffies period */
6972 if (priv->next_scan_jiffies &&
6973 time_after(priv->next_scan_jiffies, jiffies)) {
6974 rc = -EAGAIN;
6975 goto out_unlock;
6976 }
15dbf1b7
BM		 6977 /* if we just finished scan ask for delay for a broadcast scan */
6978 if ((len == 0) && priv->last_scan_jiffies &&
6979 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
6980 jiffies)) {
b481de9c
ZY		 6981 rc = -EAGAIN;
6982 goto out_unlock;
6983 }
6984 if (len) {
7878a5a4 6985 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
9387b7ca 6986 print_ssid(ssid_buf, ssid, len), (int)len);
b481de9c
ZY		 6987
6988 priv->one_direct_scan = 1;
6989 priv->direct_ssid_len = (u8)
6990 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
6991 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA		 6992 } else
6993 priv->one_direct_scan = 0;
b481de9c 6994
bb8c093b 6995 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY		 6996
6997 IWL_DEBUG_MAC80211("leave\n");
6998
6999out_unlock:
7000 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 7001 mutex_unlock(&priv->mutex);
b481de9c
ZY		 7002
7003 return rc;
7004}
7005
bb8c093b 7006static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 7007 const u8 *local_addr, const u8 *addr,
7008 struct ieee80211_key_conf *key)
7009{
bb8c093b 7010 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7011 int rc = 0;
7012 u8 sta_id;
7013
7014 IWL_DEBUG_MAC80211("enter\n");
7015
bb8c093b 7016 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY		 7017 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7018 return -EOPNOTSUPP;
7019 }
7020
7021 if (is_zero_ether_addr(addr))
7022 /* only support pairwise keys */
7023 return -EOPNOTSUPP;
7024
bb8c093b 7025 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7026 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 7027 IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
7028 addr);
b481de9c
ZY		 7029 return -EINVAL;
7030 }
7031
7032 mutex_lock(&priv->mutex);
7033
bb8c093b 7034 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7035
b481de9c
ZY		 7036 switch (cmd) {
7037 case SET_KEY:
bb8c093b 7038 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7039 if (!rc) {
bb8c093b
CH		 7040 iwl3945_set_rxon_hwcrypto(priv, 1);
7041 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7042 key->hw_key_idx = sta_id;
7043 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7044 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7045 }
7046 break;
7047 case DISABLE_KEY:
bb8c093b 7048 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7049 if (!rc) {
bb8c093b
CH		 7050 iwl3945_set_rxon_hwcrypto(priv, 0);
7051 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7052 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7053 }
7054 break;
7055 default:
7056 rc = -EINVAL;
7057 }
7058
7059 IWL_DEBUG_MAC80211("leave\n");
7060 mutex_unlock(&priv->mutex);
7061
7062 return rc;
7063}
7064
e100bb64 7065static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
b481de9c
ZY		 7066 const struct ieee80211_tx_queue_params *params)
7067{
bb8c093b 7068 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7069 unsigned long flags;
7070 int q;
b481de9c
ZY		 7071
7072 IWL_DEBUG_MAC80211("enter\n");
7073
bb8c093b 7074 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7075 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7076 return -EIO;
7077 }
7078
7079 if (queue >= AC_NUM) {
7080 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7081 return 0;
7082 }
7083
b481de9c
ZY		 7084 q = AC_NUM - 1 - queue;
7085
7086 spin_lock_irqsave(&priv->lock, flags);
7087
7088 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7089 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7090 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7091 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 7092 cpu_to_le16((params->txop * 32));
b481de9c
ZY		 7093
7094 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7095 priv->qos_data.qos_active = 1;
7096
7097 spin_unlock_irqrestore(&priv->lock, flags);
7098
7099 mutex_lock(&priv->mutex);
05c914fe 7100 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b
CH		 7101 iwl3945_activate_qos(priv, 1);
7102 else if (priv->assoc_id && iwl3945_is_associated(priv))
7103 iwl3945_activate_qos(priv, 0);
b481de9c
ZY		 7104
7105 mutex_unlock(&priv->mutex);
7106
b481de9c
ZY		 7107 IWL_DEBUG_MAC80211("leave\n");
7108 return 0;
7109}
7110
bb8c093b 7111static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7112 struct ieee80211_tx_queue_stats *stats)
7113{
bb8c093b 7114 struct iwl3945_priv *priv = hw->priv;
b481de9c 7115 int i, avail;
bb8c093b
CH		 7116 struct iwl3945_tx_queue *txq;
7117 struct iwl3945_queue *q;
b481de9c
ZY		 7118 unsigned long flags;
7119
7120 IWL_DEBUG_MAC80211("enter\n");
7121
bb8c093b 7122 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7123 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7124 return -EIO;
7125 }
7126
7127 spin_lock_irqsave(&priv->lock, flags);
7128
7129 for (i = 0; i < AC_NUM; i++) {
7130 txq = &priv->txq[i];
7131 q = &txq->q;
bb8c093b 7132 avail = iwl3945_queue_space(q);
b481de9c 7133
57ffc589
JB		 7134 stats[i].len = q->n_window - avail;
7135 stats[i].limit = q->n_window - q->high_mark;
7136 stats[i].count = q->n_window;
b481de9c
ZY		 7137
7138 }
7139 spin_unlock_irqrestore(&priv->lock, flags);
7140
7141 IWL_DEBUG_MAC80211("leave\n");
7142
7143 return 0;
7144}
7145
bb8c093b 7146static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7147 struct ieee80211_low_level_stats *stats)
7148{
7149 IWL_DEBUG_MAC80211("enter\n");
7150 IWL_DEBUG_MAC80211("leave\n");
7151
7152 return 0;
7153}
7154
bb8c093b 7155static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7156{
bb8c093b 7157 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7158 unsigned long flags;
7159
7160 mutex_lock(&priv->mutex);
7161 IWL_DEBUG_MAC80211("enter\n");
7162
bb8c093b 7163 iwl3945_reset_qos(priv);
292ae174 7164
b481de9c
ZY		 7165 spin_lock_irqsave(&priv->lock, flags);
7166 priv->assoc_id = 0;
7167 priv->assoc_capability = 0;
7168 priv->call_post_assoc_from_beacon = 0;
7169
7170 /* new association get rid of ibss beacon skb */
7171 if (priv->ibss_beacon)
7172 dev_kfree_skb(priv->ibss_beacon);
7173
7174 priv->ibss_beacon = NULL;
7175
7176 priv->beacon_int = priv->hw->conf.beacon_int;
7177 priv->timestamp1 = 0;
7178 priv->timestamp0 = 0;
05c914fe 7179 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
b481de9c
ZY		 7180 priv->beacon_int = 0;
7181
7182 spin_unlock_irqrestore(&priv->lock, flags);
7183
fde3571f
MA		 7184 if (!iwl3945_is_ready_rf(priv)) {
7185 IWL_DEBUG_MAC80211("leave - not ready\n");
7186 mutex_unlock(&priv->mutex);
7187 return;
7188 }
7189
15e869d8
MA		 7190 /* we are restarting association process
7191 * clear RXON_FILTER_ASSOC_MSK bit
7192 */
05c914fe 7193 if (priv->iw_mode != NL80211_IFTYPE_AP) {
bb8c093b 7194 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7195 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7196 iwl3945_commit_rxon(priv);
15e869d8
MA		 7197 }
7198
b481de9c 7199 /* Per mac80211.h: This is only used in IBSS mode... */
05c914fe 7200 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
15e869d8 7201
b481de9c
ZY		 7202 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7203 mutex_unlock(&priv->mutex);
7204 return;
b481de9c
ZY		 7205 }
7206
bb8c093b 7207 iwl3945_set_rate(priv);
b481de9c
ZY		 7208
7209 mutex_unlock(&priv->mutex);
7210
7211 IWL_DEBUG_MAC80211("leave\n");
7212
7213}
7214
e039fa4a 7215static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 7216{
bb8c093b 7217 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7218 unsigned long flags;
7219
b481de9c
ZY		 7220 IWL_DEBUG_MAC80211("enter\n");
7221
bb8c093b 7222 if (!iwl3945_is_ready_rf(priv)) {
b481de9c 7223 IWL_DEBUG_MAC80211("leave - RF not ready\n");
b481de9c
ZY		 7224 return -EIO;
7225 }
7226
05c914fe 7227 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
b481de9c 7228 IWL_DEBUG_MAC80211("leave - not IBSS\n");
b481de9c
ZY		 7229 return -EIO;
7230 }
7231
7232 spin_lock_irqsave(&priv->lock, flags);
7233
7234 if (priv->ibss_beacon)
7235 dev_kfree_skb(priv->ibss_beacon);
7236
7237 priv->ibss_beacon = skb;
7238
7239 priv->assoc_id = 0;
7240
7241 IWL_DEBUG_MAC80211("leave\n");
7242 spin_unlock_irqrestore(&priv->lock, flags);
7243
bb8c093b 7244 iwl3945_reset_qos(priv);
b481de9c 7245
dc4b1e7d 7246 iwl3945_post_associate(priv);
b481de9c 7247
b481de9c
ZY		 7248
7249 return 0;
7250}
7251
7252/*****************************************************************************
7253 *
7254 * sysfs attributes
7255 *
7256 *****************************************************************************/
7257
c8b0e6e1 7258#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 7259
7260/*
7261 * The following adds a new attribute to the sysfs representation
7262 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7263 * used for controlling the debug level.
7264 *
7265 * See the level definitions in iwl for details.
7266 */
7267
7268static ssize_t show_debug_level(struct device_driver *d, char *buf)
7269{
bb8c093b 7270 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY		 7271}
7272static ssize_t store_debug_level(struct device_driver *d,
7273 const char *buf, size_t count)
7274{
7275 char *p = (char *)buf;
7276 u32 val;
7277
7278 val = simple_strtoul(p, &p, 0);
7279 if (p == buf)
7280 printk(KERN_INFO DRV_NAME
7281 ": %s is not in hex or decimal form.\n", buf);
7282 else
bb8c093b 7283 iwl3945_debug_level = val;
b481de9c
ZY		 7284
7285 return strnlen(buf, count);
7286}
7287
7288static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7289 show_debug_level, store_debug_level);
7290
c8b0e6e1 7291#endif /* CONFIG_IWL3945_DEBUG */
b481de9c 7292
b481de9c
ZY		 7293static ssize_t show_temperature(struct device *d,
7294 struct device_attribute *attr, char *buf)
7295{
bb8c093b 7296 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7297
bb8c093b 7298 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7299 return -EAGAIN;
7300
bb8c093b 7301 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY		 7302}
7303
7304static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7305
b481de9c
ZY		 7306static ssize_t show_tx_power(struct device *d,
7307 struct device_attribute *attr, char *buf)
7308{
bb8c093b 7309 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7310 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7311}
7312
7313static ssize_t store_tx_power(struct device *d,
7314 struct device_attribute *attr,
7315 const char *buf, size_t count)
7316{
bb8c093b 7317 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7318 char *p = (char *)buf;
7319 u32 val;
7320
7321 val = simple_strtoul(p, &p, 10);
7322 if (p == buf)
7323 printk(KERN_INFO DRV_NAME
7324 ": %s is not in decimal form.\n", buf);
7325 else
bb8c093b 7326 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 7327
7328 return count;
7329}
7330
7331static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7332
7333static ssize_t show_flags(struct device *d,
7334 struct device_attribute *attr, char *buf)
7335{
bb8c093b 7336 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7337
7338 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7339}
7340
7341static ssize_t store_flags(struct device *d,
7342 struct device_attribute *attr,
7343 const char *buf, size_t count)
7344{
bb8c093b 7345 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7346 u32 flags = simple_strtoul(buf, NULL, 0);
7347
7348 mutex_lock(&priv->mutex);
7349 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7350 /* Cancel any currently running scans... */
bb8c093b 7351 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7352 IWL_WARNING("Could not cancel scan.\n");
7353 else {
7354 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7355 flags);
7356 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7357 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7358 }
7359 }
7360 mutex_unlock(&priv->mutex);
7361
7362 return count;
7363}
7364
7365static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7366
7367static ssize_t show_filter_flags(struct device *d,
7368 struct device_attribute *attr, char *buf)
7369{
bb8c093b 7370 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7371
7372 return sprintf(buf, "0x%04X\n",
7373 le32_to_cpu(priv->active_rxon.filter_flags));
7374}
7375
7376static ssize_t store_filter_flags(struct device *d,
7377 struct device_attribute *attr,
7378 const char *buf, size_t count)
7379{
bb8c093b 7380 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7381 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7382
7383 mutex_lock(&priv->mutex);
7384 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7385 /* Cancel any currently running scans... */
bb8c093b 7386 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7387 IWL_WARNING("Could not cancel scan.\n");
7388 else {
7389 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7390 "0x%04X\n", filter_flags);
7391 priv->staging_rxon.filter_flags =
7392 cpu_to_le32(filter_flags);
bb8c093b 7393 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7394 }
7395 }
7396 mutex_unlock(&priv->mutex);
7397
7398 return count;
7399}
7400
7401static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7402 store_filter_flags);
7403
c8b0e6e1 7404#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7405
7406static ssize_t show_measurement(struct device *d,
7407 struct device_attribute *attr, char *buf)
7408{
bb8c093b
CH		 7409 struct iwl3945_priv *priv = dev_get_drvdata(d);
7410 struct iwl3945_spectrum_notification measure_report;
b481de9c 7411 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 7412 u8 *data = (u8 *)&measure_report;
b481de9c
ZY		 7413 unsigned long flags;
7414
7415 spin_lock_irqsave(&priv->lock, flags);
7416 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7417 spin_unlock_irqrestore(&priv->lock, flags);
7418 return 0;
7419 }
7420 memcpy(&measure_report, &priv->measure_report, size);
7421 priv->measurement_status = 0;
7422 spin_unlock_irqrestore(&priv->lock, flags);
7423
7424 while (size && (PAGE_SIZE - len)) {
7425 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7426 PAGE_SIZE - len, 1);
7427 len = strlen(buf);
7428 if (PAGE_SIZE - len)
7429 buf[len++] = '\n';
7430
7431 ofs += 16;
7432 size -= min(size, 16U);
7433 }
7434
7435 return len;
7436}
7437
7438static ssize_t store_measurement(struct device *d,
7439 struct device_attribute *attr,
7440 const char *buf, size_t count)
7441{
bb8c093b 7442 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7443 struct ieee80211_measurement_params params = {
7444 .channel = le16_to_cpu(priv->active_rxon.channel),
7445 .start_time = cpu_to_le64(priv->last_tsf),
7446 .duration = cpu_to_le16(1),
7447 };
7448 u8 type = IWL_MEASURE_BASIC;
7449 u8 buffer[32];
7450 u8 channel;
7451
7452 if (count) {
7453 char *p = buffer;
7454 strncpy(buffer, buf, min(sizeof(buffer), count));
7455 channel = simple_strtoul(p, NULL, 0);
7456 if (channel)
7457 params.channel = channel;
7458
7459 p = buffer;
7460 while (*p && *p != ' ')
7461 p++;
7462 if (*p)
7463 type = simple_strtoul(p + 1, NULL, 0);
7464 }
7465
7466 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7467 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7468 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY		 7469
7470 return count;
7471}
7472
7473static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7474 show_measurement, store_measurement);
c8b0e6e1 7475#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 7476
b481de9c
ZY		 7477static ssize_t store_retry_rate(struct device *d,
7478 struct device_attribute *attr,
7479 const char *buf, size_t count)
7480{
bb8c093b 7481 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7482
7483 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7484 if (priv->retry_rate <= 0)
7485 priv->retry_rate = 1;
7486
7487 return count;
7488}
7489
7490static ssize_t show_retry_rate(struct device *d,
7491 struct device_attribute *attr, char *buf)
7492{
bb8c093b 7493 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7494 return sprintf(buf, "%d", priv->retry_rate);
7495}
7496
7497static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7498 store_retry_rate);
7499
7500static ssize_t store_power_level(struct device *d,
7501 struct device_attribute *attr,
7502 const char *buf, size_t count)
7503{
bb8c093b 7504 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7505 int rc;
7506 int mode;
7507
7508 mode = simple_strtoul(buf, NULL, 0);
7509 mutex_lock(&priv->mutex);
7510
bb8c093b 7511 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 7512 rc = -EAGAIN;
7513 goto out;
7514 }
7515
7516 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
7517 mode = IWL_POWER_AC;
7518 else
7519 mode |= IWL_POWER_ENABLED;
7520
7521 if (mode != priv->power_mode) {
bb8c093b 7522 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 7523 if (rc) {
7524 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7525 goto out;
7526 }
7527 priv->power_mode = mode;
7528 }
7529
7530 rc = count;
7531
7532 out:
7533 mutex_unlock(&priv->mutex);
7534 return rc;
7535}
7536
7537#define MAX_WX_STRING 80
7538
7539/* Values are in microsecond */
7540static const s32 timeout_duration[] = {
7541 350000,
7542 250000,
7543 75000,
7544 37000,
7545 25000,
7546};
7547static const s32 period_duration[] = {
7548 400000,
7549 700000,
7550 1000000,
7551 1000000,
7552 1000000
7553};
7554
7555static ssize_t show_power_level(struct device *d,
7556 struct device_attribute *attr, char *buf)
7557{
bb8c093b 7558 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7559 int level = IWL_POWER_LEVEL(priv->power_mode);
7560 char *p = buf;
7561
7562 p += sprintf(p, "%d ", level);
7563 switch (level) {
7564 case IWL_POWER_MODE_CAM:
7565 case IWL_POWER_AC:
7566 p += sprintf(p, "(AC)");
7567 break;
7568 case IWL_POWER_BATTERY:
7569 p += sprintf(p, "(BATTERY)");
7570 break;
7571 default:
7572 p += sprintf(p,
7573 "(Timeout %dms, Period %dms)",
7574 timeout_duration[level - 1] / 1000,
7575 period_duration[level - 1] / 1000);
7576 }
7577
7578 if (!(priv->power_mode & IWL_POWER_ENABLED))
7579 p += sprintf(p, " OFF\n");
7580 else
7581 p += sprintf(p, " \n");
7582
3ac7f146 7583 return p - buf + 1;
b481de9c
ZY		 7584
7585}
7586
7587static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7588 store_power_level);
7589
7590static ssize_t show_channels(struct device *d,
7591 struct device_attribute *attr, char *buf)
7592{
8318d78a
JB		 7593 /* all this shit doesn't belong into sysfs anyway */
7594 return 0;
b481de9c
ZY		 7595}
7596
7597static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7598
7599static ssize_t show_statistics(struct device *d,
7600 struct device_attribute *attr, char *buf)
7601{
bb8c093b
CH		 7602 struct iwl3945_priv *priv = dev_get_drvdata(d);
7603 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 7604 u32 len = 0, ofs = 0;
3ac7f146 7605 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY		 7606 int rc = 0;
7607
bb8c093b 7608 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7609 return -EAGAIN;
7610
7611 mutex_lock(&priv->mutex);
bb8c093b 7612 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY		 7613 mutex_unlock(&priv->mutex);
7614
7615 if (rc) {
7616 len = sprintf(buf,
7617 "Error sending statistics request: 0x%08X\n", rc);
7618 return len;
7619 }
7620
7621 while (size && (PAGE_SIZE - len)) {
7622 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7623 PAGE_SIZE - len, 1);
7624 len = strlen(buf);
7625 if (PAGE_SIZE - len)
7626 buf[len++] = '\n';
7627
7628 ofs += 16;
7629 size -= min(size, 16U);
7630 }
7631
7632 return len;
7633}
7634
7635static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7636
7637static ssize_t show_antenna(struct device *d,
7638 struct device_attribute *attr, char *buf)
7639{
bb8c093b 7640 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 7641
bb8c093b 7642 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7643 return -EAGAIN;
7644
7645 return sprintf(buf, "%d\n", priv->antenna);
7646}
7647
7648static ssize_t store_antenna(struct device *d,
7649 struct device_attribute *attr,
7650 const char *buf, size_t count)
7651{
7652 int ant;
bb8c093b 7653 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7654
7655 if (count == 0)
7656 return 0;
7657
7658 if (sscanf(buf, "%1i", &ant) != 1) {
7659 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7660 return count;
7661 }
7662
7663 if ((ant >= 0) && (ant <= 2)) {
7664 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7665 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY		 7666 } else
7667 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7668
7669
7670 return count;
7671}
7672
7673static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7674
7675static ssize_t show_status(struct device *d,
7676 struct device_attribute *attr, char *buf)
7677{
bb8c093b
CH		 7678 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
7679 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7680 return -EAGAIN;
7681 return sprintf(buf, "0x%08x\n", (int)priv->status);
7682}
7683
7684static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7685
7686static ssize_t dump_error_log(struct device *d,
7687 struct device_attribute *attr,
7688 const char *buf, size_t count)
7689{
7690 char *p = (char *)buf;
7691
7692 if (p[0] == '1')
bb8c093b 7693 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7694
7695 return strnlen(buf, count);
7696}
7697
7698static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7699
7700static ssize_t dump_event_log(struct device *d,
7701 struct device_attribute *attr,
7702 const char *buf, size_t count)
7703{
7704 char *p = (char *)buf;
7705
7706 if (p[0] == '1')
bb8c093b 7707 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7708
7709 return strnlen(buf, count);
7710}
7711
7712static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7713
7714/*****************************************************************************
7715 *
a96a27f9 7716 * driver setup and tear down
b481de9c
ZY		 7717 *
7718 *****************************************************************************/
7719
bb8c093b 7720static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 7721{
7722 priv->workqueue = create_workqueue(DRV_NAME);
7723
7724 init_waitqueue_head(&priv->wait_command_queue);
7725
bb8c093b
CH		 7726 INIT_WORK(&priv->up, iwl3945_bg_up);
7727 INIT_WORK(&priv->restart, iwl3945_bg_restart);
7728 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
7729 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
7730 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
7731 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7732 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7733 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH		 7734 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7735 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
7736 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
7737
7738 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY		 7739
7740 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7741 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 7742}
7743
bb8c093b 7744static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 7745{
bb8c093b 7746 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 7747
e47eb6ad 7748 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 7749 cancel_delayed_work(&priv->scan_check);
7750 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY		 7751 cancel_work_sync(&priv->beacon_update);
7752}
7753
bb8c093b 7754static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY		 7755 &dev_attr_antenna.attr,
7756 &dev_attr_channels.attr,
7757 &dev_attr_dump_errors.attr,
7758 &dev_attr_dump_events.attr,
7759 &dev_attr_flags.attr,
7760 &dev_attr_filter_flags.attr,
c8b0e6e1 7761#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7762 &dev_attr_measurement.attr,
7763#endif
7764 &dev_attr_power_level.attr,
b481de9c 7765 &dev_attr_retry_rate.attr,
b481de9c
ZY		 7766 &dev_attr_statistics.attr,
7767 &dev_attr_status.attr,
7768 &dev_attr_temperature.attr,
b481de9c
ZY		 7769 &dev_attr_tx_power.attr,
7770
7771 NULL
7772};
7773
bb8c093b 7774static struct attribute_group iwl3945_attribute_group = {
b481de9c 7775 .name = NULL, /* put in device directory */
bb8c093b 7776 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY		 7777};
7778
bb8c093b
CH		 7779static struct ieee80211_ops iwl3945_hw_ops = {
7780 .tx = iwl3945_mac_tx,
7781 .start = iwl3945_mac_start,
7782 .stop = iwl3945_mac_stop,
7783 .add_interface = iwl3945_mac_add_interface,
7784 .remove_interface = iwl3945_mac_remove_interface,
7785 .config = iwl3945_mac_config,
7786 .config_interface = iwl3945_mac_config_interface,
7787 .configure_filter = iwl3945_configure_filter,
7788 .set_key = iwl3945_mac_set_key,
7789 .get_stats = iwl3945_mac_get_stats,
7790 .get_tx_stats = iwl3945_mac_get_tx_stats,
7791 .conf_tx = iwl3945_mac_conf_tx,
bb8c093b 7792 .reset_tsf = iwl3945_mac_reset_tsf,
cd56d331 7793 .bss_info_changed = iwl3945_bss_info_changed,
bb8c093b 7794 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY		 7795};
7796
bb8c093b 7797static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 7798{
7799 int err = 0;
bb8c093b 7800 struct iwl3945_priv *priv;
b481de9c 7801 struct ieee80211_hw *hw;
82b9a121 7802 struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
0359facc 7803 unsigned long flags;
b481de9c 7804
cee53ddb
KA		 7805 /***********************
7806 * 1. Allocating HW data
7807 * ********************/
7808
6440adb5
CB		 7809 /* Disabling hardware scan means that mac80211 will perform scans
7810 * "the hard way", rather than using device's scan. */
bb8c093b 7811 if (iwl3945_param_disable_hw_scan) {
b481de9c 7812 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 7813 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY		 7814 }
7815
dfe7d458 7816 if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
bb8c093b 7817 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c 7818 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
dfe7d458 7819 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
b481de9c
ZY		 7820 err = -EINVAL;
7821 goto out;
7822 }
7823
7824 /* mac80211 allocates memory for this device instance, including
7825 * space for this driver's private structure */
bb8c093b 7826 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY		 7827 if (hw == NULL) {
7828 IWL_ERROR("Can not allocate network device\n");
7829 err = -ENOMEM;
7830 goto out;
7831 }
b481de9c 7832
cee53ddb 7833 SET_IEEE80211_DEV(hw, &pdev->dev);
f51359a8 7834
b481de9c
ZY		 7835 priv = hw->priv;
7836 priv->hw = hw;
b481de9c 7837 priv->pci_dev = pdev;
82b9a121 7838 priv->cfg = cfg;
6440adb5 7839
cee53ddb
KA		 7840 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
7841 hw->rate_control_algorithm = "iwl-3945-rs";
7842 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
7843
6440adb5 7844 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 7845 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 7846#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 7847 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY		 7848 atomic_set(&priv->restrict_refcnt, 0);
7849#endif
b481de9c 7850
566bfe5a 7851 /* Tell mac80211 our characteristics */
605a0bd6 7852 hw->flags = IEEE80211_HW_SIGNAL_DBM |
566bfe5a 7853 IEEE80211_HW_NOISE_DBM;
b481de9c 7854
f59ac048 7855 hw->wiphy->interface_modes =
f59ac048
LR		 7856 BIT(NL80211_IFTYPE_STATION) |
7857 BIT(NL80211_IFTYPE_ADHOC);
7858
ea4a82dc
LR		 7859 hw->wiphy->fw_handles_regulatory = true;
7860
6440adb5 7861 /* 4 EDCA QOS priorities */
b481de9c
ZY		 7862 hw->queues = 4;
7863
cee53ddb
KA		 7864 /***************************
7865 * 2. Initializing PCI bus
7866 * *************************/
b481de9c
ZY		 7867 if (pci_enable_device(pdev)) {
7868 err = -ENODEV;
7869 goto out_ieee80211_free_hw;
7870 }
7871
7872 pci_set_master(pdev);
7873
b481de9c
ZY		 7874 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
7875 if (!err)
7876 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
7877 if (err) {
7878 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
7879 goto out_pci_disable_device;
7880 }
7881
7882 pci_set_drvdata(pdev, priv);
7883 err = pci_request_regions(pdev, DRV_NAME);
7884 if (err)
7885 goto out_pci_disable_device;
6440adb5 7886
cee53ddb
KA		 7887 /***********************
7888 * 3. Read REV Register
7889 * ********************/
b481de9c
ZY		 7890 priv->hw_base = pci_iomap(pdev, 0, 0);
7891 if (!priv->hw_base) {
7892 err = -ENODEV;
7893 goto out_pci_release_regions;
7894 }
7895
7896 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
7897 (unsigned long long) pci_resource_len(pdev, 0));
7898 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
7899
cee53ddb
KA		 7900 /* We disable the RETRY_TIMEOUT register (0x41) to keep
7901 * PCI Tx retries from interfering with C3 CPU state */
7902 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 7903
cee53ddb
KA		 7904 /* nic init */
7905 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
7906 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
b481de9c 7907
cee53ddb 7908 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
73d7b5ac
ZY		 7909 err = iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL,
7910 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
cee53ddb
KA		 7911 if (err < 0) {
7912 IWL_DEBUG_INFO("Failed to init the card\n");
7913 goto out_remove_sysfs;
7914 }
b481de9c 7915
cee53ddb
KA		 7916 /***********************
7917 * 4. Read EEPROM
7918 * ********************/
7919 /* Read the EEPROM */
7920 err = iwl3945_eeprom_init(priv);
7921 if (err) {
7922 IWL_ERROR("Unable to init EEPROM\n");
7923 goto out_remove_sysfs;
7924 }
7925 /* MAC Address location in EEPROM same for 3945/4965 */
7926 get_eeprom_mac(priv, priv->mac_addr);
7927 IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
7928 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 7929
cee53ddb
KA		 7930 /***********************
7931 * 5. Setup HW Constants
7932 * ********************/
b481de9c 7933 /* Device-specific setup */
bb8c093b 7934 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c 7935 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY		 7936 goto out_iounmap;
7937 }
7938
cee53ddb
KA		 7939 /***********************
7940 * 6. Setup priv
7941 * ********************/
7942 priv->retry_rate = 1;
7943 priv->ibss_beacon = NULL;
7944
7945 spin_lock_init(&priv->lock);
7946 spin_lock_init(&priv->power_data.lock);
7947 spin_lock_init(&priv->sta_lock);
7948 spin_lock_init(&priv->hcmd_lock);
7949
7950 INIT_LIST_HEAD(&priv->free_frames);
7951 mutex_init(&priv->mutex);
7952
7953 /* Clear the driver's (not device's) station table */
7954 iwl3945_clear_stations_table(priv);
7955
7956 priv->data_retry_limit = -1;
7957 priv->ieee_channels = NULL;
7958 priv->ieee_rates = NULL;
7959 priv->band = IEEE80211_BAND_2GHZ;
7960
7961 priv->iw_mode = NL80211_IFTYPE_STATION;
7962
bb8c093b 7963 iwl3945_reset_qos(priv);
b481de9c
ZY		 7964
7965 priv->qos_data.qos_active = 0;
7966 priv->qos_data.qos_cap.val = 0;
b481de9c 7967
b481de9c
ZY		 7968
7969 priv->rates_mask = IWL_RATES_MASK;
7970 /* If power management is turned on, default to AC mode */
7971 priv->power_mode = IWL_POWER_AC;
7972 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
7973
cee53ddb 7974 err = iwl3945_init_channel_map(priv);
b481de9c 7975 if (err) {
cee53ddb 7976 IWL_ERROR("initializing regulatory failed: %d\n", err);
b481de9c
ZY		 7977 goto out_release_irq;
7978 }
7979
cee53ddb 7980 err = iwl3945_init_geos(priv);
b481de9c 7981 if (err) {
cee53ddb
KA		 7982 IWL_ERROR("initializing geos failed: %d\n", err);
7983 goto out_free_channel_map;
b481de9c
ZY		 7984 }
7985
cee53ddb
KA		 7986 printk(KERN_INFO DRV_NAME
7987 ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
7988
7989 /***********************************
7990 * 7. Initialize Module Parameters
7991 * **********************************/
7992
7993 /* Initialize module parameter values here */
7994 /* Disable radio (SW RF KILL) via parameter when loading driver */
7995 if (iwl3945_param_disable) {
7996 set_bit(STATUS_RF_KILL_SW, &priv->status);
7997 IWL_DEBUG_INFO("Radio disabled.\n");
849e0dce
RC		 7998 }
7999
cee53ddb
KA		 8000
8001 /***********************
8002 * 8. Setup Services
8003 * ********************/
8004
8005 spin_lock_irqsave(&priv->lock, flags);
8006 iwl3945_disable_interrupts(priv);
8007 spin_unlock_irqrestore(&priv->lock, flags);
8008
8009 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 8010 if (err) {
cee53ddb
KA		 8011 IWL_ERROR("failed to create sysfs device attributes\n");
8012 goto out_free_geos;
849e0dce 8013 }
849e0dce 8014
cee53ddb
KA		 8015 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
8016 iwl3945_setup_deferred_work(priv);
8017 iwl3945_setup_rx_handlers(priv);
8018
8019 /***********************
8020 * 9. Conclude
8021 * ********************/
8022 pci_save_state(pdev);
8023 pci_disable_device(pdev);
8024
8025 /*********************************
8026 * 10. Setup and Register mac80211
8027 * *******************************/
8028
5a66926a
ZY		 8029 err = ieee80211_register_hw(priv->hw);
8030 if (err) {
8031 IWL_ERROR("Failed to register network device (error %d)\n", err);
cee53ddb 8032 goto out_remove_sysfs;
5a66926a 8033 }
b481de9c 8034
5a66926a
ZY		 8035 priv->hw->conf.beacon_int = 100;
8036 priv->mac80211_registered = 1;
cee53ddb 8037
b481de9c 8038
ebef2008
AK		 8039 err = iwl3945_rfkill_init(priv);
8040 if (err)
8041 IWL_ERROR("Unable to initialize RFKILL system. "
8042 "Ignoring error: %d\n", err);
8043
b481de9c
ZY		 8044 return 0;
8045
cee53ddb
KA		 8046 out_remove_sysfs:
8047 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce
RC		 8048 out_free_geos:
8049 iwl3945_free_geos(priv);
8050 out_free_channel_map:
8051 iwl3945_free_channel_map(priv);
cee53ddb 8052
b481de9c
ZY		 8053
8054 out_release_irq:
b481de9c
ZY		 8055 destroy_workqueue(priv->workqueue);
8056 priv->workqueue = NULL;
bb8c093b 8057 iwl3945_unset_hw_setting(priv);
b481de9c
ZY		 8058
8059 out_iounmap:
8060 pci_iounmap(pdev, priv->hw_base);
8061 out_pci_release_regions:
8062 pci_release_regions(pdev);
8063 out_pci_disable_device:
8064 pci_disable_device(pdev);
8065 pci_set_drvdata(pdev, NULL);
8066 out_ieee80211_free_hw:
8067 ieee80211_free_hw(priv->hw);
8068 out:
8069 return err;
8070}
8071
c83dbf68 8072static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8073{
bb8c093b 8074 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
0359facc 8075 unsigned long flags;
b481de9c
ZY		 8076
8077 if (!priv)
8078 return;
8079
8080 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8081
b481de9c 8082 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8083
bb8c093b 8084 iwl3945_down(priv);
b481de9c 8085
0359facc
MA		 8086 /* make sure we flush any pending irq or
8087 * tasklet for the driver
8088 */
8089 spin_lock_irqsave(&priv->lock, flags);
8090 iwl3945_disable_interrupts(priv);
8091 spin_unlock_irqrestore(&priv->lock, flags);
8092
8093 iwl_synchronize_irq(priv);
8094
bb8c093b 8095 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8096
ebef2008 8097 iwl3945_rfkill_unregister(priv);
bb8c093b 8098 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 8099
8100 if (priv->rxq.bd)
bb8c093b
CH		 8101 iwl3945_rx_queue_free(priv, &priv->rxq);
8102 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8103
bb8c093b
CH		 8104 iwl3945_unset_hw_setting(priv);
8105 iwl3945_clear_stations_table(priv);
b481de9c 8106
3ac7f146 8107 if (priv->mac80211_registered)
b481de9c 8108 ieee80211_unregister_hw(priv->hw);
b481de9c 8109
6ef89d0a
MA		 8110 /*netif_stop_queue(dev); */
8111 flush_workqueue(priv->workqueue);
8112
bb8c093b 8113 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY		 8114 * priv->workqueue... so we can't take down the workqueue
8115 * until now... */
8116 destroy_workqueue(priv->workqueue);
8117 priv->workqueue = NULL;
8118
b481de9c
ZY		 8119 pci_iounmap(pdev, priv->hw_base);
8120 pci_release_regions(pdev);
8121 pci_disable_device(pdev);
8122 pci_set_drvdata(pdev, NULL);
8123
849e0dce
RC		 8124 iwl3945_free_channel_map(priv);
8125 iwl3945_free_geos(priv);
261415f7 8126 kfree(priv->scan);
b481de9c
ZY		 8127 if (priv->ibss_beacon)
8128 dev_kfree_skb(priv->ibss_beacon);
8129
8130 ieee80211_free_hw(priv->hw);
8131}
8132
8133#ifdef CONFIG_PM
8134
bb8c093b 8135static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8136{
bb8c093b 8137 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8138
e655b9f0
ZY		 8139 if (priv->is_open) {
8140 set_bit(STATUS_IN_SUSPEND, &priv->status);
8141 iwl3945_mac_stop(priv->hw);
8142 priv->is_open = 1;
8143 }
b481de9c 8144
b481de9c
ZY		 8145 pci_set_power_state(pdev, PCI_D3hot);
8146
b481de9c
ZY		 8147 return 0;
8148}
8149
bb8c093b 8150static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8151{
bb8c093b 8152 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8153
b481de9c 8154 pci_set_power_state(pdev, PCI_D0);
b481de9c 8155
e655b9f0
ZY		 8156 if (priv->is_open)
8157 iwl3945_mac_start(priv->hw);
b481de9c 8158
e655b9f0 8159 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 8160 return 0;
8161}
8162
8163#endif /* CONFIG_PM */
8164
ebef2008 8165/*************** RFKILL FUNCTIONS **********/
80fcc9e2 8166#ifdef CONFIG_IWL3945_RFKILL
ebef2008
AK		 8167/* software rf-kill from user */
8168static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
8169{
8170 struct iwl3945_priv *priv = data;
8171 int err = 0;
8172
80fcc9e2 8173 if (!priv->rfkill)
ebef2008
AK		 8174 return 0;
8175
8176 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
8177 return 0;
8178
a96a27f9 8179 IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
ebef2008
AK		 8180 mutex_lock(&priv->mutex);
8181
8182 switch (state) {
acdfe9b4 8183 case RFKILL_STATE_UNBLOCKED:
80fcc9e2 8184 if (iwl3945_is_rfkill_hw(priv)) {
ebef2008 8185 err = -EBUSY;
80fcc9e2
AG		 8186 goto out_unlock;
8187 }
8188 iwl3945_radio_kill_sw(priv, 0);
ebef2008 8189 break;
acdfe9b4 8190 case RFKILL_STATE_SOFT_BLOCKED:
ebef2008 8191 iwl3945_radio_kill_sw(priv, 1);
ebef2008 8192 break;
acdfe9b4 8193 default:
a96a27f9 8194 IWL_WARNING("we received unexpected RFKILL state %d\n", state);
acdfe9b4 8195 break;
ebef2008 8196 }
80fcc9e2 8197out_unlock:
ebef2008
AK		 8198 mutex_unlock(&priv->mutex);
8199
8200 return err;
8201}
8202
8203int iwl3945_rfkill_init(struct iwl3945_priv *priv)
8204{
8205 struct device *device = wiphy_dev(priv->hw->wiphy);
8206 int ret = 0;
8207
8208 BUG_ON(device == NULL);
8209
8210 IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
80fcc9e2
AG		 8211 priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
8212 if (!priv->rfkill) {
ebef2008
AK		 8213 IWL_ERROR("Unable to allocate rfkill device.\n");
8214 ret = -ENOMEM;
8215 goto error;
8216 }
8217
80fcc9e2
AG		 8218 priv->rfkill->name = priv->cfg->name;
8219 priv->rfkill->data = priv;
8220 priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
8221 priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
8222 priv->rfkill->user_claim_unsupported = 1;
ebef2008 8223
80fcc9e2
AG		 8224 priv->rfkill->dev.class->suspend = NULL;
8225 priv->rfkill->dev.class->resume = NULL;
ebef2008 8226
80fcc9e2 8227 ret = rfkill_register(priv->rfkill);
ebef2008
AK		 8228 if (ret) {
8229 IWL_ERROR("Unable to register rfkill: %d\n", ret);
80fcc9e2 8230 goto freed_rfkill;
ebef2008
AK		 8231 }
8232
8233 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8234 return ret;
8235
ebef2008 8236freed_rfkill:
80fcc9e2
AG		 8237 if (priv->rfkill != NULL)
8238 rfkill_free(priv->rfkill);
8239 priv->rfkill = NULL;
ebef2008
AK		 8240
8241error:
8242 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8243 return ret;
8244}
8245
8246void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
8247{
80fcc9e2
AG		 8248 if (priv->rfkill)
8249 rfkill_unregister(priv->rfkill);
ebef2008 8250
80fcc9e2 8251 priv->rfkill = NULL;
ebef2008
AK		 8252}
8253
8254/* set rf-kill to the right state. */
8255void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
8256{
8257
80fcc9e2
AG		 8258 if (!priv->rfkill)
8259 return;
8260
8261 if (iwl3945_is_rfkill_hw(priv)) {
8262 rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
ebef2008 8263 return;
80fcc9e2 8264 }
ebef2008 8265
80fcc9e2
AG		 8266 if (!iwl3945_is_rfkill_sw(priv))
8267 rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
ebef2008 8268 else
80fcc9e2 8269 rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
ebef2008
AK		 8270}
8271#endif
8272
b481de9c
ZY		 8273/*****************************************************************************
8274 *
8275 * driver and module entry point
8276 *
8277 *****************************************************************************/
8278
bb8c093b 8279static struct pci_driver iwl3945_driver = {
b481de9c 8280 .name = DRV_NAME,
bb8c093b
CH		 8281 .id_table = iwl3945_hw_card_ids,
8282 .probe = iwl3945_pci_probe,
8283 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8284#ifdef CONFIG_PM
bb8c093b
CH		 8285 .suspend = iwl3945_pci_suspend,
8286 .resume = iwl3945_pci_resume,
b481de9c
ZY		 8287#endif
8288};
8289
bb8c093b 8290static int __init iwl3945_init(void)
b481de9c
ZY		 8291{
8292
8293 int ret;
8294 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8295 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC		 8296
8297 ret = iwl3945_rate_control_register();
8298 if (ret) {
8299 IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
8300 return ret;
8301 }
8302
bb8c093b 8303 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY		 8304 if (ret) {
8305 IWL_ERROR("Unable to initialize PCI module\n");
897e1cf2 8306 goto error_register;
b481de9c 8307 }
c8b0e6e1 8308#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8309 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY		 8310 if (ret) {
8311 IWL_ERROR("Unable to create driver sysfs file\n");
897e1cf2 8312 goto error_debug;
b481de9c
ZY		 8313 }
8314#endif
8315
8316 return ret;
897e1cf2
RC		 8317
8318#ifdef CONFIG_IWL3945_DEBUG
8319error_debug:
8320 pci_unregister_driver(&iwl3945_driver);
8321#endif
8322error_register:
8323 iwl3945_rate_control_unregister();
8324 return ret;
b481de9c
ZY		 8325}
8326
bb8c093b 8327static void __exit iwl3945_exit(void)
b481de9c 8328{
c8b0e6e1 8329#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8330 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8331#endif
bb8c093b 8332 pci_unregister_driver(&iwl3945_driver);
897e1cf2 8333 iwl3945_rate_control_unregister();
b481de9c
ZY		 8334}
8335
a0987a8d 8336MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 8337
bb8c093b 8338module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8339MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8340module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8341MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8342module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY		 8343MODULE_PARM_DESC(hwcrypto,
8344 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 8345module_param_named(debug, iwl3945_param_debug, int, 0444);
b481de9c 8346MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8347module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY		 8348MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8349
bb8c093b 8350module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY		 8351MODULE_PARM_DESC(queues_num, "number of hw queues.");
8352
bb8c093b
CH		 8353module_exit(iwl3945_exit);
8354module_init(iwl3945_init);
Linux kernel - Deliverables
This page took 0.766205 seconds and 5 git commands to generate.