iwlwifi: make iwl-power.c more readable
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
7e272fcf 44#include <net/lib80211.h>
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45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
a3139c59
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49#define DRV_NAME "iwl3945"
50
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51#include "iwl-fh.h"
52#include "iwl-3945-fh.h"
600c0e11 53#include "iwl-commands.h"
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54#include "iwl-3945.h"
55#include "iwl-helpers.h"
5747d47f 56#include "iwl-core.h"
d20b3c65 57#include "iwl-dev.h"
b481de9c 58
4a8a4322 59static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
188cf6c7 60 struct iwl_tx_queue *txq);
416e1438 61
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62/*
63 * module name, copyright, version, etc.
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64 */
65
66#define DRV_DESCRIPTION \
67"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
68
c8b0e6e1 69#ifdef CONFIG_IWL3945_DEBUG
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70#define VD "d"
71#else
72#define VD
73#endif
74
c8b0e6e1 75#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
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76#define VS "s"
77#else
78#define VS
79#endif
80
eaa686c3 81#define IWL39_VERSION "1.2.26k" VD VS
01f8162a 82#define DRV_COPYRIGHT "Copyright(c) 2003-2009 Intel Corporation"
a7b75207 83#define DRV_AUTHOR "<ilw@linux.intel.com>"
eaa686c3 84#define DRV_VERSION IWL39_VERSION
b481de9c 85
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86
87MODULE_DESCRIPTION(DRV_DESCRIPTION);
88MODULE_VERSION(DRV_VERSION);
a7b75207 89MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
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90MODULE_LICENSE("GPL");
91
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92 /* module parameters */
93struct iwl_mod_params iwl3945_mod_params = {
94 .num_of_queues = IWL39_MAX_NUM_QUEUES,
9c74d9fb 95 .sw_crypto = 1,
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96 /* the rest are 0 by default */
97};
98
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99/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
100 * DMA services
101 *
102 * Theory of operation
103 *
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104 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
105 * of buffer descriptors, each of which points to one or more data buffers for
106 * the device to read from or fill. Driver and device exchange status of each
107 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
108 * entries in each circular buffer, to protect against confusing empty and full
109 * queue states.
110 *
111 * The device reads or writes the data in the queues via the device's several
112 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
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113 *
114 * For Tx queue, there are low mark and high mark limits. If, after queuing
115 * the packet for Tx, free space become < low mark, Tx queue stopped. When
116 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
117 * Tx queue resumed.
118 *
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119 * The 3945 operates with six queues: One receive queue, one transmit queue
120 * (#4) for sending commands to the device firmware, and four transmit queues
121 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
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122 ***************************************************/
123
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124/**
125 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
126 */
4a8a4322 127static int iwl3945_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
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128 int count, int slots_num, u32 id)
129{
130 q->n_bd = count;
131 q->n_window = slots_num;
132 q->id = id;
133
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134 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
135 * and iwl_queue_dec_wrap are broken. */
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136 BUG_ON(!is_power_of_2(count));
137
138 /* slots_num must be power-of-two size, otherwise
139 * get_cmd_index is broken. */
140 BUG_ON(!is_power_of_2(slots_num));
141
142 q->low_mark = q->n_window / 4;
143 if (q->low_mark < 4)
144 q->low_mark = 4;
145
146 q->high_mark = q->n_window / 8;
147 if (q->high_mark < 2)
148 q->high_mark = 2;
149
fc4b6853 150 q->write_ptr = q->read_ptr = 0;
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151
152 return 0;
153}
154
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155/**
156 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
157 */
4a8a4322 158static int iwl3945_tx_queue_alloc(struct iwl_priv *priv,
188cf6c7 159 struct iwl_tx_queue *txq, u32 id)
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160{
161 struct pci_dev *dev = priv->pci_dev;
162
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163 /* Driver private data, only for Tx (not command) queues,
164 * not shared with device. */
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165 if (id != IWL_CMD_QUEUE_NUM) {
166 txq->txb = kmalloc(sizeof(txq->txb[0]) *
167 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
168 if (!txq->txb) {
15b1687c 169 IWL_ERR(priv, "kmalloc for auxiliary BD "
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170 "structures failed\n");
171 goto error;
172 }
173 } else
174 txq->txb = NULL;
175
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176 /* Circular buffer of transmit frame descriptors (TFDs),
177 * shared with device */
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178 txq->tfds39 = pci_alloc_consistent(dev,
179 sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX,
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180 &txq->q.dma_addr);
181
188cf6c7 182 if (!txq->tfds39) {
15b1687c 183 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n",
188cf6c7 184 sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX);
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185 goto error;
186 }
187 txq->q.id = id;
188
189 return 0;
190
191 error:
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192 kfree(txq->txb);
193 txq->txb = NULL;
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194
195 return -ENOMEM;
196}
197
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198/**
199 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
200 */
4a8a4322 201int iwl3945_tx_queue_init(struct iwl_priv *priv,
188cf6c7 202 struct iwl_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c 203{
188cf6c7 204 int len, i;
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205 int rc = 0;
206
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207 /*
208 * Alloc buffer array for commands (Tx or other types of commands).
209 * For the command queue (#4), allocate command space + one big
210 * command for scan, since scan command is very huge; the system will
211 * not have two scans at the same time, so only one is needed.
212 * For data Tx queues (all other queues), no super-size command
213 * space is needed.
214 */
188cf6c7
SO
215 len = sizeof(struct iwl_cmd);
216 for (i = 0; i <= slots_num; i++) {
217 if (i == slots_num) {
218 if (txq_id == IWL_CMD_QUEUE_NUM)
219 len += IWL_MAX_SCAN_SIZE;
220 else
221 continue;
222 }
223
224 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
225 if (!txq->cmd[i])
226 goto err;
227 }
b481de9c 228
6440adb5 229 /* Alloc driver data array and TFD circular buffer */
bb8c093b 230 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
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231 if (rc)
232 goto err;
b481de9c 233
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234 txq->need_update = 0;
235
236 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 237 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 238 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
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239
240 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 241 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 242
6440adb5 243 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 244 iwl3945_hw_tx_queue_init(priv, txq);
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245
246 return 0;
188cf6c7
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247err:
248 for (i = 0; i < slots_num; i++) {
249 kfree(txq->cmd[i]);
250 txq->cmd[i] = NULL;
251 }
252
253 if (txq_id == IWL_CMD_QUEUE_NUM) {
254 kfree(txq->cmd[slots_num]);
255 txq->cmd[slots_num] = NULL;
256 }
257 return -ENOMEM;
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258}
259
260/**
bb8c093b 261 * iwl3945_tx_queue_free - Deallocate DMA queue.
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262 * @txq: Transmit queue to deallocate.
263 *
264 * Empty queue by removing and destroying all BD's.
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265 * Free all buffers.
266 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 267 */
188cf6c7 268void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 269{
d20b3c65 270 struct iwl_queue *q = &txq->q;
b481de9c 271 struct pci_dev *dev = priv->pci_dev;
188cf6c7 272 int len, i;
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273
274 if (q->n_bd == 0)
275 return;
276
277 /* first, empty all BD's */
fc4b6853 278 for (; q->write_ptr != q->read_ptr;
c54b679d 279 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 280 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 281
c2d79b48 282 len = sizeof(struct iwl_cmd) * q->n_window;
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283 if (q->id == IWL_CMD_QUEUE_NUM)
284 len += IWL_MAX_SCAN_SIZE;
285
6440adb5 286 /* De-alloc array of command/tx buffers */
188cf6c7
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287 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
288 kfree(txq->cmd[i]);
b481de9c 289
6440adb5 290 /* De-alloc circular buffer of TFDs */
b481de9c 291 if (txq->q.n_bd)
dbb6654c 292 pci_free_consistent(dev, sizeof(struct iwl3945_tfd) *
188cf6c7 293 txq->q.n_bd, txq->tfds39, txq->q.dma_addr);
b481de9c 294
6440adb5 295 /* De-alloc array of per-TFD driver data */
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296 kfree(txq->txb);
297 txq->txb = NULL;
b481de9c 298
6440adb5 299 /* 0-fill queue descriptor structure */
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300 memset(txq, 0, sizeof(*txq));
301}
302
b481de9c 303/*************** STATION TABLE MANAGEMENT ****
9fbab516 304 * mac80211 should be examined to determine if sta_info is duplicating
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305 * the functionality provided here
306 */
307
308/**************************************************************/
01ebd063 309#if 0 /* temporary disable till we add real remove station */
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310/**
311 * iwl3945_remove_station - Remove driver's knowledge of station.
312 *
313 * NOTE: This does not remove station from device's station table.
314 */
4a8a4322 315static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
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316{
317 int index = IWL_INVALID_STATION;
318 int i;
319 unsigned long flags;
320
321 spin_lock_irqsave(&priv->sta_lock, flags);
322
323 if (is_ap)
324 index = IWL_AP_ID;
325 else if (is_broadcast_ether_addr(addr))
3832ec9d 326 index = priv->hw_params.bcast_sta_id;
b481de9c 327 else
3832ec9d 328 for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++)
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329 if (priv->stations_39[i].used &&
330 !compare_ether_addr(priv->stations_39[i].sta.sta.addr,
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331 addr)) {
332 index = i;
333 break;
334 }
335
336 if (unlikely(index == IWL_INVALID_STATION))
337 goto out;
338
f2c7e521
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339 if (priv->stations_39[index].used) {
340 priv->stations_39[index].used = 0;
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341 priv->num_stations--;
342 }
343
344 BUG_ON(priv->num_stations < 0);
345
346out:
347 spin_unlock_irqrestore(&priv->sta_lock, flags);
348 return 0;
349}
556f8db7 350#endif
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351
352/**
353 * iwl3945_clear_stations_table - Clear the driver's station table
354 *
355 * NOTE: This does not clear or otherwise alter the device's station table.
356 */
4a8a4322 357static void iwl3945_clear_stations_table(struct iwl_priv *priv)
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358{
359 unsigned long flags;
360
361 spin_lock_irqsave(&priv->sta_lock, flags);
362
363 priv->num_stations = 0;
f2c7e521 364 memset(priv->stations_39, 0, sizeof(priv->stations_39));
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365
366 spin_unlock_irqrestore(&priv->sta_lock, flags);
367}
368
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369/**
370 * iwl3945_add_station - Add station to station tables in driver and device
371 */
4a8a4322 372u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags)
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373{
374 int i;
375 int index = IWL_INVALID_STATION;
bb8c093b 376 struct iwl3945_station_entry *station;
b481de9c 377 unsigned long flags_spin;
c14c521e 378 u8 rate;
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379
380 spin_lock_irqsave(&priv->sta_lock, flags_spin);
381 if (is_ap)
382 index = IWL_AP_ID;
383 else if (is_broadcast_ether_addr(addr))
3832ec9d 384 index = priv->hw_params.bcast_sta_id;
b481de9c 385 else
3832ec9d 386 for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) {
f2c7e521 387 if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr,
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388 addr)) {
389 index = i;
390 break;
391 }
392
f2c7e521 393 if (!priv->stations_39[i].used &&
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394 index == IWL_INVALID_STATION)
395 index = i;
396 }
397
01ebd063 398 /* These two conditions has the same outcome but keep them separate
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399 since they have different meaning */
400 if (unlikely(index == IWL_INVALID_STATION)) {
401 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
402 return index;
403 }
404
f2c7e521
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405 if (priv->stations_39[index].used &&
406 !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) {
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407 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
408 return index;
409 }
410
e174961c 411 IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
f2c7e521 412 station = &priv->stations_39[index];
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413 station->used = 1;
414 priv->num_stations++;
415
6440adb5 416 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 417 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
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418 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
419 station->sta.mode = 0;
420 station->sta.sta.sta_id = index;
421 station->sta.station_flags = 0;
422
8318d78a 423 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW
424 rate = IWL_RATE_6M_PLCP;
425 else
426 rate = IWL_RATE_1M_PLCP;
c14c521e
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427
428 /* Turn on both antennas for the station... */
429 station->sta.rate_n_flags =
bb8c093b 430 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e 431
b481de9c 432 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
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433
434 /* Add station to device's station table */
bb8c093b 435 iwl3945_send_add_station(priv, &station->sta, flags);
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436 return index;
437
438}
439
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440
441/*************** HOST COMMAND QUEUE FUNCTIONS *****/
442
c3056065 443#define IWL_CMD(x) case x: return #x
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444#define HOST_COMPLETE_TIMEOUT (HZ / 2)
445
446/**
bb8c093b 447 * iwl3945_enqueue_hcmd - enqueue a uCode command
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448 * @priv: device private data point
449 * @cmd: a point to the ucode command structure
450 *
451 * The function returns < 0 values to indicate the operation is
452 * failed. On success, it turns the index (> 0) of command in the
453 * command queue.
454 */
c2d79b48 455static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
b481de9c 456{
188cf6c7 457 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
d20b3c65 458 struct iwl_queue *q = &txq->q;
dbb6654c 459 struct iwl3945_tfd *tfd;
c2d79b48 460 struct iwl_cmd *out_cmd;
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461 u32 idx;
462 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
463 dma_addr_t phys_addr;
464 int pad;
188cf6c7 465 int ret, len;
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466 unsigned long flags;
467
468 /* If any of the command structures end up being larger than
469 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
470 * we will need to increase the size of the TFD entries */
c2d79b48 471 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
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472 !(cmd->meta.flags & CMD_SIZE_HUGE));
473
c342a1b9 474
775a6e27 475 if (iwl_is_rfkill(priv)) {
c342a1b9
GG
476 IWL_DEBUG_INFO("Not sending command - RF KILL");
477 return -EIO;
478 }
479
d20b3c65 480 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
15b1687c 481 IWL_ERR(priv, "No space for Tx\n");
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482 return -ENOSPC;
483 }
484
485 spin_lock_irqsave(&priv->hcmd_lock, flags);
486
188cf6c7 487 tfd = &txq->tfds39[q->write_ptr];
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488 memset(tfd, 0, sizeof(*tfd));
489
fc4b6853 490 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
188cf6c7 491 out_cmd = txq->cmd[idx];
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492
493 out_cmd->hdr.cmd = cmd->id;
494 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
495 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
496
497 /* At this point, the out_cmd now has all of the incoming cmd
498 * information */
499
500 out_cmd->hdr.flags = 0;
501 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 502 INDEX_TO_SEQ(q->write_ptr));
b481de9c 503 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
600c0e11 504 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
b481de9c 505
188cf6c7
SO
506 len = (idx == TFD_CMD_SLOTS) ?
507 IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
508
509 phys_addr = pci_map_single(priv->pci_dev, out_cmd,
510 len, PCI_DMA_TODEVICE);
511 pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
512 pci_unmap_len_set(&out_cmd->meta, len, len);
513 phys_addr += offsetof(struct iwl_cmd, hdr);
514
bb8c093b 515 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
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516
517 pad = U32_PAD(cmd->len);
dbb6654c 518 tfd->control_flags |= cpu_to_le32(TFD_CTL_PAD_SET(pad));
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519
520 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
521 "%d bytes at %d[%d]:%d\n",
522 get_cmd_string(out_cmd->hdr.cmd),
523 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 524 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
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525
526 txq->need_update = 1;
6440adb5
CB
527
528 /* Increment and update queue's write index */
c54b679d 529 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 530 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
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531
532 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
533 return ret ? ret : idx;
534}
535
c2d79b48
WT
536static int iwl3945_send_cmd_async(struct iwl_priv *priv,
537 struct iwl_host_cmd *cmd)
b481de9c
ZY
538{
539 int ret;
540
541 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
542
543 /* An asynchronous command can not expect an SKB to be set. */
544 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
545
546 /* An asynchronous command MUST have a callback. */
547 BUG_ON(!cmd->meta.u.callback);
548
549 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
550 return -EBUSY;
551
bb8c093b 552 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 553 if (ret < 0) {
15b1687c
WT
554 IWL_ERR(priv,
555 "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
556 get_cmd_string(cmd->id), ret);
b481de9c
ZY
557 return ret;
558 }
559 return 0;
560}
561
c2d79b48
WT
562static int iwl3945_send_cmd_sync(struct iwl_priv *priv,
563 struct iwl_host_cmd *cmd)
b481de9c
ZY
564{
565 int cmd_idx;
566 int ret;
b481de9c
ZY
567
568 BUG_ON(cmd->meta.flags & CMD_ASYNC);
569
570 /* A synchronous command can not have a callback set. */
571 BUG_ON(cmd->meta.u.callback != NULL);
572
e5472978 573 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
15b1687c
WT
574 IWL_ERR(priv,
575 "Error sending %s: Already sending a host command\n",
576 get_cmd_string(cmd->id));
e5472978
TW
577 ret = -EBUSY;
578 goto out;
b481de9c
ZY
579 }
580
581 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
582
583 if (cmd->meta.flags & CMD_WANT_SKB)
584 cmd->meta.source = &cmd->meta;
585
bb8c093b 586 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY
587 if (cmd_idx < 0) {
588 ret = cmd_idx;
15b1687c
WT
589 IWL_ERR(priv,
590 "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
591 get_cmd_string(cmd->id), ret);
b481de9c
ZY
592 goto out;
593 }
594
595 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
596 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
597 HOST_COMPLETE_TIMEOUT);
598 if (!ret) {
599 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
15b1687c 600 IWL_ERR(priv, "Error sending %s: time out after %dms\n",
b481de9c
ZY
601 get_cmd_string(cmd->id),
602 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
603
604 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
605 ret = -ETIMEDOUT;
606 goto cancel;
607 }
608 }
609
610 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
611 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
612 get_cmd_string(cmd->id));
613 ret = -ECANCELED;
614 goto fail;
615 }
616 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
617 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
618 get_cmd_string(cmd->id));
619 ret = -EIO;
620 goto fail;
621 }
622 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
15b1687c 623 IWL_ERR(priv, "Error: Response NULL in '%s'\n",
b481de9c
ZY
624 get_cmd_string(cmd->id));
625 ret = -EIO;
73e1a65d 626 goto cancel;
b481de9c
ZY
627 }
628
629 ret = 0;
630 goto out;
631
632cancel:
633 if (cmd->meta.flags & CMD_WANT_SKB) {
c2d79b48 634 struct iwl_cmd *qcmd;
b481de9c
ZY
635
636 /* Cancel the CMD_WANT_SKB flag for the cmd in the
637 * TX cmd queue. Otherwise in case the cmd comes
638 * in later, it will possibly set an invalid
639 * address (cmd->meta.source). */
188cf6c7 640 qcmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
b481de9c
ZY
641 qcmd->meta.flags &= ~CMD_WANT_SKB;
642 }
643fail:
644 if (cmd->meta.u.skb) {
645 dev_kfree_skb_any(cmd->meta.u.skb);
646 cmd->meta.u.skb = NULL;
647 }
648out:
e5472978 649 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
b481de9c
ZY
650 return ret;
651}
652
c2d79b48 653int iwl3945_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
b481de9c 654{
b481de9c 655 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 656 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 657
bb8c093b 658 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY
659}
660
4a8a4322 661int iwl3945_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len, const void *data)
b481de9c 662{
c2d79b48 663 struct iwl_host_cmd cmd = {
b481de9c
ZY
664 .id = id,
665 .len = len,
666 .data = data,
667 };
668
bb8c093b 669 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
670}
671
4a8a4322 672static int __must_check iwl3945_send_cmd_u32(struct iwl_priv *priv, u8 id, u32 val)
b481de9c 673{
c2d79b48 674 struct iwl_host_cmd cmd = {
b481de9c
ZY
675 .id = id,
676 .len = sizeof(val),
677 .data = &val,
678 };
679
bb8c093b 680 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
681}
682
4a8a4322 683int iwl3945_send_statistics_request(struct iwl_priv *priv)
b481de9c 684{
bb8c093b 685 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY
686}
687
b481de9c 688/**
bb8c093b 689 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB
690 * @band: 2.4 or 5 GHz band
691 * @channel: Any channel valid for the requested band
b481de9c 692
8318d78a 693 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY
694 *
695 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 696 * in the staging RXON flag structure based on the band
b481de9c 697 */
4a8a4322 698static int iwl3945_set_rxon_channel(struct iwl_priv *priv,
8318d78a
JB
699 enum ieee80211_band band,
700 u16 channel)
b481de9c 701{
8318d78a 702 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 703 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 704 channel, band);
b481de9c
ZY
705 return -EINVAL;
706 }
707
f2c7e521 708 if ((le16_to_cpu(priv->staging39_rxon.channel) == channel) &&
8318d78a 709 (priv->band == band))
b481de9c
ZY
710 return 0;
711
f2c7e521 712 priv->staging39_rxon.channel = cpu_to_le16(channel);
8318d78a 713 if (band == IEEE80211_BAND_5GHZ)
f2c7e521 714 priv->staging39_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
b481de9c 715 else
f2c7e521 716 priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
b481de9c 717
8318d78a 718 priv->band = band;
b481de9c 719
8318d78a 720 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY
721
722 return 0;
723}
724
725/**
bb8c093b 726 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY
727 *
728 * NOTE: This is really only useful during development and can eventually
729 * be #ifdef'd out once the driver is stable and folks aren't actively
730 * making changes
731 */
4a8a4322 732static int iwl3945_check_rxon_cmd(struct iwl_priv *priv)
b481de9c
ZY
733{
734 int error = 0;
735 int counter = 1;
f2c7e521 736 struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
b481de9c
ZY
737
738 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
739 error |= le32_to_cpu(rxon->flags &
740 (RXON_FLG_TGJ_NARROW_BAND_MSK |
741 RXON_FLG_RADAR_DETECT_MSK));
742 if (error)
39aadf8c 743 IWL_WARN(priv, "check 24G fields %d | %d\n",
b481de9c
ZY
744 counter++, error);
745 } else {
746 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
747 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
748 if (error)
39aadf8c 749 IWL_WARN(priv, "check 52 fields %d | %d\n",
b481de9c
ZY
750 counter++, error);
751 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
752 if (error)
39aadf8c 753 IWL_WARN(priv, "check 52 CCK %d | %d\n",
b481de9c
ZY
754 counter++, error);
755 }
756 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
757 if (error)
39aadf8c 758 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
b481de9c
ZY
759
760 /* make sure basic rates 6Mbps and 1Mbps are supported */
761 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
762 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
763 if (error)
39aadf8c 764 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
b481de9c
ZY
765
766 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
767 if (error)
39aadf8c 768 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
b481de9c
ZY
769
770 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
771 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
772 if (error)
39aadf8c 773 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
b481de9c
ZY
774 counter++, error);
775
776 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
777 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
778 if (error)
39aadf8c 779 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
b481de9c
ZY
780 counter++, error);
781
782 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
783 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
784 if (error)
39aadf8c 785 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
b481de9c
ZY
786 counter++, error);
787
788 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
789 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
790 RXON_FLG_ANT_A_MSK)) == 0);
791 if (error)
39aadf8c 792 IWL_WARN(priv, "check antenna %d %d\n", counter++, error);
b481de9c
ZY
793
794 if (error)
39aadf8c 795 IWL_WARN(priv, "Tuning to channel %d\n",
b481de9c
ZY
796 le16_to_cpu(rxon->channel));
797
798 if (error) {
15b1687c 799 IWL_ERR(priv, "Not a valid rxon_assoc_cmd field values\n");
b481de9c
ZY
800 return -1;
801 }
802 return 0;
803}
804
805/**
9fbab516 806 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 807 * @priv: staging_rxon is compared to active_rxon
b481de9c 808 *
9fbab516
BC
809 * If the RXON structure is changing enough to require a new tune,
810 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
811 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 812 */
4a8a4322 813static int iwl3945_full_rxon_required(struct iwl_priv *priv)
b481de9c
ZY
814{
815
816 /* These items are only settable from the full RXON command */
5d1e2325 817 if (!(iwl3945_is_associated(priv)) ||
f2c7e521
AK
818 compare_ether_addr(priv->staging39_rxon.bssid_addr,
819 priv->active39_rxon.bssid_addr) ||
820 compare_ether_addr(priv->staging39_rxon.node_addr,
821 priv->active39_rxon.node_addr) ||
822 compare_ether_addr(priv->staging39_rxon.wlap_bssid_addr,
823 priv->active39_rxon.wlap_bssid_addr) ||
824 (priv->staging39_rxon.dev_type != priv->active39_rxon.dev_type) ||
825 (priv->staging39_rxon.channel != priv->active39_rxon.channel) ||
826 (priv->staging39_rxon.air_propagation !=
827 priv->active39_rxon.air_propagation) ||
828 (priv->staging39_rxon.assoc_id != priv->active39_rxon.assoc_id))
b481de9c
ZY
829 return 1;
830
831 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
832 * be updated with the RXON_ASSOC command -- however only some
833 * flag transitions are allowed using RXON_ASSOC */
834
835 /* Check if we are not switching bands */
f2c7e521
AK
836 if ((priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
837 (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK))
b481de9c
ZY
838 return 1;
839
840 /* Check if we are switching association toggle */
f2c7e521
AK
841 if ((priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
842 (priv->active39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
b481de9c
ZY
843 return 1;
844
845 return 0;
846}
847
4a8a4322 848static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
b481de9c
ZY
849{
850 int rc = 0;
3d24a9f7 851 struct iwl_rx_packet *res = NULL;
bb8c093b 852 struct iwl3945_rxon_assoc_cmd rxon_assoc;
c2d79b48 853 struct iwl_host_cmd cmd = {
b481de9c
ZY
854 .id = REPLY_RXON_ASSOC,
855 .len = sizeof(rxon_assoc),
856 .meta.flags = CMD_WANT_SKB,
857 .data = &rxon_assoc,
858 };
f2c7e521
AK
859 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging39_rxon;
860 const struct iwl3945_rxon_cmd *rxon2 = &priv->active39_rxon;
b481de9c
ZY
861
862 if ((rxon1->flags == rxon2->flags) &&
863 (rxon1->filter_flags == rxon2->filter_flags) &&
864 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
865 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
866 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
867 return 0;
868 }
869
f2c7e521
AK
870 rxon_assoc.flags = priv->staging39_rxon.flags;
871 rxon_assoc.filter_flags = priv->staging39_rxon.filter_flags;
872 rxon_assoc.ofdm_basic_rates = priv->staging39_rxon.ofdm_basic_rates;
873 rxon_assoc.cck_basic_rates = priv->staging39_rxon.cck_basic_rates;
b481de9c
ZY
874 rxon_assoc.reserved = 0;
875
bb8c093b 876 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
877 if (rc)
878 return rc;
879
3d24a9f7 880 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c 881 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 882 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
b481de9c
ZY
883 rc = -EIO;
884 }
885
886 priv->alloc_rxb_skb--;
887 dev_kfree_skb_any(cmd.meta.u.skb);
888
889 return rc;
890}
891
892/**
bb8c093b 893 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 894 *
01ebd063 895 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY
896 * the active_rxon structure is updated with the new data. This
897 * function correctly transitions out of the RXON_ASSOC_MSK state if
898 * a HW tune is required based on the RXON structure changes.
899 */
4a8a4322 900static int iwl3945_commit_rxon(struct iwl_priv *priv)
b481de9c
ZY
901{
902 /* cast away the const for active_rxon in this function */
f2c7e521 903 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active39_rxon;
b481de9c
ZY
904 int rc = 0;
905
775a6e27 906 if (!iwl_is_alive(priv))
b481de9c
ZY
907 return -1;
908
909 /* always get timestamp with Rx frame */
f2c7e521 910 priv->staging39_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
b481de9c
ZY
911
912 /* select antenna */
f2c7e521 913 priv->staging39_rxon.flags &=
b481de9c 914 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
f2c7e521 915 priv->staging39_rxon.flags |= iwl3945_get_antenna_flags(priv);
b481de9c 916
a3139c59 917 rc = iwl3945_check_rxon_cmd(priv);
b481de9c 918 if (rc) {
15b1687c 919 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY
920 return -EINVAL;
921 }
922
923 /* If we don't need to send a full RXON, we can use
bb8c093b 924 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 925 * and other flags for the current radio configuration. */
bb8c093b
CH
926 if (!iwl3945_full_rxon_required(priv)) {
927 rc = iwl3945_send_rxon_assoc(priv);
b481de9c 928 if (rc) {
15b1687c 929 IWL_ERR(priv, "Error setting RXON_ASSOC "
b481de9c
ZY
930 "configuration (%d).\n", rc);
931 return rc;
932 }
933
f2c7e521 934 memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
b481de9c
ZY
935
936 return 0;
937 }
938
939 /* If we are currently associated and the new config requires
940 * an RXON_ASSOC and the new config wants the associated mask enabled,
941 * we must clear the associated from the active configuration
942 * before we apply the new config */
bb8c093b 943 if (iwl3945_is_associated(priv) &&
f2c7e521 944 (priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
b481de9c
ZY
945 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
946 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
947
bb8c093b
CH
948 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
949 sizeof(struct iwl3945_rxon_cmd),
f2c7e521 950 &priv->active39_rxon);
b481de9c
ZY
951
952 /* If the mask clearing failed then we set
953 * active_rxon back to what it was previously */
954 if (rc) {
955 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 956 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
b481de9c
ZY
957 "configuration (%d).\n", rc);
958 return rc;
959 }
b481de9c
ZY
960 }
961
962 IWL_DEBUG_INFO("Sending RXON\n"
963 "* with%s RXON_FILTER_ASSOC_MSK\n"
964 "* channel = %d\n"
e174961c 965 "* bssid = %pM\n",
f2c7e521 966 ((priv->staging39_rxon.filter_flags &
b481de9c 967 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
f2c7e521 968 le16_to_cpu(priv->staging39_rxon.channel),
e174961c 969 priv->staging_rxon.bssid_addr);
b481de9c
ZY
970
971 /* Apply the new configuration */
bb8c093b 972 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
f2c7e521 973 sizeof(struct iwl3945_rxon_cmd), &priv->staging39_rxon);
b481de9c 974 if (rc) {
15b1687c 975 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
b481de9c
ZY
976 return rc;
977 }
978
f2c7e521 979 memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
b481de9c 980
bb8c093b 981 iwl3945_clear_stations_table(priv);
556f8db7 982
b481de9c
ZY
983 /* If we issue a new RXON command which required a tune then we must
984 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 985 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c 986 if (rc) {
15b1687c 987 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
b481de9c
ZY
988 return rc;
989 }
990
991 /* Add the broadcast address so we can send broadcast frames */
b5323d36 992 if (iwl3945_add_station(priv, iwl_bcast_addr, 0, 0) ==
b481de9c 993 IWL_INVALID_STATION) {
15b1687c 994 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
b481de9c
ZY
995 return -EIO;
996 }
997
998 /* If we have set the ASSOC_MSK and we are in BSS mode then
999 * add the IWL_AP_ID to the station rate table */
bb8c093b 1000 if (iwl3945_is_associated(priv) &&
05c914fe 1001 (priv->iw_mode == NL80211_IFTYPE_STATION))
f2c7e521 1002 if (iwl3945_add_station(priv, priv->active39_rxon.bssid_addr, 1, 0)
b481de9c 1003 == IWL_INVALID_STATION) {
15b1687c 1004 IWL_ERR(priv, "Error adding AP address for transmit\n");
b481de9c
ZY
1005 return -EIO;
1006 }
1007
8318d78a 1008 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY
1009 rc = iwl3945_init_hw_rate_table(priv);
1010 if (rc) {
15b1687c 1011 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
b481de9c
ZY
1012 return -EIO;
1013 }
1014
1015 return 0;
1016}
1017
4a8a4322 1018static int iwl3945_send_bt_config(struct iwl_priv *priv)
b481de9c 1019{
4c897253 1020 struct iwl_bt_cmd bt_cmd = {
b481de9c
ZY
1021 .flags = 3,
1022 .lead_time = 0xAA,
1023 .max_kill = 1,
1024 .kill_ack_mask = 0,
1025 .kill_cts_mask = 0,
1026 };
1027
bb8c093b 1028 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
4c897253 1029 sizeof(bt_cmd), &bt_cmd);
b481de9c
ZY
1030}
1031
4a8a4322 1032static int iwl3945_send_scan_abort(struct iwl_priv *priv)
b481de9c
ZY
1033{
1034 int rc = 0;
3d24a9f7 1035 struct iwl_rx_packet *res;
c2d79b48 1036 struct iwl_host_cmd cmd = {
b481de9c
ZY
1037 .id = REPLY_SCAN_ABORT_CMD,
1038 .meta.flags = CMD_WANT_SKB,
1039 };
1040
1041 /* If there isn't a scan actively going on in the hardware
1042 * then we are in between scan bands and not actually
1043 * actively scanning, so don't send the abort command */
1044 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1045 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1046 return 0;
1047 }
1048
bb8c093b 1049 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
1050 if (rc) {
1051 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1052 return rc;
1053 }
1054
3d24a9f7 1055 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY
1056 if (res->u.status != CAN_ABORT_STATUS) {
1057 /* The scan abort will return 1 for success or
1058 * 2 for "failure". A failure condition can be
1059 * due to simply not being in an active scan which
1060 * can occur if we send the scan abort before we
1061 * the microcode has notified us that a scan is
1062 * completed. */
1063 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1064 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1065 clear_bit(STATUS_SCAN_HW, &priv->status);
1066 }
1067
1068 dev_kfree_skb_any(cmd.meta.u.skb);
1069
1070 return rc;
1071}
1072
4a8a4322 1073static int iwl3945_add_sta_sync_callback(struct iwl_priv *priv,
c2d79b48 1074 struct iwl_cmd *cmd, struct sk_buff *skb)
b481de9c 1075{
3d24a9f7 1076 struct iwl_rx_packet *res = NULL;
b481de9c
ZY
1077
1078 if (!skb) {
15b1687c 1079 IWL_ERR(priv, "Error: Response NULL in REPLY_ADD_STA.\n");
b481de9c
ZY
1080 return 1;
1081 }
1082
3d24a9f7 1083 res = (struct iwl_rx_packet *)skb->data;
b481de9c 1084 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 1085 IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
b481de9c
ZY
1086 res->hdr.flags);
1087 return 1;
1088 }
1089
1090 switch (res->u.add_sta.status) {
1091 case ADD_STA_SUCCESS_MSK:
1092 break;
1093 default:
1094 break;
1095 }
1096
1097 /* We didn't cache the SKB; let the caller free it */
1098 return 1;
1099}
1100
4a8a4322 1101int iwl3945_send_add_station(struct iwl_priv *priv,
bb8c093b 1102 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1103{
3d24a9f7 1104 struct iwl_rx_packet *res = NULL;
b481de9c 1105 int rc = 0;
c2d79b48 1106 struct iwl_host_cmd cmd = {
b481de9c 1107 .id = REPLY_ADD_STA,
bb8c093b 1108 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY
1109 .meta.flags = flags,
1110 .data = sta,
1111 };
1112
1113 if (flags & CMD_ASYNC)
bb8c093b 1114 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY
1115 else
1116 cmd.meta.flags |= CMD_WANT_SKB;
1117
bb8c093b 1118 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY
1119
1120 if (rc || (flags & CMD_ASYNC))
1121 return rc;
1122
3d24a9f7 1123 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c 1124 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 1125 IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
b481de9c
ZY
1126 res->hdr.flags);
1127 rc = -EIO;
1128 }
1129
1130 if (rc == 0) {
1131 switch (res->u.add_sta.status) {
1132 case ADD_STA_SUCCESS_MSK:
1133 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1134 break;
1135 default:
1136 rc = -EIO;
39aadf8c 1137 IWL_WARN(priv, "REPLY_ADD_STA failed\n");
b481de9c
ZY
1138 break;
1139 }
1140 }
1141
1142 priv->alloc_rxb_skb--;
1143 dev_kfree_skb_any(cmd.meta.u.skb);
1144
1145 return rc;
1146}
1147
4a8a4322 1148static int iwl3945_update_sta_key_info(struct iwl_priv *priv,
b481de9c
ZY
1149 struct ieee80211_key_conf *keyconf,
1150 u8 sta_id)
1151{
1152 unsigned long flags;
1153 __le16 key_flags = 0;
1154
1155 switch (keyconf->alg) {
1156 case ALG_CCMP:
1157 key_flags |= STA_KEY_FLG_CCMP;
1158 key_flags |= cpu_to_le16(
1159 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1160 key_flags &= ~STA_KEY_FLG_INVALID;
1161 break;
1162 case ALG_TKIP:
1163 case ALG_WEP:
b481de9c
ZY
1164 default:
1165 return -EINVAL;
1166 }
1167 spin_lock_irqsave(&priv->sta_lock, flags);
f2c7e521
AK
1168 priv->stations_39[sta_id].keyinfo.alg = keyconf->alg;
1169 priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen;
1170 memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key,
b481de9c
ZY
1171 keyconf->keylen);
1172
f2c7e521 1173 memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key,
b481de9c 1174 keyconf->keylen);
f2c7e521
AK
1175 priv->stations_39[sta_id].sta.key.key_flags = key_flags;
1176 priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1177 priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c
ZY
1178
1179 spin_unlock_irqrestore(&priv->sta_lock, flags);
1180
1181 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
f2c7e521 1182 iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
b481de9c
ZY
1183 return 0;
1184}
1185
4a8a4322 1186static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
b481de9c
ZY
1187{
1188 unsigned long flags;
1189
1190 spin_lock_irqsave(&priv->sta_lock, flags);
f2c7e521
AK
1191 memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1192 memset(&priv->stations_39[sta_id].sta.key, 0,
4c897253 1193 sizeof(struct iwl4965_keyinfo));
f2c7e521
AK
1194 priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1195 priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1196 priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c
ZY
1197 spin_unlock_irqrestore(&priv->sta_lock, flags);
1198
1199 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
f2c7e521 1200 iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
b481de9c
ZY
1201 return 0;
1202}
1203
4a8a4322 1204static void iwl3945_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY
1205{
1206 struct list_head *element;
1207
1208 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1209 priv->frames_count);
1210
1211 while (!list_empty(&priv->free_frames)) {
1212 element = priv->free_frames.next;
1213 list_del(element);
bb8c093b 1214 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY
1215 priv->frames_count--;
1216 }
1217
1218 if (priv->frames_count) {
39aadf8c 1219 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY
1220 priv->frames_count);
1221 priv->frames_count = 0;
1222 }
1223}
1224
4a8a4322 1225static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
b481de9c 1226{
bb8c093b 1227 struct iwl3945_frame *frame;
b481de9c
ZY
1228 struct list_head *element;
1229 if (list_empty(&priv->free_frames)) {
1230 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1231 if (!frame) {
15b1687c 1232 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY
1233 return NULL;
1234 }
1235
1236 priv->frames_count++;
1237 return frame;
1238 }
1239
1240 element = priv->free_frames.next;
1241 list_del(element);
bb8c093b 1242 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY
1243}
1244
4a8a4322 1245static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY
1246{
1247 memset(frame, 0, sizeof(*frame));
1248 list_add(&frame->list, &priv->free_frames);
1249}
1250
4a8a4322 1251unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
b481de9c 1252 struct ieee80211_hdr *hdr,
73ec1cc2 1253 int left)
b481de9c
ZY
1254{
1255
bb8c093b 1256 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
1257 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
1258 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY
1259 return 0;
1260
1261 if (priv->ibss_beacon->len > left)
1262 return 0;
1263
1264 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1265
1266 return priv->ibss_beacon->len;
1267}
1268
4a8a4322 1269static u8 iwl3945_rate_get_lowest_plcp(struct iwl_priv *priv)
b481de9c
ZY
1270{
1271 u8 i;
c24f0817
KA
1272 int rate_mask;
1273
1274 /* Set rate mask*/
f2c7e521 1275 if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
dbce56a4 1276 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
c24f0817 1277 else
dbce56a4 1278 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
b481de9c
ZY
1279
1280 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1281 i = iwl3945_rates[i].next_ieee) {
b481de9c 1282 if (rate_mask & (1 << i))
bb8c093b 1283 return iwl3945_rates[i].plcp;
b481de9c
ZY
1284 }
1285
c24f0817 1286 /* No valid rate was found. Assign the lowest one */
f2c7e521 1287 if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
c24f0817
KA
1288 return IWL_RATE_1M_PLCP;
1289 else
1290 return IWL_RATE_6M_PLCP;
b481de9c
ZY
1291}
1292
4a8a4322 1293static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 1294{
bb8c093b 1295 struct iwl3945_frame *frame;
b481de9c
ZY
1296 unsigned int frame_size;
1297 int rc;
1298 u8 rate;
1299
bb8c093b 1300 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY
1301
1302 if (!frame) {
15b1687c 1303 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY
1304 "command.\n");
1305 return -ENOMEM;
1306 }
1307
c24f0817 1308 rate = iwl3945_rate_get_lowest_plcp(priv);
b481de9c 1309
bb8c093b 1310 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1311
bb8c093b 1312 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
1313 &frame->u.cmd[0]);
1314
bb8c093b 1315 iwl3945_free_frame(priv, frame);
b481de9c
ZY
1316
1317 return rc;
1318}
1319
1320/******************************************************************************
1321 *
1322 * EEPROM related functions
1323 *
1324 ******************************************************************************/
1325
4a8a4322 1326static void get_eeprom_mac(struct iwl_priv *priv, u8 *mac)
b481de9c 1327{
f2c7e521 1328 memcpy(mac, priv->eeprom39.mac_address, 6);
b481de9c
ZY
1329}
1330
74a3a250
RC
1331/*
1332 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1333 * embedded controller) as EEPROM reader; each read is a series of pulses
1334 * to/from the EEPROM chip, not a single event, so even reads could conflict
1335 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1336 * simply claims ownership, which should be safe when this function is called
1337 * (i.e. before loading uCode!).
1338 */
4a8a4322 1339static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
74a3a250 1340{
5d49f498 1341 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
74a3a250
RC
1342 return 0;
1343}
1344
b481de9c 1345/**
bb8c093b 1346 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1347 *
f2c7e521 1348 * Load the EEPROM contents from adapter into priv->eeprom39
b481de9c
ZY
1349 *
1350 * NOTE: This routine uses the non-debug IO access functions.
1351 */
4a8a4322 1352int iwl3945_eeprom_init(struct iwl_priv *priv)
b481de9c 1353{
f2c7e521 1354 u16 *e = (u16 *)&priv->eeprom39;
5d49f498 1355 u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
f2c7e521 1356 int sz = sizeof(priv->eeprom39);
3d5717ad 1357 int ret;
b481de9c
ZY
1358 u16 addr;
1359
1360 /* The EEPROM structure has several padding buffers within it
1361 * and when adding new EEPROM maps is subject to programmer errors
1362 * which may be very difficult to identify without explicitly
1363 * checking the resulting size of the eeprom map. */
f2c7e521 1364 BUILD_BUG_ON(sizeof(priv->eeprom39) != IWL_EEPROM_IMAGE_SIZE);
b481de9c
ZY
1365
1366 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
15b1687c 1367 IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
b481de9c
ZY
1368 return -ENOENT;
1369 }
1370
6440adb5 1371 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
3d5717ad
ZY
1372 ret = iwl3945_eeprom_acquire_semaphore(priv);
1373 if (ret < 0) {
15b1687c 1374 IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY
1375 return -ENOENT;
1376 }
1377
1378 /* eeprom is an array of 16bit values */
1379 for (addr = 0; addr < sz; addr += sizeof(u16)) {
3d5717ad 1380 u32 r;
b481de9c 1381
5d49f498 1382 _iwl_write32(priv, CSR_EEPROM_REG,
3d5717ad 1383 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
5d49f498
AK
1384 _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
1385 ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
3d5717ad
ZY
1386 CSR_EEPROM_REG_READ_VALID_MSK,
1387 IWL_EEPROM_ACCESS_TIMEOUT);
1388 if (ret < 0) {
15b1687c 1389 IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
3d5717ad 1390 return ret;
b481de9c 1391 }
3d5717ad 1392
5d49f498 1393 r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
58ff6d4d 1394 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY
1395 }
1396
1397 return 0;
1398}
1399
4a8a4322 1400static void iwl3945_unset_hw_params(struct iwl_priv *priv)
b481de9c 1401{
3832ec9d 1402 if (priv->shared_virt)
b481de9c 1403 pci_free_consistent(priv->pci_dev,
bb8c093b 1404 sizeof(struct iwl3945_shared),
3832ec9d
AK
1405 priv->shared_virt,
1406 priv->shared_phys);
b481de9c
ZY
1407}
1408
1409/**
bb8c093b 1410 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY
1411 *
1412 * return : set the bit for each supported rate insert in ie
1413 */
bb8c093b 1414static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1415 u16 basic_rate, int *left)
b481de9c
ZY
1416{
1417 u16 ret_rates = 0, bit;
1418 int i;
c7c46676
TW
1419 u8 *cnt = ie;
1420 u8 *rates = ie + 1;
b481de9c
ZY
1421
1422 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1423 if (bit & supported_rate) {
1424 ret_rates |= bit;
bb8c093b 1425 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW
1426 ((bit & basic_rate) ? 0x80 : 0x00);
1427 (*cnt)++;
1428 (*left)--;
1429 if ((*left <= 0) ||
1430 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY
1431 break;
1432 }
1433 }
1434
1435 return ret_rates;
1436}
1437
1438/**
bb8c093b 1439 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1440 */
4a8a4322 1441static u16 iwl3945_fill_probe_req(struct iwl_priv *priv,
b481de9c 1442 struct ieee80211_mgmt *frame,
430cfe95 1443 int left)
b481de9c
ZY
1444{
1445 int len = 0;
1446 u8 *pos = NULL;
c7c46676 1447 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY
1448
1449 /* Make sure there is enough space for the probe request,
1450 * two mandatory IEs and the data */
1451 left -= 24;
1452 if (left < 0)
1453 return 0;
1454 len += 24;
1455
1456 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
b5323d36 1457 memcpy(frame->da, iwl_bcast_addr, ETH_ALEN);
b481de9c 1458 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
b5323d36 1459 memcpy(frame->bssid, iwl_bcast_addr, ETH_ALEN);
b481de9c
ZY
1460 frame->seq_ctrl = 0;
1461
1462 /* fill in our indirect SSID IE */
1463 /* ...next IE... */
1464
1465 left -= 2;
1466 if (left < 0)
1467 return 0;
1468 len += 2;
1469 pos = &(frame->u.probe_req.variable[0]);
1470 *pos++ = WLAN_EID_SSID;
1471 *pos++ = 0;
1472
b481de9c
ZY
1473 /* fill in supported rate */
1474 /* ...next IE... */
1475 left -= 2;
1476 if (left < 0)
1477 return 0;
c7c46676 1478
b481de9c
ZY
1479 /* ... fill it in... */
1480 *pos++ = WLAN_EID_SUPP_RATES;
1481 *pos = 0;
c7c46676
TW
1482
1483 priv->active_rate = priv->rates_mask;
1484 active_rates = priv->active_rate;
b481de9c
ZY
1485 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1486
c7c46676 1487 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1488 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW
1489 priv->active_rate_basic, &left);
1490 active_rates &= ~ret_rates;
1491
bb8c093b 1492 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW
1493 priv->active_rate_basic, &left);
1494 active_rates &= ~ret_rates;
1495
b481de9c
ZY
1496 len += 2 + *pos;
1497 pos += (*pos) + 1;
c7c46676 1498 if (active_rates == 0)
b481de9c
ZY
1499 goto fill_end;
1500
1501 /* fill in supported extended rate */
1502 /* ...next IE... */
1503 left -= 2;
1504 if (left < 0)
1505 return 0;
1506 /* ... fill it in... */
1507 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1508 *pos = 0;
bb8c093b 1509 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1510 priv->active_rate_basic, &left);
b481de9c
ZY
1511 if (*pos > 0)
1512 len += 2 + *pos;
1513
1514 fill_end:
1515 return (u16)len;
1516}
1517
1518/*
1519 * QoS support
1520*/
4a8a4322 1521static int iwl3945_send_qos_params_command(struct iwl_priv *priv,
4c897253 1522 struct iwl_qosparam_cmd *qos)
b481de9c
ZY
1523{
1524
bb8c093b 1525 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
4c897253 1526 sizeof(struct iwl_qosparam_cmd), qos);
b481de9c
ZY
1527}
1528
4a8a4322 1529static void iwl3945_activate_qos(struct iwl_priv *priv, u8 force)
b481de9c
ZY
1530{
1531 unsigned long flags;
1532
b481de9c
ZY
1533 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1534 return;
1535
b481de9c
ZY
1536 spin_lock_irqsave(&priv->lock, flags);
1537 priv->qos_data.def_qos_parm.qos_flags = 0;
1538
1539 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1540 !priv->qos_data.qos_cap.q_AP.txop_request)
1541 priv->qos_data.def_qos_parm.qos_flags |=
1542 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1543
1544 if (priv->qos_data.qos_active)
1545 priv->qos_data.def_qos_parm.qos_flags |=
1546 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1547
1548 spin_unlock_irqrestore(&priv->lock, flags);
1549
bb8c093b 1550 if (force || iwl3945_is_associated(priv)) {
a96a27f9 1551 IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
b481de9c
ZY
1552 priv->qos_data.qos_active);
1553
bb8c093b 1554 iwl3945_send_qos_params_command(priv,
b481de9c
ZY
1555 &(priv->qos_data.def_qos_parm));
1556 }
1557}
1558
b481de9c
ZY
1559/*
1560 * Power management (not Tx power!) functions
1561 */
1562#define MSEC_TO_USEC 1024
1563
600c0e11
TW
1564
1565#define NOSLP __constant_cpu_to_le16(0), 0, 0
1566#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
b481de9c
ZY
1567#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1568#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1569 __constant_cpu_to_le32(X1), \
1570 __constant_cpu_to_le32(X2), \
1571 __constant_cpu_to_le32(X3), \
1572 __constant_cpu_to_le32(X4)}
1573
b481de9c 1574/* default power management (not Tx power) table values */
a96a27f9 1575/* for TIM 0-10 */
1125eff3 1576static struct iwl_power_vec_entry range_0[IWL39_POWER_AC] = {
b481de9c
ZY
1577 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1578 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1579 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1580 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1581 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1582 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1583};
1584
a96a27f9 1585/* for TIM > 10 */
1125eff3 1586static struct iwl_power_vec_entry range_1[IWL39_POWER_AC] = {
b481de9c
ZY
1587 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1588 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1589 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1590 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1591 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1592 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1593 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1594 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1595 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1596 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1597};
1598
4a8a4322 1599int iwl3945_power_init_handle(struct iwl_priv *priv)
b481de9c
ZY
1600{
1601 int rc = 0, i;
bb8c093b 1602 struct iwl3945_power_mgr *pow_data;
1125eff3 1603 int size = sizeof(struct iwl_power_vec_entry) * IWL39_POWER_AC;
b481de9c
ZY
1604 u16 pci_pm;
1605
1606 IWL_DEBUG_POWER("Initialize power \n");
1607
f2c7e521 1608 pow_data = &(priv->power_data_39);
b481de9c
ZY
1609
1610 memset(pow_data, 0, sizeof(*pow_data));
1611
1612 pow_data->active_index = IWL_POWER_RANGE_0;
1613 pow_data->dtim_val = 0xffff;
1614
1615 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1616 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1617
1618 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1619 if (rc != 0)
1620 return 0;
1621 else {
600c0e11 1622 struct iwl_powertable_cmd *cmd;
b481de9c
ZY
1623
1624 IWL_DEBUG_POWER("adjust power command flags\n");
1625
1125eff3 1626 for (i = 0; i < IWL39_POWER_AC; i++) {
b481de9c
ZY
1627 cmd = &pow_data->pwr_range_0[i].cmd;
1628
1629 if (pci_pm & 0x1)
1630 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1631 else
1632 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1633 }
1634 }
1635 return rc;
1636}
1637
4a8a4322 1638static int iwl3945_update_power_cmd(struct iwl_priv *priv,
600c0e11 1639 struct iwl_powertable_cmd *cmd, u32 mode)
b481de9c
ZY
1640{
1641 int rc = 0, i;
1642 u8 skip;
1643 u32 max_sleep = 0;
1125eff3 1644 struct iwl_power_vec_entry *range;
b481de9c 1645 u8 period = 0;
bb8c093b 1646 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY
1647
1648 if (mode > IWL_POWER_INDEX_5) {
1649 IWL_DEBUG_POWER("Error invalid power mode \n");
1650 return -1;
1651 }
f2c7e521 1652 pow_data = &(priv->power_data_39);
b481de9c
ZY
1653
1654 if (pow_data->active_index == IWL_POWER_RANGE_0)
1655 range = &pow_data->pwr_range_0[0];
1656 else
1657 range = &pow_data->pwr_range_1[1];
1658
bb8c093b 1659 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY
1660
1661#ifdef IWL_MAC80211_DISABLE
1662 if (priv->assoc_network != NULL) {
1663 unsigned long flags;
1664
1665 period = priv->assoc_network->tim.tim_period;
1666 }
1667#endif /*IWL_MAC80211_DISABLE */
1668 skip = range[mode].no_dtim;
1669
1670 if (period == 0) {
1671 period = 1;
1672 skip = 0;
1673 }
1674
1675 if (skip == 0) {
1676 max_sleep = period;
1677 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1678 } else {
1679 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1680 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1681 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1682 }
1683
1684 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1685 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1686 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1687 }
1688
1689 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1690 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1691 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1692 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1693 le32_to_cpu(cmd->sleep_interval[0]),
1694 le32_to_cpu(cmd->sleep_interval[1]),
1695 le32_to_cpu(cmd->sleep_interval[2]),
1696 le32_to_cpu(cmd->sleep_interval[3]),
1697 le32_to_cpu(cmd->sleep_interval[4]));
1698
1699 return rc;
1700}
1701
4a8a4322 1702static int iwl3945_send_power_mode(struct iwl_priv *priv, u32 mode)
b481de9c 1703{
9a62f73b 1704 u32 uninitialized_var(final_mode);
b481de9c 1705 int rc;
600c0e11 1706 struct iwl_powertable_cmd cmd;
b481de9c
ZY
1707
1708 /* If on battery, set to 3,
01ebd063 1709 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY
1710 * else user level */
1711 switch (mode) {
1125eff3 1712 case IWL39_POWER_BATTERY:
b481de9c
ZY
1713 final_mode = IWL_POWER_INDEX_3;
1714 break;
1125eff3 1715 case IWL39_POWER_AC:
b481de9c
ZY
1716 final_mode = IWL_POWER_MODE_CAM;
1717 break;
1718 default:
1719 final_mode = mode;
1720 break;
1721 }
1722
bb8c093b 1723 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 1724
600c0e11
TW
1725 /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
1726 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD,
1727 sizeof(struct iwl3945_powertable_cmd), &cmd);
b481de9c
ZY
1728
1729 if (final_mode == IWL_POWER_MODE_CAM)
1730 clear_bit(STATUS_POWER_PMI, &priv->status);
1731 else
1732 set_bit(STATUS_POWER_PMI, &priv->status);
1733
1734 return rc;
1735}
1736
b481de9c 1737/**
bb8c093b 1738 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY
1739 *
1740 * NOTE: priv->mutex is not required before calling this function
1741 */
4a8a4322 1742static int iwl3945_scan_cancel(struct iwl_priv *priv)
b481de9c
ZY
1743{
1744 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1745 clear_bit(STATUS_SCANNING, &priv->status);
1746 return 0;
1747 }
1748
1749 if (test_bit(STATUS_SCANNING, &priv->status)) {
1750 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1751 IWL_DEBUG_SCAN("Queuing scan abort.\n");
1752 set_bit(STATUS_SCAN_ABORTING, &priv->status);
1753 queue_work(priv->workqueue, &priv->abort_scan);
1754
1755 } else
1756 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
1757
1758 return test_bit(STATUS_SCANNING, &priv->status);
1759 }
1760
1761 return 0;
1762}
1763
1764/**
bb8c093b 1765 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY
1766 * @ms: amount of time to wait (in milliseconds) for scan to abort
1767 *
1768 * NOTE: priv->mutex must be held before calling this function
1769 */
4a8a4322 1770static int iwl3945_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms)
b481de9c
ZY
1771{
1772 unsigned long now = jiffies;
1773 int ret;
1774
bb8c093b 1775 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY
1776 if (ret && ms) {
1777 mutex_unlock(&priv->mutex);
1778 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
1779 test_bit(STATUS_SCANNING, &priv->status))
1780 msleep(1);
1781 mutex_lock(&priv->mutex);
1782
1783 return test_bit(STATUS_SCANNING, &priv->status);
1784 }
1785
1786 return ret;
1787}
1788
b481de9c
ZY
1789#define MAX_UCODE_BEACON_INTERVAL 1024
1790#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
1791
bb8c093b 1792static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY
1793{
1794 u16 new_val = 0;
1795 u16 beacon_factor = 0;
1796
1797 beacon_factor =
1798 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
1799 / MAX_UCODE_BEACON_INTERVAL;
1800 new_val = beacon_val / beacon_factor;
1801
1802 return cpu_to_le16(new_val);
1803}
1804
4a8a4322 1805static void iwl3945_setup_rxon_timing(struct iwl_priv *priv)
b481de9c
ZY
1806{
1807 u64 interval_tm_unit;
1808 u64 tsf, result;
1809 unsigned long flags;
1810 struct ieee80211_conf *conf = NULL;
1811 u16 beacon_int = 0;
1812
1813 conf = ieee80211_get_hw_conf(priv->hw);
1814
1815 spin_lock_irqsave(&priv->lock, flags);
28afaf91 1816 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
b481de9c
ZY
1817 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
1818
28afaf91 1819 tsf = priv->timestamp;
b481de9c
ZY
1820
1821 beacon_int = priv->beacon_int;
1822 spin_unlock_irqrestore(&priv->lock, flags);
1823
05c914fe 1824 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
b481de9c
ZY
1825 if (beacon_int == 0) {
1826 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
1827 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
1828 } else {
1829 priv->rxon_timing.beacon_interval =
1830 cpu_to_le16(beacon_int);
1831 priv->rxon_timing.beacon_interval =
bb8c093b 1832 iwl3945_adjust_beacon_interval(
b481de9c
ZY
1833 le16_to_cpu(priv->rxon_timing.beacon_interval));
1834 }
1835
1836 priv->rxon_timing.atim_window = 0;
1837 } else {
1838 priv->rxon_timing.beacon_interval =
bb8c093b 1839 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY
1840 /* TODO: we need to get atim_window from upper stack
1841 * for now we set to 0 */
1842 priv->rxon_timing.atim_window = 0;
1843 }
1844
1845 interval_tm_unit =
1846 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
1847 result = do_div(tsf, interval_tm_unit);
1848 priv->rxon_timing.beacon_init_val =
1849 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
1850
1851 IWL_DEBUG_ASSOC
1852 ("beacon interval %d beacon timer %d beacon tim %d\n",
1853 le16_to_cpu(priv->rxon_timing.beacon_interval),
1854 le32_to_cpu(priv->rxon_timing.beacon_init_val),
1855 le16_to_cpu(priv->rxon_timing.atim_window));
1856}
1857
4a8a4322 1858static int iwl3945_scan_initiate(struct iwl_priv *priv)
b481de9c 1859{
775a6e27 1860 if (!iwl_is_ready_rf(priv)) {
b481de9c
ZY
1861 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
1862 return -EIO;
1863 }
1864
1865 if (test_bit(STATUS_SCANNING, &priv->status)) {
1866 IWL_DEBUG_SCAN("Scan already in progress.\n");
1867 return -EAGAIN;
1868 }
1869
1870 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1871 IWL_DEBUG_SCAN("Scan request while abort pending. "
1872 "Queuing.\n");
1873 return -EAGAIN;
1874 }
1875
1876 IWL_DEBUG_INFO("Starting scan...\n");
66b5004d
RR
1877 if (priv->cfg->sku & IWL_SKU_G)
1878 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
1879 if (priv->cfg->sku & IWL_SKU_A)
1880 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY
1881 set_bit(STATUS_SCANNING, &priv->status);
1882 priv->scan_start = jiffies;
1883 priv->scan_pass_start = priv->scan_start;
1884
1885 queue_work(priv->workqueue, &priv->request_scan);
1886
1887 return 0;
1888}
1889
4a8a4322 1890static int iwl3945_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
b481de9c 1891{
f2c7e521 1892 struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
b481de9c
ZY
1893
1894 if (hw_decrypt)
1895 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
1896 else
1897 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
1898
1899 return 0;
1900}
1901
4a8a4322 1902static void iwl3945_set_flags_for_phymode(struct iwl_priv *priv,
8318d78a 1903 enum ieee80211_band band)
b481de9c 1904{
8318d78a 1905 if (band == IEEE80211_BAND_5GHZ) {
f2c7e521 1906 priv->staging39_rxon.flags &=
b481de9c
ZY
1907 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1908 | RXON_FLG_CCK_MSK);
f2c7e521 1909 priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 1910 } else {
bb8c093b 1911 /* Copied from iwl3945_bg_post_associate() */
b481de9c 1912 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
f2c7e521 1913 priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 1914 else
f2c7e521 1915 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 1916
05c914fe 1917 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
f2c7e521 1918 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 1919
f2c7e521
AK
1920 priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1921 priv->staging39_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1922 priv->staging39_rxon.flags &= ~RXON_FLG_CCK_MSK;
b481de9c
ZY
1923 }
1924}
1925
1926/*
01ebd063 1927 * initialize rxon structure with default values from eeprom
b481de9c 1928 */
4a8a4322 1929static void iwl3945_connection_init_rx_config(struct iwl_priv *priv,
60294de3 1930 int mode)
b481de9c 1931{
d20b3c65 1932 const struct iwl_channel_info *ch_info;
b481de9c 1933
f2c7e521 1934 memset(&priv->staging39_rxon, 0, sizeof(priv->staging39_rxon));
b481de9c 1935
60294de3 1936 switch (mode) {
05c914fe 1937 case NL80211_IFTYPE_AP:
f2c7e521 1938 priv->staging39_rxon.dev_type = RXON_DEV_TYPE_AP;
b481de9c
ZY
1939 break;
1940
05c914fe 1941 case NL80211_IFTYPE_STATION:
f2c7e521
AK
1942 priv->staging39_rxon.dev_type = RXON_DEV_TYPE_ESS;
1943 priv->staging39_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
b481de9c
ZY
1944 break;
1945
05c914fe 1946 case NL80211_IFTYPE_ADHOC:
f2c7e521
AK
1947 priv->staging39_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1948 priv->staging39_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1949 priv->staging39_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
b481de9c
ZY
1950 RXON_FILTER_ACCEPT_GRP_MSK;
1951 break;
1952
05c914fe 1953 case NL80211_IFTYPE_MONITOR:
f2c7e521
AK
1954 priv->staging39_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
1955 priv->staging39_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
b481de9c
ZY
1956 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
1957 break;
69dc5d9d 1958 default:
15b1687c 1959 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
69dc5d9d 1960 break;
b481de9c
ZY
1961 }
1962
1963#if 0
1964 /* TODO: Figure out when short_preamble would be set and cache from
1965 * that */
1966 if (!hw_to_local(priv->hw)->short_preamble)
f2c7e521 1967 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 1968 else
f2c7e521 1969 priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c
ZY
1970#endif
1971
8318d78a 1972 ch_info = iwl3945_get_channel_info(priv, priv->band,
f2c7e521 1973 le16_to_cpu(priv->active39_rxon.channel));
b481de9c
ZY
1974
1975 if (!ch_info)
1976 ch_info = &priv->channel_info[0];
1977
1978 /*
1979 * in some case A channels are all non IBSS
1980 * in this case force B/G channel
1981 */
60294de3 1982 if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
b481de9c
ZY
1983 ch_info = &priv->channel_info[0];
1984
f2c7e521 1985 priv->staging39_rxon.channel = cpu_to_le16(ch_info->channel);
b481de9c 1986 if (is_channel_a_band(ch_info))
8318d78a 1987 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 1988 else
8318d78a 1989 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 1990
8318d78a 1991 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c 1992
f2c7e521 1993 priv->staging39_rxon.ofdm_basic_rates =
b481de9c 1994 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
f2c7e521 1995 priv->staging39_rxon.cck_basic_rates =
b481de9c
ZY
1996 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1997}
1998
4a8a4322 1999static int iwl3945_set_mode(struct iwl_priv *priv, int mode)
b481de9c 2000{
05c914fe 2001 if (mode == NL80211_IFTYPE_ADHOC) {
d20b3c65 2002 const struct iwl_channel_info *ch_info;
b481de9c 2003
bb8c093b 2004 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2005 priv->band,
f2c7e521 2006 le16_to_cpu(priv->staging39_rxon.channel));
b481de9c
ZY
2007
2008 if (!ch_info || !is_channel_ibss(ch_info)) {
15b1687c 2009 IWL_ERR(priv, "channel %d not IBSS channel\n",
f2c7e521 2010 le16_to_cpu(priv->staging39_rxon.channel));
b481de9c
ZY
2011 return -EINVAL;
2012 }
2013 }
2014
60294de3 2015 iwl3945_connection_init_rx_config(priv, mode);
f2c7e521 2016 memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
b481de9c 2017
bb8c093b 2018 iwl3945_clear_stations_table(priv);
b481de9c 2019
a96a27f9 2020 /* don't commit rxon if rf-kill is on*/
775a6e27 2021 if (!iwl_is_ready_rf(priv))
fde3571f
MA
2022 return -EAGAIN;
2023
2024 cancel_delayed_work(&priv->scan_check);
2025 if (iwl3945_scan_cancel_timeout(priv, 100)) {
39aadf8c 2026 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
fde3571f
MA
2027 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2028 return -EAGAIN;
2029 }
2030
bb8c093b 2031 iwl3945_commit_rxon(priv);
b481de9c
ZY
2032
2033 return 0;
2034}
2035
4a8a4322 2036static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
e039fa4a 2037 struct ieee80211_tx_info *info,
c2d79b48 2038 struct iwl_cmd *cmd,
b481de9c
ZY
2039 struct sk_buff *skb_frag,
2040 int last_frag)
2041{
e52119c5 2042 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
1c014420 2043 struct iwl3945_hw_key *keyinfo =
f2c7e521 2044 &priv->stations_39[info->control.hw_key->hw_key_idx].keyinfo;
b481de9c
ZY
2045
2046 switch (keyinfo->alg) {
2047 case ALG_CCMP:
e52119c5
WT
2048 tx->sec_ctl = TX_CMD_SEC_CCM;
2049 memcpy(tx->key, keyinfo->key, keyinfo->keylen);
a96a27f9 2050 IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
b481de9c
ZY
2051 break;
2052
2053 case ALG_TKIP:
2054#if 0
e52119c5 2055 tx->sec_ctl = TX_CMD_SEC_TKIP;
b481de9c
ZY
2056
2057 if (last_frag)
e52119c5 2058 memcpy(tx->tkip_mic.byte, skb_frag->tail - 8,
b481de9c
ZY
2059 8);
2060 else
e52119c5 2061 memset(tx->tkip_mic.byte, 0, 8);
b481de9c
ZY
2062#endif
2063 break;
2064
2065 case ALG_WEP:
e52119c5 2066 tx->sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 2067 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY
2068
2069 if (keyinfo->keylen == 13)
e52119c5 2070 tx->sec_ctl |= TX_CMD_SEC_KEY128;
b481de9c 2071
e52119c5 2072 memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen);
b481de9c
ZY
2073
2074 IWL_DEBUG_TX("Configuring packet for WEP encryption "
e039fa4a 2075 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY
2076 break;
2077
b481de9c 2078 default:
978785a3 2079 IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
b481de9c
ZY
2080 break;
2081 }
2082}
2083
2084/*
2085 * handle build REPLY_TX command notification.
2086 */
4a8a4322 2087static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
c2d79b48 2088 struct iwl_cmd *cmd,
e039fa4a 2089 struct ieee80211_tx_info *info,
e52119c5 2090 struct ieee80211_hdr *hdr, u8 std_id)
b481de9c 2091{
e52119c5
WT
2092 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
2093 __le32 tx_flags = tx->tx_flags;
fd7c8a40 2094 __le16 fc = hdr->frame_control;
e6a9854b 2095 u8 rc_flags = info->control.rates[0].flags;
b481de9c 2096
e52119c5 2097 tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 2098 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 2099 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 2100 if (ieee80211_is_mgmt(fc))
b481de9c 2101 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 2102 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY
2103 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2104 tx_flags |= TX_CMD_FLG_TSF_MSK;
2105 } else {
2106 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2107 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2108 }
2109
e52119c5 2110 tx->sta_id = std_id;
8b7b1e05 2111 if (ieee80211_has_morefrags(fc))
b481de9c
ZY
2112 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2113
fd7c8a40
HH
2114 if (ieee80211_is_data_qos(fc)) {
2115 u8 *qc = ieee80211_get_qos_ctl(hdr);
e52119c5 2116 tx->tid_tspec = qc[0] & 0xf;
b481de9c 2117 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2118 } else {
b481de9c 2119 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2120 }
b481de9c 2121
e6a9854b 2122 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
b481de9c
ZY
2123 tx_flags |= TX_CMD_FLG_RTS_MSK;
2124 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 2125 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
b481de9c
ZY
2126 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2127 tx_flags |= TX_CMD_FLG_CTS_MSK;
2128 }
2129
2130 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2131 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2132
2133 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH
2134 if (ieee80211_is_mgmt(fc)) {
2135 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
e52119c5 2136 tx->timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2137 else
e52119c5 2138 tx->timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2139 } else {
e52119c5 2140 tx->timeout.pm_frame_timeout = 0;
ab53d8af
MA
2141#ifdef CONFIG_IWL3945_LEDS
2142 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2143#endif
2144 }
b481de9c 2145
e52119c5
WT
2146 tx->driver_txop = 0;
2147 tx->tx_flags = tx_flags;
2148 tx->next_frame_len = 0;
b481de9c
ZY
2149}
2150
6440adb5
CB
2151/**
2152 * iwl3945_get_sta_id - Find station's index within station table
2153 */
4a8a4322 2154static int iwl3945_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY
2155{
2156 int sta_id;
2157 u16 fc = le16_to_cpu(hdr->frame_control);
2158
6440adb5 2159 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY
2160 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2161 is_multicast_ether_addr(hdr->addr1))
3832ec9d 2162 return priv->hw_params.bcast_sta_id;
b481de9c
ZY
2163
2164 switch (priv->iw_mode) {
2165
6440adb5
CB
2166 /* If we are a client station in a BSS network, use the special
2167 * AP station entry (that's the only station we communicate with) */
05c914fe 2168 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2169 return IWL_AP_ID;
2170
2171 /* If we are an AP, then find the station, or use BCAST */
05c914fe 2172 case NL80211_IFTYPE_AP:
bb8c093b 2173 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY
2174 if (sta_id != IWL_INVALID_STATION)
2175 return sta_id;
3832ec9d 2176 return priv->hw_params.bcast_sta_id;
b481de9c 2177
6440adb5
CB
2178 /* If this frame is going out to an IBSS network, find the station,
2179 * or create a new station table entry */
05c914fe 2180 case NL80211_IFTYPE_ADHOC: {
6440adb5 2181 /* Create new station table entry */
bb8c093b 2182 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY
2183 if (sta_id != IWL_INVALID_STATION)
2184 return sta_id;
2185
bb8c093b 2186 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY
2187
2188 if (sta_id != IWL_INVALID_STATION)
2189 return sta_id;
2190
e174961c 2191 IWL_DEBUG_DROP("Station %pM not in station map. "
b481de9c 2192 "Defaulting to broadcast...\n",
e174961c 2193 hdr->addr1);
40b8ec0b 2194 iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
3832ec9d 2195 return priv->hw_params.bcast_sta_id;
0795af57 2196 }
914233d6
SG
2197 /* If we are in monitor mode, use BCAST. This is required for
2198 * packet injection. */
05c914fe 2199 case NL80211_IFTYPE_MONITOR:
3832ec9d 2200 return priv->hw_params.bcast_sta_id;
914233d6 2201
b481de9c 2202 default:
39aadf8c
WT
2203 IWL_WARN(priv, "Unknown mode of operation: %d\n",
2204 priv->iw_mode);
3832ec9d 2205 return priv->hw_params.bcast_sta_id;
b481de9c
ZY
2206 }
2207}
2208
2209/*
2210 * start REPLY_TX command process
2211 */
4a8a4322 2212static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
b481de9c
ZY
2213{
2214 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 2215 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
dbb6654c 2216 struct iwl3945_tfd *tfd;
e52119c5 2217 struct iwl3945_tx_cmd *tx;
188cf6c7 2218 struct iwl_tx_queue *txq = NULL;
d20b3c65 2219 struct iwl_queue *q = NULL;
e52119c5 2220 struct iwl_cmd *out_cmd = NULL;
b481de9c
ZY
2221 dma_addr_t phys_addr;
2222 dma_addr_t txcmd_phys;
e52119c5 2223 int txq_id = skb_get_queue_mapping(skb);
54dbb525
TW
2224 u16 len, idx, len_org, hdr_len;
2225 u8 id;
2226 u8 unicast;
b481de9c 2227 u8 sta_id;
54dbb525 2228 u8 tid = 0;
b481de9c 2229 u16 seq_number = 0;
fd7c8a40 2230 __le16 fc;
b481de9c 2231 u8 wait_write_ptr = 0;
54dbb525 2232 u8 *qc = NULL;
b481de9c
ZY
2233 unsigned long flags;
2234 int rc;
2235
2236 spin_lock_irqsave(&priv->lock, flags);
775a6e27 2237 if (iwl_is_rfkill(priv)) {
b481de9c
ZY
2238 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2239 goto drop_unlock;
2240 }
2241
e039fa4a 2242 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
15b1687c 2243 IWL_ERR(priv, "ERROR: No TX rate available.\n");
b481de9c
ZY
2244 goto drop_unlock;
2245 }
2246
2247 unicast = !is_multicast_ether_addr(hdr->addr1);
2248 id = 0;
2249
fd7c8a40 2250 fc = hdr->frame_control;
b481de9c 2251
c8b0e6e1 2252#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
2253 if (ieee80211_is_auth(fc))
2254 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 2255 else if (ieee80211_is_assoc_req(fc))
b481de9c 2256 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 2257 else if (ieee80211_is_reassoc_req(fc))
b481de9c
ZY
2258 IWL_DEBUG_TX("Sending REASSOC frame\n");
2259#endif
2260
7878a5a4 2261 /* drop all data frame if we are not associated */
914233d6 2262 if (ieee80211_is_data(fc) &&
05c914fe 2263 (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
914233d6 2264 (!iwl3945_is_associated(priv) ||
05c914fe 2265 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
bb8c093b 2266 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY
2267 goto drop_unlock;
2268 }
2269
2270 spin_unlock_irqrestore(&priv->lock, flags);
2271
7294ec95 2272 hdr_len = ieee80211_hdrlen(fc);
6440adb5
CB
2273
2274 /* Find (or create) index into station table for destination station */
bb8c093b 2275 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2276 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB
2277 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
2278 hdr->addr1);
b481de9c
ZY
2279 goto drop;
2280 }
2281
2282 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2283
fd7c8a40
HH
2284 if (ieee80211_is_data_qos(fc)) {
2285 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 2286 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
f2c7e521 2287 seq_number = priv->stations_39[sta_id].tid[tid].seq_number &
b481de9c
ZY
2288 IEEE80211_SCTL_SEQ;
2289 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2290 (hdr->seq_ctrl &
2291 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2292 seq_number += 0x10;
2293 }
6440adb5
CB
2294
2295 /* Descriptor for chosen Tx queue */
188cf6c7 2296 txq = &priv->txq[txq_id];
b481de9c
ZY
2297 q = &txq->q;
2298
2299 spin_lock_irqsave(&priv->lock, flags);
2300
6440adb5 2301 /* Set up first empty TFD within this queue's circular TFD buffer */
188cf6c7 2302 tfd = &txq->tfds39[q->write_ptr];
b481de9c 2303 memset(tfd, 0, sizeof(*tfd));
fc4b6853 2304 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2305
6440adb5 2306 /* Set up driver data for this TFD */
dbb6654c 2307 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
fc4b6853 2308 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB
2309
2310 /* Init first empty entry in queue's array of Tx/cmd buffers */
188cf6c7 2311 out_cmd = txq->cmd[idx];
e52119c5 2312 tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
b481de9c 2313 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
e52119c5 2314 memset(tx, 0, sizeof(*tx));
6440adb5
CB
2315
2316 /*
2317 * Set up the Tx-command (not MAC!) header.
2318 * Store the chosen Tx queue and TFD index within the sequence field;
2319 * after Tx, uCode's Tx response will return this value so driver can
2320 * locate the frame within the tx queue and do post-tx processing.
2321 */
b481de9c
ZY
2322 out_cmd->hdr.cmd = REPLY_TX;
2323 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2324 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB
2325
2326 /* Copy MAC header from skb into command buffer */
e52119c5 2327 memcpy(tx->hdr, hdr, hdr_len);
b481de9c 2328
6440adb5
CB
2329 /*
2330 * Use the first empty entry in this queue's command buffer array
2331 * to contain the Tx command and MAC header concatenated together
2332 * (payload data will be in another buffer).
2333 * Size of this varies, due to varying MAC header length.
2334 * If end is not dword aligned, we'll have 2 extra bytes at the end
2335 * of the MAC header (device reads on dword boundaries).
2336 * We'll tell device about this padding later.
2337 */
3832ec9d 2338 len = sizeof(struct iwl3945_tx_cmd) +
4c897253 2339 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY
2340
2341 len_org = len;
2342 len = (len + 3) & ~3;
2343
2344 if (len_org != len)
2345 len_org = 1;
2346 else
2347 len_org = 0;
2348
6440adb5
CB
2349 /* Physical address of this Tx command's header (not MAC header!),
2350 * within command buffer array. */
188cf6c7
SO
2351 txcmd_phys = pci_map_single(priv->pci_dev,
2352 out_cmd, sizeof(struct iwl_cmd),
2353 PCI_DMA_TODEVICE);
2354 pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
2355 pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
2356 /* Add buffer containing Tx command and MAC(!) header to TFD's
2357 * first entry */
2358 txcmd_phys += offsetof(struct iwl_cmd, hdr);
b481de9c 2359
6440adb5
CB
2360 /* Add buffer containing Tx command and MAC(!) header to TFD's
2361 * first entry */
bb8c093b 2362 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c 2363
d0f09804 2364 if (info->control.hw_key)
e039fa4a 2365 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
b481de9c 2366
6440adb5
CB
2367 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2368 * if any (802.11 null frames have no payload). */
b481de9c
ZY
2369 len = skb->len - hdr_len;
2370 if (len) {
2371 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2372 len, PCI_DMA_TODEVICE);
bb8c093b 2373 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY
2374 }
2375
b481de9c 2376 if (!len)
6440adb5 2377 /* If there is no payload, then we use only one Tx buffer */
dbb6654c 2378 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(1));
b481de9c 2379 else
6440adb5
CB
2380 /* Else use 2 buffers.
2381 * Tell 3945 about any padding after MAC header */
dbb6654c
WT
2382 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(2) |
2383 TFD_CTL_PAD_SET(U32_PAD(len)));
b481de9c 2384
6440adb5 2385 /* Total # bytes to be transmitted */
b481de9c 2386 len = (u16)skb->len;
e52119c5 2387 tx->len = cpu_to_le16(len);
b481de9c
ZY
2388
2389 /* TODO need this for burst mode later on */
e52119c5 2390 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
b481de9c
ZY
2391
2392 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 2393 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
b481de9c 2394
e52119c5
WT
2395 tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2396 tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
b481de9c 2397
8b7b1e05 2398 if (!ieee80211_has_morefrags(hdr->frame_control)) {
b481de9c 2399 txq->need_update = 1;
3ac7f146 2400 if (qc)
f2c7e521 2401 priv->stations_39[sta_id].tid[tid].seq_number = seq_number;
b481de9c
ZY
2402 } else {
2403 wait_write_ptr = 1;
2404 txq->need_update = 0;
2405 }
2406
e52119c5 2407 iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx));
b481de9c 2408
e52119c5 2409 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr,
7294ec95 2410 ieee80211_hdrlen(fc));
b481de9c 2411
6440adb5 2412 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2413 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2414 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
2415 spin_unlock_irqrestore(&priv->lock, flags);
2416
2417 if (rc)
2418 return rc;
2419
d20b3c65 2420 if ((iwl_queue_space(q) < q->high_mark)
b481de9c
ZY
2421 && priv->mac80211_registered) {
2422 if (wait_write_ptr) {
2423 spin_lock_irqsave(&priv->lock, flags);
2424 txq->need_update = 1;
bb8c093b 2425 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY
2426 spin_unlock_irqrestore(&priv->lock, flags);
2427 }
2428
e2530083 2429 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
b481de9c
ZY
2430 }
2431
2432 return 0;
2433
2434drop_unlock:
2435 spin_unlock_irqrestore(&priv->lock, flags);
2436drop:
2437 return -1;
2438}
2439
4a8a4322 2440static void iwl3945_set_rate(struct iwl_priv *priv)
b481de9c 2441{
8318d78a 2442 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY
2443 struct ieee80211_rate *rate;
2444 int i;
2445
cbba18c6 2446 sband = iwl_get_hw_mode(priv, priv->band);
8318d78a 2447 if (!sband) {
15b1687c 2448 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
c4ba9621
SA
2449 return;
2450 }
b481de9c
ZY
2451
2452 priv->active_rate = 0;
2453 priv->active_rate_basic = 0;
2454
8318d78a
JB
2455 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2456 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2457
2458 for (i = 0; i < sband->n_bitrates; i++) {
2459 rate = &sband->bitrates[i];
2460 if ((rate->hw_value < IWL_RATE_COUNT) &&
2461 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2462 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2463 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2464 priv->active_rate |= (1 << rate->hw_value);
2465 }
b481de9c
ZY
2466 }
2467
2468 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2469 priv->active_rate, priv->active_rate_basic);
2470
2471 /*
2472 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2473 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2474 * OFDM
2475 */
2476 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
f2c7e521 2477 priv->staging39_rxon.cck_basic_rates =
b481de9c
ZY
2478 ((priv->active_rate_basic &
2479 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2480 else
f2c7e521 2481 priv->staging39_rxon.cck_basic_rates =
b481de9c
ZY
2482 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2483
2484 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
f2c7e521 2485 priv->staging39_rxon.ofdm_basic_rates =
b481de9c
ZY
2486 ((priv->active_rate_basic &
2487 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2488 IWL_FIRST_OFDM_RATE) & 0xFF;
2489 else
f2c7e521 2490 priv->staging39_rxon.ofdm_basic_rates =
b481de9c
ZY
2491 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2492}
2493
4a8a4322 2494static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
b481de9c
ZY
2495{
2496 unsigned long flags;
2497
2498 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2499 return;
2500
2501 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2502 disable_radio ? "OFF" : "ON");
2503
2504 if (disable_radio) {
bb8c093b 2505 iwl3945_scan_cancel(priv);
b481de9c 2506 /* FIXME: This is a workaround for AP */
05c914fe 2507 if (priv->iw_mode != NL80211_IFTYPE_AP) {
b481de9c 2508 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2509 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
2510 CSR_UCODE_SW_BIT_RFKILL);
2511 spin_unlock_irqrestore(&priv->lock, flags);
c496294e 2512 iwl_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY
2513 set_bit(STATUS_RF_KILL_SW, &priv->status);
2514 }
2515 return;
2516 }
2517
2518 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2519 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2520
2521 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2522 spin_unlock_irqrestore(&priv->lock, flags);
2523
2524 /* wake up ucode */
2525 msleep(10);
2526
2527 spin_lock_irqsave(&priv->lock, flags);
5d49f498
AK
2528 iwl_read32(priv, CSR_UCODE_DRV_GP1);
2529 if (!iwl_grab_nic_access(priv))
2530 iwl_release_nic_access(priv);
b481de9c
ZY
2531 spin_unlock_irqrestore(&priv->lock, flags);
2532
2533 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2534 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2535 "disabled by HW switch\n");
2536 return;
2537 }
2538
808e72a0
ZY
2539 if (priv->is_open)
2540 queue_work(priv->workqueue, &priv->restart);
b481de9c
ZY
2541 return;
2542}
2543
4a8a4322 2544void iwl3945_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
b481de9c
ZY
2545 u32 decrypt_res, struct ieee80211_rx_status *stats)
2546{
2547 u16 fc =
2548 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2549
f2c7e521 2550 if (priv->active39_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
b481de9c
ZY
2551 return;
2552
2553 if (!(fc & IEEE80211_FCTL_PROTECTED))
2554 return;
2555
2556 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2557 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2558 case RX_RES_STATUS_SEC_TYPE_TKIP:
2559 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2560 RX_RES_STATUS_BAD_ICV_MIC)
2561 stats->flag |= RX_FLAG_MMIC_ERROR;
2562 case RX_RES_STATUS_SEC_TYPE_WEP:
2563 case RX_RES_STATUS_SEC_TYPE_CCMP:
2564 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2565 RX_RES_STATUS_DECRYPT_OK) {
2566 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2567 stats->flag |= RX_FLAG_DECRYPTED;
2568 }
2569 break;
2570
2571 default:
2572 break;
2573 }
2574}
2575
c8b0e6e1 2576#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
2577
2578#include "iwl-spectrum.h"
2579
2580#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2581#define BEACON_TIME_MASK_HIGH 0xFF000000
2582#define TIME_UNIT 1024
2583
2584/*
2585 * extended beacon time format
2586 * time in usec will be changed into a 32-bit value in 8:24 format
2587 * the high 1 byte is the beacon counts
2588 * the lower 3 bytes is the time in usec within one beacon interval
2589 */
2590
bb8c093b 2591static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
2592{
2593 u32 quot;
2594 u32 rem;
2595 u32 interval = beacon_interval * 1024;
2596
2597 if (!interval || !usec)
2598 return 0;
2599
2600 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
2601 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
2602
2603 return (quot << 24) + rem;
2604}
2605
2606/* base is usually what we get from ucode with each received frame,
2607 * the same as HW timer counter counting down
2608 */
2609
bb8c093b 2610static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
2611{
2612 u32 base_low = base & BEACON_TIME_MASK_LOW;
2613 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
2614 u32 interval = beacon_interval * TIME_UNIT;
2615 u32 res = (base & BEACON_TIME_MASK_HIGH) +
2616 (addon & BEACON_TIME_MASK_HIGH);
2617
2618 if (base_low > addon_low)
2619 res += base_low - addon_low;
2620 else if (base_low < addon_low) {
2621 res += interval + base_low - addon_low;
2622 res += (1 << 24);
2623 } else
2624 res += (1 << 24);
2625
2626 return cpu_to_le32(res);
2627}
2628
4a8a4322 2629static int iwl3945_get_measurement(struct iwl_priv *priv,
b481de9c
ZY
2630 struct ieee80211_measurement_params *params,
2631 u8 type)
2632{
600c0e11 2633 struct iwl_spectrum_cmd spectrum;
3d24a9f7 2634 struct iwl_rx_packet *res;
c2d79b48 2635 struct iwl_host_cmd cmd = {
b481de9c
ZY
2636 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
2637 .data = (void *)&spectrum,
2638 .meta.flags = CMD_WANT_SKB,
2639 };
2640 u32 add_time = le64_to_cpu(params->start_time);
2641 int rc;
2642 int spectrum_resp_status;
2643 int duration = le16_to_cpu(params->duration);
2644
bb8c093b 2645 if (iwl3945_is_associated(priv))
b481de9c 2646 add_time =
bb8c093b 2647 iwl3945_usecs_to_beacons(
b481de9c
ZY
2648 le64_to_cpu(params->start_time) - priv->last_tsf,
2649 le16_to_cpu(priv->rxon_timing.beacon_interval));
2650
2651 memset(&spectrum, 0, sizeof(spectrum));
2652
2653 spectrum.channel_count = cpu_to_le16(1);
2654 spectrum.flags =
2655 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
2656 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
2657 cmd.len = sizeof(spectrum);
2658 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
2659
bb8c093b 2660 if (iwl3945_is_associated(priv))
b481de9c 2661 spectrum.start_time =
bb8c093b 2662 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
2663 add_time,
2664 le16_to_cpu(priv->rxon_timing.beacon_interval));
2665 else
2666 spectrum.start_time = 0;
2667
2668 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
2669 spectrum.channels[0].channel = params->channel;
2670 spectrum.channels[0].type = type;
f2c7e521 2671 if (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK)
b481de9c
ZY
2672 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
2673 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
2674
bb8c093b 2675 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
2676 if (rc)
2677 return rc;
2678
3d24a9f7 2679 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c 2680 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 2681 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
b481de9c
ZY
2682 rc = -EIO;
2683 }
2684
2685 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
2686 switch (spectrum_resp_status) {
2687 case 0: /* Command will be handled */
2688 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS
2689 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
2690 res->u.spectrum.id);
b481de9c
ZY
2691 priv->measurement_status &= ~MEASUREMENT_READY;
2692 }
2693 priv->measurement_status |= MEASUREMENT_ACTIVE;
2694 rc = 0;
2695 break;
2696
2697 case 1: /* Command will not be handled */
2698 rc = -EAGAIN;
2699 break;
2700 }
2701
2702 dev_kfree_skb_any(cmd.meta.u.skb);
2703
2704 return rc;
2705}
2706#endif
2707
4a8a4322 2708static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
6100b588 2709 struct iwl_rx_mem_buffer *rxb)
b481de9c 2710{
3d24a9f7
TW
2711 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
2712 struct iwl_alive_resp *palive;
b481de9c
ZY
2713 struct delayed_work *pwork;
2714
2715 palive = &pkt->u.alive_frame;
2716
2717 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
2718 "0x%01X 0x%01X\n",
2719 palive->is_valid, palive->ver_type,
2720 palive->ver_subtype);
2721
2722 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
2723 IWL_DEBUG_INFO("Initialization Alive received.\n");
3d24a9f7
TW
2724 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
2725 sizeof(struct iwl_alive_resp));
b481de9c
ZY
2726 pwork = &priv->init_alive_start;
2727 } else {
2728 IWL_DEBUG_INFO("Runtime Alive received.\n");
2729 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 2730 sizeof(struct iwl_alive_resp));
b481de9c 2731 pwork = &priv->alive_start;
bb8c093b 2732 iwl3945_disable_events(priv);
b481de9c
ZY
2733 }
2734
2735 /* We delay the ALIVE response by 5ms to
2736 * give the HW RF Kill time to activate... */
2737 if (palive->is_valid == UCODE_VALID_OK)
2738 queue_delayed_work(priv->workqueue, pwork,
2739 msecs_to_jiffies(5));
2740 else
39aadf8c 2741 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
2742}
2743
4a8a4322 2744static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
6100b588 2745 struct iwl_rx_mem_buffer *rxb)
b481de9c 2746{
c7e035a9 2747#ifdef CONFIG_IWLWIFI_DEBUG
3d24a9f7 2748 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
c7e035a9 2749#endif
b481de9c
ZY
2750
2751 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
2752 return;
2753}
2754
4a8a4322 2755static void iwl3945_rx_reply_error(struct iwl_priv *priv,
6100b588 2756 struct iwl_rx_mem_buffer *rxb)
b481de9c 2757{
3d24a9f7 2758 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 2759
15b1687c 2760 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
b481de9c
ZY
2761 "seq 0x%04X ser 0x%08X\n",
2762 le32_to_cpu(pkt->u.err_resp.error_type),
2763 get_cmd_string(pkt->u.err_resp.cmd_id),
2764 pkt->u.err_resp.cmd_id,
2765 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2766 le32_to_cpu(pkt->u.err_resp.error_info));
2767}
2768
2769#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
2770
4a8a4322 2771static void iwl3945_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
b481de9c 2772{
3d24a9f7 2773 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
f2c7e521 2774 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active39_rxon;
600c0e11 2775 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY
2776 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
2777 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
2778 rxon->channel = csa->channel;
f2c7e521 2779 priv->staging39_rxon.channel = csa->channel;
b481de9c
ZY
2780}
2781
4a8a4322 2782static void iwl3945_rx_spectrum_measure_notif(struct iwl_priv *priv,
6100b588 2783 struct iwl_rx_mem_buffer *rxb)
b481de9c 2784{
c8b0e6e1 2785#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
3d24a9f7 2786 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
600c0e11 2787 struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY
2788
2789 if (!report->state) {
2790 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
2791 "Spectrum Measure Notification: Start\n");
2792 return;
2793 }
2794
2795 memcpy(&priv->measure_report, report, sizeof(*report));
2796 priv->measurement_status |= MEASUREMENT_READY;
2797#endif
2798}
2799
4a8a4322 2800static void iwl3945_rx_pm_sleep_notif(struct iwl_priv *priv,
6100b588 2801 struct iwl_rx_mem_buffer *rxb)
b481de9c 2802{
c8b0e6e1 2803#ifdef CONFIG_IWL3945_DEBUG
3d24a9f7 2804 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
600c0e11 2805 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY
2806 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
2807 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2808#endif
2809}
2810
4a8a4322 2811static void iwl3945_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
6100b588 2812 struct iwl_rx_mem_buffer *rxb)
b481de9c 2813{
3d24a9f7 2814 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
2815 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
2816 "notification for %s:\n",
2817 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
40b8ec0b
SO
2818 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw,
2819 le32_to_cpu(pkt->len));
b481de9c
ZY
2820}
2821
bb8c093b 2822static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 2823{
4a8a4322
AK
2824 struct iwl_priv *priv =
2825 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
2826 struct sk_buff *beacon;
2827
2828 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 2829 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
2830
2831 if (!beacon) {
15b1687c 2832 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
2833 return;
2834 }
2835
2836 mutex_lock(&priv->mutex);
2837 /* new beacon skb is allocated every time; dispose previous.*/
2838 if (priv->ibss_beacon)
2839 dev_kfree_skb(priv->ibss_beacon);
2840
2841 priv->ibss_beacon = beacon;
2842 mutex_unlock(&priv->mutex);
2843
bb8c093b 2844 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
2845}
2846
4a8a4322 2847static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
6100b588 2848 struct iwl_rx_mem_buffer *rxb)
b481de9c 2849{
c8b0e6e1 2850#ifdef CONFIG_IWL3945_DEBUG
3d24a9f7 2851 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b 2852 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
2853 u8 rate = beacon->beacon_notify_hdr.rate;
2854
2855 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
2856 "tsf %d %d rate %d\n",
2857 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
2858 beacon->beacon_notify_hdr.failure_frame,
2859 le32_to_cpu(beacon->ibss_mgr_status),
2860 le32_to_cpu(beacon->high_tsf),
2861 le32_to_cpu(beacon->low_tsf), rate);
2862#endif
2863
05c914fe 2864 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
2865 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
2866 queue_work(priv->workqueue, &priv->beacon_update);
2867}
2868
2869/* Service response to REPLY_SCAN_CMD (0x80) */
4a8a4322 2870static void iwl3945_rx_reply_scan(struct iwl_priv *priv,
6100b588 2871 struct iwl_rx_mem_buffer *rxb)
b481de9c 2872{
c8b0e6e1 2873#ifdef CONFIG_IWL3945_DEBUG
3d24a9f7 2874 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253
TW
2875 struct iwl_scanreq_notification *notif =
2876 (struct iwl_scanreq_notification *)pkt->u.raw;
b481de9c
ZY
2877
2878 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
2879#endif
2880}
2881
2882/* Service SCAN_START_NOTIFICATION (0x82) */
4a8a4322 2883static void iwl3945_rx_scan_start_notif(struct iwl_priv *priv,
6100b588 2884 struct iwl_rx_mem_buffer *rxb)
b481de9c 2885{
3d24a9f7 2886 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253
TW
2887 struct iwl_scanstart_notification *notif =
2888 (struct iwl_scanstart_notification *)pkt->u.raw;
b481de9c
ZY
2889 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
2890 IWL_DEBUG_SCAN("Scan start: "
2891 "%d [802.11%s] "
2892 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
2893 notif->channel,
2894 notif->band ? "bg" : "a",
2895 notif->tsf_high,
2896 notif->tsf_low, notif->status, notif->beacon_timer);
2897}
2898
2899/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
4a8a4322 2900static void iwl3945_rx_scan_results_notif(struct iwl_priv *priv,
6100b588 2901 struct iwl_rx_mem_buffer *rxb)
b481de9c 2902{
c7e035a9 2903#ifdef CONFIG_IWLWIFI_DEBUG
3d24a9f7 2904 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253
TW
2905 struct iwl_scanresults_notification *notif =
2906 (struct iwl_scanresults_notification *)pkt->u.raw;
c7e035a9 2907#endif
b481de9c
ZY
2908
2909 IWL_DEBUG_SCAN("Scan ch.res: "
2910 "%d [802.11%s] "
2911 "(TSF: 0x%08X:%08X) - %d "
2912 "elapsed=%lu usec (%dms since last)\n",
2913 notif->channel,
2914 notif->band ? "bg" : "a",
2915 le32_to_cpu(notif->tsf_high),
2916 le32_to_cpu(notif->tsf_low),
2917 le32_to_cpu(notif->statistics[0]),
2918 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
2919 jiffies_to_msecs(elapsed_jiffies
2920 (priv->last_scan_jiffies, jiffies)));
2921
2922 priv->last_scan_jiffies = jiffies;
7878a5a4 2923 priv->next_scan_jiffies = 0;
b481de9c
ZY
2924}
2925
2926/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
4a8a4322 2927static void iwl3945_rx_scan_complete_notif(struct iwl_priv *priv,
6100b588 2928 struct iwl_rx_mem_buffer *rxb)
b481de9c 2929{
c7e035a9 2930#ifdef CONFIG_IWLWIFI_DEBUG
3d24a9f7 2931 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253 2932 struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
c7e035a9 2933#endif
b481de9c
ZY
2934
2935 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
2936 scan_notif->scanned_channels,
2937 scan_notif->tsf_low,
2938 scan_notif->tsf_high, scan_notif->status);
2939
2940 /* The HW is no longer scanning */
2941 clear_bit(STATUS_SCAN_HW, &priv->status);
2942
2943 /* The scan completion notification came in, so kill that timer... */
2944 cancel_delayed_work(&priv->scan_check);
2945
2946 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
66b5004d
RR
2947 (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
2948 "2.4" : "5.2",
b481de9c
ZY
2949 jiffies_to_msecs(elapsed_jiffies
2950 (priv->scan_pass_start, jiffies)));
2951
66b5004d
RR
2952 /* Remove this scanned band from the list of pending
2953 * bands to scan, band G precedes A in order of scanning
2954 * as seen in iwl3945_bg_request_scan */
2955 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
2956 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
2957 else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
2958 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY
2959
2960 /* If a request to abort was given, or the scan did not succeed
2961 * then we reset the scan state machine and terminate,
2962 * re-queuing another scan if one has been requested */
2963 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2964 IWL_DEBUG_INFO("Aborted scan completed.\n");
2965 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
2966 } else {
2967 /* If there are more bands on this scan pass reschedule */
2968 if (priv->scan_bands > 0)
2969 goto reschedule;
2970 }
2971
2972 priv->last_scan_jiffies = jiffies;
7878a5a4 2973 priv->next_scan_jiffies = 0;
b481de9c
ZY
2974 IWL_DEBUG_INFO("Setting scan to off\n");
2975
2976 clear_bit(STATUS_SCANNING, &priv->status);
2977
2978 IWL_DEBUG_INFO("Scan took %dms\n",
2979 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
2980
2981 queue_work(priv->workqueue, &priv->scan_completed);
2982
2983 return;
2984
2985reschedule:
2986 priv->scan_pass_start = jiffies;
2987 queue_work(priv->workqueue, &priv->request_scan);
2988}
2989
2990/* Handle notification from uCode that card's power state is changing
2991 * due to software, hardware, or critical temperature RFKILL */
4a8a4322 2992static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
6100b588 2993 struct iwl_rx_mem_buffer *rxb)
b481de9c 2994{
3d24a9f7 2995 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY
2996 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
2997 unsigned long status = priv->status;
2998
2999 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3000 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3001 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3002
5d49f498 3003 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
3004 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3005
3006 if (flags & HW_CARD_DISABLED)
3007 set_bit(STATUS_RF_KILL_HW, &priv->status);
3008 else
3009 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3010
3011
3012 if (flags & SW_CARD_DISABLED)
3013 set_bit(STATUS_RF_KILL_SW, &priv->status);
3014 else
3015 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3016
bb8c093b 3017 iwl3945_scan_cancel(priv);
b481de9c
ZY
3018
3019 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3020 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3021 (test_bit(STATUS_RF_KILL_SW, &status) !=
3022 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3023 queue_work(priv->workqueue, &priv->rf_kill);
3024 else
3025 wake_up_interruptible(&priv->wait_command_queue);
3026}
3027
3028/**
bb8c093b 3029 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
3030 *
3031 * Setup the RX handlers for each of the reply types sent from the uCode
3032 * to the host.
3033 *
3034 * This function chains into the hardware specific files for them to setup
3035 * any hardware specific handlers as well.
3036 */
4a8a4322 3037static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 3038{
bb8c093b
CH
3039 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3040 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3041 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3042 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3043 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH
3044 iwl3945_rx_spectrum_measure_notif;
3045 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3046 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH
3047 iwl3945_rx_pm_debug_statistics_notif;
3048 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3049
9fbab516
BC
3050 /*
3051 * The same handler is used for both the REPLY to a discrete
3052 * statistics request from the host as well as for the periodic
3053 * statistics notifications (after received beacons) from the uCode.
b481de9c 3054 */
bb8c093b
CH
3055 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3056 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3057
bb8c093b
CH
3058 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3059 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3060 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3061 iwl3945_rx_scan_results_notif;
b481de9c 3062 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH
3063 iwl3945_rx_scan_complete_notif;
3064 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 3065
9fbab516 3066 /* Set up hardware specific Rx handlers */
bb8c093b 3067 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
3068}
3069
91c066f2
TW
3070/**
3071 * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3072 * When FW advances 'R' index, all entries between old and new 'R' index
3073 * need to be reclaimed.
3074 */
4a8a4322 3075static void iwl3945_cmd_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW
3076 int txq_id, int index)
3077{
188cf6c7 3078 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 3079 struct iwl_queue *q = &txq->q;
91c066f2
TW
3080 int nfreed = 0;
3081
625a381a 3082 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
15b1687c 3083 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
91c066f2
TW
3084 "is out of range [0-%d] %d %d.\n", txq_id,
3085 index, q->n_bd, q->write_ptr, q->read_ptr);
3086 return;
3087 }
3088
3089 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3090 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3091 if (nfreed > 1) {
15b1687c 3092 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", index,
91c066f2
TW
3093 q->write_ptr, q->read_ptr);
3094 queue_work(priv->workqueue, &priv->restart);
3095 break;
3096 }
3097 nfreed++;
3098 }
3099}
3100
3101
b481de9c 3102/**
bb8c093b 3103 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY
3104 * @rxb: Rx buffer to reclaim
3105 *
3106 * If an Rx buffer has an async callback associated with it the callback
3107 * will be executed. The attached skb (if present) will only be freed
3108 * if the callback returns 1
3109 */
4a8a4322 3110static void iwl3945_tx_cmd_complete(struct iwl_priv *priv,
6100b588 3111 struct iwl_rx_mem_buffer *rxb)
b481de9c 3112{
3d24a9f7 3113 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
3114 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3115 int txq_id = SEQ_TO_QUEUE(sequence);
3116 int index = SEQ_TO_INDEX(sequence);
600c0e11 3117 int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
b481de9c 3118 int cmd_index;
c2d79b48 3119 struct iwl_cmd *cmd;
b481de9c 3120
b481de9c
ZY
3121 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3122
188cf6c7
SO
3123 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3124 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
b481de9c
ZY
3125
3126 /* Input error checking is done when commands are added to queue. */
3127 if (cmd->meta.flags & CMD_WANT_SKB) {
3128 cmd->meta.source->u.skb = rxb->skb;
3129 rxb->skb = NULL;
3130 } else if (cmd->meta.u.callback &&
3131 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3132 rxb->skb = NULL;
3133
91c066f2 3134 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
b481de9c
ZY
3135
3136 if (!(cmd->meta.flags & CMD_ASYNC)) {
3137 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3138 wake_up_interruptible(&priv->wait_command_queue);
3139 }
3140}
3141
3142/************************** RX-FUNCTIONS ****************************/
3143/*
3144 * Rx theory of operation
3145 *
3146 * The host allocates 32 DMA target addresses and passes the host address
3147 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3148 * 0 to 31
3149 *
3150 * Rx Queue Indexes
3151 * The host/firmware share two index registers for managing the Rx buffers.
3152 *
3153 * The READ index maps to the first position that the firmware may be writing
3154 * to -- the driver can read up to (but not including) this position and get
3155 * good data.
3156 * The READ index is managed by the firmware once the card is enabled.
3157 *
3158 * The WRITE index maps to the last position the driver has read from -- the
3159 * position preceding WRITE is the last slot the firmware can place a packet.
3160 *
3161 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3162 * WRITE = READ.
3163 *
9fbab516 3164 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
3165 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3166 *
9fbab516 3167 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
3168 * and fire the RX interrupt. The driver can then query the READ index and
3169 * process as many packets as possible, moving the WRITE index forward as it
3170 * resets the Rx queue buffers with new memory.
3171 *
3172 * The management in the driver is as follows:
3173 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3174 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3175 * to replenish the iwl->rxq->rx_free.
bb8c093b 3176 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
3177 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3178 * 'processed' and 'read' driver indexes as well)
3179 * + A received packet is processed and handed to the kernel network stack,
3180 * detached from the iwl->rxq. The driver 'processed' index is updated.
3181 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3182 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3183 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3184 * were enough free buffers and RX_STALLED is set it is cleared.
3185 *
3186 *
3187 * Driver sequence:
3188 *
9fbab516 3189 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3190 * iwl3945_rx_queue_restock
9fbab516 3191 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
3192 * queue, updates firmware pointers, and updates
3193 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3194 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
3195 *
3196 * -- enable interrupts --
6100b588 3197 * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
b481de9c
ZY
3198 * READ INDEX, detaching the SKB from the pool.
3199 * Moves the packet buffer from queue to rx_used.
bb8c093b 3200 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
3201 * slots.
3202 * ...
3203 *
3204 */
3205
b481de9c 3206/**
9fbab516 3207 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3208 */
4a8a4322 3209static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY
3210 dma_addr_t dma_addr)
3211{
3212 return cpu_to_le32((u32)dma_addr);
3213}
3214
3215/**
bb8c093b 3216 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3217 *
9fbab516 3218 * If there are slots in the RX queue that need to be restocked,
b481de9c 3219 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3220 * as we can, pulling from rx_free.
b481de9c
ZY
3221 *
3222 * This moves the 'write' index forward to catch up with 'processed', and
3223 * also updates the memory address in the firmware to reference the new
3224 * target buffer.
3225 */
4a8a4322 3226static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
b481de9c 3227{
cc2f362c 3228 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 3229 struct list_head *element;
6100b588 3230 struct iwl_rx_mem_buffer *rxb;
b481de9c
ZY
3231 unsigned long flags;
3232 int write, rc;
3233
3234 spin_lock_irqsave(&rxq->lock, flags);
3235 write = rxq->write & ~0x7;
37d68317 3236 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3237 /* Get next free Rx buffer, remove from free list */
b481de9c 3238 element = rxq->rx_free.next;
6100b588 3239 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
b481de9c 3240 list_del(element);
6440adb5
CB
3241
3242 /* Point to Rx buffer via next RBD in circular buffer */
6100b588 3243 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
b481de9c
ZY
3244 rxq->queue[rxq->write] = rxb;
3245 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3246 rxq->free_count--;
3247 }
3248 spin_unlock_irqrestore(&rxq->lock, flags);
3249 /* If the pre-allocated buffer pool is dropping low, schedule to
3250 * refill it */
3251 if (rxq->free_count <= RX_LOW_WATERMARK)
3252 queue_work(priv->workqueue, &priv->rx_replenish);
3253
3254
6440adb5
CB
3255 /* If we've added more space for the firmware to place data, tell it.
3256 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY
3257 if ((write != (rxq->write & ~0x7))
3258 || (abs(rxq->write - rxq->read) > 7)) {
3259 spin_lock_irqsave(&rxq->lock, flags);
3260 rxq->need_update = 1;
3261 spin_unlock_irqrestore(&rxq->lock, flags);
141c43a3 3262 rc = iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY
3263 if (rc)
3264 return rc;
3265 }
3266
3267 return 0;
3268}
3269
3270/**
bb8c093b 3271 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
3272 *
3273 * When moving to rx_free an SKB is allocated for the slot.
3274 *
bb8c093b 3275 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 3276 * This is called as a scheduled work item (except for during initialization)
b481de9c 3277 */
4a8a4322 3278static void iwl3945_rx_allocate(struct iwl_priv *priv)
b481de9c 3279{
cc2f362c 3280 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 3281 struct list_head *element;
6100b588 3282 struct iwl_rx_mem_buffer *rxb;
b481de9c
ZY
3283 unsigned long flags;
3284 spin_lock_irqsave(&rxq->lock, flags);
3285 while (!list_empty(&rxq->rx_used)) {
3286 element = rxq->rx_used.next;
6100b588 3287 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
6440adb5
CB
3288
3289 /* Alloc a new receive buffer */
b481de9c 3290 rxb->skb =
1e33dc64
WT
3291 alloc_skb(priv->hw_params.rx_buf_size,
3292 __GFP_NOWARN | GFP_ATOMIC);
b481de9c
ZY
3293 if (!rxb->skb) {
3294 if (net_ratelimit())
978785a3 3295 IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
b481de9c
ZY
3296 /* We don't reschedule replenish work here -- we will
3297 * call the restock method and if it still needs
3298 * more buffers it will schedule replenish */
3299 break;
3300 }
12342c47
ZY
3301
3302 /* If radiotap head is required, reserve some headroom here.
3303 * The physical head count is a variable rx_stats->phy_count.
3304 * We reserve 4 bytes here. Plus these extra bytes, the
3305 * headroom of the physical head should be enough for the
3306 * radiotap head that iwl3945 supported. See iwl3945_rt.
3307 */
3308 skb_reserve(rxb->skb, 4);
3309
b481de9c
ZY
3310 priv->alloc_rxb_skb++;
3311 list_del(element);
6440adb5
CB
3312
3313 /* Get physical address of RB/SKB */
1e33dc64
WT
3314 rxb->real_dma_addr = pci_map_single(priv->pci_dev,
3315 rxb->skb->data,
3316 priv->hw_params.rx_buf_size,
3317 PCI_DMA_FROMDEVICE);
b481de9c
ZY
3318 list_add_tail(&rxb->list, &rxq->rx_free);
3319 rxq->free_count++;
3320 }
3321 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA
3322}
3323
3324/*
3325 * this should be called while priv->lock is locked
3326 */
4fd1f841 3327static void __iwl3945_rx_replenish(void *data)
5c0eef96 3328{
4a8a4322 3329 struct iwl_priv *priv = data;
5c0eef96
MA
3330
3331 iwl3945_rx_allocate(priv);
3332 iwl3945_rx_queue_restock(priv);
3333}
3334
3335
3336void iwl3945_rx_replenish(void *data)
3337{
4a8a4322 3338 struct iwl_priv *priv = data;
5c0eef96
MA
3339 unsigned long flags;
3340
3341 iwl3945_rx_allocate(priv);
b481de9c
ZY
3342
3343 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3344 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
3345 spin_unlock_irqrestore(&priv->lock, flags);
3346}
3347
b481de9c
ZY
3348/* Convert linear signal-to-noise ratio into dB */
3349static u8 ratio2dB[100] = {
3350/* 0 1 2 3 4 5 6 7 8 9 */
3351 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3352 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3353 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3354 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3355 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3356 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3357 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3358 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3359 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3360 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3361};
3362
3363/* Calculates a relative dB value from a ratio of linear
3364 * (i.e. not dB) signal levels.
3365 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 3366int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 3367{
221c80cf
AB
3368 /* 1000:1 or higher just report as 60 dB */
3369 if (sig_ratio >= 1000)
b481de9c
ZY
3370 return 60;
3371
221c80cf 3372 /* 100:1 or higher, divide by 10 and use table,
b481de9c 3373 * add 20 dB to make up for divide by 10 */
221c80cf 3374 if (sig_ratio >= 100)
3ac7f146 3375 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY
3376
3377 /* We shouldn't see this */
3378 if (sig_ratio < 1)
3379 return 0;
3380
3381 /* Use table for ratios 1:1 - 99:1 */
3382 return (int)ratio2dB[sig_ratio];
3383}
3384
3385#define PERFECT_RSSI (-20) /* dBm */
3386#define WORST_RSSI (-95) /* dBm */
3387#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3388
3389/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3390 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3391 * about formulas used below. */
bb8c093b 3392int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY
3393{
3394 int sig_qual;
3395 int degradation = PERFECT_RSSI - rssi_dbm;
3396
3397 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3398 * as indicator; formula is (signal dbm - noise dbm).
3399 * SNR at or above 40 is a great signal (100%).
3400 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3401 * Weakest usable signal is usually 10 - 15 dB SNR. */
3402 if (noise_dbm) {
3403 if (rssi_dbm - noise_dbm >= 40)
3404 return 100;
3405 else if (rssi_dbm < noise_dbm)
3406 return 0;
3407 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3408
3409 /* Else use just the signal level.
3410 * This formula is a least squares fit of data points collected and
3411 * compared with a reference system that had a percentage (%) display
3412 * for signal quality. */
3413 } else
3414 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3415 (15 * RSSI_RANGE + 62 * degradation)) /
3416 (RSSI_RANGE * RSSI_RANGE);
3417
3418 if (sig_qual > 100)
3419 sig_qual = 100;
3420 else if (sig_qual < 1)
3421 sig_qual = 0;
3422
3423 return sig_qual;
3424}
3425
3426/**
9fbab516 3427 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
3428 *
3429 * Uses the priv->rx_handlers callback function array to invoke
3430 * the appropriate handlers, including command responses,
3431 * frame-received notifications, and other notifications.
3432 */
4a8a4322 3433static void iwl3945_rx_handle(struct iwl_priv *priv)
b481de9c 3434{
6100b588 3435 struct iwl_rx_mem_buffer *rxb;
3d24a9f7 3436 struct iwl_rx_packet *pkt;
cc2f362c 3437 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
3438 u32 r, i;
3439 int reclaim;
3440 unsigned long flags;
5c0eef96 3441 u8 fill_rx = 0;
d68ab680 3442 u32 count = 8;
b481de9c 3443
6440adb5
CB
3444 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3445 * buffer that the driver may process (last buffer filled by ucode). */
8cd812bc 3446 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
3447 i = rxq->read;
3448
37d68317 3449 if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
5c0eef96 3450 fill_rx = 1;
b481de9c
ZY
3451 /* Rx interrupt, but nothing sent from uCode */
3452 if (i == r)
3453 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3454
3455 while (i != r) {
3456 rxb = rxq->queue[i];
3457
9fbab516 3458 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
3459 * then a bug has been introduced in the queue refilling
3460 * routines -- catch it here */
3461 BUG_ON(rxb == NULL);
3462
3463 rxq->queue[i] = NULL;
3464
6100b588 3465 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->real_dma_addr,
1e33dc64 3466 priv->hw_params.rx_buf_size,
b481de9c 3467 PCI_DMA_FROMDEVICE);
3d24a9f7 3468 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
3469
3470 /* Reclaim a command buffer only if this packet is a response
3471 * to a (driver-originated) command.
3472 * If the packet (e.g. Rx frame) originated from uCode,
3473 * there is no command buffer to reclaim.
3474 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
3475 * but apparently a few don't get set; catch them here. */
3476 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
3477 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
3478 (pkt->hdr.cmd != REPLY_TX);
3479
3480 /* Based on type of command response or notification,
3481 * handle those that need handling via function in
bb8c093b 3482 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c 3483 if (priv->rx_handlers[pkt->hdr.cmd]) {
40b8ec0b 3484 IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
b481de9c
ZY
3485 "r = %d, i = %d, %s, 0x%02x\n", r, i,
3486 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3487 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
3488 } else {
3489 /* No handling needed */
40b8ec0b 3490 IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
b481de9c
ZY
3491 "r %d i %d No handler needed for %s, 0x%02x\n",
3492 r, i, get_cmd_string(pkt->hdr.cmd),
3493 pkt->hdr.cmd);
3494 }
3495
3496 if (reclaim) {
9fbab516
BC
3497 /* Invoke any callbacks, transfer the skb to caller, and
3498 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY
3499 * as we reclaim the driver command queue */
3500 if (rxb && rxb->skb)
bb8c093b 3501 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c 3502 else
39aadf8c 3503 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
3504 }
3505
3506 /* For now we just don't re-use anything. We can tweak this
3507 * later to try and re-use notification packets and SKBs that
3508 * fail to Rx correctly */
3509 if (rxb->skb != NULL) {
3510 priv->alloc_rxb_skb--;
3511 dev_kfree_skb_any(rxb->skb);
3512 rxb->skb = NULL;
3513 }
3514
6100b588 3515 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
1e33dc64
WT
3516 priv->hw_params.rx_buf_size,
3517 PCI_DMA_FROMDEVICE);
b481de9c
ZY
3518 spin_lock_irqsave(&rxq->lock, flags);
3519 list_add_tail(&rxb->list, &priv->rxq.rx_used);
3520 spin_unlock_irqrestore(&rxq->lock, flags);
3521 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
3522 /* If there are a lot of unused frames,
3523 * restock the Rx queue so ucode won't assert. */
3524 if (fill_rx) {
3525 count++;
3526 if (count >= 8) {
3527 priv->rxq.read = i;
3528 __iwl3945_rx_replenish(priv);
3529 count = 0;
3530 }
3531 }
b481de9c
ZY
3532 }
3533
3534 /* Backtrack one entry */
3535 priv->rxq.read = i;
bb8c093b 3536 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
3537}
3538
6440adb5
CB
3539/**
3540 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
3541 */
4a8a4322 3542static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
188cf6c7 3543 struct iwl_tx_queue *txq)
b481de9c
ZY
3544{
3545 u32 reg = 0;
3546 int rc = 0;
3547 int txq_id = txq->q.id;
3548
3549 if (txq->need_update == 0)
3550 return rc;
3551
3552 /* if we're trying to save power */
3553 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3554 /* wake up nic if it's powered down ...
3555 * uCode will wake up, and interrupt us again, so next
3556 * time we'll skip this part. */
5d49f498 3557 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY
3558
3559 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3560 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
5d49f498 3561 iwl_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY
3562 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3563 return rc;
3564 }
3565
3566 /* restore this queue's parameters in nic hardware. */
5d49f498 3567 rc = iwl_grab_nic_access(priv);
b481de9c
ZY
3568 if (rc)
3569 return rc;
5d49f498 3570 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 3571 txq->q.write_ptr | (txq_id << 8));
5d49f498 3572 iwl_release_nic_access(priv);
b481de9c
ZY
3573
3574 /* else not in power-save mode, uCode will never sleep when we're
3575 * trying to tx (during RFKILL, we're not trying to tx). */
3576 } else
5d49f498 3577 iwl_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 3578 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY
3579
3580 txq->need_update = 0;
3581
3582 return rc;
3583}
3584
c8b0e6e1 3585#ifdef CONFIG_IWL3945_DEBUG
4a8a4322 3586static void iwl3945_print_rx_config_cmd(struct iwl_priv *priv,
40b8ec0b 3587 struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY
3588{
3589 IWL_DEBUG_RADIO("RX CONFIG:\n");
40b8ec0b 3590 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY
3591 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
3592 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
3593 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
3594 le32_to_cpu(rxon->filter_flags));
3595 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
3596 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
3597 rxon->ofdm_basic_rates);
3598 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
e174961c
JB
3599 IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
3600 IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
b481de9c
ZY
3601 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
3602}
3603#endif
3604
4a8a4322 3605static void iwl3945_enable_interrupts(struct iwl_priv *priv)
b481de9c
ZY
3606{
3607 IWL_DEBUG_ISR("Enabling interrupts\n");
3608 set_bit(STATUS_INT_ENABLED, &priv->status);
5d49f498 3609 iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY
3610}
3611
0359facc
MA
3612
3613/* call this function to flush any scheduled tasklet */
4a8a4322 3614static inline void iwl_synchronize_irq(struct iwl_priv *priv)
0359facc 3615{
a96a27f9 3616 /* wait to make sure we flush pending tasklet*/
0359facc
MA
3617 synchronize_irq(priv->pci_dev->irq);
3618 tasklet_kill(&priv->irq_tasklet);
3619}
3620
3621
4a8a4322 3622static inline void iwl3945_disable_interrupts(struct iwl_priv *priv)
b481de9c
ZY
3623{
3624 clear_bit(STATUS_INT_ENABLED, &priv->status);
3625
3626 /* disable interrupts from uCode/NIC to host */
5d49f498 3627 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY
3628
3629 /* acknowledge/clear/reset any interrupts still pending
3630 * from uCode or flow handler (Rx/Tx DMA) */
5d49f498
AK
3631 iwl_write32(priv, CSR_INT, 0xffffffff);
3632 iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY
3633 IWL_DEBUG_ISR("Disabled interrupts\n");
3634}
3635
3636static const char *desc_lookup(int i)
3637{
3638 switch (i) {
3639 case 1:
3640 return "FAIL";
3641 case 2:
3642 return "BAD_PARAM";
3643 case 3:
3644 return "BAD_CHECKSUM";
3645 case 4:
3646 return "NMI_INTERRUPT";
3647 case 5:
3648 return "SYSASSERT";
3649 case 6:
3650 return "FATAL_ERROR";
3651 }
3652
3653 return "UNKNOWN";
3654}
3655
3656#define ERROR_START_OFFSET (1 * sizeof(u32))
3657#define ERROR_ELEM_SIZE (7 * sizeof(u32))
3658
4a8a4322 3659static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY
3660{
3661 u32 i;
3662 u32 desc, time, count, base, data1;
3663 u32 blink1, blink2, ilink1, ilink2;
3664 int rc;
3665
3666 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
3667
bb8c093b 3668 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 3669 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
b481de9c
ZY
3670 return;
3671 }
3672
5d49f498 3673 rc = iwl_grab_nic_access(priv);
b481de9c 3674 if (rc) {
39aadf8c 3675 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY
3676 return;
3677 }
3678
5d49f498 3679 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY
3680
3681 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT
3682 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
3683 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
3684 priv->status, count);
b481de9c
ZY
3685 }
3686
15b1687c 3687 IWL_ERR(priv, "Desc Time asrtPC blink2 "
b481de9c
ZY
3688 "ilink1 nmiPC Line\n");
3689 for (i = ERROR_START_OFFSET;
3690 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
3691 i += ERROR_ELEM_SIZE) {
5d49f498 3692 desc = iwl_read_targ_mem(priv, base + i);
b481de9c 3693 time =
5d49f498 3694 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 3695 blink1 =
5d49f498 3696 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 3697 blink2 =
5d49f498 3698 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 3699 ilink1 =
5d49f498 3700 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 3701 ilink2 =
5d49f498 3702 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 3703 data1 =
5d49f498 3704 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c 3705
15b1687c
WT
3706 IWL_ERR(priv,
3707 "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
3708 desc_lookup(desc), desc, time, blink1, blink2,
3709 ilink1, ilink2, data1);
b481de9c
ZY
3710 }
3711
5d49f498 3712 iwl_release_nic_access(priv);
b481de9c
ZY
3713
3714}
3715
f58177b9 3716#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
3717
3718/**
bb8c093b 3719 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 3720 *
5d49f498 3721 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
b481de9c 3722 */
4a8a4322 3723static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
b481de9c
ZY
3724 u32 num_events, u32 mode)
3725{
3726 u32 i;
3727 u32 base; /* SRAM byte address of event log header */
3728 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
3729 u32 ptr; /* SRAM byte address of log data */
3730 u32 ev, time, data; /* event log data */
3731
3732 if (num_events == 0)
3733 return;
3734
3735 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
3736
3737 if (mode == 0)
3738 event_size = 2 * sizeof(u32);
3739 else
3740 event_size = 3 * sizeof(u32);
3741
3742 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
3743
3744 /* "time" is actually "data" for mode 0 (no timestamp).
3745 * place event id # at far right for easier visual parsing. */
3746 for (i = 0; i < num_events; i++) {
5d49f498 3747 ev = iwl_read_targ_mem(priv, ptr);
b481de9c 3748 ptr += sizeof(u32);
5d49f498 3749 time = iwl_read_targ_mem(priv, ptr);
b481de9c 3750 ptr += sizeof(u32);
15b1687c
WT
3751 if (mode == 0) {
3752 /* data, ev */
3753 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
3754 } else {
5d49f498 3755 data = iwl_read_targ_mem(priv, ptr);
b481de9c 3756 ptr += sizeof(u32);
15b1687c 3757 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
b481de9c
ZY
3758 }
3759 }
3760}
3761
4a8a4322 3762static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
b481de9c
ZY
3763{
3764 int rc;
3765 u32 base; /* SRAM byte address of event log header */
3766 u32 capacity; /* event log capacity in # entries */
3767 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
3768 u32 num_wraps; /* # times uCode wrapped to top of log */
3769 u32 next_entry; /* index of next entry to be written by uCode */
3770 u32 size; /* # entries that we'll print */
3771
3772 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 3773 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 3774 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY
3775 return;
3776 }
3777
5d49f498 3778 rc = iwl_grab_nic_access(priv);
b481de9c 3779 if (rc) {
39aadf8c 3780 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY
3781 return;
3782 }
3783
3784 /* event log header */
5d49f498
AK
3785 capacity = iwl_read_targ_mem(priv, base);
3786 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
3787 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
3788 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY
3789
3790 size = num_wraps ? capacity : next_entry;
3791
3792 /* bail out if nothing in log */
3793 if (size == 0) {
15b1687c 3794 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
5d49f498 3795 iwl_release_nic_access(priv);
b481de9c
ZY
3796 return;
3797 }
3798
15b1687c 3799 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY
3800 size, num_wraps);
3801
3802 /* if uCode has wrapped back to top of log, start at the oldest entry,
3803 * i.e the next one that uCode would fill. */
3804 if (num_wraps)
bb8c093b 3805 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY
3806 capacity - next_entry, mode);
3807
3808 /* (then/else) start at top of log */
bb8c093b 3809 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 3810
5d49f498 3811 iwl_release_nic_access(priv);
b481de9c
ZY
3812}
3813
3814/**
bb8c093b 3815 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 3816 */
4a8a4322 3817static void iwl3945_irq_handle_error(struct iwl_priv *priv)
b481de9c 3818{
bb8c093b 3819 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY
3820 set_bit(STATUS_FW_ERROR, &priv->status);
3821
3822 /* Cancel currently queued command. */
3823 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3824
c8b0e6e1 3825#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 3826 if (priv->debug_level & IWL_DL_FW_ERRORS) {
bb8c093b
CH
3827 iwl3945_dump_nic_error_log(priv);
3828 iwl3945_dump_nic_event_log(priv);
f2c7e521 3829 iwl3945_print_rx_config_cmd(priv, &priv->staging39_rxon);
b481de9c
ZY
3830 }
3831#endif
3832
3833 wake_up_interruptible(&priv->wait_command_queue);
3834
3835 /* Keep the restart process from trying to send host
3836 * commands by clearing the INIT status bit */
3837 clear_bit(STATUS_READY, &priv->status);
3838
3839 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3840 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
3841 "Restarting adapter due to uCode error.\n");
3842
bb8c093b 3843 if (iwl3945_is_associated(priv)) {
f2c7e521
AK
3844 memcpy(&priv->recovery39_rxon, &priv->active39_rxon,
3845 sizeof(priv->recovery39_rxon));
b481de9c
ZY
3846 priv->error_recovering = 1;
3847 }
3848 queue_work(priv->workqueue, &priv->restart);
3849 }
3850}
3851
4a8a4322 3852static void iwl3945_error_recovery(struct iwl_priv *priv)
b481de9c
ZY
3853{
3854 unsigned long flags;
3855
f2c7e521
AK
3856 memcpy(&priv->staging39_rxon, &priv->recovery39_rxon,
3857 sizeof(priv->staging39_rxon));
3858 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 3859 iwl3945_commit_rxon(priv);
b481de9c 3860
bb8c093b 3861 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY
3862
3863 spin_lock_irqsave(&priv->lock, flags);
f2c7e521 3864 priv->assoc_id = le16_to_cpu(priv->staging39_rxon.assoc_id);
b481de9c
ZY
3865 priv->error_recovering = 0;
3866 spin_unlock_irqrestore(&priv->lock, flags);
3867}
3868
4a8a4322 3869static void iwl3945_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
3870{
3871 u32 inta, handled = 0;
3872 u32 inta_fh;
3873 unsigned long flags;
c8b0e6e1 3874#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
3875 u32 inta_mask;
3876#endif
3877
3878 spin_lock_irqsave(&priv->lock, flags);
3879
3880 /* Ack/clear/reset pending uCode interrupts.
3881 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
3882 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
5d49f498
AK
3883 inta = iwl_read32(priv, CSR_INT);
3884 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
3885
3886 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
3887 * Any new interrupts that happen after this, either while we're
3888 * in this tasklet, or later, will show up in next ISR/tasklet. */
5d49f498
AK
3889 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
3890 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 3891
c8b0e6e1 3892#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 3893 if (priv->debug_level & IWL_DL_ISR) {
9fbab516 3894 /* just for debug */
5d49f498 3895 inta_mask = iwl_read32(priv, CSR_INT_MASK);
b481de9c
ZY
3896 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
3897 inta, inta_mask, inta_fh);
3898 }
3899#endif
3900
3901 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
3902 * atomic, make sure that inta covers all the interrupts that
3903 * we've discovered, even if FH interrupt came in just after
3904 * reading CSR_INT. */
6f83eaa1 3905 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 3906 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 3907 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY
3908 inta |= CSR_INT_BIT_FH_TX;
3909
3910 /* Now service all interrupt bits discovered above. */
3911 if (inta & CSR_INT_BIT_HW_ERR) {
15b1687c 3912 IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
b481de9c
ZY
3913
3914 /* Tell the device to stop sending interrupts */
bb8c093b 3915 iwl3945_disable_interrupts(priv);
b481de9c 3916
bb8c093b 3917 iwl3945_irq_handle_error(priv);
b481de9c
ZY
3918
3919 handled |= CSR_INT_BIT_HW_ERR;
3920
3921 spin_unlock_irqrestore(&priv->lock, flags);
3922
3923 return;
3924 }
3925
c8b0e6e1 3926#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 3927 if (priv->debug_level & (IWL_DL_ISR)) {
b481de9c 3928 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP
3929 if (inta & CSR_INT_BIT_SCD)
3930 IWL_DEBUG_ISR("Scheduler finished to transmit "
3931 "the frame/frames.\n");
b481de9c
ZY
3932
3933 /* Alive notification via Rx interrupt will do the real work */
3934 if (inta & CSR_INT_BIT_ALIVE)
3935 IWL_DEBUG_ISR("Alive interrupt\n");
3936 }
3937#endif
3938 /* Safely ignore these bits for debug checks below */
25c03d8e 3939 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 3940
b481de9c
ZY
3941 /* Error detected by uCode */
3942 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
3943 IWL_ERR(priv, "Microcode SW error detected. "
3944 "Restarting 0x%X.\n", inta);
bb8c093b 3945 iwl3945_irq_handle_error(priv);
b481de9c
ZY
3946 handled |= CSR_INT_BIT_SW_ERR;
3947 }
3948
3949 /* uCode wakes up after power-down sleep */
3950 if (inta & CSR_INT_BIT_WAKEUP) {
3951 IWL_DEBUG_ISR("Wakeup interrupt\n");
141c43a3 3952 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
188cf6c7
SO
3953 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
3954 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
3955 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
3956 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
3957 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
3958 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY
3959
3960 handled |= CSR_INT_BIT_WAKEUP;
3961 }
3962
3963 /* All uCode command responses, including Tx command responses,
3964 * Rx "responses" (frame-received notification), and other
3965 * notifications from uCode come through here*/
3966 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 3967 iwl3945_rx_handle(priv);
b481de9c
ZY
3968 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
3969 }
3970
3971 if (inta & CSR_INT_BIT_FH_TX) {
3972 IWL_DEBUG_ISR("Tx interrupt\n");
3973
5d49f498
AK
3974 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
3975 if (!iwl_grab_nic_access(priv)) {
3976 iwl_write_direct32(priv, FH39_TCSR_CREDIT
bddadf86 3977 (FH39_SRVC_CHNL), 0x0);
5d49f498 3978 iwl_release_nic_access(priv);
b481de9c
ZY
3979 }
3980 handled |= CSR_INT_BIT_FH_TX;
3981 }
3982
3983 if (inta & ~handled)
15b1687c 3984 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
b481de9c
ZY
3985
3986 if (inta & ~CSR_INI_SET_MASK) {
39aadf8c 3987 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
b481de9c 3988 inta & ~CSR_INI_SET_MASK);
39aadf8c 3989 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
3990 }
3991
3992 /* Re-enable all interrupts */
0359facc
MA
3993 /* only Re-enable if disabled by irq */
3994 if (test_bit(STATUS_INT_ENABLED, &priv->status))
3995 iwl3945_enable_interrupts(priv);
b481de9c 3996
c8b0e6e1 3997#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 3998 if (priv->debug_level & (IWL_DL_ISR)) {
5d49f498
AK
3999 inta = iwl_read32(priv, CSR_INT);
4000 inta_mask = iwl_read32(priv, CSR_INT_MASK);
4001 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY
4002 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4003 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4004 }
4005#endif
4006 spin_unlock_irqrestore(&priv->lock, flags);
4007}
4008
bb8c093b 4009static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4010{
4a8a4322 4011 struct iwl_priv *priv = data;
b481de9c
ZY
4012 u32 inta, inta_mask;
4013 u32 inta_fh;
4014 if (!priv)
4015 return IRQ_NONE;
4016
4017 spin_lock(&priv->lock);
4018
4019 /* Disable (but don't clear!) interrupts here to avoid
4020 * back-to-back ISRs and sporadic interrupts from our NIC.
4021 * If we have something to service, the tasklet will re-enable ints.
4022 * If we *don't* have something, we'll re-enable before leaving here. */
5d49f498
AK
4023 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
4024 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY
4025
4026 /* Discover which interrupts are active/pending */
5d49f498
AK
4027 inta = iwl_read32(priv, CSR_INT);
4028 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY
4029
4030 /* Ignore interrupt if there's nothing in NIC to service.
4031 * This may be due to IRQ shared with another device,
4032 * or due to sporadic interrupts thrown from our NIC. */
4033 if (!inta && !inta_fh) {
4034 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4035 goto none;
4036 }
4037
4038 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4039 /* Hardware disappeared */
39aadf8c 4040 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
cb4da1a3 4041 goto unplugged;
b481de9c
ZY
4042 }
4043
4044 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4045 inta, inta_mask, inta_fh);
4046
25c03d8e
JP
4047 inta &= ~CSR_INT_BIT_SCD;
4048
bb8c093b 4049 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP
4050 if (likely(inta || inta_fh))
4051 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4052unplugged:
b481de9c
ZY
4053 spin_unlock(&priv->lock);
4054
4055 return IRQ_HANDLED;
4056
4057 none:
4058 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA
4059 /* only Re-enable if disabled by irq */
4060 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4061 iwl3945_enable_interrupts(priv);
b481de9c
ZY
4062 spin_unlock(&priv->lock);
4063 return IRQ_NONE;
4064}
4065
4066/************************** EEPROM BANDS ****************************
4067 *
bb8c093b 4068 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY
4069 * EEPROM contents to the specific channel number supported for each
4070 * band.
4071 *
f2c7e521 4072 * For example, iwl3945_priv->eeprom39.band_3_channels[4] from the band_3
b481de9c
ZY
4073 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4074 * The specific geography and calibration information for that channel
4075 * is contained in the eeprom map itself.
4076 *
4077 * During init, we copy the eeprom information and channel map
4078 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4079 *
4080 * channel_map_24/52 provides the index in the channel_info array for a
4081 * given channel. We have to have two separate maps as there is channel
4082 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4083 * band_2
4084 *
4085 * A value of 0xff stored in the channel_map indicates that the channel
4086 * is not supported by the hardware at all.
4087 *
4088 * A value of 0xfe in the channel_map indicates that the channel is not
4089 * valid for Tx with the current hardware. This means that
4090 * while the system can tune and receive on a given channel, it may not
4091 * be able to associate or transmit any frames on that
4092 * channel. There is no corresponding channel information for that
4093 * entry.
4094 *
4095 *********************************************************************/
4096
4097/* 2.4 GHz */
bb8c093b 4098static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY
4099 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4100};
4101
4102/* 5.2 GHz bands */
9fbab516 4103static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY
4104 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4105};
4106
9fbab516 4107static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY
4108 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4109};
4110
bb8c093b 4111static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY
4112 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4113};
4114
bb8c093b 4115static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY
4116 145, 149, 153, 157, 161, 165
4117};
4118
4a8a4322 4119static void iwl3945_init_band_reference(const struct iwl_priv *priv, int band,
b481de9c 4120 int *eeprom_ch_count,
0f741d99 4121 const struct iwl_eeprom_channel
b481de9c
ZY
4122 **eeprom_ch_info,
4123 const u8 **eeprom_ch_index)
4124{
4125 switch (band) {
4126 case 1: /* 2.4GHz band */
bb8c093b 4127 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
f2c7e521 4128 *eeprom_ch_info = priv->eeprom39.band_1_channels;
bb8c093b 4129 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4130 break;
9fbab516 4131 case 2: /* 4.9GHz band */
bb8c093b 4132 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
f2c7e521 4133 *eeprom_ch_info = priv->eeprom39.band_2_channels;
bb8c093b 4134 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY
4135 break;
4136 case 3: /* 5.2GHz band */
bb8c093b 4137 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
f2c7e521 4138 *eeprom_ch_info = priv->eeprom39.band_3_channels;
bb8c093b 4139 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4140 break;
9fbab516 4141 case 4: /* 5.5GHz band */
bb8c093b 4142 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
f2c7e521 4143 *eeprom_ch_info = priv->eeprom39.band_4_channels;
bb8c093b 4144 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4145 break;
9fbab516 4146 case 5: /* 5.7GHz band */
bb8c093b 4147 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
f2c7e521 4148 *eeprom_ch_info = priv->eeprom39.band_5_channels;
bb8c093b 4149 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY
4150 break;
4151 default:
4152 BUG();
4153 return;
4154 }
4155}
4156
6440adb5
CB
4157/**
4158 * iwl3945_get_channel_info - Find driver's private channel info
4159 *
4160 * Based on band and channel number.
4161 */
d20b3c65 4162const struct iwl_channel_info *
4a8a4322 4163iwl3945_get_channel_info(const struct iwl_priv *priv,
d20b3c65 4164 enum ieee80211_band band, u16 channel)
b481de9c
ZY
4165{
4166 int i;
4167
8318d78a
JB
4168 switch (band) {
4169 case IEEE80211_BAND_5GHZ:
b481de9c
ZY
4170 for (i = 14; i < priv->channel_count; i++) {
4171 if (priv->channel_info[i].channel == channel)
4172 return &priv->channel_info[i];
4173 }
4174 break;
4175
8318d78a 4176 case IEEE80211_BAND_2GHZ:
b481de9c
ZY
4177 if (channel >= 1 && channel <= 14)
4178 return &priv->channel_info[channel - 1];
4179 break;
8318d78a
JB
4180 case IEEE80211_NUM_BANDS:
4181 WARN_ON(1);
b481de9c
ZY
4182 }
4183
4184 return NULL;
4185}
4186
4187#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4188 ? # x " " : "")
4189
6440adb5
CB
4190/**
4191 * iwl3945_init_channel_map - Set up driver's info for all possible channels
4192 */
4a8a4322 4193static int iwl3945_init_channel_map(struct iwl_priv *priv)
b481de9c
ZY
4194{
4195 int eeprom_ch_count = 0;
4196 const u8 *eeprom_ch_index = NULL;
0f741d99 4197 const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 4198 int band, ch;
d20b3c65 4199 struct iwl_channel_info *ch_info;
b481de9c
ZY
4200
4201 if (priv->channel_count) {
4202 IWL_DEBUG_INFO("Channel map already initialized.\n");
4203 return 0;
4204 }
4205
f2c7e521 4206 if (priv->eeprom39.version < 0x2f) {
39aadf8c 4207 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
f2c7e521 4208 priv->eeprom39.version);
b481de9c
ZY
4209 return -EINVAL;
4210 }
4211
4212 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4213
4214 priv->channel_count =
bb8c093b
CH
4215 ARRAY_SIZE(iwl3945_eeprom_band_1) +
4216 ARRAY_SIZE(iwl3945_eeprom_band_2) +
4217 ARRAY_SIZE(iwl3945_eeprom_band_3) +
4218 ARRAY_SIZE(iwl3945_eeprom_band_4) +
4219 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY
4220
4221 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4222
d20b3c65 4223 priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
b481de9c
ZY
4224 priv->channel_count, GFP_KERNEL);
4225 if (!priv->channel_info) {
15b1687c 4226 IWL_ERR(priv, "Could not allocate channel_info\n");
b481de9c
ZY
4227 priv->channel_count = 0;
4228 return -ENOMEM;
4229 }
4230
4231 ch_info = priv->channel_info;
4232
4233 /* Loop through the 5 EEPROM bands adding them in order to the
4234 * channel map we maintain (that contains additional information than
4235 * what just in the EEPROM) */
4236 for (band = 1; band <= 5; band++) {
4237
bb8c093b 4238 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY
4239 &eeprom_ch_info, &eeprom_ch_index);
4240
4241 /* Loop through each band adding each of the channels */
4242 for (ch = 0; ch < eeprom_ch_count; ch++) {
4243 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB
4244 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4245 IEEE80211_BAND_5GHZ;
b481de9c
ZY
4246
4247 /* permanently store EEPROM's channel regulatory flags
4248 * and max power in channel info database. */
4249 ch_info->eeprom = eeprom_ch_info[ch];
4250
4251 /* Copy the run-time flags so they are there even on
4252 * invalid channels */
4253 ch_info->flags = eeprom_ch_info[ch].flags;
4254
4255 if (!(is_channel_valid(ch_info))) {
4256 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4257 "No traffic\n",
4258 ch_info->channel,
4259 ch_info->flags,
4260 is_channel_a_band(ch_info) ?
4261 "5.2" : "2.4");
4262 ch_info++;
4263 continue;
4264 }
4265
4266 /* Initialize regulatory-based run-time data */
4267 ch_info->max_power_avg = ch_info->curr_txpow =
4268 eeprom_ch_info[ch].max_power_avg;
4269 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4270 ch_info->min_power = 0;
4271
fe7c4040 4272 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
b481de9c
ZY
4273 " %ddBm): Ad-Hoc %ssupported\n",
4274 ch_info->channel,
4275 is_channel_a_band(ch_info) ?
4276 "5.2" : "2.4",
8211ef78 4277 CHECK_AND_PRINT(VALID),
b481de9c
ZY
4278 CHECK_AND_PRINT(IBSS),
4279 CHECK_AND_PRINT(ACTIVE),
4280 CHECK_AND_PRINT(RADAR),
4281 CHECK_AND_PRINT(WIDE),
b481de9c
ZY
4282 CHECK_AND_PRINT(DFS),
4283 eeprom_ch_info[ch].flags,
4284 eeprom_ch_info[ch].max_power_avg,
4285 ((eeprom_ch_info[ch].
4286 flags & EEPROM_CHANNEL_IBSS)
4287 && !(eeprom_ch_info[ch].
4288 flags & EEPROM_CHANNEL_RADAR))
4289 ? "" : "not ");
4290
4291 /* Set the user_txpower_limit to the highest power
4292 * supported by any channel */
4293 if (eeprom_ch_info[ch].max_power_avg >
4294 priv->user_txpower_limit)
4295 priv->user_txpower_limit =
4296 eeprom_ch_info[ch].max_power_avg;
4297
4298 ch_info++;
4299 }
4300 }
4301
6440adb5 4302 /* Set up txpower settings in driver for all channels */
b481de9c
ZY
4303 if (iwl3945_txpower_set_from_eeprom(priv))
4304 return -EIO;
4305
4306 return 0;
4307}
4308
849e0dce
RC
4309/*
4310 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4311 */
4a8a4322 4312static void iwl3945_free_channel_map(struct iwl_priv *priv)
849e0dce
RC
4313{
4314 kfree(priv->channel_info);
4315 priv->channel_count = 0;
4316}
4317
b481de9c
ZY
4318/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4319 * sending probe req. This should be set long enough to hear probe responses
4320 * from more than one AP. */
f9340520
AK
4321#define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
4322#define IWL_ACTIVE_DWELL_TIME_52 (20)
4323
4324#define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
4325#define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
b481de9c
ZY
4326
4327/* For faster active scanning, scan will move to the next channel if fewer than
4328 * PLCP_QUIET_THRESH packets are heard on this channel within
4329 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4330 * time if it's a quiet channel (nothing responded to our probe, and there's
4331 * no other traffic).
4332 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4333#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
f9340520 4334#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
b481de9c
ZY
4335
4336/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4337 * Must be set longer than active dwell time.
4338 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4339#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4340#define IWL_PASSIVE_DWELL_TIME_52 (10)
4341#define IWL_PASSIVE_DWELL_BASE (100)
4342#define IWL_CHANNEL_TUNE_TIME 5
4343
e720ce9d 4344#define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
f9340520 4345
4a8a4322 4346static inline u16 iwl3945_get_active_dwell_time(struct iwl_priv *priv,
f9340520
AK
4347 enum ieee80211_band band,
4348 u8 n_probes)
b481de9c 4349{
8318d78a 4350 if (band == IEEE80211_BAND_5GHZ)
f9340520
AK
4351 return IWL_ACTIVE_DWELL_TIME_52 +
4352 IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
b481de9c 4353 else
f9340520
AK
4354 return IWL_ACTIVE_DWELL_TIME_24 +
4355 IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
b481de9c
ZY
4356}
4357
4a8a4322 4358static u16 iwl3945_get_passive_dwell_time(struct iwl_priv *priv,
8318d78a 4359 enum ieee80211_band band)
b481de9c 4360{
8318d78a 4361 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY
4362 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4363 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4364
bb8c093b 4365 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
4366 /* If we're associated, we clamp the maximum passive
4367 * dwell time to be 98% of the beacon interval (minus
4368 * 2 * channel tune time) */
4369 passive = priv->beacon_int;
4370 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4371 passive = IWL_PASSIVE_DWELL_BASE;
4372 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4373 }
4374
b481de9c
ZY
4375 return passive;
4376}
4377
4a8a4322 4378static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 4379 enum ieee80211_band band,
f9340520 4380 u8 is_active, u8 n_probes,
bb8c093b 4381 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY
4382{
4383 const struct ieee80211_channel *channels = NULL;
8318d78a 4384 const struct ieee80211_supported_band *sband;
d20b3c65 4385 const struct iwl_channel_info *ch_info;
b481de9c
ZY
4386 u16 passive_dwell = 0;
4387 u16 active_dwell = 0;
4388 int added, i;
4389
cbba18c6 4390 sband = iwl_get_hw_mode(priv, band);
8318d78a 4391 if (!sband)
b481de9c
ZY
4392 return 0;
4393
8318d78a 4394 channels = sband->channels;
b481de9c 4395
f9340520 4396 active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
8318d78a 4397 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 4398
8f4807a1
AK
4399 if (passive_dwell <= active_dwell)
4400 passive_dwell = active_dwell + 1;
4401
8318d78a 4402 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB
4403 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4404 continue;
4405
8318d78a 4406 scan_ch->channel = channels[i].hw_value;
b481de9c 4407
8318d78a 4408 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c 4409 if (!is_channel_valid(ch_info)) {
66b5004d 4410 IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
b481de9c
ZY
4411 scan_ch->channel);
4412 continue;
4413 }
4414
011a0330
AK
4415 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4416 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4417 /* If passive , set up for auto-switch
4418 * and use long active_dwell time.
4419 */
b481de9c 4420 if (!is_active || is_channel_passive(ch_info) ||
011a0330 4421 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 4422 scan_ch->type = 0; /* passive */
011a0330
AK
4423 if (IWL_UCODE_API(priv->ucode_ver) == 1)
4424 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
4425 } else {
b481de9c 4426 scan_ch->type = 1; /* active */
011a0330 4427 }
b481de9c 4428
011a0330
AK
4429 /* Set direct probe bits. These may be used both for active
4430 * scan channels (probes gets sent right away),
4431 * or for passive channels (probes get se sent only after
4432 * hearing clear Rx packet).*/
4433 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
4434 if (n_probes)
4435 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
4436 } else {
4437 /* uCode v1 does not allow setting direct probe bits on
4438 * passive channel. */
4439 if ((scan_ch->type & 1) && n_probes)
4440 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
4441 }
b481de9c 4442
9fbab516 4443 /* Set txpower levels to defaults */
b481de9c
ZY
4444 scan_ch->tpc.dsp_atten = 110;
4445 /* scan_pwr_info->tpc.dsp_atten; */
4446
4447 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 4448 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
4449 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4450 else {
4451 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4452 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 4453 * power level:
8a1b0245 4454 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
4455 */
4456 }
4457
4458 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
4459 scan_ch->channel,
4460 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
4461 (scan_ch->type & 1) ?
4462 active_dwell : passive_dwell);
4463
4464 scan_ch++;
4465 added++;
4466 }
4467
4468 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
4469 return added;
4470}
4471
4a8a4322 4472static void iwl3945_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY
4473 struct ieee80211_rate *rates)
4474{
4475 int i;
4476
4477 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB
4478 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
4479 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4480 rates[i].hw_value_short = i;
4481 rates[i].flags = 0;
d9829a67 4482 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 4483 /*
8318d78a 4484 * If CCK != 1M then set short preamble rate flag.
b481de9c 4485 */
bb8c093b 4486 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 4487 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 4488 }
b481de9c
ZY
4489 }
4490}
4491
4492/**
bb8c093b 4493 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 4494 */
4a8a4322 4495static int iwl3945_init_geos(struct iwl_priv *priv)
b481de9c 4496{
d20b3c65 4497 struct iwl_channel_info *ch;
8211ef78 4498 struct ieee80211_supported_band *sband;
b481de9c
ZY
4499 struct ieee80211_channel *channels;
4500 struct ieee80211_channel *geo_ch;
4501 struct ieee80211_rate *rates;
4502 int i = 0;
b481de9c 4503
8318d78a
JB
4504 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
4505 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY
4506 IWL_DEBUG_INFO("Geography modes already initialized.\n");
4507 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4508 return 0;
4509 }
4510
b481de9c
ZY
4511 channels = kzalloc(sizeof(struct ieee80211_channel) *
4512 priv->channel_count, GFP_KERNEL);
8318d78a 4513 if (!channels)
b481de9c 4514 return -ENOMEM;
b481de9c 4515
8211ef78 4516 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY
4517 GFP_KERNEL);
4518 if (!rates) {
b481de9c
ZY
4519 kfree(channels);
4520 return -ENOMEM;
4521 }
4522
b481de9c 4523 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW
4524 sband = &priv->bands[IEEE80211_BAND_5GHZ];
4525 sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
4526 /* just OFDM */
4527 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
4528 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
4529
4530 sband = &priv->bands[IEEE80211_BAND_2GHZ];
4531 sband->channels = channels;
4532 /* OFDM & CCK */
4533 sband->bitrates = rates;
4534 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c
ZY
4535
4536 priv->ieee_channels = channels;
4537 priv->ieee_rates = rates;
4538
bb8c093b 4539 iwl3945_init_hw_rates(priv, rates);
b481de9c 4540
8211ef78 4541 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY
4542 ch = &priv->channel_info[i];
4543
8211ef78
TW
4544 /* FIXME: might be removed if scan is OK*/
4545 if (!is_channel_valid(ch))
b481de9c 4546 continue;
b481de9c
ZY
4547
4548 if (is_channel_a_band(ch))
8211ef78 4549 sband = &priv->bands[IEEE80211_BAND_5GHZ];
8318d78a 4550 else
8211ef78 4551 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 4552
8211ef78
TW
4553 geo_ch = &sband->channels[sband->n_channels++];
4554
4555 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB
4556 geo_ch->max_power = ch->max_power_avg;
4557 geo_ch->max_antenna_gain = 0xff;
7b72304d 4558 geo_ch->hw_value = ch->channel;
b481de9c
ZY
4559
4560 if (is_channel_valid(ch)) {
8318d78a
JB
4561 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
4562 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 4563
8318d78a
JB
4564 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
4565 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY
4566
4567 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 4568 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY
4569
4570 if (ch->max_power_avg > priv->max_channel_txpower_limit)
4571 priv->max_channel_txpower_limit =
4572 ch->max_power_avg;
8211ef78 4573 } else {
8318d78a 4574 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW
4575 }
4576
4577 /* Save flags for reg domain usage */
4578 geo_ch->orig_flags = geo_ch->flags;
4579
4580 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
4581 ch->channel, geo_ch->center_freq,
4582 is_channel_a_band(ch) ? "5.2" : "2.4",
4583 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
4584 "restricted" : "valid",
4585 geo_ch->flags);
b481de9c
ZY
4586 }
4587
82b9a121
TW
4588 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
4589 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW
4590 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
4591 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
4592 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 4593 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY
4594 }
4595
978785a3 4596 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB
4597 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
4598 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 4599
e0e0a67e
JL
4600 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
4601 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
4602 &priv->bands[IEEE80211_BAND_2GHZ];
4603 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
4604 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
4605 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 4606
b481de9c
ZY
4607 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4608
4609 return 0;
4610}
4611
849e0dce
RC
4612/*
4613 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
4614 */
4a8a4322 4615static void iwl3945_free_geos(struct iwl_priv *priv)
849e0dce 4616{
849e0dce
RC
4617 kfree(priv->ieee_channels);
4618 kfree(priv->ieee_rates);
4619 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
4620}
4621
b481de9c
ZY
4622/******************************************************************************
4623 *
4624 * uCode download functions
4625 *
4626 ******************************************************************************/
4627
4a8a4322 4628static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 4629{
98c92211
TW
4630 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
4631 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
4632 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
4633 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
4634 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
4635 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
4636}
4637
4638/**
bb8c093b 4639 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
4640 * looking at all data.
4641 */
4a8a4322 4642static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
4643{
4644 u32 val;
4645 u32 save_len = len;
4646 int rc = 0;
4647 u32 errcnt;
4648
4649 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
4650
5d49f498 4651 rc = iwl_grab_nic_access(priv);
b481de9c
ZY
4652 if (rc)
4653 return rc;
4654
5d49f498 4655 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 4656 IWL39_RTC_INST_LOWER_BOUND);
b481de9c
ZY
4657
4658 errcnt = 0;
4659 for (; len > 0; len -= sizeof(u32), image++) {
4660 /* read data comes through single port, auto-incr addr */
4661 /* NOTE: Use the debugless read so we don't flood kernel log
4662 * if IWL_DL_IO is set */
5d49f498 4663 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c 4664 if (val != le32_to_cpu(*image)) {
15b1687c 4665 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
4666 "offset 0x%x, is 0x%x, s/b 0x%x\n",
4667 save_len - len, val, le32_to_cpu(*image));
4668 rc = -EIO;
4669 errcnt++;
4670 if (errcnt >= 20)
4671 break;
4672 }
4673 }
4674
5d49f498 4675 iwl_release_nic_access(priv);
b481de9c
ZY
4676
4677 if (!errcnt)
bc434dd2 4678 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
4679
4680 return rc;
4681}
4682
4683
4684/**
bb8c093b 4685 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
4686 * using sample data 100 bytes apart. If these sample points are good,
4687 * it's a pretty good bet that everything between them is good, too.
4688 */
4a8a4322 4689static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
4690{
4691 u32 val;
4692 int rc = 0;
4693 u32 errcnt = 0;
4694 u32 i;
4695
4696 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
4697
5d49f498 4698 rc = iwl_grab_nic_access(priv);
b481de9c
ZY
4699 if (rc)
4700 return rc;
4701
4702 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
4703 /* read data comes through single port, auto-incr addr */
4704 /* NOTE: Use the debugless read so we don't flood kernel log
4705 * if IWL_DL_IO is set */
5d49f498 4706 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 4707 i + IWL39_RTC_INST_LOWER_BOUND);
5d49f498 4708 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
4709 if (val != le32_to_cpu(*image)) {
4710#if 0 /* Enable this if you want to see details */
15b1687c 4711 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
4712 "offset 0x%x, is 0x%x, s/b 0x%x\n",
4713 i, val, *image);
4714#endif
4715 rc = -EIO;
4716 errcnt++;
4717 if (errcnt >= 3)
4718 break;
4719 }
4720 }
4721
5d49f498 4722 iwl_release_nic_access(priv);
b481de9c
ZY
4723
4724 return rc;
4725}
4726
4727
4728/**
bb8c093b 4729 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
4730 * and verify its contents
4731 */
4a8a4322 4732static int iwl3945_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY
4733{
4734 __le32 *image;
4735 u32 len;
4736 int rc = 0;
4737
4738 /* Try bootstrap */
4739 image = (__le32 *)priv->ucode_boot.v_addr;
4740 len = priv->ucode_boot.len;
bb8c093b 4741 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
4742 if (rc == 0) {
4743 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
4744 return 0;
4745 }
4746
4747 /* Try initialize */
4748 image = (__le32 *)priv->ucode_init.v_addr;
4749 len = priv->ucode_init.len;
bb8c093b 4750 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
4751 if (rc == 0) {
4752 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
4753 return 0;
4754 }
4755
4756 /* Try runtime/protocol */
4757 image = (__le32 *)priv->ucode_code.v_addr;
4758 len = priv->ucode_code.len;
bb8c093b 4759 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY
4760 if (rc == 0) {
4761 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
4762 return 0;
4763 }
4764
15b1687c 4765 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b481de9c 4766
9fbab516
BC
4767 /* Since nothing seems to match, show first several data entries in
4768 * instruction SRAM, so maybe visual inspection will give a clue.
4769 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
4770 image = (__le32 *)priv->ucode_boot.v_addr;
4771 len = priv->ucode_boot.len;
bb8c093b 4772 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
4773
4774 return rc;
4775}
4776
4a8a4322 4777static void iwl3945_nic_start(struct iwl_priv *priv)
b481de9c
ZY
4778{
4779 /* Remove all resets to allow NIC to operate */
5d49f498 4780 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY
4781}
4782
4783/**
bb8c093b 4784 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
4785 *
4786 * Copy into buffers for card to fetch via bus-mastering
4787 */
4a8a4322 4788static int iwl3945_read_ucode(struct iwl_priv *priv)
b481de9c 4789{
a78fe754 4790 struct iwl_ucode *ucode;
a0987a8d 4791 int ret = -EINVAL, index;
b481de9c
ZY
4792 const struct firmware *ucode_raw;
4793 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC
4794 const char *name_pre = priv->cfg->fw_name_pre;
4795 const unsigned int api_max = priv->cfg->ucode_api_max;
4796 const unsigned int api_min = priv->cfg->ucode_api_min;
4797 char buf[25];
b481de9c
ZY
4798 u8 *src;
4799 size_t len;
a0987a8d 4800 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
4801
4802 /* Ask kernel firmware_class module to get the boot firmware off disk.
4803 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
4804 for (index = api_max; index >= api_min; index--) {
4805 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
4806 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
4807 if (ret < 0) {
15b1687c 4808 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
4809 buf, ret);
4810 if (ret == -ENOENT)
4811 continue;
4812 else
4813 goto error;
4814 } else {
4815 if (index < api_max)
15b1687c
WT
4816 IWL_ERR(priv, "Loaded firmware %s, "
4817 "which is deprecated. "
4818 " Please use API v%u instead.\n",
a0987a8d
RC
4819 buf, api_max);
4820 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
4821 buf, ucode_raw->size);
4822 break;
4823 }
b481de9c
ZY
4824 }
4825
a0987a8d
RC
4826 if (ret < 0)
4827 goto error;
b481de9c
ZY
4828
4829 /* Make sure that we got at least our header! */
4830 if (ucode_raw->size < sizeof(*ucode)) {
15b1687c 4831 IWL_ERR(priv, "File size way too small!\n");
90e759d1 4832 ret = -EINVAL;
b481de9c
ZY
4833 goto err_release;
4834 }
4835
4836 /* Data from ucode file: header followed by uCode images */
4837 ucode = (void *)ucode_raw->data;
4838
c02b3acd 4839 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 4840 api_ver = IWL_UCODE_API(priv->ucode_ver);
b481de9c
ZY
4841 inst_size = le32_to_cpu(ucode->inst_size);
4842 data_size = le32_to_cpu(ucode->data_size);
4843 init_size = le32_to_cpu(ucode->init_size);
4844 init_data_size = le32_to_cpu(ucode->init_data_size);
4845 boot_size = le32_to_cpu(ucode->boot_size);
4846
a0987a8d
RC
4847 /* api_ver should match the api version forming part of the
4848 * firmware filename ... but we don't check for that and only rely
4849 * on the API version read from firware header from here on forward */
4850
4851 if (api_ver < api_min || api_ver > api_max) {
15b1687c 4852 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
4853 "Driver supports v%u, firmware is v%u.\n",
4854 api_max, api_ver);
4855 priv->ucode_ver = 0;
4856 ret = -EINVAL;
4857 goto err_release;
4858 }
4859 if (api_ver != api_max)
15b1687c 4860 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
a0987a8d
RC
4861 "got %u. New firmware can be obtained "
4862 "from http://www.intellinuxwireless.org.\n",
4863 api_max, api_ver);
4864
978785a3
TW
4865 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
4866 IWL_UCODE_MAJOR(priv->ucode_ver),
4867 IWL_UCODE_MINOR(priv->ucode_ver),
4868 IWL_UCODE_API(priv->ucode_ver),
4869 IWL_UCODE_SERIAL(priv->ucode_ver));
4870
a0987a8d
RC
4871 IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
4872 priv->ucode_ver);
bc434dd2
IS
4873 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
4874 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
4875 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
4876 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
4877 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c 4878
a0987a8d 4879
b481de9c
ZY
4880 /* Verify size of file vs. image size info in file's header */
4881 if (ucode_raw->size < sizeof(*ucode) +
4882 inst_size + data_size + init_size +
4883 init_data_size + boot_size) {
4884
4885 IWL_DEBUG_INFO("uCode file size %d too small\n",
4886 (int)ucode_raw->size);
90e759d1 4887 ret = -EINVAL;
b481de9c
ZY
4888 goto err_release;
4889 }
4890
4891 /* Verify that uCode images will fit in card's SRAM */
250bdd21 4892 if (inst_size > IWL39_MAX_INST_SIZE) {
90e759d1
TW
4893 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
4894 inst_size);
4895 ret = -EINVAL;
b481de9c
ZY
4896 goto err_release;
4897 }
4898
250bdd21 4899 if (data_size > IWL39_MAX_DATA_SIZE) {
90e759d1
TW
4900 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
4901 data_size);
4902 ret = -EINVAL;
b481de9c
ZY
4903 goto err_release;
4904 }
250bdd21 4905 if (init_size > IWL39_MAX_INST_SIZE) {
90e759d1
TW
4906 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
4907 init_size);
4908 ret = -EINVAL;
b481de9c
ZY
4909 goto err_release;
4910 }
250bdd21 4911 if (init_data_size > IWL39_MAX_DATA_SIZE) {
90e759d1
TW
4912 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
4913 init_data_size);
4914 ret = -EINVAL;
b481de9c
ZY
4915 goto err_release;
4916 }
250bdd21 4917 if (boot_size > IWL39_MAX_BSM_SIZE) {
90e759d1
TW
4918 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
4919 boot_size);
4920 ret = -EINVAL;
b481de9c
ZY
4921 goto err_release;
4922 }
4923
4924 /* Allocate ucode buffers for card's bus-master loading ... */
4925
4926 /* Runtime instructions and 2 copies of data:
4927 * 1) unmodified from disk
4928 * 2) backup cache for save/restore during power-downs */
4929 priv->ucode_code.len = inst_size;
98c92211 4930 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
4931
4932 priv->ucode_data.len = data_size;
98c92211 4933 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
4934
4935 priv->ucode_data_backup.len = data_size;
98c92211 4936 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 4937
90e759d1
TW
4938 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
4939 !priv->ucode_data_backup.v_addr)
4940 goto err_pci_alloc;
b481de9c
ZY
4941
4942 /* Initialization instructions and data */
90e759d1
TW
4943 if (init_size && init_data_size) {
4944 priv->ucode_init.len = init_size;
98c92211 4945 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
4946
4947 priv->ucode_init_data.len = init_data_size;
98c92211 4948 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
4949
4950 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
4951 goto err_pci_alloc;
4952 }
b481de9c
ZY
4953
4954 /* Bootstrap (instructions only, no data) */
90e759d1
TW
4955 if (boot_size) {
4956 priv->ucode_boot.len = boot_size;
98c92211 4957 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 4958
90e759d1
TW
4959 if (!priv->ucode_boot.v_addr)
4960 goto err_pci_alloc;
4961 }
b481de9c
ZY
4962
4963 /* Copy images into buffers for card's bus-master reads ... */
4964
4965 /* Runtime instructions (first block of data in file) */
4966 src = &ucode->data[0];
4967 len = priv->ucode_code.len;
90e759d1 4968 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY
4969 memcpy(priv->ucode_code.v_addr, src, len);
4970 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
4971 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
4972
4973 /* Runtime data (2nd block)
bb8c093b 4974 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY
4975 src = &ucode->data[inst_size];
4976 len = priv->ucode_data.len;
90e759d1 4977 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
4978 memcpy(priv->ucode_data.v_addr, src, len);
4979 memcpy(priv->ucode_data_backup.v_addr, src, len);
4980
4981 /* Initialization instructions (3rd block) */
4982 if (init_size) {
4983 src = &ucode->data[inst_size + data_size];
4984 len = priv->ucode_init.len;
90e759d1
TW
4985 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
4986 len);
b481de9c
ZY
4987 memcpy(priv->ucode_init.v_addr, src, len);
4988 }
4989
4990 /* Initialization data (4th block) */
4991 if (init_data_size) {
4992 src = &ucode->data[inst_size + data_size + init_size];
4993 len = priv->ucode_init_data.len;
4994 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
4995 (int)len);
4996 memcpy(priv->ucode_init_data.v_addr, src, len);
4997 }
4998
4999 /* Bootstrap instructions (5th block) */
5000 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5001 len = priv->ucode_boot.len;
5002 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5003 (int)len);
5004 memcpy(priv->ucode_boot.v_addr, src, len);
5005
5006 /* We have our copies now, allow OS release its copies */
5007 release_firmware(ucode_raw);
5008 return 0;
5009
5010 err_pci_alloc:
15b1687c 5011 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 5012 ret = -ENOMEM;
bb8c093b 5013 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
5014
5015 err_release:
5016 release_firmware(ucode_raw);
5017
5018 error:
90e759d1 5019 return ret;
b481de9c
ZY
5020}
5021
5022
5023/**
bb8c093b 5024 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
5025 *
5026 * Tell initialization uCode where to find runtime uCode.
5027 *
5028 * BSM registers initially contain pointers to initialization uCode.
5029 * We need to replace them to load runtime uCode inst and data,
5030 * and to save runtime data when powering down.
5031 */
4a8a4322 5032static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY
5033{
5034 dma_addr_t pinst;
5035 dma_addr_t pdata;
5036 int rc = 0;
5037 unsigned long flags;
5038
5039 /* bits 31:0 for 3945 */
5040 pinst = priv->ucode_code.p_addr;
5041 pdata = priv->ucode_data_backup.p_addr;
5042
5043 spin_lock_irqsave(&priv->lock, flags);
5d49f498 5044 rc = iwl_grab_nic_access(priv);
b481de9c
ZY
5045 if (rc) {
5046 spin_unlock_irqrestore(&priv->lock, flags);
5047 return rc;
5048 }
5049
5050 /* Tell bootstrap uCode where to find image to load */
5d49f498
AK
5051 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5052 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5053 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
5054 priv->ucode_data.len);
5055
a96a27f9 5056 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 5057 * that all new ptr/size info is in place */
5d49f498 5058 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
5059 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5060
5d49f498 5061 iwl_release_nic_access(priv);
b481de9c
ZY
5062
5063 spin_unlock_irqrestore(&priv->lock, flags);
5064
5065 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5066
5067 return rc;
5068}
5069
5070/**
bb8c093b 5071 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
5072 *
5073 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5074 *
b481de9c 5075 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 5076 */
4a8a4322 5077static void iwl3945_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY
5078{
5079 /* Check alive response for "valid" sign from uCode */
5080 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5081 /* We had an error bringing up the hardware, so take it
5082 * all the way back down so we can try again */
5083 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5084 goto restart;
5085 }
5086
5087 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5088 * This is a paranoid check, because we would not have gotten the
5089 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5090 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
5091 /* Runtime instruction load was bad;
5092 * take it all the way back down so we can try again */
5093 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5094 goto restart;
5095 }
5096
5097 /* Send pointers to protocol/runtime uCode image ... init code will
5098 * load and launch runtime uCode, which will send us another "Alive"
5099 * notification. */
5100 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5101 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
5102 /* Runtime instruction load won't happen;
5103 * take it all the way back down so we can try again */
5104 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5105 goto restart;
5106 }
5107 return;
5108
5109 restart:
5110 queue_work(priv->workqueue, &priv->restart);
5111}
5112
5113
9bdf5eca
MA
5114/* temporary */
5115static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
5116 struct sk_buff *skb);
5117
b481de9c 5118/**
bb8c093b 5119 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 5120 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5121 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 5122 */
4a8a4322 5123static void iwl3945_alive_start(struct iwl_priv *priv)
b481de9c
ZY
5124{
5125 int rc = 0;
5126 int thermal_spin = 0;
5127 u32 rfkill;
5128
5129 IWL_DEBUG_INFO("Runtime Alive received.\n");
5130
5131 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5132 /* We had an error bringing up the hardware, so take it
5133 * all the way back down so we can try again */
5134 IWL_DEBUG_INFO("Alive failed.\n");
5135 goto restart;
5136 }
5137
5138 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5139 * This is a paranoid check, because we would not have gotten the
5140 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5141 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
5142 /* Runtime instruction load was bad;
5143 * take it all the way back down so we can try again */
5144 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5145 goto restart;
5146 }
5147
bb8c093b 5148 iwl3945_clear_stations_table(priv);
b481de9c 5149
5d49f498 5150 rc = iwl_grab_nic_access(priv);
b481de9c 5151 if (rc) {
39aadf8c 5152 IWL_WARN(priv, "Can not read RFKILL status from adapter\n");
b481de9c
ZY
5153 return;
5154 }
5155
5d49f498 5156 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
b481de9c 5157 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
5d49f498 5158 iwl_release_nic_access(priv);
b481de9c
ZY
5159
5160 if (rfkill & 0x1) {
5161 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 5162 /* if RFKILL is not on, then wait for thermal
b481de9c 5163 * sensor in adapter to kick in */
bb8c093b 5164 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
5165 thermal_spin++;
5166 udelay(10);
5167 }
5168
5169 if (thermal_spin)
5170 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5171 thermal_spin * 10);
5172 } else
5173 set_bit(STATUS_RF_KILL_HW, &priv->status);
5174
9fbab516 5175 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
5176 set_bit(STATUS_ALIVE, &priv->status);
5177
5178 /* Clear out the uCode error bit if it is set */
5179 clear_bit(STATUS_FW_ERROR, &priv->status);
5180
775a6e27 5181 if (iwl_is_rfkill(priv))
b481de9c
ZY
5182 return;
5183
36d6825b 5184 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
5185
5186 priv->active_rate = priv->rates_mask;
5187 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5188
bb8c093b 5189 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5190
bb8c093b
CH
5191 if (iwl3945_is_associated(priv)) {
5192 struct iwl3945_rxon_cmd *active_rxon =
f2c7e521 5193 (struct iwl3945_rxon_cmd *)(&priv->active39_rxon);
b481de9c 5194
f2c7e521
AK
5195 memcpy(&priv->staging39_rxon, &priv->active39_rxon,
5196 sizeof(priv->staging39_rxon));
b481de9c
ZY
5197 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5198 } else {
5199 /* Initialize our rx_config data */
60294de3 5200 iwl3945_connection_init_rx_config(priv, priv->iw_mode);
f2c7e521 5201 memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
b481de9c
ZY
5202 }
5203
9fbab516 5204 /* Configure Bluetooth device coexistence support */
bb8c093b 5205 iwl3945_send_bt_config(priv);
b481de9c
ZY
5206
5207 /* Configure the adapter for unassociated operation */
bb8c093b 5208 iwl3945_commit_rxon(priv);
b481de9c 5209
b481de9c
ZY
5210 iwl3945_reg_txpower_periodic(priv);
5211
fe00b5a5
RC
5212 iwl3945_led_register(priv);
5213
b481de9c 5214 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5215 set_bit(STATUS_READY, &priv->status);
5a66926a 5216 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
5217
5218 if (priv->error_recovering)
bb8c093b 5219 iwl3945_error_recovery(priv);
b481de9c 5220
9bdf5eca
MA
5221 /* reassociate for ADHOC mode */
5222 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
5223 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
5224 priv->vif);
5225 if (beacon)
5226 iwl3945_mac_beacon_update(priv->hw, beacon);
5227 }
5228
b481de9c
ZY
5229 return;
5230
5231 restart:
5232 queue_work(priv->workqueue, &priv->restart);
5233}
5234
4a8a4322 5235static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 5236
4a8a4322 5237static void __iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
5238{
5239 unsigned long flags;
5240 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5241 struct ieee80211_conf *conf = NULL;
5242
5243 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5244
5245 conf = ieee80211_get_hw_conf(priv->hw);
5246
5247 if (!exit_pending)
5248 set_bit(STATUS_EXIT_PENDING, &priv->status);
5249
ab53d8af 5250 iwl3945_led_unregister(priv);
bb8c093b 5251 iwl3945_clear_stations_table(priv);
b481de9c
ZY
5252
5253 /* Unblock any waiting calls */
5254 wake_up_interruptible_all(&priv->wait_command_queue);
5255
b481de9c
ZY
5256 /* Wipe out the EXIT_PENDING status bit if we are not actually
5257 * exiting the module */
5258 if (!exit_pending)
5259 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5260
5261 /* stop and reset the on-board processor */
5d49f498 5262 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
5263
5264 /* tell the device to stop sending interrupts */
0359facc 5265 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5266 iwl3945_disable_interrupts(priv);
0359facc
MA
5267 spin_unlock_irqrestore(&priv->lock, flags);
5268 iwl_synchronize_irq(priv);
b481de9c
ZY
5269
5270 if (priv->mac80211_registered)
5271 ieee80211_stop_queues(priv->hw);
5272
bb8c093b 5273 /* If we have not previously called iwl3945_init() then
b481de9c 5274 * clear all bits but the RF Kill and SUSPEND bits and return */
775a6e27 5275 if (!iwl_is_init(priv)) {
b481de9c
ZY
5276 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5277 STATUS_RF_KILL_HW |
5278 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5279 STATUS_RF_KILL_SW |
9788864e
RC
5280 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5281 STATUS_GEO_CONFIGURED |
b481de9c 5282 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
ebef2008
AK
5283 STATUS_IN_SUSPEND |
5284 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5285 STATUS_EXIT_PENDING;
b481de9c
ZY
5286 goto exit;
5287 }
5288
5289 /* ...otherwise clear out all the status bits but the RF Kill and
5290 * SUSPEND bits and continue taking the NIC down. */
5291 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5292 STATUS_RF_KILL_HW |
5293 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5294 STATUS_RF_KILL_SW |
9788864e
RC
5295 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5296 STATUS_GEO_CONFIGURED |
b481de9c
ZY
5297 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5298 STATUS_IN_SUSPEND |
5299 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK
5300 STATUS_FW_ERROR |
5301 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5302 STATUS_EXIT_PENDING;
b481de9c
ZY
5303
5304 spin_lock_irqsave(&priv->lock, flags);
5d49f498 5305 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
5306 spin_unlock_irqrestore(&priv->lock, flags);
5307
bb8c093b
CH
5308 iwl3945_hw_txq_ctx_stop(priv);
5309 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY
5310
5311 spin_lock_irqsave(&priv->lock, flags);
5d49f498
AK
5312 if (!iwl_grab_nic_access(priv)) {
5313 iwl_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5314 APMG_CLK_VAL_DMA_CLK_RQT);
5d49f498 5315 iwl_release_nic_access(priv);
b481de9c
ZY
5316 }
5317 spin_unlock_irqrestore(&priv->lock, flags);
5318
5319 udelay(5);
5320
01ec616d 5321 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 5322 exit:
3d24a9f7 5323 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
5324
5325 if (priv->ibss_beacon)
5326 dev_kfree_skb(priv->ibss_beacon);
5327 priv->ibss_beacon = NULL;
5328
5329 /* clear out any free frames */
bb8c093b 5330 iwl3945_clear_free_frames(priv);
b481de9c
ZY
5331}
5332
4a8a4322 5333static void iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
5334{
5335 mutex_lock(&priv->mutex);
bb8c093b 5336 __iwl3945_down(priv);
b481de9c 5337 mutex_unlock(&priv->mutex);
b24d22b1 5338
bb8c093b 5339 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
5340}
5341
5342#define MAX_HW_RESTARTS 5
5343
4a8a4322 5344static int __iwl3945_up(struct iwl_priv *priv)
b481de9c
ZY
5345{
5346 int rc, i;
5347
5348 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 5349 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
5350 return -EIO;
5351 }
5352
5353 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
39aadf8c 5354 IWL_WARN(priv, "Radio disabled by SW RF kill (module "
b481de9c 5355 "parameter)\n");
e655b9f0
ZY
5356 return -ENODEV;
5357 }
5358
e903fbd4 5359 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 5360 IWL_ERR(priv, "ucode not available for device bring up\n");
e903fbd4
RC
5361 return -EIO;
5362 }
5363
e655b9f0 5364 /* If platform's RF_KILL switch is NOT set to KILL */
5d49f498 5365 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY
5366 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5367 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5368 else {
5369 set_bit(STATUS_RF_KILL_HW, &priv->status);
5370 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
39aadf8c 5371 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
e655b9f0
ZY
5372 return -ENODEV;
5373 }
b481de9c 5374 }
80fcc9e2 5375
5d49f498 5376 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 5377
bb8c093b 5378 rc = iwl3945_hw_nic_init(priv);
b481de9c 5379 if (rc) {
15b1687c 5380 IWL_ERR(priv, "Unable to int nic\n");
b481de9c
ZY
5381 return rc;
5382 }
5383
5384 /* make sure rfkill handshake bits are cleared */
5d49f498
AK
5385 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5386 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
5387 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5388
5389 /* clear (again), then enable host interrupts */
5d49f498 5390 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
bb8c093b 5391 iwl3945_enable_interrupts(priv);
b481de9c
ZY
5392
5393 /* really make sure rfkill handshake bits are cleared */
5d49f498
AK
5394 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5395 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
5396
5397 /* Copy original ucode data image from disk into backup cache.
5398 * This will be used to initialize the on-board processor's
5399 * data SRAM for a clean start when the runtime program first loads. */
5400 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 5401 priv->ucode_data.len);
b481de9c 5402
e655b9f0
ZY
5403 /* We return success when we resume from suspend and rf_kill is on. */
5404 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
5405 return 0;
5406
b481de9c
ZY
5407 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5408
bb8c093b 5409 iwl3945_clear_stations_table(priv);
b481de9c
ZY
5410
5411 /* load bootstrap state machine,
5412 * load bootstrap program into processor's memory,
5413 * prepare to load the "initialize" uCode */
0164b9b4 5414 priv->cfg->ops->lib->load_ucode(priv);
b481de9c
ZY
5415
5416 if (rc) {
15b1687c
WT
5417 IWL_ERR(priv,
5418 "Unable to set up bootstrap uCode: %d\n", rc);
b481de9c
ZY
5419 continue;
5420 }
5421
5422 /* start card; "initialize" will load runtime ucode */
bb8c093b 5423 iwl3945_nic_start(priv);
b481de9c 5424
b481de9c
ZY
5425 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
5426
5427 return 0;
5428 }
5429
5430 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 5431 __iwl3945_down(priv);
ebef2008 5432 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
5433
5434 /* tried to restart and config the device for as long as our
5435 * patience could withstand */
15b1687c 5436 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
5437 return -EIO;
5438}
5439
5440
5441/*****************************************************************************
5442 *
5443 * Workqueue callbacks
5444 *
5445 *****************************************************************************/
5446
bb8c093b 5447static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 5448{
4a8a4322
AK
5449 struct iwl_priv *priv =
5450 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
5451
5452 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5453 return;
5454
5455 mutex_lock(&priv->mutex);
bb8c093b 5456 iwl3945_init_alive_start(priv);
b481de9c
ZY
5457 mutex_unlock(&priv->mutex);
5458}
5459
bb8c093b 5460static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 5461{
4a8a4322
AK
5462 struct iwl_priv *priv =
5463 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
5464
5465 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5466 return;
5467
5468 mutex_lock(&priv->mutex);
bb8c093b 5469 iwl3945_alive_start(priv);
b481de9c
ZY
5470 mutex_unlock(&priv->mutex);
5471}
5472
bb8c093b 5473static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 5474{
4a8a4322 5475 struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill);
b481de9c
ZY
5476
5477 wake_up_interruptible(&priv->wait_command_queue);
5478
5479 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5480 return;
5481
5482 mutex_lock(&priv->mutex);
5483
775a6e27 5484 if (!iwl_is_rfkill(priv)) {
b481de9c
ZY
5485 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
5486 "HW and/or SW RF Kill no longer active, restarting "
5487 "device\n");
2663516d
HS
5488 if (!test_bit(STATUS_EXIT_PENDING, &priv->status) &&
5489 test_bit(STATUS_ALIVE, &priv->status))
b481de9c
ZY
5490 queue_work(priv->workqueue, &priv->restart);
5491 } else {
5492
5493 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
5494 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
5495 "disabled by SW switch\n");
5496 else
39aadf8c 5497 IWL_WARN(priv, "Radio Frequency Kill Switch is On:\n"
b481de9c
ZY
5498 "Kill switch must be turned off for "
5499 "wireless networking to work.\n");
5500 }
ebef2008 5501
b481de9c 5502 mutex_unlock(&priv->mutex);
80fcc9e2 5503 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY
5504}
5505
2663516d
HS
5506static void iwl3945_rfkill_poll(struct work_struct *data)
5507{
5508 struct iwl_priv *priv =
5509 container_of(data, struct iwl_priv, rfkill_poll.work);
5510 unsigned long status = priv->status;
5511
5512 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5513 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5514 else
5515 set_bit(STATUS_RF_KILL_HW, &priv->status);
5516
5517 if (test_bit(STATUS_RF_KILL_HW, &status) != test_bit(STATUS_RF_KILL_HW, &priv->status))
5518 queue_work(priv->workqueue, &priv->rf_kill);
5519
5520 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
5521 round_jiffies_relative(2 * HZ));
5522
5523}
5524
b481de9c
ZY
5525#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
5526
bb8c093b 5527static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 5528{
4a8a4322
AK
5529 struct iwl_priv *priv =
5530 container_of(data, struct iwl_priv, scan_check.work);
b481de9c
ZY
5531
5532 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5533 return;
5534
5535 mutex_lock(&priv->mutex);
5536 if (test_bit(STATUS_SCANNING, &priv->status) ||
5537 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
5538 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
5539 "Scan completion watchdog resetting adapter (%dms)\n",
5540 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 5541
b481de9c 5542 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 5543 iwl3945_send_scan_abort(priv);
b481de9c
ZY
5544 }
5545 mutex_unlock(&priv->mutex);
5546}
5547
bb8c093b 5548static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 5549{
4a8a4322
AK
5550 struct iwl_priv *priv =
5551 container_of(data, struct iwl_priv, request_scan);
c2d79b48 5552 struct iwl_host_cmd cmd = {
b481de9c 5553 .id = REPLY_SCAN_CMD,
bb8c093b 5554 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY
5555 .meta.flags = CMD_SIZE_HUGE,
5556 };
5557 int rc = 0;
bb8c093b 5558 struct iwl3945_scan_cmd *scan;
b481de9c 5559 struct ieee80211_conf *conf = NULL;
f9340520 5560 u8 n_probes = 2;
8318d78a 5561 enum ieee80211_band band;
9387b7ca 5562 DECLARE_SSID_BUF(ssid);
b481de9c
ZY
5563
5564 conf = ieee80211_get_hw_conf(priv->hw);
5565
5566 mutex_lock(&priv->mutex);
5567
775a6e27 5568 if (!iwl_is_ready(priv)) {
39aadf8c 5569 IWL_WARN(priv, "request scan called when driver not ready.\n");
b481de9c
ZY
5570 goto done;
5571 }
5572
a96a27f9 5573 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY
5574 * was given the chance to run... */
5575 if (!test_bit(STATUS_SCANNING, &priv->status))
5576 goto done;
5577
5578 /* This should never be called or scheduled if there is currently
5579 * a scan active in the hardware. */
5580 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
5581 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
5582 "Ignoring second request.\n");
5583 rc = -EIO;
5584 goto done;
5585 }
5586
5587 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5588 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
5589 goto done;
5590 }
5591
5592 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
5593 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
5594 goto done;
5595 }
5596
775a6e27 5597 if (iwl_is_rfkill(priv)) {
b481de9c
ZY
5598 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
5599 goto done;
5600 }
5601
5602 if (!test_bit(STATUS_READY, &priv->status)) {
5603 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
5604 goto done;
5605 }
5606
5607 if (!priv->scan_bands) {
5608 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
5609 goto done;
5610 }
5611
f2c7e521
AK
5612 if (!priv->scan39) {
5613 priv->scan39 = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c 5614 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
f2c7e521 5615 if (!priv->scan39) {
b481de9c
ZY
5616 rc = -ENOMEM;
5617 goto done;
5618 }
5619 }
f2c7e521 5620 scan = priv->scan39;
bb8c093b 5621 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
5622
5623 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
5624 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
5625
bb8c093b 5626 if (iwl3945_is_associated(priv)) {
b481de9c
ZY
5627 u16 interval = 0;
5628 u32 extra;
5629 u32 suspend_time = 100;
5630 u32 scan_suspend_time = 100;
5631 unsigned long flags;
5632
5633 IWL_DEBUG_INFO("Scanning while associated...\n");
5634
5635 spin_lock_irqsave(&priv->lock, flags);
5636 interval = priv->beacon_int;
5637 spin_unlock_irqrestore(&priv->lock, flags);
5638
5639 scan->suspend_time = 0;
15e869d8 5640 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
5641 if (!interval)
5642 interval = suspend_time;
5643 /*
5644 * suspend time format:
5645 * 0-19: beacon interval in usec (time before exec.)
5646 * 20-23: 0
5647 * 24-31: number of beacons (suspend between channels)
5648 */
5649
5650 extra = (suspend_time / interval) << 24;
5651 scan_suspend_time = 0xFF0FFFFF &
5652 (extra | ((suspend_time % interval) * 1024));
5653
5654 scan->suspend_time = cpu_to_le32(scan_suspend_time);
5655 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
5656 scan_suspend_time, interval);
5657 }
5658
5659 /* We should add the ability for user to lock to PASSIVE ONLY */
5660 if (priv->one_direct_scan) {
5661 IWL_DEBUG_SCAN
5662 ("Kicking off one direct scan for '%s'\n",
9387b7ca
JL
5663 print_ssid(ssid, priv->direct_ssid,
5664 priv->direct_ssid_len));
b481de9c
ZY
5665 scan->direct_scan[0].id = WLAN_EID_SSID;
5666 scan->direct_scan[0].len = priv->direct_ssid_len;
5667 memcpy(scan->direct_scan[0].ssid,
5668 priv->direct_ssid, priv->direct_ssid_len);
f9340520 5669 n_probes++;
f9340520 5670 } else
786b4557 5671 IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
b481de9c
ZY
5672
5673 /* We don't build a direct scan probe request; the uCode will do
5674 * that based on the direct_mask added to each channel entry */
5675 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 5676 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
430cfe95 5677 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
b481de9c 5678 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
3832ec9d 5679 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY
5680 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
5681
5682 /* flags + rate selection */
5683
66b5004d 5684 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY
5685 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
5686 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
5687 scan->good_CRC_th = 0;
8318d78a 5688 band = IEEE80211_BAND_2GHZ;
66b5004d 5689 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c
ZY
5690 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
5691 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 5692 band = IEEE80211_BAND_5GHZ;
66b5004d 5693 } else {
39aadf8c 5694 IWL_WARN(priv, "Invalid scan band count\n");
b481de9c
ZY
5695 goto done;
5696 }
5697
5698 /* select Rx antennas */
5699 scan->flags |= iwl3945_get_antenna_flags(priv);
5700
05c914fe 5701 if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
b481de9c
ZY
5702 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
5703
f9340520
AK
5704 scan->channel_count =
5705 iwl3945_get_channels_for_scan(priv, band, 1, /* active */
5706 n_probes,
5707 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 5708
14b54336
RC
5709 if (scan->channel_count == 0) {
5710 IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
5711 goto done;
5712 }
5713
b481de9c 5714 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 5715 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
5716 cmd.data = scan;
5717 scan->len = cpu_to_le16(cmd.len);
5718
5719 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 5720 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY
5721 if (rc)
5722 goto done;
5723
5724 queue_delayed_work(priv->workqueue, &priv->scan_check,
5725 IWL_SCAN_CHECK_WATCHDOG);
5726
5727 mutex_unlock(&priv->mutex);
5728 return;
5729
5730 done:
2420ebc1
MA
5731 /* can not perform scan make sure we clear scanning
5732 * bits from status so next scan request can be performed.
5733 * if we dont clear scanning status bit here all next scan
5734 * will fail
5735 */
5736 clear_bit(STATUS_SCAN_HW, &priv->status);
5737 clear_bit(STATUS_SCANNING, &priv->status);
5738
01ebd063 5739 /* inform mac80211 scan aborted */
b481de9c
ZY
5740 queue_work(priv->workqueue, &priv->scan_completed);
5741 mutex_unlock(&priv->mutex);
5742}
5743
bb8c093b 5744static void iwl3945_bg_up(struct work_struct *data)
b481de9c 5745{
4a8a4322 5746 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
5747
5748 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5749 return;
5750
5751 mutex_lock(&priv->mutex);
bb8c093b 5752 __iwl3945_up(priv);
b481de9c 5753 mutex_unlock(&priv->mutex);
80fcc9e2 5754 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY
5755}
5756
bb8c093b 5757static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 5758{
4a8a4322 5759 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
5760
5761 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5762 return;
5763
bb8c093b 5764 iwl3945_down(priv);
b481de9c
ZY
5765 queue_work(priv->workqueue, &priv->up);
5766}
5767
bb8c093b 5768static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 5769{
4a8a4322
AK
5770 struct iwl_priv *priv =
5771 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
5772
5773 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5774 return;
5775
5776 mutex_lock(&priv->mutex);
bb8c093b 5777 iwl3945_rx_replenish(priv);
b481de9c
ZY
5778 mutex_unlock(&priv->mutex);
5779}
5780
7878a5a4
MA
5781#define IWL_DELAY_NEXT_SCAN (HZ*2)
5782
4a8a4322 5783static void iwl3945_post_associate(struct iwl_priv *priv)
b481de9c 5784{
b481de9c
ZY
5785 int rc = 0;
5786 struct ieee80211_conf *conf = NULL;
5787
05c914fe 5788 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 5789 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
5790 return;
5791 }
5792
5793
e174961c 5794 IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
f2c7e521 5795 priv->assoc_id, priv->active39_rxon.bssid_addr);
b481de9c
ZY
5796
5797 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5798 return;
5799
322a9811 5800 if (!priv->vif || !priv->is_open)
6ef89d0a 5801 return;
322a9811 5802
bb8c093b 5803 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 5804
b481de9c
ZY
5805 conf = ieee80211_get_hw_conf(priv->hw);
5806
f2c7e521 5807 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 5808 iwl3945_commit_rxon(priv);
b481de9c 5809
28afaf91 5810 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
bb8c093b
CH
5811 iwl3945_setup_rxon_timing(priv);
5812 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
5813 sizeof(priv->rxon_timing), &priv->rxon_timing);
5814 if (rc)
39aadf8c 5815 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
5816 "Attempting to continue.\n");
5817
f2c7e521 5818 priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 5819
f2c7e521 5820 priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c
ZY
5821
5822 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
5823 priv->assoc_id, priv->beacon_int);
5824
5825 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
f2c7e521 5826 priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 5827 else
f2c7e521 5828 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 5829
f2c7e521 5830 if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c 5831 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
f2c7e521 5832 priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 5833 else
f2c7e521 5834 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 5835
05c914fe 5836 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
f2c7e521 5837 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY
5838
5839 }
5840
bb8c093b 5841 iwl3945_commit_rxon(priv);
b481de9c
ZY
5842
5843 switch (priv->iw_mode) {
05c914fe 5844 case NL80211_IFTYPE_STATION:
bb8c093b 5845 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
5846 break;
5847
05c914fe 5848 case NL80211_IFTYPE_ADHOC:
b481de9c 5849
ce546fd2 5850 priv->assoc_id = 1;
bb8c093b 5851 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 5852 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 5853 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY
5854 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
5855 CMD_ASYNC);
bb8c093b
CH
5856 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
5857 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
5858
5859 break;
5860
5861 default:
15b1687c 5862 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 5863 __func__, priv->iw_mode);
b481de9c
ZY
5864 break;
5865 }
5866
bb8c093b 5867 iwl3945_activate_qos(priv, 0);
292ae174 5868
7878a5a4
MA
5869 /* we have just associated, don't start scan too early */
5870 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK
5871}
5872
bb8c093b 5873static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 5874{
4a8a4322 5875 struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan);
b481de9c 5876
775a6e27 5877 if (!iwl_is_ready(priv))
b481de9c
ZY
5878 return;
5879
5880 mutex_lock(&priv->mutex);
5881
5882 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 5883 iwl3945_send_scan_abort(priv);
b481de9c
ZY
5884
5885 mutex_unlock(&priv->mutex);
5886}
5887
e8975581 5888static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
76bb77e0 5889
bb8c093b 5890static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 5891{
4a8a4322
AK
5892 struct iwl_priv *priv =
5893 container_of(work, struct iwl_priv, scan_completed);
b481de9c
ZY
5894
5895 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
5896
5897 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5898 return;
5899
a0646470 5900 if (test_bit(STATUS_CONF_PENDING, &priv->status))
e8975581 5901 iwl3945_mac_config(priv->hw, 0);
76bb77e0 5902
b481de9c
ZY
5903 ieee80211_scan_completed(priv->hw);
5904
5905 /* Since setting the TXPOWER may have been deferred while
5906 * performing the scan, fire one off */
5907 mutex_lock(&priv->mutex);
bb8c093b 5908 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY
5909 mutex_unlock(&priv->mutex);
5910}
5911
5912/*****************************************************************************
5913 *
5914 * mac80211 entry point functions
5915 *
5916 *****************************************************************************/
5917
5a66926a
ZY
5918#define UCODE_READY_TIMEOUT (2 * HZ)
5919
bb8c093b 5920static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 5921{
4a8a4322 5922 struct iwl_priv *priv = hw->priv;
5a66926a 5923 int ret;
b481de9c
ZY
5924
5925 IWL_DEBUG_MAC80211("enter\n");
5926
5927 /* we should be verifying the device is ready to be opened */
5928 mutex_lock(&priv->mutex);
5929
f2c7e521 5930 memset(&priv->staging39_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
5a66926a
ZY
5931 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
5932 * ucode filename and max sizes are card-specific. */
5933
5934 if (!priv->ucode_code.len) {
5935 ret = iwl3945_read_ucode(priv);
5936 if (ret) {
15b1687c 5937 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a
ZY
5938 mutex_unlock(&priv->mutex);
5939 goto out_release_irq;
5940 }
5941 }
b481de9c 5942
e655b9f0 5943 ret = __iwl3945_up(priv);
b481de9c
ZY
5944
5945 mutex_unlock(&priv->mutex);
5a66926a 5946
80fcc9e2
AG
5947 iwl3945_rfkill_set_hw_state(priv);
5948
e655b9f0
ZY
5949 if (ret)
5950 goto out_release_irq;
5951
5952 IWL_DEBUG_INFO("Start UP work.\n");
5953
5954 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
5955 return 0;
5956
5a66926a
ZY
5957 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
5958 * mac80211 will not be run successfully. */
5959 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
5960 test_bit(STATUS_READY, &priv->status),
5961 UCODE_READY_TIMEOUT);
5962 if (!ret) {
5963 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c
WT
5964 IWL_ERR(priv,
5965 "Wait for START_ALIVE timeout after %dms.\n",
5966 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5a66926a
ZY
5967 ret = -ETIMEDOUT;
5968 goto out_release_irq;
5969 }
5970 }
5971
2663516d
HS
5972 /* ucode is running and will send rfkill notifications,
5973 * no need to poll the killswitch state anymore */
5974 cancel_delayed_work(&priv->rfkill_poll);
5975
e655b9f0 5976 priv->is_open = 1;
b481de9c
ZY
5977 IWL_DEBUG_MAC80211("leave\n");
5978 return 0;
5a66926a
ZY
5979
5980out_release_irq:
e655b9f0
ZY
5981 priv->is_open = 0;
5982 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 5983 return ret;
b481de9c
ZY
5984}
5985
bb8c093b 5986static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 5987{
4a8a4322 5988 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
5989
5990 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 5991
e655b9f0
ZY
5992 if (!priv->is_open) {
5993 IWL_DEBUG_MAC80211("leave - skip\n");
5994 return;
5995 }
5996
b481de9c 5997 priv->is_open = 0;
5a66926a 5998
775a6e27 5999 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
6000 /* stop mac, cancel any scan request and clear
6001 * RXON_FILTER_ASSOC_MSK BIT
6002 */
5a66926a
ZY
6003 mutex_lock(&priv->mutex);
6004 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f 6005 mutex_unlock(&priv->mutex);
fde3571f
MA
6006 }
6007
5a66926a
ZY
6008 iwl3945_down(priv);
6009
6010 flush_workqueue(priv->workqueue);
2663516d
HS
6011
6012 /* start polling the killswitch state again */
6013 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
6014 round_jiffies_relative(2 * HZ));
6ef89d0a 6015
b481de9c 6016 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
6017}
6018
e039fa4a 6019static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6020{
4a8a4322 6021 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6022
6023 IWL_DEBUG_MAC80211("enter\n");
6024
b481de9c 6025 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 6026 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 6027
e039fa4a 6028 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY
6029 dev_kfree_skb_any(skb);
6030
6031 IWL_DEBUG_MAC80211("leave\n");
637f8837 6032 return NETDEV_TX_OK;
b481de9c
ZY
6033}
6034
bb8c093b 6035static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY
6036 struct ieee80211_if_init_conf *conf)
6037{
4a8a4322 6038 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6039 unsigned long flags;
6040
32bfd35d 6041 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6042
32bfd35d
JB
6043 if (priv->vif) {
6044 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6045 return -EOPNOTSUPP;
b481de9c
ZY
6046 }
6047
6048 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6049 priv->vif = conf->vif;
60294de3 6050 priv->iw_mode = conf->type;
b481de9c
ZY
6051
6052 spin_unlock_irqrestore(&priv->lock, flags);
6053
6054 mutex_lock(&priv->mutex);
864792e3
TW
6055
6056 if (conf->mac_addr) {
e174961c 6057 IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
864792e3
TW
6058 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6059 }
6060
775a6e27 6061 if (iwl_is_ready(priv))
5a66926a 6062 iwl3945_set_mode(priv, conf->type);
b481de9c 6063
b481de9c
ZY
6064 mutex_unlock(&priv->mutex);
6065
5a66926a 6066 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
6067 return 0;
6068}
6069
6070/**
bb8c093b 6071 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY
6072 *
6073 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6074 * be set inappropriately and the driver currently sets the hardware up to
6075 * use it whenever needed.
6076 */
e8975581 6077static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
b481de9c 6078{
4a8a4322 6079 struct iwl_priv *priv = hw->priv;
d20b3c65 6080 const struct iwl_channel_info *ch_info;
e8975581 6081 struct ieee80211_conf *conf = &hw->conf;
b481de9c 6082 unsigned long flags;
76bb77e0 6083 int ret = 0;
b481de9c
ZY
6084
6085 mutex_lock(&priv->mutex);
8318d78a 6086 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6087
775a6e27 6088 if (!iwl_is_ready(priv)) {
b481de9c 6089 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY
6090 ret = -EIO;
6091 goto out;
b481de9c
ZY
6092 }
6093
df878d8f 6094 if (unlikely(!iwl3945_mod_params.disable_hw_scan &&
b481de9c 6095 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY
6096 IWL_DEBUG_MAC80211("leave - scanning\n");
6097 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6098 mutex_unlock(&priv->mutex);
a0646470 6099 return 0;
b481de9c
ZY
6100 }
6101
6102 spin_lock_irqsave(&priv->lock, flags);
6103
8318d78a
JB
6104 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
6105 conf->channel->hw_value);
b481de9c 6106 if (!is_channel_valid(ch_info)) {
66b5004d 6107 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
8318d78a 6108 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY
6109 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6110 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY
6111 ret = -EINVAL;
6112 goto out;
b481de9c
ZY
6113 }
6114
8318d78a 6115 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 6116
8318d78a 6117 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY
6118
6119 /* The list of supported rates and rate mask can be different
6120 * for each phymode; since the phymode may have changed, reset
6121 * the rate mask to what mac80211 lists */
bb8c093b 6122 iwl3945_set_rate(priv);
b481de9c
ZY
6123
6124 spin_unlock_irqrestore(&priv->lock, flags);
6125
6126#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6127 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6128 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 6129 goto out;
b481de9c
ZY
6130 }
6131#endif
6132
bb8c093b 6133 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY
6134
6135 if (!conf->radio_enabled) {
6136 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6137 goto out;
b481de9c
ZY
6138 }
6139
775a6e27 6140 if (iwl_is_rfkill(priv)) {
b481de9c 6141 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY
6142 ret = -EIO;
6143 goto out;
b481de9c
ZY
6144 }
6145
bb8c093b 6146 iwl3945_set_rate(priv);
b481de9c 6147
f2c7e521
AK
6148 if (memcmp(&priv->active39_rxon,
6149 &priv->staging39_rxon, sizeof(priv->staging39_rxon)))
bb8c093b 6150 iwl3945_commit_rxon(priv);
b481de9c
ZY
6151 else
6152 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6153
6154 IWL_DEBUG_MAC80211("leave\n");
6155
76bb77e0 6156out:
a0646470 6157 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6158 mutex_unlock(&priv->mutex);
76bb77e0 6159 return ret;
b481de9c
ZY
6160}
6161
4a8a4322 6162static void iwl3945_config_ap(struct iwl_priv *priv)
b481de9c
ZY
6163{
6164 int rc = 0;
6165
d986bcd1 6166 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
6167 return;
6168
6169 /* The following should be done only at AP bring up */
5d1e2325 6170 if (!(iwl3945_is_associated(priv))) {
b481de9c
ZY
6171
6172 /* RXON - unassoc (to set timing command) */
f2c7e521 6173 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6174 iwl3945_commit_rxon(priv);
b481de9c
ZY
6175
6176 /* RXON Timing */
28afaf91 6177 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
bb8c093b
CH
6178 iwl3945_setup_rxon_timing(priv);
6179 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
6180 sizeof(priv->rxon_timing), &priv->rxon_timing);
6181 if (rc)
39aadf8c 6182 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
6183 "Attempting to continue.\n");
6184
6185 /* FIXME: what should be the assoc_id for AP? */
f2c7e521 6186 priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 6187 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
f2c7e521 6188 priv->staging39_rxon.flags |=
b481de9c
ZY
6189 RXON_FLG_SHORT_PREAMBLE_MSK;
6190 else
f2c7e521 6191 priv->staging39_rxon.flags &=
b481de9c
ZY
6192 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6193
f2c7e521 6194 if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c
ZY
6195 if (priv->assoc_capability &
6196 WLAN_CAPABILITY_SHORT_SLOT_TIME)
f2c7e521 6197 priv->staging39_rxon.flags |=
b481de9c
ZY
6198 RXON_FLG_SHORT_SLOT_MSK;
6199 else
f2c7e521 6200 priv->staging39_rxon.flags &=
b481de9c
ZY
6201 ~RXON_FLG_SHORT_SLOT_MSK;
6202
05c914fe 6203 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
f2c7e521 6204 priv->staging39_rxon.flags &=
b481de9c
ZY
6205 ~RXON_FLG_SHORT_SLOT_MSK;
6206 }
6207 /* restore RXON assoc */
f2c7e521 6208 priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b 6209 iwl3945_commit_rxon(priv);
b5323d36 6210 iwl3945_add_station(priv, iwl_bcast_addr, 0, 0);
556f8db7 6211 }
bb8c093b 6212 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
6213
6214 /* FIXME - we need to add code here to detect a totally new
6215 * configuration, reset the AP, unassoc, rxon timing, assoc,
6216 * clear sta table, add BCAST sta... */
6217}
6218
32bfd35d
JB
6219static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6220 struct ieee80211_vif *vif,
4a8a4322 6221 struct ieee80211_if_conf *conf)
b481de9c 6222{
4a8a4322 6223 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6224 int rc;
6225
6226 if (conf == NULL)
6227 return -EIO;
6228
b716bb91
EG
6229 if (priv->vif != vif) {
6230 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b716bb91
EG
6231 return 0;
6232 }
6233
9d139c81 6234 /* handle this temporarily here */
05c914fe 6235 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
9d139c81
JB
6236 conf->changed & IEEE80211_IFCC_BEACON) {
6237 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
6238 if (!beacon)
6239 return -ENOMEM;
9bdf5eca 6240 mutex_lock(&priv->mutex);
9d139c81 6241 rc = iwl3945_mac_beacon_update(hw, beacon);
9bdf5eca 6242 mutex_unlock(&priv->mutex);
9d139c81
JB
6243 if (rc)
6244 return rc;
6245 }
6246
775a6e27 6247 if (!iwl_is_alive(priv))
5a66926a
ZY
6248 return -EAGAIN;
6249
b481de9c
ZY
6250 mutex_lock(&priv->mutex);
6251
b481de9c 6252 if (conf->bssid)
e174961c 6253 IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
b481de9c 6254
4150c572
JB
6255/*
6256 * very dubious code was here; the probe filtering flag is never set:
6257 *
b481de9c
ZY
6258 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6259 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6260 */
b481de9c 6261
05c914fe 6262 if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY
6263 if (!conf->bssid) {
6264 conf->bssid = priv->mac_addr;
6265 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
e174961c
JB
6266 IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
6267 conf->bssid);
b481de9c
ZY
6268 }
6269 if (priv->ibss_beacon)
6270 dev_kfree_skb(priv->ibss_beacon);
6271
9d139c81 6272 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
b481de9c
ZY
6273 }
6274
775a6e27 6275 if (iwl_is_rfkill(priv))
fde3571f
MA
6276 goto done;
6277
b481de9c
ZY
6278 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6279 !is_multicast_ether_addr(conf->bssid)) {
6280 /* If there is currently a HW scan going on in the background
6281 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6282 if (iwl3945_scan_cancel_timeout(priv, 100)) {
39aadf8c 6283 IWL_WARN(priv, "Aborted scan still in progress "
b481de9c
ZY
6284 "after 100ms\n");
6285 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6286 mutex_unlock(&priv->mutex);
6287 return -EAGAIN;
6288 }
f2c7e521 6289 memcpy(priv->staging39_rxon.bssid_addr, conf->bssid, ETH_ALEN);
b481de9c
ZY
6290
6291 /* TODO: Audit driver for usage of these members and see
6292 * if mac80211 deprecates them (priv->bssid looks like it
6293 * shouldn't be there, but I haven't scanned the IBSS code
6294 * to verify) - jpk */
6295 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6296
05c914fe 6297 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b 6298 iwl3945_config_ap(priv);
b481de9c 6299 else {
bb8c093b 6300 rc = iwl3945_commit_rxon(priv);
05c914fe 6301 if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
bb8c093b 6302 iwl3945_add_station(priv,
f2c7e521 6303 priv->active39_rxon.bssid_addr, 1, 0);
b481de9c
ZY
6304 }
6305
6306 } else {
bb8c093b 6307 iwl3945_scan_cancel_timeout(priv, 100);
f2c7e521 6308 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6309 iwl3945_commit_rxon(priv);
b481de9c
ZY
6310 }
6311
fde3571f 6312 done:
b481de9c
ZY
6313 IWL_DEBUG_MAC80211("leave\n");
6314 mutex_unlock(&priv->mutex);
6315
6316 return 0;
6317}
6318
bb8c093b 6319static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB
6320 unsigned int changed_flags,
6321 unsigned int *total_flags,
6322 int mc_count, struct dev_addr_list *mc_list)
6323{
4a8a4322 6324 struct iwl_priv *priv = hw->priv;
f2c7e521 6325 __le32 *filter_flags = &priv->staging39_rxon.filter_flags;
25b3f57c 6326
352bc8de
ZY
6327 IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
6328 changed_flags, *total_flags);
6329
6330 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
6331 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
6332 *filter_flags |= RXON_FILTER_PROMISC_MSK;
6333 else
6334 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
6335 }
6336 if (changed_flags & FIF_ALLMULTI) {
6337 if (*total_flags & FIF_ALLMULTI)
6338 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
6339 else
6340 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
6341 }
6342 if (changed_flags & FIF_CONTROL) {
6343 if (*total_flags & FIF_CONTROL)
6344 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
6345 else
6346 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
5ec03976 6347 }
352bc8de
ZY
6348 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
6349 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
6350 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
6351 else
6352 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
6353 }
6354
6355 /* We avoid iwl_commit_rxon here to commit the new filter flags
6356 * since mac80211 will call ieee80211_hw_config immediately.
6357 * (mc_list is not supported at this time). Otherwise, we need to
6358 * queue a background iwl_commit_rxon work.
6359 */
6360
6361 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
25b3f57c 6362 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4150c572
JB
6363}
6364
bb8c093b 6365static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY
6366 struct ieee80211_if_init_conf *conf)
6367{
4a8a4322 6368 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6369
6370 IWL_DEBUG_MAC80211("enter\n");
6371
6372 mutex_lock(&priv->mutex);
6ef89d0a 6373
775a6e27 6374 if (iwl_is_ready_rf(priv)) {
fde3571f 6375 iwl3945_scan_cancel_timeout(priv, 100);
f2c7e521 6376 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
fde3571f
MA
6377 iwl3945_commit_rxon(priv);
6378 }
32bfd35d
JB
6379 if (priv->vif == conf->vif) {
6380 priv->vif = NULL;
b481de9c 6381 memset(priv->bssid, 0, ETH_ALEN);
b481de9c
ZY
6382 }
6383 mutex_unlock(&priv->mutex);
6384
6385 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY
6386}
6387
cd56d331
AK
6388#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
6389
6390static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
6391 struct ieee80211_vif *vif,
6392 struct ieee80211_bss_conf *bss_conf,
6393 u32 changes)
6394{
4a8a4322 6395 struct iwl_priv *priv = hw->priv;
cd56d331
AK
6396
6397 IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
6398
6399 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
6400 IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
6401 bss_conf->use_short_preamble);
6402 if (bss_conf->use_short_preamble)
f2c7e521 6403 priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
cd56d331 6404 else
f2c7e521 6405 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
cd56d331
AK
6406 }
6407
6408 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
6409 IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
6410 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
f2c7e521 6411 priv->staging39_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
cd56d331 6412 else
f2c7e521 6413 priv->staging39_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
cd56d331
AK
6414 }
6415
6416 if (changes & BSS_CHANGED_ASSOC) {
6417 IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
6418 /* This should never happen as this function should
6419 * never be called from interrupt context. */
6420 if (WARN_ON_ONCE(in_interrupt()))
6421 return;
6422 if (bss_conf->assoc) {
6423 priv->assoc_id = bss_conf->aid;
6424 priv->beacon_int = bss_conf->beacon_int;
28afaf91 6425 priv->timestamp = bss_conf->timestamp;
cd56d331
AK
6426 priv->assoc_capability = bss_conf->assoc_capability;
6427 priv->next_scan_jiffies = jiffies +
6428 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
6429 mutex_lock(&priv->mutex);
6430 iwl3945_post_associate(priv);
6431 mutex_unlock(&priv->mutex);
6432 } else {
6433 priv->assoc_id = 0;
6434 IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
6435 }
6436 } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
6437 IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
6438 iwl3945_send_rxon_assoc(priv);
6439 }
6440
6441}
6442
bb8c093b 6443static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY
6444{
6445 int rc = 0;
6446 unsigned long flags;
4a8a4322 6447 struct iwl_priv *priv = hw->priv;
9387b7ca 6448 DECLARE_SSID_BUF(ssid_buf);
b481de9c
ZY
6449
6450 IWL_DEBUG_MAC80211("enter\n");
6451
15e869d8 6452 mutex_lock(&priv->mutex);
b481de9c
ZY
6453 spin_lock_irqsave(&priv->lock, flags);
6454
775a6e27 6455 if (!iwl_is_ready_rf(priv)) {
b481de9c
ZY
6456 rc = -EIO;
6457 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
6458 goto out_unlock;
6459 }
6460
7878a5a4
MA
6461 /* we don't schedule scan within next_scan_jiffies period */
6462 if (priv->next_scan_jiffies &&
6463 time_after(priv->next_scan_jiffies, jiffies)) {
6464 rc = -EAGAIN;
6465 goto out_unlock;
6466 }
15dbf1b7
BM
6467 /* if we just finished scan ask for delay for a broadcast scan */
6468 if ((len == 0) && priv->last_scan_jiffies &&
6469 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
6470 jiffies)) {
b481de9c
ZY
6471 rc = -EAGAIN;
6472 goto out_unlock;
6473 }
6474 if (len) {
7878a5a4 6475 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
9387b7ca 6476 print_ssid(ssid_buf, ssid, len), (int)len);
b481de9c
ZY
6477
6478 priv->one_direct_scan = 1;
6479 priv->direct_ssid_len = (u8)
6480 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
6481 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA
6482 } else
6483 priv->one_direct_scan = 0;
b481de9c 6484
bb8c093b 6485 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY
6486
6487 IWL_DEBUG_MAC80211("leave\n");
6488
6489out_unlock:
6490 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 6491 mutex_unlock(&priv->mutex);
b481de9c
ZY
6492
6493 return rc;
6494}
6495
bb8c093b 6496static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
6497 struct ieee80211_vif *vif,
6498 struct ieee80211_sta *sta,
6499 struct ieee80211_key_conf *key)
b481de9c 6500{
4a8a4322 6501 struct iwl_priv *priv = hw->priv;
dc822b5d 6502 const u8 *addr;
b481de9c
ZY
6503 int rc = 0;
6504 u8 sta_id;
dc822b5d
JB
6505 static const u8 bcast_addr[ETH_ALEN] =
6506 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
b481de9c
ZY
6507
6508 IWL_DEBUG_MAC80211("enter\n");
6509
df878d8f 6510 if (iwl3945_mod_params.sw_crypto) {
b481de9c
ZY
6511 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
6512 return -EOPNOTSUPP;
6513 }
6514
dc822b5d 6515 addr = sta ? sta->addr : bcast_addr;
b481de9c 6516
bb8c093b 6517 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 6518 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB
6519 IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
6520 addr);
b481de9c
ZY
6521 return -EINVAL;
6522 }
6523
6524 mutex_lock(&priv->mutex);
6525
bb8c093b 6526 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 6527
b481de9c
ZY
6528 switch (cmd) {
6529 case SET_KEY:
bb8c093b 6530 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 6531 if (!rc) {
bb8c093b
CH
6532 iwl3945_set_rxon_hwcrypto(priv, 1);
6533 iwl3945_commit_rxon(priv);
b481de9c
ZY
6534 key->hw_key_idx = sta_id;
6535 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
6536 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
6537 }
6538 break;
6539 case DISABLE_KEY:
bb8c093b 6540 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 6541 if (!rc) {
bb8c093b
CH
6542 iwl3945_set_rxon_hwcrypto(priv, 0);
6543 iwl3945_commit_rxon(priv);
b481de9c
ZY
6544 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
6545 }
6546 break;
6547 default:
6548 rc = -EINVAL;
6549 }
6550
6551 IWL_DEBUG_MAC80211("leave\n");
6552 mutex_unlock(&priv->mutex);
6553
6554 return rc;
6555}
6556
e100bb64 6557static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
b481de9c
ZY
6558 const struct ieee80211_tx_queue_params *params)
6559{
4a8a4322 6560 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6561 unsigned long flags;
6562 int q;
b481de9c
ZY
6563
6564 IWL_DEBUG_MAC80211("enter\n");
6565
775a6e27 6566 if (!iwl_is_ready_rf(priv)) {
b481de9c
ZY
6567 IWL_DEBUG_MAC80211("leave - RF not ready\n");
6568 return -EIO;
6569 }
6570
6571 if (queue >= AC_NUM) {
6572 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
6573 return 0;
6574 }
6575
b481de9c
ZY
6576 q = AC_NUM - 1 - queue;
6577
6578 spin_lock_irqsave(&priv->lock, flags);
6579
6580 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
6581 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
6582 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
6583 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 6584 cpu_to_le16((params->txop * 32));
b481de9c
ZY
6585
6586 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
6587 priv->qos_data.qos_active = 1;
6588
6589 spin_unlock_irqrestore(&priv->lock, flags);
6590
6591 mutex_lock(&priv->mutex);
05c914fe 6592 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b
CH
6593 iwl3945_activate_qos(priv, 1);
6594 else if (priv->assoc_id && iwl3945_is_associated(priv))
6595 iwl3945_activate_qos(priv, 0);
b481de9c
ZY
6596
6597 mutex_unlock(&priv->mutex);
6598
b481de9c
ZY
6599 IWL_DEBUG_MAC80211("leave\n");
6600 return 0;
6601}
6602
bb8c093b 6603static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY
6604 struct ieee80211_tx_queue_stats *stats)
6605{
4a8a4322 6606 struct iwl_priv *priv = hw->priv;
b481de9c 6607 int i, avail;
188cf6c7 6608 struct iwl_tx_queue *txq;
d20b3c65 6609 struct iwl_queue *q;
b481de9c
ZY
6610 unsigned long flags;
6611
6612 IWL_DEBUG_MAC80211("enter\n");
6613
775a6e27 6614 if (!iwl_is_ready_rf(priv)) {
b481de9c
ZY
6615 IWL_DEBUG_MAC80211("leave - RF not ready\n");
6616 return -EIO;
6617 }
6618
6619 spin_lock_irqsave(&priv->lock, flags);
6620
6621 for (i = 0; i < AC_NUM; i++) {
188cf6c7 6622 txq = &priv->txq[i];
b481de9c 6623 q = &txq->q;
d20b3c65 6624 avail = iwl_queue_space(q);
b481de9c 6625
57ffc589
JB
6626 stats[i].len = q->n_window - avail;
6627 stats[i].limit = q->n_window - q->high_mark;
6628 stats[i].count = q->n_window;
b481de9c
ZY
6629
6630 }
6631 spin_unlock_irqrestore(&priv->lock, flags);
6632
6633 IWL_DEBUG_MAC80211("leave\n");
6634
6635 return 0;
6636}
6637
bb8c093b 6638static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 6639{
4a8a4322 6640 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6641 unsigned long flags;
6642
6643 mutex_lock(&priv->mutex);
6644 IWL_DEBUG_MAC80211("enter\n");
6645
775a6e27 6646 iwl_reset_qos(priv);
292ae174 6647
b481de9c
ZY
6648 spin_lock_irqsave(&priv->lock, flags);
6649 priv->assoc_id = 0;
6650 priv->assoc_capability = 0;
6651 priv->call_post_assoc_from_beacon = 0;
6652
6653 /* new association get rid of ibss beacon skb */
6654 if (priv->ibss_beacon)
6655 dev_kfree_skb(priv->ibss_beacon);
6656
6657 priv->ibss_beacon = NULL;
6658
6659 priv->beacon_int = priv->hw->conf.beacon_int;
28afaf91 6660 priv->timestamp = 0;
05c914fe 6661 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
b481de9c
ZY
6662 priv->beacon_int = 0;
6663
6664 spin_unlock_irqrestore(&priv->lock, flags);
6665
775a6e27 6666 if (!iwl_is_ready_rf(priv)) {
fde3571f
MA
6667 IWL_DEBUG_MAC80211("leave - not ready\n");
6668 mutex_unlock(&priv->mutex);
6669 return;
6670 }
6671
15e869d8
MA
6672 /* we are restarting association process
6673 * clear RXON_FILTER_ASSOC_MSK bit
6674 */
05c914fe 6675 if (priv->iw_mode != NL80211_IFTYPE_AP) {
bb8c093b 6676 iwl3945_scan_cancel_timeout(priv, 100);
f2c7e521 6677 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6678 iwl3945_commit_rxon(priv);
15e869d8
MA
6679 }
6680
b481de9c 6681 /* Per mac80211.h: This is only used in IBSS mode... */
05c914fe 6682 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
15e869d8 6683
b481de9c
ZY
6684 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
6685 mutex_unlock(&priv->mutex);
6686 return;
b481de9c
ZY
6687 }
6688
bb8c093b 6689 iwl3945_set_rate(priv);
b481de9c
ZY
6690
6691 mutex_unlock(&priv->mutex);
6692
6693 IWL_DEBUG_MAC80211("leave\n");
6694
6695}
6696
e039fa4a 6697static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6698{
4a8a4322 6699 struct iwl_priv *priv = hw->priv;
b481de9c
ZY
6700 unsigned long flags;
6701
b481de9c
ZY
6702 IWL_DEBUG_MAC80211("enter\n");
6703
775a6e27 6704 if (!iwl_is_ready_rf(priv)) {
b481de9c 6705 IWL_DEBUG_MAC80211("leave - RF not ready\n");
b481de9c
ZY
6706 return -EIO;
6707 }
6708
05c914fe 6709 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
b481de9c 6710 IWL_DEBUG_MAC80211("leave - not IBSS\n");
b481de9c
ZY
6711 return -EIO;
6712 }
6713
6714 spin_lock_irqsave(&priv->lock, flags);
6715
6716 if (priv->ibss_beacon)
6717 dev_kfree_skb(priv->ibss_beacon);
6718
6719 priv->ibss_beacon = skb;
6720
6721 priv->assoc_id = 0;
6722
6723 IWL_DEBUG_MAC80211("leave\n");
6724 spin_unlock_irqrestore(&priv->lock, flags);
6725
775a6e27 6726 iwl_reset_qos(priv);
b481de9c 6727
dc4b1e7d 6728 iwl3945_post_associate(priv);
b481de9c 6729
b481de9c
ZY
6730
6731 return 0;
6732}
6733
6734/*****************************************************************************
6735 *
6736 * sysfs attributes
6737 *
6738 *****************************************************************************/
6739
c8b0e6e1 6740#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY
6741
6742/*
6743 * The following adds a new attribute to the sysfs representation
6744 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
6745 * used for controlling the debug level.
6746 *
6747 * See the level definitions in iwl for details.
6748 */
40b8ec0b
SO
6749static ssize_t show_debug_level(struct device *d,
6750 struct device_attribute *attr, char *buf)
b481de9c 6751{
4a8a4322 6752 struct iwl_priv *priv = d->driver_data;
40b8ec0b
SO
6753
6754 return sprintf(buf, "0x%08X\n", priv->debug_level);
b481de9c 6755}
40b8ec0b
SO
6756static ssize_t store_debug_level(struct device *d,
6757 struct device_attribute *attr,
b481de9c
ZY
6758 const char *buf, size_t count)
6759{
4a8a4322 6760 struct iwl_priv *priv = d->driver_data;
40b8ec0b
SO
6761 unsigned long val;
6762 int ret;
b481de9c 6763
40b8ec0b
SO
6764 ret = strict_strtoul(buf, 0, &val);
6765 if (ret)
978785a3 6766 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
b481de9c 6767 else
40b8ec0b 6768 priv->debug_level = val;
b481de9c
ZY
6769
6770 return strnlen(buf, count);
6771}
6772
40b8ec0b
SO
6773static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
6774 show_debug_level, store_debug_level);
b481de9c 6775
c8b0e6e1 6776#endif /* CONFIG_IWL3945_DEBUG */
b481de9c 6777
b481de9c
ZY
6778static ssize_t show_temperature(struct device *d,
6779 struct device_attribute *attr, char *buf)
6780{
4a8a4322 6781 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c 6782
775a6e27 6783 if (!iwl_is_alive(priv))
b481de9c
ZY
6784 return -EAGAIN;
6785
bb8c093b 6786 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
6787}
6788
6789static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
6790
b481de9c
ZY
6791static ssize_t show_tx_power(struct device *d,
6792 struct device_attribute *attr, char *buf)
6793{
4a8a4322 6794 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY
6795 return sprintf(buf, "%d\n", priv->user_txpower_limit);
6796}
6797
6798static ssize_t store_tx_power(struct device *d,
6799 struct device_attribute *attr,
6800 const char *buf, size_t count)
6801{
4a8a4322 6802 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY
6803 char *p = (char *)buf;
6804 u32 val;
6805
6806 val = simple_strtoul(p, &p, 10);
6807 if (p == buf)
978785a3 6808 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
b481de9c 6809 else
bb8c093b 6810 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
6811
6812 return count;
6813}
6814
6815static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
6816
6817static ssize_t show_flags(struct device *d,
6818 struct device_attribute *attr, char *buf)
6819{
4a8a4322 6820 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c 6821
f2c7e521 6822 return sprintf(buf, "0x%04X\n", priv->active39_rxon.flags);
b481de9c
ZY
6823}
6824
6825static ssize_t store_flags(struct device *d,
6826 struct device_attribute *attr,
6827 const char *buf, size_t count)
6828{
4a8a4322 6829 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY
6830 u32 flags = simple_strtoul(buf, NULL, 0);
6831
6832 mutex_lock(&priv->mutex);
f2c7e521 6833 if (le32_to_cpu(priv->staging39_rxon.flags) != flags) {
b481de9c 6834 /* Cancel any currently running scans... */
bb8c093b 6835 if (iwl3945_scan_cancel_timeout(priv, 100))
39aadf8c 6836 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c
ZY
6837 else {
6838 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
6839 flags);
f2c7e521 6840 priv->staging39_rxon.flags = cpu_to_le32(flags);
bb8c093b 6841 iwl3945_commit_rxon(priv);
b481de9c
ZY
6842 }
6843 }
6844 mutex_unlock(&priv->mutex);
6845
6846 return count;
6847}
6848
6849static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
6850
6851static ssize_t show_filter_flags(struct device *d,
6852 struct device_attribute *attr, char *buf)
6853{
4a8a4322 6854 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY
6855
6856 return sprintf(buf, "0x%04X\n",
f2c7e521 6857 le32_to_cpu(priv->active39_rxon.filter_flags));
b481de9c
ZY
6858}
6859
6860static ssize_t store_filter_flags(struct device *d,
6861 struct device_attribute *attr,
6862 const char *buf, size_t count)
6863{
4a8a4322 6864 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY
6865 u32 filter_flags = simple_strtoul(buf, NULL, 0);
6866
6867 mutex_lock(&priv->mutex);
f2c7e521 6868 if (le32_to_cpu(priv->staging39_rxon.filter_flags) != filter_flags) {
b481de9c 6869 /* Cancel any currently running scans... */
bb8c093b 6870 if (iwl3945_scan_cancel_timeout(priv, 100))
39aadf8c 6871 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c
ZY
6872 else {
6873 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
6874 "0x%04X\n", filter_flags);
f2c7e521 6875 priv->staging39_rxon.filter_flags =
b481de9c 6876 cpu_to_le32(filter_flags);
bb8c093b 6877 iwl3945_commit_rxon(priv);
b481de9c
ZY
6878 }
6879 }
6880 mutex_unlock(&priv->mutex);
6881
6882 return count;
6883}
6884
6885static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
6886 store_filter_flags);
6887
c8b0e6e1 6888#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
6889
6890static ssize_t show_measurement(struct device *d,
6891 struct device_attribute *attr, char *buf)
6892{
4a8a4322 6893 struct iwl_priv *priv = dev_get_drvdata(d);
600c0e11 6894 struct iwl_spectrum_notification measure_report;
b481de9c 6895 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 6896 u8 *data = (u8 *)&measure_report;
b481de9c
ZY
6897 unsigned long flags;
6898
6899 spin_lock_irqsave(&priv->lock, flags);
6900 if (!(priv->measurement_status & MEASUREMENT_READY)) {
6901 spin_unlock_irqrestore(&priv->lock, flags);
6902 return 0;
6903 }
6904 memcpy(&measure_report, &priv->measure_report, size);
6905 priv->measurement_status = 0;
6906 spin_unlock_irqrestore(&priv->lock, flags);
6907
6908 while (size && (PAGE_SIZE - len)) {
6909 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
6910 PAGE_SIZE - len, 1);
6911 len = strlen(buf);
6912 if (PAGE_SIZE - len)
6913 buf[len++] = '\n';
6914
6915 ofs += 16;
6916 size -= min(size, 16U);
6917 }
6918
6919 return len;
6920}
6921
6922static ssize_t store_measurement(struct device *d,
6923 struct device_attribute *attr,
6924 const char *buf, size_t count)
6925{
4a8a4322 6926 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 6927 struct ieee80211_measurement_params params = {
f2c7e521 6928 .channel = le16_to_cpu(priv->active39_rxon.channel),
b481de9c
ZY
6929 .start_time = cpu_to_le64(priv->last_tsf),
6930 .duration = cpu_to_le16(1),
6931 };
6932 u8 type = IWL_MEASURE_BASIC;
6933 u8 buffer[32];
6934 u8 channel;
6935
6936 if (count) {
6937 char *p = buffer;
6938 strncpy(buffer, buf, min(sizeof(buffer), count));
6939 channel = simple_strtoul(p, NULL, 0);
6940 if (channel)
6941 params.channel = channel;
6942
6943 p = buffer;
6944 while (*p && *p != ' ')
6945 p++;
6946 if (*p)
6947 type = simple_strtoul(p + 1, NULL, 0);
6948 }
6949
6950 IWL_DEBUG_INFO("Invoking measurement of type %d on "
6951 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 6952 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
6953
6954 return count;
6955}
6956
6957static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
6958 show_measurement, store_measurement);
c8b0e6e1 6959#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 6960
b481de9c
ZY
6961static ssize_t store_retry_rate(struct device *d,
6962 struct device_attribute *attr,
6963 const char *buf, size_t count)
6964{
4a8a4322 6965 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
6966
6967 priv->retry_rate = simple_strtoul(buf, NULL, 0);
6968 if (priv->retry_rate <= 0)
6969 priv->retry_rate = 1;
6970
6971 return count;
6972}
6973
6974static ssize_t show_retry_rate(struct device *d,
6975 struct device_attribute *attr, char *buf)
6976{
4a8a4322 6977 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
6978 return sprintf(buf, "%d", priv->retry_rate);
6979}
6980
6981static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
6982 store_retry_rate);
6983
6984static ssize_t store_power_level(struct device *d,
6985 struct device_attribute *attr,
6986 const char *buf, size_t count)
6987{
4a8a4322 6988 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
6989 int rc;
6990 int mode;
6991
6992 mode = simple_strtoul(buf, NULL, 0);
6993 mutex_lock(&priv->mutex);
6994
775a6e27 6995 if (!iwl_is_ready(priv)) {
b481de9c
ZY
6996 rc = -EAGAIN;
6997 goto out;
6998 }
6999
1125eff3
SO
7000 if ((mode < 1) || (mode > IWL39_POWER_LIMIT) ||
7001 (mode == IWL39_POWER_AC))
7002 mode = IWL39_POWER_AC;
b481de9c
ZY
7003 else
7004 mode |= IWL_POWER_ENABLED;
7005
7006 if (mode != priv->power_mode) {
bb8c093b 7007 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY
7008 if (rc) {
7009 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7010 goto out;
7011 }
7012 priv->power_mode = mode;
7013 }
7014
7015 rc = count;
7016
7017 out:
7018 mutex_unlock(&priv->mutex);
7019 return rc;
7020}
7021
7022#define MAX_WX_STRING 80
7023
7024/* Values are in microsecond */
7025static const s32 timeout_duration[] = {
7026 350000,
7027 250000,
7028 75000,
7029 37000,
7030 25000,
7031};
7032static const s32 period_duration[] = {
7033 400000,
7034 700000,
7035 1000000,
7036 1000000,
7037 1000000
7038};
7039
7040static ssize_t show_power_level(struct device *d,
7041 struct device_attribute *attr, char *buf)
7042{
4a8a4322 7043 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7044 int level = IWL_POWER_LEVEL(priv->power_mode);
7045 char *p = buf;
7046
7047 p += sprintf(p, "%d ", level);
7048 switch (level) {
7049 case IWL_POWER_MODE_CAM:
1125eff3 7050 case IWL39_POWER_AC:
b481de9c
ZY
7051 p += sprintf(p, "(AC)");
7052 break;
1125eff3 7053 case IWL39_POWER_BATTERY:
b481de9c
ZY
7054 p += sprintf(p, "(BATTERY)");
7055 break;
7056 default:
7057 p += sprintf(p,
7058 "(Timeout %dms, Period %dms)",
7059 timeout_duration[level - 1] / 1000,
7060 period_duration[level - 1] / 1000);
7061 }
7062
7063 if (!(priv->power_mode & IWL_POWER_ENABLED))
7064 p += sprintf(p, " OFF\n");
7065 else
7066 p += sprintf(p, " \n");
7067
3ac7f146 7068 return p - buf + 1;
b481de9c
ZY
7069
7070}
7071
7072static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7073 store_power_level);
7074
7075static ssize_t show_channels(struct device *d,
7076 struct device_attribute *attr, char *buf)
7077{
8318d78a
JB
7078 /* all this shit doesn't belong into sysfs anyway */
7079 return 0;
b481de9c
ZY
7080}
7081
7082static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7083
7084static ssize_t show_statistics(struct device *d,
7085 struct device_attribute *attr, char *buf)
7086{
4a8a4322 7087 struct iwl_priv *priv = dev_get_drvdata(d);
bb8c093b 7088 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 7089 u32 len = 0, ofs = 0;
f2c7e521 7090 u8 *data = (u8 *)&priv->statistics_39;
b481de9c
ZY
7091 int rc = 0;
7092
775a6e27 7093 if (!iwl_is_alive(priv))
b481de9c
ZY
7094 return -EAGAIN;
7095
7096 mutex_lock(&priv->mutex);
bb8c093b 7097 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY
7098 mutex_unlock(&priv->mutex);
7099
7100 if (rc) {
7101 len = sprintf(buf,
7102 "Error sending statistics request: 0x%08X\n", rc);
7103 return len;
7104 }
7105
7106 while (size && (PAGE_SIZE - len)) {
7107 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7108 PAGE_SIZE - len, 1);
7109 len = strlen(buf);
7110 if (PAGE_SIZE - len)
7111 buf[len++] = '\n';
7112
7113 ofs += 16;
7114 size -= min(size, 16U);
7115 }
7116
7117 return len;
7118}
7119
7120static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7121
7122static ssize_t show_antenna(struct device *d,
7123 struct device_attribute *attr, char *buf)
7124{
4a8a4322 7125 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 7126
775a6e27 7127 if (!iwl_is_alive(priv))
b481de9c
ZY
7128 return -EAGAIN;
7129
7130 return sprintf(buf, "%d\n", priv->antenna);
7131}
7132
7133static ssize_t store_antenna(struct device *d,
7134 struct device_attribute *attr,
7135 const char *buf, size_t count)
7136{
7137 int ant;
4a8a4322 7138 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
7139
7140 if (count == 0)
7141 return 0;
7142
7143 if (sscanf(buf, "%1i", &ant) != 1) {
7144 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7145 return count;
7146 }
7147
7148 if ((ant >= 0) && (ant <= 2)) {
7149 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7150 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY
7151 } else
7152 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7153
7154
7155 return count;
7156}
7157
7158static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7159
7160static ssize_t show_status(struct device *d,
7161 struct device_attribute *attr, char *buf)
7162{
4a8a4322 7163 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
775a6e27 7164 if (!iwl_is_alive(priv))
b481de9c
ZY
7165 return -EAGAIN;
7166 return sprintf(buf, "0x%08x\n", (int)priv->status);
7167}
7168
7169static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7170
7171static ssize_t dump_error_log(struct device *d,
7172 struct device_attribute *attr,
7173 const char *buf, size_t count)
7174{
7175 char *p = (char *)buf;
7176
7177 if (p[0] == '1')
4a8a4322 7178 iwl3945_dump_nic_error_log((struct iwl_priv *)d->driver_data);
b481de9c
ZY
7179
7180 return strnlen(buf, count);
7181}
7182
7183static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7184
7185static ssize_t dump_event_log(struct device *d,
7186 struct device_attribute *attr,
7187 const char *buf, size_t count)
7188{
7189 char *p = (char *)buf;
7190
7191 if (p[0] == '1')
4a8a4322 7192 iwl3945_dump_nic_event_log((struct iwl_priv *)d->driver_data);
b481de9c
ZY
7193
7194 return strnlen(buf, count);
7195}
7196
7197static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7198
7199/*****************************************************************************
7200 *
a96a27f9 7201 * driver setup and tear down
b481de9c
ZY
7202 *
7203 *****************************************************************************/
7204
4a8a4322 7205static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY
7206{
7207 priv->workqueue = create_workqueue(DRV_NAME);
7208
7209 init_waitqueue_head(&priv->wait_command_queue);
7210
bb8c093b
CH
7211 INIT_WORK(&priv->up, iwl3945_bg_up);
7212 INIT_WORK(&priv->restart, iwl3945_bg_restart);
7213 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
7214 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
7215 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
7216 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7217 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7218 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH
7219 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7220 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
7221 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
2663516d 7222 INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll);
bb8c093b
CH
7223
7224 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY
7225
7226 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7227 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
7228}
7229
4a8a4322 7230static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 7231{
bb8c093b 7232 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 7233
e47eb6ad 7234 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
7235 cancel_delayed_work(&priv->scan_check);
7236 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY
7237 cancel_work_sync(&priv->beacon_update);
7238}
7239
bb8c093b 7240static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
7241 &dev_attr_antenna.attr,
7242 &dev_attr_channels.attr,
7243 &dev_attr_dump_errors.attr,
7244 &dev_attr_dump_events.attr,
7245 &dev_attr_flags.attr,
7246 &dev_attr_filter_flags.attr,
c8b0e6e1 7247#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY
7248 &dev_attr_measurement.attr,
7249#endif
7250 &dev_attr_power_level.attr,
b481de9c 7251 &dev_attr_retry_rate.attr,
b481de9c
ZY
7252 &dev_attr_statistics.attr,
7253 &dev_attr_status.attr,
7254 &dev_attr_temperature.attr,
b481de9c 7255 &dev_attr_tx_power.attr,
40b8ec0b
SO
7256#ifdef CONFIG_IWL3945_DEBUG
7257 &dev_attr_debug_level.attr,
7258#endif
b481de9c
ZY
7259 NULL
7260};
7261
bb8c093b 7262static struct attribute_group iwl3945_attribute_group = {
b481de9c 7263 .name = NULL, /* put in device directory */
bb8c093b 7264 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
7265};
7266
bb8c093b
CH
7267static struct ieee80211_ops iwl3945_hw_ops = {
7268 .tx = iwl3945_mac_tx,
7269 .start = iwl3945_mac_start,
7270 .stop = iwl3945_mac_stop,
7271 .add_interface = iwl3945_mac_add_interface,
7272 .remove_interface = iwl3945_mac_remove_interface,
7273 .config = iwl3945_mac_config,
7274 .config_interface = iwl3945_mac_config_interface,
7275 .configure_filter = iwl3945_configure_filter,
7276 .set_key = iwl3945_mac_set_key,
bb8c093b
CH
7277 .get_tx_stats = iwl3945_mac_get_tx_stats,
7278 .conf_tx = iwl3945_mac_conf_tx,
bb8c093b 7279 .reset_tsf = iwl3945_mac_reset_tsf,
cd56d331 7280 .bss_info_changed = iwl3945_bss_info_changed,
bb8c093b 7281 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY
7282};
7283
e52119c5 7284static int iwl3945_init_drv(struct iwl_priv *priv)
90a30a02
KA
7285{
7286 int ret;
7287
7288 priv->retry_rate = 1;
7289 priv->ibss_beacon = NULL;
7290
7291 spin_lock_init(&priv->lock);
c7a7c8ec 7292 spin_lock_init(&priv->power_data_39.lock);
90a30a02
KA
7293 spin_lock_init(&priv->sta_lock);
7294 spin_lock_init(&priv->hcmd_lock);
7295
7296 INIT_LIST_HEAD(&priv->free_frames);
7297
7298 mutex_init(&priv->mutex);
7299
7300 /* Clear the driver's (not device's) station table */
7301 iwl3945_clear_stations_table(priv);
7302
7303 priv->data_retry_limit = -1;
7304 priv->ieee_channels = NULL;
7305 priv->ieee_rates = NULL;
7306 priv->band = IEEE80211_BAND_2GHZ;
7307
7308 priv->iw_mode = NL80211_IFTYPE_STATION;
7309
7310 iwl_reset_qos(priv);
7311
7312 priv->qos_data.qos_active = 0;
7313 priv->qos_data.qos_cap.val = 0;
7314
7315 priv->rates_mask = IWL_RATES_MASK;
7316 /* If power management is turned on, default to AC mode */
c7a7c8ec 7317 priv->power_mode = IWL39_POWER_AC;
90a30a02
KA
7318 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
7319
7320 ret = iwl3945_init_channel_map(priv);
7321 if (ret) {
7322 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
7323 goto err;
7324 }
7325
7326 ret = iwl3945_init_geos(priv);
7327 if (ret) {
7328 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
7329 goto err_free_channel_map;
7330 }
7331
7332 return 0;
7333
7334err_free_channel_map:
7335 iwl3945_free_channel_map(priv);
7336err:
7337 return ret;
7338}
7339
bb8c093b 7340static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
7341{
7342 int err = 0;
4a8a4322 7343 struct iwl_priv *priv;
b481de9c 7344 struct ieee80211_hw *hw;
c0f20d91 7345 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 7346 unsigned long flags;
b481de9c 7347
cee53ddb
KA
7348 /***********************
7349 * 1. Allocating HW data
7350 * ********************/
7351
b481de9c
ZY
7352 /* mac80211 allocates memory for this device instance, including
7353 * space for this driver's private structure */
90a30a02 7354 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
b481de9c 7355 if (hw == NULL) {
a3139c59 7356 printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
b481de9c
ZY
7357 err = -ENOMEM;
7358 goto out;
7359 }
b481de9c 7360 priv = hw->priv;
90a30a02 7361 SET_IEEE80211_DEV(hw, &pdev->dev);
6440adb5 7362
df878d8f
KA
7363 if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) ||
7364 (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) {
15b1687c
WT
7365 IWL_ERR(priv,
7366 "invalid queues_num, should be between %d and %d\n",
7367 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
a3139c59
SO
7368 err = -EINVAL;
7369 goto out;
7370 }
7371
90a30a02
KA
7372 /*
7373 * Disabling hardware scan means that mac80211 will perform scans
7374 * "the hard way", rather than using device's scan.
7375 */
df878d8f 7376 if (iwl3945_mod_params.disable_hw_scan) {
40b8ec0b
SO
7377 IWL_DEBUG_INFO("Disabling hw_scan\n");
7378 iwl3945_hw_ops.hw_scan = NULL;
7379 }
7380
90a30a02 7381
cee53ddb 7382 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
90a30a02
KA
7383 priv->cfg = cfg;
7384 priv->pci_dev = pdev;
cee53ddb 7385
c8b0e6e1 7386#ifdef CONFIG_IWL3945_DEBUG
df878d8f 7387 priv->debug_level = iwl3945_mod_params.debug;
b481de9c
ZY
7388 atomic_set(&priv->restrict_refcnt, 0);
7389#endif
90a30a02
KA
7390 hw->rate_control_algorithm = "iwl-3945-rs";
7391 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
7392
7393 /* Select antenna (may be helpful if only one antenna is connected) */
7394 priv->antenna = (enum iwl3945_antenna)iwl3945_mod_params.antenna;
b481de9c 7395
566bfe5a 7396 /* Tell mac80211 our characteristics */
605a0bd6 7397 hw->flags = IEEE80211_HW_SIGNAL_DBM |
566bfe5a 7398 IEEE80211_HW_NOISE_DBM;
b481de9c 7399
f59ac048 7400 hw->wiphy->interface_modes =
f59ac048
LR
7401 BIT(NL80211_IFTYPE_STATION) |
7402 BIT(NL80211_IFTYPE_ADHOC);
7403
ea4a82dc
LR
7404 hw->wiphy->fw_handles_regulatory = true;
7405
6440adb5 7406 /* 4 EDCA QOS priorities */
b481de9c
ZY
7407 hw->queues = 4;
7408
cee53ddb
KA
7409 /***************************
7410 * 2. Initializing PCI bus
7411 * *************************/
b481de9c
ZY
7412 if (pci_enable_device(pdev)) {
7413 err = -ENODEV;
7414 goto out_ieee80211_free_hw;
7415 }
7416
7417 pci_set_master(pdev);
7418
b481de9c
ZY
7419 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
7420 if (!err)
7421 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
7422 if (err) {
978785a3 7423 IWL_WARN(priv, "No suitable DMA available.\n");
b481de9c
ZY
7424 goto out_pci_disable_device;
7425 }
7426
7427 pci_set_drvdata(pdev, priv);
7428 err = pci_request_regions(pdev, DRV_NAME);
7429 if (err)
7430 goto out_pci_disable_device;
6440adb5 7431
cee53ddb
KA
7432 /***********************
7433 * 3. Read REV Register
7434 * ********************/
b481de9c
ZY
7435 priv->hw_base = pci_iomap(pdev, 0, 0);
7436 if (!priv->hw_base) {
7437 err = -ENODEV;
7438 goto out_pci_release_regions;
7439 }
7440
7441 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
7442 (unsigned long long) pci_resource_len(pdev, 0));
7443 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
7444
cee53ddb
KA
7445 /* We disable the RETRY_TIMEOUT register (0x41) to keep
7446 * PCI Tx retries from interfering with C3 CPU state */
7447 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 7448
90a30a02
KA
7449 /* amp init */
7450 err = priv->cfg->ops->lib->apm_ops.init(priv);
cee53ddb 7451 if (err < 0) {
90a30a02
KA
7452 IWL_DEBUG_INFO("Failed to init APMG\n");
7453 goto out_iounmap;
cee53ddb 7454 }
b481de9c 7455
cee53ddb
KA
7456 /***********************
7457 * 4. Read EEPROM
7458 * ********************/
90a30a02 7459
cee53ddb
KA
7460 /* Read the EEPROM */
7461 err = iwl3945_eeprom_init(priv);
7462 if (err) {
15b1687c 7463 IWL_ERR(priv, "Unable to init EEPROM\n");
cee53ddb
KA
7464 goto out_remove_sysfs;
7465 }
7466 /* MAC Address location in EEPROM same for 3945/4965 */
7467 get_eeprom_mac(priv, priv->mac_addr);
7468 IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
7469 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 7470
cee53ddb
KA
7471 /***********************
7472 * 5. Setup HW Constants
7473 * ********************/
b481de9c 7474 /* Device-specific setup */
3832ec9d 7475 if (iwl3945_hw_set_hw_params(priv)) {
15b1687c 7476 IWL_ERR(priv, "failed to set hw settings\n");
b481de9c
ZY
7477 goto out_iounmap;
7478 }
7479
cee53ddb
KA
7480 /***********************
7481 * 6. Setup priv
7482 * ********************/
cee53ddb 7483
90a30a02 7484 err = iwl3945_init_drv(priv);
b481de9c 7485 if (err) {
90a30a02
KA
7486 IWL_ERR(priv, "initializing driver failed\n");
7487 goto out_free_geos;
b481de9c
ZY
7488 }
7489
978785a3
TW
7490 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
7491 priv->cfg->name);
cee53ddb
KA
7492
7493 /***********************************
7494 * 7. Initialize Module Parameters
7495 * **********************************/
7496
7497 /* Initialize module parameter values here */
7498 /* Disable radio (SW RF KILL) via parameter when loading driver */
df878d8f 7499 if (iwl3945_mod_params.disable) {
cee53ddb
KA
7500 set_bit(STATUS_RF_KILL_SW, &priv->status);
7501 IWL_DEBUG_INFO("Radio disabled.\n");
849e0dce
RC
7502 }
7503
cee53ddb
KA
7504
7505 /***********************
7506 * 8. Setup Services
7507 * ********************/
7508
7509 spin_lock_irqsave(&priv->lock, flags);
7510 iwl3945_disable_interrupts(priv);
7511 spin_unlock_irqrestore(&priv->lock, flags);
7512
2663516d
HS
7513 pci_enable_msi(priv->pci_dev);
7514
7515 err = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
7516 DRV_NAME, priv);
7517 if (err) {
7518 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
7519 goto out_disable_msi;
7520 }
7521
cee53ddb 7522 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 7523 if (err) {
15b1687c 7524 IWL_ERR(priv, "failed to create sysfs device attributes\n");
90a30a02 7525 goto out_release_irq;
849e0dce 7526 }
849e0dce 7527
cee53ddb
KA
7528 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
7529 iwl3945_setup_deferred_work(priv);
7530 iwl3945_setup_rx_handlers(priv);
7531
cee53ddb 7532 /*********************************
2663516d 7533 * 9. Setup and Register mac80211
cee53ddb
KA
7534 * *******************************/
7535
5a66926a
ZY
7536 err = ieee80211_register_hw(priv->hw);
7537 if (err) {
15b1687c 7538 IWL_ERR(priv, "Failed to register network device: %d\n", err);
cee53ddb 7539 goto out_remove_sysfs;
5a66926a 7540 }
b481de9c 7541
5a66926a
ZY
7542 priv->hw->conf.beacon_int = 100;
7543 priv->mac80211_registered = 1;
cee53ddb 7544
ebef2008
AK
7545 err = iwl3945_rfkill_init(priv);
7546 if (err)
15b1687c 7547 IWL_ERR(priv, "Unable to initialize RFKILL system. "
ebef2008
AK
7548 "Ignoring error: %d\n", err);
7549
2663516d
HS
7550 /* Start monitoring the killswitch */
7551 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
7552 2 * HZ);
7553
b481de9c
ZY
7554 return 0;
7555
cee53ddb
KA
7556 out_remove_sysfs:
7557 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce
RC
7558 out_free_geos:
7559 iwl3945_free_geos(priv);
b481de9c
ZY
7560
7561 out_release_irq:
2663516d 7562 free_irq(priv->pci_dev->irq, priv);
b481de9c
ZY
7563 destroy_workqueue(priv->workqueue);
7564 priv->workqueue = NULL;
3832ec9d 7565 iwl3945_unset_hw_params(priv);
2663516d
HS
7566 out_disable_msi:
7567 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
7568 out_iounmap:
7569 pci_iounmap(pdev, priv->hw_base);
7570 out_pci_release_regions:
7571 pci_release_regions(pdev);
7572 out_pci_disable_device:
7573 pci_disable_device(pdev);
7574 pci_set_drvdata(pdev, NULL);
7575 out_ieee80211_free_hw:
7576 ieee80211_free_hw(priv->hw);
7577 out:
7578 return err;
7579}
7580
c83dbf68 7581static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 7582{
4a8a4322 7583 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 7584 unsigned long flags;
b481de9c
ZY
7585
7586 if (!priv)
7587 return;
7588
7589 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
7590
b481de9c 7591 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 7592
d552bfb6
KA
7593 if (priv->mac80211_registered) {
7594 ieee80211_unregister_hw(priv->hw);
7595 priv->mac80211_registered = 0;
7596 } else {
7597 iwl3945_down(priv);
7598 }
b481de9c 7599
0359facc
MA
7600 /* make sure we flush any pending irq or
7601 * tasklet for the driver
7602 */
7603 spin_lock_irqsave(&priv->lock, flags);
7604 iwl3945_disable_interrupts(priv);
7605 spin_unlock_irqrestore(&priv->lock, flags);
7606
7607 iwl_synchronize_irq(priv);
7608
bb8c093b 7609 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 7610
ebef2008 7611 iwl3945_rfkill_unregister(priv);
2663516d
HS
7612 cancel_delayed_work(&priv->rfkill_poll);
7613
bb8c093b 7614 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
7615
7616 if (priv->rxq.bd)
51af3d3f 7617 iwl_rx_queue_free(priv, &priv->rxq);
bb8c093b 7618 iwl3945_hw_txq_ctx_free(priv);
b481de9c 7619
3832ec9d 7620 iwl3945_unset_hw_params(priv);
bb8c093b 7621 iwl3945_clear_stations_table(priv);
b481de9c 7622
6ef89d0a
MA
7623 /*netif_stop_queue(dev); */
7624 flush_workqueue(priv->workqueue);
7625
bb8c093b 7626 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
7627 * priv->workqueue... so we can't take down the workqueue
7628 * until now... */
7629 destroy_workqueue(priv->workqueue);
7630 priv->workqueue = NULL;
7631
2663516d
HS
7632 free_irq(pdev->irq, priv);
7633 pci_disable_msi(pdev);
7634
b481de9c
ZY
7635 pci_iounmap(pdev, priv->hw_base);
7636 pci_release_regions(pdev);
7637 pci_disable_device(pdev);
7638 pci_set_drvdata(pdev, NULL);
7639
849e0dce
RC
7640 iwl3945_free_channel_map(priv);
7641 iwl3945_free_geos(priv);
f2c7e521 7642 kfree(priv->scan39);
b481de9c
ZY
7643 if (priv->ibss_beacon)
7644 dev_kfree_skb(priv->ibss_beacon);
7645
7646 ieee80211_free_hw(priv->hw);
7647}
7648
7649#ifdef CONFIG_PM
7650
bb8c093b 7651static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 7652{
4a8a4322 7653 struct iwl_priv *priv = pci_get_drvdata(pdev);
b481de9c 7654
e655b9f0
ZY
7655 if (priv->is_open) {
7656 set_bit(STATUS_IN_SUSPEND, &priv->status);
7657 iwl3945_mac_stop(priv->hw);
7658 priv->is_open = 1;
7659 }
2663516d
HS
7660 pci_save_state(pdev);
7661 pci_disable_device(pdev);
b481de9c
ZY
7662 pci_set_power_state(pdev, PCI_D3hot);
7663
b481de9c
ZY
7664 return 0;
7665}
7666
bb8c093b 7667static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 7668{
4a8a4322 7669 struct iwl_priv *priv = pci_get_drvdata(pdev);
b481de9c 7670
b481de9c 7671 pci_set_power_state(pdev, PCI_D0);
2663516d
HS
7672 pci_enable_device(pdev);
7673 pci_restore_state(pdev);
b481de9c 7674
e655b9f0
ZY
7675 if (priv->is_open)
7676 iwl3945_mac_start(priv->hw);
b481de9c 7677
e655b9f0 7678 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY
7679 return 0;
7680}
7681
7682#endif /* CONFIG_PM */
7683
ebef2008 7684/*************** RFKILL FUNCTIONS **********/
80fcc9e2 7685#ifdef CONFIG_IWL3945_RFKILL
ebef2008
AK
7686/* software rf-kill from user */
7687static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
7688{
4a8a4322 7689 struct iwl_priv *priv = data;
ebef2008
AK
7690 int err = 0;
7691
80fcc9e2 7692 if (!priv->rfkill)
ebef2008
AK
7693 return 0;
7694
7695 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
7696 return 0;
7697
a96a27f9 7698 IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
ebef2008
AK
7699 mutex_lock(&priv->mutex);
7700
7701 switch (state) {
acdfe9b4 7702 case RFKILL_STATE_UNBLOCKED:
775a6e27 7703 if (iwl_is_rfkill_hw(priv)) {
ebef2008 7704 err = -EBUSY;
80fcc9e2
AG
7705 goto out_unlock;
7706 }
7707 iwl3945_radio_kill_sw(priv, 0);
ebef2008 7708 break;
acdfe9b4 7709 case RFKILL_STATE_SOFT_BLOCKED:
ebef2008 7710 iwl3945_radio_kill_sw(priv, 1);
ebef2008 7711 break;
acdfe9b4 7712 default:
39aadf8c 7713 IWL_WARN(priv, "received unexpected RFKILL state %d\n", state);
acdfe9b4 7714 break;
ebef2008 7715 }
80fcc9e2 7716out_unlock:
ebef2008
AK
7717 mutex_unlock(&priv->mutex);
7718
7719 return err;
7720}
7721
4a8a4322 7722int iwl3945_rfkill_init(struct iwl_priv *priv)
ebef2008
AK
7723{
7724 struct device *device = wiphy_dev(priv->hw->wiphy);
7725 int ret = 0;
7726
7727 BUG_ON(device == NULL);
7728
7729 IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
80fcc9e2
AG
7730 priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
7731 if (!priv->rfkill) {
15b1687c 7732 IWL_ERR(priv, "Unable to allocate rfkill device.\n");
ebef2008
AK
7733 ret = -ENOMEM;
7734 goto error;
7735 }
7736
80fcc9e2
AG
7737 priv->rfkill->name = priv->cfg->name;
7738 priv->rfkill->data = priv;
7739 priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
7740 priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
7741 priv->rfkill->user_claim_unsupported = 1;
ebef2008 7742
80fcc9e2
AG
7743 priv->rfkill->dev.class->suspend = NULL;
7744 priv->rfkill->dev.class->resume = NULL;
ebef2008 7745
80fcc9e2 7746 ret = rfkill_register(priv->rfkill);
ebef2008 7747 if (ret) {
15b1687c 7748 IWL_ERR(priv, "Unable to register rfkill: %d\n", ret);
80fcc9e2 7749 goto freed_rfkill;
ebef2008
AK
7750 }
7751
7752 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
7753 return ret;
7754
ebef2008 7755freed_rfkill:
80fcc9e2
AG
7756 if (priv->rfkill != NULL)
7757 rfkill_free(priv->rfkill);
7758 priv->rfkill = NULL;
ebef2008
AK
7759
7760error:
7761 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
7762 return ret;
7763}
7764
4a8a4322 7765void iwl3945_rfkill_unregister(struct iwl_priv *priv)
ebef2008 7766{
80fcc9e2
AG
7767 if (priv->rfkill)
7768 rfkill_unregister(priv->rfkill);
ebef2008 7769
80fcc9e2 7770 priv->rfkill = NULL;
ebef2008
AK
7771}
7772
7773/* set rf-kill to the right state. */
4a8a4322 7774void iwl3945_rfkill_set_hw_state(struct iwl_priv *priv)
ebef2008
AK
7775{
7776
80fcc9e2
AG
7777 if (!priv->rfkill)
7778 return;
7779
775a6e27 7780 if (iwl_is_rfkill_hw(priv)) {
80fcc9e2 7781 rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
ebef2008 7782 return;
80fcc9e2 7783 }
ebef2008 7784
775a6e27 7785 if (!iwl_is_rfkill_sw(priv))
80fcc9e2 7786 rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
ebef2008 7787 else
80fcc9e2 7788 rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
ebef2008
AK
7789}
7790#endif
7791
b481de9c
ZY
7792/*****************************************************************************
7793 *
7794 * driver and module entry point
7795 *
7796 *****************************************************************************/
7797
bb8c093b 7798static struct pci_driver iwl3945_driver = {
b481de9c 7799 .name = DRV_NAME,
bb8c093b
CH
7800 .id_table = iwl3945_hw_card_ids,
7801 .probe = iwl3945_pci_probe,
7802 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 7803#ifdef CONFIG_PM
bb8c093b
CH
7804 .suspend = iwl3945_pci_suspend,
7805 .resume = iwl3945_pci_resume,
b481de9c
ZY
7806#endif
7807};
7808
bb8c093b 7809static int __init iwl3945_init(void)
b481de9c
ZY
7810{
7811
7812 int ret;
7813 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
7814 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC
7815
7816 ret = iwl3945_rate_control_register();
7817 if (ret) {
a3139c59
SO
7818 printk(KERN_ERR DRV_NAME
7819 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
7820 return ret;
7821 }
7822
bb8c093b 7823 ret = pci_register_driver(&iwl3945_driver);
b481de9c 7824 if (ret) {
a3139c59 7825 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 7826 goto error_register;
b481de9c 7827 }
b481de9c
ZY
7828
7829 return ret;
897e1cf2 7830
897e1cf2
RC
7831error_register:
7832 iwl3945_rate_control_unregister();
7833 return ret;
b481de9c
ZY
7834}
7835
bb8c093b 7836static void __exit iwl3945_exit(void)
b481de9c 7837{
bb8c093b 7838 pci_unregister_driver(&iwl3945_driver);
897e1cf2 7839 iwl3945_rate_control_unregister();
b481de9c
ZY
7840}
7841
a0987a8d 7842MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 7843
df878d8f 7844module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
b481de9c 7845MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
df878d8f 7846module_param_named(disable, iwl3945_mod_params.disable, int, 0444);
b481de9c 7847MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
9c74d9fb
SO
7848module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
7849MODULE_PARM_DESC(swcrypto,
7850 "using software crypto (default 1 [software])\n");
df878d8f 7851module_param_named(debug, iwl3945_mod_params.debug, uint, 0444);
b481de9c 7852MODULE_PARM_DESC(debug, "debug output mask");
df878d8f 7853module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
b481de9c
ZY
7854MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
7855
df878d8f 7856module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444);
b481de9c
ZY
7857MODULE_PARM_DESC(queues_num, "number of hw queues.");
7858
bb8c093b
CH
7859module_exit(iwl3945_exit);
7860module_init(iwl3945_init);
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