Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/wireless.h> | |
39 | #include <linux/firmware.h> | |
b481de9c ZY |
40 | #include <linux/etherdevice.h> |
41 | #include <linux/if_arp.h> | |
42 | ||
43 | #include <net/ieee80211_radiotap.h> | |
7e272fcf | 44 | #include <net/lib80211.h> |
b481de9c ZY |
45 | #include <net/mac80211.h> |
46 | ||
47 | #include <asm/div64.h> | |
48 | ||
a3139c59 SO |
49 | #define DRV_NAME "iwl3945" |
50 | ||
dbb6654c WT |
51 | #include "iwl-fh.h" |
52 | #include "iwl-3945-fh.h" | |
600c0e11 | 53 | #include "iwl-commands.h" |
17f841cd | 54 | #include "iwl-sta.h" |
b481de9c ZY |
55 | #include "iwl-3945.h" |
56 | #include "iwl-helpers.h" | |
5747d47f | 57 | #include "iwl-core.h" |
d20b3c65 | 58 | #include "iwl-dev.h" |
b481de9c | 59 | |
b481de9c ZY |
60 | /* |
61 | * module name, copyright, version, etc. | |
b481de9c ZY |
62 | */ |
63 | ||
64 | #define DRV_DESCRIPTION \ | |
65 | "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux" | |
66 | ||
d08853a3 | 67 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
68 | #define VD "d" |
69 | #else | |
70 | #define VD | |
71 | #endif | |
72 | ||
c8b0e6e1 | 73 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
74 | #define VS "s" |
75 | #else | |
76 | #define VS | |
77 | #endif | |
78 | ||
eaa686c3 | 79 | #define IWL39_VERSION "1.2.26k" VD VS |
01f8162a | 80 | #define DRV_COPYRIGHT "Copyright(c) 2003-2009 Intel Corporation" |
a7b75207 | 81 | #define DRV_AUTHOR "<ilw@linux.intel.com>" |
eaa686c3 | 82 | #define DRV_VERSION IWL39_VERSION |
b481de9c | 83 | |
b481de9c ZY |
84 | |
85 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
86 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 87 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c ZY |
88 | MODULE_LICENSE("GPL"); |
89 | ||
df878d8f KA |
90 | /* module parameters */ |
91 | struct iwl_mod_params iwl3945_mod_params = { | |
92 | .num_of_queues = IWL39_MAX_NUM_QUEUES, | |
9c74d9fb | 93 | .sw_crypto = 1, |
af48d048 | 94 | .restart_fw = 1, |
df878d8f KA |
95 | /* the rest are 0 by default */ |
96 | }; | |
97 | ||
b481de9c | 98 | /*************** STATION TABLE MANAGEMENT **** |
9fbab516 | 99 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
100 | * the functionality provided here |
101 | */ | |
102 | ||
103 | /**************************************************************/ | |
01ebd063 | 104 | #if 0 /* temporary disable till we add real remove station */ |
6440adb5 CB |
105 | /** |
106 | * iwl3945_remove_station - Remove driver's knowledge of station. | |
107 | * | |
108 | * NOTE: This does not remove station from device's station table. | |
109 | */ | |
4a8a4322 | 110 | static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap) |
b481de9c ZY |
111 | { |
112 | int index = IWL_INVALID_STATION; | |
113 | int i; | |
114 | unsigned long flags; | |
115 | ||
116 | spin_lock_irqsave(&priv->sta_lock, flags); | |
117 | ||
118 | if (is_ap) | |
119 | index = IWL_AP_ID; | |
120 | else if (is_broadcast_ether_addr(addr)) | |
3832ec9d | 121 | index = priv->hw_params.bcast_sta_id; |
b481de9c | 122 | else |
3832ec9d | 123 | for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) |
f2c7e521 AK |
124 | if (priv->stations_39[i].used && |
125 | !compare_ether_addr(priv->stations_39[i].sta.sta.addr, | |
b481de9c ZY |
126 | addr)) { |
127 | index = i; | |
128 | break; | |
129 | } | |
130 | ||
131 | if (unlikely(index == IWL_INVALID_STATION)) | |
132 | goto out; | |
133 | ||
f2c7e521 AK |
134 | if (priv->stations_39[index].used) { |
135 | priv->stations_39[index].used = 0; | |
b481de9c ZY |
136 | priv->num_stations--; |
137 | } | |
138 | ||
139 | BUG_ON(priv->num_stations < 0); | |
140 | ||
141 | out: | |
142 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
143 | return 0; | |
144 | } | |
556f8db7 | 145 | #endif |
6440adb5 CB |
146 | |
147 | /** | |
148 | * iwl3945_clear_stations_table - Clear the driver's station table | |
149 | * | |
150 | * NOTE: This does not clear or otherwise alter the device's station table. | |
151 | */ | |
e0158e61 | 152 | void iwl3945_clear_stations_table(struct iwl_priv *priv) |
b481de9c ZY |
153 | { |
154 | unsigned long flags; | |
155 | ||
156 | spin_lock_irqsave(&priv->sta_lock, flags); | |
157 | ||
158 | priv->num_stations = 0; | |
f2c7e521 | 159 | memset(priv->stations_39, 0, sizeof(priv->stations_39)); |
b481de9c ZY |
160 | |
161 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
162 | } | |
163 | ||
6440adb5 CB |
164 | /** |
165 | * iwl3945_add_station - Add station to station tables in driver and device | |
166 | */ | |
06fd3d86 | 167 | u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags, struct ieee80211_sta_ht_cap *ht_info) |
b481de9c ZY |
168 | { |
169 | int i; | |
170 | int index = IWL_INVALID_STATION; | |
bb8c093b | 171 | struct iwl3945_station_entry *station; |
b481de9c | 172 | unsigned long flags_spin; |
c14c521e | 173 | u8 rate; |
b481de9c ZY |
174 | |
175 | spin_lock_irqsave(&priv->sta_lock, flags_spin); | |
176 | if (is_ap) | |
177 | index = IWL_AP_ID; | |
178 | else if (is_broadcast_ether_addr(addr)) | |
3832ec9d | 179 | index = priv->hw_params.bcast_sta_id; |
b481de9c | 180 | else |
3832ec9d | 181 | for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) { |
f2c7e521 | 182 | if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr, |
b481de9c ZY |
183 | addr)) { |
184 | index = i; | |
185 | break; | |
186 | } | |
187 | ||
f2c7e521 | 188 | if (!priv->stations_39[i].used && |
b481de9c ZY |
189 | index == IWL_INVALID_STATION) |
190 | index = i; | |
191 | } | |
192 | ||
01ebd063 | 193 | /* These two conditions has the same outcome but keep them separate |
b481de9c ZY |
194 | since they have different meaning */ |
195 | if (unlikely(index == IWL_INVALID_STATION)) { | |
196 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
197 | return index; | |
198 | } | |
199 | ||
f2c7e521 AK |
200 | if (priv->stations_39[index].used && |
201 | !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) { | |
b481de9c ZY |
202 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); |
203 | return index; | |
204 | } | |
205 | ||
e1623446 | 206 | IWL_DEBUG_ASSOC(priv, "Add STA ID %d: %pM\n", index, addr); |
f2c7e521 | 207 | station = &priv->stations_39[index]; |
b481de9c ZY |
208 | station->used = 1; |
209 | priv->num_stations++; | |
210 | ||
6440adb5 | 211 | /* Set up the REPLY_ADD_STA command to send to device */ |
bb8c093b | 212 | memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd)); |
b481de9c ZY |
213 | memcpy(station->sta.sta.addr, addr, ETH_ALEN); |
214 | station->sta.mode = 0; | |
215 | station->sta.sta.sta_id = index; | |
216 | station->sta.station_flags = 0; | |
217 | ||
8318d78a | 218 | if (priv->band == IEEE80211_BAND_5GHZ) |
69946333 TW |
219 | rate = IWL_RATE_6M_PLCP; |
220 | else | |
221 | rate = IWL_RATE_1M_PLCP; | |
c14c521e ZY |
222 | |
223 | /* Turn on both antennas for the station... */ | |
224 | station->sta.rate_n_flags = | |
bb8c093b | 225 | iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK); |
c14c521e | 226 | |
b481de9c | 227 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); |
6440adb5 CB |
228 | |
229 | /* Add station to device's station table */ | |
17f841cd SO |
230 | iwl_send_add_sta(priv, |
231 | (struct iwl_addsta_cmd *)&station->sta, flags); | |
b481de9c ZY |
232 | return index; |
233 | ||
234 | } | |
235 | ||
7e4bca5e SO |
236 | /** |
237 | * iwl3945_get_antenna_flags - Get antenna flags for RXON command | |
238 | * @priv: eeprom and antenna fields are used to determine antenna flags | |
239 | * | |
240 | * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed | |
241 | * iwl3945_mod_params.antenna specifies the antenna diversity mode: | |
242 | * | |
243 | * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself | |
244 | * IWL_ANTENNA_MAIN - Force MAIN antenna | |
245 | * IWL_ANTENNA_AUX - Force AUX antenna | |
246 | */ | |
247 | __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv) | |
248 | { | |
249 | struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; | |
250 | ||
251 | switch (iwl3945_mod_params.antenna) { | |
252 | case IWL_ANTENNA_DIVERSITY: | |
253 | return 0; | |
254 | ||
255 | case IWL_ANTENNA_MAIN: | |
256 | if (eeprom->antenna_switch_type) | |
257 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
258 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
259 | ||
260 | case IWL_ANTENNA_AUX: | |
261 | if (eeprom->antenna_switch_type) | |
262 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
263 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
264 | } | |
265 | ||
266 | /* bad antenna selector value */ | |
267 | IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", | |
268 | iwl3945_mod_params.antenna); | |
269 | ||
270 | return 0; /* "diversity" is default if error */ | |
271 | } | |
272 | ||
6e21f15c | 273 | static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv, |
b481de9c ZY |
274 | struct ieee80211_key_conf *keyconf, |
275 | u8 sta_id) | |
276 | { | |
277 | unsigned long flags; | |
278 | __le16 key_flags = 0; | |
6e21f15c AK |
279 | int ret; |
280 | ||
281 | key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK); | |
282 | key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
283 | ||
284 | if (sta_id == priv->hw_params.bcast_sta_id) | |
285 | key_flags |= STA_KEY_MULTICAST_MSK; | |
286 | ||
287 | keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
288 | keyconf->hw_key_idx = keyconf->keyidx; | |
289 | key_flags &= ~STA_KEY_FLG_INVALID; | |
b481de9c | 290 | |
b481de9c | 291 | spin_lock_irqsave(&priv->sta_lock, flags); |
f2c7e521 AK |
292 | priv->stations_39[sta_id].keyinfo.alg = keyconf->alg; |
293 | priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen; | |
294 | memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key, | |
b481de9c ZY |
295 | keyconf->keylen); |
296 | ||
f2c7e521 | 297 | memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key, |
b481de9c | 298 | keyconf->keylen); |
6e21f15c | 299 | |
43da9192 | 300 | if ((priv->stations_39[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK) |
6e21f15c | 301 | == STA_KEY_FLG_NO_ENC) |
43da9192 | 302 | priv->stations_39[sta_id].sta.key.key_offset = |
6e21f15c AK |
303 | iwl_get_free_ucode_key_index(priv); |
304 | /* else, we are overriding an existing key => no need to allocated room | |
305 | * in uCode. */ | |
306 | ||
43da9192 | 307 | WARN(priv->stations_39[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, |
6e21f15c AK |
308 | "no space for a new key"); |
309 | ||
f2c7e521 AK |
310 | priv->stations_39[sta_id].sta.key.key_flags = key_flags; |
311 | priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
312 | priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c | 313 | |
6e21f15c AK |
314 | IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n"); |
315 | ||
316 | ret = iwl_send_add_sta(priv, | |
317 | (struct iwl_addsta_cmd *)&priv->stations_39[sta_id].sta, CMD_ASYNC); | |
318 | ||
b481de9c ZY |
319 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
320 | ||
6e21f15c AK |
321 | return ret; |
322 | } | |
323 | ||
324 | static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv, | |
325 | struct ieee80211_key_conf *keyconf, | |
326 | u8 sta_id) | |
327 | { | |
328 | return -EOPNOTSUPP; | |
329 | } | |
330 | ||
331 | static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv, | |
332 | struct ieee80211_key_conf *keyconf, | |
333 | u8 sta_id) | |
334 | { | |
335 | return -EOPNOTSUPP; | |
b481de9c ZY |
336 | } |
337 | ||
4a8a4322 | 338 | static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id) |
b481de9c ZY |
339 | { |
340 | unsigned long flags; | |
341 | ||
342 | spin_lock_irqsave(&priv->sta_lock, flags); | |
f2c7e521 AK |
343 | memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key)); |
344 | memset(&priv->stations_39[sta_id].sta.key, 0, | |
4c897253 | 345 | sizeof(struct iwl4965_keyinfo)); |
f2c7e521 AK |
346 | priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC; |
347 | priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
348 | priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c ZY |
349 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
350 | ||
e1623446 | 351 | IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n"); |
17f841cd SO |
352 | iwl_send_add_sta(priv, |
353 | (struct iwl_addsta_cmd *)&priv->stations_39[sta_id].sta, 0); | |
b481de9c ZY |
354 | return 0; |
355 | } | |
356 | ||
fa11d525 | 357 | static int iwl3945_set_dynamic_key(struct iwl_priv *priv, |
6e21f15c AK |
358 | struct ieee80211_key_conf *keyconf, u8 sta_id) |
359 | { | |
360 | int ret = 0; | |
361 | ||
362 | keyconf->hw_key_idx = HW_KEY_DYNAMIC; | |
363 | ||
364 | switch (keyconf->alg) { | |
365 | case ALG_CCMP: | |
366 | ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id); | |
367 | break; | |
368 | case ALG_TKIP: | |
369 | ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id); | |
370 | break; | |
371 | case ALG_WEP: | |
372 | ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id); | |
373 | break; | |
374 | default: | |
1e680233 | 375 | IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg); |
6e21f15c AK |
376 | ret = -EINVAL; |
377 | } | |
378 | ||
379 | IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n", | |
380 | keyconf->alg, keyconf->keylen, keyconf->keyidx, | |
381 | sta_id, ret); | |
382 | ||
383 | return ret; | |
384 | } | |
385 | ||
386 | static int iwl3945_remove_static_key(struct iwl_priv *priv) | |
387 | { | |
388 | int ret = -EOPNOTSUPP; | |
389 | ||
390 | return ret; | |
391 | } | |
392 | ||
393 | static int iwl3945_set_static_key(struct iwl_priv *priv, | |
394 | struct ieee80211_key_conf *key) | |
395 | { | |
396 | if (key->alg == ALG_WEP) | |
397 | return -EOPNOTSUPP; | |
398 | ||
399 | IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg); | |
400 | return -EINVAL; | |
401 | } | |
402 | ||
4a8a4322 | 403 | static void iwl3945_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
404 | { |
405 | struct list_head *element; | |
406 | ||
e1623446 | 407 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
408 | priv->frames_count); |
409 | ||
410 | while (!list_empty(&priv->free_frames)) { | |
411 | element = priv->free_frames.next; | |
412 | list_del(element); | |
bb8c093b | 413 | kfree(list_entry(element, struct iwl3945_frame, list)); |
b481de9c ZY |
414 | priv->frames_count--; |
415 | } | |
416 | ||
417 | if (priv->frames_count) { | |
39aadf8c | 418 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
419 | priv->frames_count); |
420 | priv->frames_count = 0; | |
421 | } | |
422 | } | |
423 | ||
4a8a4322 | 424 | static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv) |
b481de9c | 425 | { |
bb8c093b | 426 | struct iwl3945_frame *frame; |
b481de9c ZY |
427 | struct list_head *element; |
428 | if (list_empty(&priv->free_frames)) { | |
429 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
430 | if (!frame) { | |
15b1687c | 431 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
432 | return NULL; |
433 | } | |
434 | ||
435 | priv->frames_count++; | |
436 | return frame; | |
437 | } | |
438 | ||
439 | element = priv->free_frames.next; | |
440 | list_del(element); | |
bb8c093b | 441 | return list_entry(element, struct iwl3945_frame, list); |
b481de9c ZY |
442 | } |
443 | ||
4a8a4322 | 444 | static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame) |
b481de9c ZY |
445 | { |
446 | memset(frame, 0, sizeof(*frame)); | |
447 | list_add(&frame->list, &priv->free_frames); | |
448 | } | |
449 | ||
4a8a4322 | 450 | unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv, |
b481de9c | 451 | struct ieee80211_hdr *hdr, |
73ec1cc2 | 452 | int left) |
b481de9c ZY |
453 | { |
454 | ||
8ccde88a | 455 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
456 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
457 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
458 | return 0; |
459 | ||
460 | if (priv->ibss_beacon->len > left) | |
461 | return 0; | |
462 | ||
463 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
464 | ||
465 | return priv->ibss_beacon->len; | |
466 | } | |
467 | ||
4a8a4322 | 468 | static int iwl3945_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 469 | { |
bb8c093b | 470 | struct iwl3945_frame *frame; |
b481de9c ZY |
471 | unsigned int frame_size; |
472 | int rc; | |
473 | u8 rate; | |
474 | ||
bb8c093b | 475 | frame = iwl3945_get_free_frame(priv); |
b481de9c ZY |
476 | |
477 | if (!frame) { | |
15b1687c | 478 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
479 | "command.\n"); |
480 | return -ENOMEM; | |
481 | } | |
482 | ||
8ccde88a | 483 | rate = iwl_rate_get_lowest_plcp(priv); |
b481de9c | 484 | |
bb8c093b | 485 | frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 486 | |
518099a8 | 487 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
488 | &frame->u.cmd[0]); |
489 | ||
bb8c093b | 490 | iwl3945_free_frame(priv, frame); |
b481de9c ZY |
491 | |
492 | return rc; | |
493 | } | |
494 | ||
4a8a4322 | 495 | static void iwl3945_unset_hw_params(struct iwl_priv *priv) |
b481de9c | 496 | { |
3832ec9d | 497 | if (priv->shared_virt) |
b481de9c | 498 | pci_free_consistent(priv->pci_dev, |
bb8c093b | 499 | sizeof(struct iwl3945_shared), |
3832ec9d AK |
500 | priv->shared_virt, |
501 | priv->shared_phys); | |
b481de9c ZY |
502 | } |
503 | ||
b481de9c | 504 | #define MAX_UCODE_BEACON_INTERVAL 1024 |
c1b4aa3f | 505 | #define INTEL_CONN_LISTEN_INTERVAL cpu_to_le16(0xA) |
b481de9c | 506 | |
bb8c093b | 507 | static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val) |
b481de9c ZY |
508 | { |
509 | u16 new_val = 0; | |
510 | u16 beacon_factor = 0; | |
511 | ||
512 | beacon_factor = | |
513 | (beacon_val + MAX_UCODE_BEACON_INTERVAL) | |
514 | / MAX_UCODE_BEACON_INTERVAL; | |
515 | new_val = beacon_val / beacon_factor; | |
516 | ||
517 | return cpu_to_le16(new_val); | |
518 | } | |
519 | ||
4a8a4322 | 520 | static void iwl3945_setup_rxon_timing(struct iwl_priv *priv) |
b481de9c ZY |
521 | { |
522 | u64 interval_tm_unit; | |
523 | u64 tsf, result; | |
524 | unsigned long flags; | |
525 | struct ieee80211_conf *conf = NULL; | |
526 | u16 beacon_int = 0; | |
527 | ||
528 | conf = ieee80211_get_hw_conf(priv->hw); | |
529 | ||
530 | spin_lock_irqsave(&priv->lock, flags); | |
28afaf91 | 531 | priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp); |
b481de9c ZY |
532 | priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL; |
533 | ||
28afaf91 | 534 | tsf = priv->timestamp; |
b481de9c ZY |
535 | |
536 | beacon_int = priv->beacon_int; | |
537 | spin_unlock_irqrestore(&priv->lock, flags); | |
538 | ||
05c914fe | 539 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
b481de9c ZY |
540 | if (beacon_int == 0) { |
541 | priv->rxon_timing.beacon_interval = cpu_to_le16(100); | |
542 | priv->rxon_timing.beacon_init_val = cpu_to_le32(102400); | |
543 | } else { | |
544 | priv->rxon_timing.beacon_interval = | |
545 | cpu_to_le16(beacon_int); | |
546 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 547 | iwl3945_adjust_beacon_interval( |
b481de9c ZY |
548 | le16_to_cpu(priv->rxon_timing.beacon_interval)); |
549 | } | |
550 | ||
551 | priv->rxon_timing.atim_window = 0; | |
552 | } else { | |
553 | priv->rxon_timing.beacon_interval = | |
57c4d7b4 JB |
554 | iwl3945_adjust_beacon_interval( |
555 | priv->vif->bss_conf.beacon_int); | |
b481de9c ZY |
556 | /* TODO: we need to get atim_window from upper stack |
557 | * for now we set to 0 */ | |
558 | priv->rxon_timing.atim_window = 0; | |
559 | } | |
560 | ||
561 | interval_tm_unit = | |
562 | (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024); | |
563 | result = do_div(tsf, interval_tm_unit); | |
564 | priv->rxon_timing.beacon_init_val = | |
565 | cpu_to_le32((u32) ((u64) interval_tm_unit - result)); | |
566 | ||
e1623446 TW |
567 | IWL_DEBUG_ASSOC(priv, |
568 | "beacon interval %d beacon timer %d beacon tim %d\n", | |
b481de9c ZY |
569 | le16_to_cpu(priv->rxon_timing.beacon_interval), |
570 | le32_to_cpu(priv->rxon_timing.beacon_init_val), | |
571 | le16_to_cpu(priv->rxon_timing.atim_window)); | |
572 | } | |
573 | ||
4a8a4322 | 574 | static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv, |
e039fa4a | 575 | struct ieee80211_tx_info *info, |
c2d79b48 | 576 | struct iwl_cmd *cmd, |
b481de9c | 577 | struct sk_buff *skb_frag, |
6e21f15c | 578 | int sta_id) |
b481de9c | 579 | { |
e52119c5 | 580 | struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
1c014420 | 581 | struct iwl3945_hw_key *keyinfo = |
6e21f15c | 582 | &priv->stations_39[sta_id].keyinfo; |
b481de9c ZY |
583 | |
584 | switch (keyinfo->alg) { | |
585 | case ALG_CCMP: | |
e52119c5 WT |
586 | tx->sec_ctl = TX_CMD_SEC_CCM; |
587 | memcpy(tx->key, keyinfo->key, keyinfo->keylen); | |
e1623446 | 588 | IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n"); |
b481de9c ZY |
589 | break; |
590 | ||
591 | case ALG_TKIP: | |
b481de9c ZY |
592 | break; |
593 | ||
594 | case ALG_WEP: | |
e52119c5 | 595 | tx->sec_ctl = TX_CMD_SEC_WEP | |
e039fa4a | 596 | (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT; |
b481de9c ZY |
597 | |
598 | if (keyinfo->keylen == 13) | |
e52119c5 | 599 | tx->sec_ctl |= TX_CMD_SEC_KEY128; |
b481de9c | 600 | |
e52119c5 | 601 | memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen); |
b481de9c | 602 | |
e1623446 | 603 | IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption " |
e039fa4a | 604 | "with key %d\n", info->control.hw_key->hw_key_idx); |
b481de9c ZY |
605 | break; |
606 | ||
b481de9c | 607 | default: |
978785a3 | 608 | IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg); |
b481de9c ZY |
609 | break; |
610 | } | |
611 | } | |
612 | ||
613 | /* | |
614 | * handle build REPLY_TX command notification. | |
615 | */ | |
4a8a4322 | 616 | static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv, |
c2d79b48 | 617 | struct iwl_cmd *cmd, |
e039fa4a | 618 | struct ieee80211_tx_info *info, |
e52119c5 | 619 | struct ieee80211_hdr *hdr, u8 std_id) |
b481de9c | 620 | { |
e52119c5 WT |
621 | struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
622 | __le32 tx_flags = tx->tx_flags; | |
fd7c8a40 | 623 | __le16 fc = hdr->frame_control; |
e6a9854b | 624 | u8 rc_flags = info->control.rates[0].flags; |
b481de9c | 625 | |
e52119c5 | 626 | tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
e039fa4a | 627 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
b481de9c | 628 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 629 | if (ieee80211_is_mgmt(fc)) |
b481de9c | 630 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 631 | if (ieee80211_is_probe_resp(fc) && |
b481de9c ZY |
632 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
633 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
634 | } else { | |
635 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
636 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
637 | } | |
638 | ||
e52119c5 | 639 | tx->sta_id = std_id; |
8b7b1e05 | 640 | if (ieee80211_has_morefrags(fc)) |
b481de9c ZY |
641 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
642 | ||
fd7c8a40 HH |
643 | if (ieee80211_is_data_qos(fc)) { |
644 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
e52119c5 | 645 | tx->tid_tspec = qc[0] & 0xf; |
b481de9c | 646 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 647 | } else { |
b481de9c | 648 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 649 | } |
b481de9c | 650 | |
e6a9854b | 651 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { |
b481de9c ZY |
652 | tx_flags |= TX_CMD_FLG_RTS_MSK; |
653 | tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
e6a9854b | 654 | } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { |
b481de9c ZY |
655 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; |
656 | tx_flags |= TX_CMD_FLG_CTS_MSK; | |
657 | } | |
658 | ||
659 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
660 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
661 | ||
662 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
663 | if (ieee80211_is_mgmt(fc)) { |
664 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
e52119c5 | 665 | tx->timeout.pm_frame_timeout = cpu_to_le16(3); |
b481de9c | 666 | else |
e52119c5 | 667 | tx->timeout.pm_frame_timeout = cpu_to_le16(2); |
ab53d8af | 668 | } else { |
e52119c5 | 669 | tx->timeout.pm_frame_timeout = 0; |
5c8df2d5 | 670 | #ifdef CONFIG_IWLWIFI_LEDS |
ab53d8af MA |
671 | priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len); |
672 | #endif | |
673 | } | |
b481de9c | 674 | |
e52119c5 WT |
675 | tx->driver_txop = 0; |
676 | tx->tx_flags = tx_flags; | |
677 | tx->next_frame_len = 0; | |
b481de9c ZY |
678 | } |
679 | ||
b481de9c ZY |
680 | /* |
681 | * start REPLY_TX command process | |
682 | */ | |
4a8a4322 | 683 | static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
b481de9c ZY |
684 | { |
685 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 686 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
e52119c5 | 687 | struct iwl3945_tx_cmd *tx; |
188cf6c7 | 688 | struct iwl_tx_queue *txq = NULL; |
d20b3c65 | 689 | struct iwl_queue *q = NULL; |
e52119c5 | 690 | struct iwl_cmd *out_cmd = NULL; |
b481de9c ZY |
691 | dma_addr_t phys_addr; |
692 | dma_addr_t txcmd_phys; | |
e52119c5 | 693 | int txq_id = skb_get_queue_mapping(skb); |
df833b1d | 694 | u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */ |
54dbb525 TW |
695 | u8 id; |
696 | u8 unicast; | |
b481de9c | 697 | u8 sta_id; |
54dbb525 | 698 | u8 tid = 0; |
b481de9c | 699 | u16 seq_number = 0; |
fd7c8a40 | 700 | __le16 fc; |
b481de9c | 701 | u8 wait_write_ptr = 0; |
54dbb525 | 702 | u8 *qc = NULL; |
b481de9c ZY |
703 | unsigned long flags; |
704 | int rc; | |
705 | ||
706 | spin_lock_irqsave(&priv->lock, flags); | |
775a6e27 | 707 | if (iwl_is_rfkill(priv)) { |
e1623446 | 708 | IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n"); |
b481de9c ZY |
709 | goto drop_unlock; |
710 | } | |
711 | ||
e039fa4a | 712 | if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) { |
15b1687c | 713 | IWL_ERR(priv, "ERROR: No TX rate available.\n"); |
b481de9c ZY |
714 | goto drop_unlock; |
715 | } | |
716 | ||
717 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
718 | id = 0; | |
719 | ||
fd7c8a40 | 720 | fc = hdr->frame_control; |
b481de9c | 721 | |
d08853a3 | 722 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c | 723 | if (ieee80211_is_auth(fc)) |
e1623446 | 724 | IWL_DEBUG_TX(priv, "Sending AUTH frame\n"); |
fd7c8a40 | 725 | else if (ieee80211_is_assoc_req(fc)) |
e1623446 | 726 | IWL_DEBUG_TX(priv, "Sending ASSOC frame\n"); |
fd7c8a40 | 727 | else if (ieee80211_is_reassoc_req(fc)) |
e1623446 | 728 | IWL_DEBUG_TX(priv, "Sending REASSOC frame\n"); |
b481de9c ZY |
729 | #endif |
730 | ||
7878a5a4 | 731 | /* drop all data frame if we are not associated */ |
914233d6 | 732 | if (ieee80211_is_data(fc) && |
279b05d4 | 733 | (!iwl_is_monitor_mode(priv)) && /* packet injection */ |
8ccde88a | 734 | (!iwl_is_associated(priv) || |
05c914fe | 735 | ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) { |
e1623446 | 736 | IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n"); |
b481de9c ZY |
737 | goto drop_unlock; |
738 | } | |
739 | ||
740 | spin_unlock_irqrestore(&priv->lock, flags); | |
741 | ||
7294ec95 | 742 | hdr_len = ieee80211_hdrlen(fc); |
6440adb5 CB |
743 | |
744 | /* Find (or create) index into station table for destination station */ | |
f5d30266 | 745 | sta_id = iwl_get_sta_id(priv, hdr); |
b481de9c | 746 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 747 | IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n", |
e174961c | 748 | hdr->addr1); |
b481de9c ZY |
749 | goto drop; |
750 | } | |
751 | ||
e1623446 | 752 | IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id); |
b481de9c | 753 | |
fd7c8a40 HH |
754 | if (ieee80211_is_data_qos(fc)) { |
755 | qc = ieee80211_get_qos_ctl(hdr); | |
7294ec95 | 756 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
f2c7e521 | 757 | seq_number = priv->stations_39[sta_id].tid[tid].seq_number & |
b481de9c ZY |
758 | IEEE80211_SCTL_SEQ; |
759 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
760 | (hdr->seq_ctrl & | |
c1b4aa3f | 761 | cpu_to_le16(IEEE80211_SCTL_FRAG)); |
b481de9c ZY |
762 | seq_number += 0x10; |
763 | } | |
6440adb5 CB |
764 | |
765 | /* Descriptor for chosen Tx queue */ | |
188cf6c7 | 766 | txq = &priv->txq[txq_id]; |
b481de9c ZY |
767 | q = &txq->q; |
768 | ||
769 | spin_lock_irqsave(&priv->lock, flags); | |
770 | ||
fc4b6853 | 771 | idx = get_cmd_index(q, q->write_ptr, 0); |
b481de9c | 772 | |
6440adb5 | 773 | /* Set up driver data for this TFD */ |
dbb6654c | 774 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); |
fc4b6853 | 775 | txq->txb[q->write_ptr].skb[0] = skb; |
6440adb5 CB |
776 | |
777 | /* Init first empty entry in queue's array of Tx/cmd buffers */ | |
188cf6c7 | 778 | out_cmd = txq->cmd[idx]; |
e52119c5 | 779 | tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload; |
b481de9c | 780 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); |
e52119c5 | 781 | memset(tx, 0, sizeof(*tx)); |
6440adb5 CB |
782 | |
783 | /* | |
784 | * Set up the Tx-command (not MAC!) header. | |
785 | * Store the chosen Tx queue and TFD index within the sequence field; | |
786 | * after Tx, uCode's Tx response will return this value so driver can | |
787 | * locate the frame within the tx queue and do post-tx processing. | |
788 | */ | |
b481de9c ZY |
789 | out_cmd->hdr.cmd = REPLY_TX; |
790 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
fc4b6853 | 791 | INDEX_TO_SEQ(q->write_ptr))); |
6440adb5 CB |
792 | |
793 | /* Copy MAC header from skb into command buffer */ | |
e52119c5 | 794 | memcpy(tx->hdr, hdr, hdr_len); |
b481de9c | 795 | |
df833b1d RC |
796 | |
797 | if (info->control.hw_key) | |
798 | iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id); | |
799 | ||
800 | /* TODO need this for burst mode later on */ | |
801 | iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id); | |
802 | ||
803 | /* set is_hcca to 0; it probably will never be implemented */ | |
804 | iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0); | |
805 | ||
806 | /* Total # bytes to be transmitted */ | |
807 | len = (u16)skb->len; | |
808 | tx->len = cpu_to_le16(len); | |
809 | ||
810 | ||
811 | tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK; | |
812 | tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK; | |
813 | ||
814 | if (!ieee80211_has_morefrags(hdr->frame_control)) { | |
815 | txq->need_update = 1; | |
816 | if (qc) | |
817 | priv->stations_39[sta_id].tid[tid].seq_number = seq_number; | |
818 | } else { | |
819 | wait_write_ptr = 1; | |
820 | txq->need_update = 0; | |
821 | } | |
822 | ||
823 | IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n", | |
824 | le16_to_cpu(out_cmd->hdr.sequence)); | |
825 | IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx->tx_flags)); | |
826 | iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx)); | |
827 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr, | |
828 | ieee80211_hdrlen(fc)); | |
829 | ||
6440adb5 CB |
830 | /* |
831 | * Use the first empty entry in this queue's command buffer array | |
832 | * to contain the Tx command and MAC header concatenated together | |
833 | * (payload data will be in another buffer). | |
834 | * Size of this varies, due to varying MAC header length. | |
835 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
836 | * of the MAC header (device reads on dword boundaries). | |
837 | * We'll tell device about this padding later. | |
838 | */ | |
3832ec9d | 839 | len = sizeof(struct iwl3945_tx_cmd) + |
4c897253 | 840 | sizeof(struct iwl_cmd_header) + hdr_len; |
b481de9c ZY |
841 | |
842 | len_org = len; | |
843 | len = (len + 3) & ~3; | |
844 | ||
845 | if (len_org != len) | |
846 | len_org = 1; | |
847 | else | |
848 | len_org = 0; | |
849 | ||
6440adb5 CB |
850 | /* Physical address of this Tx command's header (not MAC header!), |
851 | * within command buffer array. */ | |
df833b1d RC |
852 | txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr, |
853 | len, PCI_DMA_TODEVICE); | |
854 | /* we do not map meta data ... so we can safely access address to | |
855 | * provide to unmap command*/ | |
188cf6c7 | 856 | pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys); |
df833b1d | 857 | pci_unmap_len_set(&out_cmd->meta, len, len); |
b481de9c | 858 | |
6440adb5 CB |
859 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
860 | * first entry */ | |
7aaa1d79 SO |
861 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
862 | txcmd_phys, len, 1, 0); | |
b481de9c | 863 | |
b481de9c | 864 | |
6440adb5 CB |
865 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
866 | * if any (802.11 null frames have no payload). */ | |
b481de9c ZY |
867 | len = skb->len - hdr_len; |
868 | if (len) { | |
869 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
870 | len, PCI_DMA_TODEVICE); | |
7aaa1d79 SO |
871 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
872 | phys_addr, len, | |
873 | 0, U32_PAD(len)); | |
b481de9c ZY |
874 | } |
875 | ||
b481de9c | 876 | |
6440adb5 | 877 | /* Tell device the write index *just past* this latest filled TFD */ |
c54b679d | 878 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
4f3602c8 | 879 | rc = iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
880 | spin_unlock_irqrestore(&priv->lock, flags); |
881 | ||
882 | if (rc) | |
883 | return rc; | |
884 | ||
d20b3c65 | 885 | if ((iwl_queue_space(q) < q->high_mark) |
b481de9c ZY |
886 | && priv->mac80211_registered) { |
887 | if (wait_write_ptr) { | |
888 | spin_lock_irqsave(&priv->lock, flags); | |
889 | txq->need_update = 1; | |
4f3602c8 | 890 | iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
891 | spin_unlock_irqrestore(&priv->lock, flags); |
892 | } | |
893 | ||
e4e72fb4 | 894 | iwl_stop_queue(priv, skb_get_queue_mapping(skb)); |
b481de9c ZY |
895 | } |
896 | ||
897 | return 0; | |
898 | ||
899 | drop_unlock: | |
900 | spin_unlock_irqrestore(&priv->lock, flags); | |
901 | drop: | |
902 | return -1; | |
903 | } | |
904 | ||
c8b0e6e1 | 905 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
906 | |
907 | #include "iwl-spectrum.h" | |
908 | ||
909 | #define BEACON_TIME_MASK_LOW 0x00FFFFFF | |
910 | #define BEACON_TIME_MASK_HIGH 0xFF000000 | |
911 | #define TIME_UNIT 1024 | |
912 | ||
913 | /* | |
914 | * extended beacon time format | |
915 | * time in usec will be changed into a 32-bit value in 8:24 format | |
916 | * the high 1 byte is the beacon counts | |
917 | * the lower 3 bytes is the time in usec within one beacon interval | |
918 | */ | |
919 | ||
bb8c093b | 920 | static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval) |
b481de9c ZY |
921 | { |
922 | u32 quot; | |
923 | u32 rem; | |
924 | u32 interval = beacon_interval * 1024; | |
925 | ||
926 | if (!interval || !usec) | |
927 | return 0; | |
928 | ||
929 | quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24); | |
930 | rem = (usec % interval) & BEACON_TIME_MASK_LOW; | |
931 | ||
932 | return (quot << 24) + rem; | |
933 | } | |
934 | ||
935 | /* base is usually what we get from ucode with each received frame, | |
936 | * the same as HW timer counter counting down | |
937 | */ | |
938 | ||
bb8c093b | 939 | static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval) |
b481de9c ZY |
940 | { |
941 | u32 base_low = base & BEACON_TIME_MASK_LOW; | |
942 | u32 addon_low = addon & BEACON_TIME_MASK_LOW; | |
943 | u32 interval = beacon_interval * TIME_UNIT; | |
944 | u32 res = (base & BEACON_TIME_MASK_HIGH) + | |
945 | (addon & BEACON_TIME_MASK_HIGH); | |
946 | ||
947 | if (base_low > addon_low) | |
948 | res += base_low - addon_low; | |
949 | else if (base_low < addon_low) { | |
950 | res += interval + base_low - addon_low; | |
951 | res += (1 << 24); | |
952 | } else | |
953 | res += (1 << 24); | |
954 | ||
955 | return cpu_to_le32(res); | |
956 | } | |
957 | ||
4a8a4322 | 958 | static int iwl3945_get_measurement(struct iwl_priv *priv, |
b481de9c ZY |
959 | struct ieee80211_measurement_params *params, |
960 | u8 type) | |
961 | { | |
600c0e11 | 962 | struct iwl_spectrum_cmd spectrum; |
3d24a9f7 | 963 | struct iwl_rx_packet *res; |
c2d79b48 | 964 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
965 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
966 | .data = (void *)&spectrum, | |
967 | .meta.flags = CMD_WANT_SKB, | |
968 | }; | |
969 | u32 add_time = le64_to_cpu(params->start_time); | |
970 | int rc; | |
971 | int spectrum_resp_status; | |
972 | int duration = le16_to_cpu(params->duration); | |
973 | ||
8ccde88a | 974 | if (iwl_is_associated(priv)) |
b481de9c | 975 | add_time = |
bb8c093b | 976 | iwl3945_usecs_to_beacons( |
b481de9c ZY |
977 | le64_to_cpu(params->start_time) - priv->last_tsf, |
978 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
979 | ||
980 | memset(&spectrum, 0, sizeof(spectrum)); | |
981 | ||
982 | spectrum.channel_count = cpu_to_le16(1); | |
983 | spectrum.flags = | |
984 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
985 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
986 | cmd.len = sizeof(spectrum); | |
987 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
988 | ||
8ccde88a | 989 | if (iwl_is_associated(priv)) |
b481de9c | 990 | spectrum.start_time = |
bb8c093b | 991 | iwl3945_add_beacon_time(priv->last_beacon_time, |
b481de9c ZY |
992 | add_time, |
993 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
994 | else | |
995 | spectrum.start_time = 0; | |
996 | ||
997 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
998 | spectrum.channels[0].channel = params->channel; | |
999 | spectrum.channels[0].type = type; | |
8ccde88a | 1000 | if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK) |
b481de9c ZY |
1001 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | |
1002 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
1003 | ||
518099a8 | 1004 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
1005 | if (rc) |
1006 | return rc; | |
1007 | ||
3d24a9f7 | 1008 | res = (struct iwl_rx_packet *)cmd.meta.u.skb->data; |
b481de9c | 1009 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
15b1687c | 1010 | IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n"); |
b481de9c ZY |
1011 | rc = -EIO; |
1012 | } | |
1013 | ||
1014 | spectrum_resp_status = le16_to_cpu(res->u.spectrum.status); | |
1015 | switch (spectrum_resp_status) { | |
1016 | case 0: /* Command will be handled */ | |
1017 | if (res->u.spectrum.id != 0xff) { | |
e1623446 | 1018 | IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n", |
bc434dd2 | 1019 | res->u.spectrum.id); |
b481de9c ZY |
1020 | priv->measurement_status &= ~MEASUREMENT_READY; |
1021 | } | |
1022 | priv->measurement_status |= MEASUREMENT_ACTIVE; | |
1023 | rc = 0; | |
1024 | break; | |
1025 | ||
1026 | case 1: /* Command will not be handled */ | |
1027 | rc = -EAGAIN; | |
1028 | break; | |
1029 | } | |
1030 | ||
1031 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1032 | ||
1033 | return rc; | |
1034 | } | |
1035 | #endif | |
1036 | ||
4a8a4322 | 1037 | static void iwl3945_rx_reply_alive(struct iwl_priv *priv, |
6100b588 | 1038 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 1039 | { |
3d24a9f7 TW |
1040 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
1041 | struct iwl_alive_resp *palive; | |
b481de9c ZY |
1042 | struct delayed_work *pwork; |
1043 | ||
1044 | palive = &pkt->u.alive_frame; | |
1045 | ||
e1623446 | 1046 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
1047 | "0x%01X 0x%01X\n", |
1048 | palive->is_valid, palive->ver_type, | |
1049 | palive->ver_subtype); | |
1050 | ||
1051 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 1052 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
3d24a9f7 TW |
1053 | memcpy(&priv->card_alive_init, &pkt->u.alive_frame, |
1054 | sizeof(struct iwl_alive_resp)); | |
b481de9c ZY |
1055 | pwork = &priv->init_alive_start; |
1056 | } else { | |
e1623446 | 1057 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 1058 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
3d24a9f7 | 1059 | sizeof(struct iwl_alive_resp)); |
b481de9c | 1060 | pwork = &priv->alive_start; |
bb8c093b | 1061 | iwl3945_disable_events(priv); |
b481de9c ZY |
1062 | } |
1063 | ||
1064 | /* We delay the ALIVE response by 5ms to | |
1065 | * give the HW RF Kill time to activate... */ | |
1066 | if (palive->is_valid == UCODE_VALID_OK) | |
1067 | queue_delayed_work(priv->workqueue, pwork, | |
1068 | msecs_to_jiffies(5)); | |
1069 | else | |
39aadf8c | 1070 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
1071 | } |
1072 | ||
4a8a4322 | 1073 | static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv, |
6100b588 | 1074 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 1075 | { |
c7e035a9 | 1076 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d24a9f7 | 1077 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
c7e035a9 | 1078 | #endif |
b481de9c | 1079 | |
e1623446 | 1080 | IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); |
b481de9c ZY |
1081 | return; |
1082 | } | |
1083 | ||
bb8c093b | 1084 | static void iwl3945_bg_beacon_update(struct work_struct *work) |
b481de9c | 1085 | { |
4a8a4322 AK |
1086 | struct iwl_priv *priv = |
1087 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
1088 | struct sk_buff *beacon; |
1089 | ||
1090 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 1091 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
1092 | |
1093 | if (!beacon) { | |
15b1687c | 1094 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
1095 | return; |
1096 | } | |
1097 | ||
1098 | mutex_lock(&priv->mutex); | |
1099 | /* new beacon skb is allocated every time; dispose previous.*/ | |
1100 | if (priv->ibss_beacon) | |
1101 | dev_kfree_skb(priv->ibss_beacon); | |
1102 | ||
1103 | priv->ibss_beacon = beacon; | |
1104 | mutex_unlock(&priv->mutex); | |
1105 | ||
bb8c093b | 1106 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
1107 | } |
1108 | ||
4a8a4322 | 1109 | static void iwl3945_rx_beacon_notif(struct iwl_priv *priv, |
6100b588 | 1110 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 1111 | { |
d08853a3 | 1112 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d24a9f7 | 1113 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
bb8c093b | 1114 | struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status); |
b481de9c ZY |
1115 | u8 rate = beacon->beacon_notify_hdr.rate; |
1116 | ||
e1623446 | 1117 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c ZY |
1118 | "tsf %d %d rate %d\n", |
1119 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
1120 | beacon->beacon_notify_hdr.failure_frame, | |
1121 | le32_to_cpu(beacon->ibss_mgr_status), | |
1122 | le32_to_cpu(beacon->high_tsf), | |
1123 | le32_to_cpu(beacon->low_tsf), rate); | |
1124 | #endif | |
1125 | ||
05c914fe | 1126 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
1127 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
1128 | queue_work(priv->workqueue, &priv->beacon_update); | |
1129 | } | |
1130 | ||
b481de9c ZY |
1131 | /* Handle notification from uCode that card's power state is changing |
1132 | * due to software, hardware, or critical temperature RFKILL */ | |
4a8a4322 | 1133 | static void iwl3945_rx_card_state_notif(struct iwl_priv *priv, |
6100b588 | 1134 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 1135 | { |
3d24a9f7 | 1136 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
1137 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
1138 | unsigned long status = priv->status; | |
1139 | ||
e1623446 | 1140 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n", |
b481de9c ZY |
1141 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
1142 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
1143 | ||
5d49f498 | 1144 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
1145 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
1146 | ||
1147 | if (flags & HW_CARD_DISABLED) | |
1148 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1149 | else | |
1150 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
1151 | ||
1152 | ||
1153 | if (flags & SW_CARD_DISABLED) | |
1154 | set_bit(STATUS_RF_KILL_SW, &priv->status); | |
1155 | else | |
1156 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
1157 | ||
af0053d6 | 1158 | iwl_scan_cancel(priv); |
b481de9c ZY |
1159 | |
1160 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
1161 | test_bit(STATUS_RF_KILL_HW, &priv->status)) || | |
1162 | (test_bit(STATUS_RF_KILL_SW, &status) != | |
1163 | test_bit(STATUS_RF_KILL_SW, &priv->status))) | |
1164 | queue_work(priv->workqueue, &priv->rf_kill); | |
1165 | else | |
1166 | wake_up_interruptible(&priv->wait_command_queue); | |
1167 | } | |
1168 | ||
1169 | /** | |
bb8c093b | 1170 | * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
1171 | * |
1172 | * Setup the RX handlers for each of the reply types sent from the uCode | |
1173 | * to the host. | |
1174 | * | |
1175 | * This function chains into the hardware specific files for them to setup | |
1176 | * any hardware specific handlers as well. | |
1177 | */ | |
4a8a4322 | 1178 | static void iwl3945_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 1179 | { |
bb8c093b CH |
1180 | priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive; |
1181 | priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta; | |
261b9c33 | 1182 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
8ccde88a | 1183 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; |
030f05ed | 1184 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 1185 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
030f05ed | 1186 | iwl_rx_pm_debug_statistics_notif; |
bb8c093b | 1187 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif; |
b481de9c | 1188 | |
9fbab516 BC |
1189 | /* |
1190 | * The same handler is used for both the REPLY to a discrete | |
1191 | * statistics request from the host as well as for the periodic | |
1192 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 1193 | */ |
bb8c093b CH |
1194 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics; |
1195 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics; | |
b481de9c | 1196 | |
261b9c33 | 1197 | iwl_setup_spectrum_handlers(priv); |
cade0eb2 | 1198 | iwl_setup_rx_scan_handlers(priv); |
bb8c093b | 1199 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif; |
b481de9c | 1200 | |
9fbab516 | 1201 | /* Set up hardware specific Rx handlers */ |
bb8c093b | 1202 | iwl3945_hw_rx_handler_setup(priv); |
b481de9c ZY |
1203 | } |
1204 | ||
b481de9c ZY |
1205 | /************************** RX-FUNCTIONS ****************************/ |
1206 | /* | |
1207 | * Rx theory of operation | |
1208 | * | |
1209 | * The host allocates 32 DMA target addresses and passes the host address | |
1210 | * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is | |
1211 | * 0 to 31 | |
1212 | * | |
1213 | * Rx Queue Indexes | |
1214 | * The host/firmware share two index registers for managing the Rx buffers. | |
1215 | * | |
1216 | * The READ index maps to the first position that the firmware may be writing | |
1217 | * to -- the driver can read up to (but not including) this position and get | |
1218 | * good data. | |
1219 | * The READ index is managed by the firmware once the card is enabled. | |
1220 | * | |
1221 | * The WRITE index maps to the last position the driver has read from -- the | |
1222 | * position preceding WRITE is the last slot the firmware can place a packet. | |
1223 | * | |
1224 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
1225 | * WRITE = READ. | |
1226 | * | |
9fbab516 | 1227 | * During initialization, the host sets up the READ queue position to the first |
b481de9c ZY |
1228 | * INDEX position, and WRITE to the last (READ - 1 wrapped) |
1229 | * | |
9fbab516 | 1230 | * When the firmware places a packet in a buffer, it will advance the READ index |
b481de9c ZY |
1231 | * and fire the RX interrupt. The driver can then query the READ index and |
1232 | * process as many packets as possible, moving the WRITE index forward as it | |
1233 | * resets the Rx queue buffers with new memory. | |
1234 | * | |
1235 | * The management in the driver is as follows: | |
1236 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
1237 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
01ebd063 | 1238 | * to replenish the iwl->rxq->rx_free. |
bb8c093b | 1239 | * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the |
b481de9c ZY |
1240 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
1241 | * 'processed' and 'read' driver indexes as well) | |
1242 | * + A received packet is processed and handed to the kernel network stack, | |
1243 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
1244 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
1245 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
1246 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
1247 | * were enough free buffers and RX_STALLED is set it is cleared. | |
1248 | * | |
1249 | * | |
1250 | * Driver sequence: | |
1251 | * | |
9fbab516 | 1252 | * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls |
bb8c093b | 1253 | * iwl3945_rx_queue_restock |
9fbab516 | 1254 | * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx |
b481de9c ZY |
1255 | * queue, updates firmware pointers, and updates |
1256 | * the WRITE index. If insufficient rx_free buffers | |
bb8c093b | 1257 | * are available, schedules iwl3945_rx_replenish |
b481de9c ZY |
1258 | * |
1259 | * -- enable interrupts -- | |
6100b588 | 1260 | * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the |
b481de9c ZY |
1261 | * READ INDEX, detaching the SKB from the pool. |
1262 | * Moves the packet buffer from queue to rx_used. | |
bb8c093b | 1263 | * Calls iwl3945_rx_queue_restock to refill any empty |
b481de9c ZY |
1264 | * slots. |
1265 | * ... | |
1266 | * | |
1267 | */ | |
1268 | ||
b481de9c | 1269 | /** |
9fbab516 | 1270 | * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
b481de9c | 1271 | */ |
4a8a4322 | 1272 | static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv, |
b481de9c ZY |
1273 | dma_addr_t dma_addr) |
1274 | { | |
1275 | return cpu_to_le32((u32)dma_addr); | |
1276 | } | |
1277 | ||
1278 | /** | |
bb8c093b | 1279 | * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool |
b481de9c | 1280 | * |
9fbab516 | 1281 | * If there are slots in the RX queue that need to be restocked, |
b481de9c | 1282 | * and we have free pre-allocated buffers, fill the ranks as much |
9fbab516 | 1283 | * as we can, pulling from rx_free. |
b481de9c ZY |
1284 | * |
1285 | * This moves the 'write' index forward to catch up with 'processed', and | |
1286 | * also updates the memory address in the firmware to reference the new | |
1287 | * target buffer. | |
1288 | */ | |
4a8a4322 | 1289 | static int iwl3945_rx_queue_restock(struct iwl_priv *priv) |
b481de9c | 1290 | { |
cc2f362c | 1291 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 1292 | struct list_head *element; |
6100b588 | 1293 | struct iwl_rx_mem_buffer *rxb; |
b481de9c ZY |
1294 | unsigned long flags; |
1295 | int write, rc; | |
1296 | ||
1297 | spin_lock_irqsave(&rxq->lock, flags); | |
1298 | write = rxq->write & ~0x7; | |
37d68317 | 1299 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
6440adb5 | 1300 | /* Get next free Rx buffer, remove from free list */ |
b481de9c | 1301 | element = rxq->rx_free.next; |
6100b588 | 1302 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); |
b481de9c | 1303 | list_del(element); |
6440adb5 CB |
1304 | |
1305 | /* Point to Rx buffer via next RBD in circular buffer */ | |
6100b588 | 1306 | rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr); |
b481de9c ZY |
1307 | rxq->queue[rxq->write] = rxb; |
1308 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
1309 | rxq->free_count--; | |
1310 | } | |
1311 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1312 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
1313 | * refill it */ | |
1314 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
1315 | queue_work(priv->workqueue, &priv->rx_replenish); | |
1316 | ||
1317 | ||
6440adb5 CB |
1318 | /* If we've added more space for the firmware to place data, tell it. |
1319 | * Increment device's write pointer in multiples of 8. */ | |
b481de9c ZY |
1320 | if ((write != (rxq->write & ~0x7)) |
1321 | || (abs(rxq->write - rxq->read) > 7)) { | |
1322 | spin_lock_irqsave(&rxq->lock, flags); | |
1323 | rxq->need_update = 1; | |
1324 | spin_unlock_irqrestore(&rxq->lock, flags); | |
141c43a3 | 1325 | rc = iwl_rx_queue_update_write_ptr(priv, rxq); |
b481de9c ZY |
1326 | if (rc) |
1327 | return rc; | |
1328 | } | |
1329 | ||
1330 | return 0; | |
1331 | } | |
1332 | ||
1333 | /** | |
bb8c093b | 1334 | * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free |
b481de9c ZY |
1335 | * |
1336 | * When moving to rx_free an SKB is allocated for the slot. | |
1337 | * | |
bb8c093b | 1338 | * Also restock the Rx queue via iwl3945_rx_queue_restock. |
01ebd063 | 1339 | * This is called as a scheduled work item (except for during initialization) |
b481de9c | 1340 | */ |
4a8a4322 | 1341 | static void iwl3945_rx_allocate(struct iwl_priv *priv) |
b481de9c | 1342 | { |
cc2f362c | 1343 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 1344 | struct list_head *element; |
6100b588 | 1345 | struct iwl_rx_mem_buffer *rxb; |
b481de9c | 1346 | unsigned long flags; |
72240498 AK |
1347 | |
1348 | while (1) { | |
1349 | spin_lock_irqsave(&rxq->lock, flags); | |
1350 | ||
1351 | if (list_empty(&rxq->rx_used)) { | |
1352 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1353 | return; | |
1354 | } | |
1355 | ||
b481de9c | 1356 | element = rxq->rx_used.next; |
6100b588 | 1357 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); |
72240498 AK |
1358 | list_del(element); |
1359 | spin_unlock_irqrestore(&rxq->lock, flags); | |
6440adb5 CB |
1360 | |
1361 | /* Alloc a new receive buffer */ | |
b481de9c | 1362 | rxb->skb = |
1e33dc64 | 1363 | alloc_skb(priv->hw_params.rx_buf_size, |
72240498 | 1364 | GFP_KERNEL); |
b481de9c ZY |
1365 | if (!rxb->skb) { |
1366 | if (net_ratelimit()) | |
978785a3 | 1367 | IWL_CRIT(priv, ": Can not allocate SKB buffers\n"); |
b481de9c ZY |
1368 | /* We don't reschedule replenish work here -- we will |
1369 | * call the restock method and if it still needs | |
1370 | * more buffers it will schedule replenish */ | |
1371 | break; | |
1372 | } | |
12342c47 ZY |
1373 | |
1374 | /* If radiotap head is required, reserve some headroom here. | |
1375 | * The physical head count is a variable rx_stats->phy_count. | |
1376 | * We reserve 4 bytes here. Plus these extra bytes, the | |
1377 | * headroom of the physical head should be enough for the | |
1378 | * radiotap head that iwl3945 supported. See iwl3945_rt. | |
1379 | */ | |
1380 | skb_reserve(rxb->skb, 4); | |
1381 | ||
6440adb5 | 1382 | /* Get physical address of RB/SKB */ |
1e33dc64 WT |
1383 | rxb->real_dma_addr = pci_map_single(priv->pci_dev, |
1384 | rxb->skb->data, | |
1385 | priv->hw_params.rx_buf_size, | |
1386 | PCI_DMA_FROMDEVICE); | |
72240498 AK |
1387 | |
1388 | spin_lock_irqsave(&rxq->lock, flags); | |
b481de9c | 1389 | list_add_tail(&rxb->list, &rxq->rx_free); |
72240498 | 1390 | priv->alloc_rxb_skb++; |
b481de9c | 1391 | rxq->free_count++; |
72240498 | 1392 | spin_unlock_irqrestore(&rxq->lock, flags); |
b481de9c | 1393 | } |
5c0eef96 MA |
1394 | } |
1395 | ||
df833b1d RC |
1396 | void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq) |
1397 | { | |
1398 | unsigned long flags; | |
1399 | int i; | |
1400 | spin_lock_irqsave(&rxq->lock, flags); | |
1401 | INIT_LIST_HEAD(&rxq->rx_free); | |
1402 | INIT_LIST_HEAD(&rxq->rx_used); | |
1403 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
1404 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
1405 | /* In the reset function, these buffers may have been allocated | |
1406 | * to an SKB, so we need to unmap and free potential storage */ | |
1407 | if (rxq->pool[i].skb != NULL) { | |
1408 | pci_unmap_single(priv->pci_dev, | |
1409 | rxq->pool[i].real_dma_addr, | |
1410 | priv->hw_params.rx_buf_size, | |
1411 | PCI_DMA_FROMDEVICE); | |
1412 | priv->alloc_rxb_skb--; | |
1413 | dev_kfree_skb(rxq->pool[i].skb); | |
1414 | rxq->pool[i].skb = NULL; | |
1415 | } | |
1416 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
1417 | } | |
1418 | ||
1419 | /* Set us so that we have processed and used all buffers, but have | |
1420 | * not restocked the Rx queue with fresh buffers */ | |
1421 | rxq->read = rxq->write = 0; | |
1422 | rxq->free_count = 0; | |
1423 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1424 | } | |
df833b1d | 1425 | |
5c0eef96 MA |
1426 | void iwl3945_rx_replenish(void *data) |
1427 | { | |
4a8a4322 | 1428 | struct iwl_priv *priv = data; |
5c0eef96 MA |
1429 | unsigned long flags; |
1430 | ||
1431 | iwl3945_rx_allocate(priv); | |
b481de9c ZY |
1432 | |
1433 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 1434 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
1435 | spin_unlock_irqrestore(&priv->lock, flags); |
1436 | } | |
1437 | ||
df833b1d RC |
1438 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. |
1439 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL | |
1440 | * This free routine walks the list of POOL entries and if SKB is set to | |
1441 | * non NULL it is unmapped and freed | |
1442 | */ | |
1443 | static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
1444 | { | |
1445 | int i; | |
1446 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
1447 | if (rxq->pool[i].skb != NULL) { | |
1448 | pci_unmap_single(priv->pci_dev, | |
1449 | rxq->pool[i].real_dma_addr, | |
1450 | priv->hw_params.rx_buf_size, | |
1451 | PCI_DMA_FROMDEVICE); | |
1452 | dev_kfree_skb(rxq->pool[i].skb); | |
1453 | } | |
1454 | } | |
1455 | ||
1456 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
1457 | rxq->dma_addr); | |
1458 | pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status), | |
1459 | rxq->rb_stts, rxq->rb_stts_dma); | |
1460 | rxq->bd = NULL; | |
1461 | rxq->rb_stts = NULL; | |
1462 | } | |
1463 | EXPORT_SYMBOL(iwl3945_rx_queue_free); | |
1464 | ||
1465 | ||
b481de9c ZY |
1466 | /* Convert linear signal-to-noise ratio into dB */ |
1467 | static u8 ratio2dB[100] = { | |
1468 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
1469 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
1470 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
1471 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
1472 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
1473 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
1474 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
1475 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
1476 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
1477 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
1478 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
1479 | }; | |
1480 | ||
1481 | /* Calculates a relative dB value from a ratio of linear | |
1482 | * (i.e. not dB) signal levels. | |
1483 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
bb8c093b | 1484 | int iwl3945_calc_db_from_ratio(int sig_ratio) |
b481de9c | 1485 | { |
221c80cf AB |
1486 | /* 1000:1 or higher just report as 60 dB */ |
1487 | if (sig_ratio >= 1000) | |
b481de9c ZY |
1488 | return 60; |
1489 | ||
221c80cf | 1490 | /* 100:1 or higher, divide by 10 and use table, |
b481de9c | 1491 | * add 20 dB to make up for divide by 10 */ |
221c80cf | 1492 | if (sig_ratio >= 100) |
3ac7f146 | 1493 | return 20 + (int)ratio2dB[sig_ratio/10]; |
b481de9c ZY |
1494 | |
1495 | /* We shouldn't see this */ | |
1496 | if (sig_ratio < 1) | |
1497 | return 0; | |
1498 | ||
1499 | /* Use table for ratios 1:1 - 99:1 */ | |
1500 | return (int)ratio2dB[sig_ratio]; | |
1501 | } | |
1502 | ||
1503 | #define PERFECT_RSSI (-20) /* dBm */ | |
1504 | #define WORST_RSSI (-95) /* dBm */ | |
1505 | #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI) | |
1506 | ||
1507 | /* Calculate an indication of rx signal quality (a percentage, not dBm!). | |
1508 | * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info | |
1509 | * about formulas used below. */ | |
bb8c093b | 1510 | int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm) |
b481de9c ZY |
1511 | { |
1512 | int sig_qual; | |
1513 | int degradation = PERFECT_RSSI - rssi_dbm; | |
1514 | ||
1515 | /* If we get a noise measurement, use signal-to-noise ratio (SNR) | |
1516 | * as indicator; formula is (signal dbm - noise dbm). | |
1517 | * SNR at or above 40 is a great signal (100%). | |
1518 | * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator. | |
1519 | * Weakest usable signal is usually 10 - 15 dB SNR. */ | |
1520 | if (noise_dbm) { | |
1521 | if (rssi_dbm - noise_dbm >= 40) | |
1522 | return 100; | |
1523 | else if (rssi_dbm < noise_dbm) | |
1524 | return 0; | |
1525 | sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2; | |
1526 | ||
1527 | /* Else use just the signal level. | |
1528 | * This formula is a least squares fit of data points collected and | |
1529 | * compared with a reference system that had a percentage (%) display | |
1530 | * for signal quality. */ | |
1531 | } else | |
1532 | sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation * | |
1533 | (15 * RSSI_RANGE + 62 * degradation)) / | |
1534 | (RSSI_RANGE * RSSI_RANGE); | |
1535 | ||
1536 | if (sig_qual > 100) | |
1537 | sig_qual = 100; | |
1538 | else if (sig_qual < 1) | |
1539 | sig_qual = 0; | |
1540 | ||
1541 | return sig_qual; | |
1542 | } | |
1543 | ||
1544 | /** | |
9fbab516 | 1545 | * iwl3945_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
1546 | * |
1547 | * Uses the priv->rx_handlers callback function array to invoke | |
1548 | * the appropriate handlers, including command responses, | |
1549 | * frame-received notifications, and other notifications. | |
1550 | */ | |
4a8a4322 | 1551 | static void iwl3945_rx_handle(struct iwl_priv *priv) |
b481de9c | 1552 | { |
6100b588 | 1553 | struct iwl_rx_mem_buffer *rxb; |
3d24a9f7 | 1554 | struct iwl_rx_packet *pkt; |
cc2f362c | 1555 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
1556 | u32 r, i; |
1557 | int reclaim; | |
1558 | unsigned long flags; | |
5c0eef96 | 1559 | u8 fill_rx = 0; |
d68ab680 | 1560 | u32 count = 8; |
b481de9c | 1561 | |
6440adb5 CB |
1562 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
1563 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8cd812bc | 1564 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
1565 | i = rxq->read; |
1566 | ||
37d68317 | 1567 | if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2)) |
5c0eef96 | 1568 | fill_rx = 1; |
b481de9c ZY |
1569 | /* Rx interrupt, but nothing sent from uCode */ |
1570 | if (i == r) | |
e1623446 | 1571 | IWL_DEBUG(priv, IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i); |
b481de9c ZY |
1572 | |
1573 | while (i != r) { | |
1574 | rxb = rxq->queue[i]; | |
1575 | ||
9fbab516 | 1576 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
1577 | * then a bug has been introduced in the queue refilling |
1578 | * routines -- catch it here */ | |
1579 | BUG_ON(rxb == NULL); | |
1580 | ||
1581 | rxq->queue[i] = NULL; | |
1582 | ||
df833b1d RC |
1583 | pci_unmap_single(priv->pci_dev, rxb->real_dma_addr, |
1584 | priv->hw_params.rx_buf_size, | |
1585 | PCI_DMA_FROMDEVICE); | |
3d24a9f7 | 1586 | pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
1587 | |
1588 | /* Reclaim a command buffer only if this packet is a response | |
1589 | * to a (driver-originated) command. | |
1590 | * If the packet (e.g. Rx frame) originated from uCode, | |
1591 | * there is no command buffer to reclaim. | |
1592 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
1593 | * but apparently a few don't get set; catch them here. */ | |
1594 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
1595 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
1596 | (pkt->hdr.cmd != REPLY_TX); | |
1597 | ||
1598 | /* Based on type of command response or notification, | |
1599 | * handle those that need handling via function in | |
bb8c093b | 1600 | * rx_handlers table. See iwl3945_setup_rx_handlers() */ |
b481de9c | 1601 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 1602 | IWL_DEBUG(priv, IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR, |
b481de9c ZY |
1603 | "r = %d, i = %d, %s, 0x%02x\n", r, i, |
1604 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
1605 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); | |
86ddbf62 | 1606 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
b481de9c ZY |
1607 | } else { |
1608 | /* No handling needed */ | |
e1623446 | 1609 | IWL_DEBUG(priv, IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR, |
b481de9c ZY |
1610 | "r %d i %d No handler needed for %s, 0x%02x\n", |
1611 | r, i, get_cmd_string(pkt->hdr.cmd), | |
1612 | pkt->hdr.cmd); | |
1613 | } | |
1614 | ||
1615 | if (reclaim) { | |
9fbab516 | 1616 | /* Invoke any callbacks, transfer the skb to caller, and |
518099a8 | 1617 | * fire off the (possibly) blocking iwl_send_cmd() |
b481de9c ZY |
1618 | * as we reclaim the driver command queue */ |
1619 | if (rxb && rxb->skb) | |
732587ab | 1620 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 1621 | else |
39aadf8c | 1622 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
1623 | } |
1624 | ||
1625 | /* For now we just don't re-use anything. We can tweak this | |
1626 | * later to try and re-use notification packets and SKBs that | |
1627 | * fail to Rx correctly */ | |
1628 | if (rxb->skb != NULL) { | |
1629 | priv->alloc_rxb_skb--; | |
1630 | dev_kfree_skb_any(rxb->skb); | |
1631 | rxb->skb = NULL; | |
1632 | } | |
1633 | ||
b481de9c ZY |
1634 | spin_lock_irqsave(&rxq->lock, flags); |
1635 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
1636 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1637 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
1638 | /* If there are a lot of unused frames, |
1639 | * restock the Rx queue so ucode won't assert. */ | |
1640 | if (fill_rx) { | |
1641 | count++; | |
1642 | if (count >= 8) { | |
1643 | priv->rxq.read = i; | |
72240498 | 1644 | iwl3945_rx_queue_restock(priv); |
5c0eef96 MA |
1645 | count = 0; |
1646 | } | |
1647 | } | |
b481de9c ZY |
1648 | } |
1649 | ||
1650 | /* Backtrack one entry */ | |
1651 | priv->rxq.read = i; | |
bb8c093b | 1652 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
1653 | } |
1654 | ||
0359facc | 1655 | /* call this function to flush any scheduled tasklet */ |
4a8a4322 | 1656 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) |
0359facc | 1657 | { |
a96a27f9 | 1658 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
1659 | synchronize_irq(priv->pci_dev->irq); |
1660 | tasklet_kill(&priv->irq_tasklet); | |
1661 | } | |
1662 | ||
b481de9c ZY |
1663 | static const char *desc_lookup(int i) |
1664 | { | |
1665 | switch (i) { | |
1666 | case 1: | |
1667 | return "FAIL"; | |
1668 | case 2: | |
1669 | return "BAD_PARAM"; | |
1670 | case 3: | |
1671 | return "BAD_CHECKSUM"; | |
1672 | case 4: | |
1673 | return "NMI_INTERRUPT"; | |
1674 | case 5: | |
1675 | return "SYSASSERT"; | |
1676 | case 6: | |
1677 | return "FATAL_ERROR"; | |
1678 | } | |
1679 | ||
1680 | return "UNKNOWN"; | |
1681 | } | |
1682 | ||
1683 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1684 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1685 | ||
4a8a4322 | 1686 | static void iwl3945_dump_nic_error_log(struct iwl_priv *priv) |
b481de9c ZY |
1687 | { |
1688 | u32 i; | |
1689 | u32 desc, time, count, base, data1; | |
1690 | u32 blink1, blink2, ilink1, ilink2; | |
1691 | int rc; | |
1692 | ||
1693 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
1694 | ||
bb8c093b | 1695 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 1696 | IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base); |
b481de9c ZY |
1697 | return; |
1698 | } | |
1699 | ||
5d49f498 | 1700 | rc = iwl_grab_nic_access(priv); |
b481de9c | 1701 | if (rc) { |
39aadf8c | 1702 | IWL_WARN(priv, "Can not read from adapter at this time.\n"); |
b481de9c ZY |
1703 | return; |
1704 | } | |
1705 | ||
5d49f498 | 1706 | count = iwl_read_targ_mem(priv, base); |
b481de9c ZY |
1707 | |
1708 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
15b1687c WT |
1709 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); |
1710 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
1711 | priv->status, count); | |
b481de9c ZY |
1712 | } |
1713 | ||
15b1687c | 1714 | IWL_ERR(priv, "Desc Time asrtPC blink2 " |
b481de9c ZY |
1715 | "ilink1 nmiPC Line\n"); |
1716 | for (i = ERROR_START_OFFSET; | |
1717 | i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET; | |
1718 | i += ERROR_ELEM_SIZE) { | |
5d49f498 | 1719 | desc = iwl_read_targ_mem(priv, base + i); |
b481de9c | 1720 | time = |
5d49f498 | 1721 | iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32)); |
b481de9c | 1722 | blink1 = |
5d49f498 | 1723 | iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32)); |
b481de9c | 1724 | blink2 = |
5d49f498 | 1725 | iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32)); |
b481de9c | 1726 | ilink1 = |
5d49f498 | 1727 | iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32)); |
b481de9c | 1728 | ilink2 = |
5d49f498 | 1729 | iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32)); |
b481de9c | 1730 | data1 = |
5d49f498 | 1731 | iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32)); |
b481de9c | 1732 | |
15b1687c WT |
1733 | IWL_ERR(priv, |
1734 | "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n", | |
1735 | desc_lookup(desc), desc, time, blink1, blink2, | |
1736 | ilink1, ilink2, data1); | |
b481de9c ZY |
1737 | } |
1738 | ||
5d49f498 | 1739 | iwl_release_nic_access(priv); |
b481de9c ZY |
1740 | |
1741 | } | |
1742 | ||
f58177b9 | 1743 | #define EVENT_START_OFFSET (6 * sizeof(u32)) |
b481de9c ZY |
1744 | |
1745 | /** | |
bb8c093b | 1746 | * iwl3945_print_event_log - Dump error event log to syslog |
b481de9c | 1747 | * |
5d49f498 | 1748 | * NOTE: Must be called with iwl_grab_nic_access() already obtained! |
b481de9c | 1749 | */ |
4a8a4322 | 1750 | static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx, |
b481de9c ZY |
1751 | u32 num_events, u32 mode) |
1752 | { | |
1753 | u32 i; | |
1754 | u32 base; /* SRAM byte address of event log header */ | |
1755 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1756 | u32 ptr; /* SRAM byte address of log data */ | |
1757 | u32 ev, time, data; /* event log data */ | |
1758 | ||
1759 | if (num_events == 0) | |
1760 | return; | |
1761 | ||
1762 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
1763 | ||
1764 | if (mode == 0) | |
1765 | event_size = 2 * sizeof(u32); | |
1766 | else | |
1767 | event_size = 3 * sizeof(u32); | |
1768 | ||
1769 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1770 | ||
1771 | /* "time" is actually "data" for mode 0 (no timestamp). | |
1772 | * place event id # at far right for easier visual parsing. */ | |
1773 | for (i = 0; i < num_events; i++) { | |
5d49f498 | 1774 | ev = iwl_read_targ_mem(priv, ptr); |
b481de9c | 1775 | ptr += sizeof(u32); |
5d49f498 | 1776 | time = iwl_read_targ_mem(priv, ptr); |
b481de9c | 1777 | ptr += sizeof(u32); |
15b1687c WT |
1778 | if (mode == 0) { |
1779 | /* data, ev */ | |
1780 | IWL_ERR(priv, "0x%08x\t%04u\n", time, ev); | |
1781 | } else { | |
5d49f498 | 1782 | data = iwl_read_targ_mem(priv, ptr); |
b481de9c | 1783 | ptr += sizeof(u32); |
15b1687c | 1784 | IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev); |
b481de9c ZY |
1785 | } |
1786 | } | |
1787 | } | |
1788 | ||
4a8a4322 | 1789 | static void iwl3945_dump_nic_event_log(struct iwl_priv *priv) |
b481de9c ZY |
1790 | { |
1791 | int rc; | |
1792 | u32 base; /* SRAM byte address of event log header */ | |
1793 | u32 capacity; /* event log capacity in # entries */ | |
1794 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
1795 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
1796 | u32 next_entry; /* index of next entry to be written by uCode */ | |
1797 | u32 size; /* # entries that we'll print */ | |
1798 | ||
1799 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
bb8c093b | 1800 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 1801 | IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); |
b481de9c ZY |
1802 | return; |
1803 | } | |
1804 | ||
5d49f498 | 1805 | rc = iwl_grab_nic_access(priv); |
b481de9c | 1806 | if (rc) { |
39aadf8c | 1807 | IWL_WARN(priv, "Can not read from adapter at this time.\n"); |
b481de9c ZY |
1808 | return; |
1809 | } | |
1810 | ||
1811 | /* event log header */ | |
5d49f498 AK |
1812 | capacity = iwl_read_targ_mem(priv, base); |
1813 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
1814 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
1815 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
b481de9c ZY |
1816 | |
1817 | size = num_wraps ? capacity : next_entry; | |
1818 | ||
1819 | /* bail out if nothing in log */ | |
1820 | if (size == 0) { | |
15b1687c | 1821 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); |
5d49f498 | 1822 | iwl_release_nic_access(priv); |
b481de9c ZY |
1823 | return; |
1824 | } | |
1825 | ||
15b1687c | 1826 | IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n", |
b481de9c ZY |
1827 | size, num_wraps); |
1828 | ||
1829 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
1830 | * i.e the next one that uCode would fill. */ | |
1831 | if (num_wraps) | |
bb8c093b | 1832 | iwl3945_print_event_log(priv, next_entry, |
b481de9c ZY |
1833 | capacity - next_entry, mode); |
1834 | ||
1835 | /* (then/else) start at top of log */ | |
bb8c093b | 1836 | iwl3945_print_event_log(priv, 0, next_entry, mode); |
b481de9c | 1837 | |
5d49f498 | 1838 | iwl_release_nic_access(priv); |
b481de9c ZY |
1839 | } |
1840 | ||
4a8a4322 | 1841 | static void iwl3945_error_recovery(struct iwl_priv *priv) |
b481de9c ZY |
1842 | { |
1843 | unsigned long flags; | |
1844 | ||
8ccde88a SO |
1845 | memcpy(&priv->staging_rxon, &priv->recovery_rxon, |
1846 | sizeof(priv->staging_rxon)); | |
1847 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 1848 | iwlcore_commit_rxon(priv); |
b481de9c | 1849 | |
06fd3d86 | 1850 | priv->cfg->ops->smgmt->add_station(priv, priv->bssid, 1, 0, NULL); |
b481de9c ZY |
1851 | |
1852 | spin_lock_irqsave(&priv->lock, flags); | |
8ccde88a | 1853 | priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id); |
b481de9c ZY |
1854 | priv->error_recovering = 0; |
1855 | spin_unlock_irqrestore(&priv->lock, flags); | |
1856 | } | |
1857 | ||
4a8a4322 | 1858 | static void iwl3945_irq_tasklet(struct iwl_priv *priv) |
b481de9c ZY |
1859 | { |
1860 | u32 inta, handled = 0; | |
1861 | u32 inta_fh; | |
1862 | unsigned long flags; | |
d08853a3 | 1863 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
1864 | u32 inta_mask; |
1865 | #endif | |
1866 | ||
1867 | spin_lock_irqsave(&priv->lock, flags); | |
1868 | ||
1869 | /* Ack/clear/reset pending uCode interrupts. | |
1870 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1871 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
5d49f498 AK |
1872 | inta = iwl_read32(priv, CSR_INT); |
1873 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
1874 | |
1875 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1876 | * Any new interrupts that happen after this, either while we're | |
1877 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
5d49f498 AK |
1878 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1879 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 1880 | |
d08853a3 | 1881 | #ifdef CONFIG_IWLWIFI_DEBUG |
40b8ec0b | 1882 | if (priv->debug_level & IWL_DL_ISR) { |
9fbab516 | 1883 | /* just for debug */ |
5d49f498 | 1884 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 1885 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
1886 | inta, inta_mask, inta_fh); |
1887 | } | |
1888 | #endif | |
1889 | ||
1890 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
1891 | * atomic, make sure that inta covers all the interrupts that | |
1892 | * we've discovered, even if FH interrupt came in just after | |
1893 | * reading CSR_INT. */ | |
6f83eaa1 | 1894 | if (inta_fh & CSR39_FH_INT_RX_MASK) |
b481de9c | 1895 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 1896 | if (inta_fh & CSR39_FH_INT_TX_MASK) |
b481de9c ZY |
1897 | inta |= CSR_INT_BIT_FH_TX; |
1898 | ||
1899 | /* Now service all interrupt bits discovered above. */ | |
1900 | if (inta & CSR_INT_BIT_HW_ERR) { | |
15b1687c | 1901 | IWL_ERR(priv, "Microcode HW error detected. Restarting.\n"); |
b481de9c ZY |
1902 | |
1903 | /* Tell the device to stop sending interrupts */ | |
ed3b932e | 1904 | iwl_disable_interrupts(priv); |
b481de9c | 1905 | |
86ddbf62 | 1906 | priv->isr_stats.hw++; |
8ccde88a | 1907 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1908 | |
1909 | handled |= CSR_INT_BIT_HW_ERR; | |
1910 | ||
1911 | spin_unlock_irqrestore(&priv->lock, flags); | |
1912 | ||
1913 | return; | |
1914 | } | |
1915 | ||
d08853a3 | 1916 | #ifdef CONFIG_IWLWIFI_DEBUG |
40b8ec0b | 1917 | if (priv->debug_level & (IWL_DL_ISR)) { |
b481de9c | 1918 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
86ddbf62 | 1919 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 1920 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 1921 | "the frame/frames.\n"); |
86ddbf62 AK |
1922 | priv->isr_stats.sch++; |
1923 | } | |
b481de9c ZY |
1924 | |
1925 | /* Alive notification via Rx interrupt will do the real work */ | |
86ddbf62 | 1926 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 1927 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
86ddbf62 AK |
1928 | priv->isr_stats.alive++; |
1929 | } | |
b481de9c ZY |
1930 | } |
1931 | #endif | |
1932 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1933 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1934 | |
b481de9c ZY |
1935 | /* Error detected by uCode */ |
1936 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1937 | IWL_ERR(priv, "Microcode SW error detected. " |
1938 | "Restarting 0x%X.\n", inta); | |
86ddbf62 AK |
1939 | priv->isr_stats.sw++; |
1940 | priv->isr_stats.sw_err = inta; | |
8ccde88a | 1941 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1942 | handled |= CSR_INT_BIT_SW_ERR; |
1943 | } | |
1944 | ||
1945 | /* uCode wakes up after power-down sleep */ | |
1946 | if (inta & CSR_INT_BIT_WAKEUP) { | |
e1623446 | 1947 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
141c43a3 | 1948 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
4f3602c8 SO |
1949 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); |
1950 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1951 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1952 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1953 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1954 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c | 1955 | |
86ddbf62 | 1956 | priv->isr_stats.wakeup++; |
b481de9c ZY |
1957 | handled |= CSR_INT_BIT_WAKEUP; |
1958 | } | |
1959 | ||
1960 | /* All uCode command responses, including Tx command responses, | |
1961 | * Rx "responses" (frame-received notification), and other | |
1962 | * notifications from uCode come through here*/ | |
1963 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
bb8c093b | 1964 | iwl3945_rx_handle(priv); |
86ddbf62 | 1965 | priv->isr_stats.rx++; |
b481de9c ZY |
1966 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1967 | } | |
1968 | ||
1969 | if (inta & CSR_INT_BIT_FH_TX) { | |
e1623446 | 1970 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); |
86ddbf62 | 1971 | priv->isr_stats.tx++; |
b481de9c | 1972 | |
5d49f498 AK |
1973 | iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); |
1974 | if (!iwl_grab_nic_access(priv)) { | |
1975 | iwl_write_direct32(priv, FH39_TCSR_CREDIT | |
bddadf86 | 1976 | (FH39_SRVC_CHNL), 0x0); |
5d49f498 | 1977 | iwl_release_nic_access(priv); |
b481de9c ZY |
1978 | } |
1979 | handled |= CSR_INT_BIT_FH_TX; | |
1980 | } | |
1981 | ||
86ddbf62 | 1982 | if (inta & ~handled) { |
15b1687c | 1983 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
86ddbf62 AK |
1984 | priv->isr_stats.unhandled++; |
1985 | } | |
b481de9c ZY |
1986 | |
1987 | if (inta & ~CSR_INI_SET_MASK) { | |
39aadf8c | 1988 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
b481de9c | 1989 | inta & ~CSR_INI_SET_MASK); |
39aadf8c | 1990 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1991 | } |
1992 | ||
1993 | /* Re-enable all interrupts */ | |
0359facc MA |
1994 | /* only Re-enable if disabled by irq */ |
1995 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
ed3b932e | 1996 | iwl_enable_interrupts(priv); |
b481de9c | 1997 | |
d08853a3 | 1998 | #ifdef CONFIG_IWLWIFI_DEBUG |
40b8ec0b | 1999 | if (priv->debug_level & (IWL_DL_ISR)) { |
5d49f498 AK |
2000 | inta = iwl_read32(priv, CSR_INT); |
2001 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
2002 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 2003 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
2004 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
2005 | } | |
2006 | #endif | |
2007 | spin_unlock_irqrestore(&priv->lock, flags); | |
2008 | } | |
2009 | ||
4a8a4322 | 2010 | static int iwl3945_get_channels_for_scan(struct iwl_priv *priv, |
8318d78a | 2011 | enum ieee80211_band band, |
f9340520 | 2012 | u8 is_active, u8 n_probes, |
bb8c093b | 2013 | struct iwl3945_scan_channel *scan_ch) |
b481de9c ZY |
2014 | { |
2015 | const struct ieee80211_channel *channels = NULL; | |
8318d78a | 2016 | const struct ieee80211_supported_band *sband; |
d20b3c65 | 2017 | const struct iwl_channel_info *ch_info; |
b481de9c ZY |
2018 | u16 passive_dwell = 0; |
2019 | u16 active_dwell = 0; | |
2020 | int added, i; | |
2021 | ||
cbba18c6 | 2022 | sband = iwl_get_hw_mode(priv, band); |
8318d78a | 2023 | if (!sband) |
b481de9c ZY |
2024 | return 0; |
2025 | ||
8318d78a | 2026 | channels = sband->channels; |
b481de9c | 2027 | |
77fecfb8 SO |
2028 | active_dwell = iwl_get_active_dwell_time(priv, band, n_probes); |
2029 | passive_dwell = iwl_get_passive_dwell_time(priv, band); | |
b481de9c | 2030 | |
8f4807a1 AK |
2031 | if (passive_dwell <= active_dwell) |
2032 | passive_dwell = active_dwell + 1; | |
2033 | ||
8318d78a | 2034 | for (i = 0, added = 0; i < sband->n_channels; i++) { |
182e2e66 JB |
2035 | if (channels[i].flags & IEEE80211_CHAN_DISABLED) |
2036 | continue; | |
2037 | ||
8318d78a | 2038 | scan_ch->channel = channels[i].hw_value; |
b481de9c | 2039 | |
e6148917 | 2040 | ch_info = iwl_get_channel_info(priv, band, scan_ch->channel); |
b481de9c | 2041 | if (!is_channel_valid(ch_info)) { |
e1623446 | 2042 | IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n", |
b481de9c ZY |
2043 | scan_ch->channel); |
2044 | continue; | |
2045 | } | |
2046 | ||
011a0330 AK |
2047 | scan_ch->active_dwell = cpu_to_le16(active_dwell); |
2048 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
2049 | /* If passive , set up for auto-switch | |
2050 | * and use long active_dwell time. | |
2051 | */ | |
b481de9c | 2052 | if (!is_active || is_channel_passive(ch_info) || |
011a0330 | 2053 | (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) { |
b481de9c | 2054 | scan_ch->type = 0; /* passive */ |
011a0330 AK |
2055 | if (IWL_UCODE_API(priv->ucode_ver) == 1) |
2056 | scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1); | |
2057 | } else { | |
b481de9c | 2058 | scan_ch->type = 1; /* active */ |
011a0330 | 2059 | } |
b481de9c | 2060 | |
011a0330 AK |
2061 | /* Set direct probe bits. These may be used both for active |
2062 | * scan channels (probes gets sent right away), | |
2063 | * or for passive channels (probes get se sent only after | |
2064 | * hearing clear Rx packet).*/ | |
2065 | if (IWL_UCODE_API(priv->ucode_ver) >= 2) { | |
2066 | if (n_probes) | |
0d21044e | 2067 | scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes); |
011a0330 AK |
2068 | } else { |
2069 | /* uCode v1 does not allow setting direct probe bits on | |
2070 | * passive channel. */ | |
2071 | if ((scan_ch->type & 1) && n_probes) | |
0d21044e | 2072 | scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes); |
011a0330 | 2073 | } |
b481de9c | 2074 | |
9fbab516 | 2075 | /* Set txpower levels to defaults */ |
b481de9c ZY |
2076 | scan_ch->tpc.dsp_atten = 110; |
2077 | /* scan_pwr_info->tpc.dsp_atten; */ | |
2078 | ||
2079 | /*scan_pwr_info->tpc.tx_gain; */ | |
8318d78a | 2080 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
2081 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; |
2082 | else { | |
2083 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
2084 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
9fbab516 | 2085 | * power level: |
8a1b0245 | 2086 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; |
b481de9c ZY |
2087 | */ |
2088 | } | |
2089 | ||
e1623446 | 2090 | IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n", |
b481de9c ZY |
2091 | scan_ch->channel, |
2092 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
2093 | (scan_ch->type & 1) ? | |
2094 | active_dwell : passive_dwell); | |
2095 | ||
2096 | scan_ch++; | |
2097 | added++; | |
2098 | } | |
2099 | ||
e1623446 | 2100 | IWL_DEBUG_SCAN(priv, "total channels to scan %d \n", added); |
b481de9c ZY |
2101 | return added; |
2102 | } | |
2103 | ||
4a8a4322 | 2104 | static void iwl3945_init_hw_rates(struct iwl_priv *priv, |
b481de9c ZY |
2105 | struct ieee80211_rate *rates) |
2106 | { | |
2107 | int i; | |
2108 | ||
2109 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
8318d78a JB |
2110 | rates[i].bitrate = iwl3945_rates[i].ieee * 5; |
2111 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
2112 | rates[i].hw_value_short = i; | |
2113 | rates[i].flags = 0; | |
d9829a67 | 2114 | if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { |
b481de9c | 2115 | /* |
8318d78a | 2116 | * If CCK != 1M then set short preamble rate flag. |
b481de9c | 2117 | */ |
bb8c093b | 2118 | rates[i].flags |= (iwl3945_rates[i].plcp == 10) ? |
8318d78a | 2119 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
b481de9c | 2120 | } |
b481de9c ZY |
2121 | } |
2122 | } | |
2123 | ||
b481de9c ZY |
2124 | /****************************************************************************** |
2125 | * | |
2126 | * uCode download functions | |
2127 | * | |
2128 | ******************************************************************************/ | |
2129 | ||
4a8a4322 | 2130 | static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 2131 | { |
98c92211 TW |
2132 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
2133 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
2134 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
2135 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
2136 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
2137 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
2138 | } |
2139 | ||
2140 | /** | |
bb8c093b | 2141 | * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host, |
b481de9c ZY |
2142 | * looking at all data. |
2143 | */ | |
4a8a4322 | 2144 | static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
2145 | { |
2146 | u32 val; | |
2147 | u32 save_len = len; | |
2148 | int rc = 0; | |
2149 | u32 errcnt; | |
2150 | ||
e1623446 | 2151 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b481de9c | 2152 | |
5d49f498 | 2153 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
2154 | if (rc) |
2155 | return rc; | |
2156 | ||
5d49f498 | 2157 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 2158 | IWL39_RTC_INST_LOWER_BOUND); |
b481de9c ZY |
2159 | |
2160 | errcnt = 0; | |
2161 | for (; len > 0; len -= sizeof(u32), image++) { | |
2162 | /* read data comes through single port, auto-incr addr */ | |
2163 | /* NOTE: Use the debugless read so we don't flood kernel log | |
2164 | * if IWL_DL_IO is set */ | |
5d49f498 | 2165 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c | 2166 | if (val != le32_to_cpu(*image)) { |
15b1687c | 2167 | IWL_ERR(priv, "uCode INST section is invalid at " |
b481de9c ZY |
2168 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
2169 | save_len - len, val, le32_to_cpu(*image)); | |
2170 | rc = -EIO; | |
2171 | errcnt++; | |
2172 | if (errcnt >= 20) | |
2173 | break; | |
2174 | } | |
2175 | } | |
2176 | ||
5d49f498 | 2177 | iwl_release_nic_access(priv); |
b481de9c ZY |
2178 | |
2179 | if (!errcnt) | |
e1623446 TW |
2180 | IWL_DEBUG_INFO(priv, |
2181 | "ucode image in INSTRUCTION memory is good\n"); | |
b481de9c ZY |
2182 | |
2183 | return rc; | |
2184 | } | |
2185 | ||
2186 | ||
2187 | /** | |
bb8c093b | 2188 | * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host, |
b481de9c ZY |
2189 | * using sample data 100 bytes apart. If these sample points are good, |
2190 | * it's a pretty good bet that everything between them is good, too. | |
2191 | */ | |
4a8a4322 | 2192 | static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
2193 | { |
2194 | u32 val; | |
2195 | int rc = 0; | |
2196 | u32 errcnt = 0; | |
2197 | u32 i; | |
2198 | ||
e1623446 | 2199 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b481de9c | 2200 | |
5d49f498 | 2201 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
2202 | if (rc) |
2203 | return rc; | |
2204 | ||
2205 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
2206 | /* read data comes through single port, auto-incr addr */ | |
2207 | /* NOTE: Use the debugless read so we don't flood kernel log | |
2208 | * if IWL_DL_IO is set */ | |
5d49f498 | 2209 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 2210 | i + IWL39_RTC_INST_LOWER_BOUND); |
5d49f498 | 2211 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
2212 | if (val != le32_to_cpu(*image)) { |
2213 | #if 0 /* Enable this if you want to see details */ | |
15b1687c | 2214 | IWL_ERR(priv, "uCode INST section is invalid at " |
b481de9c ZY |
2215 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
2216 | i, val, *image); | |
2217 | #endif | |
2218 | rc = -EIO; | |
2219 | errcnt++; | |
2220 | if (errcnt >= 3) | |
2221 | break; | |
2222 | } | |
2223 | } | |
2224 | ||
5d49f498 | 2225 | iwl_release_nic_access(priv); |
b481de9c ZY |
2226 | |
2227 | return rc; | |
2228 | } | |
2229 | ||
2230 | ||
2231 | /** | |
bb8c093b | 2232 | * iwl3945_verify_ucode - determine which instruction image is in SRAM, |
b481de9c ZY |
2233 | * and verify its contents |
2234 | */ | |
4a8a4322 | 2235 | static int iwl3945_verify_ucode(struct iwl_priv *priv) |
b481de9c ZY |
2236 | { |
2237 | __le32 *image; | |
2238 | u32 len; | |
2239 | int rc = 0; | |
2240 | ||
2241 | /* Try bootstrap */ | |
2242 | image = (__le32 *)priv->ucode_boot.v_addr; | |
2243 | len = priv->ucode_boot.len; | |
bb8c093b | 2244 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2245 | if (rc == 0) { |
e1623446 | 2246 | IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n"); |
b481de9c ZY |
2247 | return 0; |
2248 | } | |
2249 | ||
2250 | /* Try initialize */ | |
2251 | image = (__le32 *)priv->ucode_init.v_addr; | |
2252 | len = priv->ucode_init.len; | |
bb8c093b | 2253 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2254 | if (rc == 0) { |
e1623446 | 2255 | IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n"); |
b481de9c ZY |
2256 | return 0; |
2257 | } | |
2258 | ||
2259 | /* Try runtime/protocol */ | |
2260 | image = (__le32 *)priv->ucode_code.v_addr; | |
2261 | len = priv->ucode_code.len; | |
bb8c093b | 2262 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2263 | if (rc == 0) { |
e1623446 | 2264 | IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n"); |
b481de9c ZY |
2265 | return 0; |
2266 | } | |
2267 | ||
15b1687c | 2268 | IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); |
b481de9c | 2269 | |
9fbab516 BC |
2270 | /* Since nothing seems to match, show first several data entries in |
2271 | * instruction SRAM, so maybe visual inspection will give a clue. | |
2272 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
b481de9c ZY |
2273 | image = (__le32 *)priv->ucode_boot.v_addr; |
2274 | len = priv->ucode_boot.len; | |
bb8c093b | 2275 | rc = iwl3945_verify_inst_full(priv, image, len); |
b481de9c ZY |
2276 | |
2277 | return rc; | |
2278 | } | |
2279 | ||
4a8a4322 | 2280 | static void iwl3945_nic_start(struct iwl_priv *priv) |
b481de9c ZY |
2281 | { |
2282 | /* Remove all resets to allow NIC to operate */ | |
5d49f498 | 2283 | iwl_write32(priv, CSR_RESET, 0); |
b481de9c ZY |
2284 | } |
2285 | ||
2286 | /** | |
bb8c093b | 2287 | * iwl3945_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
2288 | * |
2289 | * Copy into buffers for card to fetch via bus-mastering | |
2290 | */ | |
4a8a4322 | 2291 | static int iwl3945_read_ucode(struct iwl_priv *priv) |
b481de9c | 2292 | { |
a78fe754 | 2293 | struct iwl_ucode *ucode; |
a0987a8d | 2294 | int ret = -EINVAL, index; |
b481de9c ZY |
2295 | const struct firmware *ucode_raw; |
2296 | /* firmware file name contains uCode/driver compatibility version */ | |
a0987a8d RC |
2297 | const char *name_pre = priv->cfg->fw_name_pre; |
2298 | const unsigned int api_max = priv->cfg->ucode_api_max; | |
2299 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
2300 | char buf[25]; | |
b481de9c ZY |
2301 | u8 *src; |
2302 | size_t len; | |
a0987a8d | 2303 | u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size; |
b481de9c ZY |
2304 | |
2305 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
2306 | * request_firmware() is synchronous, file is in memory on return. */ | |
a0987a8d RC |
2307 | for (index = api_max; index >= api_min; index--) { |
2308 | sprintf(buf, "%s%u%s", name_pre, index, ".ucode"); | |
2309 | ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); | |
2310 | if (ret < 0) { | |
15b1687c | 2311 | IWL_ERR(priv, "%s firmware file req failed: %d\n", |
a0987a8d RC |
2312 | buf, ret); |
2313 | if (ret == -ENOENT) | |
2314 | continue; | |
2315 | else | |
2316 | goto error; | |
2317 | } else { | |
2318 | if (index < api_max) | |
15b1687c WT |
2319 | IWL_ERR(priv, "Loaded firmware %s, " |
2320 | "which is deprecated. " | |
2321 | " Please use API v%u instead.\n", | |
a0987a8d | 2322 | buf, api_max); |
e1623446 TW |
2323 | IWL_DEBUG_INFO(priv, "Got firmware '%s' file " |
2324 | "(%zd bytes) from disk\n", | |
a0987a8d RC |
2325 | buf, ucode_raw->size); |
2326 | break; | |
2327 | } | |
b481de9c ZY |
2328 | } |
2329 | ||
a0987a8d RC |
2330 | if (ret < 0) |
2331 | goto error; | |
b481de9c ZY |
2332 | |
2333 | /* Make sure that we got at least our header! */ | |
2334 | if (ucode_raw->size < sizeof(*ucode)) { | |
15b1687c | 2335 | IWL_ERR(priv, "File size way too small!\n"); |
90e759d1 | 2336 | ret = -EINVAL; |
b481de9c ZY |
2337 | goto err_release; |
2338 | } | |
2339 | ||
2340 | /* Data from ucode file: header followed by uCode images */ | |
2341 | ucode = (void *)ucode_raw->data; | |
2342 | ||
c02b3acd | 2343 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 2344 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
b481de9c ZY |
2345 | inst_size = le32_to_cpu(ucode->inst_size); |
2346 | data_size = le32_to_cpu(ucode->data_size); | |
2347 | init_size = le32_to_cpu(ucode->init_size); | |
2348 | init_data_size = le32_to_cpu(ucode->init_data_size); | |
2349 | boot_size = le32_to_cpu(ucode->boot_size); | |
2350 | ||
a0987a8d RC |
2351 | /* api_ver should match the api version forming part of the |
2352 | * firmware filename ... but we don't check for that and only rely | |
877d0310 | 2353 | * on the API version read from firmware header from here on forward */ |
a0987a8d RC |
2354 | |
2355 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 2356 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
2357 | "Driver supports v%u, firmware is v%u.\n", |
2358 | api_max, api_ver); | |
2359 | priv->ucode_ver = 0; | |
2360 | ret = -EINVAL; | |
2361 | goto err_release; | |
2362 | } | |
2363 | if (api_ver != api_max) | |
15b1687c | 2364 | IWL_ERR(priv, "Firmware has old API version. Expected %u, " |
a0987a8d RC |
2365 | "got %u. New firmware can be obtained " |
2366 | "from http://www.intellinuxwireless.org.\n", | |
2367 | api_max, api_ver); | |
2368 | ||
978785a3 TW |
2369 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
2370 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
2371 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2372 | IWL_UCODE_API(priv->ucode_ver), | |
2373 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
2374 | ||
e1623446 | 2375 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
a0987a8d | 2376 | priv->ucode_ver); |
e1623446 TW |
2377 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n", |
2378 | inst_size); | |
2379 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n", | |
2380 | data_size); | |
2381 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n", | |
2382 | init_size); | |
2383 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n", | |
2384 | init_data_size); | |
2385 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n", | |
2386 | boot_size); | |
b481de9c | 2387 | |
a0987a8d | 2388 | |
b481de9c ZY |
2389 | /* Verify size of file vs. image size info in file's header */ |
2390 | if (ucode_raw->size < sizeof(*ucode) + | |
2391 | inst_size + data_size + init_size + | |
2392 | init_data_size + boot_size) { | |
2393 | ||
e1623446 TW |
2394 | IWL_DEBUG_INFO(priv, "uCode file size %zd too small\n", |
2395 | ucode_raw->size); | |
90e759d1 | 2396 | ret = -EINVAL; |
b481de9c ZY |
2397 | goto err_release; |
2398 | } | |
2399 | ||
2400 | /* Verify that uCode images will fit in card's SRAM */ | |
250bdd21 | 2401 | if (inst_size > IWL39_MAX_INST_SIZE) { |
e1623446 | 2402 | IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n", |
90e759d1 TW |
2403 | inst_size); |
2404 | ret = -EINVAL; | |
b481de9c ZY |
2405 | goto err_release; |
2406 | } | |
2407 | ||
250bdd21 | 2408 | if (data_size > IWL39_MAX_DATA_SIZE) { |
e1623446 | 2409 | IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n", |
90e759d1 TW |
2410 | data_size); |
2411 | ret = -EINVAL; | |
b481de9c ZY |
2412 | goto err_release; |
2413 | } | |
250bdd21 | 2414 | if (init_size > IWL39_MAX_INST_SIZE) { |
e1623446 TW |
2415 | IWL_DEBUG_INFO(priv, |
2416 | "uCode init instr len %d too large to fit in\n", | |
90e759d1 TW |
2417 | init_size); |
2418 | ret = -EINVAL; | |
b481de9c ZY |
2419 | goto err_release; |
2420 | } | |
250bdd21 | 2421 | if (init_data_size > IWL39_MAX_DATA_SIZE) { |
e1623446 TW |
2422 | IWL_DEBUG_INFO(priv, |
2423 | "uCode init data len %d too large to fit in\n", | |
90e759d1 TW |
2424 | init_data_size); |
2425 | ret = -EINVAL; | |
b481de9c ZY |
2426 | goto err_release; |
2427 | } | |
250bdd21 | 2428 | if (boot_size > IWL39_MAX_BSM_SIZE) { |
e1623446 TW |
2429 | IWL_DEBUG_INFO(priv, |
2430 | "uCode boot instr len %d too large to fit in\n", | |
90e759d1 TW |
2431 | boot_size); |
2432 | ret = -EINVAL; | |
b481de9c ZY |
2433 | goto err_release; |
2434 | } | |
2435 | ||
2436 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
2437 | ||
2438 | /* Runtime instructions and 2 copies of data: | |
2439 | * 1) unmodified from disk | |
2440 | * 2) backup cache for save/restore during power-downs */ | |
2441 | priv->ucode_code.len = inst_size; | |
98c92211 | 2442 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
2443 | |
2444 | priv->ucode_data.len = data_size; | |
98c92211 | 2445 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
2446 | |
2447 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 2448 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 2449 | |
90e759d1 TW |
2450 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
2451 | !priv->ucode_data_backup.v_addr) | |
2452 | goto err_pci_alloc; | |
b481de9c ZY |
2453 | |
2454 | /* Initialization instructions and data */ | |
90e759d1 TW |
2455 | if (init_size && init_data_size) { |
2456 | priv->ucode_init.len = init_size; | |
98c92211 | 2457 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
2458 | |
2459 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 2460 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
2461 | |
2462 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
2463 | goto err_pci_alloc; | |
2464 | } | |
b481de9c ZY |
2465 | |
2466 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
2467 | if (boot_size) { |
2468 | priv->ucode_boot.len = boot_size; | |
98c92211 | 2469 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 2470 | |
90e759d1 TW |
2471 | if (!priv->ucode_boot.v_addr) |
2472 | goto err_pci_alloc; | |
2473 | } | |
b481de9c ZY |
2474 | |
2475 | /* Copy images into buffers for card's bus-master reads ... */ | |
2476 | ||
2477 | /* Runtime instructions (first block of data in file) */ | |
2478 | src = &ucode->data[0]; | |
2479 | len = priv->ucode_code.len; | |
e1623446 TW |
2480 | IWL_DEBUG_INFO(priv, |
2481 | "Copying (but not loading) uCode instr len %zd\n", len); | |
b481de9c | 2482 | memcpy(priv->ucode_code.v_addr, src, len); |
e1623446 | 2483 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
2484 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
2485 | ||
2486 | /* Runtime data (2nd block) | |
bb8c093b | 2487 | * NOTE: Copy into backup buffer will be done in iwl3945_up() */ |
b481de9c ZY |
2488 | src = &ucode->data[inst_size]; |
2489 | len = priv->ucode_data.len; | |
e1623446 TW |
2490 | IWL_DEBUG_INFO(priv, |
2491 | "Copying (but not loading) uCode data len %zd\n", len); | |
b481de9c ZY |
2492 | memcpy(priv->ucode_data.v_addr, src, len); |
2493 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
2494 | ||
2495 | /* Initialization instructions (3rd block) */ | |
2496 | if (init_size) { | |
2497 | src = &ucode->data[inst_size + data_size]; | |
2498 | len = priv->ucode_init.len; | |
e1623446 TW |
2499 | IWL_DEBUG_INFO(priv, |
2500 | "Copying (but not loading) init instr len %zd\n", len); | |
b481de9c ZY |
2501 | memcpy(priv->ucode_init.v_addr, src, len); |
2502 | } | |
2503 | ||
2504 | /* Initialization data (4th block) */ | |
2505 | if (init_data_size) { | |
2506 | src = &ucode->data[inst_size + data_size + init_size]; | |
2507 | len = priv->ucode_init_data.len; | |
e1623446 TW |
2508 | IWL_DEBUG_INFO(priv, |
2509 | "Copying (but not loading) init data len %zd\n", len); | |
b481de9c ZY |
2510 | memcpy(priv->ucode_init_data.v_addr, src, len); |
2511 | } | |
2512 | ||
2513 | /* Bootstrap instructions (5th block) */ | |
2514 | src = &ucode->data[inst_size + data_size + init_size + init_data_size]; | |
2515 | len = priv->ucode_boot.len; | |
e1623446 TW |
2516 | IWL_DEBUG_INFO(priv, |
2517 | "Copying (but not loading) boot instr len %zd\n", len); | |
b481de9c ZY |
2518 | memcpy(priv->ucode_boot.v_addr, src, len); |
2519 | ||
2520 | /* We have our copies now, allow OS release its copies */ | |
2521 | release_firmware(ucode_raw); | |
2522 | return 0; | |
2523 | ||
2524 | err_pci_alloc: | |
15b1687c | 2525 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
90e759d1 | 2526 | ret = -ENOMEM; |
bb8c093b | 2527 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
2528 | |
2529 | err_release: | |
2530 | release_firmware(ucode_raw); | |
2531 | ||
2532 | error: | |
90e759d1 | 2533 | return ret; |
b481de9c ZY |
2534 | } |
2535 | ||
2536 | ||
2537 | /** | |
bb8c093b | 2538 | * iwl3945_set_ucode_ptrs - Set uCode address location |
b481de9c ZY |
2539 | * |
2540 | * Tell initialization uCode where to find runtime uCode. | |
2541 | * | |
2542 | * BSM registers initially contain pointers to initialization uCode. | |
2543 | * We need to replace them to load runtime uCode inst and data, | |
2544 | * and to save runtime data when powering down. | |
2545 | */ | |
4a8a4322 | 2546 | static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv) |
b481de9c ZY |
2547 | { |
2548 | dma_addr_t pinst; | |
2549 | dma_addr_t pdata; | |
2550 | int rc = 0; | |
2551 | unsigned long flags; | |
2552 | ||
2553 | /* bits 31:0 for 3945 */ | |
2554 | pinst = priv->ucode_code.p_addr; | |
2555 | pdata = priv->ucode_data_backup.p_addr; | |
2556 | ||
2557 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 | 2558 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
2559 | if (rc) { |
2560 | spin_unlock_irqrestore(&priv->lock, flags); | |
2561 | return rc; | |
2562 | } | |
2563 | ||
2564 | /* Tell bootstrap uCode where to find image to load */ | |
5d49f498 AK |
2565 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
2566 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
2567 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
b481de9c ZY |
2568 | priv->ucode_data.len); |
2569 | ||
a96a27f9 | 2570 | /* Inst byte count must be last to set up, bit 31 signals uCode |
b481de9c | 2571 | * that all new ptr/size info is in place */ |
5d49f498 | 2572 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
b481de9c ZY |
2573 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
2574 | ||
5d49f498 | 2575 | iwl_release_nic_access(priv); |
b481de9c ZY |
2576 | |
2577 | spin_unlock_irqrestore(&priv->lock, flags); | |
2578 | ||
e1623446 | 2579 | IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n"); |
b481de9c ZY |
2580 | |
2581 | return rc; | |
2582 | } | |
2583 | ||
2584 | /** | |
bb8c093b | 2585 | * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received |
b481de9c ZY |
2586 | * |
2587 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
2588 | * | |
b481de9c | 2589 | * Tell "initialize" uCode to go ahead and load the runtime uCode. |
9fbab516 | 2590 | */ |
4a8a4322 | 2591 | static void iwl3945_init_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
2592 | { |
2593 | /* Check alive response for "valid" sign from uCode */ | |
2594 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
2595 | /* We had an error bringing up the hardware, so take it | |
2596 | * all the way back down so we can try again */ | |
e1623446 | 2597 | IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n"); |
b481de9c ZY |
2598 | goto restart; |
2599 | } | |
2600 | ||
2601 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
2602 | * This is a paranoid check, because we would not have gotten the | |
2603 | * "initialize" alive if code weren't properly loaded. */ | |
bb8c093b | 2604 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
2605 | /* Runtime instruction load was bad; |
2606 | * take it all the way back down so we can try again */ | |
e1623446 | 2607 | IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n"); |
b481de9c ZY |
2608 | goto restart; |
2609 | } | |
2610 | ||
2611 | /* Send pointers to protocol/runtime uCode image ... init code will | |
2612 | * load and launch runtime uCode, which will send us another "Alive" | |
2613 | * notification. */ | |
e1623446 | 2614 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
bb8c093b | 2615 | if (iwl3945_set_ucode_ptrs(priv)) { |
b481de9c ZY |
2616 | /* Runtime instruction load won't happen; |
2617 | * take it all the way back down so we can try again */ | |
e1623446 | 2618 | IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n"); |
b481de9c ZY |
2619 | goto restart; |
2620 | } | |
2621 | return; | |
2622 | ||
2623 | restart: | |
2624 | queue_work(priv->workqueue, &priv->restart); | |
2625 | } | |
2626 | ||
b481de9c | 2627 | /** |
bb8c093b | 2628 | * iwl3945_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 2629 | * from protocol/runtime uCode (initialization uCode's |
bb8c093b | 2630 | * Alive gets handled by iwl3945_init_alive_start()). |
b481de9c | 2631 | */ |
4a8a4322 | 2632 | static void iwl3945_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
2633 | { |
2634 | int rc = 0; | |
2635 | int thermal_spin = 0; | |
2636 | u32 rfkill; | |
2637 | ||
e1623446 | 2638 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
2639 | |
2640 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
2641 | /* We had an error bringing up the hardware, so take it | |
2642 | * all the way back down so we can try again */ | |
e1623446 | 2643 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
2644 | goto restart; |
2645 | } | |
2646 | ||
2647 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
2648 | * This is a paranoid check, because we would not have gotten the | |
2649 | * "runtime" alive if code weren't properly loaded. */ | |
bb8c093b | 2650 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
2651 | /* Runtime instruction load was bad; |
2652 | * take it all the way back down so we can try again */ | |
e1623446 | 2653 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
2654 | goto restart; |
2655 | } | |
2656 | ||
40ace5b3 | 2657 | priv->cfg->ops->smgmt->clear_station_table(priv); |
b481de9c | 2658 | |
5d49f498 | 2659 | rc = iwl_grab_nic_access(priv); |
b481de9c | 2660 | if (rc) { |
39aadf8c | 2661 | IWL_WARN(priv, "Can not read RFKILL status from adapter\n"); |
b481de9c ZY |
2662 | return; |
2663 | } | |
2664 | ||
5d49f498 | 2665 | rfkill = iwl_read_prph(priv, APMG_RFKILL_REG); |
e1623446 | 2666 | IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill); |
5d49f498 | 2667 | iwl_release_nic_access(priv); |
b481de9c ZY |
2668 | |
2669 | if (rfkill & 0x1) { | |
2670 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a96a27f9 | 2671 | /* if RFKILL is not on, then wait for thermal |
b481de9c | 2672 | * sensor in adapter to kick in */ |
bb8c093b | 2673 | while (iwl3945_hw_get_temperature(priv) == 0) { |
b481de9c ZY |
2674 | thermal_spin++; |
2675 | udelay(10); | |
2676 | } | |
2677 | ||
2678 | if (thermal_spin) | |
e1623446 | 2679 | IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n", |
b481de9c ZY |
2680 | thermal_spin * 10); |
2681 | } else | |
2682 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
2683 | ||
9fbab516 | 2684 | /* After the ALIVE response, we can send commands to 3945 uCode */ |
b481de9c ZY |
2685 | set_bit(STATUS_ALIVE, &priv->status); |
2686 | ||
2687 | /* Clear out the uCode error bit if it is set */ | |
2688 | clear_bit(STATUS_FW_ERROR, &priv->status); | |
2689 | ||
775a6e27 | 2690 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
2691 | return; |
2692 | ||
36d6825b | 2693 | ieee80211_wake_queues(priv->hw); |
b481de9c ZY |
2694 | |
2695 | priv->active_rate = priv->rates_mask; | |
2696 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
2697 | ||
d25aabb0 | 2698 | iwl_power_update_mode(priv, false); |
b481de9c | 2699 | |
8ccde88a | 2700 | if (iwl_is_associated(priv)) { |
bb8c093b | 2701 | struct iwl3945_rxon_cmd *active_rxon = |
8ccde88a | 2702 | (struct iwl3945_rxon_cmd *)(&priv->active_rxon); |
b481de9c | 2703 | |
8ccde88a SO |
2704 | memcpy(&priv->staging_rxon, &priv->active_rxon, |
2705 | sizeof(priv->staging_rxon)); | |
b481de9c ZY |
2706 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2707 | } else { | |
2708 | /* Initialize our rx_config data */ | |
8ccde88a | 2709 | iwl_connection_init_rx_config(priv, priv->iw_mode); |
b481de9c ZY |
2710 | } |
2711 | ||
9fbab516 | 2712 | /* Configure Bluetooth device coexistence support */ |
17f841cd | 2713 | iwl_send_bt_config(priv); |
b481de9c ZY |
2714 | |
2715 | /* Configure the adapter for unassociated operation */ | |
e0158e61 | 2716 | iwlcore_commit_rxon(priv); |
b481de9c | 2717 | |
b481de9c ZY |
2718 | iwl3945_reg_txpower_periodic(priv); |
2719 | ||
fe00b5a5 RC |
2720 | iwl3945_led_register(priv); |
2721 | ||
e1623446 | 2722 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 2723 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 2724 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c ZY |
2725 | |
2726 | if (priv->error_recovering) | |
bb8c093b | 2727 | iwl3945_error_recovery(priv); |
b481de9c | 2728 | |
9bdf5eca MA |
2729 | /* reassociate for ADHOC mode */ |
2730 | if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) { | |
2731 | struct sk_buff *beacon = ieee80211_beacon_get(priv->hw, | |
2732 | priv->vif); | |
2733 | if (beacon) | |
9944b938 | 2734 | iwl_mac_beacon_update(priv->hw, beacon); |
9bdf5eca MA |
2735 | } |
2736 | ||
f45c2714 | 2737 | if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status)) |
727882d6 | 2738 | iwl_set_mode(priv, priv->iw_mode); |
f45c2714 | 2739 | |
b481de9c ZY |
2740 | return; |
2741 | ||
2742 | restart: | |
2743 | queue_work(priv->workqueue, &priv->restart); | |
2744 | } | |
2745 | ||
4a8a4322 | 2746 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2747 | |
4a8a4322 | 2748 | static void __iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
2749 | { |
2750 | unsigned long flags; | |
2751 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
2752 | struct ieee80211_conf *conf = NULL; | |
2753 | ||
e1623446 | 2754 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c ZY |
2755 | |
2756 | conf = ieee80211_get_hw_conf(priv->hw); | |
2757 | ||
2758 | if (!exit_pending) | |
2759 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
2760 | ||
ab53d8af | 2761 | iwl3945_led_unregister(priv); |
40ace5b3 | 2762 | priv->cfg->ops->smgmt->clear_station_table(priv); |
b481de9c ZY |
2763 | |
2764 | /* Unblock any waiting calls */ | |
2765 | wake_up_interruptible_all(&priv->wait_command_queue); | |
2766 | ||
b481de9c ZY |
2767 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2768 | * exiting the module */ | |
2769 | if (!exit_pending) | |
2770 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2771 | ||
2772 | /* stop and reset the on-board processor */ | |
5d49f498 | 2773 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
2774 | |
2775 | /* tell the device to stop sending interrupts */ | |
0359facc | 2776 | spin_lock_irqsave(&priv->lock, flags); |
ed3b932e | 2777 | iwl_disable_interrupts(priv); |
0359facc MA |
2778 | spin_unlock_irqrestore(&priv->lock, flags); |
2779 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
2780 | |
2781 | if (priv->mac80211_registered) | |
2782 | ieee80211_stop_queues(priv->hw); | |
2783 | ||
bb8c093b | 2784 | /* If we have not previously called iwl3945_init() then |
6da3a13e | 2785 | * clear all bits but the RF Kill bits and return */ |
775a6e27 | 2786 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
2787 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2788 | STATUS_RF_KILL_HW | | |
2789 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
2790 | STATUS_RF_KILL_SW | | |
9788864e RC |
2791 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2792 | STATUS_GEO_CONFIGURED | | |
ebef2008 AK |
2793 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
2794 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
2795 | goto exit; |
2796 | } | |
2797 | ||
6da3a13e WYG |
2798 | /* ...otherwise clear out all the status bits but the RF Kill |
2799 | * bits and continue taking the NIC down. */ | |
b481de9c ZY |
2800 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2801 | STATUS_RF_KILL_HW | | |
2802 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
2803 | STATUS_RF_KILL_SW | | |
9788864e RC |
2804 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2805 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2806 | test_bit(STATUS_FW_ERROR, &priv->status) << |
ebef2008 AK |
2807 | STATUS_FW_ERROR | |
2808 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2809 | STATUS_EXIT_PENDING; | |
b481de9c | 2810 | |
e9414b6b | 2811 | priv->cfg->ops->lib->apm_ops.reset(priv); |
b481de9c | 2812 | spin_lock_irqsave(&priv->lock, flags); |
5d49f498 | 2813 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
2814 | spin_unlock_irqrestore(&priv->lock, flags); |
2815 | ||
bb8c093b CH |
2816 | iwl3945_hw_txq_ctx_stop(priv); |
2817 | iwl3945_hw_rxq_stop(priv); | |
b481de9c ZY |
2818 | |
2819 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 AK |
2820 | if (!iwl_grab_nic_access(priv)) { |
2821 | iwl_write_prph(priv, APMG_CLK_DIS_REG, | |
b481de9c | 2822 | APMG_CLK_VAL_DMA_CLK_RQT); |
5d49f498 | 2823 | iwl_release_nic_access(priv); |
b481de9c ZY |
2824 | } |
2825 | spin_unlock_irqrestore(&priv->lock, flags); | |
2826 | ||
2827 | udelay(5); | |
2828 | ||
6da3a13e | 2829 | if (exit_pending) |
e9414b6b AM |
2830 | priv->cfg->ops->lib->apm_ops.stop(priv); |
2831 | else | |
2832 | priv->cfg->ops->lib->apm_ops.reset(priv); | |
2833 | ||
b481de9c | 2834 | exit: |
3d24a9f7 | 2835 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
2836 | |
2837 | if (priv->ibss_beacon) | |
2838 | dev_kfree_skb(priv->ibss_beacon); | |
2839 | priv->ibss_beacon = NULL; | |
2840 | ||
2841 | /* clear out any free frames */ | |
bb8c093b | 2842 | iwl3945_clear_free_frames(priv); |
b481de9c ZY |
2843 | } |
2844 | ||
4a8a4322 | 2845 | static void iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
2846 | { |
2847 | mutex_lock(&priv->mutex); | |
bb8c093b | 2848 | __iwl3945_down(priv); |
b481de9c | 2849 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2850 | |
bb8c093b | 2851 | iwl3945_cancel_deferred_work(priv); |
b481de9c ZY |
2852 | } |
2853 | ||
2854 | #define MAX_HW_RESTARTS 5 | |
2855 | ||
4a8a4322 | 2856 | static int __iwl3945_up(struct iwl_priv *priv) |
b481de9c ZY |
2857 | { |
2858 | int rc, i; | |
2859 | ||
2860 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 2861 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2862 | return -EIO; |
2863 | } | |
2864 | ||
2865 | if (test_bit(STATUS_RF_KILL_SW, &priv->status)) { | |
39aadf8c | 2866 | IWL_WARN(priv, "Radio disabled by SW RF kill (module " |
b481de9c | 2867 | "parameter)\n"); |
e655b9f0 ZY |
2868 | return -ENODEV; |
2869 | } | |
2870 | ||
e903fbd4 | 2871 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 2872 | IWL_ERR(priv, "ucode not available for device bring up\n"); |
e903fbd4 RC |
2873 | return -EIO; |
2874 | } | |
2875 | ||
e655b9f0 | 2876 | /* If platform's RF_KILL switch is NOT set to KILL */ |
5d49f498 | 2877 | if (iwl_read32(priv, CSR_GP_CNTRL) & |
e655b9f0 ZY |
2878 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
2879 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2880 | else { | |
2881 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6da3a13e WYG |
2882 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
2883 | return -ENODEV; | |
b481de9c | 2884 | } |
80fcc9e2 | 2885 | |
5d49f498 | 2886 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 2887 | |
bb8c093b | 2888 | rc = iwl3945_hw_nic_init(priv); |
b481de9c | 2889 | if (rc) { |
15b1687c | 2890 | IWL_ERR(priv, "Unable to int nic\n"); |
b481de9c ZY |
2891 | return rc; |
2892 | } | |
2893 | ||
2894 | /* make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
2895 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2896 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
2897 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2898 | ||
2899 | /* clear (again), then enable host interrupts */ | |
5d49f498 | 2900 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
ed3b932e | 2901 | iwl_enable_interrupts(priv); |
b481de9c ZY |
2902 | |
2903 | /* really make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
2904 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2905 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
2906 | |
2907 | /* Copy original ucode data image from disk into backup cache. | |
2908 | * This will be used to initialize the on-board processor's | |
2909 | * data SRAM for a clean start when the runtime program first loads. */ | |
2910 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 2911 | priv->ucode_data.len); |
b481de9c | 2912 | |
e655b9f0 ZY |
2913 | /* We return success when we resume from suspend and rf_kill is on. */ |
2914 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
2915 | return 0; | |
2916 | ||
b481de9c ZY |
2917 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2918 | ||
40ace5b3 | 2919 | priv->cfg->ops->smgmt->clear_station_table(priv); |
b481de9c ZY |
2920 | |
2921 | /* load bootstrap state machine, | |
2922 | * load bootstrap program into processor's memory, | |
2923 | * prepare to load the "initialize" uCode */ | |
0164b9b4 | 2924 | priv->cfg->ops->lib->load_ucode(priv); |
b481de9c ZY |
2925 | |
2926 | if (rc) { | |
15b1687c WT |
2927 | IWL_ERR(priv, |
2928 | "Unable to set up bootstrap uCode: %d\n", rc); | |
b481de9c ZY |
2929 | continue; |
2930 | } | |
2931 | ||
2932 | /* start card; "initialize" will load runtime ucode */ | |
bb8c093b | 2933 | iwl3945_nic_start(priv); |
b481de9c | 2934 | |
e1623446 | 2935 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
2936 | |
2937 | return 0; | |
2938 | } | |
2939 | ||
2940 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
bb8c093b | 2941 | __iwl3945_down(priv); |
ebef2008 | 2942 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
2943 | |
2944 | /* tried to restart and config the device for as long as our | |
2945 | * patience could withstand */ | |
15b1687c | 2946 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
2947 | return -EIO; |
2948 | } | |
2949 | ||
2950 | ||
2951 | /***************************************************************************** | |
2952 | * | |
2953 | * Workqueue callbacks | |
2954 | * | |
2955 | *****************************************************************************/ | |
2956 | ||
bb8c093b | 2957 | static void iwl3945_bg_init_alive_start(struct work_struct *data) |
b481de9c | 2958 | { |
4a8a4322 AK |
2959 | struct iwl_priv *priv = |
2960 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
2961 | |
2962 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2963 | return; | |
2964 | ||
2965 | mutex_lock(&priv->mutex); | |
bb8c093b | 2966 | iwl3945_init_alive_start(priv); |
b481de9c ZY |
2967 | mutex_unlock(&priv->mutex); |
2968 | } | |
2969 | ||
bb8c093b | 2970 | static void iwl3945_bg_alive_start(struct work_struct *data) |
b481de9c | 2971 | { |
4a8a4322 AK |
2972 | struct iwl_priv *priv = |
2973 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
2974 | |
2975 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2976 | return; | |
2977 | ||
2978 | mutex_lock(&priv->mutex); | |
bb8c093b | 2979 | iwl3945_alive_start(priv); |
b481de9c ZY |
2980 | mutex_unlock(&priv->mutex); |
2981 | } | |
2982 | ||
2663516d HS |
2983 | static void iwl3945_rfkill_poll(struct work_struct *data) |
2984 | { | |
2985 | struct iwl_priv *priv = | |
2986 | container_of(data, struct iwl_priv, rfkill_poll.work); | |
2987 | unsigned long status = priv->status; | |
2988 | ||
2989 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
2990 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2991 | else | |
2992 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
2993 | ||
2994 | if (test_bit(STATUS_RF_KILL_HW, &status) != test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
2995 | queue_work(priv->workqueue, &priv->rf_kill); | |
2996 | ||
2997 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, | |
2998 | round_jiffies_relative(2 * HZ)); | |
2999 | ||
3000 | } | |
3001 | ||
b481de9c | 3002 | #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ) |
bb8c093b | 3003 | static void iwl3945_bg_request_scan(struct work_struct *data) |
b481de9c | 3004 | { |
4a8a4322 AK |
3005 | struct iwl_priv *priv = |
3006 | container_of(data, struct iwl_priv, request_scan); | |
c2d79b48 | 3007 | struct iwl_host_cmd cmd = { |
b481de9c | 3008 | .id = REPLY_SCAN_CMD, |
bb8c093b | 3009 | .len = sizeof(struct iwl3945_scan_cmd), |
b481de9c ZY |
3010 | .meta.flags = CMD_SIZE_HUGE, |
3011 | }; | |
3012 | int rc = 0; | |
bb8c093b | 3013 | struct iwl3945_scan_cmd *scan; |
b481de9c | 3014 | struct ieee80211_conf *conf = NULL; |
1ecf9fc1 | 3015 | u8 n_probes = 0; |
8318d78a | 3016 | enum ieee80211_band band; |
1ecf9fc1 | 3017 | bool is_active = false; |
b481de9c ZY |
3018 | |
3019 | conf = ieee80211_get_hw_conf(priv->hw); | |
3020 | ||
3021 | mutex_lock(&priv->mutex); | |
3022 | ||
775a6e27 | 3023 | if (!iwl_is_ready(priv)) { |
39aadf8c | 3024 | IWL_WARN(priv, "request scan called when driver not ready.\n"); |
b481de9c ZY |
3025 | goto done; |
3026 | } | |
3027 | ||
a96a27f9 | 3028 | /* Make sure the scan wasn't canceled before this queued work |
b481de9c ZY |
3029 | * was given the chance to run... */ |
3030 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
3031 | goto done; | |
3032 | ||
3033 | /* This should never be called or scheduled if there is currently | |
3034 | * a scan active in the hardware. */ | |
3035 | if (test_bit(STATUS_SCAN_HW, &priv->status)) { | |
e1623446 TW |
3036 | IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests " |
3037 | "Ignoring second request.\n"); | |
b481de9c ZY |
3038 | rc = -EIO; |
3039 | goto done; | |
3040 | } | |
3041 | ||
3042 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
e1623446 | 3043 | IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n"); |
b481de9c ZY |
3044 | goto done; |
3045 | } | |
3046 | ||
3047 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
e1623446 TW |
3048 | IWL_DEBUG_HC(priv, |
3049 | "Scan request while abort pending. Queuing.\n"); | |
b481de9c ZY |
3050 | goto done; |
3051 | } | |
3052 | ||
775a6e27 | 3053 | if (iwl_is_rfkill(priv)) { |
e1623446 | 3054 | IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n"); |
b481de9c ZY |
3055 | goto done; |
3056 | } | |
3057 | ||
3058 | if (!test_bit(STATUS_READY, &priv->status)) { | |
e1623446 TW |
3059 | IWL_DEBUG_HC(priv, |
3060 | "Scan request while uninitialized. Queuing.\n"); | |
b481de9c ZY |
3061 | goto done; |
3062 | } | |
3063 | ||
3064 | if (!priv->scan_bands) { | |
e1623446 | 3065 | IWL_DEBUG_HC(priv, "Aborting scan due to no requested bands\n"); |
b481de9c ZY |
3066 | goto done; |
3067 | } | |
3068 | ||
805cee5b WT |
3069 | if (!priv->scan) { |
3070 | priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) + | |
b481de9c | 3071 | IWL_MAX_SCAN_SIZE, GFP_KERNEL); |
805cee5b | 3072 | if (!priv->scan) { |
b481de9c ZY |
3073 | rc = -ENOMEM; |
3074 | goto done; | |
3075 | } | |
3076 | } | |
805cee5b | 3077 | scan = priv->scan; |
bb8c093b | 3078 | memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE); |
b481de9c ZY |
3079 | |
3080 | scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; | |
3081 | scan->quiet_time = IWL_ACTIVE_QUIET_TIME; | |
3082 | ||
8ccde88a | 3083 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
3084 | u16 interval = 0; |
3085 | u32 extra; | |
3086 | u32 suspend_time = 100; | |
3087 | u32 scan_suspend_time = 100; | |
3088 | unsigned long flags; | |
3089 | ||
e1623446 | 3090 | IWL_DEBUG_INFO(priv, "Scanning while associated...\n"); |
b481de9c ZY |
3091 | |
3092 | spin_lock_irqsave(&priv->lock, flags); | |
3093 | interval = priv->beacon_int; | |
3094 | spin_unlock_irqrestore(&priv->lock, flags); | |
3095 | ||
3096 | scan->suspend_time = 0; | |
15e869d8 | 3097 | scan->max_out_time = cpu_to_le32(200 * 1024); |
b481de9c ZY |
3098 | if (!interval) |
3099 | interval = suspend_time; | |
3100 | /* | |
3101 | * suspend time format: | |
3102 | * 0-19: beacon interval in usec (time before exec.) | |
3103 | * 20-23: 0 | |
3104 | * 24-31: number of beacons (suspend between channels) | |
3105 | */ | |
3106 | ||
3107 | extra = (suspend_time / interval) << 24; | |
3108 | scan_suspend_time = 0xFF0FFFFF & | |
3109 | (extra | ((suspend_time % interval) * 1024)); | |
3110 | ||
3111 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
e1623446 | 3112 | IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n", |
b481de9c ZY |
3113 | scan_suspend_time, interval); |
3114 | } | |
3115 | ||
1ecf9fc1 JB |
3116 | if (priv->scan_request->n_ssids) { |
3117 | int i, p = 0; | |
3118 | IWL_DEBUG_SCAN(priv, "Kicking off active scan\n"); | |
3119 | for (i = 0; i < priv->scan_request->n_ssids; i++) { | |
3120 | /* always does wildcard anyway */ | |
3121 | if (!priv->scan_request->ssids[i].ssid_len) | |
3122 | continue; | |
3123 | scan->direct_scan[p].id = WLAN_EID_SSID; | |
3124 | scan->direct_scan[p].len = | |
3125 | priv->scan_request->ssids[i].ssid_len; | |
3126 | memcpy(scan->direct_scan[p].ssid, | |
3127 | priv->scan_request->ssids[i].ssid, | |
3128 | priv->scan_request->ssids[i].ssid_len); | |
3129 | n_probes++; | |
3130 | p++; | |
3131 | } | |
3132 | is_active = true; | |
f9340520 | 3133 | } else |
1ecf9fc1 | 3134 | IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n"); |
b481de9c ZY |
3135 | |
3136 | /* We don't build a direct scan probe request; the uCode will do | |
3137 | * that based on the direct_mask added to each channel entry */ | |
b481de9c | 3138 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; |
3832ec9d | 3139 | scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id; |
b481de9c ZY |
3140 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
3141 | ||
3142 | /* flags + rate selection */ | |
3143 | ||
66b5004d | 3144 | if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) { |
b481de9c ZY |
3145 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; |
3146 | scan->tx_cmd.rate = IWL_RATE_1M_PLCP; | |
3147 | scan->good_CRC_th = 0; | |
8318d78a | 3148 | band = IEEE80211_BAND_2GHZ; |
66b5004d | 3149 | } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) { |
b481de9c | 3150 | scan->tx_cmd.rate = IWL_RATE_6M_PLCP; |
b097ad29 JB |
3151 | /* |
3152 | * If active scaning is requested but a certain channel | |
3153 | * is marked passive, we can do active scanning if we | |
3154 | * detect transmissions. | |
3155 | */ | |
3156 | scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH : 0; | |
8318d78a | 3157 | band = IEEE80211_BAND_5GHZ; |
66b5004d | 3158 | } else { |
39aadf8c | 3159 | IWL_WARN(priv, "Invalid scan band count\n"); |
b481de9c ZY |
3160 | goto done; |
3161 | } | |
3162 | ||
77fecfb8 | 3163 | scan->tx_cmd.len = cpu_to_le16( |
1ecf9fc1 JB |
3164 | iwl_fill_probe_req(priv, |
3165 | (struct ieee80211_mgmt *)scan->data, | |
3166 | priv->scan_request->ie, | |
3167 | priv->scan_request->ie_len, | |
3168 | IWL_MAX_SCAN_SIZE - sizeof(*scan))); | |
77fecfb8 | 3169 | |
b481de9c ZY |
3170 | /* select Rx antennas */ |
3171 | scan->flags |= iwl3945_get_antenna_flags(priv); | |
3172 | ||
279b05d4 | 3173 | if (iwl_is_monitor_mode(priv)) |
b481de9c ZY |
3174 | scan->filter_flags = RXON_FILTER_PROMISC_MSK; |
3175 | ||
f9340520 | 3176 | scan->channel_count = |
1ecf9fc1 | 3177 | iwl3945_get_channels_for_scan(priv, band, is_active, n_probes, |
f9340520 | 3178 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); |
b481de9c | 3179 | |
14b54336 | 3180 | if (scan->channel_count == 0) { |
e1623446 | 3181 | IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count); |
14b54336 RC |
3182 | goto done; |
3183 | } | |
3184 | ||
b481de9c | 3185 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + |
bb8c093b | 3186 | scan->channel_count * sizeof(struct iwl3945_scan_channel); |
b481de9c ZY |
3187 | cmd.data = scan; |
3188 | scan->len = cpu_to_le16(cmd.len); | |
3189 | ||
3190 | set_bit(STATUS_SCAN_HW, &priv->status); | |
518099a8 | 3191 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
3192 | if (rc) |
3193 | goto done; | |
3194 | ||
3195 | queue_delayed_work(priv->workqueue, &priv->scan_check, | |
3196 | IWL_SCAN_CHECK_WATCHDOG); | |
3197 | ||
3198 | mutex_unlock(&priv->mutex); | |
3199 | return; | |
3200 | ||
3201 | done: | |
2420ebc1 MA |
3202 | /* can not perform scan make sure we clear scanning |
3203 | * bits from status so next scan request can be performed. | |
3204 | * if we dont clear scanning status bit here all next scan | |
3205 | * will fail | |
3206 | */ | |
3207 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
3208 | clear_bit(STATUS_SCANNING, &priv->status); | |
3209 | ||
01ebd063 | 3210 | /* inform mac80211 scan aborted */ |
b481de9c ZY |
3211 | queue_work(priv->workqueue, &priv->scan_completed); |
3212 | mutex_unlock(&priv->mutex); | |
3213 | } | |
3214 | ||
bb8c093b | 3215 | static void iwl3945_bg_up(struct work_struct *data) |
b481de9c | 3216 | { |
4a8a4322 | 3217 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
3218 | |
3219 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3220 | return; | |
3221 | ||
3222 | mutex_lock(&priv->mutex); | |
bb8c093b | 3223 | __iwl3945_up(priv); |
b481de9c | 3224 | mutex_unlock(&priv->mutex); |
c0af96a6 | 3225 | iwl_rfkill_set_hw_state(priv); |
b481de9c ZY |
3226 | } |
3227 | ||
bb8c093b | 3228 | static void iwl3945_bg_restart(struct work_struct *data) |
b481de9c | 3229 | { |
4a8a4322 | 3230 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
3231 | |
3232 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3233 | return; | |
3234 | ||
bb8c093b | 3235 | iwl3945_down(priv); |
b481de9c ZY |
3236 | queue_work(priv->workqueue, &priv->up); |
3237 | } | |
3238 | ||
bb8c093b | 3239 | static void iwl3945_bg_rx_replenish(struct work_struct *data) |
b481de9c | 3240 | { |
4a8a4322 AK |
3241 | struct iwl_priv *priv = |
3242 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
3243 | |
3244 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3245 | return; | |
3246 | ||
3247 | mutex_lock(&priv->mutex); | |
bb8c093b | 3248 | iwl3945_rx_replenish(priv); |
b481de9c ZY |
3249 | mutex_unlock(&priv->mutex); |
3250 | } | |
3251 | ||
7878a5a4 MA |
3252 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
3253 | ||
5bbe233b | 3254 | void iwl3945_post_associate(struct iwl_priv *priv) |
b481de9c | 3255 | { |
b481de9c ZY |
3256 | int rc = 0; |
3257 | struct ieee80211_conf *conf = NULL; | |
3258 | ||
05c914fe | 3259 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
15b1687c | 3260 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
3261 | return; |
3262 | } | |
3263 | ||
3264 | ||
e1623446 | 3265 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
8ccde88a | 3266 | priv->assoc_id, priv->active_rxon.bssid_addr); |
b481de9c ZY |
3267 | |
3268 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3269 | return; | |
3270 | ||
322a9811 | 3271 | if (!priv->vif || !priv->is_open) |
6ef89d0a | 3272 | return; |
322a9811 | 3273 | |
af0053d6 | 3274 | iwl_scan_cancel_timeout(priv, 200); |
15e869d8 | 3275 | |
b481de9c ZY |
3276 | conf = ieee80211_get_hw_conf(priv->hw); |
3277 | ||
8ccde88a | 3278 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3279 | iwlcore_commit_rxon(priv); |
b481de9c | 3280 | |
28afaf91 | 3281 | memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
bb8c093b | 3282 | iwl3945_setup_rxon_timing(priv); |
518099a8 | 3283 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c ZY |
3284 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
3285 | if (rc) | |
39aadf8c | 3286 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3287 | "Attempting to continue.\n"); |
3288 | ||
8ccde88a | 3289 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c | 3290 | |
8ccde88a | 3291 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
b481de9c | 3292 | |
e1623446 | 3293 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
b481de9c ZY |
3294 | priv->assoc_id, priv->beacon_int); |
3295 | ||
3296 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
8ccde88a | 3297 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 3298 | else |
8ccde88a | 3299 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 3300 | |
8ccde88a | 3301 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { |
b481de9c | 3302 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
8ccde88a | 3303 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 3304 | else |
8ccde88a | 3305 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 3306 | |
05c914fe | 3307 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
8ccde88a | 3308 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c ZY |
3309 | |
3310 | } | |
3311 | ||
e0158e61 | 3312 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3313 | |
3314 | switch (priv->iw_mode) { | |
05c914fe | 3315 | case NL80211_IFTYPE_STATION: |
bb8c093b | 3316 | iwl3945_rate_scale_init(priv->hw, IWL_AP_ID); |
b481de9c ZY |
3317 | break; |
3318 | ||
05c914fe | 3319 | case NL80211_IFTYPE_ADHOC: |
b481de9c | 3320 | |
ce546fd2 | 3321 | priv->assoc_id = 1; |
06fd3d86 | 3322 | priv->cfg->ops->smgmt->add_station(priv, priv->bssid, 0, 0, NULL); |
b481de9c | 3323 | iwl3945_sync_sta(priv, IWL_STA_ID, |
8318d78a | 3324 | (priv->band == IEEE80211_BAND_5GHZ) ? |
b481de9c ZY |
3325 | IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP, |
3326 | CMD_ASYNC); | |
bb8c093b CH |
3327 | iwl3945_rate_scale_init(priv->hw, IWL_STA_ID); |
3328 | iwl3945_send_beacon_cmd(priv); | |
b481de9c ZY |
3329 | |
3330 | break; | |
3331 | ||
3332 | default: | |
15b1687c | 3333 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3ac7f146 | 3334 | __func__, priv->iw_mode); |
b481de9c ZY |
3335 | break; |
3336 | } | |
3337 | ||
14d2aac5 | 3338 | iwl_activate_qos(priv, 0); |
292ae174 | 3339 | |
7878a5a4 MA |
3340 | /* we have just associated, don't start scan too early */ |
3341 | priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN; | |
cd56d331 AK |
3342 | } |
3343 | ||
b481de9c ZY |
3344 | /***************************************************************************** |
3345 | * | |
3346 | * mac80211 entry point functions | |
3347 | * | |
3348 | *****************************************************************************/ | |
3349 | ||
5a66926a ZY |
3350 | #define UCODE_READY_TIMEOUT (2 * HZ) |
3351 | ||
bb8c093b | 3352 | static int iwl3945_mac_start(struct ieee80211_hw *hw) |
b481de9c | 3353 | { |
4a8a4322 | 3354 | struct iwl_priv *priv = hw->priv; |
5a66926a | 3355 | int ret; |
b481de9c | 3356 | |
e1623446 | 3357 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
3358 | |
3359 | /* we should be verifying the device is ready to be opened */ | |
3360 | mutex_lock(&priv->mutex); | |
3361 | ||
8ccde88a | 3362 | memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon)); |
5a66926a ZY |
3363 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... |
3364 | * ucode filename and max sizes are card-specific. */ | |
3365 | ||
3366 | if (!priv->ucode_code.len) { | |
3367 | ret = iwl3945_read_ucode(priv); | |
3368 | if (ret) { | |
15b1687c | 3369 | IWL_ERR(priv, "Could not read microcode: %d\n", ret); |
5a66926a ZY |
3370 | mutex_unlock(&priv->mutex); |
3371 | goto out_release_irq; | |
3372 | } | |
3373 | } | |
b481de9c | 3374 | |
e655b9f0 | 3375 | ret = __iwl3945_up(priv); |
b481de9c ZY |
3376 | |
3377 | mutex_unlock(&priv->mutex); | |
5a66926a | 3378 | |
c0af96a6 | 3379 | iwl_rfkill_set_hw_state(priv); |
80fcc9e2 | 3380 | |
e655b9f0 ZY |
3381 | if (ret) |
3382 | goto out_release_irq; | |
3383 | ||
e1623446 | 3384 | IWL_DEBUG_INFO(priv, "Start UP work.\n"); |
e655b9f0 | 3385 | |
5a66926a ZY |
3386 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from |
3387 | * mac80211 will not be run successfully. */ | |
3388 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
3389 | test_bit(STATUS_READY, &priv->status), | |
3390 | UCODE_READY_TIMEOUT); | |
3391 | if (!ret) { | |
3392 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c WT |
3393 | IWL_ERR(priv, |
3394 | "Wait for START_ALIVE timeout after %dms.\n", | |
3395 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
5a66926a ZY |
3396 | ret = -ETIMEDOUT; |
3397 | goto out_release_irq; | |
3398 | } | |
3399 | } | |
3400 | ||
2663516d HS |
3401 | /* ucode is running and will send rfkill notifications, |
3402 | * no need to poll the killswitch state anymore */ | |
3403 | cancel_delayed_work(&priv->rfkill_poll); | |
3404 | ||
e655b9f0 | 3405 | priv->is_open = 1; |
e1623446 | 3406 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3407 | return 0; |
5a66926a ZY |
3408 | |
3409 | out_release_irq: | |
e655b9f0 | 3410 | priv->is_open = 0; |
e1623446 | 3411 | IWL_DEBUG_MAC80211(priv, "leave - failed\n"); |
5a66926a | 3412 | return ret; |
b481de9c ZY |
3413 | } |
3414 | ||
bb8c093b | 3415 | static void iwl3945_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 3416 | { |
4a8a4322 | 3417 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3418 | |
e1623446 | 3419 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
6ef89d0a | 3420 | |
e655b9f0 | 3421 | if (!priv->is_open) { |
e1623446 | 3422 | IWL_DEBUG_MAC80211(priv, "leave - skip\n"); |
e655b9f0 ZY |
3423 | return; |
3424 | } | |
3425 | ||
b481de9c | 3426 | priv->is_open = 0; |
5a66926a | 3427 | |
775a6e27 | 3428 | if (iwl_is_ready_rf(priv)) { |
e655b9f0 ZY |
3429 | /* stop mac, cancel any scan request and clear |
3430 | * RXON_FILTER_ASSOC_MSK BIT | |
3431 | */ | |
5a66926a | 3432 | mutex_lock(&priv->mutex); |
af0053d6 | 3433 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 3434 | mutex_unlock(&priv->mutex); |
fde3571f MA |
3435 | } |
3436 | ||
5a66926a ZY |
3437 | iwl3945_down(priv); |
3438 | ||
3439 | flush_workqueue(priv->workqueue); | |
2663516d HS |
3440 | |
3441 | /* start polling the killswitch state again */ | |
3442 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, | |
3443 | round_jiffies_relative(2 * HZ)); | |
6ef89d0a | 3444 | |
e1623446 | 3445 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
3446 | } |
3447 | ||
e039fa4a | 3448 | static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 3449 | { |
4a8a4322 | 3450 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3451 | |
e1623446 | 3452 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3453 | |
e1623446 | 3454 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 3455 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 3456 | |
e039fa4a | 3457 | if (iwl3945_tx_skb(priv, skb)) |
b481de9c ZY |
3458 | dev_kfree_skb_any(skb); |
3459 | ||
e1623446 | 3460 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
637f8837 | 3461 | return NETDEV_TX_OK; |
b481de9c ZY |
3462 | } |
3463 | ||
60690a6a | 3464 | void iwl3945_config_ap(struct iwl_priv *priv) |
b481de9c ZY |
3465 | { |
3466 | int rc = 0; | |
3467 | ||
d986bcd1 | 3468 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
3469 | return; |
3470 | ||
3471 | /* The following should be done only at AP bring up */ | |
8ccde88a | 3472 | if (!(iwl_is_associated(priv))) { |
b481de9c ZY |
3473 | |
3474 | /* RXON - unassoc (to set timing command) */ | |
8ccde88a | 3475 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3476 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3477 | |
3478 | /* RXON Timing */ | |
28afaf91 | 3479 | memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
bb8c093b | 3480 | iwl3945_setup_rxon_timing(priv); |
518099a8 SO |
3481 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
3482 | sizeof(priv->rxon_timing), | |
3483 | &priv->rxon_timing); | |
b481de9c | 3484 | if (rc) |
39aadf8c | 3485 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3486 | "Attempting to continue.\n"); |
3487 | ||
3488 | /* FIXME: what should be the assoc_id for AP? */ | |
8ccde88a | 3489 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
b481de9c | 3490 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) |
8ccde88a | 3491 | priv->staging_rxon.flags |= |
b481de9c ZY |
3492 | RXON_FLG_SHORT_PREAMBLE_MSK; |
3493 | else | |
8ccde88a | 3494 | priv->staging_rxon.flags &= |
b481de9c ZY |
3495 | ~RXON_FLG_SHORT_PREAMBLE_MSK; |
3496 | ||
8ccde88a | 3497 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { |
b481de9c ZY |
3498 | if (priv->assoc_capability & |
3499 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
8ccde88a | 3500 | priv->staging_rxon.flags |= |
b481de9c ZY |
3501 | RXON_FLG_SHORT_SLOT_MSK; |
3502 | else | |
8ccde88a | 3503 | priv->staging_rxon.flags &= |
b481de9c ZY |
3504 | ~RXON_FLG_SHORT_SLOT_MSK; |
3505 | ||
05c914fe | 3506 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
8ccde88a | 3507 | priv->staging_rxon.flags &= |
b481de9c ZY |
3508 | ~RXON_FLG_SHORT_SLOT_MSK; |
3509 | } | |
3510 | /* restore RXON assoc */ | |
8ccde88a | 3511 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3512 | iwlcore_commit_rxon(priv); |
06fd3d86 | 3513 | priv->cfg->ops->smgmt->add_station(priv, iwl_bcast_addr, 0, 0, NULL); |
556f8db7 | 3514 | } |
bb8c093b | 3515 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
3516 | |
3517 | /* FIXME - we need to add code here to detect a totally new | |
3518 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
3519 | * clear sta table, add BCAST sta... */ | |
3520 | } | |
3521 | ||
bb8c093b | 3522 | static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
3523 | struct ieee80211_vif *vif, |
3524 | struct ieee80211_sta *sta, | |
3525 | struct ieee80211_key_conf *key) | |
b481de9c | 3526 | { |
4a8a4322 | 3527 | struct iwl_priv *priv = hw->priv; |
dc822b5d | 3528 | const u8 *addr; |
6e21f15c AK |
3529 | int ret = 0; |
3530 | u8 sta_id = IWL_INVALID_STATION; | |
3531 | u8 static_key; | |
b481de9c | 3532 | |
e1623446 | 3533 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3534 | |
df878d8f | 3535 | if (iwl3945_mod_params.sw_crypto) { |
e1623446 | 3536 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
3537 | return -EOPNOTSUPP; |
3538 | } | |
3539 | ||
42986796 | 3540 | addr = sta ? sta->addr : iwl_bcast_addr; |
6e21f15c AK |
3541 | static_key = !iwl_is_associated(priv); |
3542 | ||
3543 | if (!static_key) { | |
40ace5b3 | 3544 | sta_id = priv->cfg->ops->smgmt->find_station(priv, addr); |
6e21f15c | 3545 | if (sta_id == IWL_INVALID_STATION) { |
12514396 | 3546 | IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n", |
6e21f15c AK |
3547 | addr); |
3548 | return -EINVAL; | |
3549 | } | |
b481de9c ZY |
3550 | } |
3551 | ||
3552 | mutex_lock(&priv->mutex); | |
af0053d6 | 3553 | iwl_scan_cancel_timeout(priv, 100); |
6e21f15c | 3554 | mutex_unlock(&priv->mutex); |
15e869d8 | 3555 | |
b481de9c | 3556 | switch (cmd) { |
6e21f15c AK |
3557 | case SET_KEY: |
3558 | if (static_key) | |
3559 | ret = iwl3945_set_static_key(priv, key); | |
3560 | else | |
3561 | ret = iwl3945_set_dynamic_key(priv, key, sta_id); | |
3562 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); | |
b481de9c ZY |
3563 | break; |
3564 | case DISABLE_KEY: | |
6e21f15c AK |
3565 | if (static_key) |
3566 | ret = iwl3945_remove_static_key(priv); | |
3567 | else | |
3568 | ret = iwl3945_clear_sta_key_info(priv, sta_id); | |
3569 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); | |
b481de9c ZY |
3570 | break; |
3571 | default: | |
42986796 | 3572 | ret = -EINVAL; |
b481de9c ZY |
3573 | } |
3574 | ||
e1623446 | 3575 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3576 | |
42986796 | 3577 | return ret; |
b481de9c ZY |
3578 | } |
3579 | ||
b481de9c ZY |
3580 | /***************************************************************************** |
3581 | * | |
3582 | * sysfs attributes | |
3583 | * | |
3584 | *****************************************************************************/ | |
3585 | ||
d08853a3 | 3586 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
3587 | |
3588 | /* | |
3589 | * The following adds a new attribute to the sysfs representation | |
3590 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
3591 | * used for controlling the debug level. | |
3592 | * | |
3593 | * See the level definitions in iwl for details. | |
3594 | */ | |
40b8ec0b SO |
3595 | static ssize_t show_debug_level(struct device *d, |
3596 | struct device_attribute *attr, char *buf) | |
b481de9c | 3597 | { |
4a8a4322 | 3598 | struct iwl_priv *priv = d->driver_data; |
40b8ec0b SO |
3599 | |
3600 | return sprintf(buf, "0x%08X\n", priv->debug_level); | |
b481de9c | 3601 | } |
40b8ec0b SO |
3602 | static ssize_t store_debug_level(struct device *d, |
3603 | struct device_attribute *attr, | |
b481de9c ZY |
3604 | const char *buf, size_t count) |
3605 | { | |
4a8a4322 | 3606 | struct iwl_priv *priv = d->driver_data; |
40b8ec0b SO |
3607 | unsigned long val; |
3608 | int ret; | |
b481de9c | 3609 | |
40b8ec0b SO |
3610 | ret = strict_strtoul(buf, 0, &val); |
3611 | if (ret) | |
978785a3 | 3612 | IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf); |
b481de9c | 3613 | else |
40b8ec0b | 3614 | priv->debug_level = val; |
b481de9c ZY |
3615 | |
3616 | return strnlen(buf, count); | |
3617 | } | |
3618 | ||
40b8ec0b SO |
3619 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
3620 | show_debug_level, store_debug_level); | |
b481de9c | 3621 | |
d08853a3 | 3622 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 3623 | |
b481de9c ZY |
3624 | static ssize_t show_temperature(struct device *d, |
3625 | struct device_attribute *attr, char *buf) | |
3626 | { | |
4a8a4322 | 3627 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c | 3628 | |
775a6e27 | 3629 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3630 | return -EAGAIN; |
3631 | ||
bb8c093b | 3632 | return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv)); |
b481de9c ZY |
3633 | } |
3634 | ||
3635 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
3636 | ||
b481de9c ZY |
3637 | static ssize_t show_tx_power(struct device *d, |
3638 | struct device_attribute *attr, char *buf) | |
3639 | { | |
4a8a4322 | 3640 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
62ea9c5b | 3641 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); |
b481de9c ZY |
3642 | } |
3643 | ||
3644 | static ssize_t store_tx_power(struct device *d, | |
3645 | struct device_attribute *attr, | |
3646 | const char *buf, size_t count) | |
3647 | { | |
4a8a4322 | 3648 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
3649 | char *p = (char *)buf; |
3650 | u32 val; | |
3651 | ||
3652 | val = simple_strtoul(p, &p, 10); | |
3653 | if (p == buf) | |
978785a3 | 3654 | IWL_INFO(priv, ": %s is not in decimal form.\n", buf); |
b481de9c | 3655 | else |
bb8c093b | 3656 | iwl3945_hw_reg_set_txpower(priv, val); |
b481de9c ZY |
3657 | |
3658 | return count; | |
3659 | } | |
3660 | ||
3661 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
3662 | ||
3663 | static ssize_t show_flags(struct device *d, | |
3664 | struct device_attribute *attr, char *buf) | |
3665 | { | |
4a8a4322 | 3666 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c | 3667 | |
8ccde88a | 3668 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); |
b481de9c ZY |
3669 | } |
3670 | ||
3671 | static ssize_t store_flags(struct device *d, | |
3672 | struct device_attribute *attr, | |
3673 | const char *buf, size_t count) | |
3674 | { | |
4a8a4322 | 3675 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
3676 | u32 flags = simple_strtoul(buf, NULL, 0); |
3677 | ||
3678 | mutex_lock(&priv->mutex); | |
8ccde88a | 3679 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { |
b481de9c | 3680 | /* Cancel any currently running scans... */ |
af0053d6 | 3681 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3682 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3683 | else { |
e1623446 | 3684 | IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n", |
b481de9c | 3685 | flags); |
8ccde88a | 3686 | priv->staging_rxon.flags = cpu_to_le32(flags); |
e0158e61 | 3687 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3688 | } |
3689 | } | |
3690 | mutex_unlock(&priv->mutex); | |
3691 | ||
3692 | return count; | |
3693 | } | |
3694 | ||
3695 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
3696 | ||
3697 | static ssize_t show_filter_flags(struct device *d, | |
3698 | struct device_attribute *attr, char *buf) | |
3699 | { | |
4a8a4322 | 3700 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
3701 | |
3702 | return sprintf(buf, "0x%04X\n", | |
8ccde88a | 3703 | le32_to_cpu(priv->active_rxon.filter_flags)); |
b481de9c ZY |
3704 | } |
3705 | ||
3706 | static ssize_t store_filter_flags(struct device *d, | |
3707 | struct device_attribute *attr, | |
3708 | const char *buf, size_t count) | |
3709 | { | |
4a8a4322 | 3710 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
3711 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
3712 | ||
3713 | mutex_lock(&priv->mutex); | |
8ccde88a | 3714 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { |
b481de9c | 3715 | /* Cancel any currently running scans... */ |
af0053d6 | 3716 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3717 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3718 | else { |
e1623446 | 3719 | IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = " |
b481de9c | 3720 | "0x%04X\n", filter_flags); |
8ccde88a | 3721 | priv->staging_rxon.filter_flags = |
b481de9c | 3722 | cpu_to_le32(filter_flags); |
e0158e61 | 3723 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3724 | } |
3725 | } | |
3726 | mutex_unlock(&priv->mutex); | |
3727 | ||
3728 | return count; | |
3729 | } | |
3730 | ||
3731 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
3732 | store_filter_flags); | |
3733 | ||
c8b0e6e1 | 3734 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
3735 | |
3736 | static ssize_t show_measurement(struct device *d, | |
3737 | struct device_attribute *attr, char *buf) | |
3738 | { | |
4a8a4322 | 3739 | struct iwl_priv *priv = dev_get_drvdata(d); |
600c0e11 | 3740 | struct iwl_spectrum_notification measure_report; |
b481de9c | 3741 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
3ac7f146 | 3742 | u8 *data = (u8 *)&measure_report; |
b481de9c ZY |
3743 | unsigned long flags; |
3744 | ||
3745 | spin_lock_irqsave(&priv->lock, flags); | |
3746 | if (!(priv->measurement_status & MEASUREMENT_READY)) { | |
3747 | spin_unlock_irqrestore(&priv->lock, flags); | |
3748 | return 0; | |
3749 | } | |
3750 | memcpy(&measure_report, &priv->measure_report, size); | |
3751 | priv->measurement_status = 0; | |
3752 | spin_unlock_irqrestore(&priv->lock, flags); | |
3753 | ||
3754 | while (size && (PAGE_SIZE - len)) { | |
3755 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
3756 | PAGE_SIZE - len, 1); | |
3757 | len = strlen(buf); | |
3758 | if (PAGE_SIZE - len) | |
3759 | buf[len++] = '\n'; | |
3760 | ||
3761 | ofs += 16; | |
3762 | size -= min(size, 16U); | |
3763 | } | |
3764 | ||
3765 | return len; | |
3766 | } | |
3767 | ||
3768 | static ssize_t store_measurement(struct device *d, | |
3769 | struct device_attribute *attr, | |
3770 | const char *buf, size_t count) | |
3771 | { | |
4a8a4322 | 3772 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3773 | struct ieee80211_measurement_params params = { |
8ccde88a | 3774 | .channel = le16_to_cpu(priv->active_rxon.channel), |
b481de9c ZY |
3775 | .start_time = cpu_to_le64(priv->last_tsf), |
3776 | .duration = cpu_to_le16(1), | |
3777 | }; | |
3778 | u8 type = IWL_MEASURE_BASIC; | |
3779 | u8 buffer[32]; | |
3780 | u8 channel; | |
3781 | ||
3782 | if (count) { | |
3783 | char *p = buffer; | |
3784 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
3785 | channel = simple_strtoul(p, NULL, 0); | |
3786 | if (channel) | |
3787 | params.channel = channel; | |
3788 | ||
3789 | p = buffer; | |
3790 | while (*p && *p != ' ') | |
3791 | p++; | |
3792 | if (*p) | |
3793 | type = simple_strtoul(p + 1, NULL, 0); | |
3794 | } | |
3795 | ||
e1623446 | 3796 | IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on " |
b481de9c | 3797 | "channel %d (for '%s')\n", type, params.channel, buf); |
bb8c093b | 3798 | iwl3945_get_measurement(priv, ¶ms, type); |
b481de9c ZY |
3799 | |
3800 | return count; | |
3801 | } | |
3802 | ||
3803 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
3804 | show_measurement, store_measurement); | |
c8b0e6e1 | 3805 | #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */ |
b481de9c | 3806 | |
b481de9c ZY |
3807 | static ssize_t store_retry_rate(struct device *d, |
3808 | struct device_attribute *attr, | |
3809 | const char *buf, size_t count) | |
3810 | { | |
4a8a4322 | 3811 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3812 | |
3813 | priv->retry_rate = simple_strtoul(buf, NULL, 0); | |
3814 | if (priv->retry_rate <= 0) | |
3815 | priv->retry_rate = 1; | |
3816 | ||
3817 | return count; | |
3818 | } | |
3819 | ||
3820 | static ssize_t show_retry_rate(struct device *d, | |
3821 | struct device_attribute *attr, char *buf) | |
3822 | { | |
4a8a4322 | 3823 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3824 | return sprintf(buf, "%d", priv->retry_rate); |
3825 | } | |
3826 | ||
3827 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate, | |
3828 | store_retry_rate); | |
3829 | ||
d25aabb0 | 3830 | |
b481de9c ZY |
3831 | static ssize_t store_power_level(struct device *d, |
3832 | struct device_attribute *attr, | |
3833 | const char *buf, size_t count) | |
3834 | { | |
4a8a4322 | 3835 | struct iwl_priv *priv = dev_get_drvdata(d); |
d25aabb0 WT |
3836 | int ret; |
3837 | unsigned long mode; | |
3838 | ||
b481de9c | 3839 | |
b481de9c ZY |
3840 | mutex_lock(&priv->mutex); |
3841 | ||
d25aabb0 WT |
3842 | ret = strict_strtoul(buf, 10, &mode); |
3843 | if (ret) | |
3844 | goto out; | |
b481de9c | 3845 | |
d25aabb0 WT |
3846 | ret = iwl_power_set_user_mode(priv, mode); |
3847 | if (ret) { | |
3848 | IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n"); | |
3849 | goto out; | |
b481de9c | 3850 | } |
d25aabb0 | 3851 | ret = count; |
b481de9c ZY |
3852 | |
3853 | out: | |
3854 | mutex_unlock(&priv->mutex); | |
d25aabb0 | 3855 | return ret; |
b481de9c ZY |
3856 | } |
3857 | ||
d25aabb0 WT |
3858 | static ssize_t show_power_level(struct device *d, |
3859 | struct device_attribute *attr, char *buf) | |
3860 | { | |
3861 | struct iwl_priv *priv = dev_get_drvdata(d); | |
3862 | int mode = priv->power_data.user_power_setting; | |
3863 | int system = priv->power_data.system_power_setting; | |
3864 | int level = priv->power_data.power_mode; | |
3865 | char *p = buf; | |
3866 | ||
3867 | switch (system) { | |
3868 | case IWL_POWER_SYS_AUTO: | |
3869 | p += sprintf(p, "SYSTEM:auto"); | |
3870 | break; | |
3871 | case IWL_POWER_SYS_AC: | |
3872 | p += sprintf(p, "SYSTEM:ac"); | |
3873 | break; | |
3874 | case IWL_POWER_SYS_BATTERY: | |
3875 | p += sprintf(p, "SYSTEM:battery"); | |
3876 | break; | |
3877 | } | |
3878 | ||
3879 | p += sprintf(p, "\tMODE:%s", (mode < IWL_POWER_AUTO) ? | |
3880 | "fixed" : "auto"); | |
3881 | p += sprintf(p, "\tINDEX:%d", level); | |
3882 | p += sprintf(p, "\n"); | |
3883 | return p - buf + 1; | |
3884 | } | |
3885 | ||
3886 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, | |
3887 | show_power_level, store_power_level); | |
3888 | ||
b481de9c ZY |
3889 | #define MAX_WX_STRING 80 |
3890 | ||
3891 | /* Values are in microsecond */ | |
3892 | static const s32 timeout_duration[] = { | |
3893 | 350000, | |
3894 | 250000, | |
3895 | 75000, | |
3896 | 37000, | |
3897 | 25000, | |
3898 | }; | |
3899 | static const s32 period_duration[] = { | |
3900 | 400000, | |
3901 | 700000, | |
3902 | 1000000, | |
3903 | 1000000, | |
3904 | 1000000 | |
3905 | }; | |
3906 | ||
b481de9c ZY |
3907 | static ssize_t show_channels(struct device *d, |
3908 | struct device_attribute *attr, char *buf) | |
3909 | { | |
8318d78a JB |
3910 | /* all this shit doesn't belong into sysfs anyway */ |
3911 | return 0; | |
b481de9c ZY |
3912 | } |
3913 | ||
3914 | static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); | |
3915 | ||
3916 | static ssize_t show_statistics(struct device *d, | |
3917 | struct device_attribute *attr, char *buf) | |
3918 | { | |
4a8a4322 | 3919 | struct iwl_priv *priv = dev_get_drvdata(d); |
bb8c093b | 3920 | u32 size = sizeof(struct iwl3945_notif_statistics); |
b481de9c | 3921 | u32 len = 0, ofs = 0; |
f2c7e521 | 3922 | u8 *data = (u8 *)&priv->statistics_39; |
b481de9c ZY |
3923 | int rc = 0; |
3924 | ||
775a6e27 | 3925 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3926 | return -EAGAIN; |
3927 | ||
3928 | mutex_lock(&priv->mutex); | |
17f841cd | 3929 | rc = iwl_send_statistics_request(priv, 0); |
b481de9c ZY |
3930 | mutex_unlock(&priv->mutex); |
3931 | ||
3932 | if (rc) { | |
3933 | len = sprintf(buf, | |
3934 | "Error sending statistics request: 0x%08X\n", rc); | |
3935 | return len; | |
3936 | } | |
3937 | ||
3938 | while (size && (PAGE_SIZE - len)) { | |
3939 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
3940 | PAGE_SIZE - len, 1); | |
3941 | len = strlen(buf); | |
3942 | if (PAGE_SIZE - len) | |
3943 | buf[len++] = '\n'; | |
3944 | ||
3945 | ofs += 16; | |
3946 | size -= min(size, 16U); | |
3947 | } | |
3948 | ||
3949 | return len; | |
3950 | } | |
3951 | ||
3952 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
3953 | ||
3954 | static ssize_t show_antenna(struct device *d, | |
3955 | struct device_attribute *attr, char *buf) | |
3956 | { | |
4a8a4322 | 3957 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3958 | |
775a6e27 | 3959 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3960 | return -EAGAIN; |
3961 | ||
7e4bca5e | 3962 | return sprintf(buf, "%d\n", iwl3945_mod_params.antenna); |
b481de9c ZY |
3963 | } |
3964 | ||
3965 | static ssize_t store_antenna(struct device *d, | |
3966 | struct device_attribute *attr, | |
3967 | const char *buf, size_t count) | |
3968 | { | |
7530f85f | 3969 | struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d); |
b481de9c | 3970 | int ant; |
b481de9c ZY |
3971 | |
3972 | if (count == 0) | |
3973 | return 0; | |
3974 | ||
3975 | if (sscanf(buf, "%1i", &ant) != 1) { | |
e1623446 | 3976 | IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n"); |
b481de9c ZY |
3977 | return count; |
3978 | } | |
3979 | ||
3980 | if ((ant >= 0) && (ant <= 2)) { | |
e1623446 | 3981 | IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant); |
7e4bca5e | 3982 | iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant; |
b481de9c | 3983 | } else |
e1623446 | 3984 | IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant); |
b481de9c ZY |
3985 | |
3986 | ||
3987 | return count; | |
3988 | } | |
3989 | ||
3990 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna); | |
3991 | ||
3992 | static ssize_t show_status(struct device *d, | |
3993 | struct device_attribute *attr, char *buf) | |
3994 | { | |
4a8a4322 | 3995 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
775a6e27 | 3996 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3997 | return -EAGAIN; |
3998 | return sprintf(buf, "0x%08x\n", (int)priv->status); | |
3999 | } | |
4000 | ||
4001 | static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); | |
4002 | ||
4003 | static ssize_t dump_error_log(struct device *d, | |
4004 | struct device_attribute *attr, | |
4005 | const char *buf, size_t count) | |
4006 | { | |
4007 | char *p = (char *)buf; | |
4008 | ||
4009 | if (p[0] == '1') | |
4a8a4322 | 4010 | iwl3945_dump_nic_error_log((struct iwl_priv *)d->driver_data); |
b481de9c ZY |
4011 | |
4012 | return strnlen(buf, count); | |
4013 | } | |
4014 | ||
4015 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | |
4016 | ||
4017 | static ssize_t dump_event_log(struct device *d, | |
4018 | struct device_attribute *attr, | |
4019 | const char *buf, size_t count) | |
4020 | { | |
4021 | char *p = (char *)buf; | |
4022 | ||
4023 | if (p[0] == '1') | |
4a8a4322 | 4024 | iwl3945_dump_nic_event_log((struct iwl_priv *)d->driver_data); |
b481de9c ZY |
4025 | |
4026 | return strnlen(buf, count); | |
4027 | } | |
4028 | ||
4029 | static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log); | |
4030 | ||
4031 | /***************************************************************************** | |
4032 | * | |
a96a27f9 | 4033 | * driver setup and tear down |
b481de9c ZY |
4034 | * |
4035 | *****************************************************************************/ | |
4036 | ||
4a8a4322 | 4037 | static void iwl3945_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 4038 | { |
d21050c7 | 4039 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
4040 | |
4041 | init_waitqueue_head(&priv->wait_command_queue); | |
4042 | ||
bb8c093b CH |
4043 | INIT_WORK(&priv->up, iwl3945_bg_up); |
4044 | INIT_WORK(&priv->restart, iwl3945_bg_restart); | |
4045 | INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish); | |
c0af96a6 | 4046 | INIT_WORK(&priv->rf_kill, iwl_bg_rf_kill); |
bb8c093b | 4047 | INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update); |
bb8c093b CH |
4048 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start); |
4049 | INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start); | |
2663516d | 4050 | INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll); |
77fecfb8 SO |
4051 | INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed); |
4052 | INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan); | |
4053 | INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan); | |
4054 | INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check); | |
bb8c093b CH |
4055 | |
4056 | iwl3945_hw_setup_deferred_work(priv); | |
b481de9c ZY |
4057 | |
4058 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
bb8c093b | 4059 | iwl3945_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
4060 | } |
4061 | ||
4a8a4322 | 4062 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 4063 | { |
bb8c093b | 4064 | iwl3945_hw_cancel_deferred_work(priv); |
b481de9c | 4065 | |
e47eb6ad | 4066 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
4067 | cancel_delayed_work(&priv->scan_check); |
4068 | cancel_delayed_work(&priv->alive_start); | |
b481de9c ZY |
4069 | cancel_work_sync(&priv->beacon_update); |
4070 | } | |
4071 | ||
bb8c093b | 4072 | static struct attribute *iwl3945_sysfs_entries[] = { |
b481de9c ZY |
4073 | &dev_attr_antenna.attr, |
4074 | &dev_attr_channels.attr, | |
4075 | &dev_attr_dump_errors.attr, | |
4076 | &dev_attr_dump_events.attr, | |
4077 | &dev_attr_flags.attr, | |
4078 | &dev_attr_filter_flags.attr, | |
c8b0e6e1 | 4079 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
4080 | &dev_attr_measurement.attr, |
4081 | #endif | |
4082 | &dev_attr_power_level.attr, | |
b481de9c | 4083 | &dev_attr_retry_rate.attr, |
b481de9c ZY |
4084 | &dev_attr_statistics.attr, |
4085 | &dev_attr_status.attr, | |
4086 | &dev_attr_temperature.attr, | |
b481de9c | 4087 | &dev_attr_tx_power.attr, |
d08853a3 | 4088 | #ifdef CONFIG_IWLWIFI_DEBUG |
40b8ec0b SO |
4089 | &dev_attr_debug_level.attr, |
4090 | #endif | |
b481de9c ZY |
4091 | NULL |
4092 | }; | |
4093 | ||
bb8c093b | 4094 | static struct attribute_group iwl3945_attribute_group = { |
b481de9c | 4095 | .name = NULL, /* put in device directory */ |
bb8c093b | 4096 | .attrs = iwl3945_sysfs_entries, |
b481de9c ZY |
4097 | }; |
4098 | ||
bb8c093b CH |
4099 | static struct ieee80211_ops iwl3945_hw_ops = { |
4100 | .tx = iwl3945_mac_tx, | |
4101 | .start = iwl3945_mac_start, | |
4102 | .stop = iwl3945_mac_stop, | |
cbb6ab94 | 4103 | .add_interface = iwl_mac_add_interface, |
d8052319 | 4104 | .remove_interface = iwl_mac_remove_interface, |
4808368d | 4105 | .config = iwl_mac_config, |
8ccde88a | 4106 | .configure_filter = iwl_configure_filter, |
bb8c093b | 4107 | .set_key = iwl3945_mac_set_key, |
aa89f31e | 4108 | .get_tx_stats = iwl_mac_get_tx_stats, |
488829f1 | 4109 | .conf_tx = iwl_mac_conf_tx, |
bd564261 | 4110 | .reset_tsf = iwl_mac_reset_tsf, |
5bbe233b | 4111 | .bss_info_changed = iwl_bss_info_changed, |
e9dde6f6 | 4112 | .hw_scan = iwl_mac_hw_scan |
b481de9c ZY |
4113 | }; |
4114 | ||
e52119c5 | 4115 | static int iwl3945_init_drv(struct iwl_priv *priv) |
90a30a02 KA |
4116 | { |
4117 | int ret; | |
e6148917 | 4118 | struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; |
90a30a02 KA |
4119 | |
4120 | priv->retry_rate = 1; | |
4121 | priv->ibss_beacon = NULL; | |
4122 | ||
4123 | spin_lock_init(&priv->lock); | |
3dae0c42 | 4124 | spin_lock_init(&priv->power_data.lock); |
90a30a02 KA |
4125 | spin_lock_init(&priv->sta_lock); |
4126 | spin_lock_init(&priv->hcmd_lock); | |
4127 | ||
4128 | INIT_LIST_HEAD(&priv->free_frames); | |
4129 | ||
4130 | mutex_init(&priv->mutex); | |
4131 | ||
4132 | /* Clear the driver's (not device's) station table */ | |
40ace5b3 | 4133 | priv->cfg->ops->smgmt->clear_station_table(priv); |
90a30a02 KA |
4134 | |
4135 | priv->data_retry_limit = -1; | |
4136 | priv->ieee_channels = NULL; | |
4137 | priv->ieee_rates = NULL; | |
4138 | priv->band = IEEE80211_BAND_2GHZ; | |
4139 | ||
4140 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
4141 | ||
4142 | iwl_reset_qos(priv); | |
4143 | ||
4144 | priv->qos_data.qos_active = 0; | |
4145 | priv->qos_data.qos_cap.val = 0; | |
4146 | ||
4147 | priv->rates_mask = IWL_RATES_MASK; | |
d25aabb0 WT |
4148 | /* If power management is turned on, default to CAM mode */ |
4149 | priv->power_mode = IWL_POWER_MODE_CAM; | |
62ea9c5b | 4150 | priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER; |
90a30a02 | 4151 | |
e6148917 SO |
4152 | if (eeprom->version < EEPROM_3945_EEPROM_VERSION) { |
4153 | IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n", | |
4154 | eeprom->version); | |
4155 | ret = -EINVAL; | |
4156 | goto err; | |
4157 | } | |
4158 | ret = iwl_init_channel_map(priv); | |
90a30a02 KA |
4159 | if (ret) { |
4160 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
4161 | goto err; | |
4162 | } | |
4163 | ||
e6148917 SO |
4164 | /* Set up txpower settings in driver for all channels */ |
4165 | if (iwl3945_txpower_set_from_eeprom(priv)) { | |
4166 | ret = -EIO; | |
4167 | goto err_free_channel_map; | |
4168 | } | |
4169 | ||
534166de | 4170 | ret = iwlcore_init_geos(priv); |
90a30a02 KA |
4171 | if (ret) { |
4172 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
4173 | goto err_free_channel_map; | |
4174 | } | |
534166de SO |
4175 | iwl3945_init_hw_rates(priv, priv->ieee_rates); |
4176 | ||
2a4ddaab AK |
4177 | return 0; |
4178 | ||
4179 | err_free_channel_map: | |
4180 | iwl_free_channel_map(priv); | |
4181 | err: | |
4182 | return ret; | |
4183 | } | |
4184 | ||
4185 | static int iwl3945_setup_mac(struct iwl_priv *priv) | |
4186 | { | |
4187 | int ret; | |
4188 | struct ieee80211_hw *hw = priv->hw; | |
4189 | ||
4190 | hw->rate_control_algorithm = "iwl-3945-rs"; | |
4191 | hw->sta_data_size = sizeof(struct iwl3945_sta_priv); | |
4192 | ||
4193 | /* Tell mac80211 our characteristics */ | |
4194 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
b1c6019b MA |
4195 | IEEE80211_HW_NOISE_DBM | |
4196 | IEEE80211_HW_SPECTRUM_MGMT; | |
2a4ddaab AK |
4197 | |
4198 | hw->wiphy->interface_modes = | |
4199 | BIT(NL80211_IFTYPE_STATION) | | |
4200 | BIT(NL80211_IFTYPE_ADHOC); | |
4201 | ||
4202 | hw->wiphy->custom_regulatory = true; | |
4203 | ||
1ecf9fc1 JB |
4204 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945; |
4205 | /* we create the 802.11 header and a zero-length SSID element */ | |
4206 | hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2; | |
d60cc91a | 4207 | |
2a4ddaab AK |
4208 | /* Default value; 4 EDCA QOS priorities */ |
4209 | hw->queues = 4; | |
4210 | ||
534166de SO |
4211 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
4212 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
4213 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
2a4ddaab | 4214 | |
534166de SO |
4215 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) |
4216 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
4217 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
90a30a02 | 4218 | |
2a4ddaab AK |
4219 | ret = ieee80211_register_hw(priv->hw); |
4220 | if (ret) { | |
4221 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
4222 | return ret; | |
4223 | } | |
4224 | priv->mac80211_registered = 1; | |
90a30a02 | 4225 | |
2a4ddaab | 4226 | return 0; |
90a30a02 KA |
4227 | } |
4228 | ||
bb8c093b | 4229 | static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
4230 | { |
4231 | int err = 0; | |
4a8a4322 | 4232 | struct iwl_priv *priv; |
b481de9c | 4233 | struct ieee80211_hw *hw; |
c0f20d91 | 4234 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
e6148917 | 4235 | struct iwl3945_eeprom *eeprom; |
0359facc | 4236 | unsigned long flags; |
b481de9c | 4237 | |
cee53ddb KA |
4238 | /*********************** |
4239 | * 1. Allocating HW data | |
4240 | * ********************/ | |
4241 | ||
b481de9c ZY |
4242 | /* mac80211 allocates memory for this device instance, including |
4243 | * space for this driver's private structure */ | |
90a30a02 | 4244 | hw = iwl_alloc_all(cfg, &iwl3945_hw_ops); |
b481de9c | 4245 | if (hw == NULL) { |
a3139c59 | 4246 | printk(KERN_ERR DRV_NAME "Can not allocate network device\n"); |
b481de9c ZY |
4247 | err = -ENOMEM; |
4248 | goto out; | |
4249 | } | |
b481de9c | 4250 | priv = hw->priv; |
90a30a02 | 4251 | SET_IEEE80211_DEV(hw, &pdev->dev); |
6440adb5 | 4252 | |
df878d8f KA |
4253 | if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) || |
4254 | (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) { | |
15b1687c WT |
4255 | IWL_ERR(priv, |
4256 | "invalid queues_num, should be between %d and %d\n", | |
4257 | IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES); | |
a3139c59 | 4258 | err = -EINVAL; |
c8f16138 | 4259 | goto out_ieee80211_free_hw; |
a3139c59 SO |
4260 | } |
4261 | ||
90a30a02 KA |
4262 | /* |
4263 | * Disabling hardware scan means that mac80211 will perform scans | |
4264 | * "the hard way", rather than using device's scan. | |
4265 | */ | |
df878d8f | 4266 | if (iwl3945_mod_params.disable_hw_scan) { |
e1623446 | 4267 | IWL_DEBUG_INFO(priv, "Disabling hw_scan\n"); |
40b8ec0b SO |
4268 | iwl3945_hw_ops.hw_scan = NULL; |
4269 | } | |
4270 | ||
90a30a02 | 4271 | |
e1623446 | 4272 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
90a30a02 KA |
4273 | priv->cfg = cfg; |
4274 | priv->pci_dev = pdev; | |
cee53ddb | 4275 | |
d08853a3 | 4276 | #ifdef CONFIG_IWLWIFI_DEBUG |
df878d8f | 4277 | priv->debug_level = iwl3945_mod_params.debug; |
b481de9c ZY |
4278 | atomic_set(&priv->restrict_refcnt, 0); |
4279 | #endif | |
b481de9c | 4280 | |
cee53ddb KA |
4281 | /*************************** |
4282 | * 2. Initializing PCI bus | |
4283 | * *************************/ | |
b481de9c ZY |
4284 | if (pci_enable_device(pdev)) { |
4285 | err = -ENODEV; | |
4286 | goto out_ieee80211_free_hw; | |
4287 | } | |
4288 | ||
4289 | pci_set_master(pdev); | |
4290 | ||
284901a9 | 4291 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
b481de9c | 4292 | if (!err) |
284901a9 | 4293 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
b481de9c | 4294 | if (err) { |
978785a3 | 4295 | IWL_WARN(priv, "No suitable DMA available.\n"); |
b481de9c ZY |
4296 | goto out_pci_disable_device; |
4297 | } | |
4298 | ||
4299 | pci_set_drvdata(pdev, priv); | |
4300 | err = pci_request_regions(pdev, DRV_NAME); | |
4301 | if (err) | |
4302 | goto out_pci_disable_device; | |
6440adb5 | 4303 | |
cee53ddb KA |
4304 | /*********************** |
4305 | * 3. Read REV Register | |
4306 | * ********************/ | |
b481de9c ZY |
4307 | priv->hw_base = pci_iomap(pdev, 0, 0); |
4308 | if (!priv->hw_base) { | |
4309 | err = -ENODEV; | |
4310 | goto out_pci_release_regions; | |
4311 | } | |
4312 | ||
e1623446 | 4313 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
b481de9c | 4314 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 4315 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
b481de9c | 4316 | |
cee53ddb KA |
4317 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
4318 | * PCI Tx retries from interfering with C3 CPU state */ | |
4319 | pci_write_config_byte(pdev, 0x41, 0x00); | |
b481de9c | 4320 | |
90a30a02 KA |
4321 | /* amp init */ |
4322 | err = priv->cfg->ops->lib->apm_ops.init(priv); | |
cee53ddb | 4323 | if (err < 0) { |
d5df2a16 | 4324 | IWL_DEBUG_INFO(priv, "Failed to init the card\n"); |
90a30a02 | 4325 | goto out_iounmap; |
cee53ddb | 4326 | } |
b481de9c | 4327 | |
cee53ddb KA |
4328 | /*********************** |
4329 | * 4. Read EEPROM | |
4330 | * ********************/ | |
90a30a02 | 4331 | |
cee53ddb | 4332 | /* Read the EEPROM */ |
e6148917 | 4333 | err = iwl_eeprom_init(priv); |
cee53ddb | 4334 | if (err) { |
15b1687c | 4335 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
c8f16138 | 4336 | goto out_iounmap; |
cee53ddb KA |
4337 | } |
4338 | /* MAC Address location in EEPROM same for 3945/4965 */ | |
e6148917 SO |
4339 | eeprom = (struct iwl3945_eeprom *)priv->eeprom; |
4340 | memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN); | |
e1623446 | 4341 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr); |
cee53ddb | 4342 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); |
b481de9c | 4343 | |
cee53ddb KA |
4344 | /*********************** |
4345 | * 5. Setup HW Constants | |
4346 | * ********************/ | |
b481de9c | 4347 | /* Device-specific setup */ |
3832ec9d | 4348 | if (iwl3945_hw_set_hw_params(priv)) { |
15b1687c | 4349 | IWL_ERR(priv, "failed to set hw settings\n"); |
c8f16138 | 4350 | goto out_eeprom_free; |
b481de9c ZY |
4351 | } |
4352 | ||
cee53ddb KA |
4353 | /*********************** |
4354 | * 6. Setup priv | |
4355 | * ********************/ | |
cee53ddb | 4356 | |
90a30a02 | 4357 | err = iwl3945_init_drv(priv); |
b481de9c | 4358 | if (err) { |
90a30a02 | 4359 | IWL_ERR(priv, "initializing driver failed\n"); |
c8f16138 | 4360 | goto out_unset_hw_params; |
b481de9c ZY |
4361 | } |
4362 | ||
978785a3 TW |
4363 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n", |
4364 | priv->cfg->name); | |
cee53ddb | 4365 | |
cee53ddb | 4366 | /*********************** |
09f9bf79 | 4367 | * 7. Setup Services |
cee53ddb KA |
4368 | * ********************/ |
4369 | ||
4370 | spin_lock_irqsave(&priv->lock, flags); | |
ed3b932e | 4371 | iwl_disable_interrupts(priv); |
cee53ddb KA |
4372 | spin_unlock_irqrestore(&priv->lock, flags); |
4373 | ||
2663516d HS |
4374 | pci_enable_msi(priv->pci_dev); |
4375 | ||
f17d08a6 | 4376 | err = request_irq(priv->pci_dev->irq, iwl_isr, IRQF_SHARED, |
2663516d HS |
4377 | DRV_NAME, priv); |
4378 | if (err) { | |
4379 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
4380 | goto out_disable_msi; | |
4381 | } | |
4382 | ||
cee53ddb | 4383 | err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
849e0dce | 4384 | if (err) { |
15b1687c | 4385 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
90a30a02 | 4386 | goto out_release_irq; |
849e0dce | 4387 | } |
849e0dce | 4388 | |
8ccde88a SO |
4389 | iwl_set_rxon_channel(priv, |
4390 | &priv->bands[IEEE80211_BAND_2GHZ].channels[5]); | |
cee53ddb KA |
4391 | iwl3945_setup_deferred_work(priv); |
4392 | iwl3945_setup_rx_handlers(priv); | |
4393 | ||
cee53ddb | 4394 | /********************************* |
09f9bf79 | 4395 | * 8. Setup and Register mac80211 |
cee53ddb KA |
4396 | * *******************************/ |
4397 | ||
2a4ddaab | 4398 | iwl_enable_interrupts(priv); |
b481de9c | 4399 | |
2a4ddaab AK |
4400 | err = iwl3945_setup_mac(priv); |
4401 | if (err) | |
4402 | goto out_remove_sysfs; | |
cee53ddb | 4403 | |
a75fbe8d AK |
4404 | err = iwl_dbgfs_register(priv, DRV_NAME); |
4405 | if (err) | |
4406 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
4407 | ||
c0af96a6 | 4408 | err = iwl_rfkill_init(priv); |
ebef2008 | 4409 | if (err) |
15b1687c | 4410 | IWL_ERR(priv, "Unable to initialize RFKILL system. " |
ebef2008 | 4411 | "Ignoring error: %d\n", err); |
2a4ddaab AK |
4412 | else |
4413 | iwl_rfkill_set_hw_state(priv); | |
ebef2008 | 4414 | |
2663516d HS |
4415 | /* Start monitoring the killswitch */ |
4416 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, | |
4417 | 2 * HZ); | |
4418 | ||
b481de9c ZY |
4419 | return 0; |
4420 | ||
cee53ddb | 4421 | out_remove_sysfs: |
c8f16138 RC |
4422 | destroy_workqueue(priv->workqueue); |
4423 | priv->workqueue = NULL; | |
cee53ddb | 4424 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 4425 | out_release_irq: |
2663516d | 4426 | free_irq(priv->pci_dev->irq, priv); |
2663516d HS |
4427 | out_disable_msi: |
4428 | pci_disable_msi(priv->pci_dev); | |
c8f16138 RC |
4429 | iwlcore_free_geos(priv); |
4430 | iwl_free_channel_map(priv); | |
4431 | out_unset_hw_params: | |
4432 | iwl3945_unset_hw_params(priv); | |
4433 | out_eeprom_free: | |
4434 | iwl_eeprom_free(priv); | |
b481de9c ZY |
4435 | out_iounmap: |
4436 | pci_iounmap(pdev, priv->hw_base); | |
4437 | out_pci_release_regions: | |
4438 | pci_release_regions(pdev); | |
4439 | out_pci_disable_device: | |
b481de9c | 4440 | pci_set_drvdata(pdev, NULL); |
623d563e | 4441 | pci_disable_device(pdev); |
b481de9c ZY |
4442 | out_ieee80211_free_hw: |
4443 | ieee80211_free_hw(priv->hw); | |
4444 | out: | |
4445 | return err; | |
4446 | } | |
4447 | ||
c83dbf68 | 4448 | static void __devexit iwl3945_pci_remove(struct pci_dev *pdev) |
b481de9c | 4449 | { |
4a8a4322 | 4450 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 4451 | unsigned long flags; |
b481de9c ZY |
4452 | |
4453 | if (!priv) | |
4454 | return; | |
4455 | ||
e1623446 | 4456 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 4457 | |
a75fbe8d AK |
4458 | iwl_dbgfs_unregister(priv); |
4459 | ||
b481de9c | 4460 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
b24d22b1 | 4461 | |
d552bfb6 KA |
4462 | if (priv->mac80211_registered) { |
4463 | ieee80211_unregister_hw(priv->hw); | |
4464 | priv->mac80211_registered = 0; | |
4465 | } else { | |
4466 | iwl3945_down(priv); | |
4467 | } | |
b481de9c | 4468 | |
0359facc MA |
4469 | /* make sure we flush any pending irq or |
4470 | * tasklet for the driver | |
4471 | */ | |
4472 | spin_lock_irqsave(&priv->lock, flags); | |
ed3b932e | 4473 | iwl_disable_interrupts(priv); |
0359facc MA |
4474 | spin_unlock_irqrestore(&priv->lock, flags); |
4475 | ||
4476 | iwl_synchronize_irq(priv); | |
4477 | ||
bb8c093b | 4478 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 4479 | |
c0af96a6 | 4480 | iwl_rfkill_unregister(priv); |
71d449b5 | 4481 | cancel_delayed_work_sync(&priv->rfkill_poll); |
2663516d | 4482 | |
bb8c093b | 4483 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
4484 | |
4485 | if (priv->rxq.bd) | |
df833b1d | 4486 | iwl3945_rx_queue_free(priv, &priv->rxq); |
bb8c093b | 4487 | iwl3945_hw_txq_ctx_free(priv); |
b481de9c | 4488 | |
3832ec9d | 4489 | iwl3945_unset_hw_params(priv); |
40ace5b3 | 4490 | priv->cfg->ops->smgmt->clear_station_table(priv); |
b481de9c | 4491 | |
6ef89d0a MA |
4492 | /*netif_stop_queue(dev); */ |
4493 | flush_workqueue(priv->workqueue); | |
4494 | ||
bb8c093b | 4495 | /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes |
b481de9c ZY |
4496 | * priv->workqueue... so we can't take down the workqueue |
4497 | * until now... */ | |
4498 | destroy_workqueue(priv->workqueue); | |
4499 | priv->workqueue = NULL; | |
4500 | ||
2663516d HS |
4501 | free_irq(pdev->irq, priv); |
4502 | pci_disable_msi(pdev); | |
4503 | ||
b481de9c ZY |
4504 | pci_iounmap(pdev, priv->hw_base); |
4505 | pci_release_regions(pdev); | |
4506 | pci_disable_device(pdev); | |
4507 | pci_set_drvdata(pdev, NULL); | |
4508 | ||
e6148917 | 4509 | iwl_free_channel_map(priv); |
534166de | 4510 | iwlcore_free_geos(priv); |
805cee5b | 4511 | kfree(priv->scan); |
b481de9c ZY |
4512 | if (priv->ibss_beacon) |
4513 | dev_kfree_skb(priv->ibss_beacon); | |
4514 | ||
4515 | ieee80211_free_hw(priv->hw); | |
4516 | } | |
4517 | ||
b481de9c ZY |
4518 | |
4519 | /***************************************************************************** | |
4520 | * | |
4521 | * driver and module entry point | |
4522 | * | |
4523 | *****************************************************************************/ | |
4524 | ||
bb8c093b | 4525 | static struct pci_driver iwl3945_driver = { |
b481de9c | 4526 | .name = DRV_NAME, |
bb8c093b CH |
4527 | .id_table = iwl3945_hw_card_ids, |
4528 | .probe = iwl3945_pci_probe, | |
4529 | .remove = __devexit_p(iwl3945_pci_remove), | |
b481de9c | 4530 | #ifdef CONFIG_PM |
6da3a13e WYG |
4531 | .suspend = iwl_pci_suspend, |
4532 | .resume = iwl_pci_resume, | |
b481de9c ZY |
4533 | #endif |
4534 | }; | |
4535 | ||
bb8c093b | 4536 | static int __init iwl3945_init(void) |
b481de9c ZY |
4537 | { |
4538 | ||
4539 | int ret; | |
4540 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
4541 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 RC |
4542 | |
4543 | ret = iwl3945_rate_control_register(); | |
4544 | if (ret) { | |
a3139c59 SO |
4545 | printk(KERN_ERR DRV_NAME |
4546 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
4547 | return ret; |
4548 | } | |
4549 | ||
bb8c093b | 4550 | ret = pci_register_driver(&iwl3945_driver); |
b481de9c | 4551 | if (ret) { |
a3139c59 | 4552 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 4553 | goto error_register; |
b481de9c | 4554 | } |
b481de9c ZY |
4555 | |
4556 | return ret; | |
897e1cf2 | 4557 | |
897e1cf2 RC |
4558 | error_register: |
4559 | iwl3945_rate_control_unregister(); | |
4560 | return ret; | |
b481de9c ZY |
4561 | } |
4562 | ||
bb8c093b | 4563 | static void __exit iwl3945_exit(void) |
b481de9c | 4564 | { |
bb8c093b | 4565 | pci_unregister_driver(&iwl3945_driver); |
897e1cf2 | 4566 | iwl3945_rate_control_unregister(); |
b481de9c ZY |
4567 | } |
4568 | ||
a0987a8d | 4569 | MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX)); |
25cb6cad | 4570 | |
df878d8f | 4571 | module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444); |
b481de9c | 4572 | MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])"); |
9c74d9fb SO |
4573 | module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, 0444); |
4574 | MODULE_PARM_DESC(swcrypto, | |
4575 | "using software crypto (default 1 [software])\n"); | |
df878d8f | 4576 | module_param_named(debug, iwl3945_mod_params.debug, uint, 0444); |
b481de9c | 4577 | MODULE_PARM_DESC(debug, "debug output mask"); |
df878d8f | 4578 | module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444); |
b481de9c ZY |
4579 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); |
4580 | ||
df878d8f | 4581 | module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444); |
b481de9c ZY |
4582 | MODULE_PARM_DESC(queues_num, "number of hw queues."); |
4583 | ||
af48d048 SO |
4584 | module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, 0444); |
4585 | MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error"); | |
4586 | ||
bb8c093b CH |
4587 | module_exit(iwl3945_exit); |
4588 | module_init(iwl3945_init); |