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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
eb7ae89c | 3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/version.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/netdevice.h> | |
39 | #include <linux/wireless.h> | |
40 | #include <linux/firmware.h> | |
b481de9c ZY |
41 | #include <linux/etherdevice.h> |
42 | #include <linux/if_arp.h> | |
43 | ||
44 | #include <net/ieee80211_radiotap.h> | |
45 | #include <net/mac80211.h> | |
46 | ||
47 | #include <asm/div64.h> | |
48 | ||
82b9a121 | 49 | #include "iwl-3945-core.h" |
b481de9c ZY |
50 | #include "iwl-3945.h" |
51 | #include "iwl-helpers.h" | |
52 | ||
c8b0e6e1 | 53 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 54 | u32 iwl3945_debug_level; |
b481de9c ZY |
55 | #endif |
56 | ||
bb8c093b CH |
57 | static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv, |
58 | struct iwl3945_tx_queue *txq); | |
416e1438 | 59 | |
b481de9c ZY |
60 | /****************************************************************************** |
61 | * | |
62 | * module boiler plate | |
63 | * | |
64 | ******************************************************************************/ | |
65 | ||
66 | /* module parameters */ | |
6440adb5 CB |
67 | static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */ |
68 | static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */ | |
69 | static int iwl3945_param_disable; /* def: 0 = enable radio */ | |
9fbab516 | 70 | static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */ |
6440adb5 CB |
71 | int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */ |
72 | static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */ | |
73 | int iwl3945_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 8 Tx queues */ | |
b481de9c ZY |
74 | |
75 | /* | |
76 | * module name, copyright, version, etc. | |
77 | * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk | |
78 | */ | |
79 | ||
80 | #define DRV_DESCRIPTION \ | |
81 | "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux" | |
82 | ||
c8b0e6e1 | 83 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
84 | #define VD "d" |
85 | #else | |
86 | #define VD | |
87 | #endif | |
88 | ||
c8b0e6e1 | 89 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
90 | #define VS "s" |
91 | #else | |
92 | #define VS | |
93 | #endif | |
94 | ||
b9e0b449 | 95 | #define IWLWIFI_VERSION "1.2.26k" VD VS |
eb7ae89c | 96 | #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation" |
b481de9c ZY |
97 | #define DRV_VERSION IWLWIFI_VERSION |
98 | ||
b481de9c ZY |
99 | |
100 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
101 | MODULE_VERSION(DRV_VERSION); | |
102 | MODULE_AUTHOR(DRV_COPYRIGHT); | |
103 | MODULE_LICENSE("GPL"); | |
104 | ||
416e1438 | 105 | static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr) |
b481de9c ZY |
106 | { |
107 | u16 fc = le16_to_cpu(hdr->frame_control); | |
108 | int hdr_len = ieee80211_get_hdrlen(fc); | |
109 | ||
110 | if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA)) | |
111 | return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN); | |
112 | return NULL; | |
113 | } | |
114 | ||
8318d78a JB |
115 | static const struct ieee80211_supported_band *iwl3945_get_band( |
116 | struct iwl3945_priv *priv, enum ieee80211_band band) | |
b481de9c | 117 | { |
8318d78a | 118 | return priv->hw->wiphy->bands[band]; |
b481de9c ZY |
119 | } |
120 | ||
bb8c093b | 121 | static int iwl3945_is_empty_essid(const char *essid, int essid_len) |
b481de9c ZY |
122 | { |
123 | /* Single white space is for Linksys APs */ | |
124 | if (essid_len == 1 && essid[0] == ' ') | |
125 | return 1; | |
126 | ||
127 | /* Otherwise, if the entire essid is 0, we assume it is hidden */ | |
128 | while (essid_len) { | |
129 | essid_len--; | |
130 | if (essid[essid_len] != '\0') | |
131 | return 0; | |
132 | } | |
133 | ||
134 | return 1; | |
135 | } | |
136 | ||
bb8c093b | 137 | static const char *iwl3945_escape_essid(const char *essid, u8 essid_len) |
b481de9c ZY |
138 | { |
139 | static char escaped[IW_ESSID_MAX_SIZE * 2 + 1]; | |
140 | const char *s = essid; | |
141 | char *d = escaped; | |
142 | ||
bb8c093b | 143 | if (iwl3945_is_empty_essid(essid, essid_len)) { |
b481de9c ZY |
144 | memcpy(escaped, "<hidden>", sizeof("<hidden>")); |
145 | return escaped; | |
146 | } | |
147 | ||
148 | essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE); | |
149 | while (essid_len--) { | |
150 | if (*s == '\0') { | |
151 | *d++ = '\\'; | |
152 | *d++ = '0'; | |
153 | s++; | |
154 | } else | |
155 | *d++ = *s++; | |
156 | } | |
157 | *d = '\0'; | |
158 | return escaped; | |
159 | } | |
160 | ||
b481de9c ZY |
161 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
162 | * DMA services | |
163 | * | |
164 | * Theory of operation | |
165 | * | |
6440adb5 CB |
166 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer |
167 | * of buffer descriptors, each of which points to one or more data buffers for | |
168 | * the device to read from or fill. Driver and device exchange status of each | |
169 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
170 | * entries in each circular buffer, to protect against confusing empty and full | |
171 | * queue states. | |
172 | * | |
173 | * The device reads or writes the data in the queues via the device's several | |
174 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
b481de9c ZY |
175 | * |
176 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
177 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
178 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
179 | * Tx queue resumed. | |
180 | * | |
6440adb5 CB |
181 | * The 3945 operates with six queues: One receive queue, one transmit queue |
182 | * (#4) for sending commands to the device firmware, and four transmit queues | |
183 | * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused. | |
b481de9c ZY |
184 | ***************************************************/ |
185 | ||
c54b679d | 186 | int iwl3945_queue_space(const struct iwl3945_queue *q) |
b481de9c | 187 | { |
fc4b6853 | 188 | int s = q->read_ptr - q->write_ptr; |
b481de9c | 189 | |
fc4b6853 | 190 | if (q->read_ptr > q->write_ptr) |
b481de9c ZY |
191 | s -= q->n_bd; |
192 | ||
193 | if (s <= 0) | |
194 | s += q->n_window; | |
195 | /* keep some reserve to not confuse empty and full situations */ | |
196 | s -= 2; | |
197 | if (s < 0) | |
198 | s = 0; | |
199 | return s; | |
200 | } | |
201 | ||
c54b679d | 202 | int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i) |
b481de9c | 203 | { |
fc4b6853 TW |
204 | return q->write_ptr > q->read_ptr ? |
205 | (i >= q->read_ptr && i < q->write_ptr) : | |
206 | !(i < q->read_ptr && i >= q->write_ptr); | |
b481de9c ZY |
207 | } |
208 | ||
c54b679d | 209 | |
bb8c093b | 210 | static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge) |
b481de9c | 211 | { |
6440adb5 | 212 | /* This is for scan command, the big buffer at end of command array */ |
b481de9c | 213 | if (is_huge) |
6440adb5 | 214 | return q->n_window; /* must be power of 2 */ |
b481de9c | 215 | |
6440adb5 | 216 | /* Otherwise, use normal size buffers */ |
b481de9c ZY |
217 | return index & (q->n_window - 1); |
218 | } | |
219 | ||
6440adb5 CB |
220 | /** |
221 | * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes | |
222 | */ | |
bb8c093b | 223 | static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q, |
b481de9c ZY |
224 | int count, int slots_num, u32 id) |
225 | { | |
226 | q->n_bd = count; | |
227 | q->n_window = slots_num; | |
228 | q->id = id; | |
229 | ||
c54b679d TW |
230 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap |
231 | * and iwl_queue_dec_wrap are broken. */ | |
b481de9c ZY |
232 | BUG_ON(!is_power_of_2(count)); |
233 | ||
234 | /* slots_num must be power-of-two size, otherwise | |
235 | * get_cmd_index is broken. */ | |
236 | BUG_ON(!is_power_of_2(slots_num)); | |
237 | ||
238 | q->low_mark = q->n_window / 4; | |
239 | if (q->low_mark < 4) | |
240 | q->low_mark = 4; | |
241 | ||
242 | q->high_mark = q->n_window / 8; | |
243 | if (q->high_mark < 2) | |
244 | q->high_mark = 2; | |
245 | ||
fc4b6853 | 246 | q->write_ptr = q->read_ptr = 0; |
b481de9c ZY |
247 | |
248 | return 0; | |
249 | } | |
250 | ||
6440adb5 CB |
251 | /** |
252 | * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
253 | */ | |
bb8c093b CH |
254 | static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv, |
255 | struct iwl3945_tx_queue *txq, u32 id) | |
b481de9c ZY |
256 | { |
257 | struct pci_dev *dev = priv->pci_dev; | |
258 | ||
6440adb5 CB |
259 | /* Driver private data, only for Tx (not command) queues, |
260 | * not shared with device. */ | |
b481de9c ZY |
261 | if (id != IWL_CMD_QUEUE_NUM) { |
262 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
263 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
264 | if (!txq->txb) { | |
01ebd063 | 265 | IWL_ERROR("kmalloc for auxiliary BD " |
b481de9c ZY |
266 | "structures failed\n"); |
267 | goto error; | |
268 | } | |
269 | } else | |
270 | txq->txb = NULL; | |
271 | ||
6440adb5 CB |
272 | /* Circular buffer of transmit frame descriptors (TFDs), |
273 | * shared with device */ | |
b481de9c ZY |
274 | txq->bd = pci_alloc_consistent(dev, |
275 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX, | |
276 | &txq->q.dma_addr); | |
277 | ||
278 | if (!txq->bd) { | |
279 | IWL_ERROR("pci_alloc_consistent(%zd) failed\n", | |
280 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX); | |
281 | goto error; | |
282 | } | |
283 | txq->q.id = id; | |
284 | ||
285 | return 0; | |
286 | ||
287 | error: | |
288 | if (txq->txb) { | |
289 | kfree(txq->txb); | |
290 | txq->txb = NULL; | |
291 | } | |
292 | ||
293 | return -ENOMEM; | |
294 | } | |
295 | ||
6440adb5 CB |
296 | /** |
297 | * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue | |
298 | */ | |
bb8c093b CH |
299 | int iwl3945_tx_queue_init(struct iwl3945_priv *priv, |
300 | struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id) | |
b481de9c ZY |
301 | { |
302 | struct pci_dev *dev = priv->pci_dev; | |
303 | int len; | |
304 | int rc = 0; | |
305 | ||
6440adb5 CB |
306 | /* |
307 | * Alloc buffer array for commands (Tx or other types of commands). | |
308 | * For the command queue (#4), allocate command space + one big | |
309 | * command for scan, since scan command is very huge; the system will | |
310 | * not have two scans at the same time, so only one is needed. | |
311 | * For data Tx queues (all other queues), no super-size command | |
312 | * space is needed. | |
313 | */ | |
bb8c093b | 314 | len = sizeof(struct iwl3945_cmd) * slots_num; |
b481de9c ZY |
315 | if (txq_id == IWL_CMD_QUEUE_NUM) |
316 | len += IWL_MAX_SCAN_SIZE; | |
317 | txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd); | |
318 | if (!txq->cmd) | |
319 | return -ENOMEM; | |
320 | ||
6440adb5 | 321 | /* Alloc driver data array and TFD circular buffer */ |
bb8c093b | 322 | rc = iwl3945_tx_queue_alloc(priv, txq, txq_id); |
b481de9c ZY |
323 | if (rc) { |
324 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); | |
325 | ||
326 | return -ENOMEM; | |
327 | } | |
328 | txq->need_update = 0; | |
329 | ||
330 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
c54b679d | 331 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ |
b481de9c | 332 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); |
6440adb5 CB |
333 | |
334 | /* Initialize queue high/low-water, head/tail indexes */ | |
bb8c093b | 335 | iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
b481de9c | 336 | |
6440adb5 | 337 | /* Tell device where to find queue, enable DMA channel. */ |
bb8c093b | 338 | iwl3945_hw_tx_queue_init(priv, txq); |
b481de9c ZY |
339 | |
340 | return 0; | |
341 | } | |
342 | ||
343 | /** | |
bb8c093b | 344 | * iwl3945_tx_queue_free - Deallocate DMA queue. |
b481de9c ZY |
345 | * @txq: Transmit queue to deallocate. |
346 | * | |
347 | * Empty queue by removing and destroying all BD's. | |
6440adb5 CB |
348 | * Free all buffers. |
349 | * 0-fill, but do not free "txq" descriptor structure. | |
b481de9c | 350 | */ |
bb8c093b | 351 | void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq) |
b481de9c | 352 | { |
bb8c093b | 353 | struct iwl3945_queue *q = &txq->q; |
b481de9c ZY |
354 | struct pci_dev *dev = priv->pci_dev; |
355 | int len; | |
356 | ||
357 | if (q->n_bd == 0) | |
358 | return; | |
359 | ||
360 | /* first, empty all BD's */ | |
fc4b6853 | 361 | for (; q->write_ptr != q->read_ptr; |
c54b679d | 362 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) |
bb8c093b | 363 | iwl3945_hw_txq_free_tfd(priv, txq); |
b481de9c | 364 | |
bb8c093b | 365 | len = sizeof(struct iwl3945_cmd) * q->n_window; |
b481de9c ZY |
366 | if (q->id == IWL_CMD_QUEUE_NUM) |
367 | len += IWL_MAX_SCAN_SIZE; | |
368 | ||
6440adb5 | 369 | /* De-alloc array of command/tx buffers */ |
b481de9c ZY |
370 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); |
371 | ||
6440adb5 | 372 | /* De-alloc circular buffer of TFDs */ |
b481de9c | 373 | if (txq->q.n_bd) |
bb8c093b | 374 | pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) * |
b481de9c ZY |
375 | txq->q.n_bd, txq->bd, txq->q.dma_addr); |
376 | ||
6440adb5 | 377 | /* De-alloc array of per-TFD driver data */ |
b481de9c ZY |
378 | if (txq->txb) { |
379 | kfree(txq->txb); | |
380 | txq->txb = NULL; | |
381 | } | |
382 | ||
6440adb5 | 383 | /* 0-fill queue descriptor structure */ |
b481de9c ZY |
384 | memset(txq, 0, sizeof(*txq)); |
385 | } | |
386 | ||
bb8c093b | 387 | const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
b481de9c ZY |
388 | |
389 | /*************** STATION TABLE MANAGEMENT **** | |
9fbab516 | 390 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
391 | * the functionality provided here |
392 | */ | |
393 | ||
394 | /**************************************************************/ | |
01ebd063 | 395 | #if 0 /* temporary disable till we add real remove station */ |
6440adb5 CB |
396 | /** |
397 | * iwl3945_remove_station - Remove driver's knowledge of station. | |
398 | * | |
399 | * NOTE: This does not remove station from device's station table. | |
400 | */ | |
bb8c093b | 401 | static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap) |
b481de9c ZY |
402 | { |
403 | int index = IWL_INVALID_STATION; | |
404 | int i; | |
405 | unsigned long flags; | |
406 | ||
407 | spin_lock_irqsave(&priv->sta_lock, flags); | |
408 | ||
409 | if (is_ap) | |
410 | index = IWL_AP_ID; | |
411 | else if (is_broadcast_ether_addr(addr)) | |
412 | index = priv->hw_setting.bcast_sta_id; | |
413 | else | |
414 | for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) | |
415 | if (priv->stations[i].used && | |
416 | !compare_ether_addr(priv->stations[i].sta.sta.addr, | |
417 | addr)) { | |
418 | index = i; | |
419 | break; | |
420 | } | |
421 | ||
422 | if (unlikely(index == IWL_INVALID_STATION)) | |
423 | goto out; | |
424 | ||
425 | if (priv->stations[index].used) { | |
426 | priv->stations[index].used = 0; | |
427 | priv->num_stations--; | |
428 | } | |
429 | ||
430 | BUG_ON(priv->num_stations < 0); | |
431 | ||
432 | out: | |
433 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
434 | return 0; | |
435 | } | |
556f8db7 | 436 | #endif |
6440adb5 CB |
437 | |
438 | /** | |
439 | * iwl3945_clear_stations_table - Clear the driver's station table | |
440 | * | |
441 | * NOTE: This does not clear or otherwise alter the device's station table. | |
442 | */ | |
bb8c093b | 443 | static void iwl3945_clear_stations_table(struct iwl3945_priv *priv) |
b481de9c ZY |
444 | { |
445 | unsigned long flags; | |
446 | ||
447 | spin_lock_irqsave(&priv->sta_lock, flags); | |
448 | ||
449 | priv->num_stations = 0; | |
450 | memset(priv->stations, 0, sizeof(priv->stations)); | |
451 | ||
452 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
453 | } | |
454 | ||
6440adb5 CB |
455 | /** |
456 | * iwl3945_add_station - Add station to station tables in driver and device | |
457 | */ | |
bb8c093b | 458 | u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags) |
b481de9c ZY |
459 | { |
460 | int i; | |
461 | int index = IWL_INVALID_STATION; | |
bb8c093b | 462 | struct iwl3945_station_entry *station; |
b481de9c | 463 | unsigned long flags_spin; |
0795af57 | 464 | DECLARE_MAC_BUF(mac); |
c14c521e | 465 | u8 rate; |
b481de9c ZY |
466 | |
467 | spin_lock_irqsave(&priv->sta_lock, flags_spin); | |
468 | if (is_ap) | |
469 | index = IWL_AP_ID; | |
470 | else if (is_broadcast_ether_addr(addr)) | |
471 | index = priv->hw_setting.bcast_sta_id; | |
472 | else | |
473 | for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) { | |
474 | if (!compare_ether_addr(priv->stations[i].sta.sta.addr, | |
475 | addr)) { | |
476 | index = i; | |
477 | break; | |
478 | } | |
479 | ||
480 | if (!priv->stations[i].used && | |
481 | index == IWL_INVALID_STATION) | |
482 | index = i; | |
483 | } | |
484 | ||
01ebd063 | 485 | /* These two conditions has the same outcome but keep them separate |
b481de9c ZY |
486 | since they have different meaning */ |
487 | if (unlikely(index == IWL_INVALID_STATION)) { | |
488 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
489 | return index; | |
490 | } | |
491 | ||
492 | if (priv->stations[index].used && | |
493 | !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) { | |
494 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
495 | return index; | |
496 | } | |
497 | ||
0795af57 | 498 | IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr)); |
b481de9c ZY |
499 | station = &priv->stations[index]; |
500 | station->used = 1; | |
501 | priv->num_stations++; | |
502 | ||
6440adb5 | 503 | /* Set up the REPLY_ADD_STA command to send to device */ |
bb8c093b | 504 | memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd)); |
b481de9c ZY |
505 | memcpy(station->sta.sta.addr, addr, ETH_ALEN); |
506 | station->sta.mode = 0; | |
507 | station->sta.sta.sta_id = index; | |
508 | station->sta.station_flags = 0; | |
509 | ||
8318d78a | 510 | if (priv->band == IEEE80211_BAND_5GHZ) |
69946333 TW |
511 | rate = IWL_RATE_6M_PLCP; |
512 | else | |
513 | rate = IWL_RATE_1M_PLCP; | |
c14c521e ZY |
514 | |
515 | /* Turn on both antennas for the station... */ | |
516 | station->sta.rate_n_flags = | |
bb8c093b | 517 | iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK); |
c14c521e ZY |
518 | station->current_rate.rate_n_flags = |
519 | le16_to_cpu(station->sta.rate_n_flags); | |
520 | ||
b481de9c | 521 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); |
6440adb5 CB |
522 | |
523 | /* Add station to device's station table */ | |
bb8c093b | 524 | iwl3945_send_add_station(priv, &station->sta, flags); |
b481de9c ZY |
525 | return index; |
526 | ||
527 | } | |
528 | ||
529 | /*************** DRIVER STATUS FUNCTIONS *****/ | |
530 | ||
bb8c093b | 531 | static inline int iwl3945_is_ready(struct iwl3945_priv *priv) |
b481de9c ZY |
532 | { |
533 | /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are | |
534 | * set but EXIT_PENDING is not */ | |
535 | return test_bit(STATUS_READY, &priv->status) && | |
536 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) && | |
537 | !test_bit(STATUS_EXIT_PENDING, &priv->status); | |
538 | } | |
539 | ||
bb8c093b | 540 | static inline int iwl3945_is_alive(struct iwl3945_priv *priv) |
b481de9c ZY |
541 | { |
542 | return test_bit(STATUS_ALIVE, &priv->status); | |
543 | } | |
544 | ||
bb8c093b | 545 | static inline int iwl3945_is_init(struct iwl3945_priv *priv) |
b481de9c ZY |
546 | { |
547 | return test_bit(STATUS_INIT, &priv->status); | |
548 | } | |
549 | ||
bb8c093b | 550 | static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv) |
b481de9c ZY |
551 | { |
552 | return test_bit(STATUS_RF_KILL_HW, &priv->status) || | |
553 | test_bit(STATUS_RF_KILL_SW, &priv->status); | |
554 | } | |
555 | ||
bb8c093b | 556 | static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv) |
b481de9c ZY |
557 | { |
558 | ||
bb8c093b | 559 | if (iwl3945_is_rfkill(priv)) |
b481de9c ZY |
560 | return 0; |
561 | ||
bb8c093b | 562 | return iwl3945_is_ready(priv); |
b481de9c ZY |
563 | } |
564 | ||
565 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
566 | ||
567 | #define IWL_CMD(x) case x : return #x | |
568 | ||
569 | static const char *get_cmd_string(u8 cmd) | |
570 | { | |
571 | switch (cmd) { | |
572 | IWL_CMD(REPLY_ALIVE); | |
573 | IWL_CMD(REPLY_ERROR); | |
574 | IWL_CMD(REPLY_RXON); | |
575 | IWL_CMD(REPLY_RXON_ASSOC); | |
576 | IWL_CMD(REPLY_QOS_PARAM); | |
577 | IWL_CMD(REPLY_RXON_TIMING); | |
578 | IWL_CMD(REPLY_ADD_STA); | |
579 | IWL_CMD(REPLY_REMOVE_STA); | |
580 | IWL_CMD(REPLY_REMOVE_ALL_STA); | |
581 | IWL_CMD(REPLY_3945_RX); | |
582 | IWL_CMD(REPLY_TX); | |
583 | IWL_CMD(REPLY_RATE_SCALE); | |
584 | IWL_CMD(REPLY_LEDS_CMD); | |
585 | IWL_CMD(REPLY_TX_LINK_QUALITY_CMD); | |
586 | IWL_CMD(RADAR_NOTIFICATION); | |
587 | IWL_CMD(REPLY_QUIET_CMD); | |
588 | IWL_CMD(REPLY_CHANNEL_SWITCH); | |
589 | IWL_CMD(CHANNEL_SWITCH_NOTIFICATION); | |
590 | IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD); | |
591 | IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION); | |
592 | IWL_CMD(POWER_TABLE_CMD); | |
593 | IWL_CMD(PM_SLEEP_NOTIFICATION); | |
594 | IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC); | |
595 | IWL_CMD(REPLY_SCAN_CMD); | |
596 | IWL_CMD(REPLY_SCAN_ABORT_CMD); | |
597 | IWL_CMD(SCAN_START_NOTIFICATION); | |
598 | IWL_CMD(SCAN_RESULTS_NOTIFICATION); | |
599 | IWL_CMD(SCAN_COMPLETE_NOTIFICATION); | |
600 | IWL_CMD(BEACON_NOTIFICATION); | |
601 | IWL_CMD(REPLY_TX_BEACON); | |
602 | IWL_CMD(WHO_IS_AWAKE_NOTIFICATION); | |
603 | IWL_CMD(QUIET_NOTIFICATION); | |
604 | IWL_CMD(REPLY_TX_PWR_TABLE_CMD); | |
605 | IWL_CMD(MEASURE_ABORT_NOTIFICATION); | |
606 | IWL_CMD(REPLY_BT_CONFIG); | |
607 | IWL_CMD(REPLY_STATISTICS_CMD); | |
608 | IWL_CMD(STATISTICS_NOTIFICATION); | |
609 | IWL_CMD(REPLY_CARD_STATE_CMD); | |
610 | IWL_CMD(CARD_STATE_NOTIFICATION); | |
611 | IWL_CMD(MISSED_BEACONS_NOTIFICATION); | |
612 | default: | |
613 | return "UNKNOWN"; | |
614 | ||
615 | } | |
616 | } | |
617 | ||
618 | #define HOST_COMPLETE_TIMEOUT (HZ / 2) | |
619 | ||
620 | /** | |
bb8c093b | 621 | * iwl3945_enqueue_hcmd - enqueue a uCode command |
b481de9c ZY |
622 | * @priv: device private data point |
623 | * @cmd: a point to the ucode command structure | |
624 | * | |
625 | * The function returns < 0 values to indicate the operation is | |
626 | * failed. On success, it turns the index (> 0) of command in the | |
627 | * command queue. | |
628 | */ | |
bb8c093b | 629 | static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c | 630 | { |
bb8c093b CH |
631 | struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; |
632 | struct iwl3945_queue *q = &txq->q; | |
633 | struct iwl3945_tfd_frame *tfd; | |
b481de9c | 634 | u32 *control_flags; |
bb8c093b | 635 | struct iwl3945_cmd *out_cmd; |
b481de9c ZY |
636 | u32 idx; |
637 | u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
638 | dma_addr_t phys_addr; | |
639 | int pad; | |
640 | u16 count; | |
641 | int ret; | |
642 | unsigned long flags; | |
643 | ||
644 | /* If any of the command structures end up being larger than | |
645 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
646 | * we will need to increase the size of the TFD entries */ | |
647 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
648 | !(cmd->meta.flags & CMD_SIZE_HUGE)); | |
649 | ||
c342a1b9 GG |
650 | |
651 | if (iwl3945_is_rfkill(priv)) { | |
652 | IWL_DEBUG_INFO("Not sending command - RF KILL"); | |
653 | return -EIO; | |
654 | } | |
655 | ||
bb8c093b | 656 | if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) { |
b481de9c ZY |
657 | IWL_ERROR("No space for Tx\n"); |
658 | return -ENOSPC; | |
659 | } | |
660 | ||
661 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
662 | ||
fc4b6853 | 663 | tfd = &txq->bd[q->write_ptr]; |
b481de9c ZY |
664 | memset(tfd, 0, sizeof(*tfd)); |
665 | ||
666 | control_flags = (u32 *) tfd; | |
667 | ||
fc4b6853 | 668 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); |
b481de9c ZY |
669 | out_cmd = &txq->cmd[idx]; |
670 | ||
671 | out_cmd->hdr.cmd = cmd->id; | |
672 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); | |
673 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
674 | ||
675 | /* At this point, the out_cmd now has all of the incoming cmd | |
676 | * information */ | |
677 | ||
678 | out_cmd->hdr.flags = 0; | |
679 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
fc4b6853 | 680 | INDEX_TO_SEQ(q->write_ptr)); |
b481de9c ZY |
681 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) |
682 | out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME); | |
683 | ||
684 | phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx + | |
bb8c093b CH |
685 | offsetof(struct iwl3945_cmd, hdr); |
686 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size); | |
b481de9c ZY |
687 | |
688 | pad = U32_PAD(cmd->len); | |
689 | count = TFD_CTL_COUNT_GET(*control_flags); | |
690 | *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad); | |
691 | ||
692 | IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, " | |
693 | "%d bytes at %d[%d]:%d\n", | |
694 | get_cmd_string(out_cmd->hdr.cmd), | |
695 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), | |
fc4b6853 | 696 | fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM); |
b481de9c ZY |
697 | |
698 | txq->need_update = 1; | |
6440adb5 CB |
699 | |
700 | /* Increment and update queue's write index */ | |
c54b679d | 701 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
bb8c093b | 702 | ret = iwl3945_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
703 | |
704 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
705 | return ret ? ret : idx; | |
706 | } | |
707 | ||
bb8c093b | 708 | static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c ZY |
709 | { |
710 | int ret; | |
711 | ||
712 | BUG_ON(!(cmd->meta.flags & CMD_ASYNC)); | |
713 | ||
714 | /* An asynchronous command can not expect an SKB to be set. */ | |
715 | BUG_ON(cmd->meta.flags & CMD_WANT_SKB); | |
716 | ||
717 | /* An asynchronous command MUST have a callback. */ | |
718 | BUG_ON(!cmd->meta.u.callback); | |
719 | ||
720 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
721 | return -EBUSY; | |
722 | ||
bb8c093b | 723 | ret = iwl3945_enqueue_hcmd(priv, cmd); |
b481de9c | 724 | if (ret < 0) { |
bb8c093b | 725 | IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n", |
b481de9c ZY |
726 | get_cmd_string(cmd->id), ret); |
727 | return ret; | |
728 | } | |
729 | return 0; | |
730 | } | |
731 | ||
bb8c093b | 732 | static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c ZY |
733 | { |
734 | int cmd_idx; | |
735 | int ret; | |
b481de9c ZY |
736 | |
737 | BUG_ON(cmd->meta.flags & CMD_ASYNC); | |
738 | ||
739 | /* A synchronous command can not have a callback set. */ | |
740 | BUG_ON(cmd->meta.u.callback != NULL); | |
741 | ||
e5472978 | 742 | if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) { |
b481de9c ZY |
743 | IWL_ERROR("Error sending %s: Already sending a host command\n", |
744 | get_cmd_string(cmd->id)); | |
e5472978 TW |
745 | ret = -EBUSY; |
746 | goto out; | |
b481de9c ZY |
747 | } |
748 | ||
749 | set_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
750 | ||
751 | if (cmd->meta.flags & CMD_WANT_SKB) | |
752 | cmd->meta.source = &cmd->meta; | |
753 | ||
bb8c093b | 754 | cmd_idx = iwl3945_enqueue_hcmd(priv, cmd); |
b481de9c ZY |
755 | if (cmd_idx < 0) { |
756 | ret = cmd_idx; | |
bb8c093b | 757 | IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n", |
b481de9c ZY |
758 | get_cmd_string(cmd->id), ret); |
759 | goto out; | |
760 | } | |
761 | ||
762 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
763 | !test_bit(STATUS_HCMD_ACTIVE, &priv->status), | |
764 | HOST_COMPLETE_TIMEOUT); | |
765 | if (!ret) { | |
766 | if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) { | |
767 | IWL_ERROR("Error sending %s: time out after %dms.\n", | |
768 | get_cmd_string(cmd->id), | |
769 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
770 | ||
771 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
772 | ret = -ETIMEDOUT; | |
773 | goto cancel; | |
774 | } | |
775 | } | |
776 | ||
777 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
778 | IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n", | |
779 | get_cmd_string(cmd->id)); | |
780 | ret = -ECANCELED; | |
781 | goto fail; | |
782 | } | |
783 | if (test_bit(STATUS_FW_ERROR, &priv->status)) { | |
784 | IWL_DEBUG_INFO("Command %s failed: FW Error\n", | |
785 | get_cmd_string(cmd->id)); | |
786 | ret = -EIO; | |
787 | goto fail; | |
788 | } | |
789 | if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) { | |
790 | IWL_ERROR("Error: Response NULL in '%s'\n", | |
791 | get_cmd_string(cmd->id)); | |
792 | ret = -EIO; | |
793 | goto out; | |
794 | } | |
795 | ||
796 | ret = 0; | |
797 | goto out; | |
798 | ||
799 | cancel: | |
800 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
bb8c093b | 801 | struct iwl3945_cmd *qcmd; |
b481de9c ZY |
802 | |
803 | /* Cancel the CMD_WANT_SKB flag for the cmd in the | |
804 | * TX cmd queue. Otherwise in case the cmd comes | |
805 | * in later, it will possibly set an invalid | |
806 | * address (cmd->meta.source). */ | |
807 | qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx]; | |
808 | qcmd->meta.flags &= ~CMD_WANT_SKB; | |
809 | } | |
810 | fail: | |
811 | if (cmd->meta.u.skb) { | |
812 | dev_kfree_skb_any(cmd->meta.u.skb); | |
813 | cmd->meta.u.skb = NULL; | |
814 | } | |
815 | out: | |
e5472978 | 816 | clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status); |
b481de9c ZY |
817 | return ret; |
818 | } | |
819 | ||
bb8c093b | 820 | int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd) |
b481de9c | 821 | { |
b481de9c | 822 | if (cmd->meta.flags & CMD_ASYNC) |
bb8c093b | 823 | return iwl3945_send_cmd_async(priv, cmd); |
b481de9c | 824 | |
bb8c093b | 825 | return iwl3945_send_cmd_sync(priv, cmd); |
b481de9c ZY |
826 | } |
827 | ||
bb8c093b | 828 | int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data) |
b481de9c | 829 | { |
bb8c093b | 830 | struct iwl3945_host_cmd cmd = { |
b481de9c ZY |
831 | .id = id, |
832 | .len = len, | |
833 | .data = data, | |
834 | }; | |
835 | ||
bb8c093b | 836 | return iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
837 | } |
838 | ||
bb8c093b | 839 | static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val) |
b481de9c | 840 | { |
bb8c093b | 841 | struct iwl3945_host_cmd cmd = { |
b481de9c ZY |
842 | .id = id, |
843 | .len = sizeof(val), | |
844 | .data = &val, | |
845 | }; | |
846 | ||
bb8c093b | 847 | return iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
848 | } |
849 | ||
bb8c093b | 850 | int iwl3945_send_statistics_request(struct iwl3945_priv *priv) |
b481de9c | 851 | { |
bb8c093b | 852 | return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0); |
b481de9c ZY |
853 | } |
854 | ||
b481de9c | 855 | /** |
bb8c093b | 856 | * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON |
8318d78a JB |
857 | * @band: 2.4 or 5 GHz band |
858 | * @channel: Any channel valid for the requested band | |
b481de9c | 859 | |
8318d78a | 860 | * In addition to setting the staging RXON, priv->band is also set. |
b481de9c ZY |
861 | * |
862 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields | |
8318d78a | 863 | * in the staging RXON flag structure based on the band |
b481de9c | 864 | */ |
8318d78a JB |
865 | static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv, |
866 | enum ieee80211_band band, | |
867 | u16 channel) | |
b481de9c | 868 | { |
8318d78a | 869 | if (!iwl3945_get_channel_info(priv, band, channel)) { |
b481de9c | 870 | IWL_DEBUG_INFO("Could not set channel to %d [%d]\n", |
8318d78a | 871 | channel, band); |
b481de9c ZY |
872 | return -EINVAL; |
873 | } | |
874 | ||
875 | if ((le16_to_cpu(priv->staging_rxon.channel) == channel) && | |
8318d78a | 876 | (priv->band == band)) |
b481de9c ZY |
877 | return 0; |
878 | ||
879 | priv->staging_rxon.channel = cpu_to_le16(channel); | |
8318d78a | 880 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
881 | priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK; |
882 | else | |
883 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
884 | ||
8318d78a | 885 | priv->band = band; |
b481de9c | 886 | |
8318d78a | 887 | IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band); |
b481de9c ZY |
888 | |
889 | return 0; | |
890 | } | |
891 | ||
892 | /** | |
bb8c093b | 893 | * iwl3945_check_rxon_cmd - validate RXON structure is valid |
b481de9c ZY |
894 | * |
895 | * NOTE: This is really only useful during development and can eventually | |
896 | * be #ifdef'd out once the driver is stable and folks aren't actively | |
897 | * making changes | |
898 | */ | |
bb8c093b | 899 | static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon) |
b481de9c ZY |
900 | { |
901 | int error = 0; | |
902 | int counter = 1; | |
903 | ||
904 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
905 | error |= le32_to_cpu(rxon->flags & | |
906 | (RXON_FLG_TGJ_NARROW_BAND_MSK | | |
907 | RXON_FLG_RADAR_DETECT_MSK)); | |
908 | if (error) | |
909 | IWL_WARNING("check 24G fields %d | %d\n", | |
910 | counter++, error); | |
911 | } else { | |
912 | error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ? | |
913 | 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK); | |
914 | if (error) | |
915 | IWL_WARNING("check 52 fields %d | %d\n", | |
916 | counter++, error); | |
917 | error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK); | |
918 | if (error) | |
919 | IWL_WARNING("check 52 CCK %d | %d\n", | |
920 | counter++, error); | |
921 | } | |
922 | error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1; | |
923 | if (error) | |
924 | IWL_WARNING("check mac addr %d | %d\n", counter++, error); | |
925 | ||
926 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
927 | error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) && | |
928 | ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0)); | |
929 | if (error) | |
930 | IWL_WARNING("check basic rate %d | %d\n", counter++, error); | |
931 | ||
932 | error |= (le16_to_cpu(rxon->assoc_id) > 2007); | |
933 | if (error) | |
934 | IWL_WARNING("check assoc id %d | %d\n", counter++, error); | |
935 | ||
936 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) | |
937 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)); | |
938 | if (error) | |
939 | IWL_WARNING("check CCK and short slot %d | %d\n", | |
940 | counter++, error); | |
941 | ||
942 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) | |
943 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)); | |
944 | if (error) | |
945 | IWL_WARNING("check CCK & auto detect %d | %d\n", | |
946 | counter++, error); | |
947 | ||
948 | error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | | |
949 | RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK); | |
950 | if (error) | |
951 | IWL_WARNING("check TGG and auto detect %d | %d\n", | |
952 | counter++, error); | |
953 | ||
954 | if ((rxon->flags & RXON_FLG_DIS_DIV_MSK)) | |
955 | error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK | | |
956 | RXON_FLG_ANT_A_MSK)) == 0); | |
957 | if (error) | |
958 | IWL_WARNING("check antenna %d %d\n", counter++, error); | |
959 | ||
960 | if (error) | |
961 | IWL_WARNING("Tuning to channel %d\n", | |
962 | le16_to_cpu(rxon->channel)); | |
963 | ||
964 | if (error) { | |
bb8c093b | 965 | IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n"); |
b481de9c ZY |
966 | return -1; |
967 | } | |
968 | return 0; | |
969 | } | |
970 | ||
971 | /** | |
9fbab516 | 972 | * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed |
01ebd063 | 973 | * @priv: staging_rxon is compared to active_rxon |
b481de9c | 974 | * |
9fbab516 BC |
975 | * If the RXON structure is changing enough to require a new tune, |
976 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
977 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
b481de9c | 978 | */ |
bb8c093b | 979 | static int iwl3945_full_rxon_required(struct iwl3945_priv *priv) |
b481de9c ZY |
980 | { |
981 | ||
982 | /* These items are only settable from the full RXON command */ | |
983 | if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) || | |
984 | compare_ether_addr(priv->staging_rxon.bssid_addr, | |
985 | priv->active_rxon.bssid_addr) || | |
986 | compare_ether_addr(priv->staging_rxon.node_addr, | |
987 | priv->active_rxon.node_addr) || | |
988 | compare_ether_addr(priv->staging_rxon.wlap_bssid_addr, | |
989 | priv->active_rxon.wlap_bssid_addr) || | |
990 | (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) || | |
991 | (priv->staging_rxon.channel != priv->active_rxon.channel) || | |
992 | (priv->staging_rxon.air_propagation != | |
993 | priv->active_rxon.air_propagation) || | |
994 | (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id)) | |
995 | return 1; | |
996 | ||
997 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
998 | * be updated with the RXON_ASSOC command -- however only some | |
999 | * flag transitions are allowed using RXON_ASSOC */ | |
1000 | ||
1001 | /* Check if we are not switching bands */ | |
1002 | if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) != | |
1003 | (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)) | |
1004 | return 1; | |
1005 | ||
1006 | /* Check if we are switching association toggle */ | |
1007 | if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) != | |
1008 | (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) | |
1009 | return 1; | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
bb8c093b | 1014 | static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv) |
b481de9c ZY |
1015 | { |
1016 | int rc = 0; | |
bb8c093b CH |
1017 | struct iwl3945_rx_packet *res = NULL; |
1018 | struct iwl3945_rxon_assoc_cmd rxon_assoc; | |
1019 | struct iwl3945_host_cmd cmd = { | |
b481de9c ZY |
1020 | .id = REPLY_RXON_ASSOC, |
1021 | .len = sizeof(rxon_assoc), | |
1022 | .meta.flags = CMD_WANT_SKB, | |
1023 | .data = &rxon_assoc, | |
1024 | }; | |
bb8c093b CH |
1025 | const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon; |
1026 | const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon; | |
b481de9c ZY |
1027 | |
1028 | if ((rxon1->flags == rxon2->flags) && | |
1029 | (rxon1->filter_flags == rxon2->filter_flags) && | |
1030 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
1031 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
1032 | IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); | |
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | rxon_assoc.flags = priv->staging_rxon.flags; | |
1037 | rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; | |
1038 | rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; | |
1039 | rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; | |
1040 | rxon_assoc.reserved = 0; | |
1041 | ||
bb8c093b | 1042 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
1043 | if (rc) |
1044 | return rc; | |
1045 | ||
bb8c093b | 1046 | res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1047 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1048 | IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n"); | |
1049 | rc = -EIO; | |
1050 | } | |
1051 | ||
1052 | priv->alloc_rxb_skb--; | |
1053 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1054 | ||
1055 | return rc; | |
1056 | } | |
1057 | ||
1058 | /** | |
bb8c093b | 1059 | * iwl3945_commit_rxon - commit staging_rxon to hardware |
b481de9c | 1060 | * |
01ebd063 | 1061 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
1062 | * the active_rxon structure is updated with the new data. This |
1063 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
1064 | * a HW tune is required based on the RXON structure changes. | |
1065 | */ | |
bb8c093b | 1066 | static int iwl3945_commit_rxon(struct iwl3945_priv *priv) |
b481de9c ZY |
1067 | { |
1068 | /* cast away the const for active_rxon in this function */ | |
bb8c093b | 1069 | struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
b481de9c | 1070 | int rc = 0; |
0795af57 | 1071 | DECLARE_MAC_BUF(mac); |
b481de9c | 1072 | |
bb8c093b | 1073 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
1074 | return -1; |
1075 | ||
1076 | /* always get timestamp with Rx frame */ | |
1077 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
1078 | ||
1079 | /* select antenna */ | |
1080 | priv->staging_rxon.flags &= | |
1081 | ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK); | |
1082 | priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv); | |
1083 | ||
bb8c093b | 1084 | rc = iwl3945_check_rxon_cmd(&priv->staging_rxon); |
b481de9c ZY |
1085 | if (rc) { |
1086 | IWL_ERROR("Invalid RXON configuration. Not committing.\n"); | |
1087 | return -EINVAL; | |
1088 | } | |
1089 | ||
1090 | /* If we don't need to send a full RXON, we can use | |
bb8c093b | 1091 | * iwl3945_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 1092 | * and other flags for the current radio configuration. */ |
bb8c093b CH |
1093 | if (!iwl3945_full_rxon_required(priv)) { |
1094 | rc = iwl3945_send_rxon_assoc(priv); | |
b481de9c ZY |
1095 | if (rc) { |
1096 | IWL_ERROR("Error setting RXON_ASSOC " | |
1097 | "configuration (%d).\n", rc); | |
1098 | return rc; | |
1099 | } | |
1100 | ||
1101 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
1102 | ||
1103 | return 0; | |
1104 | } | |
1105 | ||
1106 | /* If we are currently associated and the new config requires | |
1107 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
1108 | * we must clear the associated from the active configuration | |
1109 | * before we apply the new config */ | |
bb8c093b | 1110 | if (iwl3945_is_associated(priv) && |
b481de9c ZY |
1111 | (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) { |
1112 | IWL_DEBUG_INFO("Toggling associated bit on current RXON\n"); | |
1113 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
1114 | ||
bb8c093b CH |
1115 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON, |
1116 | sizeof(struct iwl3945_rxon_cmd), | |
b481de9c ZY |
1117 | &priv->active_rxon); |
1118 | ||
1119 | /* If the mask clearing failed then we set | |
1120 | * active_rxon back to what it was previously */ | |
1121 | if (rc) { | |
1122 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; | |
1123 | IWL_ERROR("Error clearing ASSOC_MSK on current " | |
1124 | "configuration (%d).\n", rc); | |
1125 | return rc; | |
1126 | } | |
b481de9c ZY |
1127 | } |
1128 | ||
1129 | IWL_DEBUG_INFO("Sending RXON\n" | |
1130 | "* with%s RXON_FILTER_ASSOC_MSK\n" | |
1131 | "* channel = %d\n" | |
0795af57 | 1132 | "* bssid = %s\n", |
b481de9c ZY |
1133 | ((priv->staging_rxon.filter_flags & |
1134 | RXON_FILTER_ASSOC_MSK) ? "" : "out"), | |
1135 | le16_to_cpu(priv->staging_rxon.channel), | |
0795af57 | 1136 | print_mac(mac, priv->staging_rxon.bssid_addr)); |
b481de9c ZY |
1137 | |
1138 | /* Apply the new configuration */ | |
bb8c093b CH |
1139 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON, |
1140 | sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon); | |
b481de9c ZY |
1141 | if (rc) { |
1142 | IWL_ERROR("Error setting new configuration (%d).\n", rc); | |
1143 | return rc; | |
1144 | } | |
1145 | ||
1146 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
1147 | ||
bb8c093b | 1148 | iwl3945_clear_stations_table(priv); |
556f8db7 | 1149 | |
b481de9c ZY |
1150 | /* If we issue a new RXON command which required a tune then we must |
1151 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
bb8c093b | 1152 | rc = iwl3945_hw_reg_send_txpower(priv); |
b481de9c ZY |
1153 | if (rc) { |
1154 | IWL_ERROR("Error setting Tx power (%d).\n", rc); | |
1155 | return rc; | |
1156 | } | |
1157 | ||
1158 | /* Add the broadcast address so we can send broadcast frames */ | |
bb8c093b | 1159 | if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) == |
b481de9c ZY |
1160 | IWL_INVALID_STATION) { |
1161 | IWL_ERROR("Error adding BROADCAST address for transmit.\n"); | |
1162 | return -EIO; | |
1163 | } | |
1164 | ||
1165 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
1166 | * add the IWL_AP_ID to the station rate table */ | |
bb8c093b | 1167 | if (iwl3945_is_associated(priv) && |
b481de9c | 1168 | (priv->iw_mode == IEEE80211_IF_TYPE_STA)) |
bb8c093b | 1169 | if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0) |
b481de9c ZY |
1170 | == IWL_INVALID_STATION) { |
1171 | IWL_ERROR("Error adding AP address for transmit.\n"); | |
1172 | return -EIO; | |
1173 | } | |
1174 | ||
8318d78a | 1175 | /* Init the hardware's rate fallback order based on the band */ |
b481de9c ZY |
1176 | rc = iwl3945_init_hw_rate_table(priv); |
1177 | if (rc) { | |
1178 | IWL_ERROR("Error setting HW rate table: %02X\n", rc); | |
1179 | return -EIO; | |
1180 | } | |
1181 | ||
1182 | return 0; | |
1183 | } | |
1184 | ||
bb8c093b | 1185 | static int iwl3945_send_bt_config(struct iwl3945_priv *priv) |
b481de9c | 1186 | { |
bb8c093b | 1187 | struct iwl3945_bt_cmd bt_cmd = { |
b481de9c ZY |
1188 | .flags = 3, |
1189 | .lead_time = 0xAA, | |
1190 | .max_kill = 1, | |
1191 | .kill_ack_mask = 0, | |
1192 | .kill_cts_mask = 0, | |
1193 | }; | |
1194 | ||
bb8c093b CH |
1195 | return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG, |
1196 | sizeof(struct iwl3945_bt_cmd), &bt_cmd); | |
b481de9c ZY |
1197 | } |
1198 | ||
bb8c093b | 1199 | static int iwl3945_send_scan_abort(struct iwl3945_priv *priv) |
b481de9c ZY |
1200 | { |
1201 | int rc = 0; | |
bb8c093b CH |
1202 | struct iwl3945_rx_packet *res; |
1203 | struct iwl3945_host_cmd cmd = { | |
b481de9c ZY |
1204 | .id = REPLY_SCAN_ABORT_CMD, |
1205 | .meta.flags = CMD_WANT_SKB, | |
1206 | }; | |
1207 | ||
1208 | /* If there isn't a scan actively going on in the hardware | |
1209 | * then we are in between scan bands and not actually | |
1210 | * actively scanning, so don't send the abort command */ | |
1211 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
1212 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1213 | return 0; | |
1214 | } | |
1215 | ||
bb8c093b | 1216 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
1217 | if (rc) { |
1218 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1219 | return rc; | |
1220 | } | |
1221 | ||
bb8c093b | 1222 | res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1223 | if (res->u.status != CAN_ABORT_STATUS) { |
1224 | /* The scan abort will return 1 for success or | |
1225 | * 2 for "failure". A failure condition can be | |
1226 | * due to simply not being in an active scan which | |
1227 | * can occur if we send the scan abort before we | |
1228 | * the microcode has notified us that a scan is | |
1229 | * completed. */ | |
1230 | IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status); | |
1231 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1232 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
1233 | } | |
1234 | ||
1235 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1236 | ||
1237 | return rc; | |
1238 | } | |
1239 | ||
bb8c093b CH |
1240 | static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv, |
1241 | struct iwl3945_cmd *cmd, | |
b481de9c ZY |
1242 | struct sk_buff *skb) |
1243 | { | |
1244 | return 1; | |
1245 | } | |
1246 | ||
1247 | /* | |
1248 | * CARD_STATE_CMD | |
1249 | * | |
9fbab516 | 1250 | * Use: Sets the device's internal card state to enable, disable, or halt |
b481de9c ZY |
1251 | * |
1252 | * When in the 'enable' state the card operates as normal. | |
1253 | * When in the 'disable' state, the card enters into a low power mode. | |
1254 | * When in the 'halt' state, the card is shut down and must be fully | |
1255 | * restarted to come back on. | |
1256 | */ | |
bb8c093b | 1257 | static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag) |
b481de9c | 1258 | { |
bb8c093b | 1259 | struct iwl3945_host_cmd cmd = { |
b481de9c ZY |
1260 | .id = REPLY_CARD_STATE_CMD, |
1261 | .len = sizeof(u32), | |
1262 | .data = &flags, | |
1263 | .meta.flags = meta_flag, | |
1264 | }; | |
1265 | ||
1266 | if (meta_flag & CMD_ASYNC) | |
bb8c093b | 1267 | cmd.meta.u.callback = iwl3945_card_state_sync_callback; |
b481de9c | 1268 | |
bb8c093b | 1269 | return iwl3945_send_cmd(priv, &cmd); |
b481de9c ZY |
1270 | } |
1271 | ||
bb8c093b CH |
1272 | static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv, |
1273 | struct iwl3945_cmd *cmd, struct sk_buff *skb) | |
b481de9c | 1274 | { |
bb8c093b | 1275 | struct iwl3945_rx_packet *res = NULL; |
b481de9c ZY |
1276 | |
1277 | if (!skb) { | |
1278 | IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n"); | |
1279 | return 1; | |
1280 | } | |
1281 | ||
bb8c093b | 1282 | res = (struct iwl3945_rx_packet *)skb->data; |
b481de9c ZY |
1283 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1284 | IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n", | |
1285 | res->hdr.flags); | |
1286 | return 1; | |
1287 | } | |
1288 | ||
1289 | switch (res->u.add_sta.status) { | |
1290 | case ADD_STA_SUCCESS_MSK: | |
1291 | break; | |
1292 | default: | |
1293 | break; | |
1294 | } | |
1295 | ||
1296 | /* We didn't cache the SKB; let the caller free it */ | |
1297 | return 1; | |
1298 | } | |
1299 | ||
bb8c093b CH |
1300 | int iwl3945_send_add_station(struct iwl3945_priv *priv, |
1301 | struct iwl3945_addsta_cmd *sta, u8 flags) | |
b481de9c | 1302 | { |
bb8c093b | 1303 | struct iwl3945_rx_packet *res = NULL; |
b481de9c | 1304 | int rc = 0; |
bb8c093b | 1305 | struct iwl3945_host_cmd cmd = { |
b481de9c | 1306 | .id = REPLY_ADD_STA, |
bb8c093b | 1307 | .len = sizeof(struct iwl3945_addsta_cmd), |
b481de9c ZY |
1308 | .meta.flags = flags, |
1309 | .data = sta, | |
1310 | }; | |
1311 | ||
1312 | if (flags & CMD_ASYNC) | |
bb8c093b | 1313 | cmd.meta.u.callback = iwl3945_add_sta_sync_callback; |
b481de9c ZY |
1314 | else |
1315 | cmd.meta.flags |= CMD_WANT_SKB; | |
1316 | ||
bb8c093b | 1317 | rc = iwl3945_send_cmd(priv, &cmd); |
b481de9c ZY |
1318 | |
1319 | if (rc || (flags & CMD_ASYNC)) | |
1320 | return rc; | |
1321 | ||
bb8c093b | 1322 | res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1323 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
1324 | IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n", | |
1325 | res->hdr.flags); | |
1326 | rc = -EIO; | |
1327 | } | |
1328 | ||
1329 | if (rc == 0) { | |
1330 | switch (res->u.add_sta.status) { | |
1331 | case ADD_STA_SUCCESS_MSK: | |
1332 | IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n"); | |
1333 | break; | |
1334 | default: | |
1335 | rc = -EIO; | |
1336 | IWL_WARNING("REPLY_ADD_STA failed\n"); | |
1337 | break; | |
1338 | } | |
1339 | } | |
1340 | ||
1341 | priv->alloc_rxb_skb--; | |
1342 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1343 | ||
1344 | return rc; | |
1345 | } | |
1346 | ||
bb8c093b | 1347 | static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv, |
b481de9c ZY |
1348 | struct ieee80211_key_conf *keyconf, |
1349 | u8 sta_id) | |
1350 | { | |
1351 | unsigned long flags; | |
1352 | __le16 key_flags = 0; | |
1353 | ||
1354 | switch (keyconf->alg) { | |
1355 | case ALG_CCMP: | |
1356 | key_flags |= STA_KEY_FLG_CCMP; | |
1357 | key_flags |= cpu_to_le16( | |
1358 | keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
1359 | key_flags &= ~STA_KEY_FLG_INVALID; | |
1360 | break; | |
1361 | case ALG_TKIP: | |
1362 | case ALG_WEP: | |
b481de9c ZY |
1363 | default: |
1364 | return -EINVAL; | |
1365 | } | |
1366 | spin_lock_irqsave(&priv->sta_lock, flags); | |
1367 | priv->stations[sta_id].keyinfo.alg = keyconf->alg; | |
1368 | priv->stations[sta_id].keyinfo.keylen = keyconf->keylen; | |
1369 | memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, | |
1370 | keyconf->keylen); | |
1371 | ||
1372 | memcpy(priv->stations[sta_id].sta.key.key, keyconf->key, | |
1373 | keyconf->keylen); | |
1374 | priv->stations[sta_id].sta.key.key_flags = key_flags; | |
1375 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
1376 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
1377 | ||
1378 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1379 | ||
1380 | IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n"); | |
bb8c093b | 1381 | iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0); |
b481de9c ZY |
1382 | return 0; |
1383 | } | |
1384 | ||
bb8c093b | 1385 | static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id) |
b481de9c ZY |
1386 | { |
1387 | unsigned long flags; | |
1388 | ||
1389 | spin_lock_irqsave(&priv->sta_lock, flags); | |
bb8c093b CH |
1390 | memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key)); |
1391 | memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo)); | |
b481de9c ZY |
1392 | priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC; |
1393 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
1394 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
1395 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1396 | ||
1397 | IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n"); | |
bb8c093b | 1398 | iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0); |
b481de9c ZY |
1399 | return 0; |
1400 | } | |
1401 | ||
bb8c093b | 1402 | static void iwl3945_clear_free_frames(struct iwl3945_priv *priv) |
b481de9c ZY |
1403 | { |
1404 | struct list_head *element; | |
1405 | ||
1406 | IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n", | |
1407 | priv->frames_count); | |
1408 | ||
1409 | while (!list_empty(&priv->free_frames)) { | |
1410 | element = priv->free_frames.next; | |
1411 | list_del(element); | |
bb8c093b | 1412 | kfree(list_entry(element, struct iwl3945_frame, list)); |
b481de9c ZY |
1413 | priv->frames_count--; |
1414 | } | |
1415 | ||
1416 | if (priv->frames_count) { | |
1417 | IWL_WARNING("%d frames still in use. Did we lose one?\n", | |
1418 | priv->frames_count); | |
1419 | priv->frames_count = 0; | |
1420 | } | |
1421 | } | |
1422 | ||
bb8c093b | 1423 | static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv) |
b481de9c | 1424 | { |
bb8c093b | 1425 | struct iwl3945_frame *frame; |
b481de9c ZY |
1426 | struct list_head *element; |
1427 | if (list_empty(&priv->free_frames)) { | |
1428 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
1429 | if (!frame) { | |
1430 | IWL_ERROR("Could not allocate frame!\n"); | |
1431 | return NULL; | |
1432 | } | |
1433 | ||
1434 | priv->frames_count++; | |
1435 | return frame; | |
1436 | } | |
1437 | ||
1438 | element = priv->free_frames.next; | |
1439 | list_del(element); | |
bb8c093b | 1440 | return list_entry(element, struct iwl3945_frame, list); |
b481de9c ZY |
1441 | } |
1442 | ||
bb8c093b | 1443 | static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame) |
b481de9c ZY |
1444 | { |
1445 | memset(frame, 0, sizeof(*frame)); | |
1446 | list_add(&frame->list, &priv->free_frames); | |
1447 | } | |
1448 | ||
bb8c093b | 1449 | unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv, |
b481de9c ZY |
1450 | struct ieee80211_hdr *hdr, |
1451 | const u8 *dest, int left) | |
1452 | { | |
1453 | ||
bb8c093b | 1454 | if (!iwl3945_is_associated(priv) || !priv->ibss_beacon || |
b481de9c ZY |
1455 | ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) && |
1456 | (priv->iw_mode != IEEE80211_IF_TYPE_AP))) | |
1457 | return 0; | |
1458 | ||
1459 | if (priv->ibss_beacon->len > left) | |
1460 | return 0; | |
1461 | ||
1462 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
1463 | ||
1464 | return priv->ibss_beacon->len; | |
1465 | } | |
1466 | ||
bb8c093b | 1467 | static u8 iwl3945_rate_get_lowest_plcp(int rate_mask) |
b481de9c ZY |
1468 | { |
1469 | u8 i; | |
1470 | ||
1471 | for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID; | |
bb8c093b | 1472 | i = iwl3945_rates[i].next_ieee) { |
b481de9c | 1473 | if (rate_mask & (1 << i)) |
bb8c093b | 1474 | return iwl3945_rates[i].plcp; |
b481de9c ZY |
1475 | } |
1476 | ||
1477 | return IWL_RATE_INVALID; | |
1478 | } | |
1479 | ||
bb8c093b | 1480 | static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv) |
b481de9c | 1481 | { |
bb8c093b | 1482 | struct iwl3945_frame *frame; |
b481de9c ZY |
1483 | unsigned int frame_size; |
1484 | int rc; | |
1485 | u8 rate; | |
1486 | ||
bb8c093b | 1487 | frame = iwl3945_get_free_frame(priv); |
b481de9c ZY |
1488 | |
1489 | if (!frame) { | |
1490 | IWL_ERROR("Could not obtain free frame buffer for beacon " | |
1491 | "command.\n"); | |
1492 | return -ENOMEM; | |
1493 | } | |
1494 | ||
1495 | if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) { | |
bb8c093b | 1496 | rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & |
b481de9c ZY |
1497 | 0xFF0); |
1498 | if (rate == IWL_INVALID_RATE) | |
1499 | rate = IWL_RATE_6M_PLCP; | |
1500 | } else { | |
bb8c093b | 1501 | rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF); |
b481de9c ZY |
1502 | if (rate == IWL_INVALID_RATE) |
1503 | rate = IWL_RATE_1M_PLCP; | |
1504 | } | |
1505 | ||
bb8c093b | 1506 | frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 1507 | |
bb8c093b | 1508 | rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
1509 | &frame->u.cmd[0]); |
1510 | ||
bb8c093b | 1511 | iwl3945_free_frame(priv, frame); |
b481de9c ZY |
1512 | |
1513 | return rc; | |
1514 | } | |
1515 | ||
1516 | /****************************************************************************** | |
1517 | * | |
1518 | * EEPROM related functions | |
1519 | * | |
1520 | ******************************************************************************/ | |
1521 | ||
bb8c093b | 1522 | static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac) |
b481de9c ZY |
1523 | { |
1524 | memcpy(mac, priv->eeprom.mac_address, 6); | |
1525 | } | |
1526 | ||
74a3a250 RC |
1527 | /* |
1528 | * Clear the OWNER_MSK, to establish driver (instead of uCode running on | |
1529 | * embedded controller) as EEPROM reader; each read is a series of pulses | |
1530 | * to/from the EEPROM chip, not a single event, so even reads could conflict | |
1531 | * if they weren't arbitrated by some ownership mechanism. Here, the driver | |
1532 | * simply claims ownership, which should be safe when this function is called | |
1533 | * (i.e. before loading uCode!). | |
1534 | */ | |
1535 | static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv) | |
1536 | { | |
1537 | _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK); | |
1538 | return 0; | |
1539 | } | |
1540 | ||
b481de9c | 1541 | /** |
bb8c093b | 1542 | * iwl3945_eeprom_init - read EEPROM contents |
b481de9c | 1543 | * |
6440adb5 | 1544 | * Load the EEPROM contents from adapter into priv->eeprom |
b481de9c ZY |
1545 | * |
1546 | * NOTE: This routine uses the non-debug IO access functions. | |
1547 | */ | |
bb8c093b | 1548 | int iwl3945_eeprom_init(struct iwl3945_priv *priv) |
b481de9c | 1549 | { |
58ff6d4d | 1550 | u16 *e = (u16 *)&priv->eeprom; |
bb8c093b | 1551 | u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP); |
b481de9c ZY |
1552 | u32 r; |
1553 | int sz = sizeof(priv->eeprom); | |
1554 | int rc; | |
1555 | int i; | |
1556 | u16 addr; | |
1557 | ||
1558 | /* The EEPROM structure has several padding buffers within it | |
1559 | * and when adding new EEPROM maps is subject to programmer errors | |
1560 | * which may be very difficult to identify without explicitly | |
1561 | * checking the resulting size of the eeprom map. */ | |
1562 | BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE); | |
1563 | ||
1564 | if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) { | |
1565 | IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp); | |
1566 | return -ENOENT; | |
1567 | } | |
1568 | ||
6440adb5 | 1569 | /* Make sure driver (instead of uCode) is allowed to read EEPROM */ |
bb8c093b | 1570 | rc = iwl3945_eeprom_acquire_semaphore(priv); |
b481de9c | 1571 | if (rc < 0) { |
91e17473 | 1572 | IWL_ERROR("Failed to acquire EEPROM semaphore.\n"); |
b481de9c ZY |
1573 | return -ENOENT; |
1574 | } | |
1575 | ||
1576 | /* eeprom is an array of 16bit values */ | |
1577 | for (addr = 0; addr < sz; addr += sizeof(u16)) { | |
bb8c093b CH |
1578 | _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1); |
1579 | _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD); | |
b481de9c ZY |
1580 | |
1581 | for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT; | |
1582 | i += IWL_EEPROM_ACCESS_DELAY) { | |
bb8c093b | 1583 | r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG); |
b481de9c ZY |
1584 | if (r & CSR_EEPROM_REG_READ_VALID_MSK) |
1585 | break; | |
1586 | udelay(IWL_EEPROM_ACCESS_DELAY); | |
1587 | } | |
1588 | ||
1589 | if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) { | |
1590 | IWL_ERROR("Time out reading EEPROM[%d]", addr); | |
1591 | return -ETIMEDOUT; | |
1592 | } | |
58ff6d4d | 1593 | e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16)); |
b481de9c ZY |
1594 | } |
1595 | ||
1596 | return 0; | |
1597 | } | |
1598 | ||
bb8c093b | 1599 | static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv) |
b481de9c ZY |
1600 | { |
1601 | if (priv->hw_setting.shared_virt) | |
1602 | pci_free_consistent(priv->pci_dev, | |
bb8c093b | 1603 | sizeof(struct iwl3945_shared), |
b481de9c ZY |
1604 | priv->hw_setting.shared_virt, |
1605 | priv->hw_setting.shared_phys); | |
1606 | } | |
1607 | ||
1608 | /** | |
bb8c093b | 1609 | * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field |
b481de9c ZY |
1610 | * |
1611 | * return : set the bit for each supported rate insert in ie | |
1612 | */ | |
bb8c093b | 1613 | static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate, |
c7c46676 | 1614 | u16 basic_rate, int *left) |
b481de9c ZY |
1615 | { |
1616 | u16 ret_rates = 0, bit; | |
1617 | int i; | |
c7c46676 TW |
1618 | u8 *cnt = ie; |
1619 | u8 *rates = ie + 1; | |
b481de9c ZY |
1620 | |
1621 | for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) { | |
1622 | if (bit & supported_rate) { | |
1623 | ret_rates |= bit; | |
bb8c093b | 1624 | rates[*cnt] = iwl3945_rates[i].ieee | |
c7c46676 TW |
1625 | ((bit & basic_rate) ? 0x80 : 0x00); |
1626 | (*cnt)++; | |
1627 | (*left)--; | |
1628 | if ((*left <= 0) || | |
1629 | (*cnt >= IWL_SUPPORTED_RATES_IE_LEN)) | |
b481de9c ZY |
1630 | break; |
1631 | } | |
1632 | } | |
1633 | ||
1634 | return ret_rates; | |
1635 | } | |
1636 | ||
1637 | /** | |
bb8c093b | 1638 | * iwl3945_fill_probe_req - fill in all required fields and IE for probe request |
b481de9c | 1639 | */ |
bb8c093b | 1640 | static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv, |
b481de9c ZY |
1641 | struct ieee80211_mgmt *frame, |
1642 | int left, int is_direct) | |
1643 | { | |
1644 | int len = 0; | |
1645 | u8 *pos = NULL; | |
c7c46676 | 1646 | u16 active_rates, ret_rates, cck_rates; |
b481de9c ZY |
1647 | |
1648 | /* Make sure there is enough space for the probe request, | |
1649 | * two mandatory IEs and the data */ | |
1650 | left -= 24; | |
1651 | if (left < 0) | |
1652 | return 0; | |
1653 | len += 24; | |
1654 | ||
1655 | frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ); | |
bb8c093b | 1656 | memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN); |
b481de9c | 1657 | memcpy(frame->sa, priv->mac_addr, ETH_ALEN); |
bb8c093b | 1658 | memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN); |
b481de9c ZY |
1659 | frame->seq_ctrl = 0; |
1660 | ||
1661 | /* fill in our indirect SSID IE */ | |
1662 | /* ...next IE... */ | |
1663 | ||
1664 | left -= 2; | |
1665 | if (left < 0) | |
1666 | return 0; | |
1667 | len += 2; | |
1668 | pos = &(frame->u.probe_req.variable[0]); | |
1669 | *pos++ = WLAN_EID_SSID; | |
1670 | *pos++ = 0; | |
1671 | ||
1672 | /* fill in our direct SSID IE... */ | |
1673 | if (is_direct) { | |
1674 | /* ...next IE... */ | |
1675 | left -= 2 + priv->essid_len; | |
1676 | if (left < 0) | |
1677 | return 0; | |
1678 | /* ... fill it in... */ | |
1679 | *pos++ = WLAN_EID_SSID; | |
1680 | *pos++ = priv->essid_len; | |
1681 | memcpy(pos, priv->essid, priv->essid_len); | |
1682 | pos += priv->essid_len; | |
1683 | len += 2 + priv->essid_len; | |
1684 | } | |
1685 | ||
1686 | /* fill in supported rate */ | |
1687 | /* ...next IE... */ | |
1688 | left -= 2; | |
1689 | if (left < 0) | |
1690 | return 0; | |
c7c46676 | 1691 | |
b481de9c ZY |
1692 | /* ... fill it in... */ |
1693 | *pos++ = WLAN_EID_SUPP_RATES; | |
1694 | *pos = 0; | |
c7c46676 TW |
1695 | |
1696 | priv->active_rate = priv->rates_mask; | |
1697 | active_rates = priv->active_rate; | |
b481de9c ZY |
1698 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; |
1699 | ||
c7c46676 | 1700 | cck_rates = IWL_CCK_RATES_MASK & active_rates; |
bb8c093b | 1701 | ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates, |
c7c46676 TW |
1702 | priv->active_rate_basic, &left); |
1703 | active_rates &= ~ret_rates; | |
1704 | ||
bb8c093b | 1705 | ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates, |
c7c46676 TW |
1706 | priv->active_rate_basic, &left); |
1707 | active_rates &= ~ret_rates; | |
1708 | ||
b481de9c ZY |
1709 | len += 2 + *pos; |
1710 | pos += (*pos) + 1; | |
c7c46676 | 1711 | if (active_rates == 0) |
b481de9c ZY |
1712 | goto fill_end; |
1713 | ||
1714 | /* fill in supported extended rate */ | |
1715 | /* ...next IE... */ | |
1716 | left -= 2; | |
1717 | if (left < 0) | |
1718 | return 0; | |
1719 | /* ... fill it in... */ | |
1720 | *pos++ = WLAN_EID_EXT_SUPP_RATES; | |
1721 | *pos = 0; | |
bb8c093b | 1722 | iwl3945_supported_rate_to_ie(pos, active_rates, |
c7c46676 | 1723 | priv->active_rate_basic, &left); |
b481de9c ZY |
1724 | if (*pos > 0) |
1725 | len += 2 + *pos; | |
1726 | ||
1727 | fill_end: | |
1728 | return (u16)len; | |
1729 | } | |
1730 | ||
1731 | /* | |
1732 | * QoS support | |
1733 | */ | |
bb8c093b CH |
1734 | static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv, |
1735 | struct iwl3945_qosparam_cmd *qos) | |
b481de9c ZY |
1736 | { |
1737 | ||
bb8c093b CH |
1738 | return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM, |
1739 | sizeof(struct iwl3945_qosparam_cmd), qos); | |
b481de9c ZY |
1740 | } |
1741 | ||
bb8c093b | 1742 | static void iwl3945_reset_qos(struct iwl3945_priv *priv) |
b481de9c ZY |
1743 | { |
1744 | u16 cw_min = 15; | |
1745 | u16 cw_max = 1023; | |
1746 | u8 aifs = 2; | |
1747 | u8 is_legacy = 0; | |
1748 | unsigned long flags; | |
1749 | int i; | |
1750 | ||
1751 | spin_lock_irqsave(&priv->lock, flags); | |
1752 | priv->qos_data.qos_active = 0; | |
1753 | ||
1754 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) { | |
1755 | if (priv->qos_data.qos_enable) | |
1756 | priv->qos_data.qos_active = 1; | |
1757 | if (!(priv->active_rate & 0xfff0)) { | |
1758 | cw_min = 31; | |
1759 | is_legacy = 1; | |
1760 | } | |
1761 | } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
1762 | if (priv->qos_data.qos_enable) | |
1763 | priv->qos_data.qos_active = 1; | |
1764 | } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) { | |
1765 | cw_min = 31; | |
1766 | is_legacy = 1; | |
1767 | } | |
1768 | ||
1769 | if (priv->qos_data.qos_active) | |
1770 | aifs = 3; | |
1771 | ||
1772 | priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min); | |
1773 | priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max); | |
1774 | priv->qos_data.def_qos_parm.ac[0].aifsn = aifs; | |
1775 | priv->qos_data.def_qos_parm.ac[0].edca_txop = 0; | |
1776 | priv->qos_data.def_qos_parm.ac[0].reserved1 = 0; | |
1777 | ||
1778 | if (priv->qos_data.qos_active) { | |
1779 | i = 1; | |
1780 | priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min); | |
1781 | priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max); | |
1782 | priv->qos_data.def_qos_parm.ac[i].aifsn = 7; | |
1783 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
1784 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1785 | ||
1786 | i = 2; | |
1787 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
1788 | cpu_to_le16((cw_min + 1) / 2 - 1); | |
1789 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
1790 | cpu_to_le16(cw_max); | |
1791 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; | |
1792 | if (is_legacy) | |
1793 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1794 | cpu_to_le16(6016); | |
1795 | else | |
1796 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1797 | cpu_to_le16(3008); | |
1798 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1799 | ||
1800 | i = 3; | |
1801 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
1802 | cpu_to_le16((cw_min + 1) / 4 - 1); | |
1803 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
1804 | cpu_to_le16((cw_max + 1) / 2 - 1); | |
1805 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; | |
1806 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1807 | if (is_legacy) | |
1808 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1809 | cpu_to_le16(3264); | |
1810 | else | |
1811 | priv->qos_data.def_qos_parm.ac[i].edca_txop = | |
1812 | cpu_to_le16(1504); | |
1813 | } else { | |
1814 | for (i = 1; i < 4; i++) { | |
1815 | priv->qos_data.def_qos_parm.ac[i].cw_min = | |
1816 | cpu_to_le16(cw_min); | |
1817 | priv->qos_data.def_qos_parm.ac[i].cw_max = | |
1818 | cpu_to_le16(cw_max); | |
1819 | priv->qos_data.def_qos_parm.ac[i].aifsn = aifs; | |
1820 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; | |
1821 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; | |
1822 | } | |
1823 | } | |
1824 | IWL_DEBUG_QOS("set QoS to default \n"); | |
1825 | ||
1826 | spin_unlock_irqrestore(&priv->lock, flags); | |
1827 | } | |
1828 | ||
bb8c093b | 1829 | static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force) |
b481de9c ZY |
1830 | { |
1831 | unsigned long flags; | |
1832 | ||
b481de9c ZY |
1833 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
1834 | return; | |
1835 | ||
1836 | if (!priv->qos_data.qos_enable) | |
1837 | return; | |
1838 | ||
1839 | spin_lock_irqsave(&priv->lock, flags); | |
1840 | priv->qos_data.def_qos_parm.qos_flags = 0; | |
1841 | ||
1842 | if (priv->qos_data.qos_cap.q_AP.queue_request && | |
1843 | !priv->qos_data.qos_cap.q_AP.txop_request) | |
1844 | priv->qos_data.def_qos_parm.qos_flags |= | |
1845 | QOS_PARAM_FLG_TXOP_TYPE_MSK; | |
1846 | ||
1847 | if (priv->qos_data.qos_active) | |
1848 | priv->qos_data.def_qos_parm.qos_flags |= | |
1849 | QOS_PARAM_FLG_UPDATE_EDCA_MSK; | |
1850 | ||
1851 | spin_unlock_irqrestore(&priv->lock, flags); | |
1852 | ||
bb8c093b | 1853 | if (force || iwl3945_is_associated(priv)) { |
b481de9c ZY |
1854 | IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n", |
1855 | priv->qos_data.qos_active); | |
1856 | ||
bb8c093b | 1857 | iwl3945_send_qos_params_command(priv, |
b481de9c ZY |
1858 | &(priv->qos_data.def_qos_parm)); |
1859 | } | |
1860 | } | |
1861 | ||
b481de9c ZY |
1862 | /* |
1863 | * Power management (not Tx power!) functions | |
1864 | */ | |
1865 | #define MSEC_TO_USEC 1024 | |
1866 | ||
1867 | #define NOSLP __constant_cpu_to_le32(0) | |
1868 | #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK | |
1869 | #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC) | |
1870 | #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \ | |
1871 | __constant_cpu_to_le32(X1), \ | |
1872 | __constant_cpu_to_le32(X2), \ | |
1873 | __constant_cpu_to_le32(X3), \ | |
1874 | __constant_cpu_to_le32(X4)} | |
1875 | ||
1876 | ||
1877 | /* default power management (not Tx power) table values */ | |
1878 | /* for tim 0-10 */ | |
bb8c093b | 1879 | static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = { |
b481de9c ZY |
1880 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1881 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0}, | |
1882 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0}, | |
1883 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0}, | |
1884 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1}, | |
1885 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1} | |
1886 | }; | |
1887 | ||
1888 | /* for tim > 10 */ | |
bb8c093b | 1889 | static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = { |
b481de9c ZY |
1890 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1891 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), | |
1892 | SLP_VEC(1, 2, 3, 4, 0xFF)}, 0}, | |
1893 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), | |
1894 | SLP_VEC(2, 4, 6, 7, 0xFF)}, 0}, | |
1895 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), | |
1896 | SLP_VEC(2, 6, 9, 9, 0xFF)}, 0}, | |
1897 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0}, | |
1898 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), | |
1899 | SLP_VEC(4, 7, 10, 10, 0xFF)}, 0} | |
1900 | }; | |
1901 | ||
bb8c093b | 1902 | int iwl3945_power_init_handle(struct iwl3945_priv *priv) |
b481de9c ZY |
1903 | { |
1904 | int rc = 0, i; | |
bb8c093b CH |
1905 | struct iwl3945_power_mgr *pow_data; |
1906 | int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC; | |
b481de9c ZY |
1907 | u16 pci_pm; |
1908 | ||
1909 | IWL_DEBUG_POWER("Initialize power \n"); | |
1910 | ||
1911 | pow_data = &(priv->power_data); | |
1912 | ||
1913 | memset(pow_data, 0, sizeof(*pow_data)); | |
1914 | ||
1915 | pow_data->active_index = IWL_POWER_RANGE_0; | |
1916 | pow_data->dtim_val = 0xffff; | |
1917 | ||
1918 | memcpy(&pow_data->pwr_range_0[0], &range_0[0], size); | |
1919 | memcpy(&pow_data->pwr_range_1[0], &range_1[0], size); | |
1920 | ||
1921 | rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm); | |
1922 | if (rc != 0) | |
1923 | return 0; | |
1924 | else { | |
bb8c093b | 1925 | struct iwl3945_powertable_cmd *cmd; |
b481de9c ZY |
1926 | |
1927 | IWL_DEBUG_POWER("adjust power command flags\n"); | |
1928 | ||
1929 | for (i = 0; i < IWL_POWER_AC; i++) { | |
1930 | cmd = &pow_data->pwr_range_0[i].cmd; | |
1931 | ||
1932 | if (pci_pm & 0x1) | |
1933 | cmd->flags &= ~IWL_POWER_PCI_PM_MSK; | |
1934 | else | |
1935 | cmd->flags |= IWL_POWER_PCI_PM_MSK; | |
1936 | } | |
1937 | } | |
1938 | return rc; | |
1939 | } | |
1940 | ||
bb8c093b CH |
1941 | static int iwl3945_update_power_cmd(struct iwl3945_priv *priv, |
1942 | struct iwl3945_powertable_cmd *cmd, u32 mode) | |
b481de9c ZY |
1943 | { |
1944 | int rc = 0, i; | |
1945 | u8 skip; | |
1946 | u32 max_sleep = 0; | |
bb8c093b | 1947 | struct iwl3945_power_vec_entry *range; |
b481de9c | 1948 | u8 period = 0; |
bb8c093b | 1949 | struct iwl3945_power_mgr *pow_data; |
b481de9c ZY |
1950 | |
1951 | if (mode > IWL_POWER_INDEX_5) { | |
1952 | IWL_DEBUG_POWER("Error invalid power mode \n"); | |
1953 | return -1; | |
1954 | } | |
1955 | pow_data = &(priv->power_data); | |
1956 | ||
1957 | if (pow_data->active_index == IWL_POWER_RANGE_0) | |
1958 | range = &pow_data->pwr_range_0[0]; | |
1959 | else | |
1960 | range = &pow_data->pwr_range_1[1]; | |
1961 | ||
bb8c093b | 1962 | memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd)); |
b481de9c ZY |
1963 | |
1964 | #ifdef IWL_MAC80211_DISABLE | |
1965 | if (priv->assoc_network != NULL) { | |
1966 | unsigned long flags; | |
1967 | ||
1968 | period = priv->assoc_network->tim.tim_period; | |
1969 | } | |
1970 | #endif /*IWL_MAC80211_DISABLE */ | |
1971 | skip = range[mode].no_dtim; | |
1972 | ||
1973 | if (period == 0) { | |
1974 | period = 1; | |
1975 | skip = 0; | |
1976 | } | |
1977 | ||
1978 | if (skip == 0) { | |
1979 | max_sleep = period; | |
1980 | cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
1981 | } else { | |
1982 | __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]; | |
1983 | max_sleep = (le32_to_cpu(slp_itrvl) / period) * period; | |
1984 | cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
1985 | } | |
1986 | ||
1987 | for (i = 0; i < IWL_POWER_VEC_SIZE; i++) { | |
1988 | if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep) | |
1989 | cmd->sleep_interval[i] = cpu_to_le32(max_sleep); | |
1990 | } | |
1991 | ||
1992 | IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags); | |
1993 | IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout)); | |
1994 | IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout)); | |
1995 | IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n", | |
1996 | le32_to_cpu(cmd->sleep_interval[0]), | |
1997 | le32_to_cpu(cmd->sleep_interval[1]), | |
1998 | le32_to_cpu(cmd->sleep_interval[2]), | |
1999 | le32_to_cpu(cmd->sleep_interval[3]), | |
2000 | le32_to_cpu(cmd->sleep_interval[4])); | |
2001 | ||
2002 | return rc; | |
2003 | } | |
2004 | ||
bb8c093b | 2005 | static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode) |
b481de9c | 2006 | { |
9a62f73b | 2007 | u32 uninitialized_var(final_mode); |
b481de9c | 2008 | int rc; |
bb8c093b | 2009 | struct iwl3945_powertable_cmd cmd; |
b481de9c ZY |
2010 | |
2011 | /* If on battery, set to 3, | |
01ebd063 | 2012 | * if plugged into AC power, set to CAM ("continuously aware mode"), |
b481de9c ZY |
2013 | * else user level */ |
2014 | switch (mode) { | |
2015 | case IWL_POWER_BATTERY: | |
2016 | final_mode = IWL_POWER_INDEX_3; | |
2017 | break; | |
2018 | case IWL_POWER_AC: | |
2019 | final_mode = IWL_POWER_MODE_CAM; | |
2020 | break; | |
2021 | default: | |
2022 | final_mode = mode; | |
2023 | break; | |
2024 | } | |
2025 | ||
bb8c093b | 2026 | iwl3945_update_power_cmd(priv, &cmd, final_mode); |
b481de9c | 2027 | |
bb8c093b | 2028 | rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd); |
b481de9c ZY |
2029 | |
2030 | if (final_mode == IWL_POWER_MODE_CAM) | |
2031 | clear_bit(STATUS_POWER_PMI, &priv->status); | |
2032 | else | |
2033 | set_bit(STATUS_POWER_PMI, &priv->status); | |
2034 | ||
2035 | return rc; | |
2036 | } | |
2037 | ||
bb8c093b | 2038 | int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header) |
b481de9c ZY |
2039 | { |
2040 | /* Filter incoming packets to determine if they are targeted toward | |
2041 | * this network, discarding packets coming from ourselves */ | |
2042 | switch (priv->iw_mode) { | |
2043 | case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */ | |
2044 | /* packets from our adapter are dropped (echo) */ | |
2045 | if (!compare_ether_addr(header->addr2, priv->mac_addr)) | |
2046 | return 0; | |
2047 | /* {broad,multi}cast packets to our IBSS go through */ | |
2048 | if (is_multicast_ether_addr(header->addr1)) | |
2049 | return !compare_ether_addr(header->addr3, priv->bssid); | |
2050 | /* packets to our adapter go through */ | |
2051 | return !compare_ether_addr(header->addr1, priv->mac_addr); | |
2052 | case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */ | |
2053 | /* packets from our adapter are dropped (echo) */ | |
2054 | if (!compare_ether_addr(header->addr3, priv->mac_addr)) | |
2055 | return 0; | |
2056 | /* {broad,multi}cast packets to our BSS go through */ | |
2057 | if (is_multicast_ether_addr(header->addr1)) | |
2058 | return !compare_ether_addr(header->addr2, priv->bssid); | |
2059 | /* packets to our adapter go through */ | |
2060 | return !compare_ether_addr(header->addr1, priv->mac_addr); | |
69dc5d9d TW |
2061 | default: |
2062 | return 1; | |
b481de9c ZY |
2063 | } |
2064 | ||
2065 | return 1; | |
2066 | } | |
2067 | ||
b481de9c | 2068 | /** |
bb8c093b | 2069 | * iwl3945_scan_cancel - Cancel any currently executing HW scan |
b481de9c ZY |
2070 | * |
2071 | * NOTE: priv->mutex is not required before calling this function | |
2072 | */ | |
bb8c093b | 2073 | static int iwl3945_scan_cancel(struct iwl3945_priv *priv) |
b481de9c ZY |
2074 | { |
2075 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
2076 | clear_bit(STATUS_SCANNING, &priv->status); | |
2077 | return 0; | |
2078 | } | |
2079 | ||
2080 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
2081 | if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
2082 | IWL_DEBUG_SCAN("Queuing scan abort.\n"); | |
2083 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
2084 | queue_work(priv->workqueue, &priv->abort_scan); | |
2085 | ||
2086 | } else | |
2087 | IWL_DEBUG_SCAN("Scan abort already in progress.\n"); | |
2088 | ||
2089 | return test_bit(STATUS_SCANNING, &priv->status); | |
2090 | } | |
2091 | ||
2092 | return 0; | |
2093 | } | |
2094 | ||
2095 | /** | |
bb8c093b | 2096 | * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan |
b481de9c ZY |
2097 | * @ms: amount of time to wait (in milliseconds) for scan to abort |
2098 | * | |
2099 | * NOTE: priv->mutex must be held before calling this function | |
2100 | */ | |
bb8c093b | 2101 | static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms) |
b481de9c ZY |
2102 | { |
2103 | unsigned long now = jiffies; | |
2104 | int ret; | |
2105 | ||
bb8c093b | 2106 | ret = iwl3945_scan_cancel(priv); |
b481de9c ZY |
2107 | if (ret && ms) { |
2108 | mutex_unlock(&priv->mutex); | |
2109 | while (!time_after(jiffies, now + msecs_to_jiffies(ms)) && | |
2110 | test_bit(STATUS_SCANNING, &priv->status)) | |
2111 | msleep(1); | |
2112 | mutex_lock(&priv->mutex); | |
2113 | ||
2114 | return test_bit(STATUS_SCANNING, &priv->status); | |
2115 | } | |
2116 | ||
2117 | return ret; | |
2118 | } | |
2119 | ||
bb8c093b | 2120 | static void iwl3945_sequence_reset(struct iwl3945_priv *priv) |
b481de9c ZY |
2121 | { |
2122 | /* Reset ieee stats */ | |
2123 | ||
2124 | /* We don't reset the net_device_stats (ieee->stats) on | |
2125 | * re-association */ | |
2126 | ||
2127 | priv->last_seq_num = -1; | |
2128 | priv->last_frag_num = -1; | |
2129 | priv->last_packet_time = 0; | |
2130 | ||
bb8c093b | 2131 | iwl3945_scan_cancel(priv); |
b481de9c ZY |
2132 | } |
2133 | ||
2134 | #define MAX_UCODE_BEACON_INTERVAL 1024 | |
2135 | #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA) | |
2136 | ||
bb8c093b | 2137 | static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val) |
b481de9c ZY |
2138 | { |
2139 | u16 new_val = 0; | |
2140 | u16 beacon_factor = 0; | |
2141 | ||
2142 | beacon_factor = | |
2143 | (beacon_val + MAX_UCODE_BEACON_INTERVAL) | |
2144 | / MAX_UCODE_BEACON_INTERVAL; | |
2145 | new_val = beacon_val / beacon_factor; | |
2146 | ||
2147 | return cpu_to_le16(new_val); | |
2148 | } | |
2149 | ||
bb8c093b | 2150 | static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv) |
b481de9c ZY |
2151 | { |
2152 | u64 interval_tm_unit; | |
2153 | u64 tsf, result; | |
2154 | unsigned long flags; | |
2155 | struct ieee80211_conf *conf = NULL; | |
2156 | u16 beacon_int = 0; | |
2157 | ||
2158 | conf = ieee80211_get_hw_conf(priv->hw); | |
2159 | ||
2160 | spin_lock_irqsave(&priv->lock, flags); | |
2161 | priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1); | |
2162 | priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0); | |
2163 | ||
2164 | priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL; | |
2165 | ||
2166 | tsf = priv->timestamp1; | |
2167 | tsf = ((tsf << 32) | priv->timestamp0); | |
2168 | ||
2169 | beacon_int = priv->beacon_int; | |
2170 | spin_unlock_irqrestore(&priv->lock, flags); | |
2171 | ||
2172 | if (priv->iw_mode == IEEE80211_IF_TYPE_STA) { | |
2173 | if (beacon_int == 0) { | |
2174 | priv->rxon_timing.beacon_interval = cpu_to_le16(100); | |
2175 | priv->rxon_timing.beacon_init_val = cpu_to_le32(102400); | |
2176 | } else { | |
2177 | priv->rxon_timing.beacon_interval = | |
2178 | cpu_to_le16(beacon_int); | |
2179 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 2180 | iwl3945_adjust_beacon_interval( |
b481de9c ZY |
2181 | le16_to_cpu(priv->rxon_timing.beacon_interval)); |
2182 | } | |
2183 | ||
2184 | priv->rxon_timing.atim_window = 0; | |
2185 | } else { | |
2186 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 2187 | iwl3945_adjust_beacon_interval(conf->beacon_int); |
b481de9c ZY |
2188 | /* TODO: we need to get atim_window from upper stack |
2189 | * for now we set to 0 */ | |
2190 | priv->rxon_timing.atim_window = 0; | |
2191 | } | |
2192 | ||
2193 | interval_tm_unit = | |
2194 | (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024); | |
2195 | result = do_div(tsf, interval_tm_unit); | |
2196 | priv->rxon_timing.beacon_init_val = | |
2197 | cpu_to_le32((u32) ((u64) interval_tm_unit - result)); | |
2198 | ||
2199 | IWL_DEBUG_ASSOC | |
2200 | ("beacon interval %d beacon timer %d beacon tim %d\n", | |
2201 | le16_to_cpu(priv->rxon_timing.beacon_interval), | |
2202 | le32_to_cpu(priv->rxon_timing.beacon_init_val), | |
2203 | le16_to_cpu(priv->rxon_timing.atim_window)); | |
2204 | } | |
2205 | ||
bb8c093b | 2206 | static int iwl3945_scan_initiate(struct iwl3945_priv *priv) |
b481de9c ZY |
2207 | { |
2208 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
2209 | IWL_ERROR("APs don't scan.\n"); | |
2210 | return 0; | |
2211 | } | |
2212 | ||
bb8c093b | 2213 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
2214 | IWL_DEBUG_SCAN("Aborting scan due to not ready.\n"); |
2215 | return -EIO; | |
2216 | } | |
2217 | ||
2218 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
2219 | IWL_DEBUG_SCAN("Scan already in progress.\n"); | |
2220 | return -EAGAIN; | |
2221 | } | |
2222 | ||
2223 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
2224 | IWL_DEBUG_SCAN("Scan request while abort pending. " | |
2225 | "Queuing.\n"); | |
2226 | return -EAGAIN; | |
2227 | } | |
2228 | ||
2229 | IWL_DEBUG_INFO("Starting scan...\n"); | |
2230 | priv->scan_bands = 2; | |
2231 | set_bit(STATUS_SCANNING, &priv->status); | |
2232 | priv->scan_start = jiffies; | |
2233 | priv->scan_pass_start = priv->scan_start; | |
2234 | ||
2235 | queue_work(priv->workqueue, &priv->request_scan); | |
2236 | ||
2237 | return 0; | |
2238 | } | |
2239 | ||
bb8c093b | 2240 | static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt) |
b481de9c | 2241 | { |
bb8c093b | 2242 | struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon; |
b481de9c ZY |
2243 | |
2244 | if (hw_decrypt) | |
2245 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
2246 | else | |
2247 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
2248 | ||
2249 | return 0; | |
2250 | } | |
2251 | ||
8318d78a JB |
2252 | static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv, |
2253 | enum ieee80211_band band) | |
b481de9c | 2254 | { |
8318d78a | 2255 | if (band == IEEE80211_BAND_5GHZ) { |
b481de9c ZY |
2256 | priv->staging_rxon.flags &= |
2257 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK | |
2258 | | RXON_FLG_CCK_MSK); | |
2259 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2260 | } else { | |
bb8c093b | 2261 | /* Copied from iwl3945_bg_post_associate() */ |
b481de9c ZY |
2262 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
2263 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2264 | else | |
2265 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2266 | ||
2267 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
2268 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2269 | ||
2270 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; | |
2271 | priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
2272 | priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK; | |
2273 | } | |
2274 | } | |
2275 | ||
2276 | /* | |
01ebd063 | 2277 | * initialize rxon structure with default values from eeprom |
b481de9c | 2278 | */ |
bb8c093b | 2279 | static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv) |
b481de9c | 2280 | { |
bb8c093b | 2281 | const struct iwl3945_channel_info *ch_info; |
b481de9c ZY |
2282 | |
2283 | memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon)); | |
2284 | ||
2285 | switch (priv->iw_mode) { | |
2286 | case IEEE80211_IF_TYPE_AP: | |
2287 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP; | |
2288 | break; | |
2289 | ||
2290 | case IEEE80211_IF_TYPE_STA: | |
2291 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS; | |
2292 | priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; | |
2293 | break; | |
2294 | ||
2295 | case IEEE80211_IF_TYPE_IBSS: | |
2296 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS; | |
2297 | priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK; | |
2298 | priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
2299 | RXON_FILTER_ACCEPT_GRP_MSK; | |
2300 | break; | |
2301 | ||
2302 | case IEEE80211_IF_TYPE_MNTR: | |
2303 | priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER; | |
2304 | priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK | | |
2305 | RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK; | |
2306 | break; | |
69dc5d9d TW |
2307 | default: |
2308 | IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode); | |
2309 | break; | |
b481de9c ZY |
2310 | } |
2311 | ||
2312 | #if 0 | |
2313 | /* TODO: Figure out when short_preamble would be set and cache from | |
2314 | * that */ | |
2315 | if (!hw_to_local(priv->hw)->short_preamble) | |
2316 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2317 | else | |
2318 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2319 | #endif | |
2320 | ||
8318d78a | 2321 | ch_info = iwl3945_get_channel_info(priv, priv->band, |
b481de9c ZY |
2322 | le16_to_cpu(priv->staging_rxon.channel)); |
2323 | ||
2324 | if (!ch_info) | |
2325 | ch_info = &priv->channel_info[0]; | |
2326 | ||
2327 | /* | |
2328 | * in some case A channels are all non IBSS | |
2329 | * in this case force B/G channel | |
2330 | */ | |
2331 | if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) && | |
2332 | !(is_channel_ibss(ch_info))) | |
2333 | ch_info = &priv->channel_info[0]; | |
2334 | ||
2335 | priv->staging_rxon.channel = cpu_to_le16(ch_info->channel); | |
2336 | if (is_channel_a_band(ch_info)) | |
8318d78a | 2337 | priv->band = IEEE80211_BAND_5GHZ; |
b481de9c | 2338 | else |
8318d78a | 2339 | priv->band = IEEE80211_BAND_2GHZ; |
b481de9c | 2340 | |
8318d78a | 2341 | iwl3945_set_flags_for_phymode(priv, priv->band); |
b481de9c ZY |
2342 | |
2343 | priv->staging_rxon.ofdm_basic_rates = | |
2344 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
2345 | priv->staging_rxon.cck_basic_rates = | |
2346 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
2347 | } | |
2348 | ||
bb8c093b | 2349 | static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode) |
b481de9c | 2350 | { |
b481de9c | 2351 | if (mode == IEEE80211_IF_TYPE_IBSS) { |
bb8c093b | 2352 | const struct iwl3945_channel_info *ch_info; |
b481de9c | 2353 | |
bb8c093b | 2354 | ch_info = iwl3945_get_channel_info(priv, |
8318d78a | 2355 | priv->band, |
b481de9c ZY |
2356 | le16_to_cpu(priv->staging_rxon.channel)); |
2357 | ||
2358 | if (!ch_info || !is_channel_ibss(ch_info)) { | |
2359 | IWL_ERROR("channel %d not IBSS channel\n", | |
2360 | le16_to_cpu(priv->staging_rxon.channel)); | |
2361 | return -EINVAL; | |
2362 | } | |
2363 | } | |
2364 | ||
b481de9c ZY |
2365 | priv->iw_mode = mode; |
2366 | ||
bb8c093b | 2367 | iwl3945_connection_init_rx_config(priv); |
b481de9c ZY |
2368 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
2369 | ||
bb8c093b | 2370 | iwl3945_clear_stations_table(priv); |
b481de9c | 2371 | |
fde3571f MA |
2372 | /* dont commit rxon if rf-kill is on*/ |
2373 | if (!iwl3945_is_ready_rf(priv)) | |
2374 | return -EAGAIN; | |
2375 | ||
2376 | cancel_delayed_work(&priv->scan_check); | |
2377 | if (iwl3945_scan_cancel_timeout(priv, 100)) { | |
2378 | IWL_WARNING("Aborted scan still in progress after 100ms\n"); | |
2379 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
2380 | return -EAGAIN; | |
2381 | } | |
2382 | ||
bb8c093b | 2383 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
2384 | |
2385 | return 0; | |
2386 | } | |
2387 | ||
bb8c093b | 2388 | static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv, |
b481de9c | 2389 | struct ieee80211_tx_control *ctl, |
bb8c093b | 2390 | struct iwl3945_cmd *cmd, |
b481de9c ZY |
2391 | struct sk_buff *skb_frag, |
2392 | int last_frag) | |
2393 | { | |
bb8c093b | 2394 | struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo; |
b481de9c ZY |
2395 | |
2396 | switch (keyinfo->alg) { | |
2397 | case ALG_CCMP: | |
2398 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM; | |
2399 | memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen); | |
2400 | IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n"); | |
2401 | break; | |
2402 | ||
2403 | case ALG_TKIP: | |
2404 | #if 0 | |
2405 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP; | |
2406 | ||
2407 | if (last_frag) | |
2408 | memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8, | |
2409 | 8); | |
2410 | else | |
2411 | memset(cmd->cmd.tx.tkip_mic.byte, 0, 8); | |
2412 | #endif | |
2413 | break; | |
2414 | ||
2415 | case ALG_WEP: | |
2416 | cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP | | |
2417 | (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT; | |
2418 | ||
2419 | if (keyinfo->keylen == 13) | |
2420 | cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128; | |
2421 | ||
2422 | memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen); | |
2423 | ||
2424 | IWL_DEBUG_TX("Configuring packet for WEP encryption " | |
2425 | "with key %d\n", ctl->key_idx); | |
2426 | break; | |
2427 | ||
b481de9c ZY |
2428 | default: |
2429 | printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg); | |
2430 | break; | |
2431 | } | |
2432 | } | |
2433 | ||
2434 | /* | |
2435 | * handle build REPLY_TX command notification. | |
2436 | */ | |
bb8c093b CH |
2437 | static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv, |
2438 | struct iwl3945_cmd *cmd, | |
b481de9c ZY |
2439 | struct ieee80211_tx_control *ctrl, |
2440 | struct ieee80211_hdr *hdr, | |
2441 | int is_unicast, u8 std_id) | |
2442 | { | |
2443 | __le16 *qc; | |
2444 | u16 fc = le16_to_cpu(hdr->frame_control); | |
2445 | __le32 tx_flags = cmd->cmd.tx.tx_flags; | |
2446 | ||
2447 | cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
2448 | if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) { | |
2449 | tx_flags |= TX_CMD_FLG_ACK_MSK; | |
2450 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) | |
2451 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2452 | if (ieee80211_is_probe_response(fc) && | |
2453 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) | |
2454 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
2455 | } else { | |
2456 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
2457 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2458 | } | |
2459 | ||
2460 | cmd->cmd.tx.sta_id = std_id; | |
2461 | if (ieee80211_get_morefrag(hdr)) | |
2462 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; | |
2463 | ||
2464 | qc = ieee80211_get_qos_ctrl(hdr); | |
2465 | if (qc) { | |
2466 | cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf); | |
2467 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
2468 | } else | |
2469 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2470 | ||
2471 | if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) { | |
2472 | tx_flags |= TX_CMD_FLG_RTS_MSK; | |
2473 | tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
2474 | } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) { | |
2475 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
2476 | tx_flags |= TX_CMD_FLG_CTS_MSK; | |
2477 | } | |
2478 | ||
2479 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
2480 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
2481 | ||
2482 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
2483 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) { | |
2484 | if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ || | |
2485 | (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ) | |
bc434dd2 | 2486 | cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3); |
b481de9c | 2487 | else |
bc434dd2 | 2488 | cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2); |
ab53d8af | 2489 | } else { |
b481de9c | 2490 | cmd->cmd.tx.timeout.pm_frame_timeout = 0; |
ab53d8af MA |
2491 | #ifdef CONFIG_IWL3945_LEDS |
2492 | priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len); | |
2493 | #endif | |
2494 | } | |
b481de9c ZY |
2495 | |
2496 | cmd->cmd.tx.driver_txop = 0; | |
2497 | cmd->cmd.tx.tx_flags = tx_flags; | |
2498 | cmd->cmd.tx.next_frame_len = 0; | |
2499 | } | |
2500 | ||
6440adb5 CB |
2501 | /** |
2502 | * iwl3945_get_sta_id - Find station's index within station table | |
2503 | */ | |
bb8c093b | 2504 | static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr) |
b481de9c ZY |
2505 | { |
2506 | int sta_id; | |
2507 | u16 fc = le16_to_cpu(hdr->frame_control); | |
2508 | ||
6440adb5 | 2509 | /* If this frame is broadcast or management, use broadcast station id */ |
b481de9c ZY |
2510 | if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) || |
2511 | is_multicast_ether_addr(hdr->addr1)) | |
2512 | return priv->hw_setting.bcast_sta_id; | |
2513 | ||
2514 | switch (priv->iw_mode) { | |
2515 | ||
6440adb5 CB |
2516 | /* If we are a client station in a BSS network, use the special |
2517 | * AP station entry (that's the only station we communicate with) */ | |
b481de9c ZY |
2518 | case IEEE80211_IF_TYPE_STA: |
2519 | return IWL_AP_ID; | |
2520 | ||
2521 | /* If we are an AP, then find the station, or use BCAST */ | |
2522 | case IEEE80211_IF_TYPE_AP: | |
bb8c093b | 2523 | sta_id = iwl3945_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2524 | if (sta_id != IWL_INVALID_STATION) |
2525 | return sta_id; | |
2526 | return priv->hw_setting.bcast_sta_id; | |
2527 | ||
6440adb5 CB |
2528 | /* If this frame is going out to an IBSS network, find the station, |
2529 | * or create a new station table entry */ | |
0795af57 JP |
2530 | case IEEE80211_IF_TYPE_IBSS: { |
2531 | DECLARE_MAC_BUF(mac); | |
2532 | ||
6440adb5 | 2533 | /* Create new station table entry */ |
bb8c093b | 2534 | sta_id = iwl3945_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2535 | if (sta_id != IWL_INVALID_STATION) |
2536 | return sta_id; | |
2537 | ||
bb8c093b | 2538 | sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC); |
b481de9c ZY |
2539 | |
2540 | if (sta_id != IWL_INVALID_STATION) | |
2541 | return sta_id; | |
2542 | ||
0795af57 | 2543 | IWL_DEBUG_DROP("Station %s not in station map. " |
b481de9c | 2544 | "Defaulting to broadcast...\n", |
0795af57 | 2545 | print_mac(mac, hdr->addr1)); |
bb8c093b | 2546 | iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr)); |
b481de9c | 2547 | return priv->hw_setting.bcast_sta_id; |
0795af57 | 2548 | } |
b481de9c | 2549 | default: |
01ebd063 | 2550 | IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode); |
b481de9c ZY |
2551 | return priv->hw_setting.bcast_sta_id; |
2552 | } | |
2553 | } | |
2554 | ||
2555 | /* | |
2556 | * start REPLY_TX command process | |
2557 | */ | |
bb8c093b | 2558 | static int iwl3945_tx_skb(struct iwl3945_priv *priv, |
b481de9c ZY |
2559 | struct sk_buff *skb, struct ieee80211_tx_control *ctl) |
2560 | { | |
2561 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
bb8c093b | 2562 | struct iwl3945_tfd_frame *tfd; |
b481de9c ZY |
2563 | u32 *control_flags; |
2564 | int txq_id = ctl->queue; | |
bb8c093b CH |
2565 | struct iwl3945_tx_queue *txq = NULL; |
2566 | struct iwl3945_queue *q = NULL; | |
b481de9c ZY |
2567 | dma_addr_t phys_addr; |
2568 | dma_addr_t txcmd_phys; | |
bb8c093b | 2569 | struct iwl3945_cmd *out_cmd = NULL; |
b481de9c ZY |
2570 | u16 len, idx, len_org; |
2571 | u8 id, hdr_len, unicast; | |
2572 | u8 sta_id; | |
2573 | u16 seq_number = 0; | |
2574 | u16 fc; | |
2575 | __le16 *qc; | |
2576 | u8 wait_write_ptr = 0; | |
2577 | unsigned long flags; | |
2578 | int rc; | |
2579 | ||
2580 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 2581 | if (iwl3945_is_rfkill(priv)) { |
b481de9c ZY |
2582 | IWL_DEBUG_DROP("Dropping - RF KILL\n"); |
2583 | goto drop_unlock; | |
2584 | } | |
2585 | ||
32bfd35d JB |
2586 | if (!priv->vif) { |
2587 | IWL_DEBUG_DROP("Dropping - !priv->vif\n"); | |
b481de9c ZY |
2588 | goto drop_unlock; |
2589 | } | |
2590 | ||
8318d78a | 2591 | if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) { |
b481de9c ZY |
2592 | IWL_ERROR("ERROR: No TX rate available.\n"); |
2593 | goto drop_unlock; | |
2594 | } | |
2595 | ||
2596 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
2597 | id = 0; | |
2598 | ||
2599 | fc = le16_to_cpu(hdr->frame_control); | |
2600 | ||
c8b0e6e1 | 2601 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
2602 | if (ieee80211_is_auth(fc)) |
2603 | IWL_DEBUG_TX("Sending AUTH frame\n"); | |
2604 | else if (ieee80211_is_assoc_request(fc)) | |
2605 | IWL_DEBUG_TX("Sending ASSOC frame\n"); | |
2606 | else if (ieee80211_is_reassoc_request(fc)) | |
2607 | IWL_DEBUG_TX("Sending REASSOC frame\n"); | |
2608 | #endif | |
2609 | ||
7878a5a4 | 2610 | /* drop all data frame if we are not associated */ |
a6477249 RC |
2611 | if ((!iwl3945_is_associated(priv) || |
2612 | ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) && | |
b481de9c | 2613 | ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) { |
bb8c093b | 2614 | IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n"); |
b481de9c ZY |
2615 | goto drop_unlock; |
2616 | } | |
2617 | ||
2618 | spin_unlock_irqrestore(&priv->lock, flags); | |
2619 | ||
2620 | hdr_len = ieee80211_get_hdrlen(fc); | |
6440adb5 CB |
2621 | |
2622 | /* Find (or create) index into station table for destination station */ | |
bb8c093b | 2623 | sta_id = iwl3945_get_sta_id(priv, hdr); |
b481de9c | 2624 | if (sta_id == IWL_INVALID_STATION) { |
0795af57 JP |
2625 | DECLARE_MAC_BUF(mac); |
2626 | ||
2627 | IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n", | |
2628 | print_mac(mac, hdr->addr1)); | |
b481de9c ZY |
2629 | goto drop; |
2630 | } | |
2631 | ||
2632 | IWL_DEBUG_RATE("station Id %d\n", sta_id); | |
2633 | ||
2634 | qc = ieee80211_get_qos_ctrl(hdr); | |
2635 | if (qc) { | |
2636 | u8 tid = (u8)(le16_to_cpu(*qc) & 0xf); | |
2637 | seq_number = priv->stations[sta_id].tid[tid].seq_number & | |
2638 | IEEE80211_SCTL_SEQ; | |
2639 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
2640 | (hdr->seq_ctrl & | |
2641 | __constant_cpu_to_le16(IEEE80211_SCTL_FRAG)); | |
2642 | seq_number += 0x10; | |
2643 | } | |
6440adb5 CB |
2644 | |
2645 | /* Descriptor for chosen Tx queue */ | |
b481de9c ZY |
2646 | txq = &priv->txq[txq_id]; |
2647 | q = &txq->q; | |
2648 | ||
2649 | spin_lock_irqsave(&priv->lock, flags); | |
2650 | ||
6440adb5 | 2651 | /* Set up first empty TFD within this queue's circular TFD buffer */ |
fc4b6853 | 2652 | tfd = &txq->bd[q->write_ptr]; |
b481de9c ZY |
2653 | memset(tfd, 0, sizeof(*tfd)); |
2654 | control_flags = (u32 *) tfd; | |
fc4b6853 | 2655 | idx = get_cmd_index(q, q->write_ptr, 0); |
b481de9c | 2656 | |
6440adb5 | 2657 | /* Set up driver data for this TFD */ |
bb8c093b | 2658 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info)); |
fc4b6853 TW |
2659 | txq->txb[q->write_ptr].skb[0] = skb; |
2660 | memcpy(&(txq->txb[q->write_ptr].status.control), | |
b481de9c | 2661 | ctl, sizeof(struct ieee80211_tx_control)); |
6440adb5 CB |
2662 | |
2663 | /* Init first empty entry in queue's array of Tx/cmd buffers */ | |
b481de9c ZY |
2664 | out_cmd = &txq->cmd[idx]; |
2665 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
2666 | memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx)); | |
6440adb5 CB |
2667 | |
2668 | /* | |
2669 | * Set up the Tx-command (not MAC!) header. | |
2670 | * Store the chosen Tx queue and TFD index within the sequence field; | |
2671 | * after Tx, uCode's Tx response will return this value so driver can | |
2672 | * locate the frame within the tx queue and do post-tx processing. | |
2673 | */ | |
b481de9c ZY |
2674 | out_cmd->hdr.cmd = REPLY_TX; |
2675 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
fc4b6853 | 2676 | INDEX_TO_SEQ(q->write_ptr))); |
6440adb5 CB |
2677 | |
2678 | /* Copy MAC header from skb into command buffer */ | |
b481de9c ZY |
2679 | memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len); |
2680 | ||
6440adb5 CB |
2681 | /* |
2682 | * Use the first empty entry in this queue's command buffer array | |
2683 | * to contain the Tx command and MAC header concatenated together | |
2684 | * (payload data will be in another buffer). | |
2685 | * Size of this varies, due to varying MAC header length. | |
2686 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
2687 | * of the MAC header (device reads on dword boundaries). | |
2688 | * We'll tell device about this padding later. | |
2689 | */ | |
b481de9c | 2690 | len = priv->hw_setting.tx_cmd_len + |
bb8c093b | 2691 | sizeof(struct iwl3945_cmd_header) + hdr_len; |
b481de9c ZY |
2692 | |
2693 | len_org = len; | |
2694 | len = (len + 3) & ~3; | |
2695 | ||
2696 | if (len_org != len) | |
2697 | len_org = 1; | |
2698 | else | |
2699 | len_org = 0; | |
2700 | ||
6440adb5 CB |
2701 | /* Physical address of this Tx command's header (not MAC header!), |
2702 | * within command buffer array. */ | |
bb8c093b CH |
2703 | txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx + |
2704 | offsetof(struct iwl3945_cmd, hdr); | |
b481de9c | 2705 | |
6440adb5 CB |
2706 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
2707 | * first entry */ | |
bb8c093b | 2708 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len); |
b481de9c ZY |
2709 | |
2710 | if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) | |
bb8c093b | 2711 | iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0); |
b481de9c | 2712 | |
6440adb5 CB |
2713 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
2714 | * if any (802.11 null frames have no payload). */ | |
b481de9c ZY |
2715 | len = skb->len - hdr_len; |
2716 | if (len) { | |
2717 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
2718 | len, PCI_DMA_TODEVICE); | |
bb8c093b | 2719 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len); |
b481de9c ZY |
2720 | } |
2721 | ||
b481de9c | 2722 | if (!len) |
6440adb5 | 2723 | /* If there is no payload, then we use only one Tx buffer */ |
b481de9c ZY |
2724 | *control_flags = TFD_CTL_COUNT_SET(1); |
2725 | else | |
6440adb5 CB |
2726 | /* Else use 2 buffers. |
2727 | * Tell 3945 about any padding after MAC header */ | |
b481de9c ZY |
2728 | *control_flags = TFD_CTL_COUNT_SET(2) | |
2729 | TFD_CTL_PAD_SET(U32_PAD(len)); | |
2730 | ||
6440adb5 | 2731 | /* Total # bytes to be transmitted */ |
b481de9c ZY |
2732 | len = (u16)skb->len; |
2733 | out_cmd->cmd.tx.len = cpu_to_le16(len); | |
2734 | ||
2735 | /* TODO need this for burst mode later on */ | |
bb8c093b | 2736 | iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id); |
b481de9c ZY |
2737 | |
2738 | /* set is_hcca to 0; it probably will never be implemented */ | |
bb8c093b | 2739 | iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0); |
b481de9c ZY |
2740 | |
2741 | out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK; | |
2742 | out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK; | |
2743 | ||
2744 | if (!ieee80211_get_morefrag(hdr)) { | |
2745 | txq->need_update = 1; | |
2746 | if (qc) { | |
2747 | u8 tid = (u8)(le16_to_cpu(*qc) & 0xf); | |
2748 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
2749 | } | |
2750 | } else { | |
2751 | wait_write_ptr = 1; | |
2752 | txq->need_update = 0; | |
2753 | } | |
2754 | ||
bb8c093b | 2755 | iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload, |
b481de9c ZY |
2756 | sizeof(out_cmd->cmd.tx)); |
2757 | ||
bb8c093b | 2758 | iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr, |
b481de9c ZY |
2759 | ieee80211_get_hdrlen(fc)); |
2760 | ||
6440adb5 | 2761 | /* Tell device the write index *just past* this latest filled TFD */ |
c54b679d | 2762 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
bb8c093b | 2763 | rc = iwl3945_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
2764 | spin_unlock_irqrestore(&priv->lock, flags); |
2765 | ||
2766 | if (rc) | |
2767 | return rc; | |
2768 | ||
bb8c093b | 2769 | if ((iwl3945_queue_space(q) < q->high_mark) |
b481de9c ZY |
2770 | && priv->mac80211_registered) { |
2771 | if (wait_write_ptr) { | |
2772 | spin_lock_irqsave(&priv->lock, flags); | |
2773 | txq->need_update = 1; | |
bb8c093b | 2774 | iwl3945_tx_queue_update_write_ptr(priv, txq); |
b481de9c ZY |
2775 | spin_unlock_irqrestore(&priv->lock, flags); |
2776 | } | |
2777 | ||
2778 | ieee80211_stop_queue(priv->hw, ctl->queue); | |
2779 | } | |
2780 | ||
2781 | return 0; | |
2782 | ||
2783 | drop_unlock: | |
2784 | spin_unlock_irqrestore(&priv->lock, flags); | |
2785 | drop: | |
2786 | return -1; | |
2787 | } | |
2788 | ||
bb8c093b | 2789 | static void iwl3945_set_rate(struct iwl3945_priv *priv) |
b481de9c | 2790 | { |
8318d78a | 2791 | const struct ieee80211_supported_band *sband = NULL; |
b481de9c ZY |
2792 | struct ieee80211_rate *rate; |
2793 | int i; | |
2794 | ||
8318d78a JB |
2795 | sband = iwl3945_get_band(priv, priv->band); |
2796 | if (!sband) { | |
c4ba9621 SA |
2797 | IWL_ERROR("Failed to set rate: unable to get hw mode\n"); |
2798 | return; | |
2799 | } | |
b481de9c ZY |
2800 | |
2801 | priv->active_rate = 0; | |
2802 | priv->active_rate_basic = 0; | |
2803 | ||
8318d78a JB |
2804 | IWL_DEBUG_RATE("Setting rates for %s GHz\n", |
2805 | sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5"); | |
2806 | ||
2807 | for (i = 0; i < sband->n_bitrates; i++) { | |
2808 | rate = &sband->bitrates[i]; | |
2809 | if ((rate->hw_value < IWL_RATE_COUNT) && | |
2810 | !(rate->flags & IEEE80211_CHAN_DISABLED)) { | |
2811 | IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n", | |
2812 | rate->hw_value, iwl3945_rates[rate->hw_value].plcp); | |
2813 | priv->active_rate |= (1 << rate->hw_value); | |
2814 | } | |
b481de9c ZY |
2815 | } |
2816 | ||
2817 | IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n", | |
2818 | priv->active_rate, priv->active_rate_basic); | |
2819 | ||
2820 | /* | |
2821 | * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK) | |
2822 | * otherwise set it to the default of all CCK rates and 6, 12, 24 for | |
2823 | * OFDM | |
2824 | */ | |
2825 | if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK) | |
2826 | priv->staging_rxon.cck_basic_rates = | |
2827 | ((priv->active_rate_basic & | |
2828 | IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF; | |
2829 | else | |
2830 | priv->staging_rxon.cck_basic_rates = | |
2831 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
2832 | ||
2833 | if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK) | |
2834 | priv->staging_rxon.ofdm_basic_rates = | |
2835 | ((priv->active_rate_basic & | |
2836 | (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >> | |
2837 | IWL_FIRST_OFDM_RATE) & 0xFF; | |
2838 | else | |
2839 | priv->staging_rxon.ofdm_basic_rates = | |
2840 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
2841 | } | |
2842 | ||
bb8c093b | 2843 | static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio) |
b481de9c ZY |
2844 | { |
2845 | unsigned long flags; | |
2846 | ||
2847 | if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status)) | |
2848 | return; | |
2849 | ||
2850 | IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n", | |
2851 | disable_radio ? "OFF" : "ON"); | |
2852 | ||
2853 | if (disable_radio) { | |
bb8c093b | 2854 | iwl3945_scan_cancel(priv); |
b481de9c ZY |
2855 | /* FIXME: This is a workaround for AP */ |
2856 | if (priv->iw_mode != IEEE80211_IF_TYPE_AP) { | |
2857 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 2858 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
2859 | CSR_UCODE_SW_BIT_RFKILL); |
2860 | spin_unlock_irqrestore(&priv->lock, flags); | |
bb8c093b | 2861 | iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0); |
b481de9c ZY |
2862 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
2863 | } | |
2864 | return; | |
2865 | } | |
2866 | ||
2867 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 2868 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
b481de9c ZY |
2869 | |
2870 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
2871 | spin_unlock_irqrestore(&priv->lock, flags); | |
2872 | ||
2873 | /* wake up ucode */ | |
2874 | msleep(10); | |
2875 | ||
2876 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b CH |
2877 | iwl3945_read32(priv, CSR_UCODE_DRV_GP1); |
2878 | if (!iwl3945_grab_nic_access(priv)) | |
2879 | iwl3945_release_nic_access(priv); | |
b481de9c ZY |
2880 | spin_unlock_irqrestore(&priv->lock, flags); |
2881 | ||
2882 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
2883 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
2884 | "disabled by HW switch\n"); | |
2885 | return; | |
2886 | } | |
2887 | ||
2888 | queue_work(priv->workqueue, &priv->restart); | |
2889 | return; | |
2890 | } | |
2891 | ||
bb8c093b | 2892 | void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb, |
b481de9c ZY |
2893 | u32 decrypt_res, struct ieee80211_rx_status *stats) |
2894 | { | |
2895 | u16 fc = | |
2896 | le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control); | |
2897 | ||
2898 | if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) | |
2899 | return; | |
2900 | ||
2901 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
2902 | return; | |
2903 | ||
2904 | IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res); | |
2905 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { | |
2906 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
2907 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2908 | RX_RES_STATUS_BAD_ICV_MIC) | |
2909 | stats->flag |= RX_FLAG_MMIC_ERROR; | |
2910 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
2911 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
2912 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2913 | RX_RES_STATUS_DECRYPT_OK) { | |
2914 | IWL_DEBUG_RX("hw decrypt successfully!!!\n"); | |
2915 | stats->flag |= RX_FLAG_DECRYPTED; | |
2916 | } | |
2917 | break; | |
2918 | ||
2919 | default: | |
2920 | break; | |
2921 | } | |
2922 | } | |
2923 | ||
b481de9c ZY |
2924 | #define IWL_PACKET_RETRY_TIME HZ |
2925 | ||
bb8c093b | 2926 | int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header) |
b481de9c ZY |
2927 | { |
2928 | u16 sc = le16_to_cpu(header->seq_ctrl); | |
2929 | u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4; | |
2930 | u16 frag = sc & IEEE80211_SCTL_FRAG; | |
2931 | u16 *last_seq, *last_frag; | |
2932 | unsigned long *last_time; | |
2933 | ||
2934 | switch (priv->iw_mode) { | |
2935 | case IEEE80211_IF_TYPE_IBSS:{ | |
2936 | struct list_head *p; | |
bb8c093b | 2937 | struct iwl3945_ibss_seq *entry = NULL; |
b481de9c ZY |
2938 | u8 *mac = header->addr2; |
2939 | int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1); | |
2940 | ||
2941 | __list_for_each(p, &priv->ibss_mac_hash[index]) { | |
bb8c093b | 2942 | entry = list_entry(p, struct iwl3945_ibss_seq, list); |
b481de9c ZY |
2943 | if (!compare_ether_addr(entry->mac, mac)) |
2944 | break; | |
2945 | } | |
2946 | if (p == &priv->ibss_mac_hash[index]) { | |
2947 | entry = kzalloc(sizeof(*entry), GFP_ATOMIC); | |
2948 | if (!entry) { | |
bc434dd2 | 2949 | IWL_ERROR("Cannot malloc new mac entry\n"); |
b481de9c ZY |
2950 | return 0; |
2951 | } | |
2952 | memcpy(entry->mac, mac, ETH_ALEN); | |
2953 | entry->seq_num = seq; | |
2954 | entry->frag_num = frag; | |
2955 | entry->packet_time = jiffies; | |
bc434dd2 | 2956 | list_add(&entry->list, &priv->ibss_mac_hash[index]); |
b481de9c ZY |
2957 | return 0; |
2958 | } | |
2959 | last_seq = &entry->seq_num; | |
2960 | last_frag = &entry->frag_num; | |
2961 | last_time = &entry->packet_time; | |
2962 | break; | |
2963 | } | |
2964 | case IEEE80211_IF_TYPE_STA: | |
2965 | last_seq = &priv->last_seq_num; | |
2966 | last_frag = &priv->last_frag_num; | |
2967 | last_time = &priv->last_packet_time; | |
2968 | break; | |
2969 | default: | |
2970 | return 0; | |
2971 | } | |
2972 | if ((*last_seq == seq) && | |
2973 | time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) { | |
2974 | if (*last_frag == frag) | |
2975 | goto drop; | |
2976 | if (*last_frag + 1 != frag) | |
2977 | /* out-of-order fragment */ | |
2978 | goto drop; | |
2979 | } else | |
2980 | *last_seq = seq; | |
2981 | ||
2982 | *last_frag = frag; | |
2983 | *last_time = jiffies; | |
2984 | return 0; | |
2985 | ||
2986 | drop: | |
2987 | return 1; | |
2988 | } | |
2989 | ||
c8b0e6e1 | 2990 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
2991 | |
2992 | #include "iwl-spectrum.h" | |
2993 | ||
2994 | #define BEACON_TIME_MASK_LOW 0x00FFFFFF | |
2995 | #define BEACON_TIME_MASK_HIGH 0xFF000000 | |
2996 | #define TIME_UNIT 1024 | |
2997 | ||
2998 | /* | |
2999 | * extended beacon time format | |
3000 | * time in usec will be changed into a 32-bit value in 8:24 format | |
3001 | * the high 1 byte is the beacon counts | |
3002 | * the lower 3 bytes is the time in usec within one beacon interval | |
3003 | */ | |
3004 | ||
bb8c093b | 3005 | static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval) |
b481de9c ZY |
3006 | { |
3007 | u32 quot; | |
3008 | u32 rem; | |
3009 | u32 interval = beacon_interval * 1024; | |
3010 | ||
3011 | if (!interval || !usec) | |
3012 | return 0; | |
3013 | ||
3014 | quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24); | |
3015 | rem = (usec % interval) & BEACON_TIME_MASK_LOW; | |
3016 | ||
3017 | return (quot << 24) + rem; | |
3018 | } | |
3019 | ||
3020 | /* base is usually what we get from ucode with each received frame, | |
3021 | * the same as HW timer counter counting down | |
3022 | */ | |
3023 | ||
bb8c093b | 3024 | static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval) |
b481de9c ZY |
3025 | { |
3026 | u32 base_low = base & BEACON_TIME_MASK_LOW; | |
3027 | u32 addon_low = addon & BEACON_TIME_MASK_LOW; | |
3028 | u32 interval = beacon_interval * TIME_UNIT; | |
3029 | u32 res = (base & BEACON_TIME_MASK_HIGH) + | |
3030 | (addon & BEACON_TIME_MASK_HIGH); | |
3031 | ||
3032 | if (base_low > addon_low) | |
3033 | res += base_low - addon_low; | |
3034 | else if (base_low < addon_low) { | |
3035 | res += interval + base_low - addon_low; | |
3036 | res += (1 << 24); | |
3037 | } else | |
3038 | res += (1 << 24); | |
3039 | ||
3040 | return cpu_to_le32(res); | |
3041 | } | |
3042 | ||
bb8c093b | 3043 | static int iwl3945_get_measurement(struct iwl3945_priv *priv, |
b481de9c ZY |
3044 | struct ieee80211_measurement_params *params, |
3045 | u8 type) | |
3046 | { | |
bb8c093b CH |
3047 | struct iwl3945_spectrum_cmd spectrum; |
3048 | struct iwl3945_rx_packet *res; | |
3049 | struct iwl3945_host_cmd cmd = { | |
b481de9c ZY |
3050 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
3051 | .data = (void *)&spectrum, | |
3052 | .meta.flags = CMD_WANT_SKB, | |
3053 | }; | |
3054 | u32 add_time = le64_to_cpu(params->start_time); | |
3055 | int rc; | |
3056 | int spectrum_resp_status; | |
3057 | int duration = le16_to_cpu(params->duration); | |
3058 | ||
bb8c093b | 3059 | if (iwl3945_is_associated(priv)) |
b481de9c | 3060 | add_time = |
bb8c093b | 3061 | iwl3945_usecs_to_beacons( |
b481de9c ZY |
3062 | le64_to_cpu(params->start_time) - priv->last_tsf, |
3063 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
3064 | ||
3065 | memset(&spectrum, 0, sizeof(spectrum)); | |
3066 | ||
3067 | spectrum.channel_count = cpu_to_le16(1); | |
3068 | spectrum.flags = | |
3069 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
3070 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
3071 | cmd.len = sizeof(spectrum); | |
3072 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
3073 | ||
bb8c093b | 3074 | if (iwl3945_is_associated(priv)) |
b481de9c | 3075 | spectrum.start_time = |
bb8c093b | 3076 | iwl3945_add_beacon_time(priv->last_beacon_time, |
b481de9c ZY |
3077 | add_time, |
3078 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
3079 | else | |
3080 | spectrum.start_time = 0; | |
3081 | ||
3082 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
3083 | spectrum.channels[0].channel = params->channel; | |
3084 | spectrum.channels[0].type = type; | |
3085 | if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK) | |
3086 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | | |
3087 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
3088 | ||
bb8c093b | 3089 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
3090 | if (rc) |
3091 | return rc; | |
3092 | ||
bb8c093b | 3093 | res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
3094 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
3095 | IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n"); | |
3096 | rc = -EIO; | |
3097 | } | |
3098 | ||
3099 | spectrum_resp_status = le16_to_cpu(res->u.spectrum.status); | |
3100 | switch (spectrum_resp_status) { | |
3101 | case 0: /* Command will be handled */ | |
3102 | if (res->u.spectrum.id != 0xff) { | |
bc434dd2 IS |
3103 | IWL_DEBUG_INFO("Replaced existing measurement: %d\n", |
3104 | res->u.spectrum.id); | |
b481de9c ZY |
3105 | priv->measurement_status &= ~MEASUREMENT_READY; |
3106 | } | |
3107 | priv->measurement_status |= MEASUREMENT_ACTIVE; | |
3108 | rc = 0; | |
3109 | break; | |
3110 | ||
3111 | case 1: /* Command will not be handled */ | |
3112 | rc = -EAGAIN; | |
3113 | break; | |
3114 | } | |
3115 | ||
3116 | dev_kfree_skb_any(cmd.meta.u.skb); | |
3117 | ||
3118 | return rc; | |
3119 | } | |
3120 | #endif | |
3121 | ||
bb8c093b CH |
3122 | static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv, |
3123 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3124 | { |
bb8c093b CH |
3125 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3126 | struct iwl3945_alive_resp *palive; | |
b481de9c ZY |
3127 | struct delayed_work *pwork; |
3128 | ||
3129 | palive = &pkt->u.alive_frame; | |
3130 | ||
3131 | IWL_DEBUG_INFO("Alive ucode status 0x%08X revision " | |
3132 | "0x%01X 0x%01X\n", | |
3133 | palive->is_valid, palive->ver_type, | |
3134 | palive->ver_subtype); | |
3135 | ||
3136 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
3137 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
3138 | memcpy(&priv->card_alive_init, | |
3139 | &pkt->u.alive_frame, | |
bb8c093b | 3140 | sizeof(struct iwl3945_init_alive_resp)); |
b481de9c ZY |
3141 | pwork = &priv->init_alive_start; |
3142 | } else { | |
3143 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
3144 | memcpy(&priv->card_alive, &pkt->u.alive_frame, | |
bb8c093b | 3145 | sizeof(struct iwl3945_alive_resp)); |
b481de9c | 3146 | pwork = &priv->alive_start; |
bb8c093b | 3147 | iwl3945_disable_events(priv); |
b481de9c ZY |
3148 | } |
3149 | ||
3150 | /* We delay the ALIVE response by 5ms to | |
3151 | * give the HW RF Kill time to activate... */ | |
3152 | if (palive->is_valid == UCODE_VALID_OK) | |
3153 | queue_delayed_work(priv->workqueue, pwork, | |
3154 | msecs_to_jiffies(5)); | |
3155 | else | |
3156 | IWL_WARNING("uCode did not respond OK.\n"); | |
3157 | } | |
3158 | ||
bb8c093b CH |
3159 | static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv, |
3160 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3161 | { |
bb8c093b | 3162 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3163 | |
3164 | IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); | |
3165 | return; | |
3166 | } | |
3167 | ||
bb8c093b CH |
3168 | static void iwl3945_rx_reply_error(struct iwl3945_priv *priv, |
3169 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3170 | { |
bb8c093b | 3171 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3172 | |
3173 | IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) " | |
3174 | "seq 0x%04X ser 0x%08X\n", | |
3175 | le32_to_cpu(pkt->u.err_resp.error_type), | |
3176 | get_cmd_string(pkt->u.err_resp.cmd_id), | |
3177 | pkt->u.err_resp.cmd_id, | |
3178 | le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num), | |
3179 | le32_to_cpu(pkt->u.err_resp.error_info)); | |
3180 | } | |
3181 | ||
3182 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x | |
3183 | ||
bb8c093b | 3184 | static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb) |
b481de9c | 3185 | { |
bb8c093b CH |
3186 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3187 | struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon; | |
3188 | struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif); | |
b481de9c ZY |
3189 | IWL_DEBUG_11H("CSA notif: channel %d, status %d\n", |
3190 | le16_to_cpu(csa->channel), le32_to_cpu(csa->status)); | |
3191 | rxon->channel = csa->channel; | |
3192 | priv->staging_rxon.channel = csa->channel; | |
3193 | } | |
3194 | ||
bb8c093b CH |
3195 | static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv, |
3196 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3197 | { |
c8b0e6e1 | 3198 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
bb8c093b CH |
3199 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3200 | struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif); | |
b481de9c ZY |
3201 | |
3202 | if (!report->state) { | |
3203 | IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO, | |
3204 | "Spectrum Measure Notification: Start\n"); | |
3205 | return; | |
3206 | } | |
3207 | ||
3208 | memcpy(&priv->measure_report, report, sizeof(*report)); | |
3209 | priv->measurement_status |= MEASUREMENT_READY; | |
3210 | #endif | |
3211 | } | |
3212 | ||
bb8c093b CH |
3213 | static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv, |
3214 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3215 | { |
c8b0e6e1 | 3216 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
3217 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3218 | struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif); | |
b481de9c ZY |
3219 | IWL_DEBUG_RX("sleep mode: %d, src: %d\n", |
3220 | sleep->pm_sleep_mode, sleep->pm_wakeup_src); | |
3221 | #endif | |
3222 | } | |
3223 | ||
bb8c093b CH |
3224 | static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv, |
3225 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3226 | { |
bb8c093b | 3227 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3228 | IWL_DEBUG_RADIO("Dumping %d bytes of unhandled " |
3229 | "notification for %s:\n", | |
3230 | le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd)); | |
bb8c093b | 3231 | iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len)); |
b481de9c ZY |
3232 | } |
3233 | ||
bb8c093b | 3234 | static void iwl3945_bg_beacon_update(struct work_struct *work) |
b481de9c | 3235 | { |
bb8c093b CH |
3236 | struct iwl3945_priv *priv = |
3237 | container_of(work, struct iwl3945_priv, beacon_update); | |
b481de9c ZY |
3238 | struct sk_buff *beacon; |
3239 | ||
3240 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
32bfd35d | 3241 | beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL); |
b481de9c ZY |
3242 | |
3243 | if (!beacon) { | |
3244 | IWL_ERROR("update beacon failed\n"); | |
3245 | return; | |
3246 | } | |
3247 | ||
3248 | mutex_lock(&priv->mutex); | |
3249 | /* new beacon skb is allocated every time; dispose previous.*/ | |
3250 | if (priv->ibss_beacon) | |
3251 | dev_kfree_skb(priv->ibss_beacon); | |
3252 | ||
3253 | priv->ibss_beacon = beacon; | |
3254 | mutex_unlock(&priv->mutex); | |
3255 | ||
bb8c093b | 3256 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
3257 | } |
3258 | ||
bb8c093b CH |
3259 | static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv, |
3260 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3261 | { |
c8b0e6e1 | 3262 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
3263 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3264 | struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status); | |
b481de9c ZY |
3265 | u8 rate = beacon->beacon_notify_hdr.rate; |
3266 | ||
3267 | IWL_DEBUG_RX("beacon status %x retries %d iss %d " | |
3268 | "tsf %d %d rate %d\n", | |
3269 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
3270 | beacon->beacon_notify_hdr.failure_frame, | |
3271 | le32_to_cpu(beacon->ibss_mgr_status), | |
3272 | le32_to_cpu(beacon->high_tsf), | |
3273 | le32_to_cpu(beacon->low_tsf), rate); | |
3274 | #endif | |
3275 | ||
3276 | if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) && | |
3277 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) | |
3278 | queue_work(priv->workqueue, &priv->beacon_update); | |
3279 | } | |
3280 | ||
3281 | /* Service response to REPLY_SCAN_CMD (0x80) */ | |
bb8c093b CH |
3282 | static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv, |
3283 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3284 | { |
c8b0e6e1 | 3285 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
3286 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3287 | struct iwl3945_scanreq_notification *notif = | |
3288 | (struct iwl3945_scanreq_notification *)pkt->u.raw; | |
b481de9c ZY |
3289 | |
3290 | IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status); | |
3291 | #endif | |
3292 | } | |
3293 | ||
3294 | /* Service SCAN_START_NOTIFICATION (0x82) */ | |
bb8c093b CH |
3295 | static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv, |
3296 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3297 | { |
bb8c093b CH |
3298 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3299 | struct iwl3945_scanstart_notification *notif = | |
3300 | (struct iwl3945_scanstart_notification *)pkt->u.raw; | |
b481de9c ZY |
3301 | priv->scan_start_tsf = le32_to_cpu(notif->tsf_low); |
3302 | IWL_DEBUG_SCAN("Scan start: " | |
3303 | "%d [802.11%s] " | |
3304 | "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", | |
3305 | notif->channel, | |
3306 | notif->band ? "bg" : "a", | |
3307 | notif->tsf_high, | |
3308 | notif->tsf_low, notif->status, notif->beacon_timer); | |
3309 | } | |
3310 | ||
3311 | /* Service SCAN_RESULTS_NOTIFICATION (0x83) */ | |
bb8c093b CH |
3312 | static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv, |
3313 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3314 | { |
bb8c093b CH |
3315 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3316 | struct iwl3945_scanresults_notification *notif = | |
3317 | (struct iwl3945_scanresults_notification *)pkt->u.raw; | |
b481de9c ZY |
3318 | |
3319 | IWL_DEBUG_SCAN("Scan ch.res: " | |
3320 | "%d [802.11%s] " | |
3321 | "(TSF: 0x%08X:%08X) - %d " | |
3322 | "elapsed=%lu usec (%dms since last)\n", | |
3323 | notif->channel, | |
3324 | notif->band ? "bg" : "a", | |
3325 | le32_to_cpu(notif->tsf_high), | |
3326 | le32_to_cpu(notif->tsf_low), | |
3327 | le32_to_cpu(notif->statistics[0]), | |
3328 | le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf, | |
3329 | jiffies_to_msecs(elapsed_jiffies | |
3330 | (priv->last_scan_jiffies, jiffies))); | |
3331 | ||
3332 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 3333 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
3334 | } |
3335 | ||
3336 | /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */ | |
bb8c093b CH |
3337 | static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv, |
3338 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3339 | { |
bb8c093b CH |
3340 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
3341 | struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw; | |
b481de9c ZY |
3342 | |
3343 | IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n", | |
3344 | scan_notif->scanned_channels, | |
3345 | scan_notif->tsf_low, | |
3346 | scan_notif->tsf_high, scan_notif->status); | |
3347 | ||
3348 | /* The HW is no longer scanning */ | |
3349 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
3350 | ||
3351 | /* The scan completion notification came in, so kill that timer... */ | |
3352 | cancel_delayed_work(&priv->scan_check); | |
3353 | ||
3354 | IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n", | |
3355 | (priv->scan_bands == 2) ? "2.4" : "5.2", | |
3356 | jiffies_to_msecs(elapsed_jiffies | |
3357 | (priv->scan_pass_start, jiffies))); | |
3358 | ||
3359 | /* Remove this scanned band from the list | |
3360 | * of pending bands to scan */ | |
3361 | priv->scan_bands--; | |
3362 | ||
3363 | /* If a request to abort was given, or the scan did not succeed | |
3364 | * then we reset the scan state machine and terminate, | |
3365 | * re-queuing another scan if one has been requested */ | |
3366 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
3367 | IWL_DEBUG_INFO("Aborted scan completed.\n"); | |
3368 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
3369 | } else { | |
3370 | /* If there are more bands on this scan pass reschedule */ | |
3371 | if (priv->scan_bands > 0) | |
3372 | goto reschedule; | |
3373 | } | |
3374 | ||
3375 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 3376 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
3377 | IWL_DEBUG_INFO("Setting scan to off\n"); |
3378 | ||
3379 | clear_bit(STATUS_SCANNING, &priv->status); | |
3380 | ||
3381 | IWL_DEBUG_INFO("Scan took %dms\n", | |
3382 | jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies))); | |
3383 | ||
3384 | queue_work(priv->workqueue, &priv->scan_completed); | |
3385 | ||
3386 | return; | |
3387 | ||
3388 | reschedule: | |
3389 | priv->scan_pass_start = jiffies; | |
3390 | queue_work(priv->workqueue, &priv->request_scan); | |
3391 | } | |
3392 | ||
3393 | /* Handle notification from uCode that card's power state is changing | |
3394 | * due to software, hardware, or critical temperature RFKILL */ | |
bb8c093b CH |
3395 | static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv, |
3396 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3397 | { |
bb8c093b | 3398 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3399 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
3400 | unsigned long status = priv->status; | |
3401 | ||
3402 | IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n", | |
3403 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
3404 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
3405 | ||
bb8c093b | 3406 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
3407 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
3408 | ||
3409 | if (flags & HW_CARD_DISABLED) | |
3410 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
3411 | else | |
3412 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3413 | ||
3414 | ||
3415 | if (flags & SW_CARD_DISABLED) | |
3416 | set_bit(STATUS_RF_KILL_SW, &priv->status); | |
3417 | else | |
3418 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
3419 | ||
bb8c093b | 3420 | iwl3945_scan_cancel(priv); |
b481de9c ZY |
3421 | |
3422 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
3423 | test_bit(STATUS_RF_KILL_HW, &priv->status)) || | |
3424 | (test_bit(STATUS_RF_KILL_SW, &status) != | |
3425 | test_bit(STATUS_RF_KILL_SW, &priv->status))) | |
3426 | queue_work(priv->workqueue, &priv->rf_kill); | |
3427 | else | |
3428 | wake_up_interruptible(&priv->wait_command_queue); | |
3429 | } | |
3430 | ||
3431 | /** | |
bb8c093b | 3432 | * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
3433 | * |
3434 | * Setup the RX handlers for each of the reply types sent from the uCode | |
3435 | * to the host. | |
3436 | * | |
3437 | * This function chains into the hardware specific files for them to setup | |
3438 | * any hardware specific handlers as well. | |
3439 | */ | |
bb8c093b | 3440 | static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv) |
b481de9c | 3441 | { |
bb8c093b CH |
3442 | priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive; |
3443 | priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta; | |
3444 | priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error; | |
3445 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa; | |
b481de9c | 3446 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
bb8c093b CH |
3447 | iwl3945_rx_spectrum_measure_notif; |
3448 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif; | |
b481de9c | 3449 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
bb8c093b CH |
3450 | iwl3945_rx_pm_debug_statistics_notif; |
3451 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif; | |
b481de9c | 3452 | |
9fbab516 BC |
3453 | /* |
3454 | * The same handler is used for both the REPLY to a discrete | |
3455 | * statistics request from the host as well as for the periodic | |
3456 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 3457 | */ |
bb8c093b CH |
3458 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics; |
3459 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics; | |
b481de9c | 3460 | |
bb8c093b CH |
3461 | priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan; |
3462 | priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif; | |
b481de9c | 3463 | priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] = |
bb8c093b | 3464 | iwl3945_rx_scan_results_notif; |
b481de9c | 3465 | priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] = |
bb8c093b CH |
3466 | iwl3945_rx_scan_complete_notif; |
3467 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif; | |
b481de9c | 3468 | |
9fbab516 | 3469 | /* Set up hardware specific Rx handlers */ |
bb8c093b | 3470 | iwl3945_hw_rx_handler_setup(priv); |
b481de9c ZY |
3471 | } |
3472 | ||
91c066f2 TW |
3473 | /** |
3474 | * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries | |
3475 | * When FW advances 'R' index, all entries between old and new 'R' index | |
3476 | * need to be reclaimed. | |
3477 | */ | |
3478 | static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv, | |
3479 | int txq_id, int index) | |
3480 | { | |
3481 | struct iwl3945_tx_queue *txq = &priv->txq[txq_id]; | |
3482 | struct iwl3945_queue *q = &txq->q; | |
3483 | int nfreed = 0; | |
3484 | ||
3485 | if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) { | |
3486 | IWL_ERROR("Read index for DMA queue txq id (%d), index %d, " | |
3487 | "is out of range [0-%d] %d %d.\n", txq_id, | |
3488 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
3489 | return; | |
3490 | } | |
3491 | ||
3492 | for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index; | |
3493 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
3494 | if (nfreed > 1) { | |
3495 | IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index, | |
3496 | q->write_ptr, q->read_ptr); | |
3497 | queue_work(priv->workqueue, &priv->restart); | |
3498 | break; | |
3499 | } | |
3500 | nfreed++; | |
3501 | } | |
3502 | } | |
3503 | ||
3504 | ||
b481de9c | 3505 | /** |
bb8c093b | 3506 | * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them |
b481de9c ZY |
3507 | * @rxb: Rx buffer to reclaim |
3508 | * | |
3509 | * If an Rx buffer has an async callback associated with it the callback | |
3510 | * will be executed. The attached skb (if present) will only be freed | |
3511 | * if the callback returns 1 | |
3512 | */ | |
bb8c093b CH |
3513 | static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv, |
3514 | struct iwl3945_rx_mem_buffer *rxb) | |
b481de9c | 3515 | { |
bb8c093b | 3516 | struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data; |
b481de9c ZY |
3517 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
3518 | int txq_id = SEQ_TO_QUEUE(sequence); | |
3519 | int index = SEQ_TO_INDEX(sequence); | |
3520 | int huge = sequence & SEQ_HUGE_FRAME; | |
3521 | int cmd_index; | |
bb8c093b | 3522 | struct iwl3945_cmd *cmd; |
b481de9c | 3523 | |
b481de9c ZY |
3524 | BUG_ON(txq_id != IWL_CMD_QUEUE_NUM); |
3525 | ||
3526 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); | |
3527 | cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; | |
3528 | ||
3529 | /* Input error checking is done when commands are added to queue. */ | |
3530 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
3531 | cmd->meta.source->u.skb = rxb->skb; | |
3532 | rxb->skb = NULL; | |
3533 | } else if (cmd->meta.u.callback && | |
3534 | !cmd->meta.u.callback(priv, cmd, rxb->skb)) | |
3535 | rxb->skb = NULL; | |
3536 | ||
91c066f2 | 3537 | iwl3945_cmd_queue_reclaim(priv, txq_id, index); |
b481de9c ZY |
3538 | |
3539 | if (!(cmd->meta.flags & CMD_ASYNC)) { | |
3540 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
3541 | wake_up_interruptible(&priv->wait_command_queue); | |
3542 | } | |
3543 | } | |
3544 | ||
3545 | /************************** RX-FUNCTIONS ****************************/ | |
3546 | /* | |
3547 | * Rx theory of operation | |
3548 | * | |
3549 | * The host allocates 32 DMA target addresses and passes the host address | |
3550 | * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is | |
3551 | * 0 to 31 | |
3552 | * | |
3553 | * Rx Queue Indexes | |
3554 | * The host/firmware share two index registers for managing the Rx buffers. | |
3555 | * | |
3556 | * The READ index maps to the first position that the firmware may be writing | |
3557 | * to -- the driver can read up to (but not including) this position and get | |
3558 | * good data. | |
3559 | * The READ index is managed by the firmware once the card is enabled. | |
3560 | * | |
3561 | * The WRITE index maps to the last position the driver has read from -- the | |
3562 | * position preceding WRITE is the last slot the firmware can place a packet. | |
3563 | * | |
3564 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
3565 | * WRITE = READ. | |
3566 | * | |
9fbab516 | 3567 | * During initialization, the host sets up the READ queue position to the first |
b481de9c ZY |
3568 | * INDEX position, and WRITE to the last (READ - 1 wrapped) |
3569 | * | |
9fbab516 | 3570 | * When the firmware places a packet in a buffer, it will advance the READ index |
b481de9c ZY |
3571 | * and fire the RX interrupt. The driver can then query the READ index and |
3572 | * process as many packets as possible, moving the WRITE index forward as it | |
3573 | * resets the Rx queue buffers with new memory. | |
3574 | * | |
3575 | * The management in the driver is as follows: | |
3576 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
3577 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
01ebd063 | 3578 | * to replenish the iwl->rxq->rx_free. |
bb8c093b | 3579 | * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the |
b481de9c ZY |
3580 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
3581 | * 'processed' and 'read' driver indexes as well) | |
3582 | * + A received packet is processed and handed to the kernel network stack, | |
3583 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
3584 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
3585 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
3586 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
3587 | * were enough free buffers and RX_STALLED is set it is cleared. | |
3588 | * | |
3589 | * | |
3590 | * Driver sequence: | |
3591 | * | |
9fbab516 BC |
3592 | * iwl3945_rx_queue_alloc() Allocates rx_free |
3593 | * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
bb8c093b | 3594 | * iwl3945_rx_queue_restock |
9fbab516 | 3595 | * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx |
b481de9c ZY |
3596 | * queue, updates firmware pointers, and updates |
3597 | * the WRITE index. If insufficient rx_free buffers | |
bb8c093b | 3598 | * are available, schedules iwl3945_rx_replenish |
b481de9c ZY |
3599 | * |
3600 | * -- enable interrupts -- | |
9fbab516 | 3601 | * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the |
b481de9c ZY |
3602 | * READ INDEX, detaching the SKB from the pool. |
3603 | * Moves the packet buffer from queue to rx_used. | |
bb8c093b | 3604 | * Calls iwl3945_rx_queue_restock to refill any empty |
b481de9c ZY |
3605 | * slots. |
3606 | * ... | |
3607 | * | |
3608 | */ | |
3609 | ||
3610 | /** | |
bb8c093b | 3611 | * iwl3945_rx_queue_space - Return number of free slots available in queue. |
b481de9c | 3612 | */ |
bb8c093b | 3613 | static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q) |
b481de9c ZY |
3614 | { |
3615 | int s = q->read - q->write; | |
3616 | if (s <= 0) | |
3617 | s += RX_QUEUE_SIZE; | |
3618 | /* keep some buffer to not confuse full and empty queue */ | |
3619 | s -= 2; | |
3620 | if (s < 0) | |
3621 | s = 0; | |
3622 | return s; | |
3623 | } | |
3624 | ||
3625 | /** | |
bb8c093b | 3626 | * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue |
b481de9c | 3627 | */ |
bb8c093b | 3628 | int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q) |
b481de9c ZY |
3629 | { |
3630 | u32 reg = 0; | |
3631 | int rc = 0; | |
3632 | unsigned long flags; | |
3633 | ||
3634 | spin_lock_irqsave(&q->lock, flags); | |
3635 | ||
3636 | if (q->need_update == 0) | |
3637 | goto exit_unlock; | |
3638 | ||
6440adb5 | 3639 | /* If power-saving is in use, make sure device is awake */ |
b481de9c | 3640 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { |
bb8c093b | 3641 | reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1); |
b481de9c ZY |
3642 | |
3643 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
bb8c093b | 3644 | iwl3945_set_bit(priv, CSR_GP_CNTRL, |
b481de9c ZY |
3645 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
3646 | goto exit_unlock; | |
3647 | } | |
3648 | ||
bb8c093b | 3649 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
3650 | if (rc) |
3651 | goto exit_unlock; | |
3652 | ||
6440adb5 | 3653 | /* Device expects a multiple of 8 */ |
bb8c093b | 3654 | iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, |
b481de9c | 3655 | q->write & ~0x7); |
bb8c093b | 3656 | iwl3945_release_nic_access(priv); |
6440adb5 CB |
3657 | |
3658 | /* Else device is assumed to be awake */ | |
b481de9c | 3659 | } else |
6440adb5 | 3660 | /* Device expects a multiple of 8 */ |
bb8c093b | 3661 | iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7); |
b481de9c ZY |
3662 | |
3663 | ||
3664 | q->need_update = 0; | |
3665 | ||
3666 | exit_unlock: | |
3667 | spin_unlock_irqrestore(&q->lock, flags); | |
3668 | return rc; | |
3669 | } | |
3670 | ||
3671 | /** | |
9fbab516 | 3672 | * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
b481de9c | 3673 | */ |
bb8c093b | 3674 | static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv, |
b481de9c ZY |
3675 | dma_addr_t dma_addr) |
3676 | { | |
3677 | return cpu_to_le32((u32)dma_addr); | |
3678 | } | |
3679 | ||
3680 | /** | |
bb8c093b | 3681 | * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool |
b481de9c | 3682 | * |
9fbab516 | 3683 | * If there are slots in the RX queue that need to be restocked, |
b481de9c | 3684 | * and we have free pre-allocated buffers, fill the ranks as much |
9fbab516 | 3685 | * as we can, pulling from rx_free. |
b481de9c ZY |
3686 | * |
3687 | * This moves the 'write' index forward to catch up with 'processed', and | |
3688 | * also updates the memory address in the firmware to reference the new | |
3689 | * target buffer. | |
3690 | */ | |
bb8c093b | 3691 | static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv) |
b481de9c | 3692 | { |
bb8c093b | 3693 | struct iwl3945_rx_queue *rxq = &priv->rxq; |
b481de9c | 3694 | struct list_head *element; |
bb8c093b | 3695 | struct iwl3945_rx_mem_buffer *rxb; |
b481de9c ZY |
3696 | unsigned long flags; |
3697 | int write, rc; | |
3698 | ||
3699 | spin_lock_irqsave(&rxq->lock, flags); | |
3700 | write = rxq->write & ~0x7; | |
bb8c093b | 3701 | while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
6440adb5 | 3702 | /* Get next free Rx buffer, remove from free list */ |
b481de9c | 3703 | element = rxq->rx_free.next; |
bb8c093b | 3704 | rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list); |
b481de9c | 3705 | list_del(element); |
6440adb5 CB |
3706 | |
3707 | /* Point to Rx buffer via next RBD in circular buffer */ | |
bb8c093b | 3708 | rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr); |
b481de9c ZY |
3709 | rxq->queue[rxq->write] = rxb; |
3710 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
3711 | rxq->free_count--; | |
3712 | } | |
3713 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3714 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
3715 | * refill it */ | |
3716 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
3717 | queue_work(priv->workqueue, &priv->rx_replenish); | |
3718 | ||
3719 | ||
6440adb5 CB |
3720 | /* If we've added more space for the firmware to place data, tell it. |
3721 | * Increment device's write pointer in multiples of 8. */ | |
b481de9c ZY |
3722 | if ((write != (rxq->write & ~0x7)) |
3723 | || (abs(rxq->write - rxq->read) > 7)) { | |
3724 | spin_lock_irqsave(&rxq->lock, flags); | |
3725 | rxq->need_update = 1; | |
3726 | spin_unlock_irqrestore(&rxq->lock, flags); | |
bb8c093b | 3727 | rc = iwl3945_rx_queue_update_write_ptr(priv, rxq); |
b481de9c ZY |
3728 | if (rc) |
3729 | return rc; | |
3730 | } | |
3731 | ||
3732 | return 0; | |
3733 | } | |
3734 | ||
3735 | /** | |
bb8c093b | 3736 | * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free |
b481de9c ZY |
3737 | * |
3738 | * When moving to rx_free an SKB is allocated for the slot. | |
3739 | * | |
bb8c093b | 3740 | * Also restock the Rx queue via iwl3945_rx_queue_restock. |
01ebd063 | 3741 | * This is called as a scheduled work item (except for during initialization) |
b481de9c | 3742 | */ |
5c0eef96 | 3743 | static void iwl3945_rx_allocate(struct iwl3945_priv *priv) |
b481de9c | 3744 | { |
bb8c093b | 3745 | struct iwl3945_rx_queue *rxq = &priv->rxq; |
b481de9c | 3746 | struct list_head *element; |
bb8c093b | 3747 | struct iwl3945_rx_mem_buffer *rxb; |
b481de9c ZY |
3748 | unsigned long flags; |
3749 | spin_lock_irqsave(&rxq->lock, flags); | |
3750 | while (!list_empty(&rxq->rx_used)) { | |
3751 | element = rxq->rx_used.next; | |
bb8c093b | 3752 | rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list); |
6440adb5 CB |
3753 | |
3754 | /* Alloc a new receive buffer */ | |
b481de9c ZY |
3755 | rxb->skb = |
3756 | alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC); | |
3757 | if (!rxb->skb) { | |
3758 | if (net_ratelimit()) | |
3759 | printk(KERN_CRIT DRV_NAME | |
3760 | ": Can not allocate SKB buffers\n"); | |
3761 | /* We don't reschedule replenish work here -- we will | |
3762 | * call the restock method and if it still needs | |
3763 | * more buffers it will schedule replenish */ | |
3764 | break; | |
3765 | } | |
12342c47 ZY |
3766 | |
3767 | /* If radiotap head is required, reserve some headroom here. | |
3768 | * The physical head count is a variable rx_stats->phy_count. | |
3769 | * We reserve 4 bytes here. Plus these extra bytes, the | |
3770 | * headroom of the physical head should be enough for the | |
3771 | * radiotap head that iwl3945 supported. See iwl3945_rt. | |
3772 | */ | |
3773 | skb_reserve(rxb->skb, 4); | |
3774 | ||
b481de9c ZY |
3775 | priv->alloc_rxb_skb++; |
3776 | list_del(element); | |
6440adb5 CB |
3777 | |
3778 | /* Get physical address of RB/SKB */ | |
b481de9c ZY |
3779 | rxb->dma_addr = |
3780 | pci_map_single(priv->pci_dev, rxb->skb->data, | |
3781 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
3782 | list_add_tail(&rxb->list, &rxq->rx_free); | |
3783 | rxq->free_count++; | |
3784 | } | |
3785 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5c0eef96 MA |
3786 | } |
3787 | ||
3788 | /* | |
3789 | * this should be called while priv->lock is locked | |
3790 | */ | |
4fd1f841 | 3791 | static void __iwl3945_rx_replenish(void *data) |
5c0eef96 MA |
3792 | { |
3793 | struct iwl3945_priv *priv = data; | |
3794 | ||
3795 | iwl3945_rx_allocate(priv); | |
3796 | iwl3945_rx_queue_restock(priv); | |
3797 | } | |
3798 | ||
3799 | ||
3800 | void iwl3945_rx_replenish(void *data) | |
3801 | { | |
3802 | struct iwl3945_priv *priv = data; | |
3803 | unsigned long flags; | |
3804 | ||
3805 | iwl3945_rx_allocate(priv); | |
b481de9c ZY |
3806 | |
3807 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 3808 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
3809 | spin_unlock_irqrestore(&priv->lock, flags); |
3810 | } | |
3811 | ||
3812 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. | |
9fbab516 | 3813 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL |
b481de9c ZY |
3814 | * This free routine walks the list of POOL entries and if SKB is set to |
3815 | * non NULL it is unmapped and freed | |
3816 | */ | |
bb8c093b | 3817 | static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq) |
b481de9c ZY |
3818 | { |
3819 | int i; | |
3820 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
3821 | if (rxq->pool[i].skb != NULL) { | |
3822 | pci_unmap_single(priv->pci_dev, | |
3823 | rxq->pool[i].dma_addr, | |
3824 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
3825 | dev_kfree_skb(rxq->pool[i].skb); | |
3826 | } | |
3827 | } | |
3828 | ||
3829 | pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
3830 | rxq->dma_addr); | |
3831 | rxq->bd = NULL; | |
3832 | } | |
3833 | ||
bb8c093b | 3834 | int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv) |
b481de9c | 3835 | { |
bb8c093b | 3836 | struct iwl3945_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
3837 | struct pci_dev *dev = priv->pci_dev; |
3838 | int i; | |
3839 | ||
3840 | spin_lock_init(&rxq->lock); | |
3841 | INIT_LIST_HEAD(&rxq->rx_free); | |
3842 | INIT_LIST_HEAD(&rxq->rx_used); | |
6440adb5 CB |
3843 | |
3844 | /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */ | |
b481de9c ZY |
3845 | rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr); |
3846 | if (!rxq->bd) | |
3847 | return -ENOMEM; | |
6440adb5 | 3848 | |
b481de9c ZY |
3849 | /* Fill the rx_used queue with _all_ of the Rx buffers */ |
3850 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) | |
3851 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
6440adb5 | 3852 | |
b481de9c ZY |
3853 | /* Set us so that we have processed and used all buffers, but have |
3854 | * not restocked the Rx queue with fresh buffers */ | |
3855 | rxq->read = rxq->write = 0; | |
3856 | rxq->free_count = 0; | |
3857 | rxq->need_update = 0; | |
3858 | return 0; | |
3859 | } | |
3860 | ||
bb8c093b | 3861 | void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq) |
b481de9c ZY |
3862 | { |
3863 | unsigned long flags; | |
3864 | int i; | |
3865 | spin_lock_irqsave(&rxq->lock, flags); | |
3866 | INIT_LIST_HEAD(&rxq->rx_free); | |
3867 | INIT_LIST_HEAD(&rxq->rx_used); | |
3868 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
3869 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
3870 | /* In the reset function, these buffers may have been allocated | |
3871 | * to an SKB, so we need to unmap and free potential storage */ | |
3872 | if (rxq->pool[i].skb != NULL) { | |
3873 | pci_unmap_single(priv->pci_dev, | |
3874 | rxq->pool[i].dma_addr, | |
3875 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
3876 | priv->alloc_rxb_skb--; | |
3877 | dev_kfree_skb(rxq->pool[i].skb); | |
3878 | rxq->pool[i].skb = NULL; | |
3879 | } | |
3880 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
3881 | } | |
3882 | ||
3883 | /* Set us so that we have processed and used all buffers, but have | |
3884 | * not restocked the Rx queue with fresh buffers */ | |
3885 | rxq->read = rxq->write = 0; | |
3886 | rxq->free_count = 0; | |
3887 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3888 | } | |
3889 | ||
3890 | /* Convert linear signal-to-noise ratio into dB */ | |
3891 | static u8 ratio2dB[100] = { | |
3892 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
3893 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
3894 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
3895 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
3896 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
3897 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
3898 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
3899 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
3900 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
3901 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
3902 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
3903 | }; | |
3904 | ||
3905 | /* Calculates a relative dB value from a ratio of linear | |
3906 | * (i.e. not dB) signal levels. | |
3907 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
bb8c093b | 3908 | int iwl3945_calc_db_from_ratio(int sig_ratio) |
b481de9c | 3909 | { |
221c80cf AB |
3910 | /* 1000:1 or higher just report as 60 dB */ |
3911 | if (sig_ratio >= 1000) | |
b481de9c ZY |
3912 | return 60; |
3913 | ||
221c80cf | 3914 | /* 100:1 or higher, divide by 10 and use table, |
b481de9c | 3915 | * add 20 dB to make up for divide by 10 */ |
221c80cf | 3916 | if (sig_ratio >= 100) |
b481de9c ZY |
3917 | return (20 + (int)ratio2dB[sig_ratio/10]); |
3918 | ||
3919 | /* We shouldn't see this */ | |
3920 | if (sig_ratio < 1) | |
3921 | return 0; | |
3922 | ||
3923 | /* Use table for ratios 1:1 - 99:1 */ | |
3924 | return (int)ratio2dB[sig_ratio]; | |
3925 | } | |
3926 | ||
3927 | #define PERFECT_RSSI (-20) /* dBm */ | |
3928 | #define WORST_RSSI (-95) /* dBm */ | |
3929 | #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI) | |
3930 | ||
3931 | /* Calculate an indication of rx signal quality (a percentage, not dBm!). | |
3932 | * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info | |
3933 | * about formulas used below. */ | |
bb8c093b | 3934 | int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm) |
b481de9c ZY |
3935 | { |
3936 | int sig_qual; | |
3937 | int degradation = PERFECT_RSSI - rssi_dbm; | |
3938 | ||
3939 | /* If we get a noise measurement, use signal-to-noise ratio (SNR) | |
3940 | * as indicator; formula is (signal dbm - noise dbm). | |
3941 | * SNR at or above 40 is a great signal (100%). | |
3942 | * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator. | |
3943 | * Weakest usable signal is usually 10 - 15 dB SNR. */ | |
3944 | if (noise_dbm) { | |
3945 | if (rssi_dbm - noise_dbm >= 40) | |
3946 | return 100; | |
3947 | else if (rssi_dbm < noise_dbm) | |
3948 | return 0; | |
3949 | sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2; | |
3950 | ||
3951 | /* Else use just the signal level. | |
3952 | * This formula is a least squares fit of data points collected and | |
3953 | * compared with a reference system that had a percentage (%) display | |
3954 | * for signal quality. */ | |
3955 | } else | |
3956 | sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation * | |
3957 | (15 * RSSI_RANGE + 62 * degradation)) / | |
3958 | (RSSI_RANGE * RSSI_RANGE); | |
3959 | ||
3960 | if (sig_qual > 100) | |
3961 | sig_qual = 100; | |
3962 | else if (sig_qual < 1) | |
3963 | sig_qual = 0; | |
3964 | ||
3965 | return sig_qual; | |
3966 | } | |
3967 | ||
3968 | /** | |
9fbab516 | 3969 | * iwl3945_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
3970 | * |
3971 | * Uses the priv->rx_handlers callback function array to invoke | |
3972 | * the appropriate handlers, including command responses, | |
3973 | * frame-received notifications, and other notifications. | |
3974 | */ | |
bb8c093b | 3975 | static void iwl3945_rx_handle(struct iwl3945_priv *priv) |
b481de9c | 3976 | { |
bb8c093b CH |
3977 | struct iwl3945_rx_mem_buffer *rxb; |
3978 | struct iwl3945_rx_packet *pkt; | |
3979 | struct iwl3945_rx_queue *rxq = &priv->rxq; | |
b481de9c ZY |
3980 | u32 r, i; |
3981 | int reclaim; | |
3982 | unsigned long flags; | |
5c0eef96 | 3983 | u8 fill_rx = 0; |
d68ab680 | 3984 | u32 count = 8; |
b481de9c | 3985 | |
6440adb5 CB |
3986 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
3987 | * buffer that the driver may process (last buffer filled by ucode). */ | |
bb8c093b | 3988 | r = iwl3945_hw_get_rx_read(priv); |
b481de9c ZY |
3989 | i = rxq->read; |
3990 | ||
5c0eef96 MA |
3991 | if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2)) |
3992 | fill_rx = 1; | |
b481de9c ZY |
3993 | /* Rx interrupt, but nothing sent from uCode */ |
3994 | if (i == r) | |
3995 | IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i); | |
3996 | ||
3997 | while (i != r) { | |
3998 | rxb = rxq->queue[i]; | |
3999 | ||
9fbab516 | 4000 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
4001 | * then a bug has been introduced in the queue refilling |
4002 | * routines -- catch it here */ | |
4003 | BUG_ON(rxb == NULL); | |
4004 | ||
4005 | rxq->queue[i] = NULL; | |
4006 | ||
4007 | pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr, | |
4008 | IWL_RX_BUF_SIZE, | |
4009 | PCI_DMA_FROMDEVICE); | |
bb8c093b | 4010 | pkt = (struct iwl3945_rx_packet *)rxb->skb->data; |
b481de9c ZY |
4011 | |
4012 | /* Reclaim a command buffer only if this packet is a response | |
4013 | * to a (driver-originated) command. | |
4014 | * If the packet (e.g. Rx frame) originated from uCode, | |
4015 | * there is no command buffer to reclaim. | |
4016 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
4017 | * but apparently a few don't get set; catch them here. */ | |
4018 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
4019 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
4020 | (pkt->hdr.cmd != REPLY_TX); | |
4021 | ||
4022 | /* Based on type of command response or notification, | |
4023 | * handle those that need handling via function in | |
bb8c093b | 4024 | * rx_handlers table. See iwl3945_setup_rx_handlers() */ |
b481de9c ZY |
4025 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
4026 | IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR, | |
4027 | "r = %d, i = %d, %s, 0x%02x\n", r, i, | |
4028 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
4029 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); | |
4030 | } else { | |
4031 | /* No handling needed */ | |
4032 | IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR, | |
4033 | "r %d i %d No handler needed for %s, 0x%02x\n", | |
4034 | r, i, get_cmd_string(pkt->hdr.cmd), | |
4035 | pkt->hdr.cmd); | |
4036 | } | |
4037 | ||
4038 | if (reclaim) { | |
9fbab516 BC |
4039 | /* Invoke any callbacks, transfer the skb to caller, and |
4040 | * fire off the (possibly) blocking iwl3945_send_cmd() | |
b481de9c ZY |
4041 | * as we reclaim the driver command queue */ |
4042 | if (rxb && rxb->skb) | |
bb8c093b | 4043 | iwl3945_tx_cmd_complete(priv, rxb); |
b481de9c ZY |
4044 | else |
4045 | IWL_WARNING("Claim null rxb?\n"); | |
4046 | } | |
4047 | ||
4048 | /* For now we just don't re-use anything. We can tweak this | |
4049 | * later to try and re-use notification packets and SKBs that | |
4050 | * fail to Rx correctly */ | |
4051 | if (rxb->skb != NULL) { | |
4052 | priv->alloc_rxb_skb--; | |
4053 | dev_kfree_skb_any(rxb->skb); | |
4054 | rxb->skb = NULL; | |
4055 | } | |
4056 | ||
4057 | pci_unmap_single(priv->pci_dev, rxb->dma_addr, | |
4058 | IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
4059 | spin_lock_irqsave(&rxq->lock, flags); | |
4060 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
4061 | spin_unlock_irqrestore(&rxq->lock, flags); | |
4062 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
4063 | /* If there are a lot of unused frames, |
4064 | * restock the Rx queue so ucode won't assert. */ | |
4065 | if (fill_rx) { | |
4066 | count++; | |
4067 | if (count >= 8) { | |
4068 | priv->rxq.read = i; | |
4069 | __iwl3945_rx_replenish(priv); | |
4070 | count = 0; | |
4071 | } | |
4072 | } | |
b481de9c ZY |
4073 | } |
4074 | ||
4075 | /* Backtrack one entry */ | |
4076 | priv->rxq.read = i; | |
bb8c093b | 4077 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
4078 | } |
4079 | ||
6440adb5 CB |
4080 | /** |
4081 | * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware | |
4082 | */ | |
bb8c093b CH |
4083 | static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv, |
4084 | struct iwl3945_tx_queue *txq) | |
b481de9c ZY |
4085 | { |
4086 | u32 reg = 0; | |
4087 | int rc = 0; | |
4088 | int txq_id = txq->q.id; | |
4089 | ||
4090 | if (txq->need_update == 0) | |
4091 | return rc; | |
4092 | ||
4093 | /* if we're trying to save power */ | |
4094 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
4095 | /* wake up nic if it's powered down ... | |
4096 | * uCode will wake up, and interrupt us again, so next | |
4097 | * time we'll skip this part. */ | |
bb8c093b | 4098 | reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1); |
b481de9c ZY |
4099 | |
4100 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
4101 | IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg); | |
bb8c093b | 4102 | iwl3945_set_bit(priv, CSR_GP_CNTRL, |
b481de9c ZY |
4103 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
4104 | return rc; | |
4105 | } | |
4106 | ||
4107 | /* restore this queue's parameters in nic hardware. */ | |
bb8c093b | 4108 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
4109 | if (rc) |
4110 | return rc; | |
bb8c093b | 4111 | iwl3945_write_direct32(priv, HBUS_TARG_WRPTR, |
fc4b6853 | 4112 | txq->q.write_ptr | (txq_id << 8)); |
bb8c093b | 4113 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4114 | |
4115 | /* else not in power-save mode, uCode will never sleep when we're | |
4116 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
4117 | } else | |
bb8c093b | 4118 | iwl3945_write32(priv, HBUS_TARG_WRPTR, |
fc4b6853 | 4119 | txq->q.write_ptr | (txq_id << 8)); |
b481de9c ZY |
4120 | |
4121 | txq->need_update = 0; | |
4122 | ||
4123 | return rc; | |
4124 | } | |
4125 | ||
c8b0e6e1 | 4126 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 4127 | static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon) |
b481de9c | 4128 | { |
0795af57 JP |
4129 | DECLARE_MAC_BUF(mac); |
4130 | ||
b481de9c | 4131 | IWL_DEBUG_RADIO("RX CONFIG:\n"); |
bb8c093b | 4132 | iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
b481de9c ZY |
4133 | IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
4134 | IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
4135 | IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n", | |
4136 | le32_to_cpu(rxon->filter_flags)); | |
4137 | IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type); | |
4138 | IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n", | |
4139 | rxon->ofdm_basic_rates); | |
4140 | IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); | |
0795af57 JP |
4141 | IWL_DEBUG_RADIO("u8[6] node_addr: %s\n", |
4142 | print_mac(mac, rxon->node_addr)); | |
4143 | IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n", | |
4144 | print_mac(mac, rxon->bssid_addr)); | |
b481de9c ZY |
4145 | IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); |
4146 | } | |
4147 | #endif | |
4148 | ||
bb8c093b | 4149 | static void iwl3945_enable_interrupts(struct iwl3945_priv *priv) |
b481de9c ZY |
4150 | { |
4151 | IWL_DEBUG_ISR("Enabling interrupts\n"); | |
4152 | set_bit(STATUS_INT_ENABLED, &priv->status); | |
bb8c093b | 4153 | iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK); |
b481de9c ZY |
4154 | } |
4155 | ||
0359facc MA |
4156 | |
4157 | /* call this function to flush any scheduled tasklet */ | |
4158 | static inline void iwl_synchronize_irq(struct iwl3945_priv *priv) | |
4159 | { | |
4160 | /* wait to make sure we flush pedding tasklet*/ | |
4161 | synchronize_irq(priv->pci_dev->irq); | |
4162 | tasklet_kill(&priv->irq_tasklet); | |
4163 | } | |
4164 | ||
4165 | ||
bb8c093b | 4166 | static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv) |
b481de9c ZY |
4167 | { |
4168 | clear_bit(STATUS_INT_ENABLED, &priv->status); | |
4169 | ||
4170 | /* disable interrupts from uCode/NIC to host */ | |
bb8c093b | 4171 | iwl3945_write32(priv, CSR_INT_MASK, 0x00000000); |
b481de9c ZY |
4172 | |
4173 | /* acknowledge/clear/reset any interrupts still pending | |
4174 | * from uCode or flow handler (Rx/Tx DMA) */ | |
bb8c093b CH |
4175 | iwl3945_write32(priv, CSR_INT, 0xffffffff); |
4176 | iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff); | |
b481de9c ZY |
4177 | IWL_DEBUG_ISR("Disabled interrupts\n"); |
4178 | } | |
4179 | ||
4180 | static const char *desc_lookup(int i) | |
4181 | { | |
4182 | switch (i) { | |
4183 | case 1: | |
4184 | return "FAIL"; | |
4185 | case 2: | |
4186 | return "BAD_PARAM"; | |
4187 | case 3: | |
4188 | return "BAD_CHECKSUM"; | |
4189 | case 4: | |
4190 | return "NMI_INTERRUPT"; | |
4191 | case 5: | |
4192 | return "SYSASSERT"; | |
4193 | case 6: | |
4194 | return "FATAL_ERROR"; | |
4195 | } | |
4196 | ||
4197 | return "UNKNOWN"; | |
4198 | } | |
4199 | ||
4200 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
4201 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
4202 | ||
bb8c093b | 4203 | static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv) |
b481de9c ZY |
4204 | { |
4205 | u32 i; | |
4206 | u32 desc, time, count, base, data1; | |
4207 | u32 blink1, blink2, ilink1, ilink2; | |
4208 | int rc; | |
4209 | ||
4210 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
4211 | ||
bb8c093b | 4212 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
b481de9c ZY |
4213 | IWL_ERROR("Not valid error log pointer 0x%08X\n", base); |
4214 | return; | |
4215 | } | |
4216 | ||
bb8c093b | 4217 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
4218 | if (rc) { |
4219 | IWL_WARNING("Can not read from adapter at this time.\n"); | |
4220 | return; | |
4221 | } | |
4222 | ||
bb8c093b | 4223 | count = iwl3945_read_targ_mem(priv, base); |
b481de9c ZY |
4224 | |
4225 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
4226 | IWL_ERROR("Start IWL Error Log Dump:\n"); | |
2acae16e | 4227 | IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count); |
b481de9c ZY |
4228 | } |
4229 | ||
4230 | IWL_ERROR("Desc Time asrtPC blink2 " | |
4231 | "ilink1 nmiPC Line\n"); | |
4232 | for (i = ERROR_START_OFFSET; | |
4233 | i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET; | |
4234 | i += ERROR_ELEM_SIZE) { | |
bb8c093b | 4235 | desc = iwl3945_read_targ_mem(priv, base + i); |
b481de9c | 4236 | time = |
bb8c093b | 4237 | iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32)); |
b481de9c | 4238 | blink1 = |
bb8c093b | 4239 | iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32)); |
b481de9c | 4240 | blink2 = |
bb8c093b | 4241 | iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32)); |
b481de9c | 4242 | ilink1 = |
bb8c093b | 4243 | iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32)); |
b481de9c | 4244 | ilink2 = |
bb8c093b | 4245 | iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32)); |
b481de9c | 4246 | data1 = |
bb8c093b | 4247 | iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32)); |
b481de9c ZY |
4248 | |
4249 | IWL_ERROR | |
4250 | ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n", | |
4251 | desc_lookup(desc), desc, time, blink1, blink2, | |
4252 | ilink1, ilink2, data1); | |
4253 | } | |
4254 | ||
bb8c093b | 4255 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4256 | |
4257 | } | |
4258 | ||
f58177b9 | 4259 | #define EVENT_START_OFFSET (6 * sizeof(u32)) |
b481de9c ZY |
4260 | |
4261 | /** | |
bb8c093b | 4262 | * iwl3945_print_event_log - Dump error event log to syslog |
b481de9c | 4263 | * |
bb8c093b | 4264 | * NOTE: Must be called with iwl3945_grab_nic_access() already obtained! |
b481de9c | 4265 | */ |
bb8c093b | 4266 | static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx, |
b481de9c ZY |
4267 | u32 num_events, u32 mode) |
4268 | { | |
4269 | u32 i; | |
4270 | u32 base; /* SRAM byte address of event log header */ | |
4271 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
4272 | u32 ptr; /* SRAM byte address of log data */ | |
4273 | u32 ev, time, data; /* event log data */ | |
4274 | ||
4275 | if (num_events == 0) | |
4276 | return; | |
4277 | ||
4278 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
4279 | ||
4280 | if (mode == 0) | |
4281 | event_size = 2 * sizeof(u32); | |
4282 | else | |
4283 | event_size = 3 * sizeof(u32); | |
4284 | ||
4285 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
4286 | ||
4287 | /* "time" is actually "data" for mode 0 (no timestamp). | |
4288 | * place event id # at far right for easier visual parsing. */ | |
4289 | for (i = 0; i < num_events; i++) { | |
bb8c093b | 4290 | ev = iwl3945_read_targ_mem(priv, ptr); |
b481de9c | 4291 | ptr += sizeof(u32); |
bb8c093b | 4292 | time = iwl3945_read_targ_mem(priv, ptr); |
b481de9c ZY |
4293 | ptr += sizeof(u32); |
4294 | if (mode == 0) | |
4295 | IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */ | |
4296 | else { | |
bb8c093b | 4297 | data = iwl3945_read_targ_mem(priv, ptr); |
b481de9c ZY |
4298 | ptr += sizeof(u32); |
4299 | IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev); | |
4300 | } | |
4301 | } | |
4302 | } | |
4303 | ||
bb8c093b | 4304 | static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv) |
b481de9c ZY |
4305 | { |
4306 | int rc; | |
4307 | u32 base; /* SRAM byte address of event log header */ | |
4308 | u32 capacity; /* event log capacity in # entries */ | |
4309 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
4310 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
4311 | u32 next_entry; /* index of next entry to be written by uCode */ | |
4312 | u32 size; /* # entries that we'll print */ | |
4313 | ||
4314 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
bb8c093b | 4315 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
b481de9c ZY |
4316 | IWL_ERROR("Invalid event log pointer 0x%08X\n", base); |
4317 | return; | |
4318 | } | |
4319 | ||
bb8c093b | 4320 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
4321 | if (rc) { |
4322 | IWL_WARNING("Can not read from adapter at this time.\n"); | |
4323 | return; | |
4324 | } | |
4325 | ||
4326 | /* event log header */ | |
bb8c093b CH |
4327 | capacity = iwl3945_read_targ_mem(priv, base); |
4328 | mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
4329 | num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
4330 | next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
b481de9c ZY |
4331 | |
4332 | size = num_wraps ? capacity : next_entry; | |
4333 | ||
4334 | /* bail out if nothing in log */ | |
4335 | if (size == 0) { | |
583fab37 | 4336 | IWL_ERROR("Start IWL Event Log Dump: nothing in log\n"); |
bb8c093b | 4337 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4338 | return; |
4339 | } | |
4340 | ||
583fab37 | 4341 | IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n", |
b481de9c ZY |
4342 | size, num_wraps); |
4343 | ||
4344 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
4345 | * i.e the next one that uCode would fill. */ | |
4346 | if (num_wraps) | |
bb8c093b | 4347 | iwl3945_print_event_log(priv, next_entry, |
b481de9c ZY |
4348 | capacity - next_entry, mode); |
4349 | ||
4350 | /* (then/else) start at top of log */ | |
bb8c093b | 4351 | iwl3945_print_event_log(priv, 0, next_entry, mode); |
b481de9c | 4352 | |
bb8c093b | 4353 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4354 | } |
4355 | ||
4356 | /** | |
bb8c093b | 4357 | * iwl3945_irq_handle_error - called for HW or SW error interrupt from card |
b481de9c | 4358 | */ |
bb8c093b | 4359 | static void iwl3945_irq_handle_error(struct iwl3945_priv *priv) |
b481de9c | 4360 | { |
bb8c093b | 4361 | /* Set the FW error flag -- cleared on iwl3945_down */ |
b481de9c ZY |
4362 | set_bit(STATUS_FW_ERROR, &priv->status); |
4363 | ||
4364 | /* Cancel currently queued command. */ | |
4365 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
4366 | ||
c8b0e6e1 | 4367 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
4368 | if (iwl3945_debug_level & IWL_DL_FW_ERRORS) { |
4369 | iwl3945_dump_nic_error_log(priv); | |
4370 | iwl3945_dump_nic_event_log(priv); | |
4371 | iwl3945_print_rx_config_cmd(&priv->staging_rxon); | |
b481de9c ZY |
4372 | } |
4373 | #endif | |
4374 | ||
4375 | wake_up_interruptible(&priv->wait_command_queue); | |
4376 | ||
4377 | /* Keep the restart process from trying to send host | |
4378 | * commands by clearing the INIT status bit */ | |
4379 | clear_bit(STATUS_READY, &priv->status); | |
4380 | ||
4381 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
4382 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS, | |
4383 | "Restarting adapter due to uCode error.\n"); | |
4384 | ||
bb8c093b | 4385 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
4386 | memcpy(&priv->recovery_rxon, &priv->active_rxon, |
4387 | sizeof(priv->recovery_rxon)); | |
4388 | priv->error_recovering = 1; | |
4389 | } | |
4390 | queue_work(priv->workqueue, &priv->restart); | |
4391 | } | |
4392 | } | |
4393 | ||
bb8c093b | 4394 | static void iwl3945_error_recovery(struct iwl3945_priv *priv) |
b481de9c ZY |
4395 | { |
4396 | unsigned long flags; | |
4397 | ||
4398 | memcpy(&priv->staging_rxon, &priv->recovery_rxon, | |
4399 | sizeof(priv->staging_rxon)); | |
4400 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 4401 | iwl3945_commit_rxon(priv); |
b481de9c | 4402 | |
bb8c093b | 4403 | iwl3945_add_station(priv, priv->bssid, 1, 0); |
b481de9c ZY |
4404 | |
4405 | spin_lock_irqsave(&priv->lock, flags); | |
4406 | priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id); | |
4407 | priv->error_recovering = 0; | |
4408 | spin_unlock_irqrestore(&priv->lock, flags); | |
4409 | } | |
4410 | ||
bb8c093b | 4411 | static void iwl3945_irq_tasklet(struct iwl3945_priv *priv) |
b481de9c ZY |
4412 | { |
4413 | u32 inta, handled = 0; | |
4414 | u32 inta_fh; | |
4415 | unsigned long flags; | |
c8b0e6e1 | 4416 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
4417 | u32 inta_mask; |
4418 | #endif | |
4419 | ||
4420 | spin_lock_irqsave(&priv->lock, flags); | |
4421 | ||
4422 | /* Ack/clear/reset pending uCode interrupts. | |
4423 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
4424 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
bb8c093b CH |
4425 | inta = iwl3945_read32(priv, CSR_INT); |
4426 | iwl3945_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
4427 | |
4428 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
4429 | * Any new interrupts that happen after this, either while we're | |
4430 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
bb8c093b CH |
4431 | inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS); |
4432 | iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 4433 | |
c8b0e6e1 | 4434 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 4435 | if (iwl3945_debug_level & IWL_DL_ISR) { |
9fbab516 BC |
4436 | /* just for debug */ |
4437 | inta_mask = iwl3945_read32(priv, CSR_INT_MASK); | |
b481de9c ZY |
4438 | IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
4439 | inta, inta_mask, inta_fh); | |
4440 | } | |
4441 | #endif | |
4442 | ||
4443 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
4444 | * atomic, make sure that inta covers all the interrupts that | |
4445 | * we've discovered, even if FH interrupt came in just after | |
4446 | * reading CSR_INT. */ | |
6f83eaa1 | 4447 | if (inta_fh & CSR39_FH_INT_RX_MASK) |
b481de9c | 4448 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 4449 | if (inta_fh & CSR39_FH_INT_TX_MASK) |
b481de9c ZY |
4450 | inta |= CSR_INT_BIT_FH_TX; |
4451 | ||
4452 | /* Now service all interrupt bits discovered above. */ | |
4453 | if (inta & CSR_INT_BIT_HW_ERR) { | |
4454 | IWL_ERROR("Microcode HW error detected. Restarting.\n"); | |
4455 | ||
4456 | /* Tell the device to stop sending interrupts */ | |
bb8c093b | 4457 | iwl3945_disable_interrupts(priv); |
b481de9c | 4458 | |
bb8c093b | 4459 | iwl3945_irq_handle_error(priv); |
b481de9c ZY |
4460 | |
4461 | handled |= CSR_INT_BIT_HW_ERR; | |
4462 | ||
4463 | spin_unlock_irqrestore(&priv->lock, flags); | |
4464 | ||
4465 | return; | |
4466 | } | |
4467 | ||
c8b0e6e1 | 4468 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 4469 | if (iwl3945_debug_level & (IWL_DL_ISR)) { |
b481de9c | 4470 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
25c03d8e JP |
4471 | if (inta & CSR_INT_BIT_SCD) |
4472 | IWL_DEBUG_ISR("Scheduler finished to transmit " | |
4473 | "the frame/frames.\n"); | |
b481de9c ZY |
4474 | |
4475 | /* Alive notification via Rx interrupt will do the real work */ | |
4476 | if (inta & CSR_INT_BIT_ALIVE) | |
4477 | IWL_DEBUG_ISR("Alive interrupt\n"); | |
4478 | } | |
4479 | #endif | |
4480 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 4481 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c ZY |
4482 | |
4483 | /* HW RF KILL switch toggled (4965 only) */ | |
4484 | if (inta & CSR_INT_BIT_RF_KILL) { | |
4485 | int hw_rf_kill = 0; | |
bb8c093b | 4486 | if (!(iwl3945_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
4487 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
4488 | hw_rf_kill = 1; | |
4489 | ||
4490 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR, | |
4491 | "RF_KILL bit toggled to %s.\n", | |
4492 | hw_rf_kill ? "disable radio":"enable radio"); | |
4493 | ||
4494 | /* Queue restart only if RF_KILL switch was set to "kill" | |
4495 | * when we loaded driver, and is now set to "enable". | |
4496 | * After we're Alive, RF_KILL gets handled by | |
3230455d | 4497 | * iwl3945_rx_card_state_notif() */ |
53e49093 ZY |
4498 | if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) { |
4499 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
b481de9c | 4500 | queue_work(priv->workqueue, &priv->restart); |
53e49093 | 4501 | } |
b481de9c ZY |
4502 | |
4503 | handled |= CSR_INT_BIT_RF_KILL; | |
4504 | } | |
4505 | ||
4506 | /* Chip got too hot and stopped itself (4965 only) */ | |
4507 | if (inta & CSR_INT_BIT_CT_KILL) { | |
4508 | IWL_ERROR("Microcode CT kill error detected.\n"); | |
4509 | handled |= CSR_INT_BIT_CT_KILL; | |
4510 | } | |
4511 | ||
4512 | /* Error detected by uCode */ | |
4513 | if (inta & CSR_INT_BIT_SW_ERR) { | |
4514 | IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n", | |
4515 | inta); | |
bb8c093b | 4516 | iwl3945_irq_handle_error(priv); |
b481de9c ZY |
4517 | handled |= CSR_INT_BIT_SW_ERR; |
4518 | } | |
4519 | ||
4520 | /* uCode wakes up after power-down sleep */ | |
4521 | if (inta & CSR_INT_BIT_WAKEUP) { | |
4522 | IWL_DEBUG_ISR("Wakeup interrupt\n"); | |
bb8c093b CH |
4523 | iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq); |
4524 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]); | |
4525 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]); | |
4526 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]); | |
4527 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]); | |
4528 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]); | |
4529 | iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c ZY |
4530 | |
4531 | handled |= CSR_INT_BIT_WAKEUP; | |
4532 | } | |
4533 | ||
4534 | /* All uCode command responses, including Tx command responses, | |
4535 | * Rx "responses" (frame-received notification), and other | |
4536 | * notifications from uCode come through here*/ | |
4537 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
bb8c093b | 4538 | iwl3945_rx_handle(priv); |
b481de9c ZY |
4539 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
4540 | } | |
4541 | ||
4542 | if (inta & CSR_INT_BIT_FH_TX) { | |
4543 | IWL_DEBUG_ISR("Tx interrupt\n"); | |
4544 | ||
bb8c093b CH |
4545 | iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); |
4546 | if (!iwl3945_grab_nic_access(priv)) { | |
4547 | iwl3945_write_direct32(priv, | |
b481de9c ZY |
4548 | FH_TCSR_CREDIT |
4549 | (ALM_FH_SRVC_CHNL), 0x0); | |
bb8c093b | 4550 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
4551 | } |
4552 | handled |= CSR_INT_BIT_FH_TX; | |
4553 | } | |
4554 | ||
4555 | if (inta & ~handled) | |
4556 | IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
4557 | ||
4558 | if (inta & ~CSR_INI_SET_MASK) { | |
4559 | IWL_WARNING("Disabled INTA bits 0x%08x were pending\n", | |
4560 | inta & ~CSR_INI_SET_MASK); | |
4561 | IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh); | |
4562 | } | |
4563 | ||
4564 | /* Re-enable all interrupts */ | |
0359facc MA |
4565 | /* only Re-enable if disabled by irq */ |
4566 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
4567 | iwl3945_enable_interrupts(priv); | |
b481de9c | 4568 | |
c8b0e6e1 | 4569 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b CH |
4570 | if (iwl3945_debug_level & (IWL_DL_ISR)) { |
4571 | inta = iwl3945_read32(priv, CSR_INT); | |
4572 | inta_mask = iwl3945_read32(priv, CSR_INT_MASK); | |
4573 | inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
4574 | IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
4575 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | |
4576 | } | |
4577 | #endif | |
4578 | spin_unlock_irqrestore(&priv->lock, flags); | |
4579 | } | |
4580 | ||
bb8c093b | 4581 | static irqreturn_t iwl3945_isr(int irq, void *data) |
b481de9c | 4582 | { |
bb8c093b | 4583 | struct iwl3945_priv *priv = data; |
b481de9c ZY |
4584 | u32 inta, inta_mask; |
4585 | u32 inta_fh; | |
4586 | if (!priv) | |
4587 | return IRQ_NONE; | |
4588 | ||
4589 | spin_lock(&priv->lock); | |
4590 | ||
4591 | /* Disable (but don't clear!) interrupts here to avoid | |
4592 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
4593 | * If we have something to service, the tasklet will re-enable ints. | |
4594 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
bb8c093b CH |
4595 | inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */ |
4596 | iwl3945_write32(priv, CSR_INT_MASK, 0x00000000); | |
b481de9c ZY |
4597 | |
4598 | /* Discover which interrupts are active/pending */ | |
bb8c093b CH |
4599 | inta = iwl3945_read32(priv, CSR_INT); |
4600 | inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
4601 | |
4602 | /* Ignore interrupt if there's nothing in NIC to service. | |
4603 | * This may be due to IRQ shared with another device, | |
4604 | * or due to sporadic interrupts thrown from our NIC. */ | |
4605 | if (!inta && !inta_fh) { | |
4606 | IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n"); | |
4607 | goto none; | |
4608 | } | |
4609 | ||
4610 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
4611 | /* Hardware disappeared */ | |
4612 | IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta); | |
cb4da1a3 | 4613 | goto unplugged; |
b481de9c ZY |
4614 | } |
4615 | ||
4616 | IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | |
4617 | inta, inta_mask, inta_fh); | |
4618 | ||
25c03d8e JP |
4619 | inta &= ~CSR_INT_BIT_SCD; |
4620 | ||
bb8c093b | 4621 | /* iwl3945_irq_tasklet() will service interrupts and re-enable them */ |
25c03d8e JP |
4622 | if (likely(inta || inta_fh)) |
4623 | tasklet_schedule(&priv->irq_tasklet); | |
cb4da1a3 | 4624 | unplugged: |
b481de9c ZY |
4625 | spin_unlock(&priv->lock); |
4626 | ||
4627 | return IRQ_HANDLED; | |
4628 | ||
4629 | none: | |
4630 | /* re-enable interrupts here since we don't have anything to service. */ | |
0359facc MA |
4631 | /* only Re-enable if disabled by irq */ |
4632 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
4633 | iwl3945_enable_interrupts(priv); | |
b481de9c ZY |
4634 | spin_unlock(&priv->lock); |
4635 | return IRQ_NONE; | |
4636 | } | |
4637 | ||
4638 | /************************** EEPROM BANDS **************************** | |
4639 | * | |
bb8c093b | 4640 | * The iwl3945_eeprom_band definitions below provide the mapping from the |
b481de9c ZY |
4641 | * EEPROM contents to the specific channel number supported for each |
4642 | * band. | |
4643 | * | |
bb8c093b | 4644 | * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3 |
b481de9c ZY |
4645 | * definition below maps to physical channel 42 in the 5.2GHz spectrum. |
4646 | * The specific geography and calibration information for that channel | |
4647 | * is contained in the eeprom map itself. | |
4648 | * | |
4649 | * During init, we copy the eeprom information and channel map | |
4650 | * information into priv->channel_info_24/52 and priv->channel_map_24/52 | |
4651 | * | |
4652 | * channel_map_24/52 provides the index in the channel_info array for a | |
4653 | * given channel. We have to have two separate maps as there is channel | |
4654 | * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and | |
4655 | * band_2 | |
4656 | * | |
4657 | * A value of 0xff stored in the channel_map indicates that the channel | |
4658 | * is not supported by the hardware at all. | |
4659 | * | |
4660 | * A value of 0xfe in the channel_map indicates that the channel is not | |
4661 | * valid for Tx with the current hardware. This means that | |
4662 | * while the system can tune and receive on a given channel, it may not | |
4663 | * be able to associate or transmit any frames on that | |
4664 | * channel. There is no corresponding channel information for that | |
4665 | * entry. | |
4666 | * | |
4667 | *********************************************************************/ | |
4668 | ||
4669 | /* 2.4 GHz */ | |
bb8c093b | 4670 | static const u8 iwl3945_eeprom_band_1[14] = { |
b481de9c ZY |
4671 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 |
4672 | }; | |
4673 | ||
4674 | /* 5.2 GHz bands */ | |
9fbab516 | 4675 | static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */ |
b481de9c ZY |
4676 | 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 |
4677 | }; | |
4678 | ||
9fbab516 | 4679 | static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */ |
b481de9c ZY |
4680 | 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 |
4681 | }; | |
4682 | ||
bb8c093b | 4683 | static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */ |
b481de9c ZY |
4684 | 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 |
4685 | }; | |
4686 | ||
bb8c093b | 4687 | static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */ |
b481de9c ZY |
4688 | 145, 149, 153, 157, 161, 165 |
4689 | }; | |
4690 | ||
bb8c093b | 4691 | static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band, |
b481de9c | 4692 | int *eeprom_ch_count, |
bb8c093b | 4693 | const struct iwl3945_eeprom_channel |
b481de9c ZY |
4694 | **eeprom_ch_info, |
4695 | const u8 **eeprom_ch_index) | |
4696 | { | |
4697 | switch (band) { | |
4698 | case 1: /* 2.4GHz band */ | |
bb8c093b | 4699 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1); |
b481de9c | 4700 | *eeprom_ch_info = priv->eeprom.band_1_channels; |
bb8c093b | 4701 | *eeprom_ch_index = iwl3945_eeprom_band_1; |
b481de9c | 4702 | break; |
9fbab516 | 4703 | case 2: /* 4.9GHz band */ |
bb8c093b | 4704 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2); |
b481de9c | 4705 | *eeprom_ch_info = priv->eeprom.band_2_channels; |
bb8c093b | 4706 | *eeprom_ch_index = iwl3945_eeprom_band_2; |
b481de9c ZY |
4707 | break; |
4708 | case 3: /* 5.2GHz band */ | |
bb8c093b | 4709 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3); |
b481de9c | 4710 | *eeprom_ch_info = priv->eeprom.band_3_channels; |
bb8c093b | 4711 | *eeprom_ch_index = iwl3945_eeprom_band_3; |
b481de9c | 4712 | break; |
9fbab516 | 4713 | case 4: /* 5.5GHz band */ |
bb8c093b | 4714 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4); |
b481de9c | 4715 | *eeprom_ch_info = priv->eeprom.band_4_channels; |
bb8c093b | 4716 | *eeprom_ch_index = iwl3945_eeprom_band_4; |
b481de9c | 4717 | break; |
9fbab516 | 4718 | case 5: /* 5.7GHz band */ |
bb8c093b | 4719 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5); |
b481de9c | 4720 | *eeprom_ch_info = priv->eeprom.band_5_channels; |
bb8c093b | 4721 | *eeprom_ch_index = iwl3945_eeprom_band_5; |
b481de9c ZY |
4722 | break; |
4723 | default: | |
4724 | BUG(); | |
4725 | return; | |
4726 | } | |
4727 | } | |
4728 | ||
6440adb5 CB |
4729 | /** |
4730 | * iwl3945_get_channel_info - Find driver's private channel info | |
4731 | * | |
4732 | * Based on band and channel number. | |
4733 | */ | |
bb8c093b | 4734 | const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv, |
8318d78a | 4735 | enum ieee80211_band band, u16 channel) |
b481de9c ZY |
4736 | { |
4737 | int i; | |
4738 | ||
8318d78a JB |
4739 | switch (band) { |
4740 | case IEEE80211_BAND_5GHZ: | |
b481de9c ZY |
4741 | for (i = 14; i < priv->channel_count; i++) { |
4742 | if (priv->channel_info[i].channel == channel) | |
4743 | return &priv->channel_info[i]; | |
4744 | } | |
4745 | break; | |
4746 | ||
8318d78a | 4747 | case IEEE80211_BAND_2GHZ: |
b481de9c ZY |
4748 | if (channel >= 1 && channel <= 14) |
4749 | return &priv->channel_info[channel - 1]; | |
4750 | break; | |
8318d78a JB |
4751 | case IEEE80211_NUM_BANDS: |
4752 | WARN_ON(1); | |
b481de9c ZY |
4753 | } |
4754 | ||
4755 | return NULL; | |
4756 | } | |
4757 | ||
4758 | #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \ | |
4759 | ? # x " " : "") | |
4760 | ||
6440adb5 CB |
4761 | /** |
4762 | * iwl3945_init_channel_map - Set up driver's info for all possible channels | |
4763 | */ | |
bb8c093b | 4764 | static int iwl3945_init_channel_map(struct iwl3945_priv *priv) |
b481de9c ZY |
4765 | { |
4766 | int eeprom_ch_count = 0; | |
4767 | const u8 *eeprom_ch_index = NULL; | |
bb8c093b | 4768 | const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL; |
b481de9c | 4769 | int band, ch; |
bb8c093b | 4770 | struct iwl3945_channel_info *ch_info; |
b481de9c ZY |
4771 | |
4772 | if (priv->channel_count) { | |
4773 | IWL_DEBUG_INFO("Channel map already initialized.\n"); | |
4774 | return 0; | |
4775 | } | |
4776 | ||
4777 | if (priv->eeprom.version < 0x2f) { | |
4778 | IWL_WARNING("Unsupported EEPROM version: 0x%04X\n", | |
4779 | priv->eeprom.version); | |
4780 | return -EINVAL; | |
4781 | } | |
4782 | ||
4783 | IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n"); | |
4784 | ||
4785 | priv->channel_count = | |
bb8c093b CH |
4786 | ARRAY_SIZE(iwl3945_eeprom_band_1) + |
4787 | ARRAY_SIZE(iwl3945_eeprom_band_2) + | |
4788 | ARRAY_SIZE(iwl3945_eeprom_band_3) + | |
4789 | ARRAY_SIZE(iwl3945_eeprom_band_4) + | |
4790 | ARRAY_SIZE(iwl3945_eeprom_band_5); | |
b481de9c ZY |
4791 | |
4792 | IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count); | |
4793 | ||
bb8c093b | 4794 | priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) * |
b481de9c ZY |
4795 | priv->channel_count, GFP_KERNEL); |
4796 | if (!priv->channel_info) { | |
4797 | IWL_ERROR("Could not allocate channel_info\n"); | |
4798 | priv->channel_count = 0; | |
4799 | return -ENOMEM; | |
4800 | } | |
4801 | ||
4802 | ch_info = priv->channel_info; | |
4803 | ||
4804 | /* Loop through the 5 EEPROM bands adding them in order to the | |
4805 | * channel map we maintain (that contains additional information than | |
4806 | * what just in the EEPROM) */ | |
4807 | for (band = 1; band <= 5; band++) { | |
4808 | ||
bb8c093b | 4809 | iwl3945_init_band_reference(priv, band, &eeprom_ch_count, |
b481de9c ZY |
4810 | &eeprom_ch_info, &eeprom_ch_index); |
4811 | ||
4812 | /* Loop through each band adding each of the channels */ | |
4813 | for (ch = 0; ch < eeprom_ch_count; ch++) { | |
4814 | ch_info->channel = eeprom_ch_index[ch]; | |
8318d78a JB |
4815 | ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ : |
4816 | IEEE80211_BAND_5GHZ; | |
b481de9c ZY |
4817 | |
4818 | /* permanently store EEPROM's channel regulatory flags | |
4819 | * and max power in channel info database. */ | |
4820 | ch_info->eeprom = eeprom_ch_info[ch]; | |
4821 | ||
4822 | /* Copy the run-time flags so they are there even on | |
4823 | * invalid channels */ | |
4824 | ch_info->flags = eeprom_ch_info[ch].flags; | |
4825 | ||
4826 | if (!(is_channel_valid(ch_info))) { | |
4827 | IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - " | |
4828 | "No traffic\n", | |
4829 | ch_info->channel, | |
4830 | ch_info->flags, | |
4831 | is_channel_a_band(ch_info) ? | |
4832 | "5.2" : "2.4"); | |
4833 | ch_info++; | |
4834 | continue; | |
4835 | } | |
4836 | ||
4837 | /* Initialize regulatory-based run-time data */ | |
4838 | ch_info->max_power_avg = ch_info->curr_txpow = | |
4839 | eeprom_ch_info[ch].max_power_avg; | |
4840 | ch_info->scan_power = eeprom_ch_info[ch].max_power_avg; | |
4841 | ch_info->min_power = 0; | |
4842 | ||
8211ef78 | 4843 | IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x" |
b481de9c ZY |
4844 | " %ddBm): Ad-Hoc %ssupported\n", |
4845 | ch_info->channel, | |
4846 | is_channel_a_band(ch_info) ? | |
4847 | "5.2" : "2.4", | |
8211ef78 | 4848 | CHECK_AND_PRINT(VALID), |
b481de9c ZY |
4849 | CHECK_AND_PRINT(IBSS), |
4850 | CHECK_AND_PRINT(ACTIVE), | |
4851 | CHECK_AND_PRINT(RADAR), | |
4852 | CHECK_AND_PRINT(WIDE), | |
4853 | CHECK_AND_PRINT(NARROW), | |
4854 | CHECK_AND_PRINT(DFS), | |
4855 | eeprom_ch_info[ch].flags, | |
4856 | eeprom_ch_info[ch].max_power_avg, | |
4857 | ((eeprom_ch_info[ch]. | |
4858 | flags & EEPROM_CHANNEL_IBSS) | |
4859 | && !(eeprom_ch_info[ch]. | |
4860 | flags & EEPROM_CHANNEL_RADAR)) | |
4861 | ? "" : "not "); | |
4862 | ||
4863 | /* Set the user_txpower_limit to the highest power | |
4864 | * supported by any channel */ | |
4865 | if (eeprom_ch_info[ch].max_power_avg > | |
4866 | priv->user_txpower_limit) | |
4867 | priv->user_txpower_limit = | |
4868 | eeprom_ch_info[ch].max_power_avg; | |
4869 | ||
4870 | ch_info++; | |
4871 | } | |
4872 | } | |
4873 | ||
6440adb5 | 4874 | /* Set up txpower settings in driver for all channels */ |
b481de9c ZY |
4875 | if (iwl3945_txpower_set_from_eeprom(priv)) |
4876 | return -EIO; | |
4877 | ||
4878 | return 0; | |
4879 | } | |
4880 | ||
849e0dce RC |
4881 | /* |
4882 | * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map | |
4883 | */ | |
4884 | static void iwl3945_free_channel_map(struct iwl3945_priv *priv) | |
4885 | { | |
4886 | kfree(priv->channel_info); | |
4887 | priv->channel_count = 0; | |
4888 | } | |
4889 | ||
b481de9c ZY |
4890 | /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after |
4891 | * sending probe req. This should be set long enough to hear probe responses | |
4892 | * from more than one AP. */ | |
4893 | #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */ | |
4894 | #define IWL_ACTIVE_DWELL_TIME_52 (10) | |
4895 | ||
4896 | /* For faster active scanning, scan will move to the next channel if fewer than | |
4897 | * PLCP_QUIET_THRESH packets are heard on this channel within | |
4898 | * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell | |
4899 | * time if it's a quiet channel (nothing responded to our probe, and there's | |
4900 | * no other traffic). | |
4901 | * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */ | |
4902 | #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */ | |
4903 | #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */ | |
4904 | ||
4905 | /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. | |
4906 | * Must be set longer than active dwell time. | |
4907 | * For the most reliable scan, set > AP beacon interval (typically 100msec). */ | |
4908 | #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */ | |
4909 | #define IWL_PASSIVE_DWELL_TIME_52 (10) | |
4910 | #define IWL_PASSIVE_DWELL_BASE (100) | |
4911 | #define IWL_CHANNEL_TUNE_TIME 5 | |
4912 | ||
8318d78a JB |
4913 | static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv, |
4914 | enum ieee80211_band band) | |
b481de9c | 4915 | { |
8318d78a | 4916 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
4917 | return IWL_ACTIVE_DWELL_TIME_52; |
4918 | else | |
4919 | return IWL_ACTIVE_DWELL_TIME_24; | |
4920 | } | |
4921 | ||
8318d78a JB |
4922 | static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv, |
4923 | enum ieee80211_band band) | |
b481de9c | 4924 | { |
8318d78a JB |
4925 | u16 active = iwl3945_get_active_dwell_time(priv, band); |
4926 | u16 passive = (band == IEEE80211_BAND_2GHZ) ? | |
b481de9c ZY |
4927 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 : |
4928 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52; | |
4929 | ||
bb8c093b | 4930 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
4931 | /* If we're associated, we clamp the maximum passive |
4932 | * dwell time to be 98% of the beacon interval (minus | |
4933 | * 2 * channel tune time) */ | |
4934 | passive = priv->beacon_int; | |
4935 | if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive) | |
4936 | passive = IWL_PASSIVE_DWELL_BASE; | |
4937 | passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2; | |
4938 | } | |
4939 | ||
4940 | if (passive <= active) | |
4941 | passive = active + 1; | |
4942 | ||
4943 | return passive; | |
4944 | } | |
4945 | ||
8318d78a JB |
4946 | static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv, |
4947 | enum ieee80211_band band, | |
b481de9c | 4948 | u8 is_active, u8 direct_mask, |
bb8c093b | 4949 | struct iwl3945_scan_channel *scan_ch) |
b481de9c ZY |
4950 | { |
4951 | const struct ieee80211_channel *channels = NULL; | |
8318d78a | 4952 | const struct ieee80211_supported_band *sband; |
bb8c093b | 4953 | const struct iwl3945_channel_info *ch_info; |
b481de9c ZY |
4954 | u16 passive_dwell = 0; |
4955 | u16 active_dwell = 0; | |
4956 | int added, i; | |
4957 | ||
8318d78a JB |
4958 | sband = iwl3945_get_band(priv, band); |
4959 | if (!sband) | |
b481de9c ZY |
4960 | return 0; |
4961 | ||
8318d78a | 4962 | channels = sband->channels; |
b481de9c | 4963 | |
8318d78a JB |
4964 | active_dwell = iwl3945_get_active_dwell_time(priv, band); |
4965 | passive_dwell = iwl3945_get_passive_dwell_time(priv, band); | |
b481de9c | 4966 | |
8318d78a | 4967 | for (i = 0, added = 0; i < sband->n_channels; i++) { |
182e2e66 JB |
4968 | if (channels[i].flags & IEEE80211_CHAN_DISABLED) |
4969 | continue; | |
4970 | ||
8318d78a | 4971 | if (channels[i].hw_value == |
b481de9c | 4972 | le16_to_cpu(priv->active_rxon.channel)) { |
bb8c093b | 4973 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
4974 | IWL_DEBUG_SCAN |
4975 | ("Skipping current channel %d\n", | |
4976 | le16_to_cpu(priv->active_rxon.channel)); | |
4977 | continue; | |
4978 | } | |
4979 | } else if (priv->only_active_channel) | |
4980 | continue; | |
4981 | ||
8318d78a | 4982 | scan_ch->channel = channels[i].hw_value; |
b481de9c | 4983 | |
8318d78a | 4984 | ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel); |
b481de9c ZY |
4985 | if (!is_channel_valid(ch_info)) { |
4986 | IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n", | |
4987 | scan_ch->channel); | |
4988 | continue; | |
4989 | } | |
4990 | ||
4991 | if (!is_active || is_channel_passive(ch_info) || | |
8318d78a | 4992 | (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) |
b481de9c ZY |
4993 | scan_ch->type = 0; /* passive */ |
4994 | else | |
4995 | scan_ch->type = 1; /* active */ | |
4996 | ||
4997 | if (scan_ch->type & 1) | |
4998 | scan_ch->type |= (direct_mask << 1); | |
4999 | ||
5000 | if (is_channel_narrow(ch_info)) | |
5001 | scan_ch->type |= (1 << 7); | |
5002 | ||
5003 | scan_ch->active_dwell = cpu_to_le16(active_dwell); | |
5004 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
5005 | ||
9fbab516 | 5006 | /* Set txpower levels to defaults */ |
b481de9c ZY |
5007 | scan_ch->tpc.dsp_atten = 110; |
5008 | /* scan_pwr_info->tpc.dsp_atten; */ | |
5009 | ||
5010 | /*scan_pwr_info->tpc.tx_gain; */ | |
8318d78a | 5011 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
5012 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; |
5013 | else { | |
5014 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
5015 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
9fbab516 | 5016 | * power level: |
8a1b0245 | 5017 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; |
b481de9c ZY |
5018 | */ |
5019 | } | |
5020 | ||
5021 | IWL_DEBUG_SCAN("Scanning %d [%s %d]\n", | |
5022 | scan_ch->channel, | |
5023 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
5024 | (scan_ch->type & 1) ? | |
5025 | active_dwell : passive_dwell); | |
5026 | ||
5027 | scan_ch++; | |
5028 | added++; | |
5029 | } | |
5030 | ||
5031 | IWL_DEBUG_SCAN("total channels to scan %d \n", added); | |
5032 | return added; | |
5033 | } | |
5034 | ||
bb8c093b | 5035 | static void iwl3945_init_hw_rates(struct iwl3945_priv *priv, |
b481de9c ZY |
5036 | struct ieee80211_rate *rates) |
5037 | { | |
5038 | int i; | |
5039 | ||
5040 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
8318d78a JB |
5041 | rates[i].bitrate = iwl3945_rates[i].ieee * 5; |
5042 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
5043 | rates[i].hw_value_short = i; | |
5044 | rates[i].flags = 0; | |
5045 | if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { | |
b481de9c | 5046 | /* |
8318d78a | 5047 | * If CCK != 1M then set short preamble rate flag. |
b481de9c | 5048 | */ |
bb8c093b | 5049 | rates[i].flags |= (iwl3945_rates[i].plcp == 10) ? |
8318d78a | 5050 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
b481de9c | 5051 | } |
b481de9c ZY |
5052 | } |
5053 | } | |
5054 | ||
5055 | /** | |
bb8c093b | 5056 | * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom |
b481de9c | 5057 | */ |
bb8c093b | 5058 | static int iwl3945_init_geos(struct iwl3945_priv *priv) |
b481de9c | 5059 | { |
bb8c093b | 5060 | struct iwl3945_channel_info *ch; |
8211ef78 | 5061 | struct ieee80211_supported_band *sband; |
b481de9c ZY |
5062 | struct ieee80211_channel *channels; |
5063 | struct ieee80211_channel *geo_ch; | |
5064 | struct ieee80211_rate *rates; | |
5065 | int i = 0; | |
b481de9c | 5066 | |
8318d78a JB |
5067 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || |
5068 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
b481de9c ZY |
5069 | IWL_DEBUG_INFO("Geography modes already initialized.\n"); |
5070 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
5071 | return 0; | |
5072 | } | |
5073 | ||
b481de9c ZY |
5074 | channels = kzalloc(sizeof(struct ieee80211_channel) * |
5075 | priv->channel_count, GFP_KERNEL); | |
8318d78a | 5076 | if (!channels) |
b481de9c | 5077 | return -ENOMEM; |
b481de9c | 5078 | |
8211ef78 | 5079 | rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)), |
b481de9c ZY |
5080 | GFP_KERNEL); |
5081 | if (!rates) { | |
b481de9c ZY |
5082 | kfree(channels); |
5083 | return -ENOMEM; | |
5084 | } | |
5085 | ||
b481de9c | 5086 | /* 5.2GHz channels start after the 2.4GHz channels */ |
8211ef78 TW |
5087 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
5088 | sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)]; | |
5089 | /* just OFDM */ | |
5090 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
5091 | sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE; | |
5092 | ||
5093 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
5094 | sband->channels = channels; | |
5095 | /* OFDM & CCK */ | |
5096 | sband->bitrates = rates; | |
5097 | sband->n_bitrates = IWL_RATE_COUNT; | |
b481de9c ZY |
5098 | |
5099 | priv->ieee_channels = channels; | |
5100 | priv->ieee_rates = rates; | |
5101 | ||
bb8c093b | 5102 | iwl3945_init_hw_rates(priv, rates); |
b481de9c | 5103 | |
8211ef78 | 5104 | for (i = 0; i < priv->channel_count; i++) { |
b481de9c ZY |
5105 | ch = &priv->channel_info[i]; |
5106 | ||
8211ef78 TW |
5107 | /* FIXME: might be removed if scan is OK*/ |
5108 | if (!is_channel_valid(ch)) | |
b481de9c | 5109 | continue; |
b481de9c ZY |
5110 | |
5111 | if (is_channel_a_band(ch)) | |
8211ef78 | 5112 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
8318d78a | 5113 | else |
8211ef78 | 5114 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; |
b481de9c | 5115 | |
8211ef78 TW |
5116 | geo_ch = &sband->channels[sband->n_channels++]; |
5117 | ||
5118 | geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel); | |
8318d78a JB |
5119 | geo_ch->max_power = ch->max_power_avg; |
5120 | geo_ch->max_antenna_gain = 0xff; | |
7b72304d | 5121 | geo_ch->hw_value = ch->channel; |
b481de9c ZY |
5122 | |
5123 | if (is_channel_valid(ch)) { | |
8318d78a JB |
5124 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) |
5125 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
b481de9c | 5126 | |
8318d78a JB |
5127 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) |
5128 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
b481de9c ZY |
5129 | |
5130 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
8318d78a | 5131 | geo_ch->flags |= IEEE80211_CHAN_RADAR; |
b481de9c ZY |
5132 | |
5133 | if (ch->max_power_avg > priv->max_channel_txpower_limit) | |
5134 | priv->max_channel_txpower_limit = | |
5135 | ch->max_power_avg; | |
8211ef78 | 5136 | } else { |
8318d78a | 5137 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; |
8211ef78 TW |
5138 | } |
5139 | ||
5140 | /* Save flags for reg domain usage */ | |
5141 | geo_ch->orig_flags = geo_ch->flags; | |
5142 | ||
5143 | IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n", | |
5144 | ch->channel, geo_ch->center_freq, | |
5145 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
5146 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
5147 | "restricted" : "valid", | |
5148 | geo_ch->flags); | |
b481de9c ZY |
5149 | } |
5150 | ||
82b9a121 TW |
5151 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && |
5152 | priv->cfg->sku & IWL_SKU_A) { | |
b481de9c ZY |
5153 | printk(KERN_INFO DRV_NAME |
5154 | ": Incorrectly detected BG card as ABG. Please send " | |
5155 | "your PCI ID 0x%04X:0x%04X to maintainer.\n", | |
5156 | priv->pci_dev->device, priv->pci_dev->subsystem_device); | |
82b9a121 | 5157 | priv->cfg->sku &= ~IWL_SKU_A; |
b481de9c ZY |
5158 | } |
5159 | ||
5160 | printk(KERN_INFO DRV_NAME | |
5161 | ": Tunable channels: %d 802.11bg, %d 802.11a channels\n", | |
8318d78a JB |
5162 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
5163 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
b481de9c | 5164 | |
e0e0a67e JL |
5165 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
5166 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
5167 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
5168 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
5169 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
5170 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
b481de9c | 5171 | |
b481de9c ZY |
5172 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
5173 | ||
5174 | return 0; | |
5175 | } | |
5176 | ||
849e0dce RC |
5177 | /* |
5178 | * iwl3945_free_geos - undo allocations in iwl3945_init_geos | |
5179 | */ | |
5180 | static void iwl3945_free_geos(struct iwl3945_priv *priv) | |
5181 | { | |
849e0dce RC |
5182 | kfree(priv->ieee_channels); |
5183 | kfree(priv->ieee_rates); | |
5184 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
5185 | } | |
5186 | ||
b481de9c ZY |
5187 | /****************************************************************************** |
5188 | * | |
5189 | * uCode download functions | |
5190 | * | |
5191 | ******************************************************************************/ | |
5192 | ||
bb8c093b | 5193 | static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv) |
b481de9c | 5194 | { |
98c92211 TW |
5195 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
5196 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
5197 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
5198 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
5199 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
5200 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
5201 | } |
5202 | ||
5203 | /** | |
bb8c093b | 5204 | * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host, |
b481de9c ZY |
5205 | * looking at all data. |
5206 | */ | |
bb8c093b | 5207 | static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len) |
b481de9c ZY |
5208 | { |
5209 | u32 val; | |
5210 | u32 save_len = len; | |
5211 | int rc = 0; | |
5212 | u32 errcnt; | |
5213 | ||
5214 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
5215 | ||
bb8c093b | 5216 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5217 | if (rc) |
5218 | return rc; | |
5219 | ||
bb8c093b | 5220 | iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND); |
b481de9c ZY |
5221 | |
5222 | errcnt = 0; | |
5223 | for (; len > 0; len -= sizeof(u32), image++) { | |
5224 | /* read data comes through single port, auto-incr addr */ | |
5225 | /* NOTE: Use the debugless read so we don't flood kernel log | |
5226 | * if IWL_DL_IO is set */ | |
bb8c093b | 5227 | val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
5228 | if (val != le32_to_cpu(*image)) { |
5229 | IWL_ERROR("uCode INST section is invalid at " | |
5230 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
5231 | save_len - len, val, le32_to_cpu(*image)); | |
5232 | rc = -EIO; | |
5233 | errcnt++; | |
5234 | if (errcnt >= 20) | |
5235 | break; | |
5236 | } | |
5237 | } | |
5238 | ||
bb8c093b | 5239 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5240 | |
5241 | if (!errcnt) | |
bc434dd2 | 5242 | IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n"); |
b481de9c ZY |
5243 | |
5244 | return rc; | |
5245 | } | |
5246 | ||
5247 | ||
5248 | /** | |
bb8c093b | 5249 | * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host, |
b481de9c ZY |
5250 | * using sample data 100 bytes apart. If these sample points are good, |
5251 | * it's a pretty good bet that everything between them is good, too. | |
5252 | */ | |
bb8c093b | 5253 | static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
5254 | { |
5255 | u32 val; | |
5256 | int rc = 0; | |
5257 | u32 errcnt = 0; | |
5258 | u32 i; | |
5259 | ||
5260 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
5261 | ||
bb8c093b | 5262 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5263 | if (rc) |
5264 | return rc; | |
5265 | ||
5266 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
5267 | /* read data comes through single port, auto-incr addr */ | |
5268 | /* NOTE: Use the debugless read so we don't flood kernel log | |
5269 | * if IWL_DL_IO is set */ | |
bb8c093b | 5270 | iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
b481de9c | 5271 | i + RTC_INST_LOWER_BOUND); |
bb8c093b | 5272 | val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
5273 | if (val != le32_to_cpu(*image)) { |
5274 | #if 0 /* Enable this if you want to see details */ | |
5275 | IWL_ERROR("uCode INST section is invalid at " | |
5276 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
5277 | i, val, *image); | |
5278 | #endif | |
5279 | rc = -EIO; | |
5280 | errcnt++; | |
5281 | if (errcnt >= 3) | |
5282 | break; | |
5283 | } | |
5284 | } | |
5285 | ||
bb8c093b | 5286 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5287 | |
5288 | return rc; | |
5289 | } | |
5290 | ||
5291 | ||
5292 | /** | |
bb8c093b | 5293 | * iwl3945_verify_ucode - determine which instruction image is in SRAM, |
b481de9c ZY |
5294 | * and verify its contents |
5295 | */ | |
bb8c093b | 5296 | static int iwl3945_verify_ucode(struct iwl3945_priv *priv) |
b481de9c ZY |
5297 | { |
5298 | __le32 *image; | |
5299 | u32 len; | |
5300 | int rc = 0; | |
5301 | ||
5302 | /* Try bootstrap */ | |
5303 | image = (__le32 *)priv->ucode_boot.v_addr; | |
5304 | len = priv->ucode_boot.len; | |
bb8c093b | 5305 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5306 | if (rc == 0) { |
5307 | IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n"); | |
5308 | return 0; | |
5309 | } | |
5310 | ||
5311 | /* Try initialize */ | |
5312 | image = (__le32 *)priv->ucode_init.v_addr; | |
5313 | len = priv->ucode_init.len; | |
bb8c093b | 5314 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5315 | if (rc == 0) { |
5316 | IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n"); | |
5317 | return 0; | |
5318 | } | |
5319 | ||
5320 | /* Try runtime/protocol */ | |
5321 | image = (__le32 *)priv->ucode_code.v_addr; | |
5322 | len = priv->ucode_code.len; | |
bb8c093b | 5323 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
5324 | if (rc == 0) { |
5325 | IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n"); | |
5326 | return 0; | |
5327 | } | |
5328 | ||
5329 | IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); | |
5330 | ||
9fbab516 BC |
5331 | /* Since nothing seems to match, show first several data entries in |
5332 | * instruction SRAM, so maybe visual inspection will give a clue. | |
5333 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
b481de9c ZY |
5334 | image = (__le32 *)priv->ucode_boot.v_addr; |
5335 | len = priv->ucode_boot.len; | |
bb8c093b | 5336 | rc = iwl3945_verify_inst_full(priv, image, len); |
b481de9c ZY |
5337 | |
5338 | return rc; | |
5339 | } | |
5340 | ||
5341 | ||
5342 | /* check contents of special bootstrap uCode SRAM */ | |
bb8c093b | 5343 | static int iwl3945_verify_bsm(struct iwl3945_priv *priv) |
b481de9c ZY |
5344 | { |
5345 | __le32 *image = priv->ucode_boot.v_addr; | |
5346 | u32 len = priv->ucode_boot.len; | |
5347 | u32 reg; | |
5348 | u32 val; | |
5349 | ||
5350 | IWL_DEBUG_INFO("Begin verify bsm\n"); | |
5351 | ||
5352 | /* verify BSM SRAM contents */ | |
bb8c093b | 5353 | val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG); |
b481de9c ZY |
5354 | for (reg = BSM_SRAM_LOWER_BOUND; |
5355 | reg < BSM_SRAM_LOWER_BOUND + len; | |
5356 | reg += sizeof(u32), image ++) { | |
bb8c093b | 5357 | val = iwl3945_read_prph(priv, reg); |
b481de9c ZY |
5358 | if (val != le32_to_cpu(*image)) { |
5359 | IWL_ERROR("BSM uCode verification failed at " | |
5360 | "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", | |
5361 | BSM_SRAM_LOWER_BOUND, | |
5362 | reg - BSM_SRAM_LOWER_BOUND, len, | |
5363 | val, le32_to_cpu(*image)); | |
5364 | return -EIO; | |
5365 | } | |
5366 | } | |
5367 | ||
5368 | IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n"); | |
5369 | ||
5370 | return 0; | |
5371 | } | |
5372 | ||
5373 | /** | |
bb8c093b | 5374 | * iwl3945_load_bsm - Load bootstrap instructions |
b481de9c ZY |
5375 | * |
5376 | * BSM operation: | |
5377 | * | |
5378 | * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program | |
5379 | * in special SRAM that does not power down during RFKILL. When powering back | |
5380 | * up after power-saving sleeps (or during initial uCode load), the BSM loads | |
5381 | * the bootstrap program into the on-board processor, and starts it. | |
5382 | * | |
5383 | * The bootstrap program loads (via DMA) instructions and data for a new | |
5384 | * program from host DRAM locations indicated by the host driver in the | |
5385 | * BSM_DRAM_* registers. Once the new program is loaded, it starts | |
5386 | * automatically. | |
5387 | * | |
5388 | * When initializing the NIC, the host driver points the BSM to the | |
5389 | * "initialize" uCode image. This uCode sets up some internal data, then | |
5390 | * notifies host via "initialize alive" that it is complete. | |
5391 | * | |
5392 | * The host then replaces the BSM_DRAM_* pointer values to point to the | |
5393 | * normal runtime uCode instructions and a backup uCode data cache buffer | |
5394 | * (filled initially with starting data values for the on-board processor), | |
5395 | * then triggers the "initialize" uCode to load and launch the runtime uCode, | |
5396 | * which begins normal operation. | |
5397 | * | |
5398 | * When doing a power-save shutdown, runtime uCode saves data SRAM into | |
5399 | * the backup data cache in DRAM before SRAM is powered down. | |
5400 | * | |
5401 | * When powering back up, the BSM loads the bootstrap program. This reloads | |
5402 | * the runtime uCode instructions and the backup data cache into SRAM, | |
5403 | * and re-launches the runtime uCode from where it left off. | |
5404 | */ | |
bb8c093b | 5405 | static int iwl3945_load_bsm(struct iwl3945_priv *priv) |
b481de9c ZY |
5406 | { |
5407 | __le32 *image = priv->ucode_boot.v_addr; | |
5408 | u32 len = priv->ucode_boot.len; | |
5409 | dma_addr_t pinst; | |
5410 | dma_addr_t pdata; | |
5411 | u32 inst_len; | |
5412 | u32 data_len; | |
5413 | int rc; | |
5414 | int i; | |
5415 | u32 done; | |
5416 | u32 reg_offset; | |
5417 | ||
5418 | IWL_DEBUG_INFO("Begin load bsm\n"); | |
5419 | ||
5420 | /* make sure bootstrap program is no larger than BSM's SRAM size */ | |
5421 | if (len > IWL_MAX_BSM_SIZE) | |
5422 | return -EINVAL; | |
5423 | ||
5424 | /* Tell bootstrap uCode where to find the "Initialize" uCode | |
9fbab516 | 5425 | * in host DRAM ... host DRAM physical address bits 31:0 for 3945. |
bb8c093b | 5426 | * NOTE: iwl3945_initialize_alive_start() will replace these values, |
b481de9c ZY |
5427 | * after the "initialize" uCode has run, to point to |
5428 | * runtime/protocol instructions and backup data cache. */ | |
5429 | pinst = priv->ucode_init.p_addr; | |
5430 | pdata = priv->ucode_init_data.p_addr; | |
5431 | inst_len = priv->ucode_init.len; | |
5432 | data_len = priv->ucode_init_data.len; | |
5433 | ||
bb8c093b | 5434 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5435 | if (rc) |
5436 | return rc; | |
5437 | ||
bb8c093b CH |
5438 | iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
5439 | iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
5440 | iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); | |
5441 | iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); | |
b481de9c ZY |
5442 | |
5443 | /* Fill BSM memory with bootstrap instructions */ | |
5444 | for (reg_offset = BSM_SRAM_LOWER_BOUND; | |
5445 | reg_offset < BSM_SRAM_LOWER_BOUND + len; | |
5446 | reg_offset += sizeof(u32), image++) | |
bb8c093b | 5447 | _iwl3945_write_prph(priv, reg_offset, |
b481de9c ZY |
5448 | le32_to_cpu(*image)); |
5449 | ||
bb8c093b | 5450 | rc = iwl3945_verify_bsm(priv); |
b481de9c | 5451 | if (rc) { |
bb8c093b | 5452 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5453 | return rc; |
5454 | } | |
5455 | ||
5456 | /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ | |
bb8c093b CH |
5457 | iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0); |
5458 | iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG, | |
b481de9c | 5459 | RTC_INST_LOWER_BOUND); |
bb8c093b | 5460 | iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); |
b481de9c ZY |
5461 | |
5462 | /* Load bootstrap code into instruction SRAM now, | |
5463 | * to prepare to load "initialize" uCode */ | |
bb8c093b | 5464 | iwl3945_write_prph(priv, BSM_WR_CTRL_REG, |
b481de9c ZY |
5465 | BSM_WR_CTRL_REG_BIT_START); |
5466 | ||
5467 | /* Wait for load of bootstrap uCode to finish */ | |
5468 | for (i = 0; i < 100; i++) { | |
bb8c093b | 5469 | done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG); |
b481de9c ZY |
5470 | if (!(done & BSM_WR_CTRL_REG_BIT_START)) |
5471 | break; | |
5472 | udelay(10); | |
5473 | } | |
5474 | if (i < 100) | |
5475 | IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i); | |
5476 | else { | |
5477 | IWL_ERROR("BSM write did not complete!\n"); | |
5478 | return -EIO; | |
5479 | } | |
5480 | ||
5481 | /* Enable future boot loads whenever power management unit triggers it | |
5482 | * (e.g. when powering back up after power-save shutdown) */ | |
bb8c093b | 5483 | iwl3945_write_prph(priv, BSM_WR_CTRL_REG, |
b481de9c ZY |
5484 | BSM_WR_CTRL_REG_BIT_START_EN); |
5485 | ||
bb8c093b | 5486 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5487 | |
5488 | return 0; | |
5489 | } | |
5490 | ||
bb8c093b | 5491 | static void iwl3945_nic_start(struct iwl3945_priv *priv) |
b481de9c ZY |
5492 | { |
5493 | /* Remove all resets to allow NIC to operate */ | |
bb8c093b | 5494 | iwl3945_write32(priv, CSR_RESET, 0); |
b481de9c ZY |
5495 | } |
5496 | ||
5497 | /** | |
bb8c093b | 5498 | * iwl3945_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
5499 | * |
5500 | * Copy into buffers for card to fetch via bus-mastering | |
5501 | */ | |
bb8c093b | 5502 | static int iwl3945_read_ucode(struct iwl3945_priv *priv) |
b481de9c | 5503 | { |
bb8c093b | 5504 | struct iwl3945_ucode *ucode; |
90e759d1 | 5505 | int ret = 0; |
b481de9c ZY |
5506 | const struct firmware *ucode_raw; |
5507 | /* firmware file name contains uCode/driver compatibility version */ | |
4bf775cd | 5508 | const char *name = priv->cfg->fw_name; |
b481de9c ZY |
5509 | u8 *src; |
5510 | size_t len; | |
5511 | u32 ver, inst_size, data_size, init_size, init_data_size, boot_size; | |
5512 | ||
5513 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
5514 | * request_firmware() is synchronous, file is in memory on return. */ | |
90e759d1 TW |
5515 | ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev); |
5516 | if (ret < 0) { | |
5517 | IWL_ERROR("%s firmware file req failed: Reason %d\n", | |
5518 | name, ret); | |
b481de9c ZY |
5519 | goto error; |
5520 | } | |
5521 | ||
5522 | IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n", | |
5523 | name, ucode_raw->size); | |
5524 | ||
5525 | /* Make sure that we got at least our header! */ | |
5526 | if (ucode_raw->size < sizeof(*ucode)) { | |
5527 | IWL_ERROR("File size way too small!\n"); | |
90e759d1 | 5528 | ret = -EINVAL; |
b481de9c ZY |
5529 | goto err_release; |
5530 | } | |
5531 | ||
5532 | /* Data from ucode file: header followed by uCode images */ | |
5533 | ucode = (void *)ucode_raw->data; | |
5534 | ||
5535 | ver = le32_to_cpu(ucode->ver); | |
5536 | inst_size = le32_to_cpu(ucode->inst_size); | |
5537 | data_size = le32_to_cpu(ucode->data_size); | |
5538 | init_size = le32_to_cpu(ucode->init_size); | |
5539 | init_data_size = le32_to_cpu(ucode->init_data_size); | |
5540 | boot_size = le32_to_cpu(ucode->boot_size); | |
5541 | ||
5542 | IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver); | |
bc434dd2 IS |
5543 | IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size); |
5544 | IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size); | |
5545 | IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size); | |
5546 | IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size); | |
5547 | IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size); | |
b481de9c ZY |
5548 | |
5549 | /* Verify size of file vs. image size info in file's header */ | |
5550 | if (ucode_raw->size < sizeof(*ucode) + | |
5551 | inst_size + data_size + init_size + | |
5552 | init_data_size + boot_size) { | |
5553 | ||
5554 | IWL_DEBUG_INFO("uCode file size %d too small\n", | |
5555 | (int)ucode_raw->size); | |
90e759d1 | 5556 | ret = -EINVAL; |
b481de9c ZY |
5557 | goto err_release; |
5558 | } | |
5559 | ||
5560 | /* Verify that uCode images will fit in card's SRAM */ | |
5561 | if (inst_size > IWL_MAX_INST_SIZE) { | |
90e759d1 TW |
5562 | IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n", |
5563 | inst_size); | |
5564 | ret = -EINVAL; | |
b481de9c ZY |
5565 | goto err_release; |
5566 | } | |
5567 | ||
5568 | if (data_size > IWL_MAX_DATA_SIZE) { | |
90e759d1 TW |
5569 | IWL_DEBUG_INFO("uCode data len %d too large to fit in\n", |
5570 | data_size); | |
5571 | ret = -EINVAL; | |
b481de9c ZY |
5572 | goto err_release; |
5573 | } | |
5574 | if (init_size > IWL_MAX_INST_SIZE) { | |
90e759d1 TW |
5575 | IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n", |
5576 | init_size); | |
5577 | ret = -EINVAL; | |
b481de9c ZY |
5578 | goto err_release; |
5579 | } | |
5580 | if (init_data_size > IWL_MAX_DATA_SIZE) { | |
90e759d1 TW |
5581 | IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n", |
5582 | init_data_size); | |
5583 | ret = -EINVAL; | |
b481de9c ZY |
5584 | goto err_release; |
5585 | } | |
5586 | if (boot_size > IWL_MAX_BSM_SIZE) { | |
90e759d1 TW |
5587 | IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n", |
5588 | boot_size); | |
5589 | ret = -EINVAL; | |
b481de9c ZY |
5590 | goto err_release; |
5591 | } | |
5592 | ||
5593 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
5594 | ||
5595 | /* Runtime instructions and 2 copies of data: | |
5596 | * 1) unmodified from disk | |
5597 | * 2) backup cache for save/restore during power-downs */ | |
5598 | priv->ucode_code.len = inst_size; | |
98c92211 | 5599 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
5600 | |
5601 | priv->ucode_data.len = data_size; | |
98c92211 | 5602 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
5603 | |
5604 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 5605 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 5606 | |
90e759d1 TW |
5607 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
5608 | !priv->ucode_data_backup.v_addr) | |
5609 | goto err_pci_alloc; | |
b481de9c ZY |
5610 | |
5611 | /* Initialization instructions and data */ | |
90e759d1 TW |
5612 | if (init_size && init_data_size) { |
5613 | priv->ucode_init.len = init_size; | |
98c92211 | 5614 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
5615 | |
5616 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 5617 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
5618 | |
5619 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
5620 | goto err_pci_alloc; | |
5621 | } | |
b481de9c ZY |
5622 | |
5623 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
5624 | if (boot_size) { |
5625 | priv->ucode_boot.len = boot_size; | |
98c92211 | 5626 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 5627 | |
90e759d1 TW |
5628 | if (!priv->ucode_boot.v_addr) |
5629 | goto err_pci_alloc; | |
5630 | } | |
b481de9c ZY |
5631 | |
5632 | /* Copy images into buffers for card's bus-master reads ... */ | |
5633 | ||
5634 | /* Runtime instructions (first block of data in file) */ | |
5635 | src = &ucode->data[0]; | |
5636 | len = priv->ucode_code.len; | |
90e759d1 | 5637 | IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c ZY |
5638 | memcpy(priv->ucode_code.v_addr, src, len); |
5639 | IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", | |
5640 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); | |
5641 | ||
5642 | /* Runtime data (2nd block) | |
bb8c093b | 5643 | * NOTE: Copy into backup buffer will be done in iwl3945_up() */ |
b481de9c ZY |
5644 | src = &ucode->data[inst_size]; |
5645 | len = priv->ucode_data.len; | |
90e759d1 | 5646 | IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
5647 | memcpy(priv->ucode_data.v_addr, src, len); |
5648 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
5649 | ||
5650 | /* Initialization instructions (3rd block) */ | |
5651 | if (init_size) { | |
5652 | src = &ucode->data[inst_size + data_size]; | |
5653 | len = priv->ucode_init.len; | |
90e759d1 TW |
5654 | IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n", |
5655 | len); | |
b481de9c ZY |
5656 | memcpy(priv->ucode_init.v_addr, src, len); |
5657 | } | |
5658 | ||
5659 | /* Initialization data (4th block) */ | |
5660 | if (init_data_size) { | |
5661 | src = &ucode->data[inst_size + data_size + init_size]; | |
5662 | len = priv->ucode_init_data.len; | |
5663 | IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n", | |
5664 | (int)len); | |
5665 | memcpy(priv->ucode_init_data.v_addr, src, len); | |
5666 | } | |
5667 | ||
5668 | /* Bootstrap instructions (5th block) */ | |
5669 | src = &ucode->data[inst_size + data_size + init_size + init_data_size]; | |
5670 | len = priv->ucode_boot.len; | |
5671 | IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n", | |
5672 | (int)len); | |
5673 | memcpy(priv->ucode_boot.v_addr, src, len); | |
5674 | ||
5675 | /* We have our copies now, allow OS release its copies */ | |
5676 | release_firmware(ucode_raw); | |
5677 | return 0; | |
5678 | ||
5679 | err_pci_alloc: | |
5680 | IWL_ERROR("failed to allocate pci memory\n"); | |
90e759d1 | 5681 | ret = -ENOMEM; |
bb8c093b | 5682 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
5683 | |
5684 | err_release: | |
5685 | release_firmware(ucode_raw); | |
5686 | ||
5687 | error: | |
90e759d1 | 5688 | return ret; |
b481de9c ZY |
5689 | } |
5690 | ||
5691 | ||
5692 | /** | |
bb8c093b | 5693 | * iwl3945_set_ucode_ptrs - Set uCode address location |
b481de9c ZY |
5694 | * |
5695 | * Tell initialization uCode where to find runtime uCode. | |
5696 | * | |
5697 | * BSM registers initially contain pointers to initialization uCode. | |
5698 | * We need to replace them to load runtime uCode inst and data, | |
5699 | * and to save runtime data when powering down. | |
5700 | */ | |
bb8c093b | 5701 | static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv) |
b481de9c ZY |
5702 | { |
5703 | dma_addr_t pinst; | |
5704 | dma_addr_t pdata; | |
5705 | int rc = 0; | |
5706 | unsigned long flags; | |
5707 | ||
5708 | /* bits 31:0 for 3945 */ | |
5709 | pinst = priv->ucode_code.p_addr; | |
5710 | pdata = priv->ucode_data_backup.p_addr; | |
5711 | ||
5712 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 5713 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5714 | if (rc) { |
5715 | spin_unlock_irqrestore(&priv->lock, flags); | |
5716 | return rc; | |
5717 | } | |
5718 | ||
5719 | /* Tell bootstrap uCode where to find image to load */ | |
bb8c093b CH |
5720 | iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
5721 | iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
5722 | iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
b481de9c ZY |
5723 | priv->ucode_data.len); |
5724 | ||
5725 | /* Inst bytecount must be last to set up, bit 31 signals uCode | |
5726 | * that all new ptr/size info is in place */ | |
bb8c093b | 5727 | iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
b481de9c ZY |
5728 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
5729 | ||
bb8c093b | 5730 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5731 | |
5732 | spin_unlock_irqrestore(&priv->lock, flags); | |
5733 | ||
5734 | IWL_DEBUG_INFO("Runtime uCode pointers are set.\n"); | |
5735 | ||
5736 | return rc; | |
5737 | } | |
5738 | ||
5739 | /** | |
bb8c093b | 5740 | * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received |
b481de9c ZY |
5741 | * |
5742 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
5743 | * | |
b481de9c | 5744 | * Tell "initialize" uCode to go ahead and load the runtime uCode. |
9fbab516 | 5745 | */ |
bb8c093b | 5746 | static void iwl3945_init_alive_start(struct iwl3945_priv *priv) |
b481de9c ZY |
5747 | { |
5748 | /* Check alive response for "valid" sign from uCode */ | |
5749 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
5750 | /* We had an error bringing up the hardware, so take it | |
5751 | * all the way back down so we can try again */ | |
5752 | IWL_DEBUG_INFO("Initialize Alive failed.\n"); | |
5753 | goto restart; | |
5754 | } | |
5755 | ||
5756 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
5757 | * This is a paranoid check, because we would not have gotten the | |
5758 | * "initialize" alive if code weren't properly loaded. */ | |
bb8c093b | 5759 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
5760 | /* Runtime instruction load was bad; |
5761 | * take it all the way back down so we can try again */ | |
5762 | IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); | |
5763 | goto restart; | |
5764 | } | |
5765 | ||
5766 | /* Send pointers to protocol/runtime uCode image ... init code will | |
5767 | * load and launch runtime uCode, which will send us another "Alive" | |
5768 | * notification. */ | |
5769 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
bb8c093b | 5770 | if (iwl3945_set_ucode_ptrs(priv)) { |
b481de9c ZY |
5771 | /* Runtime instruction load won't happen; |
5772 | * take it all the way back down so we can try again */ | |
5773 | IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n"); | |
5774 | goto restart; | |
5775 | } | |
5776 | return; | |
5777 | ||
5778 | restart: | |
5779 | queue_work(priv->workqueue, &priv->restart); | |
5780 | } | |
5781 | ||
5782 | ||
5783 | /** | |
bb8c093b | 5784 | * iwl3945_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 5785 | * from protocol/runtime uCode (initialization uCode's |
bb8c093b | 5786 | * Alive gets handled by iwl3945_init_alive_start()). |
b481de9c | 5787 | */ |
bb8c093b | 5788 | static void iwl3945_alive_start(struct iwl3945_priv *priv) |
b481de9c ZY |
5789 | { |
5790 | int rc = 0; | |
5791 | int thermal_spin = 0; | |
5792 | u32 rfkill; | |
5793 | ||
5794 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
5795 | ||
5796 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
5797 | /* We had an error bringing up the hardware, so take it | |
5798 | * all the way back down so we can try again */ | |
5799 | IWL_DEBUG_INFO("Alive failed.\n"); | |
5800 | goto restart; | |
5801 | } | |
5802 | ||
5803 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
5804 | * This is a paranoid check, because we would not have gotten the | |
5805 | * "runtime" alive if code weren't properly loaded. */ | |
bb8c093b | 5806 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
5807 | /* Runtime instruction load was bad; |
5808 | * take it all the way back down so we can try again */ | |
5809 | IWL_DEBUG_INFO("Bad runtime uCode load.\n"); | |
5810 | goto restart; | |
5811 | } | |
5812 | ||
bb8c093b | 5813 | iwl3945_clear_stations_table(priv); |
b481de9c | 5814 | |
bb8c093b | 5815 | rc = iwl3945_grab_nic_access(priv); |
b481de9c ZY |
5816 | if (rc) { |
5817 | IWL_WARNING("Can not read rfkill status from adapter\n"); | |
5818 | return; | |
5819 | } | |
5820 | ||
bb8c093b | 5821 | rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG); |
b481de9c | 5822 | IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill); |
bb8c093b | 5823 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5824 | |
5825 | if (rfkill & 0x1) { | |
5826 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
5827 | /* if rfkill is not on, then wait for thermal | |
5828 | * sensor in adapter to kick in */ | |
bb8c093b | 5829 | while (iwl3945_hw_get_temperature(priv) == 0) { |
b481de9c ZY |
5830 | thermal_spin++; |
5831 | udelay(10); | |
5832 | } | |
5833 | ||
5834 | if (thermal_spin) | |
5835 | IWL_DEBUG_INFO("Thermal calibration took %dus\n", | |
5836 | thermal_spin * 10); | |
5837 | } else | |
5838 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
5839 | ||
9fbab516 | 5840 | /* After the ALIVE response, we can send commands to 3945 uCode */ |
b481de9c ZY |
5841 | set_bit(STATUS_ALIVE, &priv->status); |
5842 | ||
5843 | /* Clear out the uCode error bit if it is set */ | |
5844 | clear_bit(STATUS_FW_ERROR, &priv->status); | |
5845 | ||
bb8c093b | 5846 | if (iwl3945_is_rfkill(priv)) |
b481de9c ZY |
5847 | return; |
5848 | ||
5a66926a | 5849 | ieee80211_start_queues(priv->hw); |
b481de9c ZY |
5850 | |
5851 | priv->active_rate = priv->rates_mask; | |
5852 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
5853 | ||
bb8c093b | 5854 | iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode)); |
b481de9c | 5855 | |
bb8c093b CH |
5856 | if (iwl3945_is_associated(priv)) { |
5857 | struct iwl3945_rxon_cmd *active_rxon = | |
5858 | (struct iwl3945_rxon_cmd *)(&priv->active_rxon); | |
b481de9c ZY |
5859 | |
5860 | memcpy(&priv->staging_rxon, &priv->active_rxon, | |
5861 | sizeof(priv->staging_rxon)); | |
5862 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
5863 | } else { | |
5864 | /* Initialize our rx_config data */ | |
bb8c093b | 5865 | iwl3945_connection_init_rx_config(priv); |
b481de9c ZY |
5866 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
5867 | } | |
5868 | ||
9fbab516 | 5869 | /* Configure Bluetooth device coexistence support */ |
bb8c093b | 5870 | iwl3945_send_bt_config(priv); |
b481de9c ZY |
5871 | |
5872 | /* Configure the adapter for unassociated operation */ | |
bb8c093b | 5873 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
5874 | |
5875 | /* At this point, the NIC is initialized and operational */ | |
5876 | priv->notif_missed_beacons = 0; | |
b481de9c ZY |
5877 | |
5878 | iwl3945_reg_txpower_periodic(priv); | |
5879 | ||
fe00b5a5 RC |
5880 | iwl3945_led_register(priv); |
5881 | ||
b481de9c | 5882 | IWL_DEBUG_INFO("ALIVE processing complete.\n"); |
a9f46786 | 5883 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 5884 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c ZY |
5885 | |
5886 | if (priv->error_recovering) | |
bb8c093b | 5887 | iwl3945_error_recovery(priv); |
b481de9c | 5888 | |
84363e6e | 5889 | ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC); |
b481de9c ZY |
5890 | return; |
5891 | ||
5892 | restart: | |
5893 | queue_work(priv->workqueue, &priv->restart); | |
5894 | } | |
5895 | ||
bb8c093b | 5896 | static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv); |
b481de9c | 5897 | |
bb8c093b | 5898 | static void __iwl3945_down(struct iwl3945_priv *priv) |
b481de9c ZY |
5899 | { |
5900 | unsigned long flags; | |
5901 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
5902 | struct ieee80211_conf *conf = NULL; | |
5903 | ||
5904 | IWL_DEBUG_INFO(DRV_NAME " is going down\n"); | |
5905 | ||
5906 | conf = ieee80211_get_hw_conf(priv->hw); | |
5907 | ||
5908 | if (!exit_pending) | |
5909 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5910 | ||
ab53d8af | 5911 | iwl3945_led_unregister(priv); |
bb8c093b | 5912 | iwl3945_clear_stations_table(priv); |
b481de9c ZY |
5913 | |
5914 | /* Unblock any waiting calls */ | |
5915 | wake_up_interruptible_all(&priv->wait_command_queue); | |
5916 | ||
b481de9c ZY |
5917 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
5918 | * exiting the module */ | |
5919 | if (!exit_pending) | |
5920 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
5921 | ||
5922 | /* stop and reset the on-board processor */ | |
bb8c093b | 5923 | iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
5924 | |
5925 | /* tell the device to stop sending interrupts */ | |
0359facc | 5926 | spin_lock_irqsave(&priv->lock, flags); |
bb8c093b | 5927 | iwl3945_disable_interrupts(priv); |
0359facc MA |
5928 | spin_unlock_irqrestore(&priv->lock, flags); |
5929 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
5930 | |
5931 | if (priv->mac80211_registered) | |
5932 | ieee80211_stop_queues(priv->hw); | |
5933 | ||
bb8c093b | 5934 | /* If we have not previously called iwl3945_init() then |
b481de9c | 5935 | * clear all bits but the RF Kill and SUSPEND bits and return */ |
bb8c093b | 5936 | if (!iwl3945_is_init(priv)) { |
b481de9c ZY |
5937 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
5938 | STATUS_RF_KILL_HW | | |
5939 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
5940 | STATUS_RF_KILL_SW | | |
9788864e RC |
5941 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
5942 | STATUS_GEO_CONFIGURED | | |
b481de9c ZY |
5943 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
5944 | STATUS_IN_SUSPEND; | |
5945 | goto exit; | |
5946 | } | |
5947 | ||
5948 | /* ...otherwise clear out all the status bits but the RF Kill and | |
5949 | * SUSPEND bits and continue taking the NIC down. */ | |
5950 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << | |
5951 | STATUS_RF_KILL_HW | | |
5952 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
5953 | STATUS_RF_KILL_SW | | |
9788864e RC |
5954 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
5955 | STATUS_GEO_CONFIGURED | | |
b481de9c ZY |
5956 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
5957 | STATUS_IN_SUSPEND | | |
5958 | test_bit(STATUS_FW_ERROR, &priv->status) << | |
5959 | STATUS_FW_ERROR; | |
5960 | ||
5961 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 5962 | iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
5963 | spin_unlock_irqrestore(&priv->lock, flags); |
5964 | ||
bb8c093b CH |
5965 | iwl3945_hw_txq_ctx_stop(priv); |
5966 | iwl3945_hw_rxq_stop(priv); | |
b481de9c ZY |
5967 | |
5968 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b CH |
5969 | if (!iwl3945_grab_nic_access(priv)) { |
5970 | iwl3945_write_prph(priv, APMG_CLK_DIS_REG, | |
b481de9c | 5971 | APMG_CLK_VAL_DMA_CLK_RQT); |
bb8c093b | 5972 | iwl3945_release_nic_access(priv); |
b481de9c ZY |
5973 | } |
5974 | spin_unlock_irqrestore(&priv->lock, flags); | |
5975 | ||
5976 | udelay(5); | |
5977 | ||
bb8c093b CH |
5978 | iwl3945_hw_nic_stop_master(priv); |
5979 | iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
5980 | iwl3945_hw_nic_reset(priv); | |
b481de9c ZY |
5981 | |
5982 | exit: | |
bb8c093b | 5983 | memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp)); |
b481de9c ZY |
5984 | |
5985 | if (priv->ibss_beacon) | |
5986 | dev_kfree_skb(priv->ibss_beacon); | |
5987 | priv->ibss_beacon = NULL; | |
5988 | ||
5989 | /* clear out any free frames */ | |
bb8c093b | 5990 | iwl3945_clear_free_frames(priv); |
b481de9c ZY |
5991 | } |
5992 | ||
bb8c093b | 5993 | static void iwl3945_down(struct iwl3945_priv *priv) |
b481de9c ZY |
5994 | { |
5995 | mutex_lock(&priv->mutex); | |
bb8c093b | 5996 | __iwl3945_down(priv); |
b481de9c | 5997 | mutex_unlock(&priv->mutex); |
b24d22b1 | 5998 | |
bb8c093b | 5999 | iwl3945_cancel_deferred_work(priv); |
b481de9c ZY |
6000 | } |
6001 | ||
6002 | #define MAX_HW_RESTARTS 5 | |
6003 | ||
bb8c093b | 6004 | static int __iwl3945_up(struct iwl3945_priv *priv) |
b481de9c ZY |
6005 | { |
6006 | int rc, i; | |
6007 | ||
6008 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
6009 | IWL_WARNING("Exit pending; will not bring the NIC up\n"); | |
6010 | return -EIO; | |
6011 | } | |
6012 | ||
6013 | if (test_bit(STATUS_RF_KILL_SW, &priv->status)) { | |
6014 | IWL_WARNING("Radio disabled by SW RF kill (module " | |
6015 | "parameter)\n"); | |
e655b9f0 ZY |
6016 | return -ENODEV; |
6017 | } | |
6018 | ||
e903fbd4 RC |
6019 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
6020 | IWL_ERROR("ucode not available for device bringup\n"); | |
6021 | return -EIO; | |
6022 | } | |
6023 | ||
e655b9f0 ZY |
6024 | /* If platform's RF_KILL switch is NOT set to KILL */ |
6025 | if (iwl3945_read32(priv, CSR_GP_CNTRL) & | |
6026 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
6027 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
6028 | else { | |
6029 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6030 | if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) { | |
6031 | IWL_WARNING("Radio disabled by HW RF Kill switch\n"); | |
6032 | return -ENODEV; | |
6033 | } | |
b481de9c ZY |
6034 | } |
6035 | ||
bb8c093b | 6036 | iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 6037 | |
bb8c093b | 6038 | rc = iwl3945_hw_nic_init(priv); |
b481de9c ZY |
6039 | if (rc) { |
6040 | IWL_ERROR("Unable to int nic\n"); | |
6041 | return rc; | |
6042 | } | |
6043 | ||
6044 | /* make sure rfkill handshake bits are cleared */ | |
bb8c093b CH |
6045 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
6046 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
6047 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
6048 | ||
6049 | /* clear (again), then enable host interrupts */ | |
bb8c093b CH |
6050 | iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF); |
6051 | iwl3945_enable_interrupts(priv); | |
b481de9c ZY |
6052 | |
6053 | /* really make sure rfkill handshake bits are cleared */ | |
bb8c093b CH |
6054 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
6055 | iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
6056 | |
6057 | /* Copy original ucode data image from disk into backup cache. | |
6058 | * This will be used to initialize the on-board processor's | |
6059 | * data SRAM for a clean start when the runtime program first loads. */ | |
6060 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 6061 | priv->ucode_data.len); |
b481de9c | 6062 | |
e655b9f0 ZY |
6063 | /* We return success when we resume from suspend and rf_kill is on. */ |
6064 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
6065 | return 0; | |
6066 | ||
b481de9c ZY |
6067 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
6068 | ||
bb8c093b | 6069 | iwl3945_clear_stations_table(priv); |
b481de9c ZY |
6070 | |
6071 | /* load bootstrap state machine, | |
6072 | * load bootstrap program into processor's memory, | |
6073 | * prepare to load the "initialize" uCode */ | |
bb8c093b | 6074 | rc = iwl3945_load_bsm(priv); |
b481de9c ZY |
6075 | |
6076 | if (rc) { | |
6077 | IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc); | |
6078 | continue; | |
6079 | } | |
6080 | ||
6081 | /* start card; "initialize" will load runtime ucode */ | |
bb8c093b | 6082 | iwl3945_nic_start(priv); |
b481de9c | 6083 | |
b481de9c ZY |
6084 | IWL_DEBUG_INFO(DRV_NAME " is coming up\n"); |
6085 | ||
6086 | return 0; | |
6087 | } | |
6088 | ||
6089 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
bb8c093b | 6090 | __iwl3945_down(priv); |
b481de9c ZY |
6091 | |
6092 | /* tried to restart and config the device for as long as our | |
6093 | * patience could withstand */ | |
6094 | IWL_ERROR("Unable to initialize device after %d attempts.\n", i); | |
6095 | return -EIO; | |
6096 | } | |
6097 | ||
6098 | ||
6099 | /***************************************************************************** | |
6100 | * | |
6101 | * Workqueue callbacks | |
6102 | * | |
6103 | *****************************************************************************/ | |
6104 | ||
bb8c093b | 6105 | static void iwl3945_bg_init_alive_start(struct work_struct *data) |
b481de9c | 6106 | { |
bb8c093b CH |
6107 | struct iwl3945_priv *priv = |
6108 | container_of(data, struct iwl3945_priv, init_alive_start.work); | |
b481de9c ZY |
6109 | |
6110 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6111 | return; | |
6112 | ||
6113 | mutex_lock(&priv->mutex); | |
bb8c093b | 6114 | iwl3945_init_alive_start(priv); |
b481de9c ZY |
6115 | mutex_unlock(&priv->mutex); |
6116 | } | |
6117 | ||
bb8c093b | 6118 | static void iwl3945_bg_alive_start(struct work_struct *data) |
b481de9c | 6119 | { |
bb8c093b CH |
6120 | struct iwl3945_priv *priv = |
6121 | container_of(data, struct iwl3945_priv, alive_start.work); | |
b481de9c ZY |
6122 | |
6123 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6124 | return; | |
6125 | ||
6126 | mutex_lock(&priv->mutex); | |
bb8c093b | 6127 | iwl3945_alive_start(priv); |
b481de9c ZY |
6128 | mutex_unlock(&priv->mutex); |
6129 | } | |
6130 | ||
bb8c093b | 6131 | static void iwl3945_bg_rf_kill(struct work_struct *work) |
b481de9c | 6132 | { |
bb8c093b | 6133 | struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill); |
b481de9c ZY |
6134 | |
6135 | wake_up_interruptible(&priv->wait_command_queue); | |
6136 | ||
6137 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6138 | return; | |
6139 | ||
6140 | mutex_lock(&priv->mutex); | |
6141 | ||
bb8c093b | 6142 | if (!iwl3945_is_rfkill(priv)) { |
b481de9c ZY |
6143 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL, |
6144 | "HW and/or SW RF Kill no longer active, restarting " | |
6145 | "device\n"); | |
6146 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6147 | queue_work(priv->workqueue, &priv->restart); | |
6148 | } else { | |
6149 | ||
6150 | if (!test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
6151 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
6152 | "disabled by SW switch\n"); | |
6153 | else | |
6154 | IWL_WARNING("Radio Frequency Kill Switch is On:\n" | |
6155 | "Kill switch must be turned off for " | |
6156 | "wireless networking to work.\n"); | |
6157 | } | |
6158 | mutex_unlock(&priv->mutex); | |
6159 | } | |
6160 | ||
6161 | #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ) | |
6162 | ||
bb8c093b | 6163 | static void iwl3945_bg_scan_check(struct work_struct *data) |
b481de9c | 6164 | { |
bb8c093b CH |
6165 | struct iwl3945_priv *priv = |
6166 | container_of(data, struct iwl3945_priv, scan_check.work); | |
b481de9c ZY |
6167 | |
6168 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6169 | return; | |
6170 | ||
6171 | mutex_lock(&priv->mutex); | |
6172 | if (test_bit(STATUS_SCANNING, &priv->status) || | |
6173 | test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
6174 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, | |
6175 | "Scan completion watchdog resetting adapter (%dms)\n", | |
6176 | jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG)); | |
15e869d8 | 6177 | |
b481de9c | 6178 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) |
bb8c093b | 6179 | iwl3945_send_scan_abort(priv); |
b481de9c ZY |
6180 | } |
6181 | mutex_unlock(&priv->mutex); | |
6182 | } | |
6183 | ||
bb8c093b | 6184 | static void iwl3945_bg_request_scan(struct work_struct *data) |
b481de9c | 6185 | { |
bb8c093b CH |
6186 | struct iwl3945_priv *priv = |
6187 | container_of(data, struct iwl3945_priv, request_scan); | |
6188 | struct iwl3945_host_cmd cmd = { | |
b481de9c | 6189 | .id = REPLY_SCAN_CMD, |
bb8c093b | 6190 | .len = sizeof(struct iwl3945_scan_cmd), |
b481de9c ZY |
6191 | .meta.flags = CMD_SIZE_HUGE, |
6192 | }; | |
6193 | int rc = 0; | |
bb8c093b | 6194 | struct iwl3945_scan_cmd *scan; |
b481de9c ZY |
6195 | struct ieee80211_conf *conf = NULL; |
6196 | u8 direct_mask; | |
8318d78a | 6197 | enum ieee80211_band band; |
b481de9c ZY |
6198 | |
6199 | conf = ieee80211_get_hw_conf(priv->hw); | |
6200 | ||
6201 | mutex_lock(&priv->mutex); | |
6202 | ||
bb8c093b | 6203 | if (!iwl3945_is_ready(priv)) { |
b481de9c ZY |
6204 | IWL_WARNING("request scan called when driver not ready.\n"); |
6205 | goto done; | |
6206 | } | |
6207 | ||
6208 | /* Make sure the scan wasn't cancelled before this queued work | |
6209 | * was given the chance to run... */ | |
6210 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
6211 | goto done; | |
6212 | ||
6213 | /* This should never be called or scheduled if there is currently | |
6214 | * a scan active in the hardware. */ | |
6215 | if (test_bit(STATUS_SCAN_HW, &priv->status)) { | |
6216 | IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. " | |
6217 | "Ignoring second request.\n"); | |
6218 | rc = -EIO; | |
6219 | goto done; | |
6220 | } | |
6221 | ||
6222 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
6223 | IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n"); | |
6224 | goto done; | |
6225 | } | |
6226 | ||
6227 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
6228 | IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n"); | |
6229 | goto done; | |
6230 | } | |
6231 | ||
bb8c093b | 6232 | if (iwl3945_is_rfkill(priv)) { |
b481de9c ZY |
6233 | IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n"); |
6234 | goto done; | |
6235 | } | |
6236 | ||
6237 | if (!test_bit(STATUS_READY, &priv->status)) { | |
6238 | IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n"); | |
6239 | goto done; | |
6240 | } | |
6241 | ||
6242 | if (!priv->scan_bands) { | |
6243 | IWL_DEBUG_HC("Aborting scan due to no requested bands\n"); | |
6244 | goto done; | |
6245 | } | |
6246 | ||
6247 | if (!priv->scan) { | |
bb8c093b | 6248 | priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) + |
b481de9c ZY |
6249 | IWL_MAX_SCAN_SIZE, GFP_KERNEL); |
6250 | if (!priv->scan) { | |
6251 | rc = -ENOMEM; | |
6252 | goto done; | |
6253 | } | |
6254 | } | |
6255 | scan = priv->scan; | |
bb8c093b | 6256 | memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE); |
b481de9c ZY |
6257 | |
6258 | scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; | |
6259 | scan->quiet_time = IWL_ACTIVE_QUIET_TIME; | |
6260 | ||
bb8c093b | 6261 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
6262 | u16 interval = 0; |
6263 | u32 extra; | |
6264 | u32 suspend_time = 100; | |
6265 | u32 scan_suspend_time = 100; | |
6266 | unsigned long flags; | |
6267 | ||
6268 | IWL_DEBUG_INFO("Scanning while associated...\n"); | |
6269 | ||
6270 | spin_lock_irqsave(&priv->lock, flags); | |
6271 | interval = priv->beacon_int; | |
6272 | spin_unlock_irqrestore(&priv->lock, flags); | |
6273 | ||
6274 | scan->suspend_time = 0; | |
15e869d8 | 6275 | scan->max_out_time = cpu_to_le32(200 * 1024); |
b481de9c ZY |
6276 | if (!interval) |
6277 | interval = suspend_time; | |
6278 | /* | |
6279 | * suspend time format: | |
6280 | * 0-19: beacon interval in usec (time before exec.) | |
6281 | * 20-23: 0 | |
6282 | * 24-31: number of beacons (suspend between channels) | |
6283 | */ | |
6284 | ||
6285 | extra = (suspend_time / interval) << 24; | |
6286 | scan_suspend_time = 0xFF0FFFFF & | |
6287 | (extra | ((suspend_time % interval) * 1024)); | |
6288 | ||
6289 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
6290 | IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n", | |
6291 | scan_suspend_time, interval); | |
6292 | } | |
6293 | ||
6294 | /* We should add the ability for user to lock to PASSIVE ONLY */ | |
6295 | if (priv->one_direct_scan) { | |
6296 | IWL_DEBUG_SCAN | |
6297 | ("Kicking off one direct scan for '%s'\n", | |
bb8c093b | 6298 | iwl3945_escape_essid(priv->direct_ssid, |
b481de9c ZY |
6299 | priv->direct_ssid_len)); |
6300 | scan->direct_scan[0].id = WLAN_EID_SSID; | |
6301 | scan->direct_scan[0].len = priv->direct_ssid_len; | |
6302 | memcpy(scan->direct_scan[0].ssid, | |
6303 | priv->direct_ssid, priv->direct_ssid_len); | |
6304 | direct_mask = 1; | |
bb8c093b | 6305 | } else if (!iwl3945_is_associated(priv) && priv->essid_len) { |
b481de9c ZY |
6306 | scan->direct_scan[0].id = WLAN_EID_SSID; |
6307 | scan->direct_scan[0].len = priv->essid_len; | |
6308 | memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len); | |
6309 | direct_mask = 1; | |
6310 | } else | |
6311 | direct_mask = 0; | |
6312 | ||
6313 | /* We don't build a direct scan probe request; the uCode will do | |
6314 | * that based on the direct_mask added to each channel entry */ | |
6315 | scan->tx_cmd.len = cpu_to_le16( | |
bb8c093b | 6316 | iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data, |
18904f58 | 6317 | IWL_MAX_SCAN_SIZE - sizeof(*scan), 0)); |
b481de9c ZY |
6318 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; |
6319 | scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id; | |
6320 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
6321 | ||
6322 | /* flags + rate selection */ | |
6323 | ||
6324 | switch (priv->scan_bands) { | |
6325 | case 2: | |
6326 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; | |
6327 | scan->tx_cmd.rate = IWL_RATE_1M_PLCP; | |
6328 | scan->good_CRC_th = 0; | |
8318d78a | 6329 | band = IEEE80211_BAND_2GHZ; |
b481de9c ZY |
6330 | break; |
6331 | ||
6332 | case 1: | |
6333 | scan->tx_cmd.rate = IWL_RATE_6M_PLCP; | |
6334 | scan->good_CRC_th = IWL_GOOD_CRC_TH; | |
8318d78a | 6335 | band = IEEE80211_BAND_5GHZ; |
b481de9c ZY |
6336 | break; |
6337 | ||
6338 | default: | |
6339 | IWL_WARNING("Invalid scan band count\n"); | |
6340 | goto done; | |
6341 | } | |
6342 | ||
6343 | /* select Rx antennas */ | |
6344 | scan->flags |= iwl3945_get_antenna_flags(priv); | |
6345 | ||
6346 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) | |
6347 | scan->filter_flags = RXON_FILTER_PROMISC_MSK; | |
6348 | ||
26c0f03f | 6349 | if (direct_mask) { |
b481de9c ZY |
6350 | IWL_DEBUG_SCAN |
6351 | ("Initiating direct scan for %s.\n", | |
bb8c093b | 6352 | iwl3945_escape_essid(priv->essid, priv->essid_len)); |
26c0f03f RC |
6353 | scan->channel_count = |
6354 | iwl3945_get_channels_for_scan( | |
6355 | priv, band, 1, /* active */ | |
6356 | direct_mask, | |
6357 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); | |
6358 | } else { | |
b481de9c | 6359 | IWL_DEBUG_SCAN("Initiating indirect scan.\n"); |
26c0f03f RC |
6360 | scan->channel_count = |
6361 | iwl3945_get_channels_for_scan( | |
6362 | priv, band, 0, /* passive */ | |
6363 | direct_mask, | |
6364 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); | |
6365 | } | |
b481de9c ZY |
6366 | |
6367 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + | |
bb8c093b | 6368 | scan->channel_count * sizeof(struct iwl3945_scan_channel); |
b481de9c ZY |
6369 | cmd.data = scan; |
6370 | scan->len = cpu_to_le16(cmd.len); | |
6371 | ||
6372 | set_bit(STATUS_SCAN_HW, &priv->status); | |
bb8c093b | 6373 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
6374 | if (rc) |
6375 | goto done; | |
6376 | ||
6377 | queue_delayed_work(priv->workqueue, &priv->scan_check, | |
6378 | IWL_SCAN_CHECK_WATCHDOG); | |
6379 | ||
6380 | mutex_unlock(&priv->mutex); | |
6381 | return; | |
6382 | ||
6383 | done: | |
01ebd063 | 6384 | /* inform mac80211 scan aborted */ |
b481de9c ZY |
6385 | queue_work(priv->workqueue, &priv->scan_completed); |
6386 | mutex_unlock(&priv->mutex); | |
6387 | } | |
6388 | ||
bb8c093b | 6389 | static void iwl3945_bg_up(struct work_struct *data) |
b481de9c | 6390 | { |
bb8c093b | 6391 | struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up); |
b481de9c ZY |
6392 | |
6393 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6394 | return; | |
6395 | ||
6396 | mutex_lock(&priv->mutex); | |
bb8c093b | 6397 | __iwl3945_up(priv); |
b481de9c ZY |
6398 | mutex_unlock(&priv->mutex); |
6399 | } | |
6400 | ||
bb8c093b | 6401 | static void iwl3945_bg_restart(struct work_struct *data) |
b481de9c | 6402 | { |
bb8c093b | 6403 | struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart); |
b481de9c ZY |
6404 | |
6405 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6406 | return; | |
6407 | ||
bb8c093b | 6408 | iwl3945_down(priv); |
b481de9c ZY |
6409 | queue_work(priv->workqueue, &priv->up); |
6410 | } | |
6411 | ||
bb8c093b | 6412 | static void iwl3945_bg_rx_replenish(struct work_struct *data) |
b481de9c | 6413 | { |
bb8c093b CH |
6414 | struct iwl3945_priv *priv = |
6415 | container_of(data, struct iwl3945_priv, rx_replenish); | |
b481de9c ZY |
6416 | |
6417 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6418 | return; | |
6419 | ||
6420 | mutex_lock(&priv->mutex); | |
bb8c093b | 6421 | iwl3945_rx_replenish(priv); |
b481de9c ZY |
6422 | mutex_unlock(&priv->mutex); |
6423 | } | |
6424 | ||
7878a5a4 MA |
6425 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
6426 | ||
bb8c093b | 6427 | static void iwl3945_bg_post_associate(struct work_struct *data) |
b481de9c | 6428 | { |
bb8c093b | 6429 | struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, |
b481de9c ZY |
6430 | post_associate.work); |
6431 | ||
6432 | int rc = 0; | |
6433 | struct ieee80211_conf *conf = NULL; | |
0795af57 | 6434 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
6435 | |
6436 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
6437 | IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__); | |
6438 | return; | |
6439 | } | |
6440 | ||
6441 | ||
0795af57 JP |
6442 | IWL_DEBUG_ASSOC("Associated as %d to: %s\n", |
6443 | priv->assoc_id, | |
6444 | print_mac(mac, priv->active_rxon.bssid_addr)); | |
b481de9c ZY |
6445 | |
6446 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6447 | return; | |
6448 | ||
6449 | mutex_lock(&priv->mutex); | |
6450 | ||
32bfd35d | 6451 | if (!priv->vif || !priv->is_open) { |
6ef89d0a MA |
6452 | mutex_unlock(&priv->mutex); |
6453 | return; | |
6454 | } | |
bb8c093b | 6455 | iwl3945_scan_cancel_timeout(priv, 200); |
15e869d8 | 6456 | |
b481de9c ZY |
6457 | conf = ieee80211_get_hw_conf(priv->hw); |
6458 | ||
6459 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6460 | iwl3945_commit_rxon(priv); |
b481de9c | 6461 | |
bb8c093b CH |
6462 | memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd)); |
6463 | iwl3945_setup_rxon_timing(priv); | |
6464 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING, | |
b481de9c ZY |
6465 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
6466 | if (rc) | |
6467 | IWL_WARNING("REPLY_RXON_TIMING failed - " | |
6468 | "Attempting to continue.\n"); | |
6469 | ||
6470 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
6471 | ||
6472 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
6473 | ||
6474 | IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n", | |
6475 | priv->assoc_id, priv->beacon_int); | |
6476 | ||
6477 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
6478 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
6479 | else | |
6480 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6481 | ||
6482 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
6483 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
6484 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
6485 | else | |
6486 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
6487 | ||
6488 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
6489 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
6490 | ||
6491 | } | |
6492 | ||
bb8c093b | 6493 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6494 | |
6495 | switch (priv->iw_mode) { | |
6496 | case IEEE80211_IF_TYPE_STA: | |
bb8c093b | 6497 | iwl3945_rate_scale_init(priv->hw, IWL_AP_ID); |
b481de9c ZY |
6498 | break; |
6499 | ||
6500 | case IEEE80211_IF_TYPE_IBSS: | |
6501 | ||
6502 | /* clear out the station table */ | |
bb8c093b | 6503 | iwl3945_clear_stations_table(priv); |
b481de9c | 6504 | |
bb8c093b CH |
6505 | iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0); |
6506 | iwl3945_add_station(priv, priv->bssid, 0, 0); | |
b481de9c | 6507 | iwl3945_sync_sta(priv, IWL_STA_ID, |
8318d78a | 6508 | (priv->band == IEEE80211_BAND_5GHZ) ? |
b481de9c ZY |
6509 | IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP, |
6510 | CMD_ASYNC); | |
bb8c093b CH |
6511 | iwl3945_rate_scale_init(priv->hw, IWL_STA_ID); |
6512 | iwl3945_send_beacon_cmd(priv); | |
b481de9c ZY |
6513 | |
6514 | break; | |
6515 | ||
6516 | default: | |
6517 | IWL_ERROR("%s Should not be called in %d mode\n", | |
bc434dd2 | 6518 | __FUNCTION__, priv->iw_mode); |
b481de9c ZY |
6519 | break; |
6520 | } | |
6521 | ||
bb8c093b | 6522 | iwl3945_sequence_reset(priv); |
b481de9c | 6523 | |
bb8c093b | 6524 | iwl3945_activate_qos(priv, 0); |
292ae174 | 6525 | |
7878a5a4 MA |
6526 | /* we have just associated, don't start scan too early */ |
6527 | priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN; | |
b481de9c ZY |
6528 | mutex_unlock(&priv->mutex); |
6529 | } | |
6530 | ||
bb8c093b | 6531 | static void iwl3945_bg_abort_scan(struct work_struct *work) |
b481de9c | 6532 | { |
bb8c093b | 6533 | struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan); |
b481de9c | 6534 | |
bb8c093b | 6535 | if (!iwl3945_is_ready(priv)) |
b481de9c ZY |
6536 | return; |
6537 | ||
6538 | mutex_lock(&priv->mutex); | |
6539 | ||
6540 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
bb8c093b | 6541 | iwl3945_send_scan_abort(priv); |
b481de9c ZY |
6542 | |
6543 | mutex_unlock(&priv->mutex); | |
6544 | } | |
6545 | ||
76bb77e0 ZY |
6546 | static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf); |
6547 | ||
bb8c093b | 6548 | static void iwl3945_bg_scan_completed(struct work_struct *work) |
b481de9c | 6549 | { |
bb8c093b CH |
6550 | struct iwl3945_priv *priv = |
6551 | container_of(work, struct iwl3945_priv, scan_completed); | |
b481de9c ZY |
6552 | |
6553 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n"); | |
6554 | ||
6555 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
6556 | return; | |
6557 | ||
a0646470 ZY |
6558 | if (test_bit(STATUS_CONF_PENDING, &priv->status)) |
6559 | iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw)); | |
76bb77e0 | 6560 | |
b481de9c ZY |
6561 | ieee80211_scan_completed(priv->hw); |
6562 | ||
6563 | /* Since setting the TXPOWER may have been deferred while | |
6564 | * performing the scan, fire one off */ | |
6565 | mutex_lock(&priv->mutex); | |
bb8c093b | 6566 | iwl3945_hw_reg_send_txpower(priv); |
b481de9c ZY |
6567 | mutex_unlock(&priv->mutex); |
6568 | } | |
6569 | ||
6570 | /***************************************************************************** | |
6571 | * | |
6572 | * mac80211 entry point functions | |
6573 | * | |
6574 | *****************************************************************************/ | |
6575 | ||
5a66926a ZY |
6576 | #define UCODE_READY_TIMEOUT (2 * HZ) |
6577 | ||
bb8c093b | 6578 | static int iwl3945_mac_start(struct ieee80211_hw *hw) |
b481de9c | 6579 | { |
bb8c093b | 6580 | struct iwl3945_priv *priv = hw->priv; |
5a66926a | 6581 | int ret; |
b481de9c ZY |
6582 | |
6583 | IWL_DEBUG_MAC80211("enter\n"); | |
6584 | ||
5a66926a ZY |
6585 | if (pci_enable_device(priv->pci_dev)) { |
6586 | IWL_ERROR("Fail to pci_enable_device\n"); | |
6587 | return -ENODEV; | |
6588 | } | |
6589 | pci_restore_state(priv->pci_dev); | |
6590 | pci_enable_msi(priv->pci_dev); | |
6591 | ||
6592 | ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED, | |
6593 | DRV_NAME, priv); | |
6594 | if (ret) { | |
6595 | IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq); | |
6596 | goto out_disable_msi; | |
6597 | } | |
6598 | ||
b481de9c ZY |
6599 | /* we should be verifying the device is ready to be opened */ |
6600 | mutex_lock(&priv->mutex); | |
6601 | ||
5a66926a ZY |
6602 | memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd)); |
6603 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... | |
6604 | * ucode filename and max sizes are card-specific. */ | |
6605 | ||
6606 | if (!priv->ucode_code.len) { | |
6607 | ret = iwl3945_read_ucode(priv); | |
6608 | if (ret) { | |
6609 | IWL_ERROR("Could not read microcode: %d\n", ret); | |
6610 | mutex_unlock(&priv->mutex); | |
6611 | goto out_release_irq; | |
6612 | } | |
6613 | } | |
b481de9c | 6614 | |
e655b9f0 | 6615 | ret = __iwl3945_up(priv); |
b481de9c ZY |
6616 | |
6617 | mutex_unlock(&priv->mutex); | |
5a66926a | 6618 | |
e655b9f0 ZY |
6619 | if (ret) |
6620 | goto out_release_irq; | |
6621 | ||
6622 | IWL_DEBUG_INFO("Start UP work.\n"); | |
6623 | ||
6624 | if (test_bit(STATUS_IN_SUSPEND, &priv->status)) | |
6625 | return 0; | |
6626 | ||
5a66926a ZY |
6627 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from |
6628 | * mac80211 will not be run successfully. */ | |
6629 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
6630 | test_bit(STATUS_READY, &priv->status), | |
6631 | UCODE_READY_TIMEOUT); | |
6632 | if (!ret) { | |
6633 | if (!test_bit(STATUS_READY, &priv->status)) { | |
6634 | IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n", | |
6635 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
6636 | ret = -ETIMEDOUT; | |
6637 | goto out_release_irq; | |
6638 | } | |
6639 | } | |
6640 | ||
e655b9f0 | 6641 | priv->is_open = 1; |
b481de9c ZY |
6642 | IWL_DEBUG_MAC80211("leave\n"); |
6643 | return 0; | |
5a66926a ZY |
6644 | |
6645 | out_release_irq: | |
6646 | free_irq(priv->pci_dev->irq, priv); | |
6647 | out_disable_msi: | |
6648 | pci_disable_msi(priv->pci_dev); | |
e655b9f0 ZY |
6649 | pci_disable_device(priv->pci_dev); |
6650 | priv->is_open = 0; | |
6651 | IWL_DEBUG_MAC80211("leave - failed\n"); | |
5a66926a | 6652 | return ret; |
b481de9c ZY |
6653 | } |
6654 | ||
bb8c093b | 6655 | static void iwl3945_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 6656 | { |
bb8c093b | 6657 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
6658 | |
6659 | IWL_DEBUG_MAC80211("enter\n"); | |
6ef89d0a | 6660 | |
e655b9f0 ZY |
6661 | if (!priv->is_open) { |
6662 | IWL_DEBUG_MAC80211("leave - skip\n"); | |
6663 | return; | |
6664 | } | |
6665 | ||
b481de9c | 6666 | priv->is_open = 0; |
5a66926a ZY |
6667 | |
6668 | if (iwl3945_is_ready_rf(priv)) { | |
e655b9f0 ZY |
6669 | /* stop mac, cancel any scan request and clear |
6670 | * RXON_FILTER_ASSOC_MSK BIT | |
6671 | */ | |
5a66926a ZY |
6672 | mutex_lock(&priv->mutex); |
6673 | iwl3945_scan_cancel_timeout(priv, 100); | |
6674 | cancel_delayed_work(&priv->post_associate); | |
fde3571f | 6675 | mutex_unlock(&priv->mutex); |
fde3571f MA |
6676 | } |
6677 | ||
5a66926a ZY |
6678 | iwl3945_down(priv); |
6679 | ||
6680 | flush_workqueue(priv->workqueue); | |
6681 | free_irq(priv->pci_dev->irq, priv); | |
6682 | pci_disable_msi(priv->pci_dev); | |
6683 | pci_save_state(priv->pci_dev); | |
6684 | pci_disable_device(priv->pci_dev); | |
6ef89d0a | 6685 | |
b481de9c | 6686 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
6687 | } |
6688 | ||
bb8c093b | 6689 | static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb, |
b481de9c ZY |
6690 | struct ieee80211_tx_control *ctl) |
6691 | { | |
bb8c093b | 6692 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
6693 | |
6694 | IWL_DEBUG_MAC80211("enter\n"); | |
6695 | ||
6696 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { | |
6697 | IWL_DEBUG_MAC80211("leave - monitor\n"); | |
6698 | return -1; | |
6699 | } | |
6700 | ||
6701 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, | |
8318d78a | 6702 | ctl->tx_rate->bitrate); |
b481de9c | 6703 | |
bb8c093b | 6704 | if (iwl3945_tx_skb(priv, skb, ctl)) |
b481de9c ZY |
6705 | dev_kfree_skb_any(skb); |
6706 | ||
6707 | IWL_DEBUG_MAC80211("leave\n"); | |
6708 | return 0; | |
6709 | } | |
6710 | ||
bb8c093b | 6711 | static int iwl3945_mac_add_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
6712 | struct ieee80211_if_init_conf *conf) |
6713 | { | |
bb8c093b | 6714 | struct iwl3945_priv *priv = hw->priv; |
b481de9c | 6715 | unsigned long flags; |
0795af57 | 6716 | DECLARE_MAC_BUF(mac); |
b481de9c | 6717 | |
32bfd35d | 6718 | IWL_DEBUG_MAC80211("enter: type %d\n", conf->type); |
b481de9c | 6719 | |
32bfd35d JB |
6720 | if (priv->vif) { |
6721 | IWL_DEBUG_MAC80211("leave - vif != NULL\n"); | |
864792e3 | 6722 | return -EOPNOTSUPP; |
b481de9c ZY |
6723 | } |
6724 | ||
6725 | spin_lock_irqsave(&priv->lock, flags); | |
32bfd35d | 6726 | priv->vif = conf->vif; |
b481de9c ZY |
6727 | |
6728 | spin_unlock_irqrestore(&priv->lock, flags); | |
6729 | ||
6730 | mutex_lock(&priv->mutex); | |
864792e3 TW |
6731 | |
6732 | if (conf->mac_addr) { | |
6733 | IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr)); | |
6734 | memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); | |
6735 | } | |
6736 | ||
5a66926a ZY |
6737 | if (iwl3945_is_ready(priv)) |
6738 | iwl3945_set_mode(priv, conf->type); | |
b481de9c | 6739 | |
b481de9c ZY |
6740 | mutex_unlock(&priv->mutex); |
6741 | ||
5a66926a | 6742 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
6743 | return 0; |
6744 | } | |
6745 | ||
6746 | /** | |
bb8c093b | 6747 | * iwl3945_mac_config - mac80211 config callback |
b481de9c ZY |
6748 | * |
6749 | * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to | |
6750 | * be set inappropriately and the driver currently sets the hardware up to | |
6751 | * use it whenever needed. | |
6752 | */ | |
bb8c093b | 6753 | static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) |
b481de9c | 6754 | { |
bb8c093b CH |
6755 | struct iwl3945_priv *priv = hw->priv; |
6756 | const struct iwl3945_channel_info *ch_info; | |
b481de9c | 6757 | unsigned long flags; |
76bb77e0 | 6758 | int ret = 0; |
b481de9c ZY |
6759 | |
6760 | mutex_lock(&priv->mutex); | |
8318d78a | 6761 | IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value); |
b481de9c | 6762 | |
12342c47 ZY |
6763 | priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP); |
6764 | ||
bb8c093b | 6765 | if (!iwl3945_is_ready(priv)) { |
b481de9c | 6766 | IWL_DEBUG_MAC80211("leave - not ready\n"); |
76bb77e0 ZY |
6767 | ret = -EIO; |
6768 | goto out; | |
b481de9c ZY |
6769 | } |
6770 | ||
bb8c093b | 6771 | if (unlikely(!iwl3945_param_disable_hw_scan && |
b481de9c | 6772 | test_bit(STATUS_SCANNING, &priv->status))) { |
a0646470 ZY |
6773 | IWL_DEBUG_MAC80211("leave - scanning\n"); |
6774 | set_bit(STATUS_CONF_PENDING, &priv->status); | |
b481de9c | 6775 | mutex_unlock(&priv->mutex); |
a0646470 | 6776 | return 0; |
b481de9c ZY |
6777 | } |
6778 | ||
6779 | spin_lock_irqsave(&priv->lock, flags); | |
6780 | ||
8318d78a JB |
6781 | ch_info = iwl3945_get_channel_info(priv, conf->channel->band, |
6782 | conf->channel->hw_value); | |
b481de9c ZY |
6783 | if (!is_channel_valid(ch_info)) { |
6784 | IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n", | |
8318d78a | 6785 | conf->channel->hw_value, conf->channel->band); |
b481de9c ZY |
6786 | IWL_DEBUG_MAC80211("leave - invalid channel\n"); |
6787 | spin_unlock_irqrestore(&priv->lock, flags); | |
76bb77e0 ZY |
6788 | ret = -EINVAL; |
6789 | goto out; | |
b481de9c ZY |
6790 | } |
6791 | ||
8318d78a | 6792 | iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value); |
b481de9c | 6793 | |
8318d78a | 6794 | iwl3945_set_flags_for_phymode(priv, conf->channel->band); |
b481de9c ZY |
6795 | |
6796 | /* The list of supported rates and rate mask can be different | |
6797 | * for each phymode; since the phymode may have changed, reset | |
6798 | * the rate mask to what mac80211 lists */ | |
bb8c093b | 6799 | iwl3945_set_rate(priv); |
b481de9c ZY |
6800 | |
6801 | spin_unlock_irqrestore(&priv->lock, flags); | |
6802 | ||
6803 | #ifdef IEEE80211_CONF_CHANNEL_SWITCH | |
6804 | if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) { | |
bb8c093b | 6805 | iwl3945_hw_channel_switch(priv, conf->channel); |
76bb77e0 | 6806 | goto out; |
b481de9c ZY |
6807 | } |
6808 | #endif | |
6809 | ||
bb8c093b | 6810 | iwl3945_radio_kill_sw(priv, !conf->radio_enabled); |
b481de9c ZY |
6811 | |
6812 | if (!conf->radio_enabled) { | |
6813 | IWL_DEBUG_MAC80211("leave - radio disabled\n"); | |
76bb77e0 | 6814 | goto out; |
b481de9c ZY |
6815 | } |
6816 | ||
bb8c093b | 6817 | if (iwl3945_is_rfkill(priv)) { |
b481de9c | 6818 | IWL_DEBUG_MAC80211("leave - RF kill\n"); |
76bb77e0 ZY |
6819 | ret = -EIO; |
6820 | goto out; | |
b481de9c ZY |
6821 | } |
6822 | ||
bb8c093b | 6823 | iwl3945_set_rate(priv); |
b481de9c ZY |
6824 | |
6825 | if (memcmp(&priv->active_rxon, | |
6826 | &priv->staging_rxon, sizeof(priv->staging_rxon))) | |
bb8c093b | 6827 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6828 | else |
6829 | IWL_DEBUG_INFO("No re-sending same RXON configuration.\n"); | |
6830 | ||
6831 | IWL_DEBUG_MAC80211("leave\n"); | |
6832 | ||
76bb77e0 | 6833 | out: |
a0646470 | 6834 | clear_bit(STATUS_CONF_PENDING, &priv->status); |
b481de9c | 6835 | mutex_unlock(&priv->mutex); |
76bb77e0 | 6836 | return ret; |
b481de9c ZY |
6837 | } |
6838 | ||
bb8c093b | 6839 | static void iwl3945_config_ap(struct iwl3945_priv *priv) |
b481de9c ZY |
6840 | { |
6841 | int rc = 0; | |
6842 | ||
d986bcd1 | 6843 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
6844 | return; |
6845 | ||
6846 | /* The following should be done only at AP bring up */ | |
6847 | if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) { | |
6848 | ||
6849 | /* RXON - unassoc (to set timing command) */ | |
6850 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 6851 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6852 | |
6853 | /* RXON Timing */ | |
bb8c093b CH |
6854 | memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd)); |
6855 | iwl3945_setup_rxon_timing(priv); | |
6856 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING, | |
b481de9c ZY |
6857 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
6858 | if (rc) | |
6859 | IWL_WARNING("REPLY_RXON_TIMING failed - " | |
6860 | "Attempting to continue.\n"); | |
6861 | ||
6862 | /* FIXME: what should be the assoc_id for AP? */ | |
6863 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
6864 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
6865 | priv->staging_rxon.flags |= | |
6866 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
6867 | else | |
6868 | priv->staging_rxon.flags &= | |
6869 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
6870 | ||
6871 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
6872 | if (priv->assoc_capability & | |
6873 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
6874 | priv->staging_rxon.flags |= | |
6875 | RXON_FLG_SHORT_SLOT_MSK; | |
6876 | else | |
6877 | priv->staging_rxon.flags &= | |
6878 | ~RXON_FLG_SHORT_SLOT_MSK; | |
6879 | ||
6880 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) | |
6881 | priv->staging_rxon.flags &= | |
6882 | ~RXON_FLG_SHORT_SLOT_MSK; | |
6883 | } | |
6884 | /* restore RXON assoc */ | |
6885 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
bb8c093b CH |
6886 | iwl3945_commit_rxon(priv); |
6887 | iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0); | |
556f8db7 | 6888 | } |
bb8c093b | 6889 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
6890 | |
6891 | /* FIXME - we need to add code here to detect a totally new | |
6892 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
6893 | * clear sta table, add BCAST sta... */ | |
6894 | } | |
6895 | ||
32bfd35d JB |
6896 | static int iwl3945_mac_config_interface(struct ieee80211_hw *hw, |
6897 | struct ieee80211_vif *vif, | |
b481de9c ZY |
6898 | struct ieee80211_if_conf *conf) |
6899 | { | |
bb8c093b | 6900 | struct iwl3945_priv *priv = hw->priv; |
0795af57 | 6901 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
6902 | unsigned long flags; |
6903 | int rc; | |
6904 | ||
6905 | if (conf == NULL) | |
6906 | return -EIO; | |
6907 | ||
b716bb91 EG |
6908 | if (priv->vif != vif) { |
6909 | IWL_DEBUG_MAC80211("leave - priv->vif != vif\n"); | |
6910 | mutex_unlock(&priv->mutex); | |
6911 | return 0; | |
6912 | } | |
6913 | ||
4150c572 JB |
6914 | /* XXX: this MUST use conf->mac_addr */ |
6915 | ||
b481de9c ZY |
6916 | if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) && |
6917 | (!conf->beacon || !conf->ssid_len)) { | |
6918 | IWL_DEBUG_MAC80211 | |
6919 | ("Leaving in AP mode because HostAPD is not ready.\n"); | |
6920 | return 0; | |
6921 | } | |
6922 | ||
5a66926a ZY |
6923 | if (!iwl3945_is_alive(priv)) |
6924 | return -EAGAIN; | |
6925 | ||
b481de9c ZY |
6926 | mutex_lock(&priv->mutex); |
6927 | ||
b481de9c | 6928 | if (conf->bssid) |
0795af57 JP |
6929 | IWL_DEBUG_MAC80211("bssid: %s\n", |
6930 | print_mac(mac, conf->bssid)); | |
b481de9c | 6931 | |
4150c572 JB |
6932 | /* |
6933 | * very dubious code was here; the probe filtering flag is never set: | |
6934 | * | |
b481de9c ZY |
6935 | if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) && |
6936 | !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) { | |
4150c572 | 6937 | */ |
b481de9c ZY |
6938 | |
6939 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | |
6940 | if (!conf->bssid) { | |
6941 | conf->bssid = priv->mac_addr; | |
6942 | memcpy(priv->bssid, priv->mac_addr, ETH_ALEN); | |
0795af57 JP |
6943 | IWL_DEBUG_MAC80211("bssid was set to: %s\n", |
6944 | print_mac(mac, conf->bssid)); | |
b481de9c ZY |
6945 | } |
6946 | if (priv->ibss_beacon) | |
6947 | dev_kfree_skb(priv->ibss_beacon); | |
6948 | ||
6949 | priv->ibss_beacon = conf->beacon; | |
6950 | } | |
6951 | ||
fde3571f MA |
6952 | if (iwl3945_is_rfkill(priv)) |
6953 | goto done; | |
6954 | ||
b481de9c ZY |
6955 | if (conf->bssid && !is_zero_ether_addr(conf->bssid) && |
6956 | !is_multicast_ether_addr(conf->bssid)) { | |
6957 | /* If there is currently a HW scan going on in the background | |
6958 | * then we need to cancel it else the RXON below will fail. */ | |
bb8c093b | 6959 | if (iwl3945_scan_cancel_timeout(priv, 100)) { |
b481de9c ZY |
6960 | IWL_WARNING("Aborted scan still in progress " |
6961 | "after 100ms\n"); | |
6962 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
6963 | mutex_unlock(&priv->mutex); | |
6964 | return -EAGAIN; | |
6965 | } | |
6966 | memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN); | |
6967 | ||
6968 | /* TODO: Audit driver for usage of these members and see | |
6969 | * if mac80211 deprecates them (priv->bssid looks like it | |
6970 | * shouldn't be there, but I haven't scanned the IBSS code | |
6971 | * to verify) - jpk */ | |
6972 | memcpy(priv->bssid, conf->bssid, ETH_ALEN); | |
6973 | ||
6974 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) | |
bb8c093b | 6975 | iwl3945_config_ap(priv); |
b481de9c | 6976 | else { |
bb8c093b | 6977 | rc = iwl3945_commit_rxon(priv); |
b481de9c | 6978 | if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc) |
bb8c093b | 6979 | iwl3945_add_station(priv, |
556f8db7 | 6980 | priv->active_rxon.bssid_addr, 1, 0); |
b481de9c ZY |
6981 | } |
6982 | ||
6983 | } else { | |
bb8c093b | 6984 | iwl3945_scan_cancel_timeout(priv, 100); |
b481de9c | 6985 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 6986 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6987 | } |
6988 | ||
fde3571f | 6989 | done: |
b481de9c ZY |
6990 | spin_lock_irqsave(&priv->lock, flags); |
6991 | if (!conf->ssid_len) | |
6992 | memset(priv->essid, 0, IW_ESSID_MAX_SIZE); | |
6993 | else | |
6994 | memcpy(priv->essid, conf->ssid, conf->ssid_len); | |
6995 | ||
6996 | priv->essid_len = conf->ssid_len; | |
6997 | spin_unlock_irqrestore(&priv->lock, flags); | |
6998 | ||
6999 | IWL_DEBUG_MAC80211("leave\n"); | |
7000 | mutex_unlock(&priv->mutex); | |
7001 | ||
7002 | return 0; | |
7003 | } | |
7004 | ||
bb8c093b | 7005 | static void iwl3945_configure_filter(struct ieee80211_hw *hw, |
4150c572 JB |
7006 | unsigned int changed_flags, |
7007 | unsigned int *total_flags, | |
7008 | int mc_count, struct dev_addr_list *mc_list) | |
7009 | { | |
7010 | /* | |
7011 | * XXX: dummy | |
bb8c093b | 7012 | * see also iwl3945_connection_init_rx_config |
4150c572 JB |
7013 | */ |
7014 | *total_flags = 0; | |
7015 | } | |
7016 | ||
bb8c093b | 7017 | static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
7018 | struct ieee80211_if_init_conf *conf) |
7019 | { | |
bb8c093b | 7020 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7021 | |
7022 | IWL_DEBUG_MAC80211("enter\n"); | |
7023 | ||
7024 | mutex_lock(&priv->mutex); | |
6ef89d0a | 7025 | |
fde3571f MA |
7026 | if (iwl3945_is_ready_rf(priv)) { |
7027 | iwl3945_scan_cancel_timeout(priv, 100); | |
7028 | cancel_delayed_work(&priv->post_associate); | |
7029 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
7030 | iwl3945_commit_rxon(priv); | |
7031 | } | |
32bfd35d JB |
7032 | if (priv->vif == conf->vif) { |
7033 | priv->vif = NULL; | |
b481de9c ZY |
7034 | memset(priv->bssid, 0, ETH_ALEN); |
7035 | memset(priv->essid, 0, IW_ESSID_MAX_SIZE); | |
7036 | priv->essid_len = 0; | |
7037 | } | |
7038 | mutex_unlock(&priv->mutex); | |
7039 | ||
7040 | IWL_DEBUG_MAC80211("leave\n"); | |
b481de9c ZY |
7041 | } |
7042 | ||
bb8c093b | 7043 | static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len) |
b481de9c ZY |
7044 | { |
7045 | int rc = 0; | |
7046 | unsigned long flags; | |
bb8c093b | 7047 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7048 | |
7049 | IWL_DEBUG_MAC80211("enter\n"); | |
7050 | ||
15e869d8 | 7051 | mutex_lock(&priv->mutex); |
b481de9c ZY |
7052 | spin_lock_irqsave(&priv->lock, flags); |
7053 | ||
bb8c093b | 7054 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
7055 | rc = -EIO; |
7056 | IWL_DEBUG_MAC80211("leave - not ready or exit pending\n"); | |
7057 | goto out_unlock; | |
7058 | } | |
7059 | ||
7060 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */ | |
7061 | rc = -EIO; | |
7062 | IWL_ERROR("ERROR: APs don't scan\n"); | |
7063 | goto out_unlock; | |
7064 | } | |
7065 | ||
7878a5a4 MA |
7066 | /* we don't schedule scan within next_scan_jiffies period */ |
7067 | if (priv->next_scan_jiffies && | |
7068 | time_after(priv->next_scan_jiffies, jiffies)) { | |
7069 | rc = -EAGAIN; | |
7070 | goto out_unlock; | |
7071 | } | |
b481de9c | 7072 | /* if we just finished scan ask for delay */ |
7878a5a4 MA |
7073 | if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies + |
7074 | IWL_DELAY_NEXT_SCAN, jiffies)) { | |
b481de9c ZY |
7075 | rc = -EAGAIN; |
7076 | goto out_unlock; | |
7077 | } | |
7078 | if (len) { | |
7878a5a4 | 7079 | IWL_DEBUG_SCAN("direct scan for %s [%d]\n ", |
bb8c093b | 7080 | iwl3945_escape_essid(ssid, len), (int)len); |
b481de9c ZY |
7081 | |
7082 | priv->one_direct_scan = 1; | |
7083 | priv->direct_ssid_len = (u8) | |
7084 | min((u8) len, (u8) IW_ESSID_MAX_SIZE); | |
7085 | memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len); | |
6ef89d0a MA |
7086 | } else |
7087 | priv->one_direct_scan = 0; | |
b481de9c | 7088 | |
bb8c093b | 7089 | rc = iwl3945_scan_initiate(priv); |
b481de9c ZY |
7090 | |
7091 | IWL_DEBUG_MAC80211("leave\n"); | |
7092 | ||
7093 | out_unlock: | |
7094 | spin_unlock_irqrestore(&priv->lock, flags); | |
15e869d8 | 7095 | mutex_unlock(&priv->mutex); |
b481de9c ZY |
7096 | |
7097 | return rc; | |
7098 | } | |
7099 | ||
bb8c093b | 7100 | static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
b481de9c ZY |
7101 | const u8 *local_addr, const u8 *addr, |
7102 | struct ieee80211_key_conf *key) | |
7103 | { | |
bb8c093b | 7104 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7105 | int rc = 0; |
7106 | u8 sta_id; | |
7107 | ||
7108 | IWL_DEBUG_MAC80211("enter\n"); | |
7109 | ||
bb8c093b | 7110 | if (!iwl3945_param_hwcrypto) { |
b481de9c ZY |
7111 | IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n"); |
7112 | return -EOPNOTSUPP; | |
7113 | } | |
7114 | ||
7115 | if (is_zero_ether_addr(addr)) | |
7116 | /* only support pairwise keys */ | |
7117 | return -EOPNOTSUPP; | |
7118 | ||
bb8c093b | 7119 | sta_id = iwl3945_hw_find_station(priv, addr); |
b481de9c | 7120 | if (sta_id == IWL_INVALID_STATION) { |
0795af57 JP |
7121 | DECLARE_MAC_BUF(mac); |
7122 | ||
7123 | IWL_DEBUG_MAC80211("leave - %s not in station map.\n", | |
7124 | print_mac(mac, addr)); | |
b481de9c ZY |
7125 | return -EINVAL; |
7126 | } | |
7127 | ||
7128 | mutex_lock(&priv->mutex); | |
7129 | ||
bb8c093b | 7130 | iwl3945_scan_cancel_timeout(priv, 100); |
15e869d8 | 7131 | |
b481de9c ZY |
7132 | switch (cmd) { |
7133 | case SET_KEY: | |
bb8c093b | 7134 | rc = iwl3945_update_sta_key_info(priv, key, sta_id); |
b481de9c | 7135 | if (!rc) { |
bb8c093b CH |
7136 | iwl3945_set_rxon_hwcrypto(priv, 1); |
7137 | iwl3945_commit_rxon(priv); | |
b481de9c ZY |
7138 | key->hw_key_idx = sta_id; |
7139 | IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n"); | |
7140 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
7141 | } | |
7142 | break; | |
7143 | case DISABLE_KEY: | |
bb8c093b | 7144 | rc = iwl3945_clear_sta_key_info(priv, sta_id); |
b481de9c | 7145 | if (!rc) { |
bb8c093b CH |
7146 | iwl3945_set_rxon_hwcrypto(priv, 0); |
7147 | iwl3945_commit_rxon(priv); | |
b481de9c ZY |
7148 | IWL_DEBUG_MAC80211("disable hwcrypto key\n"); |
7149 | } | |
7150 | break; | |
7151 | default: | |
7152 | rc = -EINVAL; | |
7153 | } | |
7154 | ||
7155 | IWL_DEBUG_MAC80211("leave\n"); | |
7156 | mutex_unlock(&priv->mutex); | |
7157 | ||
7158 | return rc; | |
7159 | } | |
7160 | ||
bb8c093b | 7161 | static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue, |
b481de9c ZY |
7162 | const struct ieee80211_tx_queue_params *params) |
7163 | { | |
bb8c093b | 7164 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7165 | unsigned long flags; |
7166 | int q; | |
b481de9c ZY |
7167 | |
7168 | IWL_DEBUG_MAC80211("enter\n"); | |
7169 | ||
bb8c093b | 7170 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
7171 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7172 | return -EIO; | |
7173 | } | |
7174 | ||
7175 | if (queue >= AC_NUM) { | |
7176 | IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue); | |
7177 | return 0; | |
7178 | } | |
7179 | ||
b481de9c ZY |
7180 | if (!priv->qos_data.qos_enable) { |
7181 | priv->qos_data.qos_active = 0; | |
7182 | IWL_DEBUG_MAC80211("leave - qos not enabled\n"); | |
7183 | return 0; | |
7184 | } | |
7185 | q = AC_NUM - 1 - queue; | |
7186 | ||
7187 | spin_lock_irqsave(&priv->lock, flags); | |
7188 | ||
7189 | priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min); | |
7190 | priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max); | |
7191 | priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; | |
7192 | priv->qos_data.def_qos_parm.ac[q].edca_txop = | |
3330d7be | 7193 | cpu_to_le16((params->txop * 32)); |
b481de9c ZY |
7194 | |
7195 | priv->qos_data.def_qos_parm.ac[q].reserved1 = 0; | |
7196 | priv->qos_data.qos_active = 1; | |
7197 | ||
7198 | spin_unlock_irqrestore(&priv->lock, flags); | |
7199 | ||
7200 | mutex_lock(&priv->mutex); | |
7201 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) | |
bb8c093b CH |
7202 | iwl3945_activate_qos(priv, 1); |
7203 | else if (priv->assoc_id && iwl3945_is_associated(priv)) | |
7204 | iwl3945_activate_qos(priv, 0); | |
b481de9c ZY |
7205 | |
7206 | mutex_unlock(&priv->mutex); | |
7207 | ||
b481de9c ZY |
7208 | IWL_DEBUG_MAC80211("leave\n"); |
7209 | return 0; | |
7210 | } | |
7211 | ||
bb8c093b | 7212 | static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
7213 | struct ieee80211_tx_queue_stats *stats) |
7214 | { | |
bb8c093b | 7215 | struct iwl3945_priv *priv = hw->priv; |
b481de9c | 7216 | int i, avail; |
bb8c093b CH |
7217 | struct iwl3945_tx_queue *txq; |
7218 | struct iwl3945_queue *q; | |
b481de9c ZY |
7219 | unsigned long flags; |
7220 | ||
7221 | IWL_DEBUG_MAC80211("enter\n"); | |
7222 | ||
bb8c093b | 7223 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
7224 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7225 | return -EIO; | |
7226 | } | |
7227 | ||
7228 | spin_lock_irqsave(&priv->lock, flags); | |
7229 | ||
7230 | for (i = 0; i < AC_NUM; i++) { | |
7231 | txq = &priv->txq[i]; | |
7232 | q = &txq->q; | |
bb8c093b | 7233 | avail = iwl3945_queue_space(q); |
b481de9c ZY |
7234 | |
7235 | stats->data[i].len = q->n_window - avail; | |
7236 | stats->data[i].limit = q->n_window - q->high_mark; | |
7237 | stats->data[i].count = q->n_window; | |
7238 | ||
7239 | } | |
7240 | spin_unlock_irqrestore(&priv->lock, flags); | |
7241 | ||
7242 | IWL_DEBUG_MAC80211("leave\n"); | |
7243 | ||
7244 | return 0; | |
7245 | } | |
7246 | ||
bb8c093b | 7247 | static int iwl3945_mac_get_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
7248 | struct ieee80211_low_level_stats *stats) |
7249 | { | |
7250 | IWL_DEBUG_MAC80211("enter\n"); | |
7251 | IWL_DEBUG_MAC80211("leave\n"); | |
7252 | ||
7253 | return 0; | |
7254 | } | |
7255 | ||
bb8c093b | 7256 | static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw) |
b481de9c ZY |
7257 | { |
7258 | IWL_DEBUG_MAC80211("enter\n"); | |
7259 | IWL_DEBUG_MAC80211("leave\n"); | |
7260 | ||
7261 | return 0; | |
7262 | } | |
7263 | ||
bb8c093b | 7264 | static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw) |
b481de9c | 7265 | { |
bb8c093b | 7266 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7267 | unsigned long flags; |
7268 | ||
7269 | mutex_lock(&priv->mutex); | |
7270 | IWL_DEBUG_MAC80211("enter\n"); | |
7271 | ||
bb8c093b | 7272 | iwl3945_reset_qos(priv); |
292ae174 | 7273 | |
b481de9c ZY |
7274 | cancel_delayed_work(&priv->post_associate); |
7275 | ||
7276 | spin_lock_irqsave(&priv->lock, flags); | |
7277 | priv->assoc_id = 0; | |
7278 | priv->assoc_capability = 0; | |
7279 | priv->call_post_assoc_from_beacon = 0; | |
7280 | ||
7281 | /* new association get rid of ibss beacon skb */ | |
7282 | if (priv->ibss_beacon) | |
7283 | dev_kfree_skb(priv->ibss_beacon); | |
7284 | ||
7285 | priv->ibss_beacon = NULL; | |
7286 | ||
7287 | priv->beacon_int = priv->hw->conf.beacon_int; | |
7288 | priv->timestamp1 = 0; | |
7289 | priv->timestamp0 = 0; | |
7290 | if ((priv->iw_mode == IEEE80211_IF_TYPE_STA)) | |
7291 | priv->beacon_int = 0; | |
7292 | ||
7293 | spin_unlock_irqrestore(&priv->lock, flags); | |
7294 | ||
fde3571f MA |
7295 | if (!iwl3945_is_ready_rf(priv)) { |
7296 | IWL_DEBUG_MAC80211("leave - not ready\n"); | |
7297 | mutex_unlock(&priv->mutex); | |
7298 | return; | |
7299 | } | |
7300 | ||
15e869d8 MA |
7301 | /* we are restarting association process |
7302 | * clear RXON_FILTER_ASSOC_MSK bit | |
7303 | */ | |
7304 | if (priv->iw_mode != IEEE80211_IF_TYPE_AP) { | |
bb8c093b | 7305 | iwl3945_scan_cancel_timeout(priv, 100); |
15e869d8 | 7306 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 7307 | iwl3945_commit_rxon(priv); |
15e869d8 MA |
7308 | } |
7309 | ||
b481de9c ZY |
7310 | /* Per mac80211.h: This is only used in IBSS mode... */ |
7311 | if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) { | |
15e869d8 | 7312 | |
b481de9c ZY |
7313 | IWL_DEBUG_MAC80211("leave - not in IBSS\n"); |
7314 | mutex_unlock(&priv->mutex); | |
7315 | return; | |
b481de9c ZY |
7316 | } |
7317 | ||
7318 | priv->only_active_channel = 0; | |
7319 | ||
bb8c093b | 7320 | iwl3945_set_rate(priv); |
b481de9c ZY |
7321 | |
7322 | mutex_unlock(&priv->mutex); | |
7323 | ||
7324 | IWL_DEBUG_MAC80211("leave\n"); | |
7325 | ||
7326 | } | |
7327 | ||
bb8c093b | 7328 | static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, |
b481de9c ZY |
7329 | struct ieee80211_tx_control *control) |
7330 | { | |
bb8c093b | 7331 | struct iwl3945_priv *priv = hw->priv; |
b481de9c ZY |
7332 | unsigned long flags; |
7333 | ||
7334 | mutex_lock(&priv->mutex); | |
7335 | IWL_DEBUG_MAC80211("enter\n"); | |
7336 | ||
bb8c093b | 7337 | if (!iwl3945_is_ready_rf(priv)) { |
b481de9c ZY |
7338 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
7339 | mutex_unlock(&priv->mutex); | |
7340 | return -EIO; | |
7341 | } | |
7342 | ||
7343 | if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) { | |
7344 | IWL_DEBUG_MAC80211("leave - not IBSS\n"); | |
7345 | mutex_unlock(&priv->mutex); | |
7346 | return -EIO; | |
7347 | } | |
7348 | ||
7349 | spin_lock_irqsave(&priv->lock, flags); | |
7350 | ||
7351 | if (priv->ibss_beacon) | |
7352 | dev_kfree_skb(priv->ibss_beacon); | |
7353 | ||
7354 | priv->ibss_beacon = skb; | |
7355 | ||
7356 | priv->assoc_id = 0; | |
7357 | ||
7358 | IWL_DEBUG_MAC80211("leave\n"); | |
7359 | spin_unlock_irqrestore(&priv->lock, flags); | |
7360 | ||
bb8c093b | 7361 | iwl3945_reset_qos(priv); |
b481de9c ZY |
7362 | |
7363 | queue_work(priv->workqueue, &priv->post_associate.work); | |
7364 | ||
7365 | mutex_unlock(&priv->mutex); | |
7366 | ||
7367 | return 0; | |
7368 | } | |
7369 | ||
7370 | /***************************************************************************** | |
7371 | * | |
7372 | * sysfs attributes | |
7373 | * | |
7374 | *****************************************************************************/ | |
7375 | ||
c8b0e6e1 | 7376 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
7377 | |
7378 | /* | |
7379 | * The following adds a new attribute to the sysfs representation | |
7380 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
7381 | * used for controlling the debug level. | |
7382 | * | |
7383 | * See the level definitions in iwl for details. | |
7384 | */ | |
7385 | ||
7386 | static ssize_t show_debug_level(struct device_driver *d, char *buf) | |
7387 | { | |
bb8c093b | 7388 | return sprintf(buf, "0x%08X\n", iwl3945_debug_level); |
b481de9c ZY |
7389 | } |
7390 | static ssize_t store_debug_level(struct device_driver *d, | |
7391 | const char *buf, size_t count) | |
7392 | { | |
7393 | char *p = (char *)buf; | |
7394 | u32 val; | |
7395 | ||
7396 | val = simple_strtoul(p, &p, 0); | |
7397 | if (p == buf) | |
7398 | printk(KERN_INFO DRV_NAME | |
7399 | ": %s is not in hex or decimal form.\n", buf); | |
7400 | else | |
bb8c093b | 7401 | iwl3945_debug_level = val; |
b481de9c ZY |
7402 | |
7403 | return strnlen(buf, count); | |
7404 | } | |
7405 | ||
7406 | static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO, | |
7407 | show_debug_level, store_debug_level); | |
7408 | ||
c8b0e6e1 | 7409 | #endif /* CONFIG_IWL3945_DEBUG */ |
b481de9c ZY |
7410 | |
7411 | static ssize_t show_rf_kill(struct device *d, | |
7412 | struct device_attribute *attr, char *buf) | |
7413 | { | |
7414 | /* | |
7415 | * 0 - RF kill not enabled | |
7416 | * 1 - SW based RF kill active (sysfs) | |
7417 | * 2 - HW based RF kill active | |
7418 | * 3 - Both HW and SW based RF kill active | |
7419 | */ | |
bb8c093b | 7420 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7421 | int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) | |
7422 | (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0); | |
7423 | ||
7424 | return sprintf(buf, "%i\n", val); | |
7425 | } | |
7426 | ||
7427 | static ssize_t store_rf_kill(struct device *d, | |
7428 | struct device_attribute *attr, | |
7429 | const char *buf, size_t count) | |
7430 | { | |
bb8c093b | 7431 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7432 | |
7433 | mutex_lock(&priv->mutex); | |
bb8c093b | 7434 | iwl3945_radio_kill_sw(priv, buf[0] == '1'); |
b481de9c ZY |
7435 | mutex_unlock(&priv->mutex); |
7436 | ||
7437 | return count; | |
7438 | } | |
7439 | ||
7440 | static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill); | |
7441 | ||
7442 | static ssize_t show_temperature(struct device *d, | |
7443 | struct device_attribute *attr, char *buf) | |
7444 | { | |
bb8c093b | 7445 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c | 7446 | |
bb8c093b | 7447 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
7448 | return -EAGAIN; |
7449 | ||
bb8c093b | 7450 | return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv)); |
b481de9c ZY |
7451 | } |
7452 | ||
7453 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
7454 | ||
7455 | static ssize_t show_rs_window(struct device *d, | |
7456 | struct device_attribute *attr, | |
7457 | char *buf) | |
7458 | { | |
bb8c093b CH |
7459 | struct iwl3945_priv *priv = d->driver_data; |
7460 | return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID); | |
b481de9c ZY |
7461 | } |
7462 | static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL); | |
7463 | ||
7464 | static ssize_t show_tx_power(struct device *d, | |
7465 | struct device_attribute *attr, char *buf) | |
7466 | { | |
bb8c093b | 7467 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7468 | return sprintf(buf, "%d\n", priv->user_txpower_limit); |
7469 | } | |
7470 | ||
7471 | static ssize_t store_tx_power(struct device *d, | |
7472 | struct device_attribute *attr, | |
7473 | const char *buf, size_t count) | |
7474 | { | |
bb8c093b | 7475 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7476 | char *p = (char *)buf; |
7477 | u32 val; | |
7478 | ||
7479 | val = simple_strtoul(p, &p, 10); | |
7480 | if (p == buf) | |
7481 | printk(KERN_INFO DRV_NAME | |
7482 | ": %s is not in decimal form.\n", buf); | |
7483 | else | |
bb8c093b | 7484 | iwl3945_hw_reg_set_txpower(priv, val); |
b481de9c ZY |
7485 | |
7486 | return count; | |
7487 | } | |
7488 | ||
7489 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
7490 | ||
7491 | static ssize_t show_flags(struct device *d, | |
7492 | struct device_attribute *attr, char *buf) | |
7493 | { | |
bb8c093b | 7494 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7495 | |
7496 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); | |
7497 | } | |
7498 | ||
7499 | static ssize_t store_flags(struct device *d, | |
7500 | struct device_attribute *attr, | |
7501 | const char *buf, size_t count) | |
7502 | { | |
bb8c093b | 7503 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7504 | u32 flags = simple_strtoul(buf, NULL, 0); |
7505 | ||
7506 | mutex_lock(&priv->mutex); | |
7507 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { | |
7508 | /* Cancel any currently running scans... */ | |
bb8c093b | 7509 | if (iwl3945_scan_cancel_timeout(priv, 100)) |
b481de9c ZY |
7510 | IWL_WARNING("Could not cancel scan.\n"); |
7511 | else { | |
7512 | IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n", | |
7513 | flags); | |
7514 | priv->staging_rxon.flags = cpu_to_le32(flags); | |
bb8c093b | 7515 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
7516 | } |
7517 | } | |
7518 | mutex_unlock(&priv->mutex); | |
7519 | ||
7520 | return count; | |
7521 | } | |
7522 | ||
7523 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
7524 | ||
7525 | static ssize_t show_filter_flags(struct device *d, | |
7526 | struct device_attribute *attr, char *buf) | |
7527 | { | |
bb8c093b | 7528 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7529 | |
7530 | return sprintf(buf, "0x%04X\n", | |
7531 | le32_to_cpu(priv->active_rxon.filter_flags)); | |
7532 | } | |
7533 | ||
7534 | static ssize_t store_filter_flags(struct device *d, | |
7535 | struct device_attribute *attr, | |
7536 | const char *buf, size_t count) | |
7537 | { | |
bb8c093b | 7538 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
b481de9c ZY |
7539 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
7540 | ||
7541 | mutex_lock(&priv->mutex); | |
7542 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { | |
7543 | /* Cancel any currently running scans... */ | |
bb8c093b | 7544 | if (iwl3945_scan_cancel_timeout(priv, 100)) |
b481de9c ZY |
7545 | IWL_WARNING("Could not cancel scan.\n"); |
7546 | else { | |
7547 | IWL_DEBUG_INFO("Committing rxon.filter_flags = " | |
7548 | "0x%04X\n", filter_flags); | |
7549 | priv->staging_rxon.filter_flags = | |
7550 | cpu_to_le32(filter_flags); | |
bb8c093b | 7551 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
7552 | } |
7553 | } | |
7554 | mutex_unlock(&priv->mutex); | |
7555 | ||
7556 | return count; | |
7557 | } | |
7558 | ||
7559 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
7560 | store_filter_flags); | |
7561 | ||
c8b0e6e1 | 7562 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
7563 | |
7564 | static ssize_t show_measurement(struct device *d, | |
7565 | struct device_attribute *attr, char *buf) | |
7566 | { | |
bb8c093b CH |
7567 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
7568 | struct iwl3945_spectrum_notification measure_report; | |
b481de9c ZY |
7569 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
7570 | u8 *data = (u8 *) & measure_report; | |
7571 | unsigned long flags; | |
7572 | ||
7573 | spin_lock_irqsave(&priv->lock, flags); | |
7574 | if (!(priv->measurement_status & MEASUREMENT_READY)) { | |
7575 | spin_unlock_irqrestore(&priv->lock, flags); | |
7576 | return 0; | |
7577 | } | |
7578 | memcpy(&measure_report, &priv->measure_report, size); | |
7579 | priv->measurement_status = 0; | |
7580 | spin_unlock_irqrestore(&priv->lock, flags); | |
7581 | ||
7582 | while (size && (PAGE_SIZE - len)) { | |
7583 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7584 | PAGE_SIZE - len, 1); | |
7585 | len = strlen(buf); | |
7586 | if (PAGE_SIZE - len) | |
7587 | buf[len++] = '\n'; | |
7588 | ||
7589 | ofs += 16; | |
7590 | size -= min(size, 16U); | |
7591 | } | |
7592 | ||
7593 | return len; | |
7594 | } | |
7595 | ||
7596 | static ssize_t store_measurement(struct device *d, | |
7597 | struct device_attribute *attr, | |
7598 | const char *buf, size_t count) | |
7599 | { | |
bb8c093b | 7600 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7601 | struct ieee80211_measurement_params params = { |
7602 | .channel = le16_to_cpu(priv->active_rxon.channel), | |
7603 | .start_time = cpu_to_le64(priv->last_tsf), | |
7604 | .duration = cpu_to_le16(1), | |
7605 | }; | |
7606 | u8 type = IWL_MEASURE_BASIC; | |
7607 | u8 buffer[32]; | |
7608 | u8 channel; | |
7609 | ||
7610 | if (count) { | |
7611 | char *p = buffer; | |
7612 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
7613 | channel = simple_strtoul(p, NULL, 0); | |
7614 | if (channel) | |
7615 | params.channel = channel; | |
7616 | ||
7617 | p = buffer; | |
7618 | while (*p && *p != ' ') | |
7619 | p++; | |
7620 | if (*p) | |
7621 | type = simple_strtoul(p + 1, NULL, 0); | |
7622 | } | |
7623 | ||
7624 | IWL_DEBUG_INFO("Invoking measurement of type %d on " | |
7625 | "channel %d (for '%s')\n", type, params.channel, buf); | |
bb8c093b | 7626 | iwl3945_get_measurement(priv, ¶ms, type); |
b481de9c ZY |
7627 | |
7628 | return count; | |
7629 | } | |
7630 | ||
7631 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
7632 | show_measurement, store_measurement); | |
c8b0e6e1 | 7633 | #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */ |
b481de9c | 7634 | |
b481de9c ZY |
7635 | static ssize_t store_retry_rate(struct device *d, |
7636 | struct device_attribute *attr, | |
7637 | const char *buf, size_t count) | |
7638 | { | |
bb8c093b | 7639 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7640 | |
7641 | priv->retry_rate = simple_strtoul(buf, NULL, 0); | |
7642 | if (priv->retry_rate <= 0) | |
7643 | priv->retry_rate = 1; | |
7644 | ||
7645 | return count; | |
7646 | } | |
7647 | ||
7648 | static ssize_t show_retry_rate(struct device *d, | |
7649 | struct device_attribute *attr, char *buf) | |
7650 | { | |
bb8c093b | 7651 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7652 | return sprintf(buf, "%d", priv->retry_rate); |
7653 | } | |
7654 | ||
7655 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate, | |
7656 | store_retry_rate); | |
7657 | ||
7658 | static ssize_t store_power_level(struct device *d, | |
7659 | struct device_attribute *attr, | |
7660 | const char *buf, size_t count) | |
7661 | { | |
bb8c093b | 7662 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7663 | int rc; |
7664 | int mode; | |
7665 | ||
7666 | mode = simple_strtoul(buf, NULL, 0); | |
7667 | mutex_lock(&priv->mutex); | |
7668 | ||
bb8c093b | 7669 | if (!iwl3945_is_ready(priv)) { |
b481de9c ZY |
7670 | rc = -EAGAIN; |
7671 | goto out; | |
7672 | } | |
7673 | ||
7674 | if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC)) | |
7675 | mode = IWL_POWER_AC; | |
7676 | else | |
7677 | mode |= IWL_POWER_ENABLED; | |
7678 | ||
7679 | if (mode != priv->power_mode) { | |
bb8c093b | 7680 | rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode)); |
b481de9c ZY |
7681 | if (rc) { |
7682 | IWL_DEBUG_MAC80211("failed setting power mode.\n"); | |
7683 | goto out; | |
7684 | } | |
7685 | priv->power_mode = mode; | |
7686 | } | |
7687 | ||
7688 | rc = count; | |
7689 | ||
7690 | out: | |
7691 | mutex_unlock(&priv->mutex); | |
7692 | return rc; | |
7693 | } | |
7694 | ||
7695 | #define MAX_WX_STRING 80 | |
7696 | ||
7697 | /* Values are in microsecond */ | |
7698 | static const s32 timeout_duration[] = { | |
7699 | 350000, | |
7700 | 250000, | |
7701 | 75000, | |
7702 | 37000, | |
7703 | 25000, | |
7704 | }; | |
7705 | static const s32 period_duration[] = { | |
7706 | 400000, | |
7707 | 700000, | |
7708 | 1000000, | |
7709 | 1000000, | |
7710 | 1000000 | |
7711 | }; | |
7712 | ||
7713 | static ssize_t show_power_level(struct device *d, | |
7714 | struct device_attribute *attr, char *buf) | |
7715 | { | |
bb8c093b | 7716 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7717 | int level = IWL_POWER_LEVEL(priv->power_mode); |
7718 | char *p = buf; | |
7719 | ||
7720 | p += sprintf(p, "%d ", level); | |
7721 | switch (level) { | |
7722 | case IWL_POWER_MODE_CAM: | |
7723 | case IWL_POWER_AC: | |
7724 | p += sprintf(p, "(AC)"); | |
7725 | break; | |
7726 | case IWL_POWER_BATTERY: | |
7727 | p += sprintf(p, "(BATTERY)"); | |
7728 | break; | |
7729 | default: | |
7730 | p += sprintf(p, | |
7731 | "(Timeout %dms, Period %dms)", | |
7732 | timeout_duration[level - 1] / 1000, | |
7733 | period_duration[level - 1] / 1000); | |
7734 | } | |
7735 | ||
7736 | if (!(priv->power_mode & IWL_POWER_ENABLED)) | |
7737 | p += sprintf(p, " OFF\n"); | |
7738 | else | |
7739 | p += sprintf(p, " \n"); | |
7740 | ||
7741 | return (p - buf + 1); | |
7742 | ||
7743 | } | |
7744 | ||
7745 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, | |
7746 | store_power_level); | |
7747 | ||
7748 | static ssize_t show_channels(struct device *d, | |
7749 | struct device_attribute *attr, char *buf) | |
7750 | { | |
8318d78a JB |
7751 | /* all this shit doesn't belong into sysfs anyway */ |
7752 | return 0; | |
b481de9c ZY |
7753 | } |
7754 | ||
7755 | static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); | |
7756 | ||
7757 | static ssize_t show_statistics(struct device *d, | |
7758 | struct device_attribute *attr, char *buf) | |
7759 | { | |
bb8c093b CH |
7760 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
7761 | u32 size = sizeof(struct iwl3945_notif_statistics); | |
b481de9c ZY |
7762 | u32 len = 0, ofs = 0; |
7763 | u8 *data = (u8 *) & priv->statistics; | |
7764 | int rc = 0; | |
7765 | ||
bb8c093b | 7766 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
7767 | return -EAGAIN; |
7768 | ||
7769 | mutex_lock(&priv->mutex); | |
bb8c093b | 7770 | rc = iwl3945_send_statistics_request(priv); |
b481de9c ZY |
7771 | mutex_unlock(&priv->mutex); |
7772 | ||
7773 | if (rc) { | |
7774 | len = sprintf(buf, | |
7775 | "Error sending statistics request: 0x%08X\n", rc); | |
7776 | return len; | |
7777 | } | |
7778 | ||
7779 | while (size && (PAGE_SIZE - len)) { | |
7780 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7781 | PAGE_SIZE - len, 1); | |
7782 | len = strlen(buf); | |
7783 | if (PAGE_SIZE - len) | |
7784 | buf[len++] = '\n'; | |
7785 | ||
7786 | ofs += 16; | |
7787 | size -= min(size, 16U); | |
7788 | } | |
7789 | ||
7790 | return len; | |
7791 | } | |
7792 | ||
7793 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
7794 | ||
7795 | static ssize_t show_antenna(struct device *d, | |
7796 | struct device_attribute *attr, char *buf) | |
7797 | { | |
bb8c093b | 7798 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c | 7799 | |
bb8c093b | 7800 | if (!iwl3945_is_alive(priv)) |
b481de9c ZY |
7801 | return -EAGAIN; |
7802 | ||
7803 | return sprintf(buf, "%d\n", priv->antenna); | |
7804 | } | |
7805 | ||
7806 | static ssize_t store_antenna(struct device *d, | |
7807 | struct device_attribute *attr, | |
7808 | const char *buf, size_t count) | |
7809 | { | |
7810 | int ant; | |
bb8c093b | 7811 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7812 | |
7813 | if (count == 0) | |
7814 | return 0; | |
7815 | ||
7816 | if (sscanf(buf, "%1i", &ant) != 1) { | |
7817 | IWL_DEBUG_INFO("not in hex or decimal form.\n"); | |
7818 | return count; | |
7819 | } | |
7820 | ||
7821 | if ((ant >= 0) && (ant <= 2)) { | |
7822 | IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant); | |
bb8c093b | 7823 | priv->antenna = (enum iwl3945_antenna)ant; |
b481de9c ZY |
7824 | } else |
7825 | IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant); | |
7826 | ||
7827 | ||
7828 | return count; | |
7829 | } | |
7830 | ||
7831 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna); | |
7832 | ||
7833 | static ssize_t show_status(struct device *d, | |
7834 | struct device_attribute *attr, char *buf) | |
7835 | { | |
bb8c093b CH |
7836 | struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data; |
7837 | if (!iwl3945_is_alive(priv)) | |
b481de9c ZY |
7838 | return -EAGAIN; |
7839 | return sprintf(buf, "0x%08x\n", (int)priv->status); | |
7840 | } | |
7841 | ||
7842 | static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); | |
7843 | ||
7844 | static ssize_t dump_error_log(struct device *d, | |
7845 | struct device_attribute *attr, | |
7846 | const char *buf, size_t count) | |
7847 | { | |
7848 | char *p = (char *)buf; | |
7849 | ||
7850 | if (p[0] == '1') | |
bb8c093b | 7851 | iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data); |
b481de9c ZY |
7852 | |
7853 | return strnlen(buf, count); | |
7854 | } | |
7855 | ||
7856 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | |
7857 | ||
7858 | static ssize_t dump_event_log(struct device *d, | |
7859 | struct device_attribute *attr, | |
7860 | const char *buf, size_t count) | |
7861 | { | |
7862 | char *p = (char *)buf; | |
7863 | ||
7864 | if (p[0] == '1') | |
bb8c093b | 7865 | iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data); |
b481de9c ZY |
7866 | |
7867 | return strnlen(buf, count); | |
7868 | } | |
7869 | ||
7870 | static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log); | |
7871 | ||
7872 | /***************************************************************************** | |
7873 | * | |
7874 | * driver setup and teardown | |
7875 | * | |
7876 | *****************************************************************************/ | |
7877 | ||
bb8c093b | 7878 | static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv) |
b481de9c ZY |
7879 | { |
7880 | priv->workqueue = create_workqueue(DRV_NAME); | |
7881 | ||
7882 | init_waitqueue_head(&priv->wait_command_queue); | |
7883 | ||
bb8c093b CH |
7884 | INIT_WORK(&priv->up, iwl3945_bg_up); |
7885 | INIT_WORK(&priv->restart, iwl3945_bg_restart); | |
7886 | INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish); | |
7887 | INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed); | |
7888 | INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan); | |
7889 | INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan); | |
7890 | INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill); | |
7891 | INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update); | |
7892 | INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate); | |
7893 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start); | |
7894 | INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start); | |
7895 | INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check); | |
7896 | ||
7897 | iwl3945_hw_setup_deferred_work(priv); | |
b481de9c ZY |
7898 | |
7899 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
bb8c093b | 7900 | iwl3945_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
7901 | } |
7902 | ||
bb8c093b | 7903 | static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv) |
b481de9c | 7904 | { |
bb8c093b | 7905 | iwl3945_hw_cancel_deferred_work(priv); |
b481de9c | 7906 | |
e47eb6ad | 7907 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
7908 | cancel_delayed_work(&priv->scan_check); |
7909 | cancel_delayed_work(&priv->alive_start); | |
7910 | cancel_delayed_work(&priv->post_associate); | |
7911 | cancel_work_sync(&priv->beacon_update); | |
7912 | } | |
7913 | ||
bb8c093b | 7914 | static struct attribute *iwl3945_sysfs_entries[] = { |
b481de9c ZY |
7915 | &dev_attr_antenna.attr, |
7916 | &dev_attr_channels.attr, | |
7917 | &dev_attr_dump_errors.attr, | |
7918 | &dev_attr_dump_events.attr, | |
7919 | &dev_attr_flags.attr, | |
7920 | &dev_attr_filter_flags.attr, | |
c8b0e6e1 | 7921 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
7922 | &dev_attr_measurement.attr, |
7923 | #endif | |
7924 | &dev_attr_power_level.attr, | |
b481de9c ZY |
7925 | &dev_attr_retry_rate.attr, |
7926 | &dev_attr_rf_kill.attr, | |
7927 | &dev_attr_rs_window.attr, | |
7928 | &dev_attr_statistics.attr, | |
7929 | &dev_attr_status.attr, | |
7930 | &dev_attr_temperature.attr, | |
b481de9c ZY |
7931 | &dev_attr_tx_power.attr, |
7932 | ||
7933 | NULL | |
7934 | }; | |
7935 | ||
bb8c093b | 7936 | static struct attribute_group iwl3945_attribute_group = { |
b481de9c | 7937 | .name = NULL, /* put in device directory */ |
bb8c093b | 7938 | .attrs = iwl3945_sysfs_entries, |
b481de9c ZY |
7939 | }; |
7940 | ||
bb8c093b CH |
7941 | static struct ieee80211_ops iwl3945_hw_ops = { |
7942 | .tx = iwl3945_mac_tx, | |
7943 | .start = iwl3945_mac_start, | |
7944 | .stop = iwl3945_mac_stop, | |
7945 | .add_interface = iwl3945_mac_add_interface, | |
7946 | .remove_interface = iwl3945_mac_remove_interface, | |
7947 | .config = iwl3945_mac_config, | |
7948 | .config_interface = iwl3945_mac_config_interface, | |
7949 | .configure_filter = iwl3945_configure_filter, | |
7950 | .set_key = iwl3945_mac_set_key, | |
7951 | .get_stats = iwl3945_mac_get_stats, | |
7952 | .get_tx_stats = iwl3945_mac_get_tx_stats, | |
7953 | .conf_tx = iwl3945_mac_conf_tx, | |
7954 | .get_tsf = iwl3945_mac_get_tsf, | |
7955 | .reset_tsf = iwl3945_mac_reset_tsf, | |
7956 | .beacon_update = iwl3945_mac_beacon_update, | |
7957 | .hw_scan = iwl3945_mac_hw_scan | |
b481de9c ZY |
7958 | }; |
7959 | ||
bb8c093b | 7960 | static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
7961 | { |
7962 | int err = 0; | |
bb8c093b | 7963 | struct iwl3945_priv *priv; |
b481de9c | 7964 | struct ieee80211_hw *hw; |
82b9a121 | 7965 | struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data); |
b481de9c | 7966 | int i; |
0359facc | 7967 | unsigned long flags; |
5a66926a | 7968 | DECLARE_MAC_BUF(mac); |
b481de9c | 7969 | |
6440adb5 CB |
7970 | /* Disabling hardware scan means that mac80211 will perform scans |
7971 | * "the hard way", rather than using device's scan. */ | |
bb8c093b | 7972 | if (iwl3945_param_disable_hw_scan) { |
b481de9c | 7973 | IWL_DEBUG_INFO("Disabling hw_scan\n"); |
bb8c093b | 7974 | iwl3945_hw_ops.hw_scan = NULL; |
b481de9c ZY |
7975 | } |
7976 | ||
bb8c093b CH |
7977 | if ((iwl3945_param_queues_num > IWL_MAX_NUM_QUEUES) || |
7978 | (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) { | |
b481de9c ZY |
7979 | IWL_ERROR("invalid queues_num, should be between %d and %d\n", |
7980 | IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES); | |
7981 | err = -EINVAL; | |
7982 | goto out; | |
7983 | } | |
7984 | ||
7985 | /* mac80211 allocates memory for this device instance, including | |
7986 | * space for this driver's private structure */ | |
bb8c093b | 7987 | hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops); |
b481de9c ZY |
7988 | if (hw == NULL) { |
7989 | IWL_ERROR("Can not allocate network device\n"); | |
7990 | err = -ENOMEM; | |
7991 | goto out; | |
7992 | } | |
7993 | SET_IEEE80211_DEV(hw, &pdev->dev); | |
7994 | ||
f51359a8 JB |
7995 | hw->rate_control_algorithm = "iwl-3945-rs"; |
7996 | ||
b481de9c ZY |
7997 | IWL_DEBUG_INFO("*** LOAD DRIVER ***\n"); |
7998 | priv = hw->priv; | |
7999 | priv->hw = hw; | |
8000 | ||
8001 | priv->pci_dev = pdev; | |
82b9a121 | 8002 | priv->cfg = cfg; |
6440adb5 CB |
8003 | |
8004 | /* Select antenna (may be helpful if only one antenna is connected) */ | |
bb8c093b | 8005 | priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna; |
c8b0e6e1 | 8006 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 8007 | iwl3945_debug_level = iwl3945_param_debug; |
b481de9c ZY |
8008 | atomic_set(&priv->restrict_refcnt, 0); |
8009 | #endif | |
8010 | priv->retry_rate = 1; | |
8011 | ||
8012 | priv->ibss_beacon = NULL; | |
8013 | ||
8014 | /* Tell mac80211 and its clients (e.g. Wireless Extensions) | |
8015 | * the range of signal quality values that we'll provide. | |
8016 | * Negative values for level/noise indicate that we'll provide dBm. | |
8017 | * For WE, at least, non-0 values here *enable* display of values | |
8018 | * in app (iwconfig). */ | |
8019 | hw->max_rssi = -20; /* signal level, negative indicates dBm */ | |
8020 | hw->max_noise = -20; /* noise level, negative indicates dBm */ | |
8021 | hw->max_signal = 100; /* link quality indication (%) */ | |
8022 | ||
8023 | /* Tell mac80211 our Tx characteristics */ | |
8024 | hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE; | |
8025 | ||
6440adb5 | 8026 | /* 4 EDCA QOS priorities */ |
b481de9c ZY |
8027 | hw->queues = 4; |
8028 | ||
8029 | spin_lock_init(&priv->lock); | |
8030 | spin_lock_init(&priv->power_data.lock); | |
8031 | spin_lock_init(&priv->sta_lock); | |
8032 | spin_lock_init(&priv->hcmd_lock); | |
8033 | ||
8034 | for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) | |
8035 | INIT_LIST_HEAD(&priv->ibss_mac_hash[i]); | |
8036 | ||
8037 | INIT_LIST_HEAD(&priv->free_frames); | |
8038 | ||
8039 | mutex_init(&priv->mutex); | |
8040 | if (pci_enable_device(pdev)) { | |
8041 | err = -ENODEV; | |
8042 | goto out_ieee80211_free_hw; | |
8043 | } | |
8044 | ||
8045 | pci_set_master(pdev); | |
8046 | ||
6440adb5 | 8047 | /* Clear the driver's (not device's) station table */ |
bb8c093b | 8048 | iwl3945_clear_stations_table(priv); |
b481de9c ZY |
8049 | |
8050 | priv->data_retry_limit = -1; | |
8051 | priv->ieee_channels = NULL; | |
8052 | priv->ieee_rates = NULL; | |
8318d78a | 8053 | priv->band = IEEE80211_BAND_2GHZ; |
b481de9c ZY |
8054 | |
8055 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
8056 | if (!err) | |
8057 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
8058 | if (err) { | |
8059 | printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n"); | |
8060 | goto out_pci_disable_device; | |
8061 | } | |
8062 | ||
8063 | pci_set_drvdata(pdev, priv); | |
8064 | err = pci_request_regions(pdev, DRV_NAME); | |
8065 | if (err) | |
8066 | goto out_pci_disable_device; | |
6440adb5 | 8067 | |
b481de9c ZY |
8068 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
8069 | * PCI Tx retries from interfering with C3 CPU state */ | |
8070 | pci_write_config_byte(pdev, 0x41, 0x00); | |
6440adb5 | 8071 | |
b481de9c ZY |
8072 | priv->hw_base = pci_iomap(pdev, 0, 0); |
8073 | if (!priv->hw_base) { | |
8074 | err = -ENODEV; | |
8075 | goto out_pci_release_regions; | |
8076 | } | |
8077 | ||
8078 | IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n", | |
8079 | (unsigned long long) pci_resource_len(pdev, 0)); | |
8080 | IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base); | |
8081 | ||
8082 | /* Initialize module parameter values here */ | |
8083 | ||
6440adb5 | 8084 | /* Disable radio (SW RF KILL) via parameter when loading driver */ |
bb8c093b | 8085 | if (iwl3945_param_disable) { |
b481de9c ZY |
8086 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
8087 | IWL_DEBUG_INFO("Radio disabled.\n"); | |
8088 | } | |
8089 | ||
8090 | priv->iw_mode = IEEE80211_IF_TYPE_STA; | |
8091 | ||
b481de9c | 8092 | printk(KERN_INFO DRV_NAME |
82b9a121 | 8093 | ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name); |
b481de9c ZY |
8094 | |
8095 | /* Device-specific setup */ | |
bb8c093b | 8096 | if (iwl3945_hw_set_hw_setting(priv)) { |
b481de9c | 8097 | IWL_ERROR("failed to set hw settings\n"); |
b481de9c ZY |
8098 | goto out_iounmap; |
8099 | } | |
8100 | ||
bb8c093b | 8101 | if (iwl3945_param_qos_enable) |
b481de9c ZY |
8102 | priv->qos_data.qos_enable = 1; |
8103 | ||
bb8c093b | 8104 | iwl3945_reset_qos(priv); |
b481de9c ZY |
8105 | |
8106 | priv->qos_data.qos_active = 0; | |
8107 | priv->qos_data.qos_cap.val = 0; | |
b481de9c | 8108 | |
8318d78a | 8109 | iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6); |
bb8c093b CH |
8110 | iwl3945_setup_deferred_work(priv); |
8111 | iwl3945_setup_rx_handlers(priv); | |
b481de9c ZY |
8112 | |
8113 | priv->rates_mask = IWL_RATES_MASK; | |
8114 | /* If power management is turned on, default to AC mode */ | |
8115 | priv->power_mode = IWL_POWER_AC; | |
8116 | priv->user_txpower_limit = IWL_DEFAULT_TX_POWER; | |
8117 | ||
0359facc | 8118 | spin_lock_irqsave(&priv->lock, flags); |
bb8c093b | 8119 | iwl3945_disable_interrupts(priv); |
0359facc | 8120 | spin_unlock_irqrestore(&priv->lock, flags); |
49df2b33 | 8121 | |
bb8c093b | 8122 | err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c ZY |
8123 | if (err) { |
8124 | IWL_ERROR("failed to create sysfs device attributes\n"); | |
b481de9c ZY |
8125 | goto out_release_irq; |
8126 | } | |
8127 | ||
5a66926a ZY |
8128 | /* nic init */ |
8129 | iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
8130 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
8131 | ||
8132 | iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
8133 | err = iwl3945_poll_bit(priv, CSR_GP_CNTRL, | |
8134 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
8135 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
8136 | if (err < 0) { | |
8137 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
8138 | goto out_remove_sysfs; | |
8139 | } | |
8140 | /* Read the EEPROM */ | |
8141 | err = iwl3945_eeprom_init(priv); | |
b481de9c | 8142 | if (err) { |
5a66926a ZY |
8143 | IWL_ERROR("Unable to init EEPROM\n"); |
8144 | goto out_remove_sysfs; | |
b481de9c | 8145 | } |
5a66926a ZY |
8146 | /* MAC Address location in EEPROM same for 3945/4965 */ |
8147 | get_eeprom_mac(priv, priv->mac_addr); | |
8148 | IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr)); | |
8149 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); | |
b481de9c | 8150 | |
849e0dce RC |
8151 | err = iwl3945_init_channel_map(priv); |
8152 | if (err) { | |
8153 | IWL_ERROR("initializing regulatory failed: %d\n", err); | |
8154 | goto out_remove_sysfs; | |
8155 | } | |
8156 | ||
8157 | err = iwl3945_init_geos(priv); | |
8158 | if (err) { | |
8159 | IWL_ERROR("initializing geos failed: %d\n", err); | |
8160 | goto out_free_channel_map; | |
8161 | } | |
849e0dce | 8162 | |
5a66926a ZY |
8163 | err = ieee80211_register_hw(priv->hw); |
8164 | if (err) { | |
8165 | IWL_ERROR("Failed to register network device (error %d)\n", err); | |
849e0dce | 8166 | goto out_free_geos; |
5a66926a | 8167 | } |
b481de9c | 8168 | |
5a66926a ZY |
8169 | priv->hw->conf.beacon_int = 100; |
8170 | priv->mac80211_registered = 1; | |
8171 | pci_save_state(pdev); | |
8172 | pci_disable_device(pdev); | |
b481de9c ZY |
8173 | |
8174 | return 0; | |
8175 | ||
849e0dce RC |
8176 | out_free_geos: |
8177 | iwl3945_free_geos(priv); | |
8178 | out_free_channel_map: | |
8179 | iwl3945_free_channel_map(priv); | |
5a66926a | 8180 | out_remove_sysfs: |
bb8c093b | 8181 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c ZY |
8182 | |
8183 | out_release_irq: | |
b481de9c ZY |
8184 | destroy_workqueue(priv->workqueue); |
8185 | priv->workqueue = NULL; | |
bb8c093b | 8186 | iwl3945_unset_hw_setting(priv); |
b481de9c ZY |
8187 | |
8188 | out_iounmap: | |
8189 | pci_iounmap(pdev, priv->hw_base); | |
8190 | out_pci_release_regions: | |
8191 | pci_release_regions(pdev); | |
8192 | out_pci_disable_device: | |
8193 | pci_disable_device(pdev); | |
8194 | pci_set_drvdata(pdev, NULL); | |
8195 | out_ieee80211_free_hw: | |
8196 | ieee80211_free_hw(priv->hw); | |
8197 | out: | |
8198 | return err; | |
8199 | } | |
8200 | ||
c83dbf68 | 8201 | static void __devexit iwl3945_pci_remove(struct pci_dev *pdev) |
b481de9c | 8202 | { |
bb8c093b | 8203 | struct iwl3945_priv *priv = pci_get_drvdata(pdev); |
b481de9c ZY |
8204 | struct list_head *p, *q; |
8205 | int i; | |
0359facc | 8206 | unsigned long flags; |
b481de9c ZY |
8207 | |
8208 | if (!priv) | |
8209 | return; | |
8210 | ||
8211 | IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n"); | |
8212 | ||
b481de9c | 8213 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
b24d22b1 | 8214 | |
bb8c093b | 8215 | iwl3945_down(priv); |
b481de9c | 8216 | |
0359facc MA |
8217 | /* make sure we flush any pending irq or |
8218 | * tasklet for the driver | |
8219 | */ | |
8220 | spin_lock_irqsave(&priv->lock, flags); | |
8221 | iwl3945_disable_interrupts(priv); | |
8222 | spin_unlock_irqrestore(&priv->lock, flags); | |
8223 | ||
8224 | iwl_synchronize_irq(priv); | |
8225 | ||
b481de9c ZY |
8226 | /* Free MAC hash list for ADHOC */ |
8227 | for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) { | |
8228 | list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) { | |
8229 | list_del(p); | |
bb8c093b | 8230 | kfree(list_entry(p, struct iwl3945_ibss_seq, list)); |
b481de9c ZY |
8231 | } |
8232 | } | |
8233 | ||
bb8c093b | 8234 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 8235 | |
bb8c093b | 8236 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
8237 | |
8238 | if (priv->rxq.bd) | |
bb8c093b CH |
8239 | iwl3945_rx_queue_free(priv, &priv->rxq); |
8240 | iwl3945_hw_txq_ctx_free(priv); | |
b481de9c | 8241 | |
bb8c093b CH |
8242 | iwl3945_unset_hw_setting(priv); |
8243 | iwl3945_clear_stations_table(priv); | |
b481de9c ZY |
8244 | |
8245 | if (priv->mac80211_registered) { | |
8246 | ieee80211_unregister_hw(priv->hw); | |
b481de9c ZY |
8247 | } |
8248 | ||
6ef89d0a MA |
8249 | /*netif_stop_queue(dev); */ |
8250 | flush_workqueue(priv->workqueue); | |
8251 | ||
bb8c093b | 8252 | /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes |
b481de9c ZY |
8253 | * priv->workqueue... so we can't take down the workqueue |
8254 | * until now... */ | |
8255 | destroy_workqueue(priv->workqueue); | |
8256 | priv->workqueue = NULL; | |
8257 | ||
b481de9c ZY |
8258 | pci_iounmap(pdev, priv->hw_base); |
8259 | pci_release_regions(pdev); | |
8260 | pci_disable_device(pdev); | |
8261 | pci_set_drvdata(pdev, NULL); | |
8262 | ||
849e0dce RC |
8263 | iwl3945_free_channel_map(priv); |
8264 | iwl3945_free_geos(priv); | |
b481de9c ZY |
8265 | |
8266 | if (priv->ibss_beacon) | |
8267 | dev_kfree_skb(priv->ibss_beacon); | |
8268 | ||
8269 | ieee80211_free_hw(priv->hw); | |
8270 | } | |
8271 | ||
8272 | #ifdef CONFIG_PM | |
8273 | ||
bb8c093b | 8274 | static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
b481de9c | 8275 | { |
bb8c093b | 8276 | struct iwl3945_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 8277 | |
e655b9f0 ZY |
8278 | if (priv->is_open) { |
8279 | set_bit(STATUS_IN_SUSPEND, &priv->status); | |
8280 | iwl3945_mac_stop(priv->hw); | |
8281 | priv->is_open = 1; | |
8282 | } | |
b481de9c | 8283 | |
b481de9c ZY |
8284 | pci_set_power_state(pdev, PCI_D3hot); |
8285 | ||
b481de9c ZY |
8286 | return 0; |
8287 | } | |
8288 | ||
bb8c093b | 8289 | static int iwl3945_pci_resume(struct pci_dev *pdev) |
b481de9c | 8290 | { |
bb8c093b | 8291 | struct iwl3945_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 8292 | |
b481de9c | 8293 | pci_set_power_state(pdev, PCI_D0); |
b481de9c | 8294 | |
e655b9f0 ZY |
8295 | if (priv->is_open) |
8296 | iwl3945_mac_start(priv->hw); | |
b481de9c | 8297 | |
e655b9f0 | 8298 | clear_bit(STATUS_IN_SUSPEND, &priv->status); |
b481de9c ZY |
8299 | return 0; |
8300 | } | |
8301 | ||
8302 | #endif /* CONFIG_PM */ | |
8303 | ||
8304 | /***************************************************************************** | |
8305 | * | |
8306 | * driver and module entry point | |
8307 | * | |
8308 | *****************************************************************************/ | |
8309 | ||
bb8c093b | 8310 | static struct pci_driver iwl3945_driver = { |
b481de9c | 8311 | .name = DRV_NAME, |
bb8c093b CH |
8312 | .id_table = iwl3945_hw_card_ids, |
8313 | .probe = iwl3945_pci_probe, | |
8314 | .remove = __devexit_p(iwl3945_pci_remove), | |
b481de9c | 8315 | #ifdef CONFIG_PM |
bb8c093b CH |
8316 | .suspend = iwl3945_pci_suspend, |
8317 | .resume = iwl3945_pci_resume, | |
b481de9c ZY |
8318 | #endif |
8319 | }; | |
8320 | ||
bb8c093b | 8321 | static int __init iwl3945_init(void) |
b481de9c ZY |
8322 | { |
8323 | ||
8324 | int ret; | |
8325 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
8326 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 RC |
8327 | |
8328 | ret = iwl3945_rate_control_register(); | |
8329 | if (ret) { | |
8330 | IWL_ERROR("Unable to register rate control algorithm: %d\n", ret); | |
8331 | return ret; | |
8332 | } | |
8333 | ||
bb8c093b | 8334 | ret = pci_register_driver(&iwl3945_driver); |
b481de9c ZY |
8335 | if (ret) { |
8336 | IWL_ERROR("Unable to initialize PCI module\n"); | |
897e1cf2 | 8337 | goto error_register; |
b481de9c | 8338 | } |
c8b0e6e1 | 8339 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 8340 | ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level); |
b481de9c ZY |
8341 | if (ret) { |
8342 | IWL_ERROR("Unable to create driver sysfs file\n"); | |
897e1cf2 | 8343 | goto error_debug; |
b481de9c ZY |
8344 | } |
8345 | #endif | |
8346 | ||
8347 | return ret; | |
897e1cf2 RC |
8348 | |
8349 | #ifdef CONFIG_IWL3945_DEBUG | |
8350 | error_debug: | |
8351 | pci_unregister_driver(&iwl3945_driver); | |
8352 | #endif | |
8353 | error_register: | |
8354 | iwl3945_rate_control_unregister(); | |
8355 | return ret; | |
b481de9c ZY |
8356 | } |
8357 | ||
bb8c093b | 8358 | static void __exit iwl3945_exit(void) |
b481de9c | 8359 | { |
c8b0e6e1 | 8360 | #ifdef CONFIG_IWL3945_DEBUG |
bb8c093b | 8361 | driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level); |
b481de9c | 8362 | #endif |
bb8c093b | 8363 | pci_unregister_driver(&iwl3945_driver); |
897e1cf2 | 8364 | iwl3945_rate_control_unregister(); |
b481de9c ZY |
8365 | } |
8366 | ||
bb8c093b | 8367 | module_param_named(antenna, iwl3945_param_antenna, int, 0444); |
b481de9c | 8368 | MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])"); |
bb8c093b | 8369 | module_param_named(disable, iwl3945_param_disable, int, 0444); |
b481de9c | 8370 | MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])"); |
bb8c093b | 8371 | module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444); |
b481de9c ZY |
8372 | MODULE_PARM_DESC(hwcrypto, |
8373 | "using hardware crypto engine (default 0 [software])\n"); | |
bb8c093b | 8374 | module_param_named(debug, iwl3945_param_debug, int, 0444); |
b481de9c | 8375 | MODULE_PARM_DESC(debug, "debug output mask"); |
bb8c093b | 8376 | module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444); |
b481de9c ZY |
8377 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); |
8378 | ||
bb8c093b | 8379 | module_param_named(queues_num, iwl3945_param_queues_num, int, 0444); |
b481de9c ZY |
8380 | MODULE_PARM_DESC(queues_num, "number of hw queues."); |
8381 | ||
8382 | /* QoS */ | |
bb8c093b | 8383 | module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444); |
b481de9c ZY |
8384 | MODULE_PARM_DESC(qos_enable, "enable all QoS functionality"); |
8385 | ||
bb8c093b CH |
8386 | module_exit(iwl3945_exit); |
8387 | module_init(iwl3945_init); |