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iwlwifi: remove input device and fix rfkill state
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
b481de9c
ZY		 41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
44#include <net/ieee80211_radiotap.h>
45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
82b9a121 49#include "iwl-3945-core.h"
b481de9c
ZY		 50#include "iwl-3945.h"
51#include "iwl-helpers.h"
52
c8b0e6e1 53#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 54u32 iwl3945_debug_level;
b481de9c
ZY		 55#endif
56
bb8c093b
CH		 57static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
58 struct iwl3945_tx_queue *txq);
416e1438 59
b481de9c
ZY		 60/******************************************************************************
61 *
62 * module boiler plate
63 *
64 ******************************************************************************/
65
66/* module parameters */
6440adb5
CB		 67static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
68static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
69static int iwl3945_param_disable; /* def: 0 = enable radio */
9fbab516 70static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
6440adb5
CB		 71int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
72static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
dfe7d458 73int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
b481de9c
ZY		 74
75/*
76 * module name, copyright, version, etc.
77 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
78 */
79
80#define DRV_DESCRIPTION \
81"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
82
c8b0e6e1 83#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 84#define VD "d"
85#else
86#define VD
87#endif
88
c8b0e6e1 89#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 90#define VS "s"
91#else
92#define VS
93#endif
94
b9e0b449 95#define IWLWIFI_VERSION "1.2.26k" VD VS
eb7ae89c 96#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
b481de9c
ZY		 97#define DRV_VERSION IWLWIFI_VERSION
98
b481de9c
ZY		 99
100MODULE_DESCRIPTION(DRV_DESCRIPTION);
101MODULE_VERSION(DRV_VERSION);
102MODULE_AUTHOR(DRV_COPYRIGHT);
103MODULE_LICENSE("GPL");
104
8318d78a
JB		 105static const struct ieee80211_supported_band *iwl3945_get_band(
106 struct iwl3945_priv *priv, enum ieee80211_band band)
b481de9c 107{
8318d78a 108 return priv->hw->wiphy->bands[band];
b481de9c
ZY		 109}
110
bb8c093b 111static int iwl3945_is_empty_essid(const char *essid, int essid_len)
b481de9c
ZY		 112{
113 /* Single white space is for Linksys APs */
114 if (essid_len == 1 && essid[0] == ' ')
115 return 1;
116
117 /* Otherwise, if the entire essid is 0, we assume it is hidden */
118 while (essid_len) {
119 essid_len--;
120 if (essid[essid_len] != '\0')
121 return 0;
122 }
123
124 return 1;
125}
126
bb8c093b 127static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
b481de9c
ZY		 128{
129 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
130 const char *s = essid;
131 char *d = escaped;
132
bb8c093b 133 if (iwl3945_is_empty_essid(essid, essid_len)) {
b481de9c
ZY		 134 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
135 return escaped;
136 }
137
138 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
139 while (essid_len--) {
140 if (*s == '\0') {
141 *d++ = '\\';
142 *d++ = '0';
143 s++;
144 } else
145 *d++ = *s++;
146 }
147 *d = '\0';
148 return escaped;
149}
150
b481de9c
ZY		 151/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
152 * DMA services
153 *
154 * Theory of operation
155 *
6440adb5
CB		 156 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
157 * of buffer descriptors, each of which points to one or more data buffers for
158 * the device to read from or fill. Driver and device exchange status of each
159 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
160 * entries in each circular buffer, to protect against confusing empty and full
161 * queue states.
162 *
163 * The device reads or writes the data in the queues via the device's several
164 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 165 *
166 * For Tx queue, there are low mark and high mark limits. If, after queuing
167 * the packet for Tx, free space become < low mark, Tx queue stopped. When
168 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
169 * Tx queue resumed.
170 *
6440adb5
CB		 171 * The 3945 operates with six queues: One receive queue, one transmit queue
172 * (#4) for sending commands to the device firmware, and four transmit queues
173 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
ZY		 174 ***************************************************/
175
c54b679d 176int iwl3945_queue_space(const struct iwl3945_queue *q)
b481de9c 177{
fc4b6853 178 int s = q->read_ptr - q->write_ptr;
b481de9c 179
fc4b6853 180 if (q->read_ptr > q->write_ptr)
b481de9c
ZY		 181 s -= q->n_bd;
182
183 if (s <= 0)
184 s += q->n_window;
185 /* keep some reserve to not confuse empty and full situations */
186 s -= 2;
187 if (s < 0)
188 s = 0;
189 return s;
190}
191
c54b679d 192int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
b481de9c 193{
fc4b6853
TW		 194 return q->write_ptr > q->read_ptr ?
195 (i >= q->read_ptr && i < q->write_ptr) :
196 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 197}
198
c54b679d 199
bb8c093b 200static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
b481de9c 201{
6440adb5 202 /* This is for scan command, the big buffer at end of command array */
b481de9c 203 if (is_huge)
6440adb5 204 return q->n_window; /* must be power of 2 */
b481de9c 205
6440adb5 206 /* Otherwise, use normal size buffers */
b481de9c
ZY		 207 return index & (q->n_window - 1);
208}
209
6440adb5
CB		 210/**
211 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
212 */
bb8c093b 213static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
b481de9c
ZY		 214 int count, int slots_num, u32 id)
215{
216 q->n_bd = count;
217 q->n_window = slots_num;
218 q->id = id;
219
c54b679d
TW		 220 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
221 * and iwl_queue_dec_wrap are broken. */
b481de9c
ZY		 222 BUG_ON(!is_power_of_2(count));
223
224 /* slots_num must be power-of-two size, otherwise
225 * get_cmd_index is broken. */
226 BUG_ON(!is_power_of_2(slots_num));
227
228 q->low_mark = q->n_window / 4;
229 if (q->low_mark < 4)
230 q->low_mark = 4;
231
232 q->high_mark = q->n_window / 8;
233 if (q->high_mark < 2)
234 q->high_mark = 2;
235
fc4b6853 236 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 237
238 return 0;
239}
240
6440adb5
CB		 241/**
242 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
243 */
bb8c093b
CH		 244static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
245 struct iwl3945_tx_queue *txq, u32 id)
b481de9c
ZY		 246{
247 struct pci_dev *dev = priv->pci_dev;
248
6440adb5
CB		 249 /* Driver private data, only for Tx (not command) queues,
250 * not shared with device. */
b481de9c
ZY		 251 if (id != IWL_CMD_QUEUE_NUM) {
252 txq->txb = kmalloc(sizeof(txq->txb[0]) *
253 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
254 if (!txq->txb) {
01ebd063 255 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
ZY		 256 "structures failed\n");
257 goto error;
258 }
259 } else
260 txq->txb = NULL;
261
6440adb5
CB		 262 /* Circular buffer of transmit frame descriptors (TFDs),
263 * shared with device */
b481de9c
ZY		 264 txq->bd = pci_alloc_consistent(dev,
265 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
266 &txq->q.dma_addr);
267
268 if (!txq->bd) {
269 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
270 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
271 goto error;
272 }
273 txq->q.id = id;
274
275 return 0;
276
277 error:
278 if (txq->txb) {
279 kfree(txq->txb);
280 txq->txb = NULL;
281 }
282
283 return -ENOMEM;
284}
285
6440adb5
CB		 286/**
287 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
288 */
bb8c093b
CH		 289int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
290 struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY		 291{
292 struct pci_dev *dev = priv->pci_dev;
293 int len;
294 int rc = 0;
295
6440adb5
CB		 296 /*
297 * Alloc buffer array for commands (Tx or other types of commands).
298 * For the command queue (#4), allocate command space + one big
299 * command for scan, since scan command is very huge; the system will
300 * not have two scans at the same time, so only one is needed.
301 * For data Tx queues (all other queues), no super-size command
302 * space is needed.
303 */
bb8c093b 304 len = sizeof(struct iwl3945_cmd) * slots_num;
b481de9c
ZY		 305 if (txq_id == IWL_CMD_QUEUE_NUM)
306 len += IWL_MAX_SCAN_SIZE;
307 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
308 if (!txq->cmd)
309 return -ENOMEM;
310
6440adb5 311 /* Alloc driver data array and TFD circular buffer */
bb8c093b 312 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY		 313 if (rc) {
314 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
315
316 return -ENOMEM;
317 }
318 txq->need_update = 0;
319
320 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 321 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 322 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
CB		 323
324 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 325 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 326
6440adb5 327 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 328 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 329
330 return 0;
331}
332
333/**
bb8c093b 334 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 335 * @txq: Transmit queue to deallocate.
336 *
337 * Empty queue by removing and destroying all BD's.
6440adb5
CB		 338 * Free all buffers.
339 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 340 */
bb8c093b 341void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 342{
bb8c093b 343 struct iwl3945_queue *q = &txq->q;
b481de9c
ZY		 344 struct pci_dev *dev = priv->pci_dev;
345 int len;
346
347 if (q->n_bd == 0)
348 return;
349
350 /* first, empty all BD's */
fc4b6853 351 for (; q->write_ptr != q->read_ptr;
c54b679d 352 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 353 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 354
bb8c093b 355 len = sizeof(struct iwl3945_cmd) * q->n_window;
b481de9c
ZY		 356 if (q->id == IWL_CMD_QUEUE_NUM)
357 len += IWL_MAX_SCAN_SIZE;
358
6440adb5 359 /* De-alloc array of command/tx buffers */
b481de9c
ZY		 360 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
361
6440adb5 362 /* De-alloc circular buffer of TFDs */
b481de9c 363 if (txq->q.n_bd)
bb8c093b 364 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
b481de9c
ZY		 365 txq->q.n_bd, txq->bd, txq->q.dma_addr);
366
6440adb5 367 /* De-alloc array of per-TFD driver data */
b481de9c
ZY		 368 if (txq->txb) {
369 kfree(txq->txb);
370 txq->txb = NULL;
371 }
372
6440adb5 373 /* 0-fill queue descriptor structure */
b481de9c
ZY		 374 memset(txq, 0, sizeof(*txq));
375}
376
bb8c093b 377const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
ZY		 378
379/*************** STATION TABLE MANAGEMENT ****
9fbab516 380 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 381 * the functionality provided here
382 */
383
384/**************************************************************/
01ebd063 385#if 0 /* temporary disable till we add real remove station */
6440adb5
CB		 386/**
387 * iwl3945_remove_station - Remove driver's knowledge of station.
388 *
389 * NOTE: This does not remove station from device's station table.
390 */
bb8c093b 391static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 392{
393 int index = IWL_INVALID_STATION;
394 int i;
395 unsigned long flags;
396
397 spin_lock_irqsave(&priv->sta_lock, flags);
398
399 if (is_ap)
400 index = IWL_AP_ID;
401 else if (is_broadcast_ether_addr(addr))
402 index = priv->hw_setting.bcast_sta_id;
403 else
404 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
405 if (priv->stations[i].used &&
406 !compare_ether_addr(priv->stations[i].sta.sta.addr,
407 addr)) {
408 index = i;
409 break;
410 }
411
412 if (unlikely(index == IWL_INVALID_STATION))
413 goto out;
414
415 if (priv->stations[index].used) {
416 priv->stations[index].used = 0;
417 priv->num_stations--;
418 }
419
420 BUG_ON(priv->num_stations < 0);
421
422out:
423 spin_unlock_irqrestore(&priv->sta_lock, flags);
424 return 0;
425}
556f8db7 426#endif
6440adb5
CB		 427
428/**
429 * iwl3945_clear_stations_table - Clear the driver's station table
430 *
431 * NOTE: This does not clear or otherwise alter the device's station table.
432 */
bb8c093b 433static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
b481de9c
ZY		 434{
435 unsigned long flags;
436
437 spin_lock_irqsave(&priv->sta_lock, flags);
438
439 priv->num_stations = 0;
440 memset(priv->stations, 0, sizeof(priv->stations));
441
442 spin_unlock_irqrestore(&priv->sta_lock, flags);
443}
444
6440adb5
CB		 445/**
446 * iwl3945_add_station - Add station to station tables in driver and device
447 */
bb8c093b 448u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY		 449{
450 int i;
451 int index = IWL_INVALID_STATION;
bb8c093b 452 struct iwl3945_station_entry *station;
b481de9c 453 unsigned long flags_spin;
0795af57 454 DECLARE_MAC_BUF(mac);
c14c521e 455 u8 rate;
b481de9c
ZY		 456
457 spin_lock_irqsave(&priv->sta_lock, flags_spin);
458 if (is_ap)
459 index = IWL_AP_ID;
460 else if (is_broadcast_ether_addr(addr))
461 index = priv->hw_setting.bcast_sta_id;
462 else
463 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
464 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
465 addr)) {
466 index = i;
467 break;
468 }
469
470 if (!priv->stations[i].used &&
471 index == IWL_INVALID_STATION)
472 index = i;
473 }
474
01ebd063 475 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY		 476 since they have different meaning */
477 if (unlikely(index == IWL_INVALID_STATION)) {
478 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
479 return index;
480 }
481
482 if (priv->stations[index].used &&
483 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
484 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
485 return index;
486 }
487
0795af57 488 IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
b481de9c
ZY		 489 station = &priv->stations[index];
490 station->used = 1;
491 priv->num_stations++;
492
6440adb5 493 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 494 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY		 495 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
496 station->sta.mode = 0;
497 station->sta.sta.sta_id = index;
498 station->sta.station_flags = 0;
499
8318d78a 500 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW		 501 rate = IWL_RATE_6M_PLCP;
502 else
503 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY		 504
505 /* Turn on both antennas for the station... */
506 station->sta.rate_n_flags =
bb8c093b 507 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e
ZY		 508 station->current_rate.rate_n_flags =
509 le16_to_cpu(station->sta.rate_n_flags);
510
b481de9c 511 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB		 512
513 /* Add station to device's station table */
bb8c093b 514 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 515 return index;
516
517}
518
519/*************** DRIVER STATUS FUNCTIONS *****/
520
bb8c093b 521static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
b481de9c
ZY		 522{
523 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
524 * set but EXIT_PENDING is not */
525 return test_bit(STATUS_READY, &priv->status) &&
526 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
527 !test_bit(STATUS_EXIT_PENDING, &priv->status);
528}
529
bb8c093b 530static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
b481de9c
ZY		 531{
532 return test_bit(STATUS_ALIVE, &priv->status);
533}
534
bb8c093b 535static inline int iwl3945_is_init(struct iwl3945_priv *priv)
b481de9c
ZY		 536{
537 return test_bit(STATUS_INIT, &priv->status);
538}
539
80fcc9e2
AG		 540static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
541{
542 return test_bit(STATUS_RF_KILL_SW, &priv->status);
543}
544
545static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
546{
547 return test_bit(STATUS_RF_KILL_HW, &priv->status);
548}
549
bb8c093b 550static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
b481de9c 551{
80fcc9e2
AG		 552 return iwl3945_is_rfkill_hw(priv) ||
553 iwl3945_is_rfkill_sw(priv);
b481de9c
ZY		 554}
555
bb8c093b 556static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
b481de9c
ZY		 557{
558
bb8c093b 559 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 560 return 0;
561
bb8c093b 562 return iwl3945_is_ready(priv);
b481de9c
ZY		 563}
564
565/*************** HOST COMMAND QUEUE FUNCTIONS *****/
566
567#define IWL_CMD(x) case x : return #x
568
569static const char *get_cmd_string(u8 cmd)
570{
571 switch (cmd) {
572 IWL_CMD(REPLY_ALIVE);
573 IWL_CMD(REPLY_ERROR);
574 IWL_CMD(REPLY_RXON);
575 IWL_CMD(REPLY_RXON_ASSOC);
576 IWL_CMD(REPLY_QOS_PARAM);
577 IWL_CMD(REPLY_RXON_TIMING);
578 IWL_CMD(REPLY_ADD_STA);
579 IWL_CMD(REPLY_REMOVE_STA);
580 IWL_CMD(REPLY_REMOVE_ALL_STA);
581 IWL_CMD(REPLY_3945_RX);
582 IWL_CMD(REPLY_TX);
583 IWL_CMD(REPLY_RATE_SCALE);
584 IWL_CMD(REPLY_LEDS_CMD);
585 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
586 IWL_CMD(RADAR_NOTIFICATION);
587 IWL_CMD(REPLY_QUIET_CMD);
588 IWL_CMD(REPLY_CHANNEL_SWITCH);
589 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
590 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
591 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
592 IWL_CMD(POWER_TABLE_CMD);
593 IWL_CMD(PM_SLEEP_NOTIFICATION);
594 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
595 IWL_CMD(REPLY_SCAN_CMD);
596 IWL_CMD(REPLY_SCAN_ABORT_CMD);
597 IWL_CMD(SCAN_START_NOTIFICATION);
598 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
599 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
600 IWL_CMD(BEACON_NOTIFICATION);
601 IWL_CMD(REPLY_TX_BEACON);
602 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
603 IWL_CMD(QUIET_NOTIFICATION);
604 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
605 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
606 IWL_CMD(REPLY_BT_CONFIG);
607 IWL_CMD(REPLY_STATISTICS_CMD);
608 IWL_CMD(STATISTICS_NOTIFICATION);
609 IWL_CMD(REPLY_CARD_STATE_CMD);
610 IWL_CMD(CARD_STATE_NOTIFICATION);
611 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
612 default:
613 return "UNKNOWN";
614
615 }
616}
617
618#define HOST_COMPLETE_TIMEOUT (HZ / 2)
619
620/**
bb8c093b 621 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 622 * @priv: device private data point
623 * @cmd: a point to the ucode command structure
624 *
625 * The function returns < 0 values to indicate the operation is
626 * failed. On success, it turns the index (> 0) of command in the
627 * command queue.
628 */
bb8c093b 629static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 630{
bb8c093b
CH		 631 struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
632 struct iwl3945_queue *q = &txq->q;
633 struct iwl3945_tfd_frame *tfd;
b481de9c 634 u32 *control_flags;
bb8c093b 635 struct iwl3945_cmd *out_cmd;
b481de9c
ZY		 636 u32 idx;
637 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
638 dma_addr_t phys_addr;
639 int pad;
640 u16 count;
641 int ret;
642 unsigned long flags;
643
644 /* If any of the command structures end up being larger than
645 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
646 * we will need to increase the size of the TFD entries */
647 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
648 !(cmd->meta.flags & CMD_SIZE_HUGE));
649
c342a1b9
GG		 650
651 if (iwl3945_is_rfkill(priv)) {
652 IWL_DEBUG_INFO("Not sending command - RF KILL");
653 return -EIO;
654 }
655
bb8c093b 656 if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY		 657 IWL_ERROR("No space for Tx\n");
658 return -ENOSPC;
659 }
660
661 spin_lock_irqsave(&priv->hcmd_lock, flags);
662
fc4b6853 663 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 664 memset(tfd, 0, sizeof(*tfd));
665
666 control_flags = (u32 *) tfd;
667
fc4b6853 668 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY		 669 out_cmd = &txq->cmd[idx];
670
671 out_cmd->hdr.cmd = cmd->id;
672 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
673 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
674
675 /* At this point, the out_cmd now has all of the incoming cmd
676 * information */
677
678 out_cmd->hdr.flags = 0;
679 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 680 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY		 681 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
682 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
683
684 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
bb8c093b
CH		 685 offsetof(struct iwl3945_cmd, hdr);
686 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 687
688 pad = U32_PAD(cmd->len);
689 count = TFD_CTL_COUNT_GET(*control_flags);
690 *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
691
692 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
693 "%d bytes at %d[%d]:%d\n",
694 get_cmd_string(out_cmd->hdr.cmd),
695 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 696 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 697
698 txq->need_update = 1;
6440adb5
CB		 699
700 /* Increment and update queue's write index */
c54b679d 701 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 702 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 703
704 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
705 return ret ? ret : idx;
706}
707
bb8c093b 708static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 709{
710 int ret;
711
712 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
713
714 /* An asynchronous command can not expect an SKB to be set. */
715 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
716
717 /* An asynchronous command MUST have a callback. */
718 BUG_ON(!cmd->meta.u.callback);
719
720 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
721 return -EBUSY;
722
bb8c093b 723 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 724 if (ret < 0) {
bb8c093b 725 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 726 get_cmd_string(cmd->id), ret);
727 return ret;
728 }
729 return 0;
730}
731
bb8c093b 732static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c
ZY		 733{
734 int cmd_idx;
735 int ret;
b481de9c
ZY		 736
737 BUG_ON(cmd->meta.flags & CMD_ASYNC);
738
739 /* A synchronous command can not have a callback set. */
740 BUG_ON(cmd->meta.u.callback != NULL);
741
e5472978 742 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
b481de9c
ZY		 743 IWL_ERROR("Error sending %s: Already sending a host command\n",
744 get_cmd_string(cmd->id));
e5472978
TW		 745 ret = -EBUSY;
746 goto out;
b481de9c
ZY		 747 }
748
749 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
750
751 if (cmd->meta.flags & CMD_WANT_SKB)
752 cmd->meta.source = &cmd->meta;
753
bb8c093b 754 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY		 755 if (cmd_idx < 0) {
756 ret = cmd_idx;
bb8c093b 757 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
b481de9c
ZY		 758 get_cmd_string(cmd->id), ret);
759 goto out;
760 }
761
762 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
763 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
764 HOST_COMPLETE_TIMEOUT);
765 if (!ret) {
766 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
767 IWL_ERROR("Error sending %s: time out after %dms.\n",
768 get_cmd_string(cmd->id),
769 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
770
771 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
772 ret = -ETIMEDOUT;
773 goto cancel;
774 }
775 }
776
777 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
778 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
779 get_cmd_string(cmd->id));
780 ret = -ECANCELED;
781 goto fail;
782 }
783 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
784 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
785 get_cmd_string(cmd->id));
786 ret = -EIO;
787 goto fail;
788 }
789 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
790 IWL_ERROR("Error: Response NULL in '%s'\n",
791 get_cmd_string(cmd->id));
792 ret = -EIO;
793 goto out;
794 }
795
796 ret = 0;
797 goto out;
798
799cancel:
800 if (cmd->meta.flags & CMD_WANT_SKB) {
bb8c093b 801 struct iwl3945_cmd *qcmd;
b481de9c
ZY		 802
803 /* Cancel the CMD_WANT_SKB flag for the cmd in the
804 * TX cmd queue. Otherwise in case the cmd comes
805 * in later, it will possibly set an invalid
806 * address (cmd->meta.source). */
807 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
808 qcmd->meta.flags &= ~CMD_WANT_SKB;
809 }
810fail:
811 if (cmd->meta.u.skb) {
812 dev_kfree_skb_any(cmd->meta.u.skb);
813 cmd->meta.u.skb = NULL;
814 }
815out:
e5472978 816 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
b481de9c
ZY		 817 return ret;
818}
819
bb8c093b 820int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
b481de9c 821{
b481de9c 822 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 823 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 824
bb8c093b 825 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY		 826}
827
bb8c093b 828int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
b481de9c 829{
bb8c093b 830 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 831 .id = id,
832 .len = len,
833 .data = data,
834 };
835
bb8c093b 836 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 837}
838
bb8c093b 839static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
b481de9c 840{
bb8c093b 841 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 842 .id = id,
843 .len = sizeof(val),
844 .data = &val,
845 };
846
bb8c093b 847 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 848}
849
bb8c093b 850int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
b481de9c 851{
bb8c093b 852 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY		 853}
854
b481de9c 855/**
bb8c093b 856 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB		 857 * @band: 2.4 or 5 GHz band
858 * @channel: Any channel valid for the requested band
b481de9c 859
8318d78a 860 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY		 861 *
862 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 863 * in the staging RXON flag structure based on the band
b481de9c 864 */
8318d78a
JB		 865static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
866 enum ieee80211_band band,
867 u16 channel)
b481de9c 868{
8318d78a 869 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 870 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 871 channel, band);
b481de9c
ZY		 872 return -EINVAL;
873 }
874
875 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
8318d78a 876 (priv->band == band))
b481de9c
ZY		 877 return 0;
878
879 priv->staging_rxon.channel = cpu_to_le16(channel);
8318d78a 880 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 881 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
882 else
883 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
884
8318d78a 885 priv->band = band;
b481de9c 886
8318d78a 887 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY		 888
889 return 0;
890}
891
892/**
bb8c093b 893 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 894 *
895 * NOTE: This is really only useful during development and can eventually
896 * be #ifdef'd out once the driver is stable and folks aren't actively
897 * making changes
898 */
bb8c093b 899static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 900{
901 int error = 0;
902 int counter = 1;
903
904 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
905 error |= le32_to_cpu(rxon->flags &
906 (RXON_FLG_TGJ_NARROW_BAND_MSK |
907 RXON_FLG_RADAR_DETECT_MSK));
908 if (error)
909 IWL_WARNING("check 24G fields %d | %d\n",
910 counter++, error);
911 } else {
912 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
913 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
914 if (error)
915 IWL_WARNING("check 52 fields %d | %d\n",
916 counter++, error);
917 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
918 if (error)
919 IWL_WARNING("check 52 CCK %d | %d\n",
920 counter++, error);
921 }
922 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
923 if (error)
924 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
925
926 /* make sure basic rates 6Mbps and 1Mbps are supported */
927 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
928 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
929 if (error)
930 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
931
932 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
933 if (error)
934 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
935
936 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
937 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
938 if (error)
939 IWL_WARNING("check CCK and short slot %d | %d\n",
940 counter++, error);
941
942 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
943 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
944 if (error)
945 IWL_WARNING("check CCK & auto detect %d | %d\n",
946 counter++, error);
947
948 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
949 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
950 if (error)
951 IWL_WARNING("check TGG and auto detect %d | %d\n",
952 counter++, error);
953
954 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
955 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
956 RXON_FLG_ANT_A_MSK)) == 0);
957 if (error)
958 IWL_WARNING("check antenna %d %d\n", counter++, error);
959
960 if (error)
961 IWL_WARNING("Tuning to channel %d\n",
962 le16_to_cpu(rxon->channel));
963
964 if (error) {
bb8c093b 965 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
b481de9c
ZY		 966 return -1;
967 }
968 return 0;
969}
970
971/**
9fbab516 972 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 973 * @priv: staging_rxon is compared to active_rxon
b481de9c 974 *
9fbab516
BC		 975 * If the RXON structure is changing enough to require a new tune,
976 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
977 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 978 */
bb8c093b 979static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
b481de9c
ZY		 980{
981
982 /* These items are only settable from the full RXON command */
5d1e2325 983 if (!(iwl3945_is_associated(priv)) ||
b481de9c
ZY		 984 compare_ether_addr(priv->staging_rxon.bssid_addr,
985 priv->active_rxon.bssid_addr) ||
986 compare_ether_addr(priv->staging_rxon.node_addr,
987 priv->active_rxon.node_addr) ||
988 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
989 priv->active_rxon.wlap_bssid_addr) ||
990 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
991 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
992 (priv->staging_rxon.air_propagation !=
993 priv->active_rxon.air_propagation) ||
994 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
995 return 1;
996
997 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
998 * be updated with the RXON_ASSOC command -- however only some
999 * flag transitions are allowed using RXON_ASSOC */
1000
1001 /* Check if we are not switching bands */
1002 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
1003 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
1004 return 1;
1005
1006 /* Check if we are switching association toggle */
1007 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
1008 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
1009 return 1;
1010
1011 return 0;
1012}
1013
bb8c093b 1014static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
b481de9c
ZY		 1015{
1016 int rc = 0;
bb8c093b
CH		 1017 struct iwl3945_rx_packet *res = NULL;
1018 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1019 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1020 .id = REPLY_RXON_ASSOC,
1021 .len = sizeof(rxon_assoc),
1022 .meta.flags = CMD_WANT_SKB,
1023 .data = &rxon_assoc,
1024 };
bb8c093b
CH		 1025 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
1026 const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY		 1027
1028 if ((rxon1->flags == rxon2->flags) &&
1029 (rxon1->filter_flags == rxon2->filter_flags) &&
1030 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1031 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1032 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1033 return 0;
1034 }
1035
1036 rxon_assoc.flags = priv->staging_rxon.flags;
1037 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1038 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1039 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1040 rxon_assoc.reserved = 0;
1041
bb8c093b 1042 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1043 if (rc)
1044 return rc;
1045
bb8c093b 1046 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1047 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1048 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1049 rc = -EIO;
1050 }
1051
1052 priv->alloc_rxb_skb--;
1053 dev_kfree_skb_any(cmd.meta.u.skb);
1054
1055 return rc;
1056}
1057
1058/**
bb8c093b 1059 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 1060 *
01ebd063 1061 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 1062 * the active_rxon structure is updated with the new data. This
1063 * function correctly transitions out of the RXON_ASSOC_MSK state if
1064 * a HW tune is required based on the RXON structure changes.
1065 */
bb8c093b 1066static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
b481de9c
ZY		 1067{
1068 /* cast away the const for active_rxon in this function */
bb8c093b 1069 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
b481de9c 1070 int rc = 0;
0795af57 1071 DECLARE_MAC_BUF(mac);
b481de9c 1072
bb8c093b 1073 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 1074 return -1;
1075
1076 /* always get timestamp with Rx frame */
1077 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1078
1079 /* select antenna */
1080 priv->staging_rxon.flags &=
1081 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1082 priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1083
bb8c093b 1084 rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY		 1085 if (rc) {
1086 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
1087 return -EINVAL;
1088 }
1089
1090 /* If we don't need to send a full RXON, we can use
bb8c093b 1091 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 1092 * and other flags for the current radio configuration. */
bb8c093b
CH		 1093 if (!iwl3945_full_rxon_required(priv)) {
1094 rc = iwl3945_send_rxon_assoc(priv);
b481de9c
ZY		 1095 if (rc) {
1096 IWL_ERROR("Error setting RXON_ASSOC "
1097 "configuration (%d).\n", rc);
1098 return rc;
1099 }
1100
1101 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1102
1103 return 0;
1104 }
1105
1106 /* If we are currently associated and the new config requires
1107 * an RXON_ASSOC and the new config wants the associated mask enabled,
1108 * we must clear the associated from the active configuration
1109 * before we apply the new config */
bb8c093b 1110 if (iwl3945_is_associated(priv) &&
b481de9c
ZY		 1111 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1112 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1113 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1114
bb8c093b
CH		 1115 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1116 sizeof(struct iwl3945_rxon_cmd),
b481de9c
ZY		 1117 &priv->active_rxon);
1118
1119 /* If the mask clearing failed then we set
1120 * active_rxon back to what it was previously */
1121 if (rc) {
1122 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1123 IWL_ERROR("Error clearing ASSOC_MSK on current "
1124 "configuration (%d).\n", rc);
1125 return rc;
1126 }
b481de9c
ZY		 1127 }
1128
1129 IWL_DEBUG_INFO("Sending RXON\n"
1130 "* with%s RXON_FILTER_ASSOC_MSK\n"
1131 "* channel = %d\n"
0795af57 1132 "* bssid = %s\n",
b481de9c
ZY		 1133 ((priv->staging_rxon.filter_flags &
1134 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1135 le16_to_cpu(priv->staging_rxon.channel),
0795af57 1136 print_mac(mac, priv->staging_rxon.bssid_addr));
b481de9c
ZY		 1137
1138 /* Apply the new configuration */
bb8c093b
CH		 1139 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1140 sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY		 1141 if (rc) {
1142 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1143 return rc;
1144 }
1145
1146 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1147
bb8c093b 1148 iwl3945_clear_stations_table(priv);
556f8db7 1149
b481de9c
ZY		 1150 /* If we issue a new RXON command which required a tune then we must
1151 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 1152 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1153 if (rc) {
1154 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1155 return rc;
1156 }
1157
1158 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 1159 if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
b481de9c
ZY		 1160 IWL_INVALID_STATION) {
1161 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1162 return -EIO;
1163 }
1164
1165 /* If we have set the ASSOC_MSK and we are in BSS mode then
1166 * add the IWL_AP_ID to the station rate table */
bb8c093b 1167 if (iwl3945_is_associated(priv) &&
b481de9c 1168 (priv->iw_mode == IEEE80211_IF_TYPE_STA))
bb8c093b 1169 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
b481de9c
ZY		 1170 == IWL_INVALID_STATION) {
1171 IWL_ERROR("Error adding AP address for transmit.\n");
1172 return -EIO;
1173 }
1174
8318d78a 1175 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY		 1176 rc = iwl3945_init_hw_rate_table(priv);
1177 if (rc) {
1178 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1179 return -EIO;
1180 }
1181
1182 return 0;
1183}
1184
bb8c093b 1185static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
b481de9c 1186{
bb8c093b 1187 struct iwl3945_bt_cmd bt_cmd = {
b481de9c
ZY		 1188 .flags = 3,
1189 .lead_time = 0xAA,
1190 .max_kill = 1,
1191 .kill_ack_mask = 0,
1192 .kill_cts_mask = 0,
1193 };
1194
bb8c093b
CH		 1195 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1196 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
b481de9c
ZY		 1197}
1198
bb8c093b 1199static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
b481de9c
ZY		 1200{
1201 int rc = 0;
bb8c093b
CH		 1202 struct iwl3945_rx_packet *res;
1203 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1204 .id = REPLY_SCAN_ABORT_CMD,
1205 .meta.flags = CMD_WANT_SKB,
1206 };
1207
1208 /* If there isn't a scan actively going on in the hardware
1209 * then we are in between scan bands and not actually
1210 * actively scanning, so don't send the abort command */
1211 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1212 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1213 return 0;
1214 }
1215
bb8c093b 1216 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1217 if (rc) {
1218 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1219 return rc;
1220 }
1221
bb8c093b 1222 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1223 if (res->u.status != CAN_ABORT_STATUS) {
1224 /* The scan abort will return 1 for success or
1225 * 2 for "failure". A failure condition can be
1226 * due to simply not being in an active scan which
1227 * can occur if we send the scan abort before we
1228 * the microcode has notified us that a scan is
1229 * completed. */
1230 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1231 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1232 clear_bit(STATUS_SCAN_HW, &priv->status);
1233 }
1234
1235 dev_kfree_skb_any(cmd.meta.u.skb);
1236
1237 return rc;
1238}
1239
bb8c093b
CH		 1240static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1241 struct iwl3945_cmd *cmd,
b481de9c
ZY		 1242 struct sk_buff *skb)
1243{
1244 return 1;
1245}
1246
1247/*
1248 * CARD_STATE_CMD
1249 *
9fbab516 1250 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY		 1251 *
1252 * When in the 'enable' state the card operates as normal.
1253 * When in the 'disable' state, the card enters into a low power mode.
1254 * When in the 'halt' state, the card is shut down and must be fully
1255 * restarted to come back on.
1256 */
bb8c093b 1257static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1258{
bb8c093b 1259 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 1260 .id = REPLY_CARD_STATE_CMD,
1261 .len = sizeof(u32),
1262 .data = &flags,
1263 .meta.flags = meta_flag,
1264 };
1265
1266 if (meta_flag & CMD_ASYNC)
bb8c093b 1267 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
b481de9c 1268
bb8c093b 1269 return iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1270}
1271
bb8c093b
CH		 1272static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1273 struct iwl3945_cmd *cmd, struct sk_buff *skb)
b481de9c 1274{
bb8c093b 1275 struct iwl3945_rx_packet *res = NULL;
b481de9c
ZY		 1276
1277 if (!skb) {
1278 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1279 return 1;
1280 }
1281
bb8c093b 1282 res = (struct iwl3945_rx_packet *)skb->data;
b481de9c
ZY		 1283 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1284 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1285 res->hdr.flags);
1286 return 1;
1287 }
1288
1289 switch (res->u.add_sta.status) {
1290 case ADD_STA_SUCCESS_MSK:
1291 break;
1292 default:
1293 break;
1294 }
1295
1296 /* We didn't cache the SKB; let the caller free it */
1297 return 1;
1298}
1299
bb8c093b
CH		 1300int iwl3945_send_add_station(struct iwl3945_priv *priv,
1301 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1302{
bb8c093b 1303 struct iwl3945_rx_packet *res = NULL;
b481de9c 1304 int rc = 0;
bb8c093b 1305 struct iwl3945_host_cmd cmd = {
b481de9c 1306 .id = REPLY_ADD_STA,
bb8c093b 1307 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY		 1308 .meta.flags = flags,
1309 .data = sta,
1310 };
1311
1312 if (flags & CMD_ASYNC)
bb8c093b 1313 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY		 1314 else
1315 cmd.meta.flags |= CMD_WANT_SKB;
1316
bb8c093b 1317 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1318
1319 if (rc || (flags & CMD_ASYNC))
1320 return rc;
1321
bb8c093b 1322 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1323 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1324 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1325 res->hdr.flags);
1326 rc = -EIO;
1327 }
1328
1329 if (rc == 0) {
1330 switch (res->u.add_sta.status) {
1331 case ADD_STA_SUCCESS_MSK:
1332 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1333 break;
1334 default:
1335 rc = -EIO;
1336 IWL_WARNING("REPLY_ADD_STA failed\n");
1337 break;
1338 }
1339 }
1340
1341 priv->alloc_rxb_skb--;
1342 dev_kfree_skb_any(cmd.meta.u.skb);
1343
1344 return rc;
1345}
1346
bb8c093b 1347static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
b481de9c
ZY		 1348 struct ieee80211_key_conf *keyconf,
1349 u8 sta_id)
1350{
1351 unsigned long flags;
1352 __le16 key_flags = 0;
1353
1354 switch (keyconf->alg) {
1355 case ALG_CCMP:
1356 key_flags |= STA_KEY_FLG_CCMP;
1357 key_flags |= cpu_to_le16(
1358 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1359 key_flags &= ~STA_KEY_FLG_INVALID;
1360 break;
1361 case ALG_TKIP:
1362 case ALG_WEP:
b481de9c
ZY		 1363 default:
1364 return -EINVAL;
1365 }
1366 spin_lock_irqsave(&priv->sta_lock, flags);
1367 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1368 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1369 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1370 keyconf->keylen);
1371
1372 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1373 keyconf->keylen);
1374 priv->stations[sta_id].sta.key.key_flags = key_flags;
1375 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1376 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1377
1378 spin_unlock_irqrestore(&priv->sta_lock, flags);
1379
1380 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
bb8c093b 1381 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1382 return 0;
1383}
1384
bb8c093b 1385static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
b481de9c
ZY		 1386{
1387 unsigned long flags;
1388
1389 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH		 1390 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1391 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
b481de9c
ZY		 1392 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1393 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1394 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1395 spin_unlock_irqrestore(&priv->sta_lock, flags);
1396
1397 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1398 iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1399 return 0;
1400}
1401
bb8c093b 1402static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
b481de9c
ZY		 1403{
1404 struct list_head *element;
1405
1406 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1407 priv->frames_count);
1408
1409 while (!list_empty(&priv->free_frames)) {
1410 element = priv->free_frames.next;
1411 list_del(element);
bb8c093b 1412 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY		 1413 priv->frames_count--;
1414 }
1415
1416 if (priv->frames_count) {
1417 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1418 priv->frames_count);
1419 priv->frames_count = 0;
1420 }
1421}
1422
bb8c093b 1423static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
b481de9c 1424{
bb8c093b 1425 struct iwl3945_frame *frame;
b481de9c
ZY		 1426 struct list_head *element;
1427 if (list_empty(&priv->free_frames)) {
1428 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1429 if (!frame) {
1430 IWL_ERROR("Could not allocate frame!\n");
1431 return NULL;
1432 }
1433
1434 priv->frames_count++;
1435 return frame;
1436 }
1437
1438 element = priv->free_frames.next;
1439 list_del(element);
bb8c093b 1440 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY		 1441}
1442
bb8c093b 1443static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY		 1444{
1445 memset(frame, 0, sizeof(*frame));
1446 list_add(&frame->list, &priv->free_frames);
1447}
1448
bb8c093b 1449unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
b481de9c
ZY		 1450 struct ieee80211_hdr *hdr,
1451 const u8 *dest, int left)
1452{
1453
bb8c093b 1454 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
b481de9c
ZY		 1455 ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
1456 (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
1457 return 0;
1458
1459 if (priv->ibss_beacon->len > left)
1460 return 0;
1461
1462 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1463
1464 return priv->ibss_beacon->len;
1465}
1466
bb8c093b 1467static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY		 1468{
1469 u8 i;
1470
1471 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1472 i = iwl3945_rates[i].next_ieee) {
b481de9c 1473 if (rate_mask & (1 << i))
bb8c093b 1474 return iwl3945_rates[i].plcp;
b481de9c
ZY		 1475 }
1476
1477 return IWL_RATE_INVALID;
1478}
1479
bb8c093b 1480static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
b481de9c 1481{
bb8c093b 1482 struct iwl3945_frame *frame;
b481de9c
ZY		 1483 unsigned int frame_size;
1484 int rc;
1485 u8 rate;
1486
bb8c093b 1487 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY		 1488
1489 if (!frame) {
1490 IWL_ERROR("Could not obtain free frame buffer for beacon "
1491 "command.\n");
1492 return -ENOMEM;
1493 }
1494
1495 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1496 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY		 1497 0xFF0);
1498 if (rate == IWL_INVALID_RATE)
1499 rate = IWL_RATE_6M_PLCP;
1500 } else {
bb8c093b 1501 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY		 1502 if (rate == IWL_INVALID_RATE)
1503 rate = IWL_RATE_1M_PLCP;
1504 }
1505
bb8c093b 1506 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1507
bb8c093b 1508 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1509 &frame->u.cmd[0]);
1510
bb8c093b 1511 iwl3945_free_frame(priv, frame);
b481de9c
ZY		 1512
1513 return rc;
1514}
1515
1516/******************************************************************************
1517 *
1518 * EEPROM related functions
1519 *
1520 ******************************************************************************/
1521
bb8c093b 1522static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
b481de9c
ZY		 1523{
1524 memcpy(mac, priv->eeprom.mac_address, 6);
1525}
1526
74a3a250
RC		 1527/*
1528 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1529 * embedded controller) as EEPROM reader; each read is a series of pulses
1530 * to/from the EEPROM chip, not a single event, so even reads could conflict
1531 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1532 * simply claims ownership, which should be safe when this function is called
1533 * (i.e. before loading uCode!).
1534 */
1535static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1536{
1537 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1538 return 0;
1539}
1540
b481de9c 1541/**
bb8c093b 1542 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1543 *
6440adb5 1544 * Load the EEPROM contents from adapter into priv->eeprom
b481de9c
ZY		 1545 *
1546 * NOTE: This routine uses the non-debug IO access functions.
1547 */
bb8c093b 1548int iwl3945_eeprom_init(struct iwl3945_priv *priv)
b481de9c 1549{
58ff6d4d 1550 u16 *e = (u16 *)&priv->eeprom;
bb8c093b 1551 u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
b481de9c
ZY		 1552 u32 r;
1553 int sz = sizeof(priv->eeprom);
1554 int rc;
1555 int i;
1556 u16 addr;
1557
1558 /* The EEPROM structure has several padding buffers within it
1559 * and when adding new EEPROM maps is subject to programmer errors
1560 * which may be very difficult to identify without explicitly
1561 * checking the resulting size of the eeprom map. */
1562 BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1563
1564 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
1565 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
1566 return -ENOENT;
1567 }
1568
6440adb5 1569 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
bb8c093b 1570 rc = iwl3945_eeprom_acquire_semaphore(priv);
b481de9c 1571 if (rc < 0) {
91e17473 1572 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY		 1573 return -ENOENT;
1574 }
1575
1576 /* eeprom is an array of 16bit values */
1577 for (addr = 0; addr < sz; addr += sizeof(u16)) {
bb8c093b
CH		 1578 _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
1579 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
b481de9c
ZY		 1580
1581 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1582 i += IWL_EEPROM_ACCESS_DELAY) {
bb8c093b 1583 r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
b481de9c
ZY		 1584 if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1585 break;
1586 udelay(IWL_EEPROM_ACCESS_DELAY);
1587 }
1588
1589 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
1590 IWL_ERROR("Time out reading EEPROM[%d]", addr);
1591 return -ETIMEDOUT;
1592 }
58ff6d4d 1593 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY		 1594 }
1595
1596 return 0;
1597}
1598
bb8c093b 1599static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 1600{
1601 if (priv->hw_setting.shared_virt)
1602 pci_free_consistent(priv->pci_dev,
bb8c093b 1603 sizeof(struct iwl3945_shared),
b481de9c
ZY		 1604 priv->hw_setting.shared_virt,
1605 priv->hw_setting.shared_phys);
1606}
1607
1608/**
bb8c093b 1609 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1610 *
1611 * return : set the bit for each supported rate insert in ie
1612 */
bb8c093b 1613static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1614 u16 basic_rate, int *left)
b481de9c
ZY		 1615{
1616 u16 ret_rates = 0, bit;
1617 int i;
c7c46676
TW		 1618 u8 *cnt = ie;
1619 u8 *rates = ie + 1;
b481de9c
ZY		 1620
1621 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1622 if (bit & supported_rate) {
1623 ret_rates |= bit;
bb8c093b 1624 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW		 1625 ((bit & basic_rate) ? 0x80 : 0x00);
1626 (*cnt)++;
1627 (*left)--;
1628 if ((*left <= 0) ||
1629 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1630 break;
1631 }
1632 }
1633
1634 return ret_rates;
1635}
1636
1637/**
bb8c093b 1638 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1639 */
bb8c093b 1640static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
b481de9c
ZY		 1641 struct ieee80211_mgmt *frame,
1642 int left, int is_direct)
1643{
1644 int len = 0;
1645 u8 *pos = NULL;
c7c46676 1646 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY		 1647
1648 /* Make sure there is enough space for the probe request,
1649 * two mandatory IEs and the data */
1650 left -= 24;
1651 if (left < 0)
1652 return 0;
1653 len += 24;
1654
1655 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1656 memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c 1657 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1658 memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
b481de9c
ZY		 1659 frame->seq_ctrl = 0;
1660
1661 /* fill in our indirect SSID IE */
1662 /* ...next IE... */
1663
1664 left -= 2;
1665 if (left < 0)
1666 return 0;
1667 len += 2;
1668 pos = &(frame->u.probe_req.variable[0]);
1669 *pos++ = WLAN_EID_SSID;
1670 *pos++ = 0;
1671
1672 /* fill in our direct SSID IE... */
1673 if (is_direct) {
1674 /* ...next IE... */
1675 left -= 2 + priv->essid_len;
1676 if (left < 0)
1677 return 0;
1678 /* ... fill it in... */
1679 *pos++ = WLAN_EID_SSID;
1680 *pos++ = priv->essid_len;
1681 memcpy(pos, priv->essid, priv->essid_len);
1682 pos += priv->essid_len;
1683 len += 2 + priv->essid_len;
1684 }
1685
1686 /* fill in supported rate */
1687 /* ...next IE... */
1688 left -= 2;
1689 if (left < 0)
1690 return 0;
c7c46676 1691
b481de9c
ZY		 1692 /* ... fill it in... */
1693 *pos++ = WLAN_EID_SUPP_RATES;
1694 *pos = 0;
c7c46676
TW		 1695
1696 priv->active_rate = priv->rates_mask;
1697 active_rates = priv->active_rate;
b481de9c
ZY		 1698 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1699
c7c46676 1700 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1701 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW		 1702 priv->active_rate_basic, &left);
1703 active_rates &= ~ret_rates;
1704
bb8c093b 1705 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW		 1706 priv->active_rate_basic, &left);
1707 active_rates &= ~ret_rates;
1708
b481de9c
ZY		 1709 len += 2 + *pos;
1710 pos += (*pos) + 1;
c7c46676 1711 if (active_rates == 0)
b481de9c
ZY		 1712 goto fill_end;
1713
1714 /* fill in supported extended rate */
1715 /* ...next IE... */
1716 left -= 2;
1717 if (left < 0)
1718 return 0;
1719 /* ... fill it in... */
1720 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1721 *pos = 0;
bb8c093b 1722 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1723 priv->active_rate_basic, &left);
b481de9c
ZY		 1724 if (*pos > 0)
1725 len += 2 + *pos;
1726
1727 fill_end:
1728 return (u16)len;
1729}
1730
1731/*
1732 * QoS support
1733*/
bb8c093b
CH		 1734static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1735 struct iwl3945_qosparam_cmd *qos)
b481de9c
ZY		 1736{
1737
bb8c093b
CH		 1738 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1739 sizeof(struct iwl3945_qosparam_cmd), qos);
b481de9c
ZY		 1740}
1741
bb8c093b 1742static void iwl3945_reset_qos(struct iwl3945_priv *priv)
b481de9c
ZY		 1743{
1744 u16 cw_min = 15;
1745 u16 cw_max = 1023;
1746 u8 aifs = 2;
1747 u8 is_legacy = 0;
1748 unsigned long flags;
1749 int i;
1750
1751 spin_lock_irqsave(&priv->lock, flags);
1752 priv->qos_data.qos_active = 0;
1753
1754 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
1755 if (priv->qos_data.qos_enable)
1756 priv->qos_data.qos_active = 1;
1757 if (!(priv->active_rate & 0xfff0)) {
1758 cw_min = 31;
1759 is_legacy = 1;
1760 }
1761 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
1762 if (priv->qos_data.qos_enable)
1763 priv->qos_data.qos_active = 1;
1764 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1765 cw_min = 31;
1766 is_legacy = 1;
1767 }
1768
1769 if (priv->qos_data.qos_active)
1770 aifs = 3;
1771
1772 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1773 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1774 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1775 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1776 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1777
1778 if (priv->qos_data.qos_active) {
1779 i = 1;
1780 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1781 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1782 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1783 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1784 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1785
1786 i = 2;
1787 priv->qos_data.def_qos_parm.ac[i].cw_min =
1788 cpu_to_le16((cw_min + 1) / 2 - 1);
1789 priv->qos_data.def_qos_parm.ac[i].cw_max =
1790 cpu_to_le16(cw_max);
1791 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1792 if (is_legacy)
1793 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1794 cpu_to_le16(6016);
1795 else
1796 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1797 cpu_to_le16(3008);
1798 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1799
1800 i = 3;
1801 priv->qos_data.def_qos_parm.ac[i].cw_min =
1802 cpu_to_le16((cw_min + 1) / 4 - 1);
1803 priv->qos_data.def_qos_parm.ac[i].cw_max =
1804 cpu_to_le16((cw_max + 1) / 2 - 1);
1805 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1806 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1807 if (is_legacy)
1808 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1809 cpu_to_le16(3264);
1810 else
1811 priv->qos_data.def_qos_parm.ac[i].edca_txop =
1812 cpu_to_le16(1504);
1813 } else {
1814 for (i = 1; i < 4; i++) {
1815 priv->qos_data.def_qos_parm.ac[i].cw_min =
1816 cpu_to_le16(cw_min);
1817 priv->qos_data.def_qos_parm.ac[i].cw_max =
1818 cpu_to_le16(cw_max);
1819 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1820 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1821 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1822 }
1823 }
1824 IWL_DEBUG_QOS("set QoS to default \n");
1825
1826 spin_unlock_irqrestore(&priv->lock, flags);
1827}
1828
bb8c093b 1829static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
b481de9c
ZY		 1830{
1831 unsigned long flags;
1832
b481de9c
ZY		 1833 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1834 return;
1835
1836 if (!priv->qos_data.qos_enable)
1837 return;
1838
1839 spin_lock_irqsave(&priv->lock, flags);
1840 priv->qos_data.def_qos_parm.qos_flags = 0;
1841
1842 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1843 !priv->qos_data.qos_cap.q_AP.txop_request)
1844 priv->qos_data.def_qos_parm.qos_flags |=
1845 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1846
1847 if (priv->qos_data.qos_active)
1848 priv->qos_data.def_qos_parm.qos_flags |=
1849 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1850
1851 spin_unlock_irqrestore(&priv->lock, flags);
1852
bb8c093b 1853 if (force || iwl3945_is_associated(priv)) {
b481de9c
ZY		 1854 IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
1855 priv->qos_data.qos_active);
1856
bb8c093b 1857 iwl3945_send_qos_params_command(priv,
b481de9c
ZY		 1858 &(priv->qos_data.def_qos_parm));
1859 }
1860}
1861
b481de9c
ZY		 1862/*
1863 * Power management (not Tx power!) functions
1864 */
1865#define MSEC_TO_USEC 1024
1866
1867#define NOSLP __constant_cpu_to_le32(0)
1868#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
1869#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1870#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1871 __constant_cpu_to_le32(X1), \
1872 __constant_cpu_to_le32(X2), \
1873 __constant_cpu_to_le32(X3), \
1874 __constant_cpu_to_le32(X4)}
1875
1876
1877/* default power management (not Tx power) table values */
1878/* for tim 0-10 */
bb8c093b 1879static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY		 1880 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1881 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1882 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1883 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1884 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1885 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1886};
1887
1888/* for tim > 10 */
bb8c093b 1889static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY		 1890 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1891 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1892 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1893 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1894 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1895 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1896 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1897 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1898 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1899 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1900};
1901
bb8c093b 1902int iwl3945_power_init_handle(struct iwl3945_priv *priv)
b481de9c
ZY		 1903{
1904 int rc = 0, i;
bb8c093b
CH		 1905 struct iwl3945_power_mgr *pow_data;
1906 int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY		 1907 u16 pci_pm;
1908
1909 IWL_DEBUG_POWER("Initialize power \n");
1910
1911 pow_data = &(priv->power_data);
1912
1913 memset(pow_data, 0, sizeof(*pow_data));
1914
1915 pow_data->active_index = IWL_POWER_RANGE_0;
1916 pow_data->dtim_val = 0xffff;
1917
1918 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1919 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1920
1921 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1922 if (rc != 0)
1923 return 0;
1924 else {
bb8c093b 1925 struct iwl3945_powertable_cmd *cmd;
b481de9c
ZY		 1926
1927 IWL_DEBUG_POWER("adjust power command flags\n");
1928
1929 for (i = 0; i < IWL_POWER_AC; i++) {
1930 cmd = &pow_data->pwr_range_0[i].cmd;
1931
1932 if (pci_pm & 0x1)
1933 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1934 else
1935 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1936 }
1937 }
1938 return rc;
1939}
1940
bb8c093b
CH		 1941static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
1942 struct iwl3945_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 1943{
1944 int rc = 0, i;
1945 u8 skip;
1946 u32 max_sleep = 0;
bb8c093b 1947 struct iwl3945_power_vec_entry *range;
b481de9c 1948 u8 period = 0;
bb8c093b 1949 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY		 1950
1951 if (mode > IWL_POWER_INDEX_5) {
1952 IWL_DEBUG_POWER("Error invalid power mode \n");
1953 return -1;
1954 }
1955 pow_data = &(priv->power_data);
1956
1957 if (pow_data->active_index == IWL_POWER_RANGE_0)
1958 range = &pow_data->pwr_range_0[0];
1959 else
1960 range = &pow_data->pwr_range_1[1];
1961
bb8c093b 1962 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY		 1963
1964#ifdef IWL_MAC80211_DISABLE
1965 if (priv->assoc_network != NULL) {
1966 unsigned long flags;
1967
1968 period = priv->assoc_network->tim.tim_period;
1969 }
1970#endif /*IWL_MAC80211_DISABLE */
1971 skip = range[mode].no_dtim;
1972
1973 if (period == 0) {
1974 period = 1;
1975 skip = 0;
1976 }
1977
1978 if (skip == 0) {
1979 max_sleep = period;
1980 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1981 } else {
1982 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1983 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1984 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1985 }
1986
1987 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1988 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1989 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1990 }
1991
1992 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1993 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1994 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1995 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1996 le32_to_cpu(cmd->sleep_interval[0]),
1997 le32_to_cpu(cmd->sleep_interval[1]),
1998 le32_to_cpu(cmd->sleep_interval[2]),
1999 le32_to_cpu(cmd->sleep_interval[3]),
2000 le32_to_cpu(cmd->sleep_interval[4]));
2001
2002 return rc;
2003}
2004
bb8c093b 2005static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
b481de9c 2006{
9a62f73b 2007 u32 uninitialized_var(final_mode);
b481de9c 2008 int rc;
bb8c093b 2009 struct iwl3945_powertable_cmd cmd;
b481de9c
ZY		 2010
2011 /* If on battery, set to 3,
01ebd063 2012 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 2013 * else user level */
2014 switch (mode) {
2015 case IWL_POWER_BATTERY:
2016 final_mode = IWL_POWER_INDEX_3;
2017 break;
2018 case IWL_POWER_AC:
2019 final_mode = IWL_POWER_MODE_CAM;
2020 break;
2021 default:
2022 final_mode = mode;
2023 break;
2024 }
2025
bb8c093b 2026 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 2027
bb8c093b 2028 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 2029
2030 if (final_mode == IWL_POWER_MODE_CAM)
2031 clear_bit(STATUS_POWER_PMI, &priv->status);
2032 else
2033 set_bit(STATUS_POWER_PMI, &priv->status);
2034
2035 return rc;
2036}
2037
bb8c093b 2038int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 2039{
2040 /* Filter incoming packets to determine if they are targeted toward
2041 * this network, discarding packets coming from ourselves */
2042 switch (priv->iw_mode) {
2043 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
2044 /* packets from our adapter are dropped (echo) */
2045 if (!compare_ether_addr(header->addr2, priv->mac_addr))
2046 return 0;
2047 /* {broad,multi}cast packets to our IBSS go through */
2048 if (is_multicast_ether_addr(header->addr1))
2049 return !compare_ether_addr(header->addr3, priv->bssid);
2050 /* packets to our adapter go through */
2051 return !compare_ether_addr(header->addr1, priv->mac_addr);
2052 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
2053 /* packets from our adapter are dropped (echo) */
2054 if (!compare_ether_addr(header->addr3, priv->mac_addr))
2055 return 0;
2056 /* {broad,multi}cast packets to our BSS go through */
2057 if (is_multicast_ether_addr(header->addr1))
2058 return !compare_ether_addr(header->addr2, priv->bssid);
2059 /* packets to our adapter go through */
2060 return !compare_ether_addr(header->addr1, priv->mac_addr);
69dc5d9d
TW		 2061 default:
2062 return 1;
b481de9c
ZY		 2063 }
2064
2065 return 1;
2066}
2067
b481de9c 2068/**
bb8c093b 2069 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 2070 *
2071 * NOTE: priv->mutex is not required before calling this function
2072 */
bb8c093b 2073static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
b481de9c
ZY		 2074{
2075 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
2076 clear_bit(STATUS_SCANNING, &priv->status);
2077 return 0;
2078 }
2079
2080 if (test_bit(STATUS_SCANNING, &priv->status)) {
2081 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2082 IWL_DEBUG_SCAN("Queuing scan abort.\n");
2083 set_bit(STATUS_SCAN_ABORTING, &priv->status);
2084 queue_work(priv->workqueue, &priv->abort_scan);
2085
2086 } else
2087 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
2088
2089 return test_bit(STATUS_SCANNING, &priv->status);
2090 }
2091
2092 return 0;
2093}
2094
2095/**
bb8c093b 2096 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 2097 * @ms: amount of time to wait (in milliseconds) for scan to abort
2098 *
2099 * NOTE: priv->mutex must be held before calling this function
2100 */
bb8c093b 2101static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
b481de9c
ZY		 2102{
2103 unsigned long now = jiffies;
2104 int ret;
2105
bb8c093b 2106 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY		 2107 if (ret && ms) {
2108 mutex_unlock(&priv->mutex);
2109 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2110 test_bit(STATUS_SCANNING, &priv->status))
2111 msleep(1);
2112 mutex_lock(&priv->mutex);
2113
2114 return test_bit(STATUS_SCANNING, &priv->status);
2115 }
2116
2117 return ret;
2118}
2119
bb8c093b 2120static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 2121{
2122 /* Reset ieee stats */
2123
2124 /* We don't reset the net_device_stats (ieee->stats) on
2125 * re-association */
2126
2127 priv->last_seq_num = -1;
2128 priv->last_frag_num = -1;
2129 priv->last_packet_time = 0;
2130
bb8c093b 2131 iwl3945_scan_cancel(priv);
b481de9c
ZY		 2132}
2133
2134#define MAX_UCODE_BEACON_INTERVAL 1024
2135#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
2136
bb8c093b 2137static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 2138{
2139 u16 new_val = 0;
2140 u16 beacon_factor = 0;
2141
2142 beacon_factor =
2143 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2144 / MAX_UCODE_BEACON_INTERVAL;
2145 new_val = beacon_val / beacon_factor;
2146
2147 return cpu_to_le16(new_val);
2148}
2149
bb8c093b 2150static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
b481de9c
ZY		 2151{
2152 u64 interval_tm_unit;
2153 u64 tsf, result;
2154 unsigned long flags;
2155 struct ieee80211_conf *conf = NULL;
2156 u16 beacon_int = 0;
2157
2158 conf = ieee80211_get_hw_conf(priv->hw);
2159
2160 spin_lock_irqsave(&priv->lock, flags);
2161 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2162 priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2163
2164 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2165
2166 tsf = priv->timestamp1;
2167 tsf = ((tsf << 32) | priv->timestamp0);
2168
2169 beacon_int = priv->beacon_int;
2170 spin_unlock_irqrestore(&priv->lock, flags);
2171
2172 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
2173 if (beacon_int == 0) {
2174 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2175 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2176 } else {
2177 priv->rxon_timing.beacon_interval =
2178 cpu_to_le16(beacon_int);
2179 priv->rxon_timing.beacon_interval =
bb8c093b 2180 iwl3945_adjust_beacon_interval(
b481de9c
ZY		 2181 le16_to_cpu(priv->rxon_timing.beacon_interval));
2182 }
2183
2184 priv->rxon_timing.atim_window = 0;
2185 } else {
2186 priv->rxon_timing.beacon_interval =
bb8c093b 2187 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 2188 /* TODO: we need to get atim_window from upper stack
2189 * for now we set to 0 */
2190 priv->rxon_timing.atim_window = 0;
2191 }
2192
2193 interval_tm_unit =
2194 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2195 result = do_div(tsf, interval_tm_unit);
2196 priv->rxon_timing.beacon_init_val =
2197 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2198
2199 IWL_DEBUG_ASSOC
2200 ("beacon interval %d beacon timer %d beacon tim %d\n",
2201 le16_to_cpu(priv->rxon_timing.beacon_interval),
2202 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2203 le16_to_cpu(priv->rxon_timing.atim_window));
2204}
2205
bb8c093b 2206static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
b481de9c
ZY		 2207{
2208 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
2209 IWL_ERROR("APs don't scan.\n");
2210 return 0;
2211 }
2212
bb8c093b 2213 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 2214 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2215 return -EIO;
2216 }
2217
2218 if (test_bit(STATUS_SCANNING, &priv->status)) {
2219 IWL_DEBUG_SCAN("Scan already in progress.\n");
2220 return -EAGAIN;
2221 }
2222
2223 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2224 IWL_DEBUG_SCAN("Scan request while abort pending. "
2225 "Queuing.\n");
2226 return -EAGAIN;
2227 }
2228
2229 IWL_DEBUG_INFO("Starting scan...\n");
66b5004d
RR		 2230 if (priv->cfg->sku & IWL_SKU_G)
2231 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
2232 if (priv->cfg->sku & IWL_SKU_A)
2233 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 2234 set_bit(STATUS_SCANNING, &priv->status);
2235 priv->scan_start = jiffies;
2236 priv->scan_pass_start = priv->scan_start;
2237
2238 queue_work(priv->workqueue, &priv->request_scan);
2239
2240 return 0;
2241}
2242
bb8c093b 2243static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
b481de9c 2244{
bb8c093b 2245 struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 2246
2247 if (hw_decrypt)
2248 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2249 else
2250 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2251
2252 return 0;
2253}
2254
8318d78a
JB		 2255static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2256 enum ieee80211_band band)
b481de9c 2257{
8318d78a 2258 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY		 2259 priv->staging_rxon.flags &=
2260 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2261 | RXON_FLG_CCK_MSK);
2262 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2263 } else {
bb8c093b 2264 /* Copied from iwl3945_bg_post_associate() */
b481de9c
ZY		 2265 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2266 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2267 else
2268 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2269
2270 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
2271 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2272
2273 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2274 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2275 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2276 }
2277}
2278
2279/*
01ebd063 2280 * initialize rxon structure with default values from eeprom
b481de9c 2281 */
bb8c093b 2282static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
b481de9c 2283{
bb8c093b 2284 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 2285
2286 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2287
2288 switch (priv->iw_mode) {
2289 case IEEE80211_IF_TYPE_AP:
2290 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2291 break;
2292
2293 case IEEE80211_IF_TYPE_STA:
2294 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2295 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2296 break;
2297
2298 case IEEE80211_IF_TYPE_IBSS:
2299 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2300 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2301 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2302 RXON_FILTER_ACCEPT_GRP_MSK;
2303 break;
2304
2305 case IEEE80211_IF_TYPE_MNTR:
2306 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2307 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2308 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2309 break;
69dc5d9d
TW		 2310 default:
2311 IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
2312 break;
b481de9c
ZY		 2313 }
2314
2315#if 0
2316 /* TODO: Figure out when short_preamble would be set and cache from
2317 * that */
2318 if (!hw_to_local(priv->hw)->short_preamble)
2319 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2320 else
2321 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2322#endif
2323
8318d78a 2324 ch_info = iwl3945_get_channel_info(priv, priv->band,
25b3f57c 2325 le16_to_cpu(priv->active_rxon.channel));
b481de9c
ZY		 2326
2327 if (!ch_info)
2328 ch_info = &priv->channel_info[0];
2329
2330 /*
2331 * in some case A channels are all non IBSS
2332 * in this case force B/G channel
2333 */
2334 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
2335 !(is_channel_ibss(ch_info)))
2336 ch_info = &priv->channel_info[0];
2337
2338 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2339 if (is_channel_a_band(ch_info))
8318d78a 2340 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 2341 else
8318d78a 2342 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 2343
8318d78a 2344 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY		 2345
2346 priv->staging_rxon.ofdm_basic_rates =
2347 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2348 priv->staging_rxon.cck_basic_rates =
2349 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2350}
2351
bb8c093b 2352static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
b481de9c 2353{
b481de9c 2354 if (mode == IEEE80211_IF_TYPE_IBSS) {
bb8c093b 2355 const struct iwl3945_channel_info *ch_info;
b481de9c 2356
bb8c093b 2357 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2358 priv->band,
b481de9c
ZY		 2359 le16_to_cpu(priv->staging_rxon.channel));
2360
2361 if (!ch_info || !is_channel_ibss(ch_info)) {
2362 IWL_ERROR("channel %d not IBSS channel\n",
2363 le16_to_cpu(priv->staging_rxon.channel));
2364 return -EINVAL;
2365 }
2366 }
2367
b481de9c
ZY		 2368 priv->iw_mode = mode;
2369
bb8c093b 2370 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 2371 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2372
bb8c093b 2373 iwl3945_clear_stations_table(priv);
b481de9c 2374
fde3571f
MA		 2375 /* dont commit rxon if rf-kill is on*/
2376 if (!iwl3945_is_ready_rf(priv))
2377 return -EAGAIN;
2378
2379 cancel_delayed_work(&priv->scan_check);
2380 if (iwl3945_scan_cancel_timeout(priv, 100)) {
2381 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2382 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2383 return -EAGAIN;
2384 }
2385
bb8c093b 2386 iwl3945_commit_rxon(priv);
b481de9c
ZY		 2387
2388 return 0;
2389}
2390
bb8c093b 2391static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
e039fa4a 2392 struct ieee80211_tx_info *info,
bb8c093b 2393 struct iwl3945_cmd *cmd,
b481de9c
ZY		 2394 struct sk_buff *skb_frag,
2395 int last_frag)
2396{
1c014420 2397 struct iwl3945_hw_key *keyinfo =
e039fa4a 2398 &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
b481de9c
ZY		 2399
2400 switch (keyinfo->alg) {
2401 case ALG_CCMP:
2402 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2403 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2404 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2405 break;
2406
2407 case ALG_TKIP:
2408#if 0
2409 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2410
2411 if (last_frag)
2412 memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2413 8);
2414 else
2415 memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2416#endif
2417 break;
2418
2419 case ALG_WEP:
2420 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 2421 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY		 2422
2423 if (keyinfo->keylen == 13)
2424 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2425
2426 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2427
2428 IWL_DEBUG_TX("Configuring packet for WEP encryption "
e039fa4a 2429 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY		 2430 break;
2431
b481de9c
ZY		 2432 default:
2433 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2434 break;
2435 }
2436}
2437
2438/*
2439 * handle build REPLY_TX command notification.
2440 */
bb8c093b
CH		 2441static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2442 struct iwl3945_cmd *cmd,
e039fa4a 2443 struct ieee80211_tx_info *info,
b481de9c
ZY		 2444 struct ieee80211_hdr *hdr,
2445 int is_unicast, u8 std_id)
2446{
fd7c8a40 2447 __le16 fc = hdr->frame_control;
b481de9c
ZY		 2448 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2449
2450 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 2451 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 2452 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 2453 if (ieee80211_is_mgmt(fc))
b481de9c 2454 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 2455 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY		 2456 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2457 tx_flags |= TX_CMD_FLG_TSF_MSK;
2458 } else {
2459 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2460 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2461 }
2462
2463 cmd->cmd.tx.sta_id = std_id;
8b7b1e05 2464 if (ieee80211_has_morefrags(fc))
b481de9c
ZY		 2465 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2466
fd7c8a40
HH		 2467 if (ieee80211_is_data_qos(fc)) {
2468 u8 *qc = ieee80211_get_qos_ctl(hdr);
54dbb525 2469 cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
b481de9c 2470 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2471 } else {
b481de9c 2472 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2473 }
b481de9c 2474
e039fa4a 2475 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
b481de9c
ZY		 2476 tx_flags |= TX_CMD_FLG_RTS_MSK;
2477 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e039fa4a 2478 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
b481de9c
ZY		 2479 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2480 tx_flags |= TX_CMD_FLG_CTS_MSK;
2481 }
2482
2483 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2484 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2485
2486 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH		 2487 if (ieee80211_is_mgmt(fc)) {
2488 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
bc434dd2 2489 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2490 else
bc434dd2 2491 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2492 } else {
b481de9c 2493 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
ab53d8af
MA		 2494#ifdef CONFIG_IWL3945_LEDS
2495 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2496#endif
2497 }
b481de9c
ZY		 2498
2499 cmd->cmd.tx.driver_txop = 0;
2500 cmd->cmd.tx.tx_flags = tx_flags;
2501 cmd->cmd.tx.next_frame_len = 0;
2502}
2503
6440adb5
CB		 2504/**
2505 * iwl3945_get_sta_id - Find station's index within station table
2506 */
bb8c093b 2507static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY		 2508{
2509 int sta_id;
2510 u16 fc = le16_to_cpu(hdr->frame_control);
2511
6440adb5 2512 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2513 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2514 is_multicast_ether_addr(hdr->addr1))
2515 return priv->hw_setting.bcast_sta_id;
2516
2517 switch (priv->iw_mode) {
2518
6440adb5
CB		 2519 /* If we are a client station in a BSS network, use the special
2520 * AP station entry (that's the only station we communicate with) */
b481de9c
ZY		 2521 case IEEE80211_IF_TYPE_STA:
2522 return IWL_AP_ID;
2523
2524 /* If we are an AP, then find the station, or use BCAST */
2525 case IEEE80211_IF_TYPE_AP:
bb8c093b 2526 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2527 if (sta_id != IWL_INVALID_STATION)
2528 return sta_id;
2529 return priv->hw_setting.bcast_sta_id;
2530
6440adb5
CB		 2531 /* If this frame is going out to an IBSS network, find the station,
2532 * or create a new station table entry */
0795af57
JP		 2533 case IEEE80211_IF_TYPE_IBSS: {
2534 DECLARE_MAC_BUF(mac);
2535
6440adb5 2536 /* Create new station table entry */
bb8c093b 2537 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2538 if (sta_id != IWL_INVALID_STATION)
2539 return sta_id;
2540
bb8c093b 2541 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY		 2542
2543 if (sta_id != IWL_INVALID_STATION)
2544 return sta_id;
2545
0795af57 2546 IWL_DEBUG_DROP("Station %s not in station map. "
b481de9c 2547 "Defaulting to broadcast...\n",
0795af57 2548 print_mac(mac, hdr->addr1));
bb8c093b 2549 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c 2550 return priv->hw_setting.bcast_sta_id;
0795af57 2551 }
914233d6
SG		 2552 /* If we are in monitor mode, use BCAST. This is required for
2553 * packet injection. */
2554 case IEEE80211_IF_TYPE_MNTR:
2555 return priv->hw_setting.bcast_sta_id;
2556
b481de9c 2557 default:
01ebd063 2558 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
b481de9c
ZY		 2559 return priv->hw_setting.bcast_sta_id;
2560 }
2561}
2562
2563/*
2564 * start REPLY_TX command process
2565 */
e039fa4a 2566static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
b481de9c
ZY		 2567{
2568 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 2569 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bb8c093b 2570 struct iwl3945_tfd_frame *tfd;
b481de9c 2571 u32 *control_flags;
e2530083 2572 int txq_id = skb_get_queue_mapping(skb);
bb8c093b
CH		 2573 struct iwl3945_tx_queue *txq = NULL;
2574 struct iwl3945_queue *q = NULL;
b481de9c
ZY		 2575 dma_addr_t phys_addr;
2576 dma_addr_t txcmd_phys;
bb8c093b 2577 struct iwl3945_cmd *out_cmd = NULL;
54dbb525
TW		 2578 u16 len, idx, len_org, hdr_len;
2579 u8 id;
2580 u8 unicast;
b481de9c 2581 u8 sta_id;
54dbb525 2582 u8 tid = 0;
b481de9c 2583 u16 seq_number = 0;
fd7c8a40 2584 __le16 fc;
b481de9c 2585 u8 wait_write_ptr = 0;
54dbb525 2586 u8 *qc = NULL;
b481de9c
ZY		 2587 unsigned long flags;
2588 int rc;
2589
2590 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2591 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 2592 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2593 goto drop_unlock;
2594 }
2595
e039fa4a 2596 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY		 2597 IWL_ERROR("ERROR: No TX rate available.\n");
2598 goto drop_unlock;
2599 }
2600
2601 unicast = !is_multicast_ether_addr(hdr->addr1);
2602 id = 0;
2603
fd7c8a40 2604 fc = hdr->frame_control;
b481de9c 2605
c8b0e6e1 2606#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 2607 if (ieee80211_is_auth(fc))
2608 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 2609 else if (ieee80211_is_assoc_req(fc))
b481de9c 2610 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 2611 else if (ieee80211_is_reassoc_req(fc))
b481de9c
ZY		 2612 IWL_DEBUG_TX("Sending REASSOC frame\n");
2613#endif
2614
7878a5a4 2615 /* drop all data frame if we are not associated */
914233d6
SG		 2616 if (ieee80211_is_data(fc) &&
2617 (priv->iw_mode != IEEE80211_IF_TYPE_MNTR) && /* packet injection */
2618 (!iwl3945_is_associated(priv) ||
2619 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id))) {
bb8c093b 2620 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY		 2621 goto drop_unlock;
2622 }
2623
2624 spin_unlock_irqrestore(&priv->lock, flags);
2625
fd7c8a40 2626 hdr_len = ieee80211_get_hdrlen(le16_to_cpu(fc));
6440adb5
CB		 2627
2628 /* Find (or create) index into station table for destination station */
bb8c093b 2629 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2630 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 2631 DECLARE_MAC_BUF(mac);
2632
2633 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
2634 print_mac(mac, hdr->addr1));
b481de9c
ZY		 2635 goto drop;
2636 }
2637
2638 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2639
fd7c8a40
HH		 2640 if (ieee80211_is_data_qos(fc)) {
2641 qc = ieee80211_get_qos_ctl(hdr);
54dbb525 2642 tid = qc[0] & 0xf;
b481de9c
ZY		 2643 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2644 IEEE80211_SCTL_SEQ;
2645 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2646 (hdr->seq_ctrl &
2647 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2648 seq_number += 0x10;
2649 }
6440adb5
CB		 2650
2651 /* Descriptor for chosen Tx queue */
b481de9c
ZY		 2652 txq = &priv->txq[txq_id];
2653 q = &txq->q;
2654
2655 spin_lock_irqsave(&priv->lock, flags);
2656
6440adb5 2657 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2658 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 2659 memset(tfd, 0, sizeof(*tfd));
2660 control_flags = (u32 *) tfd;
fc4b6853 2661 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2662
6440adb5 2663 /* Set up driver data for this TFD */
bb8c093b 2664 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
fc4b6853 2665 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB		 2666
2667 /* Init first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY		 2668 out_cmd = &txq->cmd[idx];
2669 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2670 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB		 2671
2672 /*
2673 * Set up the Tx-command (not MAC!) header.
2674 * Store the chosen Tx queue and TFD index within the sequence field;
2675 * after Tx, uCode's Tx response will return this value so driver can
2676 * locate the frame within the tx queue and do post-tx processing.
2677 */
b481de9c
ZY		 2678 out_cmd->hdr.cmd = REPLY_TX;
2679 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2680 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB		 2681
2682 /* Copy MAC header from skb into command buffer */
b481de9c
ZY		 2683 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2684
6440adb5
CB		 2685 /*
2686 * Use the first empty entry in this queue's command buffer array
2687 * to contain the Tx command and MAC header concatenated together
2688 * (payload data will be in another buffer).
2689 * Size of this varies, due to varying MAC header length.
2690 * If end is not dword aligned, we'll have 2 extra bytes at the end
2691 * of the MAC header (device reads on dword boundaries).
2692 * We'll tell device about this padding later.
2693 */
b481de9c 2694 len = priv->hw_setting.tx_cmd_len +
bb8c093b 2695 sizeof(struct iwl3945_cmd_header) + hdr_len;
b481de9c
ZY		 2696
2697 len_org = len;
2698 len = (len + 3) & ~3;
2699
2700 if (len_org != len)
2701 len_org = 1;
2702 else
2703 len_org = 0;
2704
6440adb5
CB		 2705 /* Physical address of this Tx command's header (not MAC header!),
2706 * within command buffer array. */
bb8c093b
CH		 2707 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2708 offsetof(struct iwl3945_cmd, hdr);
b481de9c 2709
6440adb5
CB		 2710 /* Add buffer containing Tx command and MAC(!) header to TFD's
2711 * first entry */
bb8c093b 2712 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c 2713
e039fa4a
JB		 2714 if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT))
2715 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
b481de9c 2716
6440adb5
CB		 2717 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2718 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 2719 len = skb->len - hdr_len;
2720 if (len) {
2721 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2722 len, PCI_DMA_TODEVICE);
bb8c093b 2723 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 2724 }
2725
b481de9c 2726 if (!len)
6440adb5 2727 /* If there is no payload, then we use only one Tx buffer */
b481de9c
ZY		 2728 *control_flags = TFD_CTL_COUNT_SET(1);
2729 else
6440adb5
CB		 2730 /* Else use 2 buffers.
2731 * Tell 3945 about any padding after MAC header */
b481de9c
ZY		 2732 *control_flags = TFD_CTL_COUNT_SET(2) |
2733 TFD_CTL_PAD_SET(U32_PAD(len));
2734
6440adb5 2735 /* Total # bytes to be transmitted */
b481de9c
ZY		 2736 len = (u16)skb->len;
2737 out_cmd->cmd.tx.len = cpu_to_le16(len);
2738
2739 /* TODO need this for burst mode later on */
e039fa4a 2740 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
b481de9c
ZY		 2741
2742 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 2743 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
b481de9c
ZY		 2744
2745 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2746 out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2747
8b7b1e05 2748 if (!ieee80211_has_morefrags(hdr->frame_control)) {
b481de9c
ZY		 2749 txq->need_update = 1;
2750 if (qc) {
b481de9c
ZY		 2751 priv->stations[sta_id].tid[tid].seq_number = seq_number;
2752 }
2753 } else {
2754 wait_write_ptr = 1;
2755 txq->need_update = 0;
2756 }
2757
bb8c093b 2758 iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY		 2759 sizeof(out_cmd->cmd.tx));
2760
bb8c093b 2761 iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
fd7c8a40 2762 ieee80211_get_hdrlen(le16_to_cpu(fc)));
b481de9c 2763
6440adb5 2764 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2765 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2766 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2767 spin_unlock_irqrestore(&priv->lock, flags);
2768
2769 if (rc)
2770 return rc;
2771
bb8c093b 2772 if ((iwl3945_queue_space(q) < q->high_mark)
b481de9c
ZY		 2773 && priv->mac80211_registered) {
2774 if (wait_write_ptr) {
2775 spin_lock_irqsave(&priv->lock, flags);
2776 txq->need_update = 1;
bb8c093b 2777 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2778 spin_unlock_irqrestore(&priv->lock, flags);
2779 }
2780
e2530083 2781 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
b481de9c
ZY		 2782 }
2783
2784 return 0;
2785
2786drop_unlock:
2787 spin_unlock_irqrestore(&priv->lock, flags);
2788drop:
2789 return -1;
2790}
2791
bb8c093b 2792static void iwl3945_set_rate(struct iwl3945_priv *priv)
b481de9c 2793{
8318d78a 2794 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY		 2795 struct ieee80211_rate *rate;
2796 int i;
2797
8318d78a
JB		 2798 sband = iwl3945_get_band(priv, priv->band);
2799 if (!sband) {
c4ba9621
SA		 2800 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2801 return;
2802 }
b481de9c
ZY		 2803
2804 priv->active_rate = 0;
2805 priv->active_rate_basic = 0;
2806
8318d78a
JB		 2807 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2808 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2809
2810 for (i = 0; i < sband->n_bitrates; i++) {
2811 rate = &sband->bitrates[i];
2812 if ((rate->hw_value < IWL_RATE_COUNT) &&
2813 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2814 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2815 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2816 priv->active_rate |= (1 << rate->hw_value);
2817 }
b481de9c
ZY		 2818 }
2819
2820 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2821 priv->active_rate, priv->active_rate_basic);
2822
2823 /*
2824 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2825 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2826 * OFDM
2827 */
2828 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2829 priv->staging_rxon.cck_basic_rates =
2830 ((priv->active_rate_basic &
2831 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2832 else
2833 priv->staging_rxon.cck_basic_rates =
2834 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2835
2836 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2837 priv->staging_rxon.ofdm_basic_rates =
2838 ((priv->active_rate_basic &
2839 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2840 IWL_FIRST_OFDM_RATE) & 0xFF;
2841 else
2842 priv->staging_rxon.ofdm_basic_rates =
2843 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2844}
2845
bb8c093b 2846static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
b481de9c
ZY		 2847{
2848 unsigned long flags;
2849
2850 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2851 return;
2852
2853 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2854 disable_radio ? "OFF" : "ON");
2855
2856 if (disable_radio) {
bb8c093b 2857 iwl3945_scan_cancel(priv);
b481de9c
ZY		 2858 /* FIXME: This is a workaround for AP */
2859 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
2860 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2861 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 2862 CSR_UCODE_SW_BIT_RFKILL);
2863 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 2864 iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY		 2865 set_bit(STATUS_RF_KILL_SW, &priv->status);
2866 }
2867 return;
2868 }
2869
2870 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2871 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2872
2873 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2874 spin_unlock_irqrestore(&priv->lock, flags);
2875
2876 /* wake up ucode */
2877 msleep(10);
2878
2879 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 2880 iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
2881 if (!iwl3945_grab_nic_access(priv))
2882 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2883 spin_unlock_irqrestore(&priv->lock, flags);
2884
2885 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2886 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2887 "disabled by HW switch\n");
2888 return;
2889 }
2890
808e72a0
ZY		 2891 if (priv->is_open)
2892 queue_work(priv->workqueue, &priv->restart);
b481de9c
ZY		 2893 return;
2894}
2895
bb8c093b 2896void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 2897 u32 decrypt_res, struct ieee80211_rx_status *stats)
2898{
2899 u16 fc =
2900 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2901
2902 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2903 return;
2904
2905 if (!(fc & IEEE80211_FCTL_PROTECTED))
2906 return;
2907
2908 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2909 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2910 case RX_RES_STATUS_SEC_TYPE_TKIP:
2911 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2912 RX_RES_STATUS_BAD_ICV_MIC)
2913 stats->flag |= RX_FLAG_MMIC_ERROR;
2914 case RX_RES_STATUS_SEC_TYPE_WEP:
2915 case RX_RES_STATUS_SEC_TYPE_CCMP:
2916 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2917 RX_RES_STATUS_DECRYPT_OK) {
2918 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2919 stats->flag |= RX_FLAG_DECRYPTED;
2920 }
2921 break;
2922
2923 default:
2924 break;
2925 }
2926}
2927
b481de9c
ZY		 2928#define IWL_PACKET_RETRY_TIME HZ
2929
bb8c093b 2930int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 2931{
2932 u16 sc = le16_to_cpu(header->seq_ctrl);
2933 u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
2934 u16 frag = sc & IEEE80211_SCTL_FRAG;
2935 u16 *last_seq, *last_frag;
2936 unsigned long *last_time;
2937
2938 switch (priv->iw_mode) {
2939 case IEEE80211_IF_TYPE_IBSS:{
2940 struct list_head *p;
bb8c093b 2941 struct iwl3945_ibss_seq *entry = NULL;
b481de9c
ZY		 2942 u8 *mac = header->addr2;
2943 int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
2944
2945 __list_for_each(p, &priv->ibss_mac_hash[index]) {
bb8c093b 2946 entry = list_entry(p, struct iwl3945_ibss_seq, list);
b481de9c
ZY		 2947 if (!compare_ether_addr(entry->mac, mac))
2948 break;
2949 }
2950 if (p == &priv->ibss_mac_hash[index]) {
2951 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
2952 if (!entry) {
bc434dd2 2953 IWL_ERROR("Cannot malloc new mac entry\n");
b481de9c
ZY		 2954 return 0;
2955 }
2956 memcpy(entry->mac, mac, ETH_ALEN);
2957 entry->seq_num = seq;
2958 entry->frag_num = frag;
2959 entry->packet_time = jiffies;
bc434dd2 2960 list_add(&entry->list, &priv->ibss_mac_hash[index]);
b481de9c
ZY		 2961 return 0;
2962 }
2963 last_seq = &entry->seq_num;
2964 last_frag = &entry->frag_num;
2965 last_time = &entry->packet_time;
2966 break;
2967 }
2968 case IEEE80211_IF_TYPE_STA:
2969 last_seq = &priv->last_seq_num;
2970 last_frag = &priv->last_frag_num;
2971 last_time = &priv->last_packet_time;
2972 break;
2973 default:
2974 return 0;
2975 }
2976 if ((*last_seq == seq) &&
2977 time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
2978 if (*last_frag == frag)
2979 goto drop;
2980 if (*last_frag + 1 != frag)
2981 /* out-of-order fragment */
2982 goto drop;
2983 } else
2984 *last_seq = seq;
2985
2986 *last_frag = frag;
2987 *last_time = jiffies;
2988 return 0;
2989
2990 drop:
2991 return 1;
2992}
2993
c8b0e6e1 2994#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 2995
2996#include "iwl-spectrum.h"
2997
2998#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2999#define BEACON_TIME_MASK_HIGH 0xFF000000
3000#define TIME_UNIT 1024
3001
3002/*
3003 * extended beacon time format
3004 * time in usec will be changed into a 32-bit value in 8:24 format
3005 * the high 1 byte is the beacon counts
3006 * the lower 3 bytes is the time in usec within one beacon interval
3007 */
3008
bb8c093b 3009static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 3010{
3011 u32 quot;
3012 u32 rem;
3013 u32 interval = beacon_interval * 1024;
3014
3015 if (!interval || !usec)
3016 return 0;
3017
3018 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
3019 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
3020
3021 return (quot << 24) + rem;
3022}
3023
3024/* base is usually what we get from ucode with each received frame,
3025 * the same as HW timer counter counting down
3026 */
3027
bb8c093b 3028static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 3029{
3030 u32 base_low = base & BEACON_TIME_MASK_LOW;
3031 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
3032 u32 interval = beacon_interval * TIME_UNIT;
3033 u32 res = (base & BEACON_TIME_MASK_HIGH) +
3034 (addon & BEACON_TIME_MASK_HIGH);
3035
3036 if (base_low > addon_low)
3037 res += base_low - addon_low;
3038 else if (base_low < addon_low) {
3039 res += interval + base_low - addon_low;
3040 res += (1 << 24);
3041 } else
3042 res += (1 << 24);
3043
3044 return cpu_to_le32(res);
3045}
3046
bb8c093b 3047static int iwl3945_get_measurement(struct iwl3945_priv *priv,
b481de9c
ZY		 3048 struct ieee80211_measurement_params *params,
3049 u8 type)
3050{
bb8c093b
CH		 3051 struct iwl3945_spectrum_cmd spectrum;
3052 struct iwl3945_rx_packet *res;
3053 struct iwl3945_host_cmd cmd = {
b481de9c
ZY		 3054 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
3055 .data = (void *)&spectrum,
3056 .meta.flags = CMD_WANT_SKB,
3057 };
3058 u32 add_time = le64_to_cpu(params->start_time);
3059 int rc;
3060 int spectrum_resp_status;
3061 int duration = le16_to_cpu(params->duration);
3062
bb8c093b 3063 if (iwl3945_is_associated(priv))
b481de9c 3064 add_time =
bb8c093b 3065 iwl3945_usecs_to_beacons(
b481de9c
ZY		 3066 le64_to_cpu(params->start_time) - priv->last_tsf,
3067 le16_to_cpu(priv->rxon_timing.beacon_interval));
3068
3069 memset(&spectrum, 0, sizeof(spectrum));
3070
3071 spectrum.channel_count = cpu_to_le16(1);
3072 spectrum.flags =
3073 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
3074 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
3075 cmd.len = sizeof(spectrum);
3076 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
3077
bb8c093b 3078 if (iwl3945_is_associated(priv))
b481de9c 3079 spectrum.start_time =
bb8c093b 3080 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 3081 add_time,
3082 le16_to_cpu(priv->rxon_timing.beacon_interval));
3083 else
3084 spectrum.start_time = 0;
3085
3086 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
3087 spectrum.channels[0].channel = params->channel;
3088 spectrum.channels[0].type = type;
3089 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
3090 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
3091 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
3092
bb8c093b 3093 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 3094 if (rc)
3095 return rc;
3096
bb8c093b 3097 res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 3098 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
3099 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
3100 rc = -EIO;
3101 }
3102
3103 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
3104 switch (spectrum_resp_status) {
3105 case 0: /* Command will be handled */
3106 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS		 3107 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
3108 res->u.spectrum.id);
b481de9c
ZY		 3109 priv->measurement_status &= ~MEASUREMENT_READY;
3110 }
3111 priv->measurement_status |= MEASUREMENT_ACTIVE;
3112 rc = 0;
3113 break;
3114
3115 case 1: /* Command will not be handled */
3116 rc = -EAGAIN;
3117 break;
3118 }
3119
3120 dev_kfree_skb_any(cmd.meta.u.skb);
3121
3122 return rc;
3123}
3124#endif
3125
bb8c093b
CH		 3126static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
3127 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3128{
bb8c093b
CH		 3129 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3130 struct iwl3945_alive_resp *palive;
b481de9c
ZY		 3131 struct delayed_work *pwork;
3132
3133 palive = &pkt->u.alive_frame;
3134
3135 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3136 "0x%01X 0x%01X\n",
3137 palive->is_valid, palive->ver_type,
3138 palive->ver_subtype);
3139
3140 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3141 IWL_DEBUG_INFO("Initialization Alive received.\n");
3142 memcpy(&priv->card_alive_init,
3143 &pkt->u.alive_frame,
bb8c093b 3144 sizeof(struct iwl3945_init_alive_resp));
b481de9c
ZY		 3145 pwork = &priv->init_alive_start;
3146 } else {
3147 IWL_DEBUG_INFO("Runtime Alive received.\n");
3148 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 3149 sizeof(struct iwl3945_alive_resp));
b481de9c 3150 pwork = &priv->alive_start;
bb8c093b 3151 iwl3945_disable_events(priv);
b481de9c
ZY		 3152 }
3153
3154 /* We delay the ALIVE response by 5ms to
3155 * give the HW RF Kill time to activate... */
3156 if (palive->is_valid == UCODE_VALID_OK)
3157 queue_delayed_work(priv->workqueue, pwork,
3158 msecs_to_jiffies(5));
3159 else
3160 IWL_WARNING("uCode did not respond OK.\n");
3161}
3162
bb8c093b
CH		 3163static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
3164 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3165{
bb8c093b 3166 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3167
3168 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3169 return;
3170}
3171
bb8c093b
CH		 3172static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
3173 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3174{
bb8c093b 3175 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3176
3177 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3178 "seq 0x%04X ser 0x%08X\n",
3179 le32_to_cpu(pkt->u.err_resp.error_type),
3180 get_cmd_string(pkt->u.err_resp.cmd_id),
3181 pkt->u.err_resp.cmd_id,
3182 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3183 le32_to_cpu(pkt->u.err_resp.error_info));
3184}
3185
3186#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3187
bb8c093b 3188static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3189{
bb8c093b
CH		 3190 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3191 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3192 struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 3193 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3194 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3195 rxon->channel = csa->channel;
3196 priv->staging_rxon.channel = csa->channel;
3197}
3198
bb8c093b
CH		 3199static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3200 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3201{
c8b0e6e1 3202#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
bb8c093b
CH		 3203 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3204 struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 3205
3206 if (!report->state) {
3207 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3208 "Spectrum Measure Notification: Start\n");
3209 return;
3210 }
3211
3212 memcpy(&priv->measure_report, report, sizeof(*report));
3213 priv->measurement_status |= MEASUREMENT_READY;
3214#endif
3215}
3216
bb8c093b
CH		 3217static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3218 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3219{
c8b0e6e1 3220#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3221 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3222 struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 3223 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3224 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3225#endif
3226}
3227
bb8c093b
CH		 3228static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3229 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3230{
bb8c093b 3231 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3232 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3233 "notification for %s:\n",
3234 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bb8c093b 3235 iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 3236}
3237
bb8c093b 3238static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 3239{
bb8c093b
CH		 3240 struct iwl3945_priv *priv =
3241 container_of(work, struct iwl3945_priv, beacon_update);
b481de9c
ZY		 3242 struct sk_buff *beacon;
3243
3244 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 3245 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 3246
3247 if (!beacon) {
3248 IWL_ERROR("update beacon failed\n");
3249 return;
3250 }
3251
3252 mutex_lock(&priv->mutex);
3253 /* new beacon skb is allocated every time; dispose previous.*/
3254 if (priv->ibss_beacon)
3255 dev_kfree_skb(priv->ibss_beacon);
3256
3257 priv->ibss_beacon = beacon;
3258 mutex_unlock(&priv->mutex);
3259
bb8c093b 3260 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 3261}
3262
bb8c093b
CH		 3263static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3264 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3265{
c8b0e6e1 3266#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3267 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3268 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY		 3269 u8 rate = beacon->beacon_notify_hdr.rate;
3270
3271 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3272 "tsf %d %d rate %d\n",
3273 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3274 beacon->beacon_notify_hdr.failure_frame,
3275 le32_to_cpu(beacon->ibss_mgr_status),
3276 le32_to_cpu(beacon->high_tsf),
3277 le32_to_cpu(beacon->low_tsf), rate);
3278#endif
3279
3280 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
3281 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3282 queue_work(priv->workqueue, &priv->beacon_update);
3283}
3284
3285/* Service response to REPLY_SCAN_CMD (0x80) */
bb8c093b
CH		 3286static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3287 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3288{
c8b0e6e1 3289#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 3290 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3291 struct iwl3945_scanreq_notification *notif =
3292 (struct iwl3945_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 3293
3294 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3295#endif
3296}
3297
3298/* Service SCAN_START_NOTIFICATION (0x82) */
bb8c093b
CH		 3299static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3300 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3301{
bb8c093b
CH		 3302 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3303 struct iwl3945_scanstart_notification *notif =
3304 (struct iwl3945_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 3305 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3306 IWL_DEBUG_SCAN("Scan start: "
3307 "%d [802.11%s] "
3308 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3309 notif->channel,
3310 notif->band ? "bg" : "a",
3311 notif->tsf_high,
3312 notif->tsf_low, notif->status, notif->beacon_timer);
3313}
3314
3315/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
bb8c093b
CH		 3316static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3317 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3318{
bb8c093b
CH		 3319 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3320 struct iwl3945_scanresults_notification *notif =
3321 (struct iwl3945_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 3322
3323 IWL_DEBUG_SCAN("Scan ch.res: "
3324 "%d [802.11%s] "
3325 "(TSF: 0x%08X:%08X) - %d "
3326 "elapsed=%lu usec (%dms since last)\n",
3327 notif->channel,
3328 notif->band ? "bg" : "a",
3329 le32_to_cpu(notif->tsf_high),
3330 le32_to_cpu(notif->tsf_low),
3331 le32_to_cpu(notif->statistics[0]),
3332 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3333 jiffies_to_msecs(elapsed_jiffies
3334 (priv->last_scan_jiffies, jiffies)));
3335
3336 priv->last_scan_jiffies = jiffies;
7878a5a4 3337 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3338}
3339
3340/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
bb8c093b
CH		 3341static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3342 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3343{
bb8c093b
CH		 3344 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3345 struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 3346
3347 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3348 scan_notif->scanned_channels,
3349 scan_notif->tsf_low,
3350 scan_notif->tsf_high, scan_notif->status);
3351
3352 /* The HW is no longer scanning */
3353 clear_bit(STATUS_SCAN_HW, &priv->status);
3354
3355 /* The scan completion notification came in, so kill that timer... */
3356 cancel_delayed_work(&priv->scan_check);
3357
3358 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
66b5004d
RR		 3359 (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
3360 "2.4" : "5.2",
b481de9c
ZY		 3361 jiffies_to_msecs(elapsed_jiffies
3362 (priv->scan_pass_start, jiffies)));
3363
66b5004d
RR		 3364 /* Remove this scanned band from the list of pending
3365 * bands to scan, band G precedes A in order of scanning
3366 * as seen in iwl3945_bg_request_scan */
3367 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
3368 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
3369 else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
3370 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 3371
3372 /* If a request to abort was given, or the scan did not succeed
3373 * then we reset the scan state machine and terminate,
3374 * re-queuing another scan if one has been requested */
3375 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3376 IWL_DEBUG_INFO("Aborted scan completed.\n");
3377 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3378 } else {
3379 /* If there are more bands on this scan pass reschedule */
3380 if (priv->scan_bands > 0)
3381 goto reschedule;
3382 }
3383
3384 priv->last_scan_jiffies = jiffies;
7878a5a4 3385 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3386 IWL_DEBUG_INFO("Setting scan to off\n");
3387
3388 clear_bit(STATUS_SCANNING, &priv->status);
3389
3390 IWL_DEBUG_INFO("Scan took %dms\n",
3391 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3392
3393 queue_work(priv->workqueue, &priv->scan_completed);
3394
3395 return;
3396
3397reschedule:
3398 priv->scan_pass_start = jiffies;
3399 queue_work(priv->workqueue, &priv->request_scan);
3400}
3401
3402/* Handle notification from uCode that card's power state is changing
3403 * due to software, hardware, or critical temperature RFKILL */
bb8c093b
CH		 3404static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3405 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3406{
bb8c093b 3407 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3408 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3409 unsigned long status = priv->status;
3410
3411 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3412 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3413 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3414
bb8c093b 3415 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3416 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3417
3418 if (flags & HW_CARD_DISABLED)
3419 set_bit(STATUS_RF_KILL_HW, &priv->status);
3420 else
3421 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3422
3423
3424 if (flags & SW_CARD_DISABLED)
3425 set_bit(STATUS_RF_KILL_SW, &priv->status);
3426 else
3427 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3428
bb8c093b 3429 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3430
3431 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3432 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3433 (test_bit(STATUS_RF_KILL_SW, &status) !=
3434 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3435 queue_work(priv->workqueue, &priv->rf_kill);
3436 else
3437 wake_up_interruptible(&priv->wait_command_queue);
3438}
3439
3440/**
bb8c093b 3441 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 3442 *
3443 * Setup the RX handlers for each of the reply types sent from the uCode
3444 * to the host.
3445 *
3446 * This function chains into the hardware specific files for them to setup
3447 * any hardware specific handlers as well.
3448 */
bb8c093b 3449static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
b481de9c 3450{
bb8c093b
CH		 3451 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3452 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3453 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3454 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3455 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 3456 iwl3945_rx_spectrum_measure_notif;
3457 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3458 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 3459 iwl3945_rx_pm_debug_statistics_notif;
3460 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3461
9fbab516
BC		 3462 /*
3463 * The same handler is used for both the REPLY to a discrete
3464 * statistics request from the host as well as for the periodic
3465 * statistics notifications (after received beacons) from the uCode.
b481de9c 3466 */
bb8c093b
CH		 3467 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3468 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3469
bb8c093b
CH		 3470 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3471 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3472 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3473 iwl3945_rx_scan_results_notif;
b481de9c 3474 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 3475 iwl3945_rx_scan_complete_notif;
3476 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 3477
9fbab516 3478 /* Set up hardware specific Rx handlers */
bb8c093b 3479 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY		 3480}
3481
91c066f2
TW		 3482/**
3483 * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3484 * When FW advances 'R' index, all entries between old and new 'R' index
3485 * need to be reclaimed.
3486 */
3487static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
3488 int txq_id, int index)
3489{
3490 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3491 struct iwl3945_queue *q = &txq->q;
3492 int nfreed = 0;
3493
3494 if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
3495 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3496 "is out of range [0-%d] %d %d.\n", txq_id,
3497 index, q->n_bd, q->write_ptr, q->read_ptr);
3498 return;
3499 }
3500
3501 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3502 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3503 if (nfreed > 1) {
3504 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
3505 q->write_ptr, q->read_ptr);
3506 queue_work(priv->workqueue, &priv->restart);
3507 break;
3508 }
3509 nfreed++;
3510 }
3511}
3512
3513
b481de9c 3514/**
bb8c093b 3515 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 3516 * @rxb: Rx buffer to reclaim
3517 *
3518 * If an Rx buffer has an async callback associated with it the callback
3519 * will be executed. The attached skb (if present) will only be freed
3520 * if the callback returns 1
3521 */
bb8c093b
CH		 3522static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3523 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 3524{
bb8c093b 3525 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3526 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3527 int txq_id = SEQ_TO_QUEUE(sequence);
3528 int index = SEQ_TO_INDEX(sequence);
3529 int huge = sequence & SEQ_HUGE_FRAME;
3530 int cmd_index;
bb8c093b 3531 struct iwl3945_cmd *cmd;
b481de9c 3532
b481de9c
ZY		 3533 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3534
3535 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3536 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3537
3538 /* Input error checking is done when commands are added to queue. */
3539 if (cmd->meta.flags & CMD_WANT_SKB) {
3540 cmd->meta.source->u.skb = rxb->skb;
3541 rxb->skb = NULL;
3542 } else if (cmd->meta.u.callback &&
3543 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3544 rxb->skb = NULL;
3545
91c066f2 3546 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3547
3548 if (!(cmd->meta.flags & CMD_ASYNC)) {
3549 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3550 wake_up_interruptible(&priv->wait_command_queue);
3551 }
3552}
3553
3554/************************** RX-FUNCTIONS ****************************/
3555/*
3556 * Rx theory of operation
3557 *
3558 * The host allocates 32 DMA target addresses and passes the host address
3559 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3560 * 0 to 31
3561 *
3562 * Rx Queue Indexes
3563 * The host/firmware share two index registers for managing the Rx buffers.
3564 *
3565 * The READ index maps to the first position that the firmware may be writing
3566 * to -- the driver can read up to (but not including) this position and get
3567 * good data.
3568 * The READ index is managed by the firmware once the card is enabled.
3569 *
3570 * The WRITE index maps to the last position the driver has read from -- the
3571 * position preceding WRITE is the last slot the firmware can place a packet.
3572 *
3573 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3574 * WRITE = READ.
3575 *
9fbab516 3576 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 3577 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3578 *
9fbab516 3579 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 3580 * and fire the RX interrupt. The driver can then query the READ index and
3581 * process as many packets as possible, moving the WRITE index forward as it
3582 * resets the Rx queue buffers with new memory.
3583 *
3584 * The management in the driver is as follows:
3585 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3586 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3587 * to replenish the iwl->rxq->rx_free.
bb8c093b 3588 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 3589 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3590 * 'processed' and 'read' driver indexes as well)
3591 * + A received packet is processed and handed to the kernel network stack,
3592 * detached from the iwl->rxq. The driver 'processed' index is updated.
3593 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3594 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3595 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3596 * were enough free buffers and RX_STALLED is set it is cleared.
3597 *
3598 *
3599 * Driver sequence:
3600 *
9fbab516
BC		 3601 * iwl3945_rx_queue_alloc() Allocates rx_free
3602 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3603 * iwl3945_rx_queue_restock
9fbab516 3604 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 3605 * queue, updates firmware pointers, and updates
3606 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3607 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY		 3608 *
3609 * -- enable interrupts --
9fbab516 3610 * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
b481de9c
ZY		 3611 * READ INDEX, detaching the SKB from the pool.
3612 * Moves the packet buffer from queue to rx_used.
bb8c093b 3613 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY		 3614 * slots.
3615 * ...
3616 *
3617 */
3618
3619/**
bb8c093b 3620 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3621 */
bb8c093b 3622static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
b481de9c
ZY		 3623{
3624 int s = q->read - q->write;
3625 if (s <= 0)
3626 s += RX_QUEUE_SIZE;
3627 /* keep some buffer to not confuse full and empty queue */
3628 s -= 2;
3629 if (s < 0)
3630 s = 0;
3631 return s;
3632}
3633
3634/**
bb8c093b 3635 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3636 */
bb8c093b 3637int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
b481de9c
ZY		 3638{
3639 u32 reg = 0;
3640 int rc = 0;
3641 unsigned long flags;
3642
3643 spin_lock_irqsave(&q->lock, flags);
3644
3645 if (q->need_update == 0)
3646 goto exit_unlock;
3647
6440adb5 3648 /* If power-saving is in use, make sure device is awake */
b481de9c 3649 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
bb8c093b 3650 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3651
3652 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
bb8c093b 3653 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3654 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3655 goto exit_unlock;
3656 }
3657
bb8c093b 3658 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 3659 if (rc)
3660 goto exit_unlock;
3661
6440adb5 3662 /* Device expects a multiple of 8 */
bb8c093b 3663 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 3664 q->write & ~0x7);
bb8c093b 3665 iwl3945_release_nic_access(priv);
6440adb5
CB		 3666
3667 /* Else device is assumed to be awake */
b481de9c 3668 } else
6440adb5 3669 /* Device expects a multiple of 8 */
bb8c093b 3670 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 3671
3672
3673 q->need_update = 0;
3674
3675 exit_unlock:
3676 spin_unlock_irqrestore(&q->lock, flags);
3677 return rc;
3678}
3679
3680/**
9fbab516 3681 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3682 */
bb8c093b 3683static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
b481de9c
ZY		 3684 dma_addr_t dma_addr)
3685{
3686 return cpu_to_le32((u32)dma_addr);
3687}
3688
3689/**
bb8c093b 3690 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3691 *
9fbab516 3692 * If there are slots in the RX queue that need to be restocked,
b481de9c 3693 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3694 * as we can, pulling from rx_free.
b481de9c
ZY		 3695 *
3696 * This moves the 'write' index forward to catch up with 'processed', and
3697 * also updates the memory address in the firmware to reference the new
3698 * target buffer.
3699 */
bb8c093b 3700static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
b481de9c 3701{
bb8c093b 3702 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3703 struct list_head *element;
bb8c093b 3704 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3705 unsigned long flags;
3706 int write, rc;
3707
3708 spin_lock_irqsave(&rxq->lock, flags);
3709 write = rxq->write & ~0x7;
bb8c093b 3710 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3711 /* Get next free Rx buffer, remove from free list */
b481de9c 3712 element = rxq->rx_free.next;
bb8c093b 3713 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
b481de9c 3714 list_del(element);
6440adb5
CB		 3715
3716 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 3717 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY		 3718 rxq->queue[rxq->write] = rxb;
3719 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3720 rxq->free_count--;
3721 }
3722 spin_unlock_irqrestore(&rxq->lock, flags);
3723 /* If the pre-allocated buffer pool is dropping low, schedule to
3724 * refill it */
3725 if (rxq->free_count <= RX_LOW_WATERMARK)
3726 queue_work(priv->workqueue, &priv->rx_replenish);
3727
3728
6440adb5
CB		 3729 /* If we've added more space for the firmware to place data, tell it.
3730 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 3731 if ((write != (rxq->write & ~0x7))
3732 || (abs(rxq->write - rxq->read) > 7)) {
3733 spin_lock_irqsave(&rxq->lock, flags);
3734 rxq->need_update = 1;
3735 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 3736 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 3737 if (rc)
3738 return rc;
3739 }
3740
3741 return 0;
3742}
3743
3744/**
bb8c093b 3745 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 3746 *
3747 * When moving to rx_free an SKB is allocated for the slot.
3748 *
bb8c093b 3749 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 3750 * This is called as a scheduled work item (except for during initialization)
b481de9c 3751 */
5c0eef96 3752static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
b481de9c 3753{
bb8c093b 3754 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 3755 struct list_head *element;
bb8c093b 3756 struct iwl3945_rx_mem_buffer *rxb;
b481de9c
ZY		 3757 unsigned long flags;
3758 spin_lock_irqsave(&rxq->lock, flags);
3759 while (!list_empty(&rxq->rx_used)) {
3760 element = rxq->rx_used.next;
bb8c093b 3761 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
6440adb5
CB		 3762
3763 /* Alloc a new receive buffer */
b481de9c
ZY		 3764 rxb->skb =
3765 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3766 if (!rxb->skb) {
3767 if (net_ratelimit())
3768 printk(KERN_CRIT DRV_NAME
3769 ": Can not allocate SKB buffers\n");
3770 /* We don't reschedule replenish work here -- we will
3771 * call the restock method and if it still needs
3772 * more buffers it will schedule replenish */
3773 break;
3774 }
12342c47
ZY		 3775
3776 /* If radiotap head is required, reserve some headroom here.
3777 * The physical head count is a variable rx_stats->phy_count.
3778 * We reserve 4 bytes here. Plus these extra bytes, the
3779 * headroom of the physical head should be enough for the
3780 * radiotap head that iwl3945 supported. See iwl3945_rt.
3781 */
3782 skb_reserve(rxb->skb, 4);
3783
b481de9c
ZY		 3784 priv->alloc_rxb_skb++;
3785 list_del(element);
6440adb5
CB		 3786
3787 /* Get physical address of RB/SKB */
b481de9c
ZY		 3788 rxb->dma_addr =
3789 pci_map_single(priv->pci_dev, rxb->skb->data,
3790 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3791 list_add_tail(&rxb->list, &rxq->rx_free);
3792 rxq->free_count++;
3793 }
3794 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA		 3795}
3796
3797/*
3798 * this should be called while priv->lock is locked
3799 */
4fd1f841 3800static void __iwl3945_rx_replenish(void *data)
5c0eef96
MA		 3801{
3802 struct iwl3945_priv *priv = data;
3803
3804 iwl3945_rx_allocate(priv);
3805 iwl3945_rx_queue_restock(priv);
3806}
3807
3808
3809void iwl3945_rx_replenish(void *data)
3810{
3811 struct iwl3945_priv *priv = data;
3812 unsigned long flags;
3813
3814 iwl3945_rx_allocate(priv);
b481de9c
ZY		 3815
3816 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3817 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3818 spin_unlock_irqrestore(&priv->lock, flags);
3819}
3820
3821/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 3822 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY		 3823 * This free routine walks the list of POOL entries and if SKB is set to
3824 * non NULL it is unmapped and freed
3825 */
bb8c093b 3826static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3827{
3828 int i;
3829 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3830 if (rxq->pool[i].skb != NULL) {
3831 pci_unmap_single(priv->pci_dev,
3832 rxq->pool[i].dma_addr,
3833 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3834 dev_kfree_skb(rxq->pool[i].skb);
3835 }
3836 }
3837
3838 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3839 rxq->dma_addr);
3840 rxq->bd = NULL;
3841}
3842
bb8c093b 3843int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
b481de9c 3844{
bb8c093b 3845 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3846 struct pci_dev *dev = priv->pci_dev;
3847 int i;
3848
3849 spin_lock_init(&rxq->lock);
3850 INIT_LIST_HEAD(&rxq->rx_free);
3851 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB		 3852
3853 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY		 3854 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3855 if (!rxq->bd)
3856 return -ENOMEM;
6440adb5 3857
b481de9c
ZY		 3858 /* Fill the rx_used queue with _all_ of the Rx buffers */
3859 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3860 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 3861
b481de9c
ZY		 3862 /* Set us so that we have processed and used all buffers, but have
3863 * not restocked the Rx queue with fresh buffers */
3864 rxq->read = rxq->write = 0;
3865 rxq->free_count = 0;
3866 rxq->need_update = 0;
3867 return 0;
3868}
3869
bb8c093b 3870void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 3871{
3872 unsigned long flags;
3873 int i;
3874 spin_lock_irqsave(&rxq->lock, flags);
3875 INIT_LIST_HEAD(&rxq->rx_free);
3876 INIT_LIST_HEAD(&rxq->rx_used);
3877 /* Fill the rx_used queue with _all_ of the Rx buffers */
3878 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3879 /* In the reset function, these buffers may have been allocated
3880 * to an SKB, so we need to unmap and free potential storage */
3881 if (rxq->pool[i].skb != NULL) {
3882 pci_unmap_single(priv->pci_dev,
3883 rxq->pool[i].dma_addr,
3884 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3885 priv->alloc_rxb_skb--;
3886 dev_kfree_skb(rxq->pool[i].skb);
3887 rxq->pool[i].skb = NULL;
3888 }
3889 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3890 }
3891
3892 /* Set us so that we have processed and used all buffers, but have
3893 * not restocked the Rx queue with fresh buffers */
3894 rxq->read = rxq->write = 0;
3895 rxq->free_count = 0;
3896 spin_unlock_irqrestore(&rxq->lock, flags);
3897}
3898
3899/* Convert linear signal-to-noise ratio into dB */
3900static u8 ratio2dB[100] = {
3901/* 0 1 2 3 4 5 6 7 8 9 */
3902 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3903 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3904 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3905 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3906 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3907 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3908 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3909 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3910 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3911 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3912};
3913
3914/* Calculates a relative dB value from a ratio of linear
3915 * (i.e. not dB) signal levels.
3916 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 3917int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 3918{
221c80cf
AB		 3919 /* 1000:1 or higher just report as 60 dB */
3920 if (sig_ratio >= 1000)
b481de9c
ZY		 3921 return 60;
3922
221c80cf 3923 /* 100:1 or higher, divide by 10 and use table,
b481de9c 3924 * add 20 dB to make up for divide by 10 */
221c80cf 3925 if (sig_ratio >= 100)
b481de9c
ZY		 3926 return (20 + (int)ratio2dB[sig_ratio/10]);
3927
3928 /* We shouldn't see this */
3929 if (sig_ratio < 1)
3930 return 0;
3931
3932 /* Use table for ratios 1:1 - 99:1 */
3933 return (int)ratio2dB[sig_ratio];
3934}
3935
3936#define PERFECT_RSSI (-20) /* dBm */
3937#define WORST_RSSI (-95) /* dBm */
3938#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3939
3940/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3941 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3942 * about formulas used below. */
bb8c093b 3943int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 3944{
3945 int sig_qual;
3946 int degradation = PERFECT_RSSI - rssi_dbm;
3947
3948 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3949 * as indicator; formula is (signal dbm - noise dbm).
3950 * SNR at or above 40 is a great signal (100%).
3951 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3952 * Weakest usable signal is usually 10 - 15 dB SNR. */
3953 if (noise_dbm) {
3954 if (rssi_dbm - noise_dbm >= 40)
3955 return 100;
3956 else if (rssi_dbm < noise_dbm)
3957 return 0;
3958 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3959
3960 /* Else use just the signal level.
3961 * This formula is a least squares fit of data points collected and
3962 * compared with a reference system that had a percentage (%) display
3963 * for signal quality. */
3964 } else
3965 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3966 (15 * RSSI_RANGE + 62 * degradation)) /
3967 (RSSI_RANGE * RSSI_RANGE);
3968
3969 if (sig_qual > 100)
3970 sig_qual = 100;
3971 else if (sig_qual < 1)
3972 sig_qual = 0;
3973
3974 return sig_qual;
3975}
3976
3977/**
9fbab516 3978 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 3979 *
3980 * Uses the priv->rx_handlers callback function array to invoke
3981 * the appropriate handlers, including command responses,
3982 * frame-received notifications, and other notifications.
3983 */
bb8c093b 3984static void iwl3945_rx_handle(struct iwl3945_priv *priv)
b481de9c 3985{
bb8c093b
CH		 3986 struct iwl3945_rx_mem_buffer *rxb;
3987 struct iwl3945_rx_packet *pkt;
3988 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3989 u32 r, i;
3990 int reclaim;
3991 unsigned long flags;
5c0eef96 3992 u8 fill_rx = 0;
d68ab680 3993 u32 count = 8;
b481de9c 3994
6440adb5
CB		 3995 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3996 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 3997 r = iwl3945_hw_get_rx_read(priv);
b481de9c
ZY		 3998 i = rxq->read;
3999
5c0eef96
MA		 4000 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
4001 fill_rx = 1;
b481de9c
ZY		 4002 /* Rx interrupt, but nothing sent from uCode */
4003 if (i == r)
4004 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
4005
4006 while (i != r) {
4007 rxb = rxq->queue[i];
4008
9fbab516 4009 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 4010 * then a bug has been introduced in the queue refilling
4011 * routines -- catch it here */
4012 BUG_ON(rxb == NULL);
4013
4014 rxq->queue[i] = NULL;
4015
4016 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
4017 IWL_RX_BUF_SIZE,
4018 PCI_DMA_FROMDEVICE);
bb8c093b 4019 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
b481de9c
ZY		 4020
4021 /* Reclaim a command buffer only if this packet is a response
4022 * to a (driver-originated) command.
4023 * If the packet (e.g. Rx frame) originated from uCode,
4024 * there is no command buffer to reclaim.
4025 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4026 * but apparently a few don't get set; catch them here. */
4027 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
4028 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
4029 (pkt->hdr.cmd != REPLY_TX);
4030
4031 /* Based on type of command response or notification,
4032 * handle those that need handling via function in
bb8c093b 4033 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c
ZY		 4034 if (priv->rx_handlers[pkt->hdr.cmd]) {
4035 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4036 "r = %d, i = %d, %s, 0x%02x\n", r, i,
4037 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4038 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
4039 } else {
4040 /* No handling needed */
4041 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4042 "r %d i %d No handler needed for %s, 0x%02x\n",
4043 r, i, get_cmd_string(pkt->hdr.cmd),
4044 pkt->hdr.cmd);
4045 }
4046
4047 if (reclaim) {
9fbab516
BC		 4048 /* Invoke any callbacks, transfer the skb to caller, and
4049 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY		 4050 * as we reclaim the driver command queue */
4051 if (rxb && rxb->skb)
bb8c093b 4052 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c
ZY		 4053 else
4054 IWL_WARNING("Claim null rxb?\n");
4055 }
4056
4057 /* For now we just don't re-use anything. We can tweak this
4058 * later to try and re-use notification packets and SKBs that
4059 * fail to Rx correctly */
4060 if (rxb->skb != NULL) {
4061 priv->alloc_rxb_skb--;
4062 dev_kfree_skb_any(rxb->skb);
4063 rxb->skb = NULL;
4064 }
4065
4066 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
4067 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
4068 spin_lock_irqsave(&rxq->lock, flags);
4069 list_add_tail(&rxb->list, &priv->rxq.rx_used);
4070 spin_unlock_irqrestore(&rxq->lock, flags);
4071 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 4072 /* If there are a lot of unused frames,
4073 * restock the Rx queue so ucode won't assert. */
4074 if (fill_rx) {
4075 count++;
4076 if (count >= 8) {
4077 priv->rxq.read = i;
4078 __iwl3945_rx_replenish(priv);
4079 count = 0;
4080 }
4081 }
b481de9c
ZY		 4082 }
4083
4084 /* Backtrack one entry */
4085 priv->rxq.read = i;
bb8c093b 4086 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 4087}
4088
6440adb5
CB		 4089/**
4090 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
4091 */
bb8c093b
CH		 4092static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
4093 struct iwl3945_tx_queue *txq)
b481de9c
ZY		 4094{
4095 u32 reg = 0;
4096 int rc = 0;
4097 int txq_id = txq->q.id;
4098
4099 if (txq->need_update == 0)
4100 return rc;
4101
4102 /* if we're trying to save power */
4103 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
4104 /* wake up nic if it's powered down ...
4105 * uCode will wake up, and interrupt us again, so next
4106 * time we'll skip this part. */
bb8c093b 4107 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 4108
4109 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
4110 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
bb8c093b 4111 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 4112 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4113 return rc;
4114 }
4115
4116 /* restore this queue's parameters in nic hardware. */
bb8c093b 4117 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4118 if (rc)
4119 return rc;
bb8c093b 4120 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 4121 txq->q.write_ptr | (txq_id << 8));
bb8c093b 4122 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4123
4124 /* else not in power-save mode, uCode will never sleep when we're
4125 * trying to tx (during RFKILL, we're not trying to tx). */
4126 } else
bb8c093b 4127 iwl3945_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 4128 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 4129
4130 txq->need_update = 0;
4131
4132 return rc;
4133}
4134
c8b0e6e1 4135#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4136static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
b481de9c 4137{
0795af57
JP		 4138 DECLARE_MAC_BUF(mac);
4139
b481de9c 4140 IWL_DEBUG_RADIO("RX CONFIG:\n");
bb8c093b 4141 iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 4142 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4143 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4144 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4145 le32_to_cpu(rxon->filter_flags));
4146 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4147 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4148 rxon->ofdm_basic_rates);
4149 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
0795af57
JP		 4150 IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
4151 print_mac(mac, rxon->node_addr));
4152 IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
4153 print_mac(mac, rxon->bssid_addr));
b481de9c
ZY		 4154 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4155}
4156#endif
4157
bb8c093b 4158static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4159{
4160 IWL_DEBUG_ISR("Enabling interrupts\n");
4161 set_bit(STATUS_INT_ENABLED, &priv->status);
bb8c093b 4162 iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 4163}
4164
0359facc
MA		 4165
4166/* call this function to flush any scheduled tasklet */
4167static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
4168{
4169 /* wait to make sure we flush pedding tasklet*/
4170 synchronize_irq(priv->pci_dev->irq);
4171 tasklet_kill(&priv->irq_tasklet);
4172}
4173
4174
bb8c093b 4175static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
b481de9c
ZY		 4176{
4177 clear_bit(STATUS_INT_ENABLED, &priv->status);
4178
4179 /* disable interrupts from uCode/NIC to host */
bb8c093b 4180 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4181
4182 /* acknowledge/clear/reset any interrupts still pending
4183 * from uCode or flow handler (Rx/Tx DMA) */
bb8c093b
CH		 4184 iwl3945_write32(priv, CSR_INT, 0xffffffff);
4185 iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 4186 IWL_DEBUG_ISR("Disabled interrupts\n");
4187}
4188
4189static const char *desc_lookup(int i)
4190{
4191 switch (i) {
4192 case 1:
4193 return "FAIL";
4194 case 2:
4195 return "BAD_PARAM";
4196 case 3:
4197 return "BAD_CHECKSUM";
4198 case 4:
4199 return "NMI_INTERRUPT";
4200 case 5:
4201 return "SYSASSERT";
4202 case 6:
4203 return "FATAL_ERROR";
4204 }
4205
4206 return "UNKNOWN";
4207}
4208
4209#define ERROR_START_OFFSET (1 * sizeof(u32))
4210#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4211
bb8c093b 4212static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4213{
4214 u32 i;
4215 u32 desc, time, count, base, data1;
4216 u32 blink1, blink2, ilink1, ilink2;
4217 int rc;
4218
4219 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4220
bb8c093b 4221 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4222 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4223 return;
4224 }
4225
bb8c093b 4226 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4227 if (rc) {
4228 IWL_WARNING("Can not read from adapter at this time.\n");
4229 return;
4230 }
4231
bb8c093b 4232 count = iwl3945_read_targ_mem(priv, base);
b481de9c
ZY		 4233
4234 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4235 IWL_ERROR("Start IWL Error Log Dump:\n");
2acae16e 4236 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
b481de9c
ZY		 4237 }
4238
4239 IWL_ERROR("Desc Time asrtPC blink2 "
4240 "ilink1 nmiPC Line\n");
4241 for (i = ERROR_START_OFFSET;
4242 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4243 i += ERROR_ELEM_SIZE) {
bb8c093b 4244 desc = iwl3945_read_targ_mem(priv, base + i);
b481de9c 4245 time =
bb8c093b 4246 iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 4247 blink1 =
bb8c093b 4248 iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 4249 blink2 =
bb8c093b 4250 iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 4251 ilink1 =
bb8c093b 4252 iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 4253 ilink2 =
bb8c093b 4254 iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 4255 data1 =
bb8c093b 4256 iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c
ZY		 4257
4258 IWL_ERROR
4259 ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4260 desc_lookup(desc), desc, time, blink1, blink2,
4261 ilink1, ilink2, data1);
4262 }
4263
bb8c093b 4264 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4265
4266}
4267
f58177b9 4268#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY		 4269
4270/**
bb8c093b 4271 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 4272 *
bb8c093b 4273 * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
b481de9c 4274 */
bb8c093b 4275static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
b481de9c
ZY		 4276 u32 num_events, u32 mode)
4277{
4278 u32 i;
4279 u32 base; /* SRAM byte address of event log header */
4280 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4281 u32 ptr; /* SRAM byte address of log data */
4282 u32 ev, time, data; /* event log data */
4283
4284 if (num_events == 0)
4285 return;
4286
4287 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4288
4289 if (mode == 0)
4290 event_size = 2 * sizeof(u32);
4291 else
4292 event_size = 3 * sizeof(u32);
4293
4294 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4295
4296 /* "time" is actually "data" for mode 0 (no timestamp).
4297 * place event id # at far right for easier visual parsing. */
4298 for (i = 0; i < num_events; i++) {
bb8c093b 4299 ev = iwl3945_read_targ_mem(priv, ptr);
b481de9c 4300 ptr += sizeof(u32);
bb8c093b 4301 time = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4302 ptr += sizeof(u32);
4303 if (mode == 0)
4304 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4305 else {
bb8c093b 4306 data = iwl3945_read_targ_mem(priv, ptr);
b481de9c
ZY		 4307 ptr += sizeof(u32);
4308 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4309 }
4310 }
4311}
4312
bb8c093b 4313static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
b481de9c
ZY		 4314{
4315 int rc;
4316 u32 base; /* SRAM byte address of event log header */
4317 u32 capacity; /* event log capacity in # entries */
4318 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4319 u32 num_wraps; /* # times uCode wrapped to top of log */
4320 u32 next_entry; /* index of next entry to be written by uCode */
4321 u32 size; /* # entries that we'll print */
4322
4323 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4324 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4325 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4326 return;
4327 }
4328
bb8c093b 4329 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 4330 if (rc) {
4331 IWL_WARNING("Can not read from adapter at this time.\n");
4332 return;
4333 }
4334
4335 /* event log header */
bb8c093b
CH		 4336 capacity = iwl3945_read_targ_mem(priv, base);
4337 mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4338 num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4339 next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 4340
4341 size = num_wraps ? capacity : next_entry;
4342
4343 /* bail out if nothing in log */
4344 if (size == 0) {
583fab37 4345 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
bb8c093b 4346 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4347 return;
4348 }
4349
583fab37 4350 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 4351 size, num_wraps);
4352
4353 /* if uCode has wrapped back to top of log, start at the oldest entry,
4354 * i.e the next one that uCode would fill. */
4355 if (num_wraps)
bb8c093b 4356 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY		 4357 capacity - next_entry, mode);
4358
4359 /* (then/else) start at top of log */
bb8c093b 4360 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 4361
bb8c093b 4362 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4363}
4364
4365/**
bb8c093b 4366 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4367 */
bb8c093b 4368static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
b481de9c 4369{
bb8c093b 4370 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY		 4371 set_bit(STATUS_FW_ERROR, &priv->status);
4372
4373 /* Cancel currently queued command. */
4374 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4375
c8b0e6e1 4376#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4377 if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4378 iwl3945_dump_nic_error_log(priv);
4379 iwl3945_dump_nic_event_log(priv);
4380 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY		 4381 }
4382#endif
4383
4384 wake_up_interruptible(&priv->wait_command_queue);
4385
4386 /* Keep the restart process from trying to send host
4387 * commands by clearing the INIT status bit */
4388 clear_bit(STATUS_READY, &priv->status);
4389
4390 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4391 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4392 "Restarting adapter due to uCode error.\n");
4393
bb8c093b 4394 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4395 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4396 sizeof(priv->recovery_rxon));
4397 priv->error_recovering = 1;
4398 }
4399 queue_work(priv->workqueue, &priv->restart);
4400 }
4401}
4402
bb8c093b 4403static void iwl3945_error_recovery(struct iwl3945_priv *priv)
b481de9c
ZY		 4404{
4405 unsigned long flags;
4406
4407 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4408 sizeof(priv->staging_rxon));
4409 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4410 iwl3945_commit_rxon(priv);
b481de9c 4411
bb8c093b 4412 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY		 4413
4414 spin_lock_irqsave(&priv->lock, flags);
4415 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4416 priv->error_recovering = 0;
4417 spin_unlock_irqrestore(&priv->lock, flags);
4418}
4419
bb8c093b 4420static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
b481de9c
ZY		 4421{
4422 u32 inta, handled = 0;
4423 u32 inta_fh;
4424 unsigned long flags;
c8b0e6e1 4425#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 4426 u32 inta_mask;
4427#endif
4428
4429 spin_lock_irqsave(&priv->lock, flags);
4430
4431 /* Ack/clear/reset pending uCode interrupts.
4432 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4433 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
bb8c093b
CH		 4434 inta = iwl3945_read32(priv, CSR_INT);
4435 iwl3945_write32(priv, CSR_INT, inta);
b481de9c
ZY		 4436
4437 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4438 * Any new interrupts that happen after this, either while we're
4439 * in this tasklet, or later, will show up in next ISR/tasklet. */
bb8c093b
CH		 4440 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4441 iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4442
c8b0e6e1 4443#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4444 if (iwl3945_debug_level & IWL_DL_ISR) {
9fbab516
BC		 4445 /* just for debug */
4446 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 4447 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4448 inta, inta_mask, inta_fh);
4449 }
4450#endif
4451
4452 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4453 * atomic, make sure that inta covers all the interrupts that
4454 * we've discovered, even if FH interrupt came in just after
4455 * reading CSR_INT. */
6f83eaa1 4456 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 4457 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 4458 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY		 4459 inta |= CSR_INT_BIT_FH_TX;
4460
4461 /* Now service all interrupt bits discovered above. */
4462 if (inta & CSR_INT_BIT_HW_ERR) {
4463 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4464
4465 /* Tell the device to stop sending interrupts */
bb8c093b 4466 iwl3945_disable_interrupts(priv);
b481de9c 4467
bb8c093b 4468 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4469
4470 handled |= CSR_INT_BIT_HW_ERR;
4471
4472 spin_unlock_irqrestore(&priv->lock, flags);
4473
4474 return;
4475 }
4476
c8b0e6e1 4477#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 4478 if (iwl3945_debug_level & (IWL_DL_ISR)) {
b481de9c 4479 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP		 4480 if (inta & CSR_INT_BIT_SCD)
4481 IWL_DEBUG_ISR("Scheduler finished to transmit "
4482 "the frame/frames.\n");
b481de9c
ZY		 4483
4484 /* Alive notification via Rx interrupt will do the real work */
4485 if (inta & CSR_INT_BIT_ALIVE)
4486 IWL_DEBUG_ISR("Alive interrupt\n");
4487 }
4488#endif
4489 /* Safely ignore these bits for debug checks below */
25c03d8e 4490 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c
ZY		 4491
4492 /* HW RF KILL switch toggled (4965 only) */
4493 if (inta & CSR_INT_BIT_RF_KILL) {
4494 int hw_rf_kill = 0;
bb8c093b 4495 if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 4496 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4497 hw_rf_kill = 1;
4498
4499 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4500 "RF_KILL bit toggled to %s.\n",
4501 hw_rf_kill ? "disable radio":"enable radio");
4502
4503 /* Queue restart only if RF_KILL switch was set to "kill"
4504 * when we loaded driver, and is now set to "enable".
4505 * After we're Alive, RF_KILL gets handled by
3230455d 4506 * iwl3945_rx_card_state_notif() */
53e49093
ZY		 4507 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4508 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 4509 queue_work(priv->workqueue, &priv->restart);
53e49093 4510 }
b481de9c
ZY		 4511
4512 handled |= CSR_INT_BIT_RF_KILL;
4513 }
4514
4515 /* Chip got too hot and stopped itself (4965 only) */
4516 if (inta & CSR_INT_BIT_CT_KILL) {
4517 IWL_ERROR("Microcode CT kill error detected.\n");
4518 handled |= CSR_INT_BIT_CT_KILL;
4519 }
4520
4521 /* Error detected by uCode */
4522 if (inta & CSR_INT_BIT_SW_ERR) {
4523 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4524 inta);
bb8c093b 4525 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4526 handled |= CSR_INT_BIT_SW_ERR;
4527 }
4528
4529 /* uCode wakes up after power-down sleep */
4530 if (inta & CSR_INT_BIT_WAKEUP) {
4531 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH		 4532 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4533 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4534 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4535 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4536 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4537 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4538 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 4539
4540 handled |= CSR_INT_BIT_WAKEUP;
4541 }
4542
4543 /* All uCode command responses, including Tx command responses,
4544 * Rx "responses" (frame-received notification), and other
4545 * notifications from uCode come through here*/
4546 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4547 iwl3945_rx_handle(priv);
b481de9c
ZY		 4548 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4549 }
4550
4551 if (inta & CSR_INT_BIT_FH_TX) {
4552 IWL_DEBUG_ISR("Tx interrupt\n");
4553
bb8c093b
CH		 4554 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4555 if (!iwl3945_grab_nic_access(priv)) {
4556 iwl3945_write_direct32(priv,
b481de9c
ZY		 4557 FH_TCSR_CREDIT
4558 (ALM_FH_SRVC_CHNL), 0x0);
bb8c093b 4559 iwl3945_release_nic_access(priv);
b481de9c
ZY		 4560 }
4561 handled |= CSR_INT_BIT_FH_TX;
4562 }
4563
4564 if (inta & ~handled)
4565 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4566
4567 if (inta & ~CSR_INI_SET_MASK) {
4568 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4569 inta & ~CSR_INI_SET_MASK);
4570 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4571 }
4572
4573 /* Re-enable all interrupts */
0359facc
MA		 4574 /* only Re-enable if disabled by irq */
4575 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4576 iwl3945_enable_interrupts(priv);
b481de9c 4577
c8b0e6e1 4578#ifdef CONFIG_IWL3945_DEBUG
bb8c093b
CH		 4579 if (iwl3945_debug_level & (IWL_DL_ISR)) {
4580 inta = iwl3945_read32(priv, CSR_INT);
4581 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4582 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4583 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4584 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4585 }
4586#endif
4587 spin_unlock_irqrestore(&priv->lock, flags);
4588}
4589
bb8c093b 4590static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4591{
bb8c093b 4592 struct iwl3945_priv *priv = data;
b481de9c
ZY		 4593 u32 inta, inta_mask;
4594 u32 inta_fh;
4595 if (!priv)
4596 return IRQ_NONE;
4597
4598 spin_lock(&priv->lock);
4599
4600 /* Disable (but don't clear!) interrupts here to avoid
4601 * back-to-back ISRs and sporadic interrupts from our NIC.
4602 * If we have something to service, the tasklet will re-enable ints.
4603 * If we *don't* have something, we'll re-enable before leaving here. */
bb8c093b
CH		 4604 inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
4605 iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4606
4607 /* Discover which interrupts are active/pending */
bb8c093b
CH		 4608 inta = iwl3945_read32(priv, CSR_INT);
4609 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4610
4611 /* Ignore interrupt if there's nothing in NIC to service.
4612 * This may be due to IRQ shared with another device,
4613 * or due to sporadic interrupts thrown from our NIC. */
4614 if (!inta && !inta_fh) {
4615 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4616 goto none;
4617 }
4618
4619 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4620 /* Hardware disappeared */
4621 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
cb4da1a3 4622 goto unplugged;
b481de9c
ZY		 4623 }
4624
4625 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4626 inta, inta_mask, inta_fh);
4627
25c03d8e
JP		 4628 inta &= ~CSR_INT_BIT_SCD;
4629
bb8c093b 4630 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP		 4631 if (likely(inta || inta_fh))
4632 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4633unplugged:
b481de9c
ZY		 4634 spin_unlock(&priv->lock);
4635
4636 return IRQ_HANDLED;
4637
4638 none:
4639 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA		 4640 /* only Re-enable if disabled by irq */
4641 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4642 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 4643 spin_unlock(&priv->lock);
4644 return IRQ_NONE;
4645}
4646
4647/************************** EEPROM BANDS ****************************
4648 *
bb8c093b 4649 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY		 4650 * EEPROM contents to the specific channel number supported for each
4651 * band.
4652 *
bb8c093b 4653 * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
b481de9c
ZY		 4654 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4655 * The specific geography and calibration information for that channel
4656 * is contained in the eeprom map itself.
4657 *
4658 * During init, we copy the eeprom information and channel map
4659 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4660 *
4661 * channel_map_24/52 provides the index in the channel_info array for a
4662 * given channel. We have to have two separate maps as there is channel
4663 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4664 * band_2
4665 *
4666 * A value of 0xff stored in the channel_map indicates that the channel
4667 * is not supported by the hardware at all.
4668 *
4669 * A value of 0xfe in the channel_map indicates that the channel is not
4670 * valid for Tx with the current hardware. This means that
4671 * while the system can tune and receive on a given channel, it may not
4672 * be able to associate or transmit any frames on that
4673 * channel. There is no corresponding channel information for that
4674 * entry.
4675 *
4676 *********************************************************************/
4677
4678/* 2.4 GHz */
bb8c093b 4679static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY		 4680 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4681};
4682
4683/* 5.2 GHz bands */
9fbab516 4684static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY		 4685 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4686};
4687
9fbab516 4688static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY		 4689 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4690};
4691
bb8c093b 4692static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY		 4693 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4694};
4695
bb8c093b 4696static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY		 4697 145, 149, 153, 157, 161, 165
4698};
4699
bb8c093b 4700static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
b481de9c 4701 int *eeprom_ch_count,
bb8c093b 4702 const struct iwl3945_eeprom_channel
b481de9c
ZY		 4703 **eeprom_ch_info,
4704 const u8 **eeprom_ch_index)
4705{
4706 switch (band) {
4707 case 1: /* 2.4GHz band */
bb8c093b 4708 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
b481de9c 4709 *eeprom_ch_info = priv->eeprom.band_1_channels;
bb8c093b 4710 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4711 break;
9fbab516 4712 case 2: /* 4.9GHz band */
bb8c093b 4713 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
b481de9c 4714 *eeprom_ch_info = priv->eeprom.band_2_channels;
bb8c093b 4715 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY		 4716 break;
4717 case 3: /* 5.2GHz band */
bb8c093b 4718 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
b481de9c 4719 *eeprom_ch_info = priv->eeprom.band_3_channels;
bb8c093b 4720 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4721 break;
9fbab516 4722 case 4: /* 5.5GHz band */
bb8c093b 4723 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
b481de9c 4724 *eeprom_ch_info = priv->eeprom.band_4_channels;
bb8c093b 4725 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4726 break;
9fbab516 4727 case 5: /* 5.7GHz band */
bb8c093b 4728 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c 4729 *eeprom_ch_info = priv->eeprom.band_5_channels;
bb8c093b 4730 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY		 4731 break;
4732 default:
4733 BUG();
4734 return;
4735 }
4736}
4737
6440adb5
CB		 4738/**
4739 * iwl3945_get_channel_info - Find driver's private channel info
4740 *
4741 * Based on band and channel number.
4742 */
bb8c093b 4743const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
8318d78a 4744 enum ieee80211_band band, u16 channel)
b481de9c
ZY		 4745{
4746 int i;
4747
8318d78a
JB		 4748 switch (band) {
4749 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 4750 for (i = 14; i < priv->channel_count; i++) {
4751 if (priv->channel_info[i].channel == channel)
4752 return &priv->channel_info[i];
4753 }
4754 break;
4755
8318d78a 4756 case IEEE80211_BAND_2GHZ:
b481de9c
ZY		 4757 if (channel >= 1 && channel <= 14)
4758 return &priv->channel_info[channel - 1];
4759 break;
8318d78a
JB		 4760 case IEEE80211_NUM_BANDS:
4761 WARN_ON(1);
b481de9c
ZY		 4762 }
4763
4764 return NULL;
4765}
4766
4767#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4768 ? # x " " : "")
4769
6440adb5
CB		 4770/**
4771 * iwl3945_init_channel_map - Set up driver's info for all possible channels
4772 */
bb8c093b 4773static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
b481de9c
ZY		 4774{
4775 int eeprom_ch_count = 0;
4776 const u8 *eeprom_ch_index = NULL;
bb8c093b 4777 const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 4778 int band, ch;
bb8c093b 4779 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4780
4781 if (priv->channel_count) {
4782 IWL_DEBUG_INFO("Channel map already initialized.\n");
4783 return 0;
4784 }
4785
4786 if (priv->eeprom.version < 0x2f) {
4787 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
4788 priv->eeprom.version);
4789 return -EINVAL;
4790 }
4791
4792 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4793
4794 priv->channel_count =
bb8c093b
CH		 4795 ARRAY_SIZE(iwl3945_eeprom_band_1) +
4796 ARRAY_SIZE(iwl3945_eeprom_band_2) +
4797 ARRAY_SIZE(iwl3945_eeprom_band_3) +
4798 ARRAY_SIZE(iwl3945_eeprom_band_4) +
4799 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY		 4800
4801 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4802
bb8c093b 4803 priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
b481de9c
ZY		 4804 priv->channel_count, GFP_KERNEL);
4805 if (!priv->channel_info) {
4806 IWL_ERROR("Could not allocate channel_info\n");
4807 priv->channel_count = 0;
4808 return -ENOMEM;
4809 }
4810
4811 ch_info = priv->channel_info;
4812
4813 /* Loop through the 5 EEPROM bands adding them in order to the
4814 * channel map we maintain (that contains additional information than
4815 * what just in the EEPROM) */
4816 for (band = 1; band <= 5; band++) {
4817
bb8c093b 4818 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 4819 &eeprom_ch_info, &eeprom_ch_index);
4820
4821 /* Loop through each band adding each of the channels */
4822 for (ch = 0; ch < eeprom_ch_count; ch++) {
4823 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB		 4824 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4825 IEEE80211_BAND_5GHZ;
b481de9c
ZY		 4826
4827 /* permanently store EEPROM's channel regulatory flags
4828 * and max power in channel info database. */
4829 ch_info->eeprom = eeprom_ch_info[ch];
4830
4831 /* Copy the run-time flags so they are there even on
4832 * invalid channels */
4833 ch_info->flags = eeprom_ch_info[ch].flags;
4834
4835 if (!(is_channel_valid(ch_info))) {
4836 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4837 "No traffic\n",
4838 ch_info->channel,
4839 ch_info->flags,
4840 is_channel_a_band(ch_info) ?
4841 "5.2" : "2.4");
4842 ch_info++;
4843 continue;
4844 }
4845
4846 /* Initialize regulatory-based run-time data */
4847 ch_info->max_power_avg = ch_info->curr_txpow =
4848 eeprom_ch_info[ch].max_power_avg;
4849 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4850 ch_info->min_power = 0;
4851
fe7c4040 4852 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
b481de9c
ZY		 4853 " %ddBm): Ad-Hoc %ssupported\n",
4854 ch_info->channel,
4855 is_channel_a_band(ch_info) ?
4856 "5.2" : "2.4",
8211ef78 4857 CHECK_AND_PRINT(VALID),
b481de9c
ZY		 4858 CHECK_AND_PRINT(IBSS),
4859 CHECK_AND_PRINT(ACTIVE),
4860 CHECK_AND_PRINT(RADAR),
4861 CHECK_AND_PRINT(WIDE),
b481de9c
ZY		 4862 CHECK_AND_PRINT(DFS),
4863 eeprom_ch_info[ch].flags,
4864 eeprom_ch_info[ch].max_power_avg,
4865 ((eeprom_ch_info[ch].
4866 flags & EEPROM_CHANNEL_IBSS)
4867 && !(eeprom_ch_info[ch].
4868 flags & EEPROM_CHANNEL_RADAR))
4869 ? "" : "not ");
4870
4871 /* Set the user_txpower_limit to the highest power
4872 * supported by any channel */
4873 if (eeprom_ch_info[ch].max_power_avg >
4874 priv->user_txpower_limit)
4875 priv->user_txpower_limit =
4876 eeprom_ch_info[ch].max_power_avg;
4877
4878 ch_info++;
4879 }
4880 }
4881
6440adb5 4882 /* Set up txpower settings in driver for all channels */
b481de9c
ZY		 4883 if (iwl3945_txpower_set_from_eeprom(priv))
4884 return -EIO;
4885
4886 return 0;
4887}
4888
849e0dce
RC		 4889/*
4890 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4891 */
4892static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
4893{
4894 kfree(priv->channel_info);
4895 priv->channel_count = 0;
4896}
4897
b481de9c
ZY		 4898/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4899 * sending probe req. This should be set long enough to hear probe responses
4900 * from more than one AP. */
4901#define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
4902#define IWL_ACTIVE_DWELL_TIME_52 (10)
4903
4904/* For faster active scanning, scan will move to the next channel if fewer than
4905 * PLCP_QUIET_THRESH packets are heard on this channel within
4906 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4907 * time if it's a quiet channel (nothing responded to our probe, and there's
4908 * no other traffic).
4909 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4910#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
4911#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
4912
4913/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4914 * Must be set longer than active dwell time.
4915 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4916#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4917#define IWL_PASSIVE_DWELL_TIME_52 (10)
4918#define IWL_PASSIVE_DWELL_BASE (100)
4919#define IWL_CHANNEL_TUNE_TIME 5
4920
8318d78a
JB		 4921static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
4922 enum ieee80211_band band)
b481de9c 4923{
8318d78a 4924 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4925 return IWL_ACTIVE_DWELL_TIME_52;
4926 else
4927 return IWL_ACTIVE_DWELL_TIME_24;
4928}
4929
8318d78a
JB		 4930static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
4931 enum ieee80211_band band)
b481de9c 4932{
8318d78a
JB		 4933 u16 active = iwl3945_get_active_dwell_time(priv, band);
4934 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY		 4935 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4936 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4937
bb8c093b 4938 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4939 /* If we're associated, we clamp the maximum passive
4940 * dwell time to be 98% of the beacon interval (minus
4941 * 2 * channel tune time) */
4942 passive = priv->beacon_int;
4943 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4944 passive = IWL_PASSIVE_DWELL_BASE;
4945 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4946 }
4947
4948 if (passive <= active)
4949 passive = active + 1;
4950
4951 return passive;
4952}
4953
8318d78a
JB		 4954static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
4955 enum ieee80211_band band,
b481de9c 4956 u8 is_active, u8 direct_mask,
bb8c093b 4957 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY		 4958{
4959 const struct ieee80211_channel *channels = NULL;
8318d78a 4960 const struct ieee80211_supported_band *sband;
bb8c093b 4961 const struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 4962 u16 passive_dwell = 0;
4963 u16 active_dwell = 0;
4964 int added, i;
4965
8318d78a
JB		 4966 sband = iwl3945_get_band(priv, band);
4967 if (!sband)
b481de9c
ZY		 4968 return 0;
4969
8318d78a 4970 channels = sband->channels;
b481de9c 4971
8318d78a
JB		 4972 active_dwell = iwl3945_get_active_dwell_time(priv, band);
4973 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 4974
8318d78a 4975 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB		 4976 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4977 continue;
4978
8318d78a 4979 scan_ch->channel = channels[i].hw_value;
b481de9c 4980
8318d78a 4981 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c 4982 if (!is_channel_valid(ch_info)) {
66b5004d 4983 IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
b481de9c
ZY		 4984 scan_ch->channel);
4985 continue;
4986 }
4987
4988 if (!is_active || is_channel_passive(ch_info) ||
8318d78a 4989 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
b481de9c
ZY		 4990 scan_ch->type = 0; /* passive */
4991 else
4992 scan_ch->type = 1; /* active */
4993
4994 if (scan_ch->type & 1)
4995 scan_ch->type |= (direct_mask << 1);
4996
b481de9c
ZY		 4997 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4998 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4999
9fbab516 5000 /* Set txpower levels to defaults */
b481de9c
ZY		 5001 scan_ch->tpc.dsp_atten = 110;
5002 /* scan_pwr_info->tpc.dsp_atten; */
5003
5004 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 5005 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 5006 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
5007 else {
5008 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
5009 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 5010 * power level:
8a1b0245 5011 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY		 5012 */
5013 }
5014
5015 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
5016 scan_ch->channel,
5017 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
5018 (scan_ch->type & 1) ?
5019 active_dwell : passive_dwell);
5020
5021 scan_ch++;
5022 added++;
5023 }
5024
5025 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
5026 return added;
5027}
5028
bb8c093b 5029static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
b481de9c
ZY		 5030 struct ieee80211_rate *rates)
5031{
5032 int i;
5033
5034 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB		 5035 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
5036 rates[i].hw_value = i; /* Rate scaling will work on indexes */
5037 rates[i].hw_value_short = i;
5038 rates[i].flags = 0;
5039 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 5040 /*
8318d78a 5041 * If CCK != 1M then set short preamble rate flag.
b481de9c 5042 */
bb8c093b 5043 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 5044 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 5045 }
b481de9c
ZY		 5046 }
5047}
5048
5049/**
bb8c093b 5050 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 5051 */
bb8c093b 5052static int iwl3945_init_geos(struct iwl3945_priv *priv)
b481de9c 5053{
bb8c093b 5054 struct iwl3945_channel_info *ch;
8211ef78 5055 struct ieee80211_supported_band *sband;
b481de9c
ZY		 5056 struct ieee80211_channel *channels;
5057 struct ieee80211_channel *geo_ch;
5058 struct ieee80211_rate *rates;
5059 int i = 0;
b481de9c 5060
8318d78a
JB		 5061 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
5062 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY		 5063 IWL_DEBUG_INFO("Geography modes already initialized.\n");
5064 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5065 return 0;
5066 }
5067
b481de9c
ZY		 5068 channels = kzalloc(sizeof(struct ieee80211_channel) *
5069 priv->channel_count, GFP_KERNEL);
8318d78a 5070 if (!channels)
b481de9c 5071 return -ENOMEM;
b481de9c 5072
8211ef78 5073 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY		 5074 GFP_KERNEL);
5075 if (!rates) {
b481de9c
ZY		 5076 kfree(channels);
5077 return -ENOMEM;
5078 }
5079
b481de9c 5080 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW		 5081 sband = &priv->bands[IEEE80211_BAND_5GHZ];
5082 sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
5083 /* just OFDM */
5084 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
5085 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
5086
5087 sband = &priv->bands[IEEE80211_BAND_2GHZ];
5088 sband->channels = channels;
5089 /* OFDM & CCK */
5090 sband->bitrates = rates;
5091 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c
ZY		 5092
5093 priv->ieee_channels = channels;
5094 priv->ieee_rates = rates;
5095
bb8c093b 5096 iwl3945_init_hw_rates(priv, rates);
b481de9c 5097
8211ef78 5098 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY		 5099 ch = &priv->channel_info[i];
5100
8211ef78
TW		 5101 /* FIXME: might be removed if scan is OK*/
5102 if (!is_channel_valid(ch))
b481de9c 5103 continue;
b481de9c
ZY		 5104
5105 if (is_channel_a_band(ch))
8211ef78 5106 sband = &priv->bands[IEEE80211_BAND_5GHZ];
8318d78a 5107 else
8211ef78 5108 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 5109
8211ef78
TW		 5110 geo_ch = &sband->channels[sband->n_channels++];
5111
5112 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB		 5113 geo_ch->max_power = ch->max_power_avg;
5114 geo_ch->max_antenna_gain = 0xff;
7b72304d 5115 geo_ch->hw_value = ch->channel;
b481de9c
ZY		 5116
5117 if (is_channel_valid(ch)) {
8318d78a
JB		 5118 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
5119 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 5120
8318d78a
JB		 5121 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
5122 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY		 5123
5124 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 5125 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY		 5126
5127 if (ch->max_power_avg > priv->max_channel_txpower_limit)
5128 priv->max_channel_txpower_limit =
5129 ch->max_power_avg;
8211ef78 5130 } else {
8318d78a 5131 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW		 5132 }
5133
5134 /* Save flags for reg domain usage */
5135 geo_ch->orig_flags = geo_ch->flags;
5136
5137 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
5138 ch->channel, geo_ch->center_freq,
5139 is_channel_a_band(ch) ? "5.2" : "2.4",
5140 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
5141 "restricted" : "valid",
5142 geo_ch->flags);
b481de9c
ZY		 5143 }
5144
82b9a121
TW		 5145 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
5146 priv->cfg->sku & IWL_SKU_A) {
b481de9c
ZY		 5147 printk(KERN_INFO DRV_NAME
5148 ": Incorrectly detected BG card as ABG. Please send "
5149 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
5150 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 5151 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY		 5152 }
5153
5154 printk(KERN_INFO DRV_NAME
5155 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB		 5156 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
5157 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 5158
e0e0a67e
JL		 5159 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
5160 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
5161 &priv->bands[IEEE80211_BAND_2GHZ];
5162 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
5163 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
5164 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 5165
b481de9c
ZY		 5166 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5167
5168 return 0;
5169}
5170
849e0dce
RC		 5171/*
5172 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
5173 */
5174static void iwl3945_free_geos(struct iwl3945_priv *priv)
5175{
849e0dce
RC		 5176 kfree(priv->ieee_channels);
5177 kfree(priv->ieee_rates);
5178 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5179}
5180
b481de9c
ZY		 5181/******************************************************************************
5182 *
5183 * uCode download functions
5184 *
5185 ******************************************************************************/
5186
bb8c093b 5187static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
b481de9c 5188{
98c92211
TW		 5189 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5190 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5191 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5192 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5193 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5194 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 5195}
5196
5197/**
bb8c093b 5198 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5199 * looking at all data.
5200 */
bb8c093b 5201static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
b481de9c
ZY		 5202{
5203 u32 val;
5204 u32 save_len = len;
5205 int rc = 0;
5206 u32 errcnt;
5207
5208 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5209
bb8c093b 5210 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5211 if (rc)
5212 return rc;
5213
bb8c093b 5214 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY		 5215
5216 errcnt = 0;
5217 for (; len > 0; len -= sizeof(u32), image++) {
5218 /* read data comes through single port, auto-incr addr */
5219 /* NOTE: Use the debugless read so we don't flood kernel log
5220 * if IWL_DL_IO is set */
bb8c093b 5221 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5222 if (val != le32_to_cpu(*image)) {
5223 IWL_ERROR("uCode INST section is invalid at "
5224 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5225 save_len - len, val, le32_to_cpu(*image));
5226 rc = -EIO;
5227 errcnt++;
5228 if (errcnt >= 20)
5229 break;
5230 }
5231 }
5232
bb8c093b 5233 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5234
5235 if (!errcnt)
bc434dd2 5236 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY		 5237
5238 return rc;
5239}
5240
5241
5242/**
bb8c093b 5243 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5244 * using sample data 100 bytes apart. If these sample points are good,
5245 * it's a pretty good bet that everything between them is good, too.
5246 */
bb8c093b 5247static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5248{
5249 u32 val;
5250 int rc = 0;
5251 u32 errcnt = 0;
5252 u32 i;
5253
5254 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5255
bb8c093b 5256 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5257 if (rc)
5258 return rc;
5259
5260 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5261 /* read data comes through single port, auto-incr addr */
5262 /* NOTE: Use the debugless read so we don't flood kernel log
5263 * if IWL_DL_IO is set */
bb8c093b 5264 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5265 i + RTC_INST_LOWER_BOUND);
bb8c093b 5266 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5267 if (val != le32_to_cpu(*image)) {
5268#if 0 /* Enable this if you want to see details */
5269 IWL_ERROR("uCode INST section is invalid at "
5270 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5271 i, val, *image);
5272#endif
5273 rc = -EIO;
5274 errcnt++;
5275 if (errcnt >= 3)
5276 break;
5277 }
5278 }
5279
bb8c093b 5280 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5281
5282 return rc;
5283}
5284
5285
5286/**
bb8c093b 5287 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 5288 * and verify its contents
5289 */
bb8c093b 5290static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
b481de9c
ZY		 5291{
5292 __le32 *image;
5293 u32 len;
5294 int rc = 0;
5295
5296 /* Try bootstrap */
5297 image = (__le32 *)priv->ucode_boot.v_addr;
5298 len = priv->ucode_boot.len;
bb8c093b 5299 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5300 if (rc == 0) {
5301 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5302 return 0;
5303 }
5304
5305 /* Try initialize */
5306 image = (__le32 *)priv->ucode_init.v_addr;
5307 len = priv->ucode_init.len;
bb8c093b 5308 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5309 if (rc == 0) {
5310 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5311 return 0;
5312 }
5313
5314 /* Try runtime/protocol */
5315 image = (__le32 *)priv->ucode_code.v_addr;
5316 len = priv->ucode_code.len;
bb8c093b 5317 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5318 if (rc == 0) {
5319 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5320 return 0;
5321 }
5322
5323 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5324
9fbab516
BC		 5325 /* Since nothing seems to match, show first several data entries in
5326 * instruction SRAM, so maybe visual inspection will give a clue.
5327 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 5328 image = (__le32 *)priv->ucode_boot.v_addr;
5329 len = priv->ucode_boot.len;
bb8c093b 5330 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY		 5331
5332 return rc;
5333}
5334
5335
5336/* check contents of special bootstrap uCode SRAM */
bb8c093b 5337static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5338{
5339 __le32 *image = priv->ucode_boot.v_addr;
5340 u32 len = priv->ucode_boot.len;
5341 u32 reg;
5342 u32 val;
5343
5344 IWL_DEBUG_INFO("Begin verify bsm\n");
5345
5346 /* verify BSM SRAM contents */
bb8c093b 5347 val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY		 5348 for (reg = BSM_SRAM_LOWER_BOUND;
5349 reg < BSM_SRAM_LOWER_BOUND + len;
5350 reg += sizeof(u32), image ++) {
bb8c093b 5351 val = iwl3945_read_prph(priv, reg);
b481de9c
ZY		 5352 if (val != le32_to_cpu(*image)) {
5353 IWL_ERROR("BSM uCode verification failed at "
5354 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5355 BSM_SRAM_LOWER_BOUND,
5356 reg - BSM_SRAM_LOWER_BOUND, len,
5357 val, le32_to_cpu(*image));
5358 return -EIO;
5359 }
5360 }
5361
5362 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5363
5364 return 0;
5365}
5366
5367/**
bb8c093b 5368 * iwl3945_load_bsm - Load bootstrap instructions
b481de9c
ZY		 5369 *
5370 * BSM operation:
5371 *
5372 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5373 * in special SRAM that does not power down during RFKILL. When powering back
5374 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5375 * the bootstrap program into the on-board processor, and starts it.
5376 *
5377 * The bootstrap program loads (via DMA) instructions and data for a new
5378 * program from host DRAM locations indicated by the host driver in the
5379 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5380 * automatically.
5381 *
5382 * When initializing the NIC, the host driver points the BSM to the
5383 * "initialize" uCode image. This uCode sets up some internal data, then
5384 * notifies host via "initialize alive" that it is complete.
5385 *
5386 * The host then replaces the BSM_DRAM_* pointer values to point to the
5387 * normal runtime uCode instructions and a backup uCode data cache buffer
5388 * (filled initially with starting data values for the on-board processor),
5389 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5390 * which begins normal operation.
5391 *
5392 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5393 * the backup data cache in DRAM before SRAM is powered down.
5394 *
5395 * When powering back up, the BSM loads the bootstrap program. This reloads
5396 * the runtime uCode instructions and the backup data cache into SRAM,
5397 * and re-launches the runtime uCode from where it left off.
5398 */
bb8c093b 5399static int iwl3945_load_bsm(struct iwl3945_priv *priv)
b481de9c
ZY		 5400{
5401 __le32 *image = priv->ucode_boot.v_addr;
5402 u32 len = priv->ucode_boot.len;
5403 dma_addr_t pinst;
5404 dma_addr_t pdata;
5405 u32 inst_len;
5406 u32 data_len;
5407 int rc;
5408 int i;
5409 u32 done;
5410 u32 reg_offset;
5411
5412 IWL_DEBUG_INFO("Begin load bsm\n");
5413
5414 /* make sure bootstrap program is no larger than BSM's SRAM size */
5415 if (len > IWL_MAX_BSM_SIZE)
5416 return -EINVAL;
5417
5418 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5419 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
bb8c093b 5420 * NOTE: iwl3945_initialize_alive_start() will replace these values,
b481de9c
ZY		 5421 * after the "initialize" uCode has run, to point to
5422 * runtime/protocol instructions and backup data cache. */
5423 pinst = priv->ucode_init.p_addr;
5424 pdata = priv->ucode_init_data.p_addr;
5425 inst_len = priv->ucode_init.len;
5426 data_len = priv->ucode_init_data.len;
5427
bb8c093b 5428 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5429 if (rc)
5430 return rc;
5431
bb8c093b
CH		 5432 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5433 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5434 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5435 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY		 5436
5437 /* Fill BSM memory with bootstrap instructions */
5438 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5439 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5440 reg_offset += sizeof(u32), image++)
bb8c093b 5441 _iwl3945_write_prph(priv, reg_offset,
b481de9c
ZY		 5442 le32_to_cpu(*image));
5443
bb8c093b 5444 rc = iwl3945_verify_bsm(priv);
b481de9c 5445 if (rc) {
bb8c093b 5446 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5447 return rc;
5448 }
5449
5450 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
bb8c093b
CH		 5451 iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5452 iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5453 RTC_INST_LOWER_BOUND);
bb8c093b 5454 iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY		 5455
5456 /* Load bootstrap code into instruction SRAM now,
5457 * to prepare to load "initialize" uCode */
bb8c093b 5458 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5459 BSM_WR_CTRL_REG_BIT_START);
5460
5461 /* Wait for load of bootstrap uCode to finish */
5462 for (i = 0; i < 100; i++) {
bb8c093b 5463 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY		 5464 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5465 break;
5466 udelay(10);
5467 }
5468 if (i < 100)
5469 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5470 else {
5471 IWL_ERROR("BSM write did not complete!\n");
5472 return -EIO;
5473 }
5474
5475 /* Enable future boot loads whenever power management unit triggers it
5476 * (e.g. when powering back up after power-save shutdown) */
bb8c093b 5477 iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5478 BSM_WR_CTRL_REG_BIT_START_EN);
5479
bb8c093b 5480 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5481
5482 return 0;
5483}
5484
bb8c093b 5485static void iwl3945_nic_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5486{
5487 /* Remove all resets to allow NIC to operate */
bb8c093b 5488 iwl3945_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 5489}
5490
5491/**
bb8c093b 5492 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 5493 *
5494 * Copy into buffers for card to fetch via bus-mastering
5495 */
bb8c093b 5496static int iwl3945_read_ucode(struct iwl3945_priv *priv)
b481de9c 5497{
bb8c093b 5498 struct iwl3945_ucode *ucode;
90e759d1 5499 int ret = 0;
b481de9c
ZY		 5500 const struct firmware *ucode_raw;
5501 /* firmware file name contains uCode/driver compatibility version */
4bf775cd 5502 const char *name = priv->cfg->fw_name;
b481de9c
ZY		 5503 u8 *src;
5504 size_t len;
5505 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
5506
5507 /* Ask kernel firmware_class module to get the boot firmware off disk.
5508 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW		 5509 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
5510 if (ret < 0) {
5511 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5512 name, ret);
b481de9c
ZY		 5513 goto error;
5514 }
5515
5516 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5517 name, ucode_raw->size);
5518
5519 /* Make sure that we got at least our header! */
5520 if (ucode_raw->size < sizeof(*ucode)) {
5521 IWL_ERROR("File size way too small!\n");
90e759d1 5522 ret = -EINVAL;
b481de9c
ZY		 5523 goto err_release;
5524 }
5525
5526 /* Data from ucode file: header followed by uCode images */
5527 ucode = (void *)ucode_raw->data;
5528
5529 ver = le32_to_cpu(ucode->ver);
5530 inst_size = le32_to_cpu(ucode->inst_size);
5531 data_size = le32_to_cpu(ucode->data_size);
5532 init_size = le32_to_cpu(ucode->init_size);
5533 init_data_size = le32_to_cpu(ucode->init_data_size);
5534 boot_size = le32_to_cpu(ucode->boot_size);
5535
5536 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
bc434dd2
IS		 5537 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5538 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5539 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5540 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5541 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c
ZY		 5542
5543 /* Verify size of file vs. image size info in file's header */
5544 if (ucode_raw->size < sizeof(*ucode) +
5545 inst_size + data_size + init_size +
5546 init_data_size + boot_size) {
5547
5548 IWL_DEBUG_INFO("uCode file size %d too small\n",
5549 (int)ucode_raw->size);
90e759d1 5550 ret = -EINVAL;
b481de9c
ZY		 5551 goto err_release;
5552 }
5553
5554 /* Verify that uCode images will fit in card's SRAM */
5555 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5556 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5557 inst_size);
5558 ret = -EINVAL;
b481de9c
ZY		 5559 goto err_release;
5560 }
5561
5562 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5563 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5564 data_size);
5565 ret = -EINVAL;
b481de9c
ZY		 5566 goto err_release;
5567 }
5568 if (init_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5569 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5570 init_size);
5571 ret = -EINVAL;
b481de9c
ZY		 5572 goto err_release;
5573 }
5574 if (init_data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5575 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5576 init_data_size);
5577 ret = -EINVAL;
b481de9c
ZY		 5578 goto err_release;
5579 }
5580 if (boot_size > IWL_MAX_BSM_SIZE) {
90e759d1
TW		 5581 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5582 boot_size);
5583 ret = -EINVAL;
b481de9c
ZY		 5584 goto err_release;
5585 }
5586
5587 /* Allocate ucode buffers for card's bus-master loading ... */
5588
5589 /* Runtime instructions and 2 copies of data:
5590 * 1) unmodified from disk
5591 * 2) backup cache for save/restore during power-downs */
5592 priv->ucode_code.len = inst_size;
98c92211 5593 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 5594
5595 priv->ucode_data.len = data_size;
98c92211 5596 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 5597
5598 priv->ucode_data_backup.len = data_size;
98c92211 5599 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 5600
90e759d1
TW		 5601 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5602 !priv->ucode_data_backup.v_addr)
5603 goto err_pci_alloc;
b481de9c
ZY		 5604
5605 /* Initialization instructions and data */
90e759d1
TW		 5606 if (init_size && init_data_size) {
5607 priv->ucode_init.len = init_size;
98c92211 5608 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 5609
5610 priv->ucode_init_data.len = init_data_size;
98c92211 5611 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 5612
5613 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5614 goto err_pci_alloc;
5615 }
b481de9c
ZY		 5616
5617 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 5618 if (boot_size) {
5619 priv->ucode_boot.len = boot_size;
98c92211 5620 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5621
90e759d1
TW		 5622 if (!priv->ucode_boot.v_addr)
5623 goto err_pci_alloc;
5624 }
b481de9c
ZY		 5625
5626 /* Copy images into buffers for card's bus-master reads ... */
5627
5628 /* Runtime instructions (first block of data in file) */
5629 src = &ucode->data[0];
5630 len = priv->ucode_code.len;
90e759d1 5631 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 5632 memcpy(priv->ucode_code.v_addr, src, len);
5633 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5634 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5635
5636 /* Runtime data (2nd block)
bb8c093b 5637 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY		 5638 src = &ucode->data[inst_size];
5639 len = priv->ucode_data.len;
90e759d1 5640 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 5641 memcpy(priv->ucode_data.v_addr, src, len);
5642 memcpy(priv->ucode_data_backup.v_addr, src, len);
5643
5644 /* Initialization instructions (3rd block) */
5645 if (init_size) {
5646 src = &ucode->data[inst_size + data_size];
5647 len = priv->ucode_init.len;
90e759d1
TW		 5648 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5649 len);
b481de9c
ZY		 5650 memcpy(priv->ucode_init.v_addr, src, len);
5651 }
5652
5653 /* Initialization data (4th block) */
5654 if (init_data_size) {
5655 src = &ucode->data[inst_size + data_size + init_size];
5656 len = priv->ucode_init_data.len;
5657 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5658 (int)len);
5659 memcpy(priv->ucode_init_data.v_addr, src, len);
5660 }
5661
5662 /* Bootstrap instructions (5th block) */
5663 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5664 len = priv->ucode_boot.len;
5665 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5666 (int)len);
5667 memcpy(priv->ucode_boot.v_addr, src, len);
5668
5669 /* We have our copies now, allow OS release its copies */
5670 release_firmware(ucode_raw);
5671 return 0;
5672
5673 err_pci_alloc:
5674 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 5675 ret = -ENOMEM;
bb8c093b 5676 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 5677
5678 err_release:
5679 release_firmware(ucode_raw);
5680
5681 error:
90e759d1 5682 return ret;
b481de9c
ZY		 5683}
5684
5685
5686/**
bb8c093b 5687 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 5688 *
5689 * Tell initialization uCode where to find runtime uCode.
5690 *
5691 * BSM registers initially contain pointers to initialization uCode.
5692 * We need to replace them to load runtime uCode inst and data,
5693 * and to save runtime data when powering down.
5694 */
bb8c093b 5695static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
b481de9c
ZY		 5696{
5697 dma_addr_t pinst;
5698 dma_addr_t pdata;
5699 int rc = 0;
5700 unsigned long flags;
5701
5702 /* bits 31:0 for 3945 */
5703 pinst = priv->ucode_code.p_addr;
5704 pdata = priv->ucode_data_backup.p_addr;
5705
5706 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5707 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5708 if (rc) {
5709 spin_unlock_irqrestore(&priv->lock, flags);
5710 return rc;
5711 }
5712
5713 /* Tell bootstrap uCode where to find image to load */
bb8c093b
CH		 5714 iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5715 iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5716 iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 5717 priv->ucode_data.len);
5718
5719 /* Inst bytecount must be last to set up, bit 31 signals uCode
5720 * that all new ptr/size info is in place */
bb8c093b 5721 iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 5722 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5723
bb8c093b 5724 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5725
5726 spin_unlock_irqrestore(&priv->lock, flags);
5727
5728 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5729
5730 return rc;
5731}
5732
5733/**
bb8c093b 5734 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 5735 *
5736 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5737 *
b481de9c 5738 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 5739 */
bb8c093b 5740static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5741{
5742 /* Check alive response for "valid" sign from uCode */
5743 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5744 /* We had an error bringing up the hardware, so take it
5745 * all the way back down so we can try again */
5746 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5747 goto restart;
5748 }
5749
5750 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5751 * This is a paranoid check, because we would not have gotten the
5752 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5753 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5754 /* Runtime instruction load was bad;
5755 * take it all the way back down so we can try again */
5756 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5757 goto restart;
5758 }
5759
5760 /* Send pointers to protocol/runtime uCode image ... init code will
5761 * load and launch runtime uCode, which will send us another "Alive"
5762 * notification. */
5763 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5764 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY		 5765 /* Runtime instruction load won't happen;
5766 * take it all the way back down so we can try again */
5767 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5768 goto restart;
5769 }
5770 return;
5771
5772 restart:
5773 queue_work(priv->workqueue, &priv->restart);
5774}
5775
5776
5777/**
bb8c093b 5778 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 5779 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5780 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 5781 */
bb8c093b 5782static void iwl3945_alive_start(struct iwl3945_priv *priv)
b481de9c
ZY		 5783{
5784 int rc = 0;
5785 int thermal_spin = 0;
5786 u32 rfkill;
5787
5788 IWL_DEBUG_INFO("Runtime Alive received.\n");
5789
5790 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5791 /* We had an error bringing up the hardware, so take it
5792 * all the way back down so we can try again */
5793 IWL_DEBUG_INFO("Alive failed.\n");
5794 goto restart;
5795 }
5796
5797 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5798 * This is a paranoid check, because we would not have gotten the
5799 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5800 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5801 /* Runtime instruction load was bad;
5802 * take it all the way back down so we can try again */
5803 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5804 goto restart;
5805 }
5806
bb8c093b 5807 iwl3945_clear_stations_table(priv);
b481de9c 5808
bb8c093b 5809 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 5810 if (rc) {
5811 IWL_WARNING("Can not read rfkill status from adapter\n");
5812 return;
5813 }
5814
bb8c093b 5815 rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
b481de9c 5816 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
bb8c093b 5817 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5818
5819 if (rfkill & 0x1) {
5820 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5821 /* if rfkill is not on, then wait for thermal
5822 * sensor in adapter to kick in */
bb8c093b 5823 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY		 5824 thermal_spin++;
5825 udelay(10);
5826 }
5827
5828 if (thermal_spin)
5829 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5830 thermal_spin * 10);
5831 } else
5832 set_bit(STATUS_RF_KILL_HW, &priv->status);
5833
9fbab516 5834 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY		 5835 set_bit(STATUS_ALIVE, &priv->status);
5836
5837 /* Clear out the uCode error bit if it is set */
5838 clear_bit(STATUS_FW_ERROR, &priv->status);
5839
bb8c093b 5840 if (iwl3945_is_rfkill(priv))
b481de9c
ZY		 5841 return;
5842
36d6825b 5843 ieee80211_wake_queues(priv->hw);
b481de9c
ZY		 5844
5845 priv->active_rate = priv->rates_mask;
5846 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5847
bb8c093b 5848 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5849
bb8c093b
CH		 5850 if (iwl3945_is_associated(priv)) {
5851 struct iwl3945_rxon_cmd *active_rxon =
5852 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY		 5853
5854 memcpy(&priv->staging_rxon, &priv->active_rxon,
5855 sizeof(priv->staging_rxon));
5856 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5857 } else {
5858 /* Initialize our rx_config data */
bb8c093b 5859 iwl3945_connection_init_rx_config(priv);
b481de9c
ZY		 5860 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
5861 }
5862
9fbab516 5863 /* Configure Bluetooth device coexistence support */
bb8c093b 5864 iwl3945_send_bt_config(priv);
b481de9c
ZY		 5865
5866 /* Configure the adapter for unassociated operation */
bb8c093b 5867 iwl3945_commit_rxon(priv);
b481de9c 5868
b481de9c
ZY		 5869 iwl3945_reg_txpower_periodic(priv);
5870
fe00b5a5
RC		 5871 iwl3945_led_register(priv);
5872
b481de9c 5873 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5874 set_bit(STATUS_READY, &priv->status);
5a66926a 5875 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 5876
5877 if (priv->error_recovering)
bb8c093b 5878 iwl3945_error_recovery(priv);
b481de9c 5879
84363e6e 5880 ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
b481de9c
ZY		 5881 return;
5882
5883 restart:
5884 queue_work(priv->workqueue, &priv->restart);
5885}
5886
bb8c093b 5887static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
b481de9c 5888
bb8c093b 5889static void __iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5890{
5891 unsigned long flags;
5892 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5893 struct ieee80211_conf *conf = NULL;
5894
5895 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5896
5897 conf = ieee80211_get_hw_conf(priv->hw);
5898
5899 if (!exit_pending)
5900 set_bit(STATUS_EXIT_PENDING, &priv->status);
5901
ab53d8af 5902 iwl3945_led_unregister(priv);
bb8c093b 5903 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5904
5905 /* Unblock any waiting calls */
5906 wake_up_interruptible_all(&priv->wait_command_queue);
5907
b481de9c
ZY		 5908 /* Wipe out the EXIT_PENDING status bit if we are not actually
5909 * exiting the module */
5910 if (!exit_pending)
5911 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5912
5913 /* stop and reset the on-board processor */
bb8c093b 5914 iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 5915
5916 /* tell the device to stop sending interrupts */
0359facc 5917 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5918 iwl3945_disable_interrupts(priv);
0359facc
MA		 5919 spin_unlock_irqrestore(&priv->lock, flags);
5920 iwl_synchronize_irq(priv);
b481de9c
ZY		 5921
5922 if (priv->mac80211_registered)
5923 ieee80211_stop_queues(priv->hw);
5924
bb8c093b 5925 /* If we have not previously called iwl3945_init() then
b481de9c 5926 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 5927 if (!iwl3945_is_init(priv)) {
b481de9c
ZY		 5928 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5929 STATUS_RF_KILL_HW |
5930 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5931 STATUS_RF_KILL_SW |
9788864e
RC		 5932 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5933 STATUS_GEO_CONFIGURED |
b481de9c 5934 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
ebef2008
AK		 5935 STATUS_IN_SUSPEND |
5936 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5937 STATUS_EXIT_PENDING;
b481de9c
ZY		 5938 goto exit;
5939 }
5940
5941 /* ...otherwise clear out all the status bits but the RF Kill and
5942 * SUSPEND bits and continue taking the NIC down. */
5943 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5944 STATUS_RF_KILL_HW |
5945 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5946 STATUS_RF_KILL_SW |
9788864e
RC		 5947 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5948 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5949 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5950 STATUS_IN_SUSPEND |
5951 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK		 5952 STATUS_FW_ERROR |
5953 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5954 STATUS_EXIT_PENDING;
b481de9c
ZY		 5955
5956 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5957 iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 5958 spin_unlock_irqrestore(&priv->lock, flags);
5959
bb8c093b
CH		 5960 iwl3945_hw_txq_ctx_stop(priv);
5961 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY		 5962
5963 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 5964 if (!iwl3945_grab_nic_access(priv)) {
5965 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5966 APMG_CLK_VAL_DMA_CLK_RQT);
bb8c093b 5967 iwl3945_release_nic_access(priv);
b481de9c
ZY		 5968 }
5969 spin_unlock_irqrestore(&priv->lock, flags);
5970
5971 udelay(5);
5972
bb8c093b
CH		 5973 iwl3945_hw_nic_stop_master(priv);
5974 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
5975 iwl3945_hw_nic_reset(priv);
b481de9c
ZY		 5976
5977 exit:
bb8c093b 5978 memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
b481de9c
ZY		 5979
5980 if (priv->ibss_beacon)
5981 dev_kfree_skb(priv->ibss_beacon);
5982 priv->ibss_beacon = NULL;
5983
5984 /* clear out any free frames */
bb8c093b 5985 iwl3945_clear_free_frames(priv);
b481de9c
ZY		 5986}
5987
bb8c093b 5988static void iwl3945_down(struct iwl3945_priv *priv)
b481de9c
ZY		 5989{
5990 mutex_lock(&priv->mutex);
bb8c093b 5991 __iwl3945_down(priv);
b481de9c 5992 mutex_unlock(&priv->mutex);
b24d22b1 5993
bb8c093b 5994 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY		 5995}
5996
5997#define MAX_HW_RESTARTS 5
5998
bb8c093b 5999static int __iwl3945_up(struct iwl3945_priv *priv)
b481de9c
ZY		 6000{
6001 int rc, i;
6002
6003 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6004 IWL_WARNING("Exit pending; will not bring the NIC up\n");
6005 return -EIO;
6006 }
6007
6008 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
6009 IWL_WARNING("Radio disabled by SW RF kill (module "
6010 "parameter)\n");
e655b9f0
ZY		 6011 return -ENODEV;
6012 }
6013
e903fbd4
RC		 6014 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
6015 IWL_ERROR("ucode not available for device bringup\n");
6016 return -EIO;
6017 }
6018
e655b9f0
ZY		 6019 /* If platform's RF_KILL switch is NOT set to KILL */
6020 if (iwl3945_read32(priv, CSR_GP_CNTRL) &
6021 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6022 clear_bit(STATUS_RF_KILL_HW, &priv->status);
6023 else {
6024 set_bit(STATUS_RF_KILL_HW, &priv->status);
6025 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
6026 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
6027 return -ENODEV;
6028 }
b481de9c 6029 }
80fcc9e2 6030
bb8c093b 6031 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 6032
bb8c093b 6033 rc = iwl3945_hw_nic_init(priv);
b481de9c
ZY		 6034 if (rc) {
6035 IWL_ERROR("Unable to int nic\n");
6036 return rc;
6037 }
6038
6039 /* make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6040 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6041 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 6042 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
6043
6044 /* clear (again), then enable host interrupts */
bb8c093b
CH		 6045 iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
6046 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 6047
6048 /* really make sure rfkill handshake bits are cleared */
bb8c093b
CH		 6049 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
6050 iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 6051
6052 /* Copy original ucode data image from disk into backup cache.
6053 * This will be used to initialize the on-board processor's
6054 * data SRAM for a clean start when the runtime program first loads. */
6055 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 6056 priv->ucode_data.len);
b481de9c 6057
e655b9f0
ZY		 6058 /* We return success when we resume from suspend and rf_kill is on. */
6059 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
6060 return 0;
6061
b481de9c
ZY		 6062 for (i = 0; i < MAX_HW_RESTARTS; i++) {
6063
bb8c093b 6064 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 6065
6066 /* load bootstrap state machine,
6067 * load bootstrap program into processor's memory,
6068 * prepare to load the "initialize" uCode */
bb8c093b 6069 rc = iwl3945_load_bsm(priv);
b481de9c
ZY		 6070
6071 if (rc) {
6072 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
6073 continue;
6074 }
6075
6076 /* start card; "initialize" will load runtime ucode */
bb8c093b 6077 iwl3945_nic_start(priv);
b481de9c 6078
b481de9c
ZY		 6079 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
6080
6081 return 0;
6082 }
6083
6084 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 6085 __iwl3945_down(priv);
ebef2008 6086 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 6087
6088 /* tried to restart and config the device for as long as our
6089 * patience could withstand */
6090 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
6091 return -EIO;
6092}
6093
6094
6095/*****************************************************************************
6096 *
6097 * Workqueue callbacks
6098 *
6099 *****************************************************************************/
6100
bb8c093b 6101static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 6102{
bb8c093b
CH		 6103 struct iwl3945_priv *priv =
6104 container_of(data, struct iwl3945_priv, init_alive_start.work);
b481de9c
ZY		 6105
6106 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6107 return;
6108
6109 mutex_lock(&priv->mutex);
bb8c093b 6110 iwl3945_init_alive_start(priv);
b481de9c
ZY		 6111 mutex_unlock(&priv->mutex);
6112}
6113
bb8c093b 6114static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 6115{
bb8c093b
CH		 6116 struct iwl3945_priv *priv =
6117 container_of(data, struct iwl3945_priv, alive_start.work);
b481de9c
ZY		 6118
6119 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6120 return;
6121
6122 mutex_lock(&priv->mutex);
bb8c093b 6123 iwl3945_alive_start(priv);
b481de9c
ZY		 6124 mutex_unlock(&priv->mutex);
6125}
6126
bb8c093b 6127static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 6128{
bb8c093b 6129 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
b481de9c
ZY		 6130
6131 wake_up_interruptible(&priv->wait_command_queue);
6132
6133 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6134 return;
6135
6136 mutex_lock(&priv->mutex);
6137
bb8c093b 6138 if (!iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6139 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6140 "HW and/or SW RF Kill no longer active, restarting "
6141 "device\n");
6142 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6143 queue_work(priv->workqueue, &priv->restart);
6144 } else {
6145
6146 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6147 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6148 "disabled by SW switch\n");
6149 else
6150 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6151 "Kill switch must be turned off for "
6152 "wireless networking to work.\n");
6153 }
ebef2008 6154
b481de9c 6155 mutex_unlock(&priv->mutex);
80fcc9e2 6156 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 6157}
6158
5ec03976
AK		 6159static void iwl3945_bg_set_monitor(struct work_struct *work)
6160{
6161 struct iwl3945_priv *priv = container_of(work,
6162 struct iwl3945_priv, set_monitor);
6163
6164 IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
6165
6166 mutex_lock(&priv->mutex);
6167
6168 if (!iwl3945_is_ready(priv))
6169 IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
6170 else
6171 if (iwl3945_set_mode(priv, IEEE80211_IF_TYPE_MNTR) != 0)
6172 IWL_ERROR("iwl3945_set_mode() failed\n");
6173
6174 mutex_unlock(&priv->mutex);
6175}
6176
b481de9c
ZY		 6177#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6178
bb8c093b 6179static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 6180{
bb8c093b
CH		 6181 struct iwl3945_priv *priv =
6182 container_of(data, struct iwl3945_priv, scan_check.work);
b481de9c
ZY		 6183
6184 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6185 return;
6186
6187 mutex_lock(&priv->mutex);
6188 if (test_bit(STATUS_SCANNING, &priv->status) ||
6189 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6190 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6191 "Scan completion watchdog resetting adapter (%dms)\n",
6192 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 6193
b481de9c 6194 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6195 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6196 }
6197 mutex_unlock(&priv->mutex);
6198}
6199
bb8c093b 6200static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 6201{
bb8c093b
CH		 6202 struct iwl3945_priv *priv =
6203 container_of(data, struct iwl3945_priv, request_scan);
6204 struct iwl3945_host_cmd cmd = {
b481de9c 6205 .id = REPLY_SCAN_CMD,
bb8c093b 6206 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY		 6207 .meta.flags = CMD_SIZE_HUGE,
6208 };
6209 int rc = 0;
bb8c093b 6210 struct iwl3945_scan_cmd *scan;
b481de9c
ZY		 6211 struct ieee80211_conf *conf = NULL;
6212 u8 direct_mask;
8318d78a 6213 enum ieee80211_band band;
b481de9c
ZY		 6214
6215 conf = ieee80211_get_hw_conf(priv->hw);
6216
6217 mutex_lock(&priv->mutex);
6218
bb8c093b 6219 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 6220 IWL_WARNING("request scan called when driver not ready.\n");
6221 goto done;
6222 }
6223
6224 /* Make sure the scan wasn't cancelled before this queued work
6225 * was given the chance to run... */
6226 if (!test_bit(STATUS_SCANNING, &priv->status))
6227 goto done;
6228
6229 /* This should never be called or scheduled if there is currently
6230 * a scan active in the hardware. */
6231 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6232 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6233 "Ignoring second request.\n");
6234 rc = -EIO;
6235 goto done;
6236 }
6237
6238 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6239 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6240 goto done;
6241 }
6242
6243 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6244 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6245 goto done;
6246 }
6247
bb8c093b 6248 if (iwl3945_is_rfkill(priv)) {
b481de9c
ZY		 6249 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6250 goto done;
6251 }
6252
6253 if (!test_bit(STATUS_READY, &priv->status)) {
6254 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6255 goto done;
6256 }
6257
6258 if (!priv->scan_bands) {
6259 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6260 goto done;
6261 }
6262
6263 if (!priv->scan) {
bb8c093b 6264 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c
ZY		 6265 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6266 if (!priv->scan) {
6267 rc = -ENOMEM;
6268 goto done;
6269 }
6270 }
6271 scan = priv->scan;
bb8c093b 6272 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 6273
6274 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6275 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6276
bb8c093b 6277 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 6278 u16 interval = 0;
6279 u32 extra;
6280 u32 suspend_time = 100;
6281 u32 scan_suspend_time = 100;
6282 unsigned long flags;
6283
6284 IWL_DEBUG_INFO("Scanning while associated...\n");
6285
6286 spin_lock_irqsave(&priv->lock, flags);
6287 interval = priv->beacon_int;
6288 spin_unlock_irqrestore(&priv->lock, flags);
6289
6290 scan->suspend_time = 0;
15e869d8 6291 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 6292 if (!interval)
6293 interval = suspend_time;
6294 /*
6295 * suspend time format:
6296 * 0-19: beacon interval in usec (time before exec.)
6297 * 20-23: 0
6298 * 24-31: number of beacons (suspend between channels)
6299 */
6300
6301 extra = (suspend_time / interval) << 24;
6302 scan_suspend_time = 0xFF0FFFFF &
6303 (extra | ((suspend_time % interval) * 1024));
6304
6305 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6306 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6307 scan_suspend_time, interval);
6308 }
6309
6310 /* We should add the ability for user to lock to PASSIVE ONLY */
6311 if (priv->one_direct_scan) {
6312 IWL_DEBUG_SCAN
6313 ("Kicking off one direct scan for '%s'\n",
bb8c093b 6314 iwl3945_escape_essid(priv->direct_ssid,
b481de9c
ZY		 6315 priv->direct_ssid_len));
6316 scan->direct_scan[0].id = WLAN_EID_SSID;
6317 scan->direct_scan[0].len = priv->direct_ssid_len;
6318 memcpy(scan->direct_scan[0].ssid,
6319 priv->direct_ssid, priv->direct_ssid_len);
6320 direct_mask = 1;
bb8c093b 6321 } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
786b4557
BM		 6322 IWL_DEBUG_SCAN
6323 ("Kicking off one direct scan for '%s' when not associated\n",
6324 iwl3945_escape_essid(priv->essid, priv->essid_len));
b481de9c
ZY		 6325 scan->direct_scan[0].id = WLAN_EID_SSID;
6326 scan->direct_scan[0].len = priv->essid_len;
6327 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
6328 direct_mask = 1;
786b4557
BM		 6329 } else {
6330 IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
b481de9c 6331 direct_mask = 0;
786b4557 6332 }
b481de9c
ZY		 6333
6334 /* We don't build a direct scan probe request; the uCode will do
6335 * that based on the direct_mask added to each channel entry */
6336 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 6337 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
18904f58 6338 IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
b481de9c
ZY		 6339 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6340 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6341 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6342
6343 /* flags + rate selection */
6344
66b5004d 6345 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY		 6346 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6347 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
6348 scan->good_CRC_th = 0;
8318d78a 6349 band = IEEE80211_BAND_2GHZ;
66b5004d 6350 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c
ZY		 6351 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
6352 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6353 band = IEEE80211_BAND_5GHZ;
66b5004d 6354 } else {
b481de9c
ZY		 6355 IWL_WARNING("Invalid scan band count\n");
6356 goto done;
6357 }
6358
6359 /* select Rx antennas */
6360 scan->flags |= iwl3945_get_antenna_flags(priv);
6361
6362 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
6363 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6364
786b4557 6365 if (direct_mask)
26c0f03f
RC		 6366 scan->channel_count =
6367 iwl3945_get_channels_for_scan(
6368 priv, band, 1, /* active */
6369 direct_mask,
6370 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
786b4557 6371 else
26c0f03f
RC		 6372 scan->channel_count =
6373 iwl3945_get_channels_for_scan(
6374 priv, band, 0, /* passive */
6375 direct_mask,
6376 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c
ZY		 6377
6378 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6379 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY		 6380 cmd.data = scan;
6381 scan->len = cpu_to_le16(cmd.len);
6382
6383 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 6384 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 6385 if (rc)
6386 goto done;
6387
6388 queue_delayed_work(priv->workqueue, &priv->scan_check,
6389 IWL_SCAN_CHECK_WATCHDOG);
6390
6391 mutex_unlock(&priv->mutex);
6392 return;
6393
6394 done:
01ebd063 6395 /* inform mac80211 scan aborted */
b481de9c
ZY		 6396 queue_work(priv->workqueue, &priv->scan_completed);
6397 mutex_unlock(&priv->mutex);
6398}
6399
bb8c093b 6400static void iwl3945_bg_up(struct work_struct *data)
b481de9c 6401{
bb8c093b 6402 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
b481de9c
ZY		 6403
6404 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6405 return;
6406
6407 mutex_lock(&priv->mutex);
bb8c093b 6408 __iwl3945_up(priv);
b481de9c 6409 mutex_unlock(&priv->mutex);
80fcc9e2 6410 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 6411}
6412
bb8c093b 6413static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 6414{
bb8c093b 6415 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
b481de9c
ZY		 6416
6417 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6418 return;
6419
bb8c093b 6420 iwl3945_down(priv);
b481de9c
ZY		 6421 queue_work(priv->workqueue, &priv->up);
6422}
6423
bb8c093b 6424static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 6425{
bb8c093b
CH		 6426 struct iwl3945_priv *priv =
6427 container_of(data, struct iwl3945_priv, rx_replenish);
b481de9c
ZY		 6428
6429 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6430 return;
6431
6432 mutex_lock(&priv->mutex);
bb8c093b 6433 iwl3945_rx_replenish(priv);
b481de9c
ZY		 6434 mutex_unlock(&priv->mutex);
6435}
6436
7878a5a4
MA		 6437#define IWL_DELAY_NEXT_SCAN (HZ*2)
6438
bb8c093b 6439static void iwl3945_bg_post_associate(struct work_struct *data)
b481de9c 6440{
bb8c093b 6441 struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
b481de9c
ZY		 6442 post_associate.work);
6443
6444 int rc = 0;
6445 struct ieee80211_conf *conf = NULL;
0795af57 6446 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6447
6448 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6449 IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
6450 return;
6451 }
6452
6453
0795af57
JP		 6454 IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
6455 priv->assoc_id,
6456 print_mac(mac, priv->active_rxon.bssid_addr));
b481de9c
ZY		 6457
6458 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6459 return;
6460
6461 mutex_lock(&priv->mutex);
6462
32bfd35d 6463 if (!priv->vif || !priv->is_open) {
6ef89d0a
MA		 6464 mutex_unlock(&priv->mutex);
6465 return;
6466 }
bb8c093b 6467 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 6468
b481de9c
ZY		 6469 conf = ieee80211_get_hw_conf(priv->hw);
6470
6471 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6472 iwl3945_commit_rxon(priv);
b481de9c 6473
bb8c093b
CH		 6474 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6475 iwl3945_setup_rxon_timing(priv);
6476 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6477 sizeof(priv->rxon_timing), &priv->rxon_timing);
6478 if (rc)
6479 IWL_WARNING("REPLY_RXON_TIMING failed - "
6480 "Attempting to continue.\n");
6481
6482 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6483
6484 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6485
6486 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6487 priv->assoc_id, priv->beacon_int);
6488
6489 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6490 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6491 else
6492 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6493
6494 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6495 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6496 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6497 else
6498 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6499
6500 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6501 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6502
6503 }
6504
bb8c093b 6505 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6506
6507 switch (priv->iw_mode) {
6508 case IEEE80211_IF_TYPE_STA:
bb8c093b 6509 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 6510 break;
6511
6512 case IEEE80211_IF_TYPE_IBSS:
6513
6514 /* clear out the station table */
bb8c093b 6515 iwl3945_clear_stations_table(priv);
b481de9c 6516
bb8c093b
CH		 6517 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
6518 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 6519 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 6520 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY		 6521 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
6522 CMD_ASYNC);
bb8c093b
CH		 6523 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
6524 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6525
6526 break;
6527
6528 default:
6529 IWL_ERROR("%s Should not be called in %d mode\n",
bc434dd2 6530 __FUNCTION__, priv->iw_mode);
b481de9c
ZY		 6531 break;
6532 }
6533
bb8c093b 6534 iwl3945_sequence_reset(priv);
b481de9c 6535
bb8c093b 6536 iwl3945_activate_qos(priv, 0);
292ae174 6537
7878a5a4
MA		 6538 /* we have just associated, don't start scan too early */
6539 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
b481de9c
ZY		 6540 mutex_unlock(&priv->mutex);
6541}
6542
bb8c093b 6543static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 6544{
bb8c093b 6545 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
b481de9c 6546
bb8c093b 6547 if (!iwl3945_is_ready(priv))
b481de9c
ZY		 6548 return;
6549
6550 mutex_lock(&priv->mutex);
6551
6552 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6553 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 6554
6555 mutex_unlock(&priv->mutex);
6556}
6557
76bb77e0
ZY		 6558static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
6559
bb8c093b 6560static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 6561{
bb8c093b
CH		 6562 struct iwl3945_priv *priv =
6563 container_of(work, struct iwl3945_priv, scan_completed);
b481de9c
ZY		 6564
6565 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6566
6567 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6568 return;
6569
a0646470
ZY		 6570 if (test_bit(STATUS_CONF_PENDING, &priv->status))
6571 iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
76bb77e0 6572
b481de9c
ZY		 6573 ieee80211_scan_completed(priv->hw);
6574
6575 /* Since setting the TXPOWER may have been deferred while
6576 * performing the scan, fire one off */
6577 mutex_lock(&priv->mutex);
bb8c093b 6578 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 6579 mutex_unlock(&priv->mutex);
6580}
6581
6582/*****************************************************************************
6583 *
6584 * mac80211 entry point functions
6585 *
6586 *****************************************************************************/
6587
5a66926a
ZY		 6588#define UCODE_READY_TIMEOUT (2 * HZ)
6589
bb8c093b 6590static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 6591{
bb8c093b 6592 struct iwl3945_priv *priv = hw->priv;
5a66926a 6593 int ret;
b481de9c
ZY		 6594
6595 IWL_DEBUG_MAC80211("enter\n");
6596
5a66926a
ZY		 6597 if (pci_enable_device(priv->pci_dev)) {
6598 IWL_ERROR("Fail to pci_enable_device\n");
6599 return -ENODEV;
6600 }
6601 pci_restore_state(priv->pci_dev);
6602 pci_enable_msi(priv->pci_dev);
6603
6604 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
6605 DRV_NAME, priv);
6606 if (ret) {
6607 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6608 goto out_disable_msi;
6609 }
6610
b481de9c
ZY		 6611 /* we should be verifying the device is ready to be opened */
6612 mutex_lock(&priv->mutex);
6613
5a66926a
ZY		 6614 memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
6615 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6616 * ucode filename and max sizes are card-specific. */
6617
6618 if (!priv->ucode_code.len) {
6619 ret = iwl3945_read_ucode(priv);
6620 if (ret) {
6621 IWL_ERROR("Could not read microcode: %d\n", ret);
6622 mutex_unlock(&priv->mutex);
6623 goto out_release_irq;
6624 }
6625 }
b481de9c 6626
e655b9f0 6627 ret = __iwl3945_up(priv);
b481de9c
ZY		 6628
6629 mutex_unlock(&priv->mutex);
5a66926a 6630
80fcc9e2
AG		 6631 iwl3945_rfkill_set_hw_state(priv);
6632
e655b9f0
ZY		 6633 if (ret)
6634 goto out_release_irq;
6635
6636 IWL_DEBUG_INFO("Start UP work.\n");
6637
6638 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6639 return 0;
6640
5a66926a
ZY		 6641 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6642 * mac80211 will not be run successfully. */
6643 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6644 test_bit(STATUS_READY, &priv->status),
6645 UCODE_READY_TIMEOUT);
6646 if (!ret) {
6647 if (!test_bit(STATUS_READY, &priv->status)) {
6648 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6649 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6650 ret = -ETIMEDOUT;
6651 goto out_release_irq;
6652 }
6653 }
6654
e655b9f0 6655 priv->is_open = 1;
b481de9c
ZY		 6656 IWL_DEBUG_MAC80211("leave\n");
6657 return 0;
5a66926a
ZY		 6658
6659out_release_irq:
6660 free_irq(priv->pci_dev->irq, priv);
6661out_disable_msi:
6662 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY		 6663 pci_disable_device(priv->pci_dev);
6664 priv->is_open = 0;
6665 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6666 return ret;
b481de9c
ZY		 6667}
6668
bb8c093b 6669static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6670{
bb8c093b 6671 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6672
6673 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6674
e655b9f0
ZY		 6675 if (!priv->is_open) {
6676 IWL_DEBUG_MAC80211("leave - skip\n");
6677 return;
6678 }
6679
b481de9c 6680 priv->is_open = 0;
5a66926a
ZY		 6681
6682 if (iwl3945_is_ready_rf(priv)) {
e655b9f0
ZY		 6683 /* stop mac, cancel any scan request and clear
6684 * RXON_FILTER_ASSOC_MSK BIT
6685 */
5a66926a
ZY		 6686 mutex_lock(&priv->mutex);
6687 iwl3945_scan_cancel_timeout(priv, 100);
6688 cancel_delayed_work(&priv->post_associate);
fde3571f 6689 mutex_unlock(&priv->mutex);
fde3571f
MA		 6690 }
6691
5a66926a
ZY		 6692 iwl3945_down(priv);
6693
6694 flush_workqueue(priv->workqueue);
6695 free_irq(priv->pci_dev->irq, priv);
6696 pci_disable_msi(priv->pci_dev);
6697 pci_save_state(priv->pci_dev);
6698 pci_disable_device(priv->pci_dev);
6ef89d0a 6699
b481de9c 6700 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6701}
6702
e039fa4a 6703static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6704{
bb8c093b 6705 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 6706
6707 IWL_DEBUG_MAC80211("enter\n");
6708
6709 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
6710 IWL_DEBUG_MAC80211("leave - monitor\n");
6afe6828
ZY		 6711 dev_kfree_skb_any(skb);
6712 return 0;
b481de9c
ZY		 6713 }
6714
6715 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 6716 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 6717
e039fa4a 6718 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY		 6719 dev_kfree_skb_any(skb);
6720
6721 IWL_DEBUG_MAC80211("leave\n");
6722 return 0;
6723}
6724
bb8c093b 6725static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6726 struct ieee80211_if_init_conf *conf)
6727{
bb8c093b 6728 struct iwl3945_priv *priv = hw->priv;
b481de9c 6729 unsigned long flags;
0795af57 6730 DECLARE_MAC_BUF(mac);
b481de9c 6731
32bfd35d 6732 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6733
32bfd35d
JB		 6734 if (priv->vif) {
6735 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6736 return -EOPNOTSUPP;
b481de9c
ZY		 6737 }
6738
6739 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6740 priv->vif = conf->vif;
b481de9c
ZY		 6741
6742 spin_unlock_irqrestore(&priv->lock, flags);
6743
6744 mutex_lock(&priv->mutex);
864792e3
TW		 6745
6746 if (conf->mac_addr) {
6747 IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
6748 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6749 }
6750
5a66926a
ZY		 6751 if (iwl3945_is_ready(priv))
6752 iwl3945_set_mode(priv, conf->type);
b481de9c 6753
b481de9c
ZY		 6754 mutex_unlock(&priv->mutex);
6755
5a66926a 6756 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6757 return 0;
6758}
6759
6760/**
bb8c093b 6761 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY		 6762 *
6763 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6764 * be set inappropriately and the driver currently sets the hardware up to
6765 * use it whenever needed.
6766 */
bb8c093b 6767static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
b481de9c 6768{
bb8c093b
CH		 6769 struct iwl3945_priv *priv = hw->priv;
6770 const struct iwl3945_channel_info *ch_info;
b481de9c 6771 unsigned long flags;
76bb77e0 6772 int ret = 0;
b481de9c
ZY		 6773
6774 mutex_lock(&priv->mutex);
8318d78a 6775 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6776
12342c47
ZY		 6777 priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
6778
bb8c093b 6779 if (!iwl3945_is_ready(priv)) {
b481de9c 6780 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY		 6781 ret = -EIO;
6782 goto out;
b481de9c
ZY		 6783 }
6784
bb8c093b 6785 if (unlikely(!iwl3945_param_disable_hw_scan &&
b481de9c 6786 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY		 6787 IWL_DEBUG_MAC80211("leave - scanning\n");
6788 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6789 mutex_unlock(&priv->mutex);
a0646470 6790 return 0;
b481de9c
ZY		 6791 }
6792
6793 spin_lock_irqsave(&priv->lock, flags);
6794
8318d78a
JB		 6795 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
6796 conf->channel->hw_value);
b481de9c 6797 if (!is_channel_valid(ch_info)) {
66b5004d 6798 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
8318d78a 6799 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY		 6800 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6801 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY		 6802 ret = -EINVAL;
6803 goto out;
b481de9c
ZY		 6804 }
6805
8318d78a 6806 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 6807
8318d78a 6808 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY		 6809
6810 /* The list of supported rates and rate mask can be different
6811 * for each phymode; since the phymode may have changed, reset
6812 * the rate mask to what mac80211 lists */
bb8c093b 6813 iwl3945_set_rate(priv);
b481de9c
ZY		 6814
6815 spin_unlock_irqrestore(&priv->lock, flags);
6816
6817#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6818 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6819 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 6820 goto out;
b481de9c
ZY		 6821 }
6822#endif
6823
bb8c093b 6824 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 6825
6826 if (!conf->radio_enabled) {
6827 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6828 goto out;
b481de9c
ZY		 6829 }
6830
bb8c093b 6831 if (iwl3945_is_rfkill(priv)) {
b481de9c 6832 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY		 6833 ret = -EIO;
6834 goto out;
b481de9c
ZY		 6835 }
6836
bb8c093b 6837 iwl3945_set_rate(priv);
b481de9c
ZY		 6838
6839 if (memcmp(&priv->active_rxon,
6840 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 6841 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6842 else
6843 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6844
6845 IWL_DEBUG_MAC80211("leave\n");
6846
76bb77e0 6847out:
a0646470 6848 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6849 mutex_unlock(&priv->mutex);
76bb77e0 6850 return ret;
b481de9c
ZY		 6851}
6852
bb8c093b 6853static void iwl3945_config_ap(struct iwl3945_priv *priv)
b481de9c
ZY		 6854{
6855 int rc = 0;
6856
d986bcd1 6857 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 6858 return;
6859
6860 /* The following should be done only at AP bring up */
5d1e2325 6861 if (!(iwl3945_is_associated(priv))) {
b481de9c
ZY		 6862
6863 /* RXON - unassoc (to set timing command) */
6864 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6865 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6866
6867 /* RXON Timing */
bb8c093b
CH		 6868 memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
6869 iwl3945_setup_rxon_timing(priv);
6870 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6871 sizeof(priv->rxon_timing), &priv->rxon_timing);
6872 if (rc)
6873 IWL_WARNING("REPLY_RXON_TIMING failed - "
6874 "Attempting to continue.\n");
6875
6876 /* FIXME: what should be the assoc_id for AP? */
6877 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6878 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6879 priv->staging_rxon.flags |=
6880 RXON_FLG_SHORT_PREAMBLE_MSK;
6881 else
6882 priv->staging_rxon.flags &=
6883 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6884
6885 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6886 if (priv->assoc_capability &
6887 WLAN_CAPABILITY_SHORT_SLOT_TIME)
6888 priv->staging_rxon.flags |=
6889 RXON_FLG_SHORT_SLOT_MSK;
6890 else
6891 priv->staging_rxon.flags &=
6892 ~RXON_FLG_SHORT_SLOT_MSK;
6893
6894 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6895 priv->staging_rxon.flags &=
6896 ~RXON_FLG_SHORT_SLOT_MSK;
6897 }
6898 /* restore RXON assoc */
6899 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b
CH		 6900 iwl3945_commit_rxon(priv);
6901 iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
556f8db7 6902 }
bb8c093b 6903 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6904
6905 /* FIXME - we need to add code here to detect a totally new
6906 * configuration, reset the AP, unassoc, rxon timing, assoc,
6907 * clear sta table, add BCAST sta... */
6908}
6909
32bfd35d
JB		 6910static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6911 struct ieee80211_vif *vif,
b481de9c
ZY		 6912 struct ieee80211_if_conf *conf)
6913{
bb8c093b 6914 struct iwl3945_priv *priv = hw->priv;
0795af57 6915 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6916 unsigned long flags;
6917 int rc;
6918
6919 if (conf == NULL)
6920 return -EIO;
6921
b716bb91
EG		 6922 if (priv->vif != vif) {
6923 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b716bb91
EG		 6924 return 0;
6925 }
6926
4150c572
JB		 6927 /* XXX: this MUST use conf->mac_addr */
6928
b481de9c
ZY		 6929 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
6930 (!conf->beacon || !conf->ssid_len)) {
6931 IWL_DEBUG_MAC80211
6932 ("Leaving in AP mode because HostAPD is not ready.\n");
6933 return 0;
6934 }
6935
5a66926a
ZY		 6936 if (!iwl3945_is_alive(priv))
6937 return -EAGAIN;
6938
b481de9c
ZY		 6939 mutex_lock(&priv->mutex);
6940
b481de9c 6941 if (conf->bssid)
0795af57
JP		 6942 IWL_DEBUG_MAC80211("bssid: %s\n",
6943 print_mac(mac, conf->bssid));
b481de9c 6944
4150c572
JB		 6945/*
6946 * very dubious code was here; the probe filtering flag is never set:
6947 *
b481de9c
ZY		 6948 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6949 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6950 */
b481de9c
ZY		 6951
6952 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6953 if (!conf->bssid) {
6954 conf->bssid = priv->mac_addr;
6955 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
0795af57
JP		 6956 IWL_DEBUG_MAC80211("bssid was set to: %s\n",
6957 print_mac(mac, conf->bssid));
b481de9c
ZY		 6958 }
6959 if (priv->ibss_beacon)
6960 dev_kfree_skb(priv->ibss_beacon);
6961
6962 priv->ibss_beacon = conf->beacon;
6963 }
6964
fde3571f
MA		 6965 if (iwl3945_is_rfkill(priv))
6966 goto done;
6967
b481de9c
ZY		 6968 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6969 !is_multicast_ether_addr(conf->bssid)) {
6970 /* If there is currently a HW scan going on in the background
6971 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6972 if (iwl3945_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 6973 IWL_WARNING("Aborted scan still in progress "
6974 "after 100ms\n");
6975 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6976 mutex_unlock(&priv->mutex);
6977 return -EAGAIN;
6978 }
6979 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
6980
6981 /* TODO: Audit driver for usage of these members and see
6982 * if mac80211 deprecates them (priv->bssid looks like it
6983 * shouldn't be there, but I haven't scanned the IBSS code
6984 * to verify) - jpk */
6985 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6986
6987 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b 6988 iwl3945_config_ap(priv);
b481de9c 6989 else {
bb8c093b 6990 rc = iwl3945_commit_rxon(priv);
b481de9c 6991 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
bb8c093b 6992 iwl3945_add_station(priv,
556f8db7 6993 priv->active_rxon.bssid_addr, 1, 0);
b481de9c
ZY		 6994 }
6995
6996 } else {
bb8c093b 6997 iwl3945_scan_cancel_timeout(priv, 100);
b481de9c 6998 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6999 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7000 }
7001
fde3571f 7002 done:
b481de9c
ZY		 7003 spin_lock_irqsave(&priv->lock, flags);
7004 if (!conf->ssid_len)
7005 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7006 else
7007 memcpy(priv->essid, conf->ssid, conf->ssid_len);
7008
7009 priv->essid_len = conf->ssid_len;
7010 spin_unlock_irqrestore(&priv->lock, flags);
7011
7012 IWL_DEBUG_MAC80211("leave\n");
7013 mutex_unlock(&priv->mutex);
7014
7015 return 0;
7016}
7017
bb8c093b 7018static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 7019 unsigned int changed_flags,
7020 unsigned int *total_flags,
7021 int mc_count, struct dev_addr_list *mc_list)
7022{
5ec03976 7023 struct iwl3945_priv *priv = hw->priv;
25b3f57c
RF		 7024
7025 if (changed_flags & (*total_flags) & FIF_OTHER_BSS) {
7026 IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
7027 IEEE80211_IF_TYPE_MNTR,
7028 changed_flags, *total_flags);
7029 /* queue work 'cuz mac80211 is holding a lock which
7030 * prevents us from issuing (synchronous) f/w cmds */
7031 queue_work(priv->workqueue, &priv->set_monitor);
5ec03976 7032 }
25b3f57c
RF		 7033 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI |
7034 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4150c572
JB		 7035}
7036
bb8c093b 7037static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 7038 struct ieee80211_if_init_conf *conf)
7039{
bb8c093b 7040 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7041
7042 IWL_DEBUG_MAC80211("enter\n");
7043
7044 mutex_lock(&priv->mutex);
6ef89d0a 7045
fde3571f
MA		 7046 if (iwl3945_is_ready_rf(priv)) {
7047 iwl3945_scan_cancel_timeout(priv, 100);
7048 cancel_delayed_work(&priv->post_associate);
7049 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
7050 iwl3945_commit_rxon(priv);
7051 }
32bfd35d
JB		 7052 if (priv->vif == conf->vif) {
7053 priv->vif = NULL;
b481de9c
ZY		 7054 memset(priv->bssid, 0, ETH_ALEN);
7055 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
7056 priv->essid_len = 0;
7057 }
7058 mutex_unlock(&priv->mutex);
7059
7060 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 7061}
7062
bb8c093b 7063static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 7064{
7065 int rc = 0;
7066 unsigned long flags;
bb8c093b 7067 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7068
7069 IWL_DEBUG_MAC80211("enter\n");
7070
15e869d8 7071 mutex_lock(&priv->mutex);
b481de9c
ZY		 7072 spin_lock_irqsave(&priv->lock, flags);
7073
bb8c093b 7074 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7075 rc = -EIO;
7076 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
7077 goto out_unlock;
7078 }
7079
7080 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
7081 rc = -EIO;
7082 IWL_ERROR("ERROR: APs don't scan\n");
7083 goto out_unlock;
7084 }
7085
7878a5a4
MA		 7086 /* we don't schedule scan within next_scan_jiffies period */
7087 if (priv->next_scan_jiffies &&
7088 time_after(priv->next_scan_jiffies, jiffies)) {
7089 rc = -EAGAIN;
7090 goto out_unlock;
7091 }
15dbf1b7
BM		 7092 /* if we just finished scan ask for delay for a broadcast scan */
7093 if ((len == 0) && priv->last_scan_jiffies &&
7094 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
7095 jiffies)) {
b481de9c
ZY		 7096 rc = -EAGAIN;
7097 goto out_unlock;
7098 }
7099 if (len) {
7878a5a4 7100 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
bb8c093b 7101 iwl3945_escape_essid(ssid, len), (int)len);
b481de9c
ZY		 7102
7103 priv->one_direct_scan = 1;
7104 priv->direct_ssid_len = (u8)
7105 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
7106 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA		 7107 } else
7108 priv->one_direct_scan = 0;
b481de9c 7109
bb8c093b 7110 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY		 7111
7112 IWL_DEBUG_MAC80211("leave\n");
7113
7114out_unlock:
7115 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 7116 mutex_unlock(&priv->mutex);
b481de9c
ZY		 7117
7118 return rc;
7119}
7120
bb8c093b 7121static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 7122 const u8 *local_addr, const u8 *addr,
7123 struct ieee80211_key_conf *key)
7124{
bb8c093b 7125 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7126 int rc = 0;
7127 u8 sta_id;
7128
7129 IWL_DEBUG_MAC80211("enter\n");
7130
bb8c093b 7131 if (!iwl3945_param_hwcrypto) {
b481de9c
ZY		 7132 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7133 return -EOPNOTSUPP;
7134 }
7135
7136 if (is_zero_ether_addr(addr))
7137 /* only support pairwise keys */
7138 return -EOPNOTSUPP;
7139
bb8c093b 7140 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 7141 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 7142 DECLARE_MAC_BUF(mac);
7143
7144 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
7145 print_mac(mac, addr));
b481de9c
ZY		 7146 return -EINVAL;
7147 }
7148
7149 mutex_lock(&priv->mutex);
7150
bb8c093b 7151 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7152
b481de9c
ZY		 7153 switch (cmd) {
7154 case SET_KEY:
bb8c093b 7155 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 7156 if (!rc) {
bb8c093b
CH		 7157 iwl3945_set_rxon_hwcrypto(priv, 1);
7158 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7159 key->hw_key_idx = sta_id;
7160 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
7161 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7162 }
7163 break;
7164 case DISABLE_KEY:
bb8c093b 7165 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 7166 if (!rc) {
bb8c093b
CH		 7167 iwl3945_set_rxon_hwcrypto(priv, 0);
7168 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7169 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
7170 }
7171 break;
7172 default:
7173 rc = -EINVAL;
7174 }
7175
7176 IWL_DEBUG_MAC80211("leave\n");
7177 mutex_unlock(&priv->mutex);
7178
7179 return rc;
7180}
7181
e100bb64 7182static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
b481de9c
ZY		 7183 const struct ieee80211_tx_queue_params *params)
7184{
bb8c093b 7185 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7186 unsigned long flags;
7187 int q;
b481de9c
ZY		 7188
7189 IWL_DEBUG_MAC80211("enter\n");
7190
bb8c093b 7191 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7192 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7193 return -EIO;
7194 }
7195
7196 if (queue >= AC_NUM) {
7197 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7198 return 0;
7199 }
7200
b481de9c
ZY		 7201 if (!priv->qos_data.qos_enable) {
7202 priv->qos_data.qos_active = 0;
7203 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7204 return 0;
7205 }
7206 q = AC_NUM - 1 - queue;
7207
7208 spin_lock_irqsave(&priv->lock, flags);
7209
7210 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7211 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7212 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7213 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 7214 cpu_to_le16((params->txop * 32));
b481de9c
ZY		 7215
7216 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7217 priv->qos_data.qos_active = 1;
7218
7219 spin_unlock_irqrestore(&priv->lock, flags);
7220
7221 mutex_lock(&priv->mutex);
7222 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b
CH		 7223 iwl3945_activate_qos(priv, 1);
7224 else if (priv->assoc_id && iwl3945_is_associated(priv))
7225 iwl3945_activate_qos(priv, 0);
b481de9c
ZY		 7226
7227 mutex_unlock(&priv->mutex);
7228
b481de9c
ZY		 7229 IWL_DEBUG_MAC80211("leave\n");
7230 return 0;
7231}
7232
bb8c093b 7233static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7234 struct ieee80211_tx_queue_stats *stats)
7235{
bb8c093b 7236 struct iwl3945_priv *priv = hw->priv;
b481de9c 7237 int i, avail;
bb8c093b
CH		 7238 struct iwl3945_tx_queue *txq;
7239 struct iwl3945_queue *q;
b481de9c
ZY		 7240 unsigned long flags;
7241
7242 IWL_DEBUG_MAC80211("enter\n");
7243
bb8c093b 7244 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7245 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7246 return -EIO;
7247 }
7248
7249 spin_lock_irqsave(&priv->lock, flags);
7250
7251 for (i = 0; i < AC_NUM; i++) {
7252 txq = &priv->txq[i];
7253 q = &txq->q;
bb8c093b 7254 avail = iwl3945_queue_space(q);
b481de9c 7255
57ffc589
JB		 7256 stats[i].len = q->n_window - avail;
7257 stats[i].limit = q->n_window - q->high_mark;
7258 stats[i].count = q->n_window;
b481de9c
ZY		 7259
7260 }
7261 spin_unlock_irqrestore(&priv->lock, flags);
7262
7263 IWL_DEBUG_MAC80211("leave\n");
7264
7265 return 0;
7266}
7267
bb8c093b 7268static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7269 struct ieee80211_low_level_stats *stats)
7270{
7271 IWL_DEBUG_MAC80211("enter\n");
7272 IWL_DEBUG_MAC80211("leave\n");
7273
7274 return 0;
7275}
7276
bb8c093b 7277static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY		 7278{
7279 IWL_DEBUG_MAC80211("enter\n");
7280 IWL_DEBUG_MAC80211("leave\n");
7281
7282 return 0;
7283}
7284
bb8c093b 7285static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7286{
bb8c093b 7287 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7288 unsigned long flags;
7289
7290 mutex_lock(&priv->mutex);
7291 IWL_DEBUG_MAC80211("enter\n");
7292
bb8c093b 7293 iwl3945_reset_qos(priv);
292ae174 7294
b481de9c
ZY		 7295 cancel_delayed_work(&priv->post_associate);
7296
7297 spin_lock_irqsave(&priv->lock, flags);
7298 priv->assoc_id = 0;
7299 priv->assoc_capability = 0;
7300 priv->call_post_assoc_from_beacon = 0;
7301
7302 /* new association get rid of ibss beacon skb */
7303 if (priv->ibss_beacon)
7304 dev_kfree_skb(priv->ibss_beacon);
7305
7306 priv->ibss_beacon = NULL;
7307
7308 priv->beacon_int = priv->hw->conf.beacon_int;
7309 priv->timestamp1 = 0;
7310 priv->timestamp0 = 0;
7311 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
7312 priv->beacon_int = 0;
7313
7314 spin_unlock_irqrestore(&priv->lock, flags);
7315
fde3571f
MA		 7316 if (!iwl3945_is_ready_rf(priv)) {
7317 IWL_DEBUG_MAC80211("leave - not ready\n");
7318 mutex_unlock(&priv->mutex);
7319 return;
7320 }
7321
15e869d8
MA		 7322 /* we are restarting association process
7323 * clear RXON_FILTER_ASSOC_MSK bit
7324 */
7325 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
bb8c093b 7326 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 7327 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7328 iwl3945_commit_rxon(priv);
15e869d8
MA		 7329 }
7330
b481de9c
ZY		 7331 /* Per mac80211.h: This is only used in IBSS mode... */
7332 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
15e869d8 7333
b481de9c
ZY		 7334 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7335 mutex_unlock(&priv->mutex);
7336 return;
b481de9c
ZY		 7337 }
7338
bb8c093b 7339 iwl3945_set_rate(priv);
b481de9c
ZY		 7340
7341 mutex_unlock(&priv->mutex);
7342
7343 IWL_DEBUG_MAC80211("leave\n");
7344
7345}
7346
e039fa4a 7347static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 7348{
bb8c093b 7349 struct iwl3945_priv *priv = hw->priv;
b481de9c
ZY		 7350 unsigned long flags;
7351
7352 mutex_lock(&priv->mutex);
7353 IWL_DEBUG_MAC80211("enter\n");
7354
bb8c093b 7355 if (!iwl3945_is_ready_rf(priv)) {
b481de9c
ZY		 7356 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7357 mutex_unlock(&priv->mutex);
7358 return -EIO;
7359 }
7360
7361 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
7362 IWL_DEBUG_MAC80211("leave - not IBSS\n");
7363 mutex_unlock(&priv->mutex);
7364 return -EIO;
7365 }
7366
7367 spin_lock_irqsave(&priv->lock, flags);
7368
7369 if (priv->ibss_beacon)
7370 dev_kfree_skb(priv->ibss_beacon);
7371
7372 priv->ibss_beacon = skb;
7373
7374 priv->assoc_id = 0;
7375
7376 IWL_DEBUG_MAC80211("leave\n");
7377 spin_unlock_irqrestore(&priv->lock, flags);
7378
bb8c093b 7379 iwl3945_reset_qos(priv);
b481de9c
ZY		 7380
7381 queue_work(priv->workqueue, &priv->post_associate.work);
7382
7383 mutex_unlock(&priv->mutex);
7384
7385 return 0;
7386}
7387
7388/*****************************************************************************
7389 *
7390 * sysfs attributes
7391 *
7392 *****************************************************************************/
7393
c8b0e6e1 7394#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 7395
7396/*
7397 * The following adds a new attribute to the sysfs representation
7398 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7399 * used for controlling the debug level.
7400 *
7401 * See the level definitions in iwl for details.
7402 */
7403
7404static ssize_t show_debug_level(struct device_driver *d, char *buf)
7405{
bb8c093b 7406 return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
b481de9c
ZY		 7407}
7408static ssize_t store_debug_level(struct device_driver *d,
7409 const char *buf, size_t count)
7410{
7411 char *p = (char *)buf;
7412 u32 val;
7413
7414 val = simple_strtoul(p, &p, 0);
7415 if (p == buf)
7416 printk(KERN_INFO DRV_NAME
7417 ": %s is not in hex or decimal form.\n", buf);
7418 else
bb8c093b 7419 iwl3945_debug_level = val;
b481de9c
ZY		 7420
7421 return strnlen(buf, count);
7422}
7423
7424static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7425 show_debug_level, store_debug_level);
7426
c8b0e6e1 7427#endif /* CONFIG_IWL3945_DEBUG */
b481de9c 7428
b481de9c
ZY		 7429static ssize_t show_temperature(struct device *d,
7430 struct device_attribute *attr, char *buf)
7431{
bb8c093b 7432 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c 7433
bb8c093b 7434 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7435 return -EAGAIN;
7436
bb8c093b 7437 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY		 7438}
7439
7440static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7441
7442static ssize_t show_rs_window(struct device *d,
7443 struct device_attribute *attr,
7444 char *buf)
7445{
bb8c093b
CH		 7446 struct iwl3945_priv *priv = d->driver_data;
7447 return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
b481de9c
ZY		 7448}
7449static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
7450
7451static ssize_t show_tx_power(struct device *d,
7452 struct device_attribute *attr, char *buf)
7453{
bb8c093b 7454 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7455 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7456}
7457
7458static ssize_t store_tx_power(struct device *d,
7459 struct device_attribute *attr,
7460 const char *buf, size_t count)
7461{
bb8c093b 7462 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7463 char *p = (char *)buf;
7464 u32 val;
7465
7466 val = simple_strtoul(p, &p, 10);
7467 if (p == buf)
7468 printk(KERN_INFO DRV_NAME
7469 ": %s is not in decimal form.\n", buf);
7470 else
bb8c093b 7471 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 7472
7473 return count;
7474}
7475
7476static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7477
7478static ssize_t show_flags(struct device *d,
7479 struct device_attribute *attr, char *buf)
7480{
bb8c093b 7481 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7482
7483 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7484}
7485
7486static ssize_t store_flags(struct device *d,
7487 struct device_attribute *attr,
7488 const char *buf, size_t count)
7489{
bb8c093b 7490 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7491 u32 flags = simple_strtoul(buf, NULL, 0);
7492
7493 mutex_lock(&priv->mutex);
7494 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7495 /* Cancel any currently running scans... */
bb8c093b 7496 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7497 IWL_WARNING("Could not cancel scan.\n");
7498 else {
7499 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7500 flags);
7501 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7502 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7503 }
7504 }
7505 mutex_unlock(&priv->mutex);
7506
7507 return count;
7508}
7509
7510static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7511
7512static ssize_t show_filter_flags(struct device *d,
7513 struct device_attribute *attr, char *buf)
7514{
bb8c093b 7515 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7516
7517 return sprintf(buf, "0x%04X\n",
7518 le32_to_cpu(priv->active_rxon.filter_flags));
7519}
7520
7521static ssize_t store_filter_flags(struct device *d,
7522 struct device_attribute *attr,
7523 const char *buf, size_t count)
7524{
bb8c093b 7525 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
b481de9c
ZY		 7526 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7527
7528 mutex_lock(&priv->mutex);
7529 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7530 /* Cancel any currently running scans... */
bb8c093b 7531 if (iwl3945_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7532 IWL_WARNING("Could not cancel scan.\n");
7533 else {
7534 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7535 "0x%04X\n", filter_flags);
7536 priv->staging_rxon.filter_flags =
7537 cpu_to_le32(filter_flags);
bb8c093b 7538 iwl3945_commit_rxon(priv);
b481de9c
ZY		 7539 }
7540 }
7541 mutex_unlock(&priv->mutex);
7542
7543 return count;
7544}
7545
7546static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7547 store_filter_flags);
7548
c8b0e6e1 7549#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7550
7551static ssize_t show_measurement(struct device *d,
7552 struct device_attribute *attr, char *buf)
7553{
bb8c093b
CH		 7554 struct iwl3945_priv *priv = dev_get_drvdata(d);
7555 struct iwl3945_spectrum_notification measure_report;
b481de9c
ZY		 7556 u32 size = sizeof(measure_report), len = 0, ofs = 0;
7557 u8 *data = (u8 *) & measure_report;
7558 unsigned long flags;
7559
7560 spin_lock_irqsave(&priv->lock, flags);
7561 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7562 spin_unlock_irqrestore(&priv->lock, flags);
7563 return 0;
7564 }
7565 memcpy(&measure_report, &priv->measure_report, size);
7566 priv->measurement_status = 0;
7567 spin_unlock_irqrestore(&priv->lock, flags);
7568
7569 while (size && (PAGE_SIZE - len)) {
7570 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7571 PAGE_SIZE - len, 1);
7572 len = strlen(buf);
7573 if (PAGE_SIZE - len)
7574 buf[len++] = '\n';
7575
7576 ofs += 16;
7577 size -= min(size, 16U);
7578 }
7579
7580 return len;
7581}
7582
7583static ssize_t store_measurement(struct device *d,
7584 struct device_attribute *attr,
7585 const char *buf, size_t count)
7586{
bb8c093b 7587 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7588 struct ieee80211_measurement_params params = {
7589 .channel = le16_to_cpu(priv->active_rxon.channel),
7590 .start_time = cpu_to_le64(priv->last_tsf),
7591 .duration = cpu_to_le16(1),
7592 };
7593 u8 type = IWL_MEASURE_BASIC;
7594 u8 buffer[32];
7595 u8 channel;
7596
7597 if (count) {
7598 char *p = buffer;
7599 strncpy(buffer, buf, min(sizeof(buffer), count));
7600 channel = simple_strtoul(p, NULL, 0);
7601 if (channel)
7602 params.channel = channel;
7603
7604 p = buffer;
7605 while (*p && *p != ' ')
7606 p++;
7607 if (*p)
7608 type = simple_strtoul(p + 1, NULL, 0);
7609 }
7610
7611 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7612 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7613 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY		 7614
7615 return count;
7616}
7617
7618static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7619 show_measurement, store_measurement);
c8b0e6e1 7620#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 7621
b481de9c
ZY		 7622static ssize_t store_retry_rate(struct device *d,
7623 struct device_attribute *attr,
7624 const char *buf, size_t count)
7625{
bb8c093b 7626 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7627
7628 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7629 if (priv->retry_rate <= 0)
7630 priv->retry_rate = 1;
7631
7632 return count;
7633}
7634
7635static ssize_t show_retry_rate(struct device *d,
7636 struct device_attribute *attr, char *buf)
7637{
bb8c093b 7638 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7639 return sprintf(buf, "%d", priv->retry_rate);
7640}
7641
7642static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7643 store_retry_rate);
7644
7645static ssize_t store_power_level(struct device *d,
7646 struct device_attribute *attr,
7647 const char *buf, size_t count)
7648{
bb8c093b 7649 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7650 int rc;
7651 int mode;
7652
7653 mode = simple_strtoul(buf, NULL, 0);
7654 mutex_lock(&priv->mutex);
7655
bb8c093b 7656 if (!iwl3945_is_ready(priv)) {
b481de9c
ZY		 7657 rc = -EAGAIN;
7658 goto out;
7659 }
7660
7661 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
7662 mode = IWL_POWER_AC;
7663 else
7664 mode |= IWL_POWER_ENABLED;
7665
7666 if (mode != priv->power_mode) {
bb8c093b 7667 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 7668 if (rc) {
7669 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7670 goto out;
7671 }
7672 priv->power_mode = mode;
7673 }
7674
7675 rc = count;
7676
7677 out:
7678 mutex_unlock(&priv->mutex);
7679 return rc;
7680}
7681
7682#define MAX_WX_STRING 80
7683
7684/* Values are in microsecond */
7685static const s32 timeout_duration[] = {
7686 350000,
7687 250000,
7688 75000,
7689 37000,
7690 25000,
7691};
7692static const s32 period_duration[] = {
7693 400000,
7694 700000,
7695 1000000,
7696 1000000,
7697 1000000
7698};
7699
7700static ssize_t show_power_level(struct device *d,
7701 struct device_attribute *attr, char *buf)
7702{
bb8c093b 7703 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7704 int level = IWL_POWER_LEVEL(priv->power_mode);
7705 char *p = buf;
7706
7707 p += sprintf(p, "%d ", level);
7708 switch (level) {
7709 case IWL_POWER_MODE_CAM:
7710 case IWL_POWER_AC:
7711 p += sprintf(p, "(AC)");
7712 break;
7713 case IWL_POWER_BATTERY:
7714 p += sprintf(p, "(BATTERY)");
7715 break;
7716 default:
7717 p += sprintf(p,
7718 "(Timeout %dms, Period %dms)",
7719 timeout_duration[level - 1] / 1000,
7720 period_duration[level - 1] / 1000);
7721 }
7722
7723 if (!(priv->power_mode & IWL_POWER_ENABLED))
7724 p += sprintf(p, " OFF\n");
7725 else
7726 p += sprintf(p, " \n");
7727
7728 return (p - buf + 1);
7729
7730}
7731
7732static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7733 store_power_level);
7734
7735static ssize_t show_channels(struct device *d,
7736 struct device_attribute *attr, char *buf)
7737{
8318d78a
JB		 7738 /* all this shit doesn't belong into sysfs anyway */
7739 return 0;
b481de9c
ZY		 7740}
7741
7742static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7743
7744static ssize_t show_statistics(struct device *d,
7745 struct device_attribute *attr, char *buf)
7746{
bb8c093b
CH		 7747 struct iwl3945_priv *priv = dev_get_drvdata(d);
7748 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c
ZY		 7749 u32 len = 0, ofs = 0;
7750 u8 *data = (u8 *) & priv->statistics;
7751 int rc = 0;
7752
bb8c093b 7753 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7754 return -EAGAIN;
7755
7756 mutex_lock(&priv->mutex);
bb8c093b 7757 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY		 7758 mutex_unlock(&priv->mutex);
7759
7760 if (rc) {
7761 len = sprintf(buf,
7762 "Error sending statistics request: 0x%08X\n", rc);
7763 return len;
7764 }
7765
7766 while (size && (PAGE_SIZE - len)) {
7767 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7768 PAGE_SIZE - len, 1);
7769 len = strlen(buf);
7770 if (PAGE_SIZE - len)
7771 buf[len++] = '\n';
7772
7773 ofs += 16;
7774 size -= min(size, 16U);
7775 }
7776
7777 return len;
7778}
7779
7780static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7781
7782static ssize_t show_antenna(struct device *d,
7783 struct device_attribute *attr, char *buf)
7784{
bb8c093b 7785 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c 7786
bb8c093b 7787 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7788 return -EAGAIN;
7789
7790 return sprintf(buf, "%d\n", priv->antenna);
7791}
7792
7793static ssize_t store_antenna(struct device *d,
7794 struct device_attribute *attr,
7795 const char *buf, size_t count)
7796{
7797 int ant;
bb8c093b 7798 struct iwl3945_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7799
7800 if (count == 0)
7801 return 0;
7802
7803 if (sscanf(buf, "%1i", &ant) != 1) {
7804 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7805 return count;
7806 }
7807
7808 if ((ant >= 0) && (ant <= 2)) {
7809 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7810 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY		 7811 } else
7812 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7813
7814
7815 return count;
7816}
7817
7818static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7819
7820static ssize_t show_status(struct device *d,
7821 struct device_attribute *attr, char *buf)
7822{
bb8c093b
CH		 7823 struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
7824 if (!iwl3945_is_alive(priv))
b481de9c
ZY		 7825 return -EAGAIN;
7826 return sprintf(buf, "0x%08x\n", (int)priv->status);
7827}
7828
7829static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7830
7831static ssize_t dump_error_log(struct device *d,
7832 struct device_attribute *attr,
7833 const char *buf, size_t count)
7834{
7835 char *p = (char *)buf;
7836
7837 if (p[0] == '1')
bb8c093b 7838 iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7839
7840 return strnlen(buf, count);
7841}
7842
7843static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7844
7845static ssize_t dump_event_log(struct device *d,
7846 struct device_attribute *attr,
7847 const char *buf, size_t count)
7848{
7849 char *p = (char *)buf;
7850
7851 if (p[0] == '1')
bb8c093b 7852 iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
b481de9c
ZY		 7853
7854 return strnlen(buf, count);
7855}
7856
7857static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7858
7859/*****************************************************************************
7860 *
7861 * driver setup and teardown
7862 *
7863 *****************************************************************************/
7864
bb8c093b 7865static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 7866{
7867 priv->workqueue = create_workqueue(DRV_NAME);
7868
7869 init_waitqueue_head(&priv->wait_command_queue);
7870
bb8c093b
CH		 7871 INIT_WORK(&priv->up, iwl3945_bg_up);
7872 INIT_WORK(&priv->restart, iwl3945_bg_restart);
7873 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
7874 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
7875 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
7876 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7877 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7878 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
5ec03976 7879 INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor);
bb8c093b
CH		 7880 INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
7881 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7882 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
7883 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
7884
7885 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY		 7886
7887 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7888 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 7889}
7890
bb8c093b 7891static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c 7892{
bb8c093b 7893 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 7894
e47eb6ad 7895 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 7896 cancel_delayed_work(&priv->scan_check);
7897 cancel_delayed_work(&priv->alive_start);
7898 cancel_delayed_work(&priv->post_associate);
7899 cancel_work_sync(&priv->beacon_update);
7900}
7901
bb8c093b 7902static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY		 7903 &dev_attr_antenna.attr,
7904 &dev_attr_channels.attr,
7905 &dev_attr_dump_errors.attr,
7906 &dev_attr_dump_events.attr,
7907 &dev_attr_flags.attr,
7908 &dev_attr_filter_flags.attr,
c8b0e6e1 7909#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7910 &dev_attr_measurement.attr,
7911#endif
7912 &dev_attr_power_level.attr,
b481de9c 7913 &dev_attr_retry_rate.attr,
b481de9c
ZY		 7914 &dev_attr_rs_window.attr,
7915 &dev_attr_statistics.attr,
7916 &dev_attr_status.attr,
7917 &dev_attr_temperature.attr,
b481de9c
ZY		 7918 &dev_attr_tx_power.attr,
7919
7920 NULL
7921};
7922
bb8c093b 7923static struct attribute_group iwl3945_attribute_group = {
b481de9c 7924 .name = NULL, /* put in device directory */
bb8c093b 7925 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY		 7926};
7927
bb8c093b
CH		 7928static struct ieee80211_ops iwl3945_hw_ops = {
7929 .tx = iwl3945_mac_tx,
7930 .start = iwl3945_mac_start,
7931 .stop = iwl3945_mac_stop,
7932 .add_interface = iwl3945_mac_add_interface,
7933 .remove_interface = iwl3945_mac_remove_interface,
7934 .config = iwl3945_mac_config,
7935 .config_interface = iwl3945_mac_config_interface,
7936 .configure_filter = iwl3945_configure_filter,
7937 .set_key = iwl3945_mac_set_key,
7938 .get_stats = iwl3945_mac_get_stats,
7939 .get_tx_stats = iwl3945_mac_get_tx_stats,
7940 .conf_tx = iwl3945_mac_conf_tx,
7941 .get_tsf = iwl3945_mac_get_tsf,
7942 .reset_tsf = iwl3945_mac_reset_tsf,
7943 .beacon_update = iwl3945_mac_beacon_update,
7944 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY		 7945};
7946
bb8c093b 7947static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 7948{
7949 int err = 0;
bb8c093b 7950 struct iwl3945_priv *priv;
b481de9c 7951 struct ieee80211_hw *hw;
82b9a121 7952 struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
b481de9c 7953 int i;
0359facc 7954 unsigned long flags;
5a66926a 7955 DECLARE_MAC_BUF(mac);
b481de9c 7956
6440adb5
CB		 7957 /* Disabling hardware scan means that mac80211 will perform scans
7958 * "the hard way", rather than using device's scan. */
bb8c093b 7959 if (iwl3945_param_disable_hw_scan) {
b481de9c 7960 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 7961 iwl3945_hw_ops.hw_scan = NULL;
b481de9c
ZY		 7962 }
7963
dfe7d458 7964 if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
bb8c093b 7965 (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
b481de9c 7966 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
dfe7d458 7967 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
b481de9c
ZY		 7968 err = -EINVAL;
7969 goto out;
7970 }
7971
7972 /* mac80211 allocates memory for this device instance, including
7973 * space for this driver's private structure */
bb8c093b 7974 hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
b481de9c
ZY		 7975 if (hw == NULL) {
7976 IWL_ERROR("Can not allocate network device\n");
7977 err = -ENOMEM;
7978 goto out;
7979 }
7980 SET_IEEE80211_DEV(hw, &pdev->dev);
7981
f51359a8
JB		 7982 hw->rate_control_algorithm = "iwl-3945-rs";
7983
b481de9c
ZY		 7984 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
7985 priv = hw->priv;
7986 priv->hw = hw;
7987
7988 priv->pci_dev = pdev;
82b9a121 7989 priv->cfg = cfg;
6440adb5
CB		 7990
7991 /* Select antenna (may be helpful if only one antenna is connected) */
bb8c093b 7992 priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
c8b0e6e1 7993#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 7994 iwl3945_debug_level = iwl3945_param_debug;
b481de9c
ZY		 7995 atomic_set(&priv->restrict_refcnt, 0);
7996#endif
7997 priv->retry_rate = 1;
7998
7999 priv->ibss_beacon = NULL;
8000
566bfe5a
BR		 8001 /* Tell mac80211 our characteristics */
8002 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
8003 IEEE80211_HW_SIGNAL_DBM |
8004 IEEE80211_HW_NOISE_DBM;
b481de9c 8005
6440adb5 8006 /* 4 EDCA QOS priorities */
b481de9c
ZY		 8007 hw->queues = 4;
8008
8009 spin_lock_init(&priv->lock);
8010 spin_lock_init(&priv->power_data.lock);
8011 spin_lock_init(&priv->sta_lock);
8012 spin_lock_init(&priv->hcmd_lock);
8013
8014 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
8015 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
8016
8017 INIT_LIST_HEAD(&priv->free_frames);
8018
8019 mutex_init(&priv->mutex);
8020 if (pci_enable_device(pdev)) {
8021 err = -ENODEV;
8022 goto out_ieee80211_free_hw;
8023 }
8024
8025 pci_set_master(pdev);
8026
6440adb5 8027 /* Clear the driver's (not device's) station table */
bb8c093b 8028 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 8029
8030 priv->data_retry_limit = -1;
8031 priv->ieee_channels = NULL;
8032 priv->ieee_rates = NULL;
8318d78a 8033 priv->band = IEEE80211_BAND_2GHZ;
b481de9c
ZY		 8034
8035 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8036 if (!err)
8037 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
8038 if (err) {
8039 printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
8040 goto out_pci_disable_device;
8041 }
8042
8043 pci_set_drvdata(pdev, priv);
8044 err = pci_request_regions(pdev, DRV_NAME);
8045 if (err)
8046 goto out_pci_disable_device;
6440adb5 8047
b481de9c
ZY		 8048 /* We disable the RETRY_TIMEOUT register (0x41) to keep
8049 * PCI Tx retries from interfering with C3 CPU state */
8050 pci_write_config_byte(pdev, 0x41, 0x00);
6440adb5 8051
b481de9c
ZY		 8052 priv->hw_base = pci_iomap(pdev, 0, 0);
8053 if (!priv->hw_base) {
8054 err = -ENODEV;
8055 goto out_pci_release_regions;
8056 }
8057
8058 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
8059 (unsigned long long) pci_resource_len(pdev, 0));
8060 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
8061
8062 /* Initialize module parameter values here */
8063
6440adb5 8064 /* Disable radio (SW RF KILL) via parameter when loading driver */
bb8c093b 8065 if (iwl3945_param_disable) {
b481de9c
ZY		 8066 set_bit(STATUS_RF_KILL_SW, &priv->status);
8067 IWL_DEBUG_INFO("Radio disabled.\n");
8068 }
8069
8070 priv->iw_mode = IEEE80211_IF_TYPE_STA;
8071
b481de9c 8072 printk(KERN_INFO DRV_NAME
82b9a121 8073 ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
b481de9c
ZY		 8074
8075 /* Device-specific setup */
bb8c093b 8076 if (iwl3945_hw_set_hw_setting(priv)) {
b481de9c 8077 IWL_ERROR("failed to set hw settings\n");
b481de9c
ZY		 8078 goto out_iounmap;
8079 }
8080
bb8c093b 8081 if (iwl3945_param_qos_enable)
b481de9c
ZY		 8082 priv->qos_data.qos_enable = 1;
8083
bb8c093b 8084 iwl3945_reset_qos(priv);
b481de9c
ZY		 8085
8086 priv->qos_data.qos_active = 0;
8087 priv->qos_data.qos_cap.val = 0;
b481de9c 8088
8318d78a 8089 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
bb8c093b
CH		 8090 iwl3945_setup_deferred_work(priv);
8091 iwl3945_setup_rx_handlers(priv);
b481de9c
ZY		 8092
8093 priv->rates_mask = IWL_RATES_MASK;
8094 /* If power management is turned on, default to AC mode */
8095 priv->power_mode = IWL_POWER_AC;
8096 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
8097
0359facc 8098 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 8099 iwl3945_disable_interrupts(priv);
0359facc 8100 spin_unlock_irqrestore(&priv->lock, flags);
49df2b33 8101
bb8c093b 8102 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8103 if (err) {
8104 IWL_ERROR("failed to create sysfs device attributes\n");
b481de9c
ZY		 8105 goto out_release_irq;
8106 }
8107
5a66926a
ZY		 8108 /* nic init */
8109 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
8110 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
8111
8112 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
8113 err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
8114 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
8115 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
8116 if (err < 0) {
8117 IWL_DEBUG_INFO("Failed to init the card\n");
8118 goto out_remove_sysfs;
8119 }
8120 /* Read the EEPROM */
8121 err = iwl3945_eeprom_init(priv);
b481de9c 8122 if (err) {
5a66926a
ZY		 8123 IWL_ERROR("Unable to init EEPROM\n");
8124 goto out_remove_sysfs;
b481de9c 8125 }
5a66926a
ZY		 8126 /* MAC Address location in EEPROM same for 3945/4965 */
8127 get_eeprom_mac(priv, priv->mac_addr);
8128 IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
8129 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 8130
849e0dce
RC		 8131 err = iwl3945_init_channel_map(priv);
8132 if (err) {
8133 IWL_ERROR("initializing regulatory failed: %d\n", err);
8134 goto out_remove_sysfs;
8135 }
8136
8137 err = iwl3945_init_geos(priv);
8138 if (err) {
8139 IWL_ERROR("initializing geos failed: %d\n", err);
8140 goto out_free_channel_map;
8141 }
849e0dce 8142
5a66926a
ZY		 8143 err = ieee80211_register_hw(priv->hw);
8144 if (err) {
8145 IWL_ERROR("Failed to register network device (error %d)\n", err);
849e0dce 8146 goto out_free_geos;
5a66926a 8147 }
b481de9c 8148
5a66926a
ZY		 8149 priv->hw->conf.beacon_int = 100;
8150 priv->mac80211_registered = 1;
8151 pci_save_state(pdev);
8152 pci_disable_device(pdev);
b481de9c 8153
ebef2008
AK		 8154 err = iwl3945_rfkill_init(priv);
8155 if (err)
8156 IWL_ERROR("Unable to initialize RFKILL system. "
8157 "Ignoring error: %d\n", err);
8158
b481de9c
ZY		 8159 return 0;
8160
849e0dce
RC		 8161 out_free_geos:
8162 iwl3945_free_geos(priv);
8163 out_free_channel_map:
8164 iwl3945_free_channel_map(priv);
5a66926a 8165 out_remove_sysfs:
bb8c093b 8166 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c
ZY		 8167
8168 out_release_irq:
b481de9c
ZY		 8169 destroy_workqueue(priv->workqueue);
8170 priv->workqueue = NULL;
bb8c093b 8171 iwl3945_unset_hw_setting(priv);
b481de9c
ZY		 8172
8173 out_iounmap:
8174 pci_iounmap(pdev, priv->hw_base);
8175 out_pci_release_regions:
8176 pci_release_regions(pdev);
8177 out_pci_disable_device:
8178 pci_disable_device(pdev);
8179 pci_set_drvdata(pdev, NULL);
8180 out_ieee80211_free_hw:
8181 ieee80211_free_hw(priv->hw);
8182 out:
8183 return err;
8184}
8185
c83dbf68 8186static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 8187{
bb8c093b 8188 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c
ZY		 8189 struct list_head *p, *q;
8190 int i;
0359facc 8191 unsigned long flags;
b481de9c
ZY		 8192
8193 if (!priv)
8194 return;
8195
8196 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8197
b481de9c 8198 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8199
bb8c093b 8200 iwl3945_down(priv);
b481de9c 8201
0359facc
MA		 8202 /* make sure we flush any pending irq or
8203 * tasklet for the driver
8204 */
8205 spin_lock_irqsave(&priv->lock, flags);
8206 iwl3945_disable_interrupts(priv);
8207 spin_unlock_irqrestore(&priv->lock, flags);
8208
8209 iwl_synchronize_irq(priv);
8210
b481de9c
ZY		 8211 /* Free MAC hash list for ADHOC */
8212 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
8213 list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
8214 list_del(p);
bb8c093b 8215 kfree(list_entry(p, struct iwl3945_ibss_seq, list));
b481de9c
ZY		 8216 }
8217 }
8218
bb8c093b 8219 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 8220
ebef2008 8221 iwl3945_rfkill_unregister(priv);
bb8c093b 8222 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 8223
8224 if (priv->rxq.bd)
bb8c093b
CH		 8225 iwl3945_rx_queue_free(priv, &priv->rxq);
8226 iwl3945_hw_txq_ctx_free(priv);
b481de9c 8227
bb8c093b
CH		 8228 iwl3945_unset_hw_setting(priv);
8229 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 8230
8231 if (priv->mac80211_registered) {
8232 ieee80211_unregister_hw(priv->hw);
b481de9c
ZY		 8233 }
8234
6ef89d0a
MA		 8235 /*netif_stop_queue(dev); */
8236 flush_workqueue(priv->workqueue);
8237
bb8c093b 8238 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY		 8239 * priv->workqueue... so we can't take down the workqueue
8240 * until now... */
8241 destroy_workqueue(priv->workqueue);
8242 priv->workqueue = NULL;
8243
b481de9c
ZY		 8244 pci_iounmap(pdev, priv->hw_base);
8245 pci_release_regions(pdev);
8246 pci_disable_device(pdev);
8247 pci_set_drvdata(pdev, NULL);
8248
849e0dce
RC		 8249 iwl3945_free_channel_map(priv);
8250 iwl3945_free_geos(priv);
261415f7 8251 kfree(priv->scan);
b481de9c
ZY		 8252 if (priv->ibss_beacon)
8253 dev_kfree_skb(priv->ibss_beacon);
8254
8255 ieee80211_free_hw(priv->hw);
8256}
8257
8258#ifdef CONFIG_PM
8259
bb8c093b 8260static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8261{
bb8c093b 8262 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8263
e655b9f0
ZY		 8264 if (priv->is_open) {
8265 set_bit(STATUS_IN_SUSPEND, &priv->status);
8266 iwl3945_mac_stop(priv->hw);
8267 priv->is_open = 1;
8268 }
b481de9c 8269
b481de9c
ZY		 8270 pci_set_power_state(pdev, PCI_D3hot);
8271
b481de9c
ZY		 8272 return 0;
8273}
8274
bb8c093b 8275static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 8276{
bb8c093b 8277 struct iwl3945_priv *priv = pci_get_drvdata(pdev);
b481de9c 8278
b481de9c 8279 pci_set_power_state(pdev, PCI_D0);
b481de9c 8280
e655b9f0
ZY		 8281 if (priv->is_open)
8282 iwl3945_mac_start(priv->hw);
b481de9c 8283
e655b9f0 8284 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 8285 return 0;
8286}
8287
8288#endif /* CONFIG_PM */
8289
ebef2008 8290/*************** RFKILL FUNCTIONS **********/
80fcc9e2 8291#ifdef CONFIG_IWL3945_RFKILL
ebef2008
AK		 8292/* software rf-kill from user */
8293static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
8294{
8295 struct iwl3945_priv *priv = data;
8296 int err = 0;
8297
80fcc9e2 8298 if (!priv->rfkill)
ebef2008
AK		 8299 return 0;
8300
8301 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
8302 return 0;
8303
8304 IWL_DEBUG_RF_KILL("we recieved soft RFKILL set to state %d\n", state);
8305 mutex_lock(&priv->mutex);
8306
8307 switch (state) {
acdfe9b4 8308 case RFKILL_STATE_UNBLOCKED:
80fcc9e2 8309 if (iwl3945_is_rfkill_hw(priv)) {
ebef2008 8310 err = -EBUSY;
80fcc9e2
AG		 8311 goto out_unlock;
8312 }
8313 iwl3945_radio_kill_sw(priv, 0);
ebef2008 8314 break;
acdfe9b4 8315 case RFKILL_STATE_SOFT_BLOCKED:
ebef2008 8316 iwl3945_radio_kill_sw(priv, 1);
ebef2008 8317 break;
acdfe9b4
ZY		 8318 default:
8319 IWL_WARNING("we recieved unexpected RFKILL state %d\n", state);
8320 break;
ebef2008 8321 }
80fcc9e2 8322out_unlock:
ebef2008
AK		 8323 mutex_unlock(&priv->mutex);
8324
8325 return err;
8326}
8327
8328int iwl3945_rfkill_init(struct iwl3945_priv *priv)
8329{
8330 struct device *device = wiphy_dev(priv->hw->wiphy);
8331 int ret = 0;
8332
8333 BUG_ON(device == NULL);
8334
8335 IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
80fcc9e2
AG		 8336 priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
8337 if (!priv->rfkill) {
ebef2008
AK		 8338 IWL_ERROR("Unable to allocate rfkill device.\n");
8339 ret = -ENOMEM;
8340 goto error;
8341 }
8342
80fcc9e2
AG		 8343 priv->rfkill->name = priv->cfg->name;
8344 priv->rfkill->data = priv;
8345 priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
8346 priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
8347 priv->rfkill->user_claim_unsupported = 1;
ebef2008 8348
80fcc9e2
AG		 8349 priv->rfkill->dev.class->suspend = NULL;
8350 priv->rfkill->dev.class->resume = NULL;
ebef2008 8351
80fcc9e2 8352 ret = rfkill_register(priv->rfkill);
ebef2008
AK		 8353 if (ret) {
8354 IWL_ERROR("Unable to register rfkill: %d\n", ret);
80fcc9e2 8355 goto freed_rfkill;
ebef2008
AK		 8356 }
8357
8358 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8359 return ret;
8360
ebef2008 8361freed_rfkill:
80fcc9e2
AG		 8362 if (priv->rfkill != NULL)
8363 rfkill_free(priv->rfkill);
8364 priv->rfkill = NULL;
ebef2008
AK		 8365
8366error:
8367 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
8368 return ret;
8369}
8370
8371void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
8372{
80fcc9e2
AG		 8373 if (priv->rfkill)
8374 rfkill_unregister(priv->rfkill);
ebef2008 8375
80fcc9e2 8376 priv->rfkill = NULL;
ebef2008
AK		 8377}
8378
8379/* set rf-kill to the right state. */
8380void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
8381{
8382
80fcc9e2
AG		 8383 if (!priv->rfkill)
8384 return;
8385
8386 if (iwl3945_is_rfkill_hw(priv)) {
8387 rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
ebef2008 8388 return;
80fcc9e2 8389 }
ebef2008 8390
80fcc9e2
AG		 8391 if (!iwl3945_is_rfkill_sw(priv))
8392 rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
ebef2008 8393 else
80fcc9e2 8394 rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
ebef2008
AK		 8395}
8396#endif
8397
b481de9c
ZY		 8398/*****************************************************************************
8399 *
8400 * driver and module entry point
8401 *
8402 *****************************************************************************/
8403
bb8c093b 8404static struct pci_driver iwl3945_driver = {
b481de9c 8405 .name = DRV_NAME,
bb8c093b
CH		 8406 .id_table = iwl3945_hw_card_ids,
8407 .probe = iwl3945_pci_probe,
8408 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 8409#ifdef CONFIG_PM
bb8c093b
CH		 8410 .suspend = iwl3945_pci_suspend,
8411 .resume = iwl3945_pci_resume,
b481de9c
ZY		 8412#endif
8413};
8414
bb8c093b 8415static int __init iwl3945_init(void)
b481de9c
ZY		 8416{
8417
8418 int ret;
8419 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8420 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC		 8421
8422 ret = iwl3945_rate_control_register();
8423 if (ret) {
8424 IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
8425 return ret;
8426 }
8427
bb8c093b 8428 ret = pci_register_driver(&iwl3945_driver);
b481de9c
ZY		 8429 if (ret) {
8430 IWL_ERROR("Unable to initialize PCI module\n");
897e1cf2 8431 goto error_register;
b481de9c 8432 }
c8b0e6e1 8433#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8434 ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c
ZY		 8435 if (ret) {
8436 IWL_ERROR("Unable to create driver sysfs file\n");
897e1cf2 8437 goto error_debug;
b481de9c
ZY		 8438 }
8439#endif
8440
8441 return ret;
897e1cf2
RC		 8442
8443#ifdef CONFIG_IWL3945_DEBUG
8444error_debug:
8445 pci_unregister_driver(&iwl3945_driver);
8446#endif
8447error_register:
8448 iwl3945_rate_control_unregister();
8449 return ret;
b481de9c
ZY		 8450}
8451
bb8c093b 8452static void __exit iwl3945_exit(void)
b481de9c 8453{
c8b0e6e1 8454#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 8455 driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
b481de9c 8456#endif
bb8c093b 8457 pci_unregister_driver(&iwl3945_driver);
897e1cf2 8458 iwl3945_rate_control_unregister();
b481de9c
ZY		 8459}
8460
bb8c093b 8461module_param_named(antenna, iwl3945_param_antenna, int, 0444);
b481de9c 8462MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
bb8c093b 8463module_param_named(disable, iwl3945_param_disable, int, 0444);
b481de9c 8464MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
bb8c093b 8465module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
b481de9c
ZY		 8466MODULE_PARM_DESC(hwcrypto,
8467 "using hardware crypto engine (default 0 [software])\n");
bb8c093b 8468module_param_named(debug, iwl3945_param_debug, int, 0444);
b481de9c 8469MODULE_PARM_DESC(debug, "debug output mask");
bb8c093b 8470module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
b481de9c
ZY		 8471MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
8472
bb8c093b 8473module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
b481de9c
ZY		 8474MODULE_PARM_DESC(queues_num, "number of hw queues.");
8475
8476/* QoS */
bb8c093b 8477module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
b481de9c
ZY		 8478MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
8479
bb8c093b
CH		 8480module_exit(iwl3945_exit);
8481module_init(iwl3945_init);
Linux kernel - Deliverables
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