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mac80211: make wake/stop_queue_by_reason() functions static
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
ZY		 32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
b481de9c
ZY		 40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
43#include <net/ieee80211_radiotap.h>
7e272fcf 44#include <net/lib80211.h>
b481de9c
ZY		 45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
a3139c59
SO		 49#define DRV_NAME "iwl3945"
50
dbb6654c
WT		 51#include "iwl-fh.h"
52#include "iwl-3945-fh.h"
600c0e11 53#include "iwl-commands.h"
b481de9c
ZY		 54#include "iwl-3945.h"
55#include "iwl-helpers.h"
5747d47f 56#include "iwl-core.h"
d20b3c65 57#include "iwl-dev.h"
b481de9c 58
4a8a4322 59static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
188cf6c7 60 struct iwl_tx_queue *txq);
416e1438 61
b481de9c
ZY		 62/*
63 * module name, copyright, version, etc.
b481de9c
ZY		 64 */
65
66#define DRV_DESCRIPTION \
67"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
68
c8b0e6e1 69#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 70#define VD "d"
71#else
72#define VD
73#endif
74
c8b0e6e1 75#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 76#define VS "s"
77#else
78#define VS
79#endif
80
eaa686c3 81#define IWL39_VERSION "1.2.26k" VD VS
eb7ae89c 82#define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
a7b75207 83#define DRV_AUTHOR "<ilw@linux.intel.com>"
eaa686c3 84#define DRV_VERSION IWL39_VERSION
b481de9c 85
b481de9c
ZY		 86
87MODULE_DESCRIPTION(DRV_DESCRIPTION);
88MODULE_VERSION(DRV_VERSION);
a7b75207 89MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c
ZY		 90MODULE_LICENSE("GPL");
91
df878d8f
KA		 92 /* module parameters */
93struct iwl_mod_params iwl3945_mod_params = {
94 .num_of_queues = IWL39_MAX_NUM_QUEUES,
95 /* the rest are 0 by default */
96};
97
b481de9c
ZY		 98/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
99 * DMA services
100 *
101 * Theory of operation
102 *
6440adb5
CB		 103 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
104 * of buffer descriptors, each of which points to one or more data buffers for
105 * the device to read from or fill. Driver and device exchange status of each
106 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
107 * entries in each circular buffer, to protect against confusing empty and full
108 * queue states.
109 *
110 * The device reads or writes the data in the queues via the device's several
111 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 112 *
113 * For Tx queue, there are low mark and high mark limits. If, after queuing
114 * the packet for Tx, free space become < low mark, Tx queue stopped. When
115 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
116 * Tx queue resumed.
117 *
6440adb5
CB		 118 * The 3945 operates with six queues: One receive queue, one transmit queue
119 * (#4) for sending commands to the device firmware, and four transmit queues
120 * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
b481de9c
ZY		 121 ***************************************************/
122
d20b3c65 123int iwl3945_x2_queue_used(const struct iwl_queue *q, int i)
b481de9c 124{
fc4b6853
TW		 125 return q->write_ptr > q->read_ptr ?
126 (i >= q->read_ptr && i < q->write_ptr) :
127 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 128}
129
6440adb5
CB		 130/**
131 * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
132 */
4a8a4322 133static int iwl3945_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
b481de9c
ZY		 134 int count, int slots_num, u32 id)
135{
136 q->n_bd = count;
137 q->n_window = slots_num;
138 q->id = id;
139
c54b679d
TW		 140 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
141 * and iwl_queue_dec_wrap are broken. */
b481de9c
ZY		 142 BUG_ON(!is_power_of_2(count));
143
144 /* slots_num must be power-of-two size, otherwise
145 * get_cmd_index is broken. */
146 BUG_ON(!is_power_of_2(slots_num));
147
148 q->low_mark = q->n_window / 4;
149 if (q->low_mark < 4)
150 q->low_mark = 4;
151
152 q->high_mark = q->n_window / 8;
153 if (q->high_mark < 2)
154 q->high_mark = 2;
155
fc4b6853 156 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 157
158 return 0;
159}
160
6440adb5
CB		 161/**
162 * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
163 */
4a8a4322 164static int iwl3945_tx_queue_alloc(struct iwl_priv *priv,
188cf6c7 165 struct iwl_tx_queue *txq, u32 id)
b481de9c
ZY		 166{
167 struct pci_dev *dev = priv->pci_dev;
168
6440adb5
CB		 169 /* Driver private data, only for Tx (not command) queues,
170 * not shared with device. */
b481de9c
ZY		 171 if (id != IWL_CMD_QUEUE_NUM) {
172 txq->txb = kmalloc(sizeof(txq->txb[0]) *
173 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
174 if (!txq->txb) {
15b1687c 175 IWL_ERR(priv, "kmalloc for auxiliary BD "
b481de9c
ZY		 176 "structures failed\n");
177 goto error;
178 }
179 } else
180 txq->txb = NULL;
181
6440adb5
CB		 182 /* Circular buffer of transmit frame descriptors (TFDs),
183 * shared with device */
188cf6c7
SO		 184 txq->tfds39 = pci_alloc_consistent(dev,
185 sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX,
b481de9c
ZY		 186 &txq->q.dma_addr);
187
188cf6c7 188 if (!txq->tfds39) {
15b1687c 189 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n",
188cf6c7 190 sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX);
b481de9c
ZY		 191 goto error;
192 }
193 txq->q.id = id;
194
195 return 0;
196
197 error:
3ac7f146
TW		 198 kfree(txq->txb);
199 txq->txb = NULL;
b481de9c
ZY		 200
201 return -ENOMEM;
202}
203
6440adb5
CB		 204/**
205 * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
206 */
4a8a4322 207int iwl3945_tx_queue_init(struct iwl_priv *priv,
188cf6c7 208 struct iwl_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c 209{
188cf6c7 210 int len, i;
b481de9c
ZY		 211 int rc = 0;
212
6440adb5
CB		 213 /*
214 * Alloc buffer array for commands (Tx or other types of commands).
215 * For the command queue (#4), allocate command space + one big
216 * command for scan, since scan command is very huge; the system will
217 * not have two scans at the same time, so only one is needed.
218 * For data Tx queues (all other queues), no super-size command
219 * space is needed.
220 */
188cf6c7
SO		 221 len = sizeof(struct iwl_cmd);
222 for (i = 0; i <= slots_num; i++) {
223 if (i == slots_num) {
224 if (txq_id == IWL_CMD_QUEUE_NUM)
225 len += IWL_MAX_SCAN_SIZE;
226 else
227 continue;
228 }
229
230 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
231 if (!txq->cmd[i])
232 goto err;
233 }
b481de9c 234
6440adb5 235 /* Alloc driver data array and TFD circular buffer */
bb8c093b 236 rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
188cf6c7
SO		 237 if (rc)
238 goto err;
b481de9c 239
b481de9c
ZY		 240 txq->need_update = 0;
241
242 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 243 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 244 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
6440adb5
CB		 245
246 /* Initialize queue high/low-water, head/tail indexes */
bb8c093b 247 iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 248
6440adb5 249 /* Tell device where to find queue, enable DMA channel. */
bb8c093b 250 iwl3945_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 251
252 return 0;
188cf6c7
SO		 253err:
254 for (i = 0; i < slots_num; i++) {
255 kfree(txq->cmd[i]);
256 txq->cmd[i] = NULL;
257 }
258
259 if (txq_id == IWL_CMD_QUEUE_NUM) {
260 kfree(txq->cmd[slots_num]);
261 txq->cmd[slots_num] = NULL;
262 }
263 return -ENOMEM;
b481de9c
ZY		 264}
265
266/**
bb8c093b 267 * iwl3945_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 268 * @txq: Transmit queue to deallocate.
269 *
270 * Empty queue by removing and destroying all BD's.
6440adb5
CB		 271 * Free all buffers.
272 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 273 */
188cf6c7 274void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 275{
d20b3c65 276 struct iwl_queue *q = &txq->q;
b481de9c 277 struct pci_dev *dev = priv->pci_dev;
188cf6c7 278 int len, i;
b481de9c
ZY		 279
280 if (q->n_bd == 0)
281 return;
282
283 /* first, empty all BD's */
fc4b6853 284 for (; q->write_ptr != q->read_ptr;
c54b679d 285 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 286 iwl3945_hw_txq_free_tfd(priv, txq);
b481de9c 287
c2d79b48 288 len = sizeof(struct iwl_cmd) * q->n_window;
b481de9c
ZY		 289 if (q->id == IWL_CMD_QUEUE_NUM)
290 len += IWL_MAX_SCAN_SIZE;
291
6440adb5 292 /* De-alloc array of command/tx buffers */
188cf6c7
SO		 293 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
294 kfree(txq->cmd[i]);
b481de9c 295
6440adb5 296 /* De-alloc circular buffer of TFDs */
b481de9c 297 if (txq->q.n_bd)
dbb6654c 298 pci_free_consistent(dev, sizeof(struct iwl3945_tfd) *
188cf6c7 299 txq->q.n_bd, txq->tfds39, txq->q.dma_addr);
b481de9c 300
6440adb5 301 /* De-alloc array of per-TFD driver data */
3ac7f146
TW		 302 kfree(txq->txb);
303 txq->txb = NULL;
b481de9c 304
6440adb5 305 /* 0-fill queue descriptor structure */
b481de9c
ZY		 306 memset(txq, 0, sizeof(*txq));
307}
308
b481de9c 309/*************** STATION TABLE MANAGEMENT ****
9fbab516 310 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 311 * the functionality provided here
312 */
313
314/**************************************************************/
01ebd063 315#if 0 /* temporary disable till we add real remove station */
6440adb5
CB		 316/**
317 * iwl3945_remove_station - Remove driver's knowledge of station.
318 *
319 * NOTE: This does not remove station from device's station table.
320 */
4a8a4322 321static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 322{
323 int index = IWL_INVALID_STATION;
324 int i;
325 unsigned long flags;
326
327 spin_lock_irqsave(&priv->sta_lock, flags);
328
329 if (is_ap)
330 index = IWL_AP_ID;
331 else if (is_broadcast_ether_addr(addr))
3832ec9d 332 index = priv->hw_params.bcast_sta_id;
b481de9c 333 else
3832ec9d 334 for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++)
f2c7e521
AK		 335 if (priv->stations_39[i].used &&
336 !compare_ether_addr(priv->stations_39[i].sta.sta.addr,
b481de9c
ZY		 337 addr)) {
338 index = i;
339 break;
340 }
341
342 if (unlikely(index == IWL_INVALID_STATION))
343 goto out;
344
f2c7e521
AK		 345 if (priv->stations_39[index].used) {
346 priv->stations_39[index].used = 0;
b481de9c
ZY		 347 priv->num_stations--;
348 }
349
350 BUG_ON(priv->num_stations < 0);
351
352out:
353 spin_unlock_irqrestore(&priv->sta_lock, flags);
354 return 0;
355}
556f8db7 356#endif
6440adb5
CB		 357
358/**
359 * iwl3945_clear_stations_table - Clear the driver's station table
360 *
361 * NOTE: This does not clear or otherwise alter the device's station table.
362 */
4a8a4322 363static void iwl3945_clear_stations_table(struct iwl_priv *priv)
b481de9c
ZY		 364{
365 unsigned long flags;
366
367 spin_lock_irqsave(&priv->sta_lock, flags);
368
369 priv->num_stations = 0;
f2c7e521 370 memset(priv->stations_39, 0, sizeof(priv->stations_39));
b481de9c
ZY		 371
372 spin_unlock_irqrestore(&priv->sta_lock, flags);
373}
374
6440adb5
CB		 375/**
376 * iwl3945_add_station - Add station to station tables in driver and device
377 */
4a8a4322 378u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags)
b481de9c
ZY		 379{
380 int i;
381 int index = IWL_INVALID_STATION;
bb8c093b 382 struct iwl3945_station_entry *station;
b481de9c 383 unsigned long flags_spin;
c14c521e 384 u8 rate;
b481de9c
ZY		 385
386 spin_lock_irqsave(&priv->sta_lock, flags_spin);
387 if (is_ap)
388 index = IWL_AP_ID;
389 else if (is_broadcast_ether_addr(addr))
3832ec9d 390 index = priv->hw_params.bcast_sta_id;
b481de9c 391 else
3832ec9d 392 for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) {
f2c7e521 393 if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr,
b481de9c
ZY		 394 addr)) {
395 index = i;
396 break;
397 }
398
f2c7e521 399 if (!priv->stations_39[i].used &&
b481de9c
ZY		 400 index == IWL_INVALID_STATION)
401 index = i;
402 }
403
01ebd063 404 /* These two conditions has the same outcome but keep them separate
b481de9c
ZY		 405 since they have different meaning */
406 if (unlikely(index == IWL_INVALID_STATION)) {
407 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
408 return index;
409 }
410
f2c7e521
AK		 411 if (priv->stations_39[index].used &&
412 !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) {
b481de9c
ZY		 413 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
414 return index;
415 }
416
e174961c 417 IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
f2c7e521 418 station = &priv->stations_39[index];
b481de9c
ZY		 419 station->used = 1;
420 priv->num_stations++;
421
6440adb5 422 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 423 memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
b481de9c
ZY		 424 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
425 station->sta.mode = 0;
426 station->sta.sta.sta_id = index;
427 station->sta.station_flags = 0;
428
8318d78a 429 if (priv->band == IEEE80211_BAND_5GHZ)
69946333
TW		 430 rate = IWL_RATE_6M_PLCP;
431 else
432 rate = IWL_RATE_1M_PLCP;
c14c521e
ZY		 433
434 /* Turn on both antennas for the station... */
435 station->sta.rate_n_flags =
bb8c093b 436 iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
c14c521e 437
b481de9c 438 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB		 439
440 /* Add station to device's station table */
bb8c093b 441 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 442 return index;
443
444}
445
b481de9c
ZY		 446
447/*************** HOST COMMAND QUEUE FUNCTIONS *****/
448
c3056065 449#define IWL_CMD(x) case x: return #x
b481de9c
ZY		 450#define HOST_COMPLETE_TIMEOUT (HZ / 2)
451
452/**
bb8c093b 453 * iwl3945_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 454 * @priv: device private data point
455 * @cmd: a point to the ucode command structure
456 *
457 * The function returns < 0 values to indicate the operation is
458 * failed. On success, it turns the index (> 0) of command in the
459 * command queue.
460 */
c2d79b48 461static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
b481de9c 462{
188cf6c7 463 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
d20b3c65 464 struct iwl_queue *q = &txq->q;
dbb6654c 465 struct iwl3945_tfd *tfd;
c2d79b48 466 struct iwl_cmd *out_cmd;
b481de9c
ZY		 467 u32 idx;
468 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
469 dma_addr_t phys_addr;
470 int pad;
188cf6c7 471 int ret, len;
b481de9c
ZY		 472 unsigned long flags;
473
474 /* If any of the command structures end up being larger than
475 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
476 * we will need to increase the size of the TFD entries */
c2d79b48 477 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
b481de9c
ZY		 478 !(cmd->meta.flags & CMD_SIZE_HUGE));
479
c342a1b9 480
775a6e27 481 if (iwl_is_rfkill(priv)) {
c342a1b9
GG		 482 IWL_DEBUG_INFO("Not sending command - RF KILL");
483 return -EIO;
484 }
485
d20b3c65 486 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
15b1687c 487 IWL_ERR(priv, "No space for Tx\n");
b481de9c
ZY		 488 return -ENOSPC;
489 }
490
491 spin_lock_irqsave(&priv->hcmd_lock, flags);
492
188cf6c7 493 tfd = &txq->tfds39[q->write_ptr];
b481de9c
ZY		 494 memset(tfd, 0, sizeof(*tfd));
495
fc4b6853 496 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
188cf6c7 497 out_cmd = txq->cmd[idx];
b481de9c
ZY		 498
499 out_cmd->hdr.cmd = cmd->id;
500 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
501 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
502
503 /* At this point, the out_cmd now has all of the incoming cmd
504 * information */
505
506 out_cmd->hdr.flags = 0;
507 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 508 INDEX_TO_SEQ(q->write_ptr));
b481de9c 509 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
600c0e11 510 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
b481de9c 511
188cf6c7
SO		 512 len = (idx == TFD_CMD_SLOTS) ?
513 IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
514
515 phys_addr = pci_map_single(priv->pci_dev, out_cmd,
516 len, PCI_DMA_TODEVICE);
517 pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
518 pci_unmap_len_set(&out_cmd->meta, len, len);
519 phys_addr += offsetof(struct iwl_cmd, hdr);
520
bb8c093b 521 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 522
523 pad = U32_PAD(cmd->len);
dbb6654c 524 tfd->control_flags |= cpu_to_le32(TFD_CTL_PAD_SET(pad));
b481de9c
ZY		 525
526 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
527 "%d bytes at %d[%d]:%d\n",
528 get_cmd_string(out_cmd->hdr.cmd),
529 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 530 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 531
532 txq->need_update = 1;
6440adb5
CB		 533
534 /* Increment and update queue's write index */
c54b679d 535 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 536 ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 537
538 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
539 return ret ? ret : idx;
540}
541
c2d79b48
WT		 542static int iwl3945_send_cmd_async(struct iwl_priv *priv,
543 struct iwl_host_cmd *cmd)
b481de9c
ZY		 544{
545 int ret;
546
547 BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
548
549 /* An asynchronous command can not expect an SKB to be set. */
550 BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
551
552 /* An asynchronous command MUST have a callback. */
553 BUG_ON(!cmd->meta.u.callback);
554
555 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
556 return -EBUSY;
557
bb8c093b 558 ret = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c 559 if (ret < 0) {
15b1687c
WT		 560 IWL_ERR(priv,
561 "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
562 get_cmd_string(cmd->id), ret);
b481de9c
ZY		 563 return ret;
564 }
565 return 0;
566}
567
c2d79b48
WT		 568static int iwl3945_send_cmd_sync(struct iwl_priv *priv,
569 struct iwl_host_cmd *cmd)
b481de9c
ZY		 570{
571 int cmd_idx;
572 int ret;
b481de9c
ZY		 573
574 BUG_ON(cmd->meta.flags & CMD_ASYNC);
575
576 /* A synchronous command can not have a callback set. */
577 BUG_ON(cmd->meta.u.callback != NULL);
578
e5472978 579 if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
15b1687c
WT		 580 IWL_ERR(priv,
581 "Error sending %s: Already sending a host command\n",
582 get_cmd_string(cmd->id));
e5472978
TW		 583 ret = -EBUSY;
584 goto out;
b481de9c
ZY		 585 }
586
587 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
588
589 if (cmd->meta.flags & CMD_WANT_SKB)
590 cmd->meta.source = &cmd->meta;
591
bb8c093b 592 cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
b481de9c
ZY		 593 if (cmd_idx < 0) {
594 ret = cmd_idx;
15b1687c
WT		 595 IWL_ERR(priv,
596 "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
597 get_cmd_string(cmd->id), ret);
b481de9c
ZY		 598 goto out;
599 }
600
601 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
602 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
603 HOST_COMPLETE_TIMEOUT);
604 if (!ret) {
605 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
15b1687c 606 IWL_ERR(priv, "Error sending %s: time out after %dms\n",
b481de9c
ZY		 607 get_cmd_string(cmd->id),
608 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
609
610 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
611 ret = -ETIMEDOUT;
612 goto cancel;
613 }
614 }
615
616 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
617 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
618 get_cmd_string(cmd->id));
619 ret = -ECANCELED;
620 goto fail;
621 }
622 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
623 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
624 get_cmd_string(cmd->id));
625 ret = -EIO;
626 goto fail;
627 }
628 if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
15b1687c 629 IWL_ERR(priv, "Error: Response NULL in '%s'\n",
b481de9c
ZY		 630 get_cmd_string(cmd->id));
631 ret = -EIO;
73e1a65d 632 goto cancel;
b481de9c
ZY		 633 }
634
635 ret = 0;
636 goto out;
637
638cancel:
639 if (cmd->meta.flags & CMD_WANT_SKB) {
c2d79b48 640 struct iwl_cmd *qcmd;
b481de9c
ZY		 641
642 /* Cancel the CMD_WANT_SKB flag for the cmd in the
643 * TX cmd queue. Otherwise in case the cmd comes
644 * in later, it will possibly set an invalid
645 * address (cmd->meta.source). */
188cf6c7 646 qcmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
b481de9c
ZY		 647 qcmd->meta.flags &= ~CMD_WANT_SKB;
648 }
649fail:
650 if (cmd->meta.u.skb) {
651 dev_kfree_skb_any(cmd->meta.u.skb);
652 cmd->meta.u.skb = NULL;
653 }
654out:
e5472978 655 clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
b481de9c
ZY		 656 return ret;
657}
658
c2d79b48 659int iwl3945_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
b481de9c 660{
b481de9c 661 if (cmd->meta.flags & CMD_ASYNC)
bb8c093b 662 return iwl3945_send_cmd_async(priv, cmd);
b481de9c 663
bb8c093b 664 return iwl3945_send_cmd_sync(priv, cmd);
b481de9c
ZY		 665}
666
4a8a4322 667int iwl3945_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len, const void *data)
b481de9c 668{
c2d79b48 669 struct iwl_host_cmd cmd = {
b481de9c
ZY		 670 .id = id,
671 .len = len,
672 .data = data,
673 };
674
bb8c093b 675 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 676}
677
4a8a4322 678static int __must_check iwl3945_send_cmd_u32(struct iwl_priv *priv, u8 id, u32 val)
b481de9c 679{
c2d79b48 680 struct iwl_host_cmd cmd = {
b481de9c
ZY		 681 .id = id,
682 .len = sizeof(val),
683 .data = &val,
684 };
685
bb8c093b 686 return iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 687}
688
4a8a4322 689int iwl3945_send_statistics_request(struct iwl_priv *priv)
b481de9c 690{
bb8c093b 691 return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
b481de9c
ZY		 692}
693
b481de9c 694/**
bb8c093b 695 * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
8318d78a
JB		 696 * @band: 2.4 or 5 GHz band
697 * @channel: Any channel valid for the requested band
b481de9c 698
8318d78a 699 * In addition to setting the staging RXON, priv->band is also set.
b481de9c
ZY		 700 *
701 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
8318d78a 702 * in the staging RXON flag structure based on the band
b481de9c 703 */
4a8a4322 704static int iwl3945_set_rxon_channel(struct iwl_priv *priv,
8318d78a
JB		 705 enum ieee80211_band band,
706 u16 channel)
b481de9c 707{
8318d78a 708 if (!iwl3945_get_channel_info(priv, band, channel)) {
b481de9c 709 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
8318d78a 710 channel, band);
b481de9c
ZY		 711 return -EINVAL;
712 }
713
f2c7e521 714 if ((le16_to_cpu(priv->staging39_rxon.channel) == channel) &&
8318d78a 715 (priv->band == band))
b481de9c
ZY		 716 return 0;
717
f2c7e521 718 priv->staging39_rxon.channel = cpu_to_le16(channel);
8318d78a 719 if (band == IEEE80211_BAND_5GHZ)
f2c7e521 720 priv->staging39_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
b481de9c 721 else
f2c7e521 722 priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
b481de9c 723
8318d78a 724 priv->band = band;
b481de9c 725
8318d78a 726 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
b481de9c
ZY		 727
728 return 0;
729}
730
731/**
bb8c093b 732 * iwl3945_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 733 *
734 * NOTE: This is really only useful during development and can eventually
735 * be #ifdef'd out once the driver is stable and folks aren't actively
736 * making changes
737 */
4a8a4322 738static int iwl3945_check_rxon_cmd(struct iwl_priv *priv)
b481de9c
ZY		 739{
740 int error = 0;
741 int counter = 1;
f2c7e521 742 struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
b481de9c
ZY		 743
744 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
745 error |= le32_to_cpu(rxon->flags &
746 (RXON_FLG_TGJ_NARROW_BAND_MSK |
747 RXON_FLG_RADAR_DETECT_MSK));
748 if (error)
39aadf8c 749 IWL_WARN(priv, "check 24G fields %d | %d\n",
b481de9c
ZY		 750 counter++, error);
751 } else {
752 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
753 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
754 if (error)
39aadf8c 755 IWL_WARN(priv, "check 52 fields %d | %d\n",
b481de9c
ZY		 756 counter++, error);
757 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
758 if (error)
39aadf8c 759 IWL_WARN(priv, "check 52 CCK %d | %d\n",
b481de9c
ZY		 760 counter++, error);
761 }
762 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
763 if (error)
39aadf8c 764 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
b481de9c
ZY		 765
766 /* make sure basic rates 6Mbps and 1Mbps are supported */
767 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
768 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
769 if (error)
39aadf8c 770 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
b481de9c
ZY		 771
772 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
773 if (error)
39aadf8c 774 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
b481de9c
ZY		 775
776 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
777 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
778 if (error)
39aadf8c 779 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
b481de9c
ZY		 780 counter++, error);
781
782 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
783 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
784 if (error)
39aadf8c 785 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
b481de9c
ZY		 786 counter++, error);
787
788 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
789 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
790 if (error)
39aadf8c 791 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
b481de9c
ZY		 792 counter++, error);
793
794 if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
795 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
796 RXON_FLG_ANT_A_MSK)) == 0);
797 if (error)
39aadf8c 798 IWL_WARN(priv, "check antenna %d %d\n", counter++, error);
b481de9c
ZY		 799
800 if (error)
39aadf8c 801 IWL_WARN(priv, "Tuning to channel %d\n",
b481de9c
ZY		 802 le16_to_cpu(rxon->channel));
803
804 if (error) {
15b1687c 805 IWL_ERR(priv, "Not a valid rxon_assoc_cmd field values\n");
b481de9c
ZY		 806 return -1;
807 }
808 return 0;
809}
810
811/**
9fbab516 812 * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 813 * @priv: staging_rxon is compared to active_rxon
b481de9c 814 *
9fbab516
BC		 815 * If the RXON structure is changing enough to require a new tune,
816 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
817 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 818 */
4a8a4322 819static int iwl3945_full_rxon_required(struct iwl_priv *priv)
b481de9c
ZY		 820{
821
822 /* These items are only settable from the full RXON command */
5d1e2325 823 if (!(iwl3945_is_associated(priv)) ||
f2c7e521
AK		 824 compare_ether_addr(priv->staging39_rxon.bssid_addr,
825 priv->active39_rxon.bssid_addr) ||
826 compare_ether_addr(priv->staging39_rxon.node_addr,
827 priv->active39_rxon.node_addr) ||
828 compare_ether_addr(priv->staging39_rxon.wlap_bssid_addr,
829 priv->active39_rxon.wlap_bssid_addr) ||
830 (priv->staging39_rxon.dev_type != priv->active39_rxon.dev_type) ||
831 (priv->staging39_rxon.channel != priv->active39_rxon.channel) ||
832 (priv->staging39_rxon.air_propagation !=
833 priv->active39_rxon.air_propagation) ||
834 (priv->staging39_rxon.assoc_id != priv->active39_rxon.assoc_id))
b481de9c
ZY		 835 return 1;
836
837 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
838 * be updated with the RXON_ASSOC command -- however only some
839 * flag transitions are allowed using RXON_ASSOC */
840
841 /* Check if we are not switching bands */
f2c7e521
AK		 842 if ((priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
843 (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK))
b481de9c
ZY		 844 return 1;
845
846 /* Check if we are switching association toggle */
f2c7e521
AK		 847 if ((priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
848 (priv->active39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
b481de9c
ZY		 849 return 1;
850
851 return 0;
852}
853
4a8a4322 854static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
b481de9c
ZY		 855{
856 int rc = 0;
3d24a9f7 857 struct iwl_rx_packet *res = NULL;
bb8c093b 858 struct iwl3945_rxon_assoc_cmd rxon_assoc;
c2d79b48 859 struct iwl_host_cmd cmd = {
b481de9c
ZY		 860 .id = REPLY_RXON_ASSOC,
861 .len = sizeof(rxon_assoc),
862 .meta.flags = CMD_WANT_SKB,
863 .data = &rxon_assoc,
864 };
f2c7e521
AK		 865 const struct iwl3945_rxon_cmd *rxon1 = &priv->staging39_rxon;
866 const struct iwl3945_rxon_cmd *rxon2 = &priv->active39_rxon;
b481de9c
ZY		 867
868 if ((rxon1->flags == rxon2->flags) &&
869 (rxon1->filter_flags == rxon2->filter_flags) &&
870 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
871 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
872 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
873 return 0;
874 }
875
f2c7e521
AK		 876 rxon_assoc.flags = priv->staging39_rxon.flags;
877 rxon_assoc.filter_flags = priv->staging39_rxon.filter_flags;
878 rxon_assoc.ofdm_basic_rates = priv->staging39_rxon.ofdm_basic_rates;
879 rxon_assoc.cck_basic_rates = priv->staging39_rxon.cck_basic_rates;
b481de9c
ZY		 880 rxon_assoc.reserved = 0;
881
bb8c093b 882 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 883 if (rc)
884 return rc;
885
3d24a9f7 886 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c 887 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 888 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
b481de9c
ZY		 889 rc = -EIO;
890 }
891
892 priv->alloc_rxb_skb--;
893 dev_kfree_skb_any(cmd.meta.u.skb);
894
895 return rc;
896}
897
898/**
bb8c093b 899 * iwl3945_commit_rxon - commit staging_rxon to hardware
b481de9c 900 *
01ebd063 901 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 902 * the active_rxon structure is updated with the new data. This
903 * function correctly transitions out of the RXON_ASSOC_MSK state if
904 * a HW tune is required based on the RXON structure changes.
905 */
4a8a4322 906static int iwl3945_commit_rxon(struct iwl_priv *priv)
b481de9c
ZY		 907{
908 /* cast away the const for active_rxon in this function */
f2c7e521 909 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active39_rxon;
b481de9c
ZY		 910 int rc = 0;
911
775a6e27 912 if (!iwl_is_alive(priv))
b481de9c
ZY		 913 return -1;
914
915 /* always get timestamp with Rx frame */
f2c7e521 916 priv->staging39_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
b481de9c
ZY		 917
918 /* select antenna */
f2c7e521 919 priv->staging39_rxon.flags &=
b481de9c 920 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
f2c7e521 921 priv->staging39_rxon.flags |= iwl3945_get_antenna_flags(priv);
b481de9c 922
a3139c59 923 rc = iwl3945_check_rxon_cmd(priv);
b481de9c 924 if (rc) {
15b1687c 925 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY		 926 return -EINVAL;
927 }
928
929 /* If we don't need to send a full RXON, we can use
bb8c093b 930 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 931 * and other flags for the current radio configuration. */
bb8c093b
CH		 932 if (!iwl3945_full_rxon_required(priv)) {
933 rc = iwl3945_send_rxon_assoc(priv);
b481de9c 934 if (rc) {
15b1687c 935 IWL_ERR(priv, "Error setting RXON_ASSOC "
b481de9c
ZY		 936 "configuration (%d).\n", rc);
937 return rc;
938 }
939
f2c7e521 940 memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
b481de9c
ZY		 941
942 return 0;
943 }
944
945 /* If we are currently associated and the new config requires
946 * an RXON_ASSOC and the new config wants the associated mask enabled,
947 * we must clear the associated from the active configuration
948 * before we apply the new config */
bb8c093b 949 if (iwl3945_is_associated(priv) &&
f2c7e521 950 (priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
b481de9c
ZY		 951 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
952 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
953
bb8c093b
CH		 954 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
955 sizeof(struct iwl3945_rxon_cmd),
f2c7e521 956 &priv->active39_rxon);
b481de9c
ZY		 957
958 /* If the mask clearing failed then we set
959 * active_rxon back to what it was previously */
960 if (rc) {
961 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 962 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
b481de9c
ZY		 963 "configuration (%d).\n", rc);
964 return rc;
965 }
b481de9c
ZY		 966 }
967
968 IWL_DEBUG_INFO("Sending RXON\n"
969 "* with%s RXON_FILTER_ASSOC_MSK\n"
970 "* channel = %d\n"
e174961c 971 "* bssid = %pM\n",
f2c7e521 972 ((priv->staging39_rxon.filter_flags &
b481de9c 973 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
f2c7e521 974 le16_to_cpu(priv->staging39_rxon.channel),
e174961c 975 priv->staging_rxon.bssid_addr);
b481de9c
ZY		 976
977 /* Apply the new configuration */
bb8c093b 978 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
f2c7e521 979 sizeof(struct iwl3945_rxon_cmd), &priv->staging39_rxon);
b481de9c 980 if (rc) {
15b1687c 981 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
b481de9c
ZY		 982 return rc;
983 }
984
f2c7e521 985 memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
b481de9c 986
bb8c093b 987 iwl3945_clear_stations_table(priv);
556f8db7 988
b481de9c
ZY		 989 /* If we issue a new RXON command which required a tune then we must
990 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 991 rc = iwl3945_hw_reg_send_txpower(priv);
b481de9c 992 if (rc) {
15b1687c 993 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
b481de9c
ZY		 994 return rc;
995 }
996
997 /* Add the broadcast address so we can send broadcast frames */
b5323d36 998 if (iwl3945_add_station(priv, iwl_bcast_addr, 0, 0) ==
b481de9c 999 IWL_INVALID_STATION) {
15b1687c 1000 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
b481de9c
ZY		 1001 return -EIO;
1002 }
1003
1004 /* If we have set the ASSOC_MSK and we are in BSS mode then
1005 * add the IWL_AP_ID to the station rate table */
bb8c093b 1006 if (iwl3945_is_associated(priv) &&
05c914fe 1007 (priv->iw_mode == NL80211_IFTYPE_STATION))
f2c7e521 1008 if (iwl3945_add_station(priv, priv->active39_rxon.bssid_addr, 1, 0)
b481de9c 1009 == IWL_INVALID_STATION) {
15b1687c 1010 IWL_ERR(priv, "Error adding AP address for transmit\n");
b481de9c
ZY		 1011 return -EIO;
1012 }
1013
8318d78a 1014 /* Init the hardware's rate fallback order based on the band */
b481de9c
ZY		 1015 rc = iwl3945_init_hw_rate_table(priv);
1016 if (rc) {
15b1687c 1017 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
b481de9c
ZY		 1018 return -EIO;
1019 }
1020
1021 return 0;
1022}
1023
4a8a4322 1024static int iwl3945_send_bt_config(struct iwl_priv *priv)
b481de9c 1025{
4c897253 1026 struct iwl_bt_cmd bt_cmd = {
b481de9c
ZY		 1027 .flags = 3,
1028 .lead_time = 0xAA,
1029 .max_kill = 1,
1030 .kill_ack_mask = 0,
1031 .kill_cts_mask = 0,
1032 };
1033
bb8c093b 1034 return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
4c897253 1035 sizeof(bt_cmd), &bt_cmd);
b481de9c
ZY		 1036}
1037
4a8a4322 1038static int iwl3945_send_scan_abort(struct iwl_priv *priv)
b481de9c
ZY		 1039{
1040 int rc = 0;
3d24a9f7 1041 struct iwl_rx_packet *res;
c2d79b48 1042 struct iwl_host_cmd cmd = {
b481de9c
ZY		 1043 .id = REPLY_SCAN_ABORT_CMD,
1044 .meta.flags = CMD_WANT_SKB,
1045 };
1046
1047 /* If there isn't a scan actively going on in the hardware
1048 * then we are in between scan bands and not actually
1049 * actively scanning, so don't send the abort command */
1050 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1051 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1052 return 0;
1053 }
1054
bb8c093b 1055 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1056 if (rc) {
1057 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1058 return rc;
1059 }
1060
3d24a9f7 1061 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1062 if (res->u.status != CAN_ABORT_STATUS) {
1063 /* The scan abort will return 1 for success or
1064 * 2 for "failure". A failure condition can be
1065 * due to simply not being in an active scan which
1066 * can occur if we send the scan abort before we
1067 * the microcode has notified us that a scan is
1068 * completed. */
1069 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1070 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1071 clear_bit(STATUS_SCAN_HW, &priv->status);
1072 }
1073
1074 dev_kfree_skb_any(cmd.meta.u.skb);
1075
1076 return rc;
1077}
1078
4a8a4322 1079static int iwl3945_add_sta_sync_callback(struct iwl_priv *priv,
c2d79b48 1080 struct iwl_cmd *cmd, struct sk_buff *skb)
b481de9c 1081{
3d24a9f7 1082 struct iwl_rx_packet *res = NULL;
b481de9c
ZY		 1083
1084 if (!skb) {
15b1687c 1085 IWL_ERR(priv, "Error: Response NULL in REPLY_ADD_STA.\n");
b481de9c
ZY		 1086 return 1;
1087 }
1088
3d24a9f7 1089 res = (struct iwl_rx_packet *)skb->data;
b481de9c 1090 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 1091 IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
b481de9c
ZY		 1092 res->hdr.flags);
1093 return 1;
1094 }
1095
1096 switch (res->u.add_sta.status) {
1097 case ADD_STA_SUCCESS_MSK:
1098 break;
1099 default:
1100 break;
1101 }
1102
1103 /* We didn't cache the SKB; let the caller free it */
1104 return 1;
1105}
1106
4a8a4322 1107int iwl3945_send_add_station(struct iwl_priv *priv,
bb8c093b 1108 struct iwl3945_addsta_cmd *sta, u8 flags)
b481de9c 1109{
3d24a9f7 1110 struct iwl_rx_packet *res = NULL;
b481de9c 1111 int rc = 0;
c2d79b48 1112 struct iwl_host_cmd cmd = {
b481de9c 1113 .id = REPLY_ADD_STA,
bb8c093b 1114 .len = sizeof(struct iwl3945_addsta_cmd),
b481de9c
ZY		 1115 .meta.flags = flags,
1116 .data = sta,
1117 };
1118
1119 if (flags & CMD_ASYNC)
bb8c093b 1120 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
b481de9c
ZY		 1121 else
1122 cmd.meta.flags |= CMD_WANT_SKB;
1123
bb8c093b 1124 rc = iwl3945_send_cmd(priv, &cmd);
b481de9c
ZY		 1125
1126 if (rc || (flags & CMD_ASYNC))
1127 return rc;
1128
3d24a9f7 1129 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c 1130 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 1131 IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
b481de9c
ZY		 1132 res->hdr.flags);
1133 rc = -EIO;
1134 }
1135
1136 if (rc == 0) {
1137 switch (res->u.add_sta.status) {
1138 case ADD_STA_SUCCESS_MSK:
1139 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1140 break;
1141 default:
1142 rc = -EIO;
39aadf8c 1143 IWL_WARN(priv, "REPLY_ADD_STA failed\n");
b481de9c
ZY		 1144 break;
1145 }
1146 }
1147
1148 priv->alloc_rxb_skb--;
1149 dev_kfree_skb_any(cmd.meta.u.skb);
1150
1151 return rc;
1152}
1153
4a8a4322 1154static int iwl3945_update_sta_key_info(struct iwl_priv *priv,
b481de9c
ZY		 1155 struct ieee80211_key_conf *keyconf,
1156 u8 sta_id)
1157{
1158 unsigned long flags;
1159 __le16 key_flags = 0;
1160
1161 switch (keyconf->alg) {
1162 case ALG_CCMP:
1163 key_flags |= STA_KEY_FLG_CCMP;
1164 key_flags |= cpu_to_le16(
1165 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1166 key_flags &= ~STA_KEY_FLG_INVALID;
1167 break;
1168 case ALG_TKIP:
1169 case ALG_WEP:
b481de9c
ZY		 1170 default:
1171 return -EINVAL;
1172 }
1173 spin_lock_irqsave(&priv->sta_lock, flags);
f2c7e521
AK		 1174 priv->stations_39[sta_id].keyinfo.alg = keyconf->alg;
1175 priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen;
1176 memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key,
b481de9c
ZY		 1177 keyconf->keylen);
1178
f2c7e521 1179 memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key,
b481de9c 1180 keyconf->keylen);
f2c7e521
AK		 1181 priv->stations_39[sta_id].sta.key.key_flags = key_flags;
1182 priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1183 priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c
ZY		 1184
1185 spin_unlock_irqrestore(&priv->sta_lock, flags);
1186
1187 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
f2c7e521 1188 iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
b481de9c
ZY		 1189 return 0;
1190}
1191
4a8a4322 1192static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
b481de9c
ZY		 1193{
1194 unsigned long flags;
1195
1196 spin_lock_irqsave(&priv->sta_lock, flags);
f2c7e521
AK		 1197 memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1198 memset(&priv->stations_39[sta_id].sta.key, 0,
4c897253 1199 sizeof(struct iwl4965_keyinfo));
f2c7e521
AK		 1200 priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1201 priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1202 priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c
ZY		 1203 spin_unlock_irqrestore(&priv->sta_lock, flags);
1204
1205 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
f2c7e521 1206 iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
b481de9c
ZY		 1207 return 0;
1208}
1209
4a8a4322 1210static void iwl3945_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 1211{
1212 struct list_head *element;
1213
1214 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1215 priv->frames_count);
1216
1217 while (!list_empty(&priv->free_frames)) {
1218 element = priv->free_frames.next;
1219 list_del(element);
bb8c093b 1220 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY		 1221 priv->frames_count--;
1222 }
1223
1224 if (priv->frames_count) {
39aadf8c 1225 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY		 1226 priv->frames_count);
1227 priv->frames_count = 0;
1228 }
1229}
1230
4a8a4322 1231static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
b481de9c 1232{
bb8c093b 1233 struct iwl3945_frame *frame;
b481de9c
ZY		 1234 struct list_head *element;
1235 if (list_empty(&priv->free_frames)) {
1236 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1237 if (!frame) {
15b1687c 1238 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY		 1239 return NULL;
1240 }
1241
1242 priv->frames_count++;
1243 return frame;
1244 }
1245
1246 element = priv->free_frames.next;
1247 list_del(element);
bb8c093b 1248 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY		 1249}
1250
4a8a4322 1251static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY		 1252{
1253 memset(frame, 0, sizeof(*frame));
1254 list_add(&frame->list, &priv->free_frames);
1255}
1256
4a8a4322 1257unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
b481de9c 1258 struct ieee80211_hdr *hdr,
73ec1cc2 1259 int left)
b481de9c
ZY		 1260{
1261
bb8c093b 1262 if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB		 1263 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
1264 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY		 1265 return 0;
1266
1267 if (priv->ibss_beacon->len > left)
1268 return 0;
1269
1270 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1271
1272 return priv->ibss_beacon->len;
1273}
1274
4a8a4322 1275static u8 iwl3945_rate_get_lowest_plcp(struct iwl_priv *priv)
b481de9c
ZY		 1276{
1277 u8 i;
c24f0817
KA		 1278 int rate_mask;
1279
1280 /* Set rate mask*/
f2c7e521 1281 if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
dbce56a4 1282 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
c24f0817 1283 else
dbce56a4 1284 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
b481de9c
ZY		 1285
1286 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1287 i = iwl3945_rates[i].next_ieee) {
b481de9c 1288 if (rate_mask & (1 << i))
bb8c093b 1289 return iwl3945_rates[i].plcp;
b481de9c
ZY		 1290 }
1291
c24f0817 1292 /* No valid rate was found. Assign the lowest one */
f2c7e521 1293 if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
c24f0817
KA		 1294 return IWL_RATE_1M_PLCP;
1295 else
1296 return IWL_RATE_6M_PLCP;
b481de9c
ZY		 1297}
1298
4a8a4322 1299static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 1300{
bb8c093b 1301 struct iwl3945_frame *frame;
b481de9c
ZY		 1302 unsigned int frame_size;
1303 int rc;
1304 u8 rate;
1305
bb8c093b 1306 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY		 1307
1308 if (!frame) {
15b1687c 1309 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY		 1310 "command.\n");
1311 return -ENOMEM;
1312 }
1313
c24f0817 1314 rate = iwl3945_rate_get_lowest_plcp(priv);
b481de9c 1315
bb8c093b 1316 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1317
bb8c093b 1318 rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1319 &frame->u.cmd[0]);
1320
bb8c093b 1321 iwl3945_free_frame(priv, frame);
b481de9c
ZY		 1322
1323 return rc;
1324}
1325
1326/******************************************************************************
1327 *
1328 * EEPROM related functions
1329 *
1330 ******************************************************************************/
1331
4a8a4322 1332static void get_eeprom_mac(struct iwl_priv *priv, u8 *mac)
b481de9c 1333{
f2c7e521 1334 memcpy(mac, priv->eeprom39.mac_address, 6);
b481de9c
ZY		 1335}
1336
74a3a250
RC		 1337/*
1338 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1339 * embedded controller) as EEPROM reader; each read is a series of pulses
1340 * to/from the EEPROM chip, not a single event, so even reads could conflict
1341 * if they weren't arbitrated by some ownership mechanism. Here, the driver
1342 * simply claims ownership, which should be safe when this function is called
1343 * (i.e. before loading uCode!).
1344 */
4a8a4322 1345static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
74a3a250 1346{
5d49f498 1347 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
74a3a250
RC		 1348 return 0;
1349}
1350
b481de9c 1351/**
bb8c093b 1352 * iwl3945_eeprom_init - read EEPROM contents
b481de9c 1353 *
f2c7e521 1354 * Load the EEPROM contents from adapter into priv->eeprom39
b481de9c
ZY		 1355 *
1356 * NOTE: This routine uses the non-debug IO access functions.
1357 */
4a8a4322 1358int iwl3945_eeprom_init(struct iwl_priv *priv)
b481de9c 1359{
f2c7e521 1360 u16 *e = (u16 *)&priv->eeprom39;
5d49f498 1361 u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
f2c7e521 1362 int sz = sizeof(priv->eeprom39);
3d5717ad 1363 int ret;
b481de9c
ZY		 1364 u16 addr;
1365
1366 /* The EEPROM structure has several padding buffers within it
1367 * and when adding new EEPROM maps is subject to programmer errors
1368 * which may be very difficult to identify without explicitly
1369 * checking the resulting size of the eeprom map. */
f2c7e521 1370 BUILD_BUG_ON(sizeof(priv->eeprom39) != IWL_EEPROM_IMAGE_SIZE);
b481de9c
ZY		 1371
1372 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
15b1687c 1373 IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
b481de9c
ZY		 1374 return -ENOENT;
1375 }
1376
6440adb5 1377 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
3d5717ad
ZY		 1378 ret = iwl3945_eeprom_acquire_semaphore(priv);
1379 if (ret < 0) {
15b1687c 1380 IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
b481de9c
ZY		 1381 return -ENOENT;
1382 }
1383
1384 /* eeprom is an array of 16bit values */
1385 for (addr = 0; addr < sz; addr += sizeof(u16)) {
3d5717ad 1386 u32 r;
b481de9c 1387
5d49f498 1388 _iwl_write32(priv, CSR_EEPROM_REG,
3d5717ad 1389 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
5d49f498
AK		 1390 _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
1391 ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
3d5717ad
ZY		 1392 CSR_EEPROM_REG_READ_VALID_MSK,
1393 IWL_EEPROM_ACCESS_TIMEOUT);
1394 if (ret < 0) {
15b1687c 1395 IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
3d5717ad 1396 return ret;
b481de9c 1397 }
3d5717ad 1398
5d49f498 1399 r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
58ff6d4d 1400 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
b481de9c
ZY		 1401 }
1402
1403 return 0;
1404}
1405
4a8a4322 1406static void iwl3945_unset_hw_params(struct iwl_priv *priv)
b481de9c 1407{
3832ec9d 1408 if (priv->shared_virt)
b481de9c 1409 pci_free_consistent(priv->pci_dev,
bb8c093b 1410 sizeof(struct iwl3945_shared),
3832ec9d
AK		 1411 priv->shared_virt,
1412 priv->shared_phys);
b481de9c
ZY		 1413}
1414
1415/**
bb8c093b 1416 * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1417 *
1418 * return : set the bit for each supported rate insert in ie
1419 */
bb8c093b 1420static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1421 u16 basic_rate, int *left)
b481de9c
ZY		 1422{
1423 u16 ret_rates = 0, bit;
1424 int i;
c7c46676
TW		 1425 u8 *cnt = ie;
1426 u8 *rates = ie + 1;
b481de9c
ZY		 1427
1428 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1429 if (bit & supported_rate) {
1430 ret_rates |= bit;
bb8c093b 1431 rates[*cnt] = iwl3945_rates[i].ieee |
c7c46676
TW		 1432 ((bit & basic_rate) ? 0x80 : 0x00);
1433 (*cnt)++;
1434 (*left)--;
1435 if ((*left <= 0) ||
1436 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1437 break;
1438 }
1439 }
1440
1441 return ret_rates;
1442}
1443
1444/**
bb8c093b 1445 * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1446 */
4a8a4322 1447static u16 iwl3945_fill_probe_req(struct iwl_priv *priv,
b481de9c 1448 struct ieee80211_mgmt *frame,
430cfe95 1449 int left)
b481de9c
ZY		 1450{
1451 int len = 0;
1452 u8 *pos = NULL;
c7c46676 1453 u16 active_rates, ret_rates, cck_rates;
b481de9c
ZY		 1454
1455 /* Make sure there is enough space for the probe request,
1456 * two mandatory IEs and the data */
1457 left -= 24;
1458 if (left < 0)
1459 return 0;
1460 len += 24;
1461
1462 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
b5323d36 1463 memcpy(frame->da, iwl_bcast_addr, ETH_ALEN);
b481de9c 1464 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
b5323d36 1465 memcpy(frame->bssid, iwl_bcast_addr, ETH_ALEN);
b481de9c
ZY		 1466 frame->seq_ctrl = 0;
1467
1468 /* fill in our indirect SSID IE */
1469 /* ...next IE... */
1470
1471 left -= 2;
1472 if (left < 0)
1473 return 0;
1474 len += 2;
1475 pos = &(frame->u.probe_req.variable[0]);
1476 *pos++ = WLAN_EID_SSID;
1477 *pos++ = 0;
1478
b481de9c
ZY		 1479 /* fill in supported rate */
1480 /* ...next IE... */
1481 left -= 2;
1482 if (left < 0)
1483 return 0;
c7c46676 1484
b481de9c
ZY		 1485 /* ... fill it in... */
1486 *pos++ = WLAN_EID_SUPP_RATES;
1487 *pos = 0;
c7c46676
TW		 1488
1489 priv->active_rate = priv->rates_mask;
1490 active_rates = priv->active_rate;
b481de9c
ZY		 1491 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1492
c7c46676 1493 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1494 ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
c7c46676
TW		 1495 priv->active_rate_basic, &left);
1496 active_rates &= ~ret_rates;
1497
bb8c093b 1498 ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676
TW		 1499 priv->active_rate_basic, &left);
1500 active_rates &= ~ret_rates;
1501
b481de9c
ZY		 1502 len += 2 + *pos;
1503 pos += (*pos) + 1;
c7c46676 1504 if (active_rates == 0)
b481de9c
ZY		 1505 goto fill_end;
1506
1507 /* fill in supported extended rate */
1508 /* ...next IE... */
1509 left -= 2;
1510 if (left < 0)
1511 return 0;
1512 /* ... fill it in... */
1513 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1514 *pos = 0;
bb8c093b 1515 iwl3945_supported_rate_to_ie(pos, active_rates,
c7c46676 1516 priv->active_rate_basic, &left);
b481de9c
ZY		 1517 if (*pos > 0)
1518 len += 2 + *pos;
1519
1520 fill_end:
1521 return (u16)len;
1522}
1523
1524/*
1525 * QoS support
1526*/
4a8a4322 1527static int iwl3945_send_qos_params_command(struct iwl_priv *priv,
4c897253 1528 struct iwl_qosparam_cmd *qos)
b481de9c
ZY		 1529{
1530
bb8c093b 1531 return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
4c897253 1532 sizeof(struct iwl_qosparam_cmd), qos);
b481de9c
ZY		 1533}
1534
4a8a4322 1535static void iwl3945_activate_qos(struct iwl_priv *priv, u8 force)
b481de9c
ZY		 1536{
1537 unsigned long flags;
1538
b481de9c
ZY		 1539 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1540 return;
1541
b481de9c
ZY		 1542 spin_lock_irqsave(&priv->lock, flags);
1543 priv->qos_data.def_qos_parm.qos_flags = 0;
1544
1545 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1546 !priv->qos_data.qos_cap.q_AP.txop_request)
1547 priv->qos_data.def_qos_parm.qos_flags |=
1548 QOS_PARAM_FLG_TXOP_TYPE_MSK;
1549
1550 if (priv->qos_data.qos_active)
1551 priv->qos_data.def_qos_parm.qos_flags |=
1552 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1553
1554 spin_unlock_irqrestore(&priv->lock, flags);
1555
bb8c093b 1556 if (force || iwl3945_is_associated(priv)) {
a96a27f9 1557 IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
b481de9c
ZY		 1558 priv->qos_data.qos_active);
1559
bb8c093b 1560 iwl3945_send_qos_params_command(priv,
b481de9c
ZY		 1561 &(priv->qos_data.def_qos_parm));
1562 }
1563}
1564
b481de9c
ZY		 1565/*
1566 * Power management (not Tx power!) functions
1567 */
1568#define MSEC_TO_USEC 1024
1569
600c0e11
TW		 1570
1571#define NOSLP __constant_cpu_to_le16(0), 0, 0
1572#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
b481de9c
ZY		 1573#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1574#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1575 __constant_cpu_to_le32(X1), \
1576 __constant_cpu_to_le32(X2), \
1577 __constant_cpu_to_le32(X3), \
1578 __constant_cpu_to_le32(X4)}
1579
b481de9c 1580/* default power management (not Tx power) table values */
a96a27f9 1581/* for TIM 0-10 */
1125eff3 1582static struct iwl_power_vec_entry range_0[IWL39_POWER_AC] = {
b481de9c
ZY		 1583 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1584 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1585 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1586 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1587 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1588 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1589};
1590
a96a27f9 1591/* for TIM > 10 */
1125eff3 1592static struct iwl_power_vec_entry range_1[IWL39_POWER_AC] = {
b481de9c
ZY		 1593 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1594 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1595 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1596 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1597 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1598 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1599 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1600 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1601 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1602 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1603};
1604
4a8a4322 1605int iwl3945_power_init_handle(struct iwl_priv *priv)
b481de9c
ZY		 1606{
1607 int rc = 0, i;
bb8c093b 1608 struct iwl3945_power_mgr *pow_data;
1125eff3 1609 int size = sizeof(struct iwl_power_vec_entry) * IWL39_POWER_AC;
b481de9c
ZY		 1610 u16 pci_pm;
1611
1612 IWL_DEBUG_POWER("Initialize power \n");
1613
f2c7e521 1614 pow_data = &(priv->power_data_39);
b481de9c
ZY		 1615
1616 memset(pow_data, 0, sizeof(*pow_data));
1617
1618 pow_data->active_index = IWL_POWER_RANGE_0;
1619 pow_data->dtim_val = 0xffff;
1620
1621 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1622 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1623
1624 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1625 if (rc != 0)
1626 return 0;
1627 else {
600c0e11 1628 struct iwl_powertable_cmd *cmd;
b481de9c
ZY		 1629
1630 IWL_DEBUG_POWER("adjust power command flags\n");
1631
1125eff3 1632 for (i = 0; i < IWL39_POWER_AC; i++) {
b481de9c
ZY		 1633 cmd = &pow_data->pwr_range_0[i].cmd;
1634
1635 if (pci_pm & 0x1)
1636 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1637 else
1638 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1639 }
1640 }
1641 return rc;
1642}
1643
4a8a4322 1644static int iwl3945_update_power_cmd(struct iwl_priv *priv,
600c0e11 1645 struct iwl_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 1646{
1647 int rc = 0, i;
1648 u8 skip;
1649 u32 max_sleep = 0;
1125eff3 1650 struct iwl_power_vec_entry *range;
b481de9c 1651 u8 period = 0;
bb8c093b 1652 struct iwl3945_power_mgr *pow_data;
b481de9c
ZY		 1653
1654 if (mode > IWL_POWER_INDEX_5) {
1655 IWL_DEBUG_POWER("Error invalid power mode \n");
1656 return -1;
1657 }
f2c7e521 1658 pow_data = &(priv->power_data_39);
b481de9c
ZY		 1659
1660 if (pow_data->active_index == IWL_POWER_RANGE_0)
1661 range = &pow_data->pwr_range_0[0];
1662 else
1663 range = &pow_data->pwr_range_1[1];
1664
bb8c093b 1665 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
b481de9c
ZY		 1666
1667#ifdef IWL_MAC80211_DISABLE
1668 if (priv->assoc_network != NULL) {
1669 unsigned long flags;
1670
1671 period = priv->assoc_network->tim.tim_period;
1672 }
1673#endif /*IWL_MAC80211_DISABLE */
1674 skip = range[mode].no_dtim;
1675
1676 if (period == 0) {
1677 period = 1;
1678 skip = 0;
1679 }
1680
1681 if (skip == 0) {
1682 max_sleep = period;
1683 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1684 } else {
1685 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1686 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1687 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1688 }
1689
1690 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1691 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1692 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1693 }
1694
1695 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1696 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1697 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1698 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1699 le32_to_cpu(cmd->sleep_interval[0]),
1700 le32_to_cpu(cmd->sleep_interval[1]),
1701 le32_to_cpu(cmd->sleep_interval[2]),
1702 le32_to_cpu(cmd->sleep_interval[3]),
1703 le32_to_cpu(cmd->sleep_interval[4]));
1704
1705 return rc;
1706}
1707
4a8a4322 1708static int iwl3945_send_power_mode(struct iwl_priv *priv, u32 mode)
b481de9c 1709{
9a62f73b 1710 u32 uninitialized_var(final_mode);
b481de9c 1711 int rc;
600c0e11 1712 struct iwl_powertable_cmd cmd;
b481de9c
ZY		 1713
1714 /* If on battery, set to 3,
01ebd063 1715 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 1716 * else user level */
1717 switch (mode) {
1125eff3 1718 case IWL39_POWER_BATTERY:
b481de9c
ZY		 1719 final_mode = IWL_POWER_INDEX_3;
1720 break;
1125eff3 1721 case IWL39_POWER_AC:
b481de9c
ZY		 1722 final_mode = IWL_POWER_MODE_CAM;
1723 break;
1724 default:
1725 final_mode = mode;
1726 break;
1727 }
1728
bb8c093b 1729 iwl3945_update_power_cmd(priv, &cmd, final_mode);
b481de9c 1730
600c0e11
TW		 1731 /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
1732 rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD,
1733 sizeof(struct iwl3945_powertable_cmd), &cmd);
b481de9c
ZY		 1734
1735 if (final_mode == IWL_POWER_MODE_CAM)
1736 clear_bit(STATUS_POWER_PMI, &priv->status);
1737 else
1738 set_bit(STATUS_POWER_PMI, &priv->status);
1739
1740 return rc;
1741}
1742
b481de9c 1743/**
bb8c093b 1744 * iwl3945_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 1745 *
1746 * NOTE: priv->mutex is not required before calling this function
1747 */
4a8a4322 1748static int iwl3945_scan_cancel(struct iwl_priv *priv)
b481de9c
ZY		 1749{
1750 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1751 clear_bit(STATUS_SCANNING, &priv->status);
1752 return 0;
1753 }
1754
1755 if (test_bit(STATUS_SCANNING, &priv->status)) {
1756 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1757 IWL_DEBUG_SCAN("Queuing scan abort.\n");
1758 set_bit(STATUS_SCAN_ABORTING, &priv->status);
1759 queue_work(priv->workqueue, &priv->abort_scan);
1760
1761 } else
1762 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
1763
1764 return test_bit(STATUS_SCANNING, &priv->status);
1765 }
1766
1767 return 0;
1768}
1769
1770/**
bb8c093b 1771 * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 1772 * @ms: amount of time to wait (in milliseconds) for scan to abort
1773 *
1774 * NOTE: priv->mutex must be held before calling this function
1775 */
4a8a4322 1776static int iwl3945_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms)
b481de9c
ZY		 1777{
1778 unsigned long now = jiffies;
1779 int ret;
1780
bb8c093b 1781 ret = iwl3945_scan_cancel(priv);
b481de9c
ZY		 1782 if (ret && ms) {
1783 mutex_unlock(&priv->mutex);
1784 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
1785 test_bit(STATUS_SCANNING, &priv->status))
1786 msleep(1);
1787 mutex_lock(&priv->mutex);
1788
1789 return test_bit(STATUS_SCANNING, &priv->status);
1790 }
1791
1792 return ret;
1793}
1794
b481de9c
ZY		 1795#define MAX_UCODE_BEACON_INTERVAL 1024
1796#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
1797
bb8c093b 1798static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 1799{
1800 u16 new_val = 0;
1801 u16 beacon_factor = 0;
1802
1803 beacon_factor =
1804 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
1805 / MAX_UCODE_BEACON_INTERVAL;
1806 new_val = beacon_val / beacon_factor;
1807
1808 return cpu_to_le16(new_val);
1809}
1810
4a8a4322 1811static void iwl3945_setup_rxon_timing(struct iwl_priv *priv)
b481de9c
ZY		 1812{
1813 u64 interval_tm_unit;
1814 u64 tsf, result;
1815 unsigned long flags;
1816 struct ieee80211_conf *conf = NULL;
1817 u16 beacon_int = 0;
1818
1819 conf = ieee80211_get_hw_conf(priv->hw);
1820
1821 spin_lock_irqsave(&priv->lock, flags);
28afaf91 1822 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
b481de9c
ZY		 1823 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
1824
28afaf91 1825 tsf = priv->timestamp;
b481de9c
ZY		 1826
1827 beacon_int = priv->beacon_int;
1828 spin_unlock_irqrestore(&priv->lock, flags);
1829
05c914fe 1830 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
b481de9c
ZY		 1831 if (beacon_int == 0) {
1832 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
1833 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
1834 } else {
1835 priv->rxon_timing.beacon_interval =
1836 cpu_to_le16(beacon_int);
1837 priv->rxon_timing.beacon_interval =
bb8c093b 1838 iwl3945_adjust_beacon_interval(
b481de9c
ZY		 1839 le16_to_cpu(priv->rxon_timing.beacon_interval));
1840 }
1841
1842 priv->rxon_timing.atim_window = 0;
1843 } else {
1844 priv->rxon_timing.beacon_interval =
bb8c093b 1845 iwl3945_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 1846 /* TODO: we need to get atim_window from upper stack
1847 * for now we set to 0 */
1848 priv->rxon_timing.atim_window = 0;
1849 }
1850
1851 interval_tm_unit =
1852 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
1853 result = do_div(tsf, interval_tm_unit);
1854 priv->rxon_timing.beacon_init_val =
1855 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
1856
1857 IWL_DEBUG_ASSOC
1858 ("beacon interval %d beacon timer %d beacon tim %d\n",
1859 le16_to_cpu(priv->rxon_timing.beacon_interval),
1860 le32_to_cpu(priv->rxon_timing.beacon_init_val),
1861 le16_to_cpu(priv->rxon_timing.atim_window));
1862}
1863
4a8a4322 1864static int iwl3945_scan_initiate(struct iwl_priv *priv)
b481de9c 1865{
775a6e27 1866 if (!iwl_is_ready_rf(priv)) {
b481de9c
ZY		 1867 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
1868 return -EIO;
1869 }
1870
1871 if (test_bit(STATUS_SCANNING, &priv->status)) {
1872 IWL_DEBUG_SCAN("Scan already in progress.\n");
1873 return -EAGAIN;
1874 }
1875
1876 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1877 IWL_DEBUG_SCAN("Scan request while abort pending. "
1878 "Queuing.\n");
1879 return -EAGAIN;
1880 }
1881
1882 IWL_DEBUG_INFO("Starting scan...\n");
66b5004d
RR		 1883 if (priv->cfg->sku & IWL_SKU_G)
1884 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
1885 if (priv->cfg->sku & IWL_SKU_A)
1886 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 1887 set_bit(STATUS_SCANNING, &priv->status);
1888 priv->scan_start = jiffies;
1889 priv->scan_pass_start = priv->scan_start;
1890
1891 queue_work(priv->workqueue, &priv->request_scan);
1892
1893 return 0;
1894}
1895
4a8a4322 1896static int iwl3945_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
b481de9c 1897{
f2c7e521 1898 struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
b481de9c
ZY		 1899
1900 if (hw_decrypt)
1901 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
1902 else
1903 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
1904
1905 return 0;
1906}
1907
4a8a4322 1908static void iwl3945_set_flags_for_phymode(struct iwl_priv *priv,
8318d78a 1909 enum ieee80211_band band)
b481de9c 1910{
8318d78a 1911 if (band == IEEE80211_BAND_5GHZ) {
f2c7e521 1912 priv->staging39_rxon.flags &=
b481de9c
ZY		 1913 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1914 | RXON_FLG_CCK_MSK);
f2c7e521 1915 priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 1916 } else {
bb8c093b 1917 /* Copied from iwl3945_bg_post_associate() */
b481de9c 1918 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
f2c7e521 1919 priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 1920 else
f2c7e521 1921 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 1922
05c914fe 1923 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
f2c7e521 1924 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 1925
f2c7e521
AK		 1926 priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1927 priv->staging39_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1928 priv->staging39_rxon.flags &= ~RXON_FLG_CCK_MSK;
b481de9c
ZY		 1929 }
1930}
1931
1932/*
01ebd063 1933 * initialize rxon structure with default values from eeprom
b481de9c 1934 */
4a8a4322 1935static void iwl3945_connection_init_rx_config(struct iwl_priv *priv,
60294de3 1936 int mode)
b481de9c 1937{
d20b3c65 1938 const struct iwl_channel_info *ch_info;
b481de9c 1939
f2c7e521 1940 memset(&priv->staging39_rxon, 0, sizeof(priv->staging39_rxon));
b481de9c 1941
60294de3 1942 switch (mode) {
05c914fe 1943 case NL80211_IFTYPE_AP:
f2c7e521 1944 priv->staging39_rxon.dev_type = RXON_DEV_TYPE_AP;
b481de9c
ZY		 1945 break;
1946
05c914fe 1947 case NL80211_IFTYPE_STATION:
f2c7e521
AK		 1948 priv->staging39_rxon.dev_type = RXON_DEV_TYPE_ESS;
1949 priv->staging39_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
b481de9c
ZY		 1950 break;
1951
05c914fe 1952 case NL80211_IFTYPE_ADHOC:
f2c7e521
AK		 1953 priv->staging39_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1954 priv->staging39_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1955 priv->staging39_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
b481de9c
ZY		 1956 RXON_FILTER_ACCEPT_GRP_MSK;
1957 break;
1958
05c914fe 1959 case NL80211_IFTYPE_MONITOR:
f2c7e521
AK		 1960 priv->staging39_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
1961 priv->staging39_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
b481de9c
ZY		 1962 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
1963 break;
69dc5d9d 1964 default:
15b1687c 1965 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
69dc5d9d 1966 break;
b481de9c
ZY		 1967 }
1968
1969#if 0
1970 /* TODO: Figure out when short_preamble would be set and cache from
1971 * that */
1972 if (!hw_to_local(priv->hw)->short_preamble)
f2c7e521 1973 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 1974 else
f2c7e521 1975 priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c
ZY		 1976#endif
1977
8318d78a 1978 ch_info = iwl3945_get_channel_info(priv, priv->band,
f2c7e521 1979 le16_to_cpu(priv->active39_rxon.channel));
b481de9c
ZY		 1980
1981 if (!ch_info)
1982 ch_info = &priv->channel_info[0];
1983
1984 /*
1985 * in some case A channels are all non IBSS
1986 * in this case force B/G channel
1987 */
60294de3 1988 if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
b481de9c
ZY		 1989 ch_info = &priv->channel_info[0];
1990
f2c7e521 1991 priv->staging39_rxon.channel = cpu_to_le16(ch_info->channel);
b481de9c 1992 if (is_channel_a_band(ch_info))
8318d78a 1993 priv->band = IEEE80211_BAND_5GHZ;
b481de9c 1994 else
8318d78a 1995 priv->band = IEEE80211_BAND_2GHZ;
b481de9c 1996
8318d78a 1997 iwl3945_set_flags_for_phymode(priv, priv->band);
b481de9c 1998
f2c7e521 1999 priv->staging39_rxon.ofdm_basic_rates =
b481de9c 2000 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
f2c7e521 2001 priv->staging39_rxon.cck_basic_rates =
b481de9c
ZY		 2002 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2003}
2004
4a8a4322 2005static int iwl3945_set_mode(struct iwl_priv *priv, int mode)
b481de9c 2006{
05c914fe 2007 if (mode == NL80211_IFTYPE_ADHOC) {
d20b3c65 2008 const struct iwl_channel_info *ch_info;
b481de9c 2009
bb8c093b 2010 ch_info = iwl3945_get_channel_info(priv,
8318d78a 2011 priv->band,
f2c7e521 2012 le16_to_cpu(priv->staging39_rxon.channel));
b481de9c
ZY		 2013
2014 if (!ch_info || !is_channel_ibss(ch_info)) {
15b1687c 2015 IWL_ERR(priv, "channel %d not IBSS channel\n",
f2c7e521 2016 le16_to_cpu(priv->staging39_rxon.channel));
b481de9c
ZY		 2017 return -EINVAL;
2018 }
2019 }
2020
60294de3 2021 iwl3945_connection_init_rx_config(priv, mode);
f2c7e521 2022 memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
b481de9c 2023
bb8c093b 2024 iwl3945_clear_stations_table(priv);
b481de9c 2025
a96a27f9 2026 /* don't commit rxon if rf-kill is on*/
775a6e27 2027 if (!iwl_is_ready_rf(priv))
fde3571f
MA		 2028 return -EAGAIN;
2029
2030 cancel_delayed_work(&priv->scan_check);
2031 if (iwl3945_scan_cancel_timeout(priv, 100)) {
39aadf8c 2032 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
fde3571f
MA		 2033 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2034 return -EAGAIN;
2035 }
2036
bb8c093b 2037 iwl3945_commit_rxon(priv);
b481de9c
ZY		 2038
2039 return 0;
2040}
2041
4a8a4322 2042static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
e039fa4a 2043 struct ieee80211_tx_info *info,
c2d79b48 2044 struct iwl_cmd *cmd,
b481de9c
ZY		 2045 struct sk_buff *skb_frag,
2046 int last_frag)
2047{
e52119c5 2048 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
1c014420 2049 struct iwl3945_hw_key *keyinfo =
f2c7e521 2050 &priv->stations_39[info->control.hw_key->hw_key_idx].keyinfo;
b481de9c
ZY		 2051
2052 switch (keyinfo->alg) {
2053 case ALG_CCMP:
e52119c5
WT		 2054 tx->sec_ctl = TX_CMD_SEC_CCM;
2055 memcpy(tx->key, keyinfo->key, keyinfo->keylen);
a96a27f9 2056 IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
b481de9c
ZY		 2057 break;
2058
2059 case ALG_TKIP:
2060#if 0
e52119c5 2061 tx->sec_ctl = TX_CMD_SEC_TKIP;
b481de9c
ZY		 2062
2063 if (last_frag)
e52119c5 2064 memcpy(tx->tkip_mic.byte, skb_frag->tail - 8,
b481de9c
ZY		 2065 8);
2066 else
e52119c5 2067 memset(tx->tkip_mic.byte, 0, 8);
b481de9c
ZY		 2068#endif
2069 break;
2070
2071 case ALG_WEP:
e52119c5 2072 tx->sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 2073 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY		 2074
2075 if (keyinfo->keylen == 13)
e52119c5 2076 tx->sec_ctl |= TX_CMD_SEC_KEY128;
b481de9c 2077
e52119c5 2078 memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen);
b481de9c
ZY		 2079
2080 IWL_DEBUG_TX("Configuring packet for WEP encryption "
e039fa4a 2081 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY		 2082 break;
2083
b481de9c 2084 default:
978785a3 2085 IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
b481de9c
ZY		 2086 break;
2087 }
2088}
2089
2090/*
2091 * handle build REPLY_TX command notification.
2092 */
4a8a4322 2093static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
c2d79b48 2094 struct iwl_cmd *cmd,
e039fa4a 2095 struct ieee80211_tx_info *info,
e52119c5 2096 struct ieee80211_hdr *hdr, u8 std_id)
b481de9c 2097{
e52119c5
WT		 2098 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
2099 __le32 tx_flags = tx->tx_flags;
fd7c8a40 2100 __le16 fc = hdr->frame_control;
e6a9854b 2101 u8 rc_flags = info->control.rates[0].flags;
b481de9c 2102
e52119c5 2103 tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 2104 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 2105 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 2106 if (ieee80211_is_mgmt(fc))
b481de9c 2107 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 2108 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY		 2109 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2110 tx_flags |= TX_CMD_FLG_TSF_MSK;
2111 } else {
2112 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2113 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2114 }
2115
e52119c5 2116 tx->sta_id = std_id;
8b7b1e05 2117 if (ieee80211_has_morefrags(fc))
b481de9c
ZY		 2118 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2119
fd7c8a40
HH		 2120 if (ieee80211_is_data_qos(fc)) {
2121 u8 *qc = ieee80211_get_qos_ctl(hdr);
e52119c5 2122 tx->tid_tspec = qc[0] & 0xf;
b481de9c 2123 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2124 } else {
b481de9c 2125 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 2126 }
b481de9c 2127
e6a9854b 2128 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
b481de9c
ZY		 2129 tx_flags |= TX_CMD_FLG_RTS_MSK;
2130 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 2131 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
b481de9c
ZY		 2132 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2133 tx_flags |= TX_CMD_FLG_CTS_MSK;
2134 }
2135
2136 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2137 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2138
2139 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH		 2140 if (ieee80211_is_mgmt(fc)) {
2141 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
e52119c5 2142 tx->timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2143 else
e52119c5 2144 tx->timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2145 } else {
e52119c5 2146 tx->timeout.pm_frame_timeout = 0;
ab53d8af
MA		 2147#ifdef CONFIG_IWL3945_LEDS
2148 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2149#endif
2150 }
b481de9c 2151
e52119c5
WT		 2152 tx->driver_txop = 0;
2153 tx->tx_flags = tx_flags;
2154 tx->next_frame_len = 0;
b481de9c
ZY		 2155}
2156
6440adb5
CB		 2157/**
2158 * iwl3945_get_sta_id - Find station's index within station table
2159 */
4a8a4322 2160static int iwl3945_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
b481de9c
ZY		 2161{
2162 int sta_id;
2163 u16 fc = le16_to_cpu(hdr->frame_control);
2164
6440adb5 2165 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2166 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2167 is_multicast_ether_addr(hdr->addr1))
3832ec9d 2168 return priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2169
2170 switch (priv->iw_mode) {
2171
6440adb5
CB		 2172 /* If we are a client station in a BSS network, use the special
2173 * AP station entry (that's the only station we communicate with) */
05c914fe 2174 case NL80211_IFTYPE_STATION:
b481de9c
ZY		 2175 return IWL_AP_ID;
2176
2177 /* If we are an AP, then find the station, or use BCAST */
05c914fe 2178 case NL80211_IFTYPE_AP:
bb8c093b 2179 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2180 if (sta_id != IWL_INVALID_STATION)
2181 return sta_id;
3832ec9d 2182 return priv->hw_params.bcast_sta_id;
b481de9c 2183
6440adb5
CB		 2184 /* If this frame is going out to an IBSS network, find the station,
2185 * or create a new station table entry */
05c914fe 2186 case NL80211_IFTYPE_ADHOC: {
6440adb5 2187 /* Create new station table entry */
bb8c093b 2188 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2189 if (sta_id != IWL_INVALID_STATION)
2190 return sta_id;
2191
bb8c093b 2192 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
b481de9c
ZY		 2193
2194 if (sta_id != IWL_INVALID_STATION)
2195 return sta_id;
2196
e174961c 2197 IWL_DEBUG_DROP("Station %pM not in station map. "
b481de9c 2198 "Defaulting to broadcast...\n",
e174961c 2199 hdr->addr1);
40b8ec0b 2200 iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
3832ec9d 2201 return priv->hw_params.bcast_sta_id;
0795af57 2202 }
914233d6
SG		 2203 /* If we are in monitor mode, use BCAST. This is required for
2204 * packet injection. */
05c914fe 2205 case NL80211_IFTYPE_MONITOR:
3832ec9d 2206 return priv->hw_params.bcast_sta_id;
914233d6 2207
b481de9c 2208 default:
39aadf8c
WT		 2209 IWL_WARN(priv, "Unknown mode of operation: %d\n",
2210 priv->iw_mode);
3832ec9d 2211 return priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2212 }
2213}
2214
2215/*
2216 * start REPLY_TX command process
2217 */
4a8a4322 2218static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
b481de9c
ZY		 2219{
2220 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 2221 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
dbb6654c 2222 struct iwl3945_tfd *tfd;
e52119c5 2223 struct iwl3945_tx_cmd *tx;
188cf6c7 2224 struct iwl_tx_queue *txq = NULL;
d20b3c65 2225 struct iwl_queue *q = NULL;
e52119c5 2226 struct iwl_cmd *out_cmd = NULL;
b481de9c
ZY		 2227 dma_addr_t phys_addr;
2228 dma_addr_t txcmd_phys;
e52119c5 2229 int txq_id = skb_get_queue_mapping(skb);
54dbb525
TW		 2230 u16 len, idx, len_org, hdr_len;
2231 u8 id;
2232 u8 unicast;
b481de9c 2233 u8 sta_id;
54dbb525 2234 u8 tid = 0;
b481de9c 2235 u16 seq_number = 0;
fd7c8a40 2236 __le16 fc;
b481de9c 2237 u8 wait_write_ptr = 0;
54dbb525 2238 u8 *qc = NULL;
b481de9c
ZY		 2239 unsigned long flags;
2240 int rc;
2241
2242 spin_lock_irqsave(&priv->lock, flags);
775a6e27 2243 if (iwl_is_rfkill(priv)) {
b481de9c
ZY		 2244 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2245 goto drop_unlock;
2246 }
2247
e039fa4a 2248 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
15b1687c 2249 IWL_ERR(priv, "ERROR: No TX rate available.\n");
b481de9c
ZY		 2250 goto drop_unlock;
2251 }
2252
2253 unicast = !is_multicast_ether_addr(hdr->addr1);
2254 id = 0;
2255
fd7c8a40 2256 fc = hdr->frame_control;
b481de9c 2257
c8b0e6e1 2258#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 2259 if (ieee80211_is_auth(fc))
2260 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 2261 else if (ieee80211_is_assoc_req(fc))
b481de9c 2262 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 2263 else if (ieee80211_is_reassoc_req(fc))
b481de9c
ZY		 2264 IWL_DEBUG_TX("Sending REASSOC frame\n");
2265#endif
2266
7878a5a4 2267 /* drop all data frame if we are not associated */
914233d6 2268 if (ieee80211_is_data(fc) &&
05c914fe 2269 (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
914233d6 2270 (!iwl3945_is_associated(priv) ||
05c914fe 2271 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
bb8c093b 2272 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
b481de9c
ZY		 2273 goto drop_unlock;
2274 }
2275
2276 spin_unlock_irqrestore(&priv->lock, flags);
2277
7294ec95 2278 hdr_len = ieee80211_hdrlen(fc);
6440adb5
CB		 2279
2280 /* Find (or create) index into station table for destination station */
bb8c093b 2281 sta_id = iwl3945_get_sta_id(priv, hdr);
b481de9c 2282 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 2283 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
2284 hdr->addr1);
b481de9c
ZY		 2285 goto drop;
2286 }
2287
2288 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2289
fd7c8a40
HH		 2290 if (ieee80211_is_data_qos(fc)) {
2291 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 2292 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
f2c7e521 2293 seq_number = priv->stations_39[sta_id].tid[tid].seq_number &
b481de9c
ZY		 2294 IEEE80211_SCTL_SEQ;
2295 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2296 (hdr->seq_ctrl &
2297 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2298 seq_number += 0x10;
2299 }
6440adb5
CB		 2300
2301 /* Descriptor for chosen Tx queue */
188cf6c7 2302 txq = &priv->txq[txq_id];
b481de9c
ZY		 2303 q = &txq->q;
2304
2305 spin_lock_irqsave(&priv->lock, flags);
2306
6440adb5 2307 /* Set up first empty TFD within this queue's circular TFD buffer */
188cf6c7 2308 tfd = &txq->tfds39[q->write_ptr];
b481de9c 2309 memset(tfd, 0, sizeof(*tfd));
fc4b6853 2310 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2311
6440adb5 2312 /* Set up driver data for this TFD */
dbb6654c 2313 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
fc4b6853 2314 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB		 2315
2316 /* Init first empty entry in queue's array of Tx/cmd buffers */
188cf6c7 2317 out_cmd = txq->cmd[idx];
e52119c5 2318 tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
b481de9c 2319 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
e52119c5 2320 memset(tx, 0, sizeof(*tx));
6440adb5
CB		 2321
2322 /*
2323 * Set up the Tx-command (not MAC!) header.
2324 * Store the chosen Tx queue and TFD index within the sequence field;
2325 * after Tx, uCode's Tx response will return this value so driver can
2326 * locate the frame within the tx queue and do post-tx processing.
2327 */
b481de9c
ZY		 2328 out_cmd->hdr.cmd = REPLY_TX;
2329 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2330 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB		 2331
2332 /* Copy MAC header from skb into command buffer */
e52119c5 2333 memcpy(tx->hdr, hdr, hdr_len);
b481de9c 2334
6440adb5
CB		 2335 /*
2336 * Use the first empty entry in this queue's command buffer array
2337 * to contain the Tx command and MAC header concatenated together
2338 * (payload data will be in another buffer).
2339 * Size of this varies, due to varying MAC header length.
2340 * If end is not dword aligned, we'll have 2 extra bytes at the end
2341 * of the MAC header (device reads on dword boundaries).
2342 * We'll tell device about this padding later.
2343 */
3832ec9d 2344 len = sizeof(struct iwl3945_tx_cmd) +
4c897253 2345 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY		 2346
2347 len_org = len;
2348 len = (len + 3) & ~3;
2349
2350 if (len_org != len)
2351 len_org = 1;
2352 else
2353 len_org = 0;
2354
6440adb5
CB		 2355 /* Physical address of this Tx command's header (not MAC header!),
2356 * within command buffer array. */
188cf6c7
SO		 2357 txcmd_phys = pci_map_single(priv->pci_dev,
2358 out_cmd, sizeof(struct iwl_cmd),
2359 PCI_DMA_TODEVICE);
2360 pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
2361 pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
2362 /* Add buffer containing Tx command and MAC(!) header to TFD's
2363 * first entry */
2364 txcmd_phys += offsetof(struct iwl_cmd, hdr);
b481de9c 2365
6440adb5
CB		 2366 /* Add buffer containing Tx command and MAC(!) header to TFD's
2367 * first entry */
bb8c093b 2368 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c 2369
d0f09804 2370 if (info->control.hw_key)
e039fa4a 2371 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
b481de9c 2372
6440adb5
CB		 2373 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2374 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 2375 len = skb->len - hdr_len;
2376 if (len) {
2377 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2378 len, PCI_DMA_TODEVICE);
bb8c093b 2379 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 2380 }
2381
b481de9c 2382 if (!len)
6440adb5 2383 /* If there is no payload, then we use only one Tx buffer */
dbb6654c 2384 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(1));
b481de9c 2385 else
6440adb5
CB		 2386 /* Else use 2 buffers.
2387 * Tell 3945 about any padding after MAC header */
dbb6654c
WT		 2388 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(2) |
2389 TFD_CTL_PAD_SET(U32_PAD(len)));
b481de9c 2390
6440adb5 2391 /* Total # bytes to be transmitted */
b481de9c 2392 len = (u16)skb->len;
e52119c5 2393 tx->len = cpu_to_le16(len);
b481de9c
ZY		 2394
2395 /* TODO need this for burst mode later on */
e52119c5 2396 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
b481de9c
ZY		 2397
2398 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 2399 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
b481de9c 2400
e52119c5
WT		 2401 tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2402 tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
b481de9c 2403
8b7b1e05 2404 if (!ieee80211_has_morefrags(hdr->frame_control)) {
b481de9c 2405 txq->need_update = 1;
3ac7f146 2406 if (qc)
f2c7e521 2407 priv->stations_39[sta_id].tid[tid].seq_number = seq_number;
b481de9c
ZY		 2408 } else {
2409 wait_write_ptr = 1;
2410 txq->need_update = 0;
2411 }
2412
e52119c5 2413 iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx));
b481de9c 2414
e52119c5 2415 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr,
7294ec95 2416 ieee80211_hdrlen(fc));
b481de9c 2417
6440adb5 2418 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2419 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2420 rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2421 spin_unlock_irqrestore(&priv->lock, flags);
2422
2423 if (rc)
2424 return rc;
2425
d20b3c65 2426 if ((iwl_queue_space(q) < q->high_mark)
b481de9c
ZY		 2427 && priv->mac80211_registered) {
2428 if (wait_write_ptr) {
2429 spin_lock_irqsave(&priv->lock, flags);
2430 txq->need_update = 1;
bb8c093b 2431 iwl3945_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2432 spin_unlock_irqrestore(&priv->lock, flags);
2433 }
2434
e2530083 2435 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
b481de9c
ZY		 2436 }
2437
2438 return 0;
2439
2440drop_unlock:
2441 spin_unlock_irqrestore(&priv->lock, flags);
2442drop:
2443 return -1;
2444}
2445
4a8a4322 2446static void iwl3945_set_rate(struct iwl_priv *priv)
b481de9c 2447{
8318d78a 2448 const struct ieee80211_supported_band *sband = NULL;
b481de9c
ZY		 2449 struct ieee80211_rate *rate;
2450 int i;
2451
cbba18c6 2452 sband = iwl_get_hw_mode(priv, priv->band);
8318d78a 2453 if (!sband) {
15b1687c 2454 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
c4ba9621
SA		 2455 return;
2456 }
b481de9c
ZY		 2457
2458 priv->active_rate = 0;
2459 priv->active_rate_basic = 0;
2460
8318d78a
JB		 2461 IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2462 sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2463
2464 for (i = 0; i < sband->n_bitrates; i++) {
2465 rate = &sband->bitrates[i];
2466 if ((rate->hw_value < IWL_RATE_COUNT) &&
2467 !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2468 IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2469 rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2470 priv->active_rate |= (1 << rate->hw_value);
2471 }
b481de9c
ZY		 2472 }
2473
2474 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2475 priv->active_rate, priv->active_rate_basic);
2476
2477 /*
2478 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2479 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2480 * OFDM
2481 */
2482 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
f2c7e521 2483 priv->staging39_rxon.cck_basic_rates =
b481de9c
ZY		 2484 ((priv->active_rate_basic &
2485 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2486 else
f2c7e521 2487 priv->staging39_rxon.cck_basic_rates =
b481de9c
ZY		 2488 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2489
2490 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
f2c7e521 2491 priv->staging39_rxon.ofdm_basic_rates =
b481de9c
ZY		 2492 ((priv->active_rate_basic &
2493 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2494 IWL_FIRST_OFDM_RATE) & 0xFF;
2495 else
f2c7e521 2496 priv->staging39_rxon.ofdm_basic_rates =
b481de9c
ZY		 2497 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2498}
2499
4a8a4322 2500static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
b481de9c
ZY		 2501{
2502 unsigned long flags;
2503
2504 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2505 return;
2506
2507 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2508 disable_radio ? "OFF" : "ON");
2509
2510 if (disable_radio) {
bb8c093b 2511 iwl3945_scan_cancel(priv);
b481de9c 2512 /* FIXME: This is a workaround for AP */
05c914fe 2513 if (priv->iw_mode != NL80211_IFTYPE_AP) {
b481de9c 2514 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2515 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 2516 CSR_UCODE_SW_BIT_RFKILL);
2517 spin_unlock_irqrestore(&priv->lock, flags);
c496294e 2518 iwl_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
b481de9c
ZY		 2519 set_bit(STATUS_RF_KILL_SW, &priv->status);
2520 }
2521 return;
2522 }
2523
2524 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2525 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2526
2527 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2528 spin_unlock_irqrestore(&priv->lock, flags);
2529
2530 /* wake up ucode */
2531 msleep(10);
2532
2533 spin_lock_irqsave(&priv->lock, flags);
5d49f498
AK		 2534 iwl_read32(priv, CSR_UCODE_DRV_GP1);
2535 if (!iwl_grab_nic_access(priv))
2536 iwl_release_nic_access(priv);
b481de9c
ZY		 2537 spin_unlock_irqrestore(&priv->lock, flags);
2538
2539 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2540 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2541 "disabled by HW switch\n");
2542 return;
2543 }
2544
808e72a0
ZY		 2545 if (priv->is_open)
2546 queue_work(priv->workqueue, &priv->restart);
b481de9c
ZY		 2547 return;
2548}
2549
4a8a4322 2550void iwl3945_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 2551 u32 decrypt_res, struct ieee80211_rx_status *stats)
2552{
2553 u16 fc =
2554 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2555
f2c7e521 2556 if (priv->active39_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
b481de9c
ZY		 2557 return;
2558
2559 if (!(fc & IEEE80211_FCTL_PROTECTED))
2560 return;
2561
2562 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2563 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2564 case RX_RES_STATUS_SEC_TYPE_TKIP:
2565 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2566 RX_RES_STATUS_BAD_ICV_MIC)
2567 stats->flag |= RX_FLAG_MMIC_ERROR;
2568 case RX_RES_STATUS_SEC_TYPE_WEP:
2569 case RX_RES_STATUS_SEC_TYPE_CCMP:
2570 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2571 RX_RES_STATUS_DECRYPT_OK) {
2572 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2573 stats->flag |= RX_FLAG_DECRYPTED;
2574 }
2575 break;
2576
2577 default:
2578 break;
2579 }
2580}
2581
c8b0e6e1 2582#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 2583
2584#include "iwl-spectrum.h"
2585
2586#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2587#define BEACON_TIME_MASK_HIGH 0xFF000000
2588#define TIME_UNIT 1024
2589
2590/*
2591 * extended beacon time format
2592 * time in usec will be changed into a 32-bit value in 8:24 format
2593 * the high 1 byte is the beacon counts
2594 * the lower 3 bytes is the time in usec within one beacon interval
2595 */
2596
bb8c093b 2597static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 2598{
2599 u32 quot;
2600 u32 rem;
2601 u32 interval = beacon_interval * 1024;
2602
2603 if (!interval || !usec)
2604 return 0;
2605
2606 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
2607 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
2608
2609 return (quot << 24) + rem;
2610}
2611
2612/* base is usually what we get from ucode with each received frame,
2613 * the same as HW timer counter counting down
2614 */
2615
bb8c093b 2616static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 2617{
2618 u32 base_low = base & BEACON_TIME_MASK_LOW;
2619 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
2620 u32 interval = beacon_interval * TIME_UNIT;
2621 u32 res = (base & BEACON_TIME_MASK_HIGH) +
2622 (addon & BEACON_TIME_MASK_HIGH);
2623
2624 if (base_low > addon_low)
2625 res += base_low - addon_low;
2626 else if (base_low < addon_low) {
2627 res += interval + base_low - addon_low;
2628 res += (1 << 24);
2629 } else
2630 res += (1 << 24);
2631
2632 return cpu_to_le32(res);
2633}
2634
4a8a4322 2635static int iwl3945_get_measurement(struct iwl_priv *priv,
b481de9c
ZY		 2636 struct ieee80211_measurement_params *params,
2637 u8 type)
2638{
600c0e11 2639 struct iwl_spectrum_cmd spectrum;
3d24a9f7 2640 struct iwl_rx_packet *res;
c2d79b48 2641 struct iwl_host_cmd cmd = {
b481de9c
ZY		 2642 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
2643 .data = (void *)&spectrum,
2644 .meta.flags = CMD_WANT_SKB,
2645 };
2646 u32 add_time = le64_to_cpu(params->start_time);
2647 int rc;
2648 int spectrum_resp_status;
2649 int duration = le16_to_cpu(params->duration);
2650
bb8c093b 2651 if (iwl3945_is_associated(priv))
b481de9c 2652 add_time =
bb8c093b 2653 iwl3945_usecs_to_beacons(
b481de9c
ZY		 2654 le64_to_cpu(params->start_time) - priv->last_tsf,
2655 le16_to_cpu(priv->rxon_timing.beacon_interval));
2656
2657 memset(&spectrum, 0, sizeof(spectrum));
2658
2659 spectrum.channel_count = cpu_to_le16(1);
2660 spectrum.flags =
2661 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
2662 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
2663 cmd.len = sizeof(spectrum);
2664 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
2665
bb8c093b 2666 if (iwl3945_is_associated(priv))
b481de9c 2667 spectrum.start_time =
bb8c093b 2668 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 2669 add_time,
2670 le16_to_cpu(priv->rxon_timing.beacon_interval));
2671 else
2672 spectrum.start_time = 0;
2673
2674 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
2675 spectrum.channels[0].channel = params->channel;
2676 spectrum.channels[0].type = type;
f2c7e521 2677 if (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK)
b481de9c
ZY		 2678 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
2679 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
2680
bb8c093b 2681 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 2682 if (rc)
2683 return rc;
2684
3d24a9f7 2685 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
b481de9c 2686 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 2687 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
b481de9c
ZY		 2688 rc = -EIO;
2689 }
2690
2691 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
2692 switch (spectrum_resp_status) {
2693 case 0: /* Command will be handled */
2694 if (res->u.spectrum.id != 0xff) {
bc434dd2
IS		 2695 IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
2696 res->u.spectrum.id);
b481de9c
ZY		 2697 priv->measurement_status &= ~MEASUREMENT_READY;
2698 }
2699 priv->measurement_status |= MEASUREMENT_ACTIVE;
2700 rc = 0;
2701 break;
2702
2703 case 1: /* Command will not be handled */
2704 rc = -EAGAIN;
2705 break;
2706 }
2707
2708 dev_kfree_skb_any(cmd.meta.u.skb);
2709
2710 return rc;
2711}
2712#endif
2713
4a8a4322 2714static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
6100b588 2715 struct iwl_rx_mem_buffer *rxb)
b481de9c 2716{
3d24a9f7
TW		 2717 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
2718 struct iwl_alive_resp *palive;
b481de9c
ZY		 2719 struct delayed_work *pwork;
2720
2721 palive = &pkt->u.alive_frame;
2722
2723 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
2724 "0x%01X 0x%01X\n",
2725 palive->is_valid, palive->ver_type,
2726 palive->ver_subtype);
2727
2728 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
2729 IWL_DEBUG_INFO("Initialization Alive received.\n");
3d24a9f7
TW		 2730 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
2731 sizeof(struct iwl_alive_resp));
b481de9c
ZY		 2732 pwork = &priv->init_alive_start;
2733 } else {
2734 IWL_DEBUG_INFO("Runtime Alive received.\n");
2735 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 2736 sizeof(struct iwl_alive_resp));
b481de9c 2737 pwork = &priv->alive_start;
bb8c093b 2738 iwl3945_disable_events(priv);
b481de9c
ZY		 2739 }
2740
2741 /* We delay the ALIVE response by 5ms to
2742 * give the HW RF Kill time to activate... */
2743 if (palive->is_valid == UCODE_VALID_OK)
2744 queue_delayed_work(priv->workqueue, pwork,
2745 msecs_to_jiffies(5));
2746 else
39aadf8c 2747 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY		 2748}
2749
4a8a4322 2750static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
6100b588 2751 struct iwl_rx_mem_buffer *rxb)
b481de9c 2752{
3d24a9f7 2753 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 2754
2755 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
2756 return;
2757}
2758
4a8a4322 2759static void iwl3945_rx_reply_error(struct iwl_priv *priv,
6100b588 2760 struct iwl_rx_mem_buffer *rxb)
b481de9c 2761{
3d24a9f7 2762 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 2763
15b1687c 2764 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
b481de9c
ZY		 2765 "seq 0x%04X ser 0x%08X\n",
2766 le32_to_cpu(pkt->u.err_resp.error_type),
2767 get_cmd_string(pkt->u.err_resp.cmd_id),
2768 pkt->u.err_resp.cmd_id,
2769 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2770 le32_to_cpu(pkt->u.err_resp.error_info));
2771}
2772
2773#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
2774
4a8a4322 2775static void iwl3945_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
b481de9c 2776{
3d24a9f7 2777 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
f2c7e521 2778 struct iwl3945_rxon_cmd *rxon = (void *)&priv->active39_rxon;
600c0e11 2779 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 2780 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
2781 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
2782 rxon->channel = csa->channel;
f2c7e521 2783 priv->staging39_rxon.channel = csa->channel;
b481de9c
ZY		 2784}
2785
4a8a4322 2786static void iwl3945_rx_spectrum_measure_notif(struct iwl_priv *priv,
6100b588 2787 struct iwl_rx_mem_buffer *rxb)
b481de9c 2788{
c8b0e6e1 2789#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
3d24a9f7 2790 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
600c0e11 2791 struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 2792
2793 if (!report->state) {
2794 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
2795 "Spectrum Measure Notification: Start\n");
2796 return;
2797 }
2798
2799 memcpy(&priv->measure_report, report, sizeof(*report));
2800 priv->measurement_status |= MEASUREMENT_READY;
2801#endif
2802}
2803
4a8a4322 2804static void iwl3945_rx_pm_sleep_notif(struct iwl_priv *priv,
6100b588 2805 struct iwl_rx_mem_buffer *rxb)
b481de9c 2806{
c8b0e6e1 2807#ifdef CONFIG_IWL3945_DEBUG
3d24a9f7 2808 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
600c0e11 2809 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 2810 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
2811 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2812#endif
2813}
2814
4a8a4322 2815static void iwl3945_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
6100b588 2816 struct iwl_rx_mem_buffer *rxb)
b481de9c 2817{
3d24a9f7 2818 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 2819 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
2820 "notification for %s:\n",
2821 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
40b8ec0b
SO		 2822 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw,
2823 le32_to_cpu(pkt->len));
b481de9c
ZY		 2824}
2825
bb8c093b 2826static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 2827{
4a8a4322
AK		 2828 struct iwl_priv *priv =
2829 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 2830 struct sk_buff *beacon;
2831
2832 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 2833 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 2834
2835 if (!beacon) {
15b1687c 2836 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY		 2837 return;
2838 }
2839
2840 mutex_lock(&priv->mutex);
2841 /* new beacon skb is allocated every time; dispose previous.*/
2842 if (priv->ibss_beacon)
2843 dev_kfree_skb(priv->ibss_beacon);
2844
2845 priv->ibss_beacon = beacon;
2846 mutex_unlock(&priv->mutex);
2847
bb8c093b 2848 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 2849}
2850
4a8a4322 2851static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
6100b588 2852 struct iwl_rx_mem_buffer *rxb)
b481de9c 2853{
c8b0e6e1 2854#ifdef CONFIG_IWL3945_DEBUG
3d24a9f7 2855 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b 2856 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY		 2857 u8 rate = beacon->beacon_notify_hdr.rate;
2858
2859 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
2860 "tsf %d %d rate %d\n",
2861 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
2862 beacon->beacon_notify_hdr.failure_frame,
2863 le32_to_cpu(beacon->ibss_mgr_status),
2864 le32_to_cpu(beacon->high_tsf),
2865 le32_to_cpu(beacon->low_tsf), rate);
2866#endif
2867
05c914fe 2868 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY		 2869 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
2870 queue_work(priv->workqueue, &priv->beacon_update);
2871}
2872
2873/* Service response to REPLY_SCAN_CMD (0x80) */
4a8a4322 2874static void iwl3945_rx_reply_scan(struct iwl_priv *priv,
6100b588 2875 struct iwl_rx_mem_buffer *rxb)
b481de9c 2876{
c8b0e6e1 2877#ifdef CONFIG_IWL3945_DEBUG
3d24a9f7 2878 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253
TW		 2879 struct iwl_scanreq_notification *notif =
2880 (struct iwl_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 2881
2882 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
2883#endif
2884}
2885
2886/* Service SCAN_START_NOTIFICATION (0x82) */
4a8a4322 2887static void iwl3945_rx_scan_start_notif(struct iwl_priv *priv,
6100b588 2888 struct iwl_rx_mem_buffer *rxb)
b481de9c 2889{
3d24a9f7 2890 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253
TW		 2891 struct iwl_scanstart_notification *notif =
2892 (struct iwl_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 2893 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
2894 IWL_DEBUG_SCAN("Scan start: "
2895 "%d [802.11%s] "
2896 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
2897 notif->channel,
2898 notif->band ? "bg" : "a",
2899 notif->tsf_high,
2900 notif->tsf_low, notif->status, notif->beacon_timer);
2901}
2902
2903/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
4a8a4322 2904static void iwl3945_rx_scan_results_notif(struct iwl_priv *priv,
6100b588 2905 struct iwl_rx_mem_buffer *rxb)
b481de9c 2906{
3d24a9f7 2907 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253
TW		 2908 struct iwl_scanresults_notification *notif =
2909 (struct iwl_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 2910
2911 IWL_DEBUG_SCAN("Scan ch.res: "
2912 "%d [802.11%s] "
2913 "(TSF: 0x%08X:%08X) - %d "
2914 "elapsed=%lu usec (%dms since last)\n",
2915 notif->channel,
2916 notif->band ? "bg" : "a",
2917 le32_to_cpu(notif->tsf_high),
2918 le32_to_cpu(notif->tsf_low),
2919 le32_to_cpu(notif->statistics[0]),
2920 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
2921 jiffies_to_msecs(elapsed_jiffies
2922 (priv->last_scan_jiffies, jiffies)));
2923
2924 priv->last_scan_jiffies = jiffies;
7878a5a4 2925 priv->next_scan_jiffies = 0;
b481de9c
ZY		 2926}
2927
2928/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
4a8a4322 2929static void iwl3945_rx_scan_complete_notif(struct iwl_priv *priv,
6100b588 2930 struct iwl_rx_mem_buffer *rxb)
b481de9c 2931{
3d24a9f7 2932 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
4c897253 2933 struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 2934
2935 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
2936 scan_notif->scanned_channels,
2937 scan_notif->tsf_low,
2938 scan_notif->tsf_high, scan_notif->status);
2939
2940 /* The HW is no longer scanning */
2941 clear_bit(STATUS_SCAN_HW, &priv->status);
2942
2943 /* The scan completion notification came in, so kill that timer... */
2944 cancel_delayed_work(&priv->scan_check);
2945
2946 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
66b5004d
RR		 2947 (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
2948 "2.4" : "5.2",
b481de9c
ZY		 2949 jiffies_to_msecs(elapsed_jiffies
2950 (priv->scan_pass_start, jiffies)));
2951
66b5004d
RR		 2952 /* Remove this scanned band from the list of pending
2953 * bands to scan, band G precedes A in order of scanning
2954 * as seen in iwl3945_bg_request_scan */
2955 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
2956 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
2957 else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
2958 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
b481de9c
ZY		 2959
2960 /* If a request to abort was given, or the scan did not succeed
2961 * then we reset the scan state machine and terminate,
2962 * re-queuing another scan if one has been requested */
2963 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2964 IWL_DEBUG_INFO("Aborted scan completed.\n");
2965 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
2966 } else {
2967 /* If there are more bands on this scan pass reschedule */
2968 if (priv->scan_bands > 0)
2969 goto reschedule;
2970 }
2971
2972 priv->last_scan_jiffies = jiffies;
7878a5a4 2973 priv->next_scan_jiffies = 0;
b481de9c
ZY		 2974 IWL_DEBUG_INFO("Setting scan to off\n");
2975
2976 clear_bit(STATUS_SCANNING, &priv->status);
2977
2978 IWL_DEBUG_INFO("Scan took %dms\n",
2979 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
2980
2981 queue_work(priv->workqueue, &priv->scan_completed);
2982
2983 return;
2984
2985reschedule:
2986 priv->scan_pass_start = jiffies;
2987 queue_work(priv->workqueue, &priv->request_scan);
2988}
2989
2990/* Handle notification from uCode that card's power state is changing
2991 * due to software, hardware, or critical temperature RFKILL */
4a8a4322 2992static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
6100b588 2993 struct iwl_rx_mem_buffer *rxb)
b481de9c 2994{
3d24a9f7 2995 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 2996 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
2997 unsigned long status = priv->status;
2998
2999 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3000 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3001 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3002
5d49f498 3003 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3004 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3005
3006 if (flags & HW_CARD_DISABLED)
3007 set_bit(STATUS_RF_KILL_HW, &priv->status);
3008 else
3009 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3010
3011
3012 if (flags & SW_CARD_DISABLED)
3013 set_bit(STATUS_RF_KILL_SW, &priv->status);
3014 else
3015 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3016
bb8c093b 3017 iwl3945_scan_cancel(priv);
b481de9c
ZY		 3018
3019 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3020 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3021 (test_bit(STATUS_RF_KILL_SW, &status) !=
3022 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3023 queue_work(priv->workqueue, &priv->rf_kill);
3024 else
3025 wake_up_interruptible(&priv->wait_command_queue);
3026}
3027
3028/**
bb8c093b 3029 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 3030 *
3031 * Setup the RX handlers for each of the reply types sent from the uCode
3032 * to the host.
3033 *
3034 * This function chains into the hardware specific files for them to setup
3035 * any hardware specific handlers as well.
3036 */
4a8a4322 3037static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 3038{
bb8c093b
CH		 3039 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3040 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3041 priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3042 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
b481de9c 3043 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 3044 iwl3945_rx_spectrum_measure_notif;
3045 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
b481de9c 3046 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 3047 iwl3945_rx_pm_debug_statistics_notif;
3048 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 3049
9fbab516
BC		 3050 /*
3051 * The same handler is used for both the REPLY to a discrete
3052 * statistics request from the host as well as for the periodic
3053 * statistics notifications (after received beacons) from the uCode.
b481de9c 3054 */
bb8c093b
CH		 3055 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3056 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 3057
bb8c093b
CH		 3058 priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3059 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
b481de9c 3060 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3061 iwl3945_rx_scan_results_notif;
b481de9c 3062 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 3063 iwl3945_rx_scan_complete_notif;
3064 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 3065
9fbab516 3066 /* Set up hardware specific Rx handlers */
bb8c093b 3067 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY		 3068}
3069
91c066f2
TW		 3070/**
3071 * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3072 * When FW advances 'R' index, all entries between old and new 'R' index
3073 * need to be reclaimed.
3074 */
4a8a4322 3075static void iwl3945_cmd_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 3076 int txq_id, int index)
3077{
188cf6c7 3078 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 3079 struct iwl_queue *q = &txq->q;
91c066f2
TW		 3080 int nfreed = 0;
3081
3082 if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
15b1687c 3083 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
91c066f2
TW		 3084 "is out of range [0-%d] %d %d.\n", txq_id,
3085 index, q->n_bd, q->write_ptr, q->read_ptr);
3086 return;
3087 }
3088
3089 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3090 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3091 if (nfreed > 1) {
15b1687c 3092 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", index,
91c066f2
TW		 3093 q->write_ptr, q->read_ptr);
3094 queue_work(priv->workqueue, &priv->restart);
3095 break;
3096 }
3097 nfreed++;
3098 }
3099}
3100
3101
b481de9c 3102/**
bb8c093b 3103 * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 3104 * @rxb: Rx buffer to reclaim
3105 *
3106 * If an Rx buffer has an async callback associated with it the callback
3107 * will be executed. The attached skb (if present) will only be freed
3108 * if the callback returns 1
3109 */
4a8a4322 3110static void iwl3945_tx_cmd_complete(struct iwl_priv *priv,
6100b588 3111 struct iwl_rx_mem_buffer *rxb)
b481de9c 3112{
3d24a9f7 3113 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3114 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3115 int txq_id = SEQ_TO_QUEUE(sequence);
3116 int index = SEQ_TO_INDEX(sequence);
600c0e11 3117 int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
b481de9c 3118 int cmd_index;
c2d79b48 3119 struct iwl_cmd *cmd;
b481de9c 3120
b481de9c
ZY		 3121 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3122
188cf6c7
SO		 3123 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3124 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
b481de9c
ZY		 3125
3126 /* Input error checking is done when commands are added to queue. */
3127 if (cmd->meta.flags & CMD_WANT_SKB) {
3128 cmd->meta.source->u.skb = rxb->skb;
3129 rxb->skb = NULL;
3130 } else if (cmd->meta.u.callback &&
3131 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3132 rxb->skb = NULL;
3133
91c066f2 3134 iwl3945_cmd_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3135
3136 if (!(cmd->meta.flags & CMD_ASYNC)) {
3137 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3138 wake_up_interruptible(&priv->wait_command_queue);
3139 }
3140}
3141
3142/************************** RX-FUNCTIONS ****************************/
3143/*
3144 * Rx theory of operation
3145 *
3146 * The host allocates 32 DMA target addresses and passes the host address
3147 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3148 * 0 to 31
3149 *
3150 * Rx Queue Indexes
3151 * The host/firmware share two index registers for managing the Rx buffers.
3152 *
3153 * The READ index maps to the first position that the firmware may be writing
3154 * to -- the driver can read up to (but not including) this position and get
3155 * good data.
3156 * The READ index is managed by the firmware once the card is enabled.
3157 *
3158 * The WRITE index maps to the last position the driver has read from -- the
3159 * position preceding WRITE is the last slot the firmware can place a packet.
3160 *
3161 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3162 * WRITE = READ.
3163 *
9fbab516 3164 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 3165 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3166 *
9fbab516 3167 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 3168 * and fire the RX interrupt. The driver can then query the READ index and
3169 * process as many packets as possible, moving the WRITE index forward as it
3170 * resets the Rx queue buffers with new memory.
3171 *
3172 * The management in the driver is as follows:
3173 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3174 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3175 * to replenish the iwl->rxq->rx_free.
bb8c093b 3176 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 3177 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3178 * 'processed' and 'read' driver indexes as well)
3179 * + A received packet is processed and handed to the kernel network stack,
3180 * detached from the iwl->rxq. The driver 'processed' index is updated.
3181 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3182 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3183 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3184 * were enough free buffers and RX_STALLED is set it is cleared.
3185 *
3186 *
3187 * Driver sequence:
3188 *
9fbab516 3189 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3190 * iwl3945_rx_queue_restock
9fbab516 3191 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 3192 * queue, updates firmware pointers, and updates
3193 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3194 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY		 3195 *
3196 * -- enable interrupts --
6100b588 3197 * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
b481de9c
ZY		 3198 * READ INDEX, detaching the SKB from the pool.
3199 * Moves the packet buffer from queue to rx_used.
bb8c093b 3200 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY		 3201 * slots.
3202 * ...
3203 *
3204 */
3205
3206/**
bb8c093b 3207 * iwl3945_rx_queue_space - Return number of free slots available in queue.
b481de9c 3208 */
cc2f362c 3209static int iwl3945_rx_queue_space(const struct iwl_rx_queue *q)
b481de9c
ZY		 3210{
3211 int s = q->read - q->write;
3212 if (s <= 0)
3213 s += RX_QUEUE_SIZE;
3214 /* keep some buffer to not confuse full and empty queue */
3215 s -= 2;
3216 if (s < 0)
3217 s = 0;
3218 return s;
3219}
3220
3221/**
bb8c093b 3222 * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3223 */
4a8a4322 3224int iwl3945_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
b481de9c
ZY		 3225{
3226 u32 reg = 0;
3227 int rc = 0;
3228 unsigned long flags;
3229
3230 spin_lock_irqsave(&q->lock, flags);
3231
3232 if (q->need_update == 0)
3233 goto exit_unlock;
3234
6440adb5 3235 /* If power-saving is in use, make sure device is awake */
b481de9c 3236 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
5d49f498 3237 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3238
3239 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
5d49f498 3240 iwl_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3241 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3242 goto exit_unlock;
3243 }
3244
5d49f498 3245 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 3246 if (rc)
3247 goto exit_unlock;
3248
6440adb5 3249 /* Device expects a multiple of 8 */
5d49f498 3250 iwl_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
b481de9c 3251 q->write & ~0x7);
5d49f498 3252 iwl_release_nic_access(priv);
6440adb5
CB		 3253
3254 /* Else device is assumed to be awake */
b481de9c 3255 } else
6440adb5 3256 /* Device expects a multiple of 8 */
5d49f498 3257 iwl_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 3258
3259
3260 q->need_update = 0;
3261
3262 exit_unlock:
3263 spin_unlock_irqrestore(&q->lock, flags);
3264 return rc;
3265}
3266
3267/**
9fbab516 3268 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3269 */
4a8a4322 3270static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY		 3271 dma_addr_t dma_addr)
3272{
3273 return cpu_to_le32((u32)dma_addr);
3274}
3275
3276/**
bb8c093b 3277 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3278 *
9fbab516 3279 * If there are slots in the RX queue that need to be restocked,
b481de9c 3280 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3281 * as we can, pulling from rx_free.
b481de9c
ZY		 3282 *
3283 * This moves the 'write' index forward to catch up with 'processed', and
3284 * also updates the memory address in the firmware to reference the new
3285 * target buffer.
3286 */
4a8a4322 3287static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
b481de9c 3288{
cc2f362c 3289 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 3290 struct list_head *element;
6100b588 3291 struct iwl_rx_mem_buffer *rxb;
b481de9c
ZY		 3292 unsigned long flags;
3293 int write, rc;
3294
3295 spin_lock_irqsave(&rxq->lock, flags);
3296 write = rxq->write & ~0x7;
bb8c093b 3297 while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3298 /* Get next free Rx buffer, remove from free list */
b481de9c 3299 element = rxq->rx_free.next;
6100b588 3300 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
b481de9c 3301 list_del(element);
6440adb5
CB		 3302
3303 /* Point to Rx buffer via next RBD in circular buffer */
6100b588 3304 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
b481de9c
ZY		 3305 rxq->queue[rxq->write] = rxb;
3306 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3307 rxq->free_count--;
3308 }
3309 spin_unlock_irqrestore(&rxq->lock, flags);
3310 /* If the pre-allocated buffer pool is dropping low, schedule to
3311 * refill it */
3312 if (rxq->free_count <= RX_LOW_WATERMARK)
3313 queue_work(priv->workqueue, &priv->rx_replenish);
3314
3315
6440adb5
CB		 3316 /* If we've added more space for the firmware to place data, tell it.
3317 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 3318 if ((write != (rxq->write & ~0x7))
3319 || (abs(rxq->write - rxq->read) > 7)) {
3320 spin_lock_irqsave(&rxq->lock, flags);
3321 rxq->need_update = 1;
3322 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 3323 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 3324 if (rc)
3325 return rc;
3326 }
3327
3328 return 0;
3329}
3330
3331/**
bb8c093b 3332 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 3333 *
3334 * When moving to rx_free an SKB is allocated for the slot.
3335 *
bb8c093b 3336 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 3337 * This is called as a scheduled work item (except for during initialization)
b481de9c 3338 */
4a8a4322 3339static void iwl3945_rx_allocate(struct iwl_priv *priv)
b481de9c 3340{
cc2f362c 3341 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 3342 struct list_head *element;
6100b588 3343 struct iwl_rx_mem_buffer *rxb;
b481de9c
ZY		 3344 unsigned long flags;
3345 spin_lock_irqsave(&rxq->lock, flags);
3346 while (!list_empty(&rxq->rx_used)) {
3347 element = rxq->rx_used.next;
6100b588 3348 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
6440adb5
CB		 3349
3350 /* Alloc a new receive buffer */
b481de9c
ZY		 3351 rxb->skb =
3352 alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3353 if (!rxb->skb) {
3354 if (net_ratelimit())
978785a3 3355 IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
b481de9c
ZY		 3356 /* We don't reschedule replenish work here -- we will
3357 * call the restock method and if it still needs
3358 * more buffers it will schedule replenish */
3359 break;
3360 }
12342c47
ZY		 3361
3362 /* If radiotap head is required, reserve some headroom here.
3363 * The physical head count is a variable rx_stats->phy_count.
3364 * We reserve 4 bytes here. Plus these extra bytes, the
3365 * headroom of the physical head should be enough for the
3366 * radiotap head that iwl3945 supported. See iwl3945_rt.
3367 */
3368 skb_reserve(rxb->skb, 4);
3369
b481de9c
ZY		 3370 priv->alloc_rxb_skb++;
3371 list_del(element);
6440adb5
CB		 3372
3373 /* Get physical address of RB/SKB */
6100b588 3374 rxb->real_dma_addr =
b481de9c
ZY		 3375 pci_map_single(priv->pci_dev, rxb->skb->data,
3376 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3377 list_add_tail(&rxb->list, &rxq->rx_free);
3378 rxq->free_count++;
3379 }
3380 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA		 3381}
3382
3383/*
3384 * this should be called while priv->lock is locked
3385 */
4fd1f841 3386static void __iwl3945_rx_replenish(void *data)
5c0eef96 3387{
4a8a4322 3388 struct iwl_priv *priv = data;
5c0eef96
MA		 3389
3390 iwl3945_rx_allocate(priv);
3391 iwl3945_rx_queue_restock(priv);
3392}
3393
3394
3395void iwl3945_rx_replenish(void *data)
3396{
4a8a4322 3397 struct iwl_priv *priv = data;
5c0eef96
MA		 3398 unsigned long flags;
3399
3400 iwl3945_rx_allocate(priv);
b481de9c
ZY		 3401
3402 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3403 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3404 spin_unlock_irqrestore(&priv->lock, flags);
3405}
3406
b481de9c
ZY		 3407/* Convert linear signal-to-noise ratio into dB */
3408static u8 ratio2dB[100] = {
3409/* 0 1 2 3 4 5 6 7 8 9 */
3410 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3411 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3412 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3413 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3414 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3415 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3416 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3417 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3418 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3419 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
3420};
3421
3422/* Calculates a relative dB value from a ratio of linear
3423 * (i.e. not dB) signal levels.
3424 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 3425int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 3426{
221c80cf
AB		 3427 /* 1000:1 or higher just report as 60 dB */
3428 if (sig_ratio >= 1000)
b481de9c
ZY		 3429 return 60;
3430
221c80cf 3431 /* 100:1 or higher, divide by 10 and use table,
b481de9c 3432 * add 20 dB to make up for divide by 10 */
221c80cf 3433 if (sig_ratio >= 100)
3ac7f146 3434 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY		 3435
3436 /* We shouldn't see this */
3437 if (sig_ratio < 1)
3438 return 0;
3439
3440 /* Use table for ratios 1:1 - 99:1 */
3441 return (int)ratio2dB[sig_ratio];
3442}
3443
3444#define PERFECT_RSSI (-20) /* dBm */
3445#define WORST_RSSI (-95) /* dBm */
3446#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3447
3448/* Calculate an indication of rx signal quality (a percentage, not dBm!).
3449 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3450 * about formulas used below. */
bb8c093b 3451int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 3452{
3453 int sig_qual;
3454 int degradation = PERFECT_RSSI - rssi_dbm;
3455
3456 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3457 * as indicator; formula is (signal dbm - noise dbm).
3458 * SNR at or above 40 is a great signal (100%).
3459 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3460 * Weakest usable signal is usually 10 - 15 dB SNR. */
3461 if (noise_dbm) {
3462 if (rssi_dbm - noise_dbm >= 40)
3463 return 100;
3464 else if (rssi_dbm < noise_dbm)
3465 return 0;
3466 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3467
3468 /* Else use just the signal level.
3469 * This formula is a least squares fit of data points collected and
3470 * compared with a reference system that had a percentage (%) display
3471 * for signal quality. */
3472 } else
3473 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3474 (15 * RSSI_RANGE + 62 * degradation)) /
3475 (RSSI_RANGE * RSSI_RANGE);
3476
3477 if (sig_qual > 100)
3478 sig_qual = 100;
3479 else if (sig_qual < 1)
3480 sig_qual = 0;
3481
3482 return sig_qual;
3483}
3484
3485/**
9fbab516 3486 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 3487 *
3488 * Uses the priv->rx_handlers callback function array to invoke
3489 * the appropriate handlers, including command responses,
3490 * frame-received notifications, and other notifications.
3491 */
4a8a4322 3492static void iwl3945_rx_handle(struct iwl_priv *priv)
b481de9c 3493{
6100b588 3494 struct iwl_rx_mem_buffer *rxb;
3d24a9f7 3495 struct iwl_rx_packet *pkt;
cc2f362c 3496 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3497 u32 r, i;
3498 int reclaim;
3499 unsigned long flags;
5c0eef96 3500 u8 fill_rx = 0;
d68ab680 3501 u32 count = 8;
b481de9c 3502
6440adb5
CB		 3503 /* uCode's read index (stored in shared DRAM) indicates the last Rx
3504 * buffer that the driver may process (last buffer filled by ucode). */
8cd812bc 3505 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 3506 i = rxq->read;
3507
5c0eef96
MA		 3508 if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3509 fill_rx = 1;
b481de9c
ZY		 3510 /* Rx interrupt, but nothing sent from uCode */
3511 if (i == r)
3512 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3513
3514 while (i != r) {
3515 rxb = rxq->queue[i];
3516
9fbab516 3517 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 3518 * then a bug has been introduced in the queue refilling
3519 * routines -- catch it here */
3520 BUG_ON(rxb == NULL);
3521
3522 rxq->queue[i] = NULL;
3523
6100b588 3524 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->real_dma_addr,
b481de9c
ZY		 3525 IWL_RX_BUF_SIZE,
3526 PCI_DMA_FROMDEVICE);
3d24a9f7 3527 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3528
3529 /* Reclaim a command buffer only if this packet is a response
3530 * to a (driver-originated) command.
3531 * If the packet (e.g. Rx frame) originated from uCode,
3532 * there is no command buffer to reclaim.
3533 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
3534 * but apparently a few don't get set; catch them here. */
3535 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
3536 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
3537 (pkt->hdr.cmd != REPLY_TX);
3538
3539 /* Based on type of command response or notification,
3540 * handle those that need handling via function in
bb8c093b 3541 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c 3542 if (priv->rx_handlers[pkt->hdr.cmd]) {
40b8ec0b 3543 IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
b481de9c
ZY		 3544 "r = %d, i = %d, %s, 0x%02x\n", r, i,
3545 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3546 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
3547 } else {
3548 /* No handling needed */
40b8ec0b 3549 IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
b481de9c
ZY		 3550 "r %d i %d No handler needed for %s, 0x%02x\n",
3551 r, i, get_cmd_string(pkt->hdr.cmd),
3552 pkt->hdr.cmd);
3553 }
3554
3555 if (reclaim) {
9fbab516
BC		 3556 /* Invoke any callbacks, transfer the skb to caller, and
3557 * fire off the (possibly) blocking iwl3945_send_cmd()
b481de9c
ZY		 3558 * as we reclaim the driver command queue */
3559 if (rxb && rxb->skb)
bb8c093b 3560 iwl3945_tx_cmd_complete(priv, rxb);
b481de9c 3561 else
39aadf8c 3562 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 3563 }
3564
3565 /* For now we just don't re-use anything. We can tweak this
3566 * later to try and re-use notification packets and SKBs that
3567 * fail to Rx correctly */
3568 if (rxb->skb != NULL) {
3569 priv->alloc_rxb_skb--;
3570 dev_kfree_skb_any(rxb->skb);
3571 rxb->skb = NULL;
3572 }
3573
6100b588 3574 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
b481de9c
ZY		 3575 IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3576 spin_lock_irqsave(&rxq->lock, flags);
3577 list_add_tail(&rxb->list, &priv->rxq.rx_used);
3578 spin_unlock_irqrestore(&rxq->lock, flags);
3579 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 3580 /* If there are a lot of unused frames,
3581 * restock the Rx queue so ucode won't assert. */
3582 if (fill_rx) {
3583 count++;
3584 if (count >= 8) {
3585 priv->rxq.read = i;
3586 __iwl3945_rx_replenish(priv);
3587 count = 0;
3588 }
3589 }
b481de9c
ZY		 3590 }
3591
3592 /* Backtrack one entry */
3593 priv->rxq.read = i;
bb8c093b 3594 iwl3945_rx_queue_restock(priv);
b481de9c
ZY		 3595}
3596
6440adb5
CB		 3597/**
3598 * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
3599 */
4a8a4322 3600static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
188cf6c7 3601 struct iwl_tx_queue *txq)
b481de9c
ZY		 3602{
3603 u32 reg = 0;
3604 int rc = 0;
3605 int txq_id = txq->q.id;
3606
3607 if (txq->need_update == 0)
3608 return rc;
3609
3610 /* if we're trying to save power */
3611 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3612 /* wake up nic if it's powered down ...
3613 * uCode will wake up, and interrupt us again, so next
3614 * time we'll skip this part. */
5d49f498 3615 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3616
3617 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3618 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
5d49f498 3619 iwl_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3620 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3621 return rc;
3622 }
3623
3624 /* restore this queue's parameters in nic hardware. */
5d49f498 3625 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 3626 if (rc)
3627 return rc;
5d49f498 3628 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 3629 txq->q.write_ptr | (txq_id << 8));
5d49f498 3630 iwl_release_nic_access(priv);
b481de9c
ZY		 3631
3632 /* else not in power-save mode, uCode will never sleep when we're
3633 * trying to tx (during RFKILL, we're not trying to tx). */
3634 } else
5d49f498 3635 iwl_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 3636 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 3637
3638 txq->need_update = 0;
3639
3640 return rc;
3641}
3642
c8b0e6e1 3643#ifdef CONFIG_IWL3945_DEBUG
4a8a4322 3644static void iwl3945_print_rx_config_cmd(struct iwl_priv *priv,
40b8ec0b 3645 struct iwl3945_rxon_cmd *rxon)
b481de9c
ZY		 3646{
3647 IWL_DEBUG_RADIO("RX CONFIG:\n");
40b8ec0b 3648 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 3649 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
3650 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
3651 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
3652 le32_to_cpu(rxon->filter_flags));
3653 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
3654 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
3655 rxon->ofdm_basic_rates);
3656 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
e174961c
JB		 3657 IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
3658 IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
b481de9c
ZY		 3659 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
3660}
3661#endif
3662
4a8a4322 3663static void iwl3945_enable_interrupts(struct iwl_priv *priv)
b481de9c
ZY		 3664{
3665 IWL_DEBUG_ISR("Enabling interrupts\n");
3666 set_bit(STATUS_INT_ENABLED, &priv->status);
5d49f498 3667 iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 3668}
3669
0359facc
MA		 3670
3671/* call this function to flush any scheduled tasklet */
4a8a4322 3672static inline void iwl_synchronize_irq(struct iwl_priv *priv)
0359facc 3673{
a96a27f9 3674 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 3675 synchronize_irq(priv->pci_dev->irq);
3676 tasklet_kill(&priv->irq_tasklet);
3677}
3678
3679
4a8a4322 3680static inline void iwl3945_disable_interrupts(struct iwl_priv *priv)
b481de9c
ZY		 3681{
3682 clear_bit(STATUS_INT_ENABLED, &priv->status);
3683
3684 /* disable interrupts from uCode/NIC to host */
5d49f498 3685 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 3686
3687 /* acknowledge/clear/reset any interrupts still pending
3688 * from uCode or flow handler (Rx/Tx DMA) */
5d49f498
AK		 3689 iwl_write32(priv, CSR_INT, 0xffffffff);
3690 iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 3691 IWL_DEBUG_ISR("Disabled interrupts\n");
3692}
3693
3694static const char *desc_lookup(int i)
3695{
3696 switch (i) {
3697 case 1:
3698 return "FAIL";
3699 case 2:
3700 return "BAD_PARAM";
3701 case 3:
3702 return "BAD_CHECKSUM";
3703 case 4:
3704 return "NMI_INTERRUPT";
3705 case 5:
3706 return "SYSASSERT";
3707 case 6:
3708 return "FATAL_ERROR";
3709 }
3710
3711 return "UNKNOWN";
3712}
3713
3714#define ERROR_START_OFFSET (1 * sizeof(u32))
3715#define ERROR_ELEM_SIZE (7 * sizeof(u32))
3716
4a8a4322 3717static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY		 3718{
3719 u32 i;
3720 u32 desc, time, count, base, data1;
3721 u32 blink1, blink2, ilink1, ilink2;
3722 int rc;
3723
3724 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
3725
bb8c093b 3726 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 3727 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
b481de9c
ZY		 3728 return;
3729 }
3730
5d49f498 3731 rc = iwl_grab_nic_access(priv);
b481de9c 3732 if (rc) {
39aadf8c 3733 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY		 3734 return;
3735 }
3736
5d49f498 3737 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY		 3738
3739 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT		 3740 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
3741 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
3742 priv->status, count);
b481de9c
ZY		 3743 }
3744
15b1687c 3745 IWL_ERR(priv, "Desc Time asrtPC blink2 "
b481de9c
ZY		 3746 "ilink1 nmiPC Line\n");
3747 for (i = ERROR_START_OFFSET;
3748 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
3749 i += ERROR_ELEM_SIZE) {
5d49f498 3750 desc = iwl_read_targ_mem(priv, base + i);
b481de9c 3751 time =
5d49f498 3752 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 3753 blink1 =
5d49f498 3754 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 3755 blink2 =
5d49f498 3756 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 3757 ilink1 =
5d49f498 3758 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 3759 ilink2 =
5d49f498 3760 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 3761 data1 =
5d49f498 3762 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c 3763
15b1687c
WT		 3764 IWL_ERR(priv,
3765 "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
3766 desc_lookup(desc), desc, time, blink1, blink2,
3767 ilink1, ilink2, data1);
b481de9c
ZY		 3768 }
3769
5d49f498 3770 iwl_release_nic_access(priv);
b481de9c
ZY		 3771
3772}
3773
f58177b9 3774#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY		 3775
3776/**
bb8c093b 3777 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 3778 *
5d49f498 3779 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
b481de9c 3780 */
4a8a4322 3781static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
b481de9c
ZY		 3782 u32 num_events, u32 mode)
3783{
3784 u32 i;
3785 u32 base; /* SRAM byte address of event log header */
3786 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
3787 u32 ptr; /* SRAM byte address of log data */
3788 u32 ev, time, data; /* event log data */
3789
3790 if (num_events == 0)
3791 return;
3792
3793 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
3794
3795 if (mode == 0)
3796 event_size = 2 * sizeof(u32);
3797 else
3798 event_size = 3 * sizeof(u32);
3799
3800 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
3801
3802 /* "time" is actually "data" for mode 0 (no timestamp).
3803 * place event id # at far right for easier visual parsing. */
3804 for (i = 0; i < num_events; i++) {
5d49f498 3805 ev = iwl_read_targ_mem(priv, ptr);
b481de9c 3806 ptr += sizeof(u32);
5d49f498 3807 time = iwl_read_targ_mem(priv, ptr);
b481de9c 3808 ptr += sizeof(u32);
15b1687c
WT		 3809 if (mode == 0) {
3810 /* data, ev */
3811 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
3812 } else {
5d49f498 3813 data = iwl_read_targ_mem(priv, ptr);
b481de9c 3814 ptr += sizeof(u32);
15b1687c 3815 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
b481de9c
ZY		 3816 }
3817 }
3818}
3819
4a8a4322 3820static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
b481de9c
ZY		 3821{
3822 int rc;
3823 u32 base; /* SRAM byte address of event log header */
3824 u32 capacity; /* event log capacity in # entries */
3825 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
3826 u32 num_wraps; /* # times uCode wrapped to top of log */
3827 u32 next_entry; /* index of next entry to be written by uCode */
3828 u32 size; /* # entries that we'll print */
3829
3830 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 3831 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 3832 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 3833 return;
3834 }
3835
5d49f498 3836 rc = iwl_grab_nic_access(priv);
b481de9c 3837 if (rc) {
39aadf8c 3838 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY		 3839 return;
3840 }
3841
3842 /* event log header */
5d49f498
AK		 3843 capacity = iwl_read_targ_mem(priv, base);
3844 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
3845 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
3846 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 3847
3848 size = num_wraps ? capacity : next_entry;
3849
3850 /* bail out if nothing in log */
3851 if (size == 0) {
15b1687c 3852 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
5d49f498 3853 iwl_release_nic_access(priv);
b481de9c
ZY		 3854 return;
3855 }
3856
15b1687c 3857 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 3858 size, num_wraps);
3859
3860 /* if uCode has wrapped back to top of log, start at the oldest entry,
3861 * i.e the next one that uCode would fill. */
3862 if (num_wraps)
bb8c093b 3863 iwl3945_print_event_log(priv, next_entry,
b481de9c
ZY		 3864 capacity - next_entry, mode);
3865
3866 /* (then/else) start at top of log */
bb8c093b 3867 iwl3945_print_event_log(priv, 0, next_entry, mode);
b481de9c 3868
5d49f498 3869 iwl_release_nic_access(priv);
b481de9c
ZY		 3870}
3871
3872/**
bb8c093b 3873 * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 3874 */
4a8a4322 3875static void iwl3945_irq_handle_error(struct iwl_priv *priv)
b481de9c 3876{
bb8c093b 3877 /* Set the FW error flag -- cleared on iwl3945_down */
b481de9c
ZY		 3878 set_bit(STATUS_FW_ERROR, &priv->status);
3879
3880 /* Cancel currently queued command. */
3881 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3882
c8b0e6e1 3883#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 3884 if (priv->debug_level & IWL_DL_FW_ERRORS) {
bb8c093b
CH		 3885 iwl3945_dump_nic_error_log(priv);
3886 iwl3945_dump_nic_event_log(priv);
f2c7e521 3887 iwl3945_print_rx_config_cmd(priv, &priv->staging39_rxon);
b481de9c
ZY		 3888 }
3889#endif
3890
3891 wake_up_interruptible(&priv->wait_command_queue);
3892
3893 /* Keep the restart process from trying to send host
3894 * commands by clearing the INIT status bit */
3895 clear_bit(STATUS_READY, &priv->status);
3896
3897 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3898 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
3899 "Restarting adapter due to uCode error.\n");
3900
bb8c093b 3901 if (iwl3945_is_associated(priv)) {
f2c7e521
AK		 3902 memcpy(&priv->recovery39_rxon, &priv->active39_rxon,
3903 sizeof(priv->recovery39_rxon));
b481de9c
ZY		 3904 priv->error_recovering = 1;
3905 }
3906 queue_work(priv->workqueue, &priv->restart);
3907 }
3908}
3909
4a8a4322 3910static void iwl3945_error_recovery(struct iwl_priv *priv)
b481de9c
ZY		 3911{
3912 unsigned long flags;
3913
f2c7e521
AK		 3914 memcpy(&priv->staging39_rxon, &priv->recovery39_rxon,
3915 sizeof(priv->staging39_rxon));
3916 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 3917 iwl3945_commit_rxon(priv);
b481de9c 3918
bb8c093b 3919 iwl3945_add_station(priv, priv->bssid, 1, 0);
b481de9c
ZY		 3920
3921 spin_lock_irqsave(&priv->lock, flags);
f2c7e521 3922 priv->assoc_id = le16_to_cpu(priv->staging39_rxon.assoc_id);
b481de9c
ZY		 3923 priv->error_recovering = 0;
3924 spin_unlock_irqrestore(&priv->lock, flags);
3925}
3926
4a8a4322 3927static void iwl3945_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY		 3928{
3929 u32 inta, handled = 0;
3930 u32 inta_fh;
3931 unsigned long flags;
c8b0e6e1 3932#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 3933 u32 inta_mask;
3934#endif
3935
3936 spin_lock_irqsave(&priv->lock, flags);
3937
3938 /* Ack/clear/reset pending uCode interrupts.
3939 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
3940 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
5d49f498
AK		 3941 inta = iwl_read32(priv, CSR_INT);
3942 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 3943
3944 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
3945 * Any new interrupts that happen after this, either while we're
3946 * in this tasklet, or later, will show up in next ISR/tasklet. */
5d49f498
AK		 3947 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
3948 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 3949
c8b0e6e1 3950#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 3951 if (priv->debug_level & IWL_DL_ISR) {
9fbab516 3952 /* just for debug */
5d49f498 3953 inta_mask = iwl_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 3954 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
3955 inta, inta_mask, inta_fh);
3956 }
3957#endif
3958
3959 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
3960 * atomic, make sure that inta covers all the interrupts that
3961 * we've discovered, even if FH interrupt came in just after
3962 * reading CSR_INT. */
6f83eaa1 3963 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 3964 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 3965 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY		 3966 inta |= CSR_INT_BIT_FH_TX;
3967
3968 /* Now service all interrupt bits discovered above. */
3969 if (inta & CSR_INT_BIT_HW_ERR) {
15b1687c 3970 IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
b481de9c
ZY		 3971
3972 /* Tell the device to stop sending interrupts */
bb8c093b 3973 iwl3945_disable_interrupts(priv);
b481de9c 3974
bb8c093b 3975 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 3976
3977 handled |= CSR_INT_BIT_HW_ERR;
3978
3979 spin_unlock_irqrestore(&priv->lock, flags);
3980
3981 return;
3982 }
3983
c8b0e6e1 3984#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 3985 if (priv->debug_level & (IWL_DL_ISR)) {
b481de9c 3986 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP		 3987 if (inta & CSR_INT_BIT_SCD)
3988 IWL_DEBUG_ISR("Scheduler finished to transmit "
3989 "the frame/frames.\n");
b481de9c
ZY		 3990
3991 /* Alive notification via Rx interrupt will do the real work */
3992 if (inta & CSR_INT_BIT_ALIVE)
3993 IWL_DEBUG_ISR("Alive interrupt\n");
3994 }
3995#endif
3996 /* Safely ignore these bits for debug checks below */
25c03d8e 3997 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 3998
b481de9c
ZY		 3999 /* Error detected by uCode */
4000 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT		 4001 IWL_ERR(priv, "Microcode SW error detected. "
4002 "Restarting 0x%X.\n", inta);
bb8c093b 4003 iwl3945_irq_handle_error(priv);
b481de9c
ZY		 4004 handled |= CSR_INT_BIT_SW_ERR;
4005 }
4006
4007 /* uCode wakes up after power-down sleep */
4008 if (inta & CSR_INT_BIT_WAKEUP) {
4009 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b 4010 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
188cf6c7
SO		 4011 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4012 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4013 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4014 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4015 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4016 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 4017
4018 handled |= CSR_INT_BIT_WAKEUP;
4019 }
4020
4021 /* All uCode command responses, including Tx command responses,
4022 * Rx "responses" (frame-received notification), and other
4023 * notifications from uCode come through here*/
4024 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4025 iwl3945_rx_handle(priv);
b481de9c
ZY		 4026 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4027 }
4028
4029 if (inta & CSR_INT_BIT_FH_TX) {
4030 IWL_DEBUG_ISR("Tx interrupt\n");
4031
5d49f498
AK		 4032 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4033 if (!iwl_grab_nic_access(priv)) {
4034 iwl_write_direct32(priv, FH39_TCSR_CREDIT
bddadf86 4035 (FH39_SRVC_CHNL), 0x0);
5d49f498 4036 iwl_release_nic_access(priv);
b481de9c
ZY		 4037 }
4038 handled |= CSR_INT_BIT_FH_TX;
4039 }
4040
4041 if (inta & ~handled)
15b1687c 4042 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
b481de9c
ZY		 4043
4044 if (inta & ~CSR_INI_SET_MASK) {
39aadf8c 4045 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
b481de9c 4046 inta & ~CSR_INI_SET_MASK);
39aadf8c 4047 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY		 4048 }
4049
4050 /* Re-enable all interrupts */
0359facc
MA		 4051 /* only Re-enable if disabled by irq */
4052 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4053 iwl3945_enable_interrupts(priv);
b481de9c 4054
c8b0e6e1 4055#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 4056 if (priv->debug_level & (IWL_DL_ISR)) {
5d49f498
AK		 4057 inta = iwl_read32(priv, CSR_INT);
4058 inta_mask = iwl_read32(priv, CSR_INT_MASK);
4059 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4060 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4061 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4062 }
4063#endif
4064 spin_unlock_irqrestore(&priv->lock, flags);
4065}
4066
bb8c093b 4067static irqreturn_t iwl3945_isr(int irq, void *data)
b481de9c 4068{
4a8a4322 4069 struct iwl_priv *priv = data;
b481de9c
ZY		 4070 u32 inta, inta_mask;
4071 u32 inta_fh;
4072 if (!priv)
4073 return IRQ_NONE;
4074
4075 spin_lock(&priv->lock);
4076
4077 /* Disable (but don't clear!) interrupts here to avoid
4078 * back-to-back ISRs and sporadic interrupts from our NIC.
4079 * If we have something to service, the tasklet will re-enable ints.
4080 * If we *don't* have something, we'll re-enable before leaving here. */
5d49f498
AK		 4081 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
4082 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4083
4084 /* Discover which interrupts are active/pending */
5d49f498
AK		 4085 inta = iwl_read32(priv, CSR_INT);
4086 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4087
4088 /* Ignore interrupt if there's nothing in NIC to service.
4089 * This may be due to IRQ shared with another device,
4090 * or due to sporadic interrupts thrown from our NIC. */
4091 if (!inta && !inta_fh) {
4092 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4093 goto none;
4094 }
4095
4096 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4097 /* Hardware disappeared */
39aadf8c 4098 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
cb4da1a3 4099 goto unplugged;
b481de9c
ZY		 4100 }
4101
4102 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4103 inta, inta_mask, inta_fh);
4104
25c03d8e
JP		 4105 inta &= ~CSR_INT_BIT_SCD;
4106
bb8c093b 4107 /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP		 4108 if (likely(inta || inta_fh))
4109 tasklet_schedule(&priv->irq_tasklet);
cb4da1a3 4110unplugged:
b481de9c
ZY		 4111 spin_unlock(&priv->lock);
4112
4113 return IRQ_HANDLED;
4114
4115 none:
4116 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA		 4117 /* only Re-enable if disabled by irq */
4118 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4119 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 4120 spin_unlock(&priv->lock);
4121 return IRQ_NONE;
4122}
4123
4124/************************** EEPROM BANDS ****************************
4125 *
bb8c093b 4126 * The iwl3945_eeprom_band definitions below provide the mapping from the
b481de9c
ZY		 4127 * EEPROM contents to the specific channel number supported for each
4128 * band.
4129 *
f2c7e521 4130 * For example, iwl3945_priv->eeprom39.band_3_channels[4] from the band_3
b481de9c
ZY		 4131 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4132 * The specific geography and calibration information for that channel
4133 * is contained in the eeprom map itself.
4134 *
4135 * During init, we copy the eeprom information and channel map
4136 * information into priv->channel_info_24/52 and priv->channel_map_24/52
4137 *
4138 * channel_map_24/52 provides the index in the channel_info array for a
4139 * given channel. We have to have two separate maps as there is channel
4140 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4141 * band_2
4142 *
4143 * A value of 0xff stored in the channel_map indicates that the channel
4144 * is not supported by the hardware at all.
4145 *
4146 * A value of 0xfe in the channel_map indicates that the channel is not
4147 * valid for Tx with the current hardware. This means that
4148 * while the system can tune and receive on a given channel, it may not
4149 * be able to associate or transmit any frames on that
4150 * channel. There is no corresponding channel information for that
4151 * entry.
4152 *
4153 *********************************************************************/
4154
4155/* 2.4 GHz */
bb8c093b 4156static const u8 iwl3945_eeprom_band_1[14] = {
b481de9c
ZY		 4157 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4158};
4159
4160/* 5.2 GHz bands */
9fbab516 4161static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
b481de9c
ZY		 4162 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4163};
4164
9fbab516 4165static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
b481de9c
ZY		 4166 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4167};
4168
bb8c093b 4169static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
b481de9c
ZY		 4170 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4171};
4172
bb8c093b 4173static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
b481de9c
ZY		 4174 145, 149, 153, 157, 161, 165
4175};
4176
4a8a4322 4177static void iwl3945_init_band_reference(const struct iwl_priv *priv, int band,
b481de9c 4178 int *eeprom_ch_count,
0f741d99 4179 const struct iwl_eeprom_channel
b481de9c
ZY		 4180 **eeprom_ch_info,
4181 const u8 **eeprom_ch_index)
4182{
4183 switch (band) {
4184 case 1: /* 2.4GHz band */
bb8c093b 4185 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
f2c7e521 4186 *eeprom_ch_info = priv->eeprom39.band_1_channels;
bb8c093b 4187 *eeprom_ch_index = iwl3945_eeprom_band_1;
b481de9c 4188 break;
9fbab516 4189 case 2: /* 4.9GHz band */
bb8c093b 4190 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
f2c7e521 4191 *eeprom_ch_info = priv->eeprom39.band_2_channels;
bb8c093b 4192 *eeprom_ch_index = iwl3945_eeprom_band_2;
b481de9c
ZY		 4193 break;
4194 case 3: /* 5.2GHz band */
bb8c093b 4195 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
f2c7e521 4196 *eeprom_ch_info = priv->eeprom39.band_3_channels;
bb8c093b 4197 *eeprom_ch_index = iwl3945_eeprom_band_3;
b481de9c 4198 break;
9fbab516 4199 case 4: /* 5.5GHz band */
bb8c093b 4200 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
f2c7e521 4201 *eeprom_ch_info = priv->eeprom39.band_4_channels;
bb8c093b 4202 *eeprom_ch_index = iwl3945_eeprom_band_4;
b481de9c 4203 break;
9fbab516 4204 case 5: /* 5.7GHz band */
bb8c093b 4205 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
f2c7e521 4206 *eeprom_ch_info = priv->eeprom39.band_5_channels;
bb8c093b 4207 *eeprom_ch_index = iwl3945_eeprom_band_5;
b481de9c
ZY		 4208 break;
4209 default:
4210 BUG();
4211 return;
4212 }
4213}
4214
6440adb5
CB		 4215/**
4216 * iwl3945_get_channel_info - Find driver's private channel info
4217 *
4218 * Based on band and channel number.
4219 */
d20b3c65 4220const struct iwl_channel_info *
4a8a4322 4221iwl3945_get_channel_info(const struct iwl_priv *priv,
d20b3c65 4222 enum ieee80211_band band, u16 channel)
b481de9c
ZY		 4223{
4224 int i;
4225
8318d78a
JB		 4226 switch (band) {
4227 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 4228 for (i = 14; i < priv->channel_count; i++) {
4229 if (priv->channel_info[i].channel == channel)
4230 return &priv->channel_info[i];
4231 }
4232 break;
4233
8318d78a 4234 case IEEE80211_BAND_2GHZ:
b481de9c
ZY		 4235 if (channel >= 1 && channel <= 14)
4236 return &priv->channel_info[channel - 1];
4237 break;
8318d78a
JB		 4238 case IEEE80211_NUM_BANDS:
4239 WARN_ON(1);
b481de9c
ZY		 4240 }
4241
4242 return NULL;
4243}
4244
4245#define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4246 ? # x " " : "")
4247
6440adb5
CB		 4248/**
4249 * iwl3945_init_channel_map - Set up driver's info for all possible channels
4250 */
4a8a4322 4251static int iwl3945_init_channel_map(struct iwl_priv *priv)
b481de9c
ZY		 4252{
4253 int eeprom_ch_count = 0;
4254 const u8 *eeprom_ch_index = NULL;
0f741d99 4255 const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
b481de9c 4256 int band, ch;
d20b3c65 4257 struct iwl_channel_info *ch_info;
b481de9c
ZY		 4258
4259 if (priv->channel_count) {
4260 IWL_DEBUG_INFO("Channel map already initialized.\n");
4261 return 0;
4262 }
4263
f2c7e521 4264 if (priv->eeprom39.version < 0x2f) {
39aadf8c 4265 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
f2c7e521 4266 priv->eeprom39.version);
b481de9c
ZY		 4267 return -EINVAL;
4268 }
4269
4270 IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4271
4272 priv->channel_count =
bb8c093b
CH		 4273 ARRAY_SIZE(iwl3945_eeprom_band_1) +
4274 ARRAY_SIZE(iwl3945_eeprom_band_2) +
4275 ARRAY_SIZE(iwl3945_eeprom_band_3) +
4276 ARRAY_SIZE(iwl3945_eeprom_band_4) +
4277 ARRAY_SIZE(iwl3945_eeprom_band_5);
b481de9c
ZY		 4278
4279 IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4280
d20b3c65 4281 priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
b481de9c
ZY		 4282 priv->channel_count, GFP_KERNEL);
4283 if (!priv->channel_info) {
15b1687c 4284 IWL_ERR(priv, "Could not allocate channel_info\n");
b481de9c
ZY		 4285 priv->channel_count = 0;
4286 return -ENOMEM;
4287 }
4288
4289 ch_info = priv->channel_info;
4290
4291 /* Loop through the 5 EEPROM bands adding them in order to the
4292 * channel map we maintain (that contains additional information than
4293 * what just in the EEPROM) */
4294 for (band = 1; band <= 5; band++) {
4295
bb8c093b 4296 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
b481de9c
ZY		 4297 &eeprom_ch_info, &eeprom_ch_index);
4298
4299 /* Loop through each band adding each of the channels */
4300 for (ch = 0; ch < eeprom_ch_count; ch++) {
4301 ch_info->channel = eeprom_ch_index[ch];
8318d78a
JB		 4302 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4303 IEEE80211_BAND_5GHZ;
b481de9c
ZY		 4304
4305 /* permanently store EEPROM's channel regulatory flags
4306 * and max power in channel info database. */
4307 ch_info->eeprom = eeprom_ch_info[ch];
4308
4309 /* Copy the run-time flags so they are there even on
4310 * invalid channels */
4311 ch_info->flags = eeprom_ch_info[ch].flags;
4312
4313 if (!(is_channel_valid(ch_info))) {
4314 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4315 "No traffic\n",
4316 ch_info->channel,
4317 ch_info->flags,
4318 is_channel_a_band(ch_info) ?
4319 "5.2" : "2.4");
4320 ch_info++;
4321 continue;
4322 }
4323
4324 /* Initialize regulatory-based run-time data */
4325 ch_info->max_power_avg = ch_info->curr_txpow =
4326 eeprom_ch_info[ch].max_power_avg;
4327 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4328 ch_info->min_power = 0;
4329
fe7c4040 4330 IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
b481de9c
ZY		 4331 " %ddBm): Ad-Hoc %ssupported\n",
4332 ch_info->channel,
4333 is_channel_a_band(ch_info) ?
4334 "5.2" : "2.4",
8211ef78 4335 CHECK_AND_PRINT(VALID),
b481de9c
ZY		 4336 CHECK_AND_PRINT(IBSS),
4337 CHECK_AND_PRINT(ACTIVE),
4338 CHECK_AND_PRINT(RADAR),
4339 CHECK_AND_PRINT(WIDE),
b481de9c
ZY		 4340 CHECK_AND_PRINT(DFS),
4341 eeprom_ch_info[ch].flags,
4342 eeprom_ch_info[ch].max_power_avg,
4343 ((eeprom_ch_info[ch].
4344 flags & EEPROM_CHANNEL_IBSS)
4345 && !(eeprom_ch_info[ch].
4346 flags & EEPROM_CHANNEL_RADAR))
4347 ? "" : "not ");
4348
4349 /* Set the user_txpower_limit to the highest power
4350 * supported by any channel */
4351 if (eeprom_ch_info[ch].max_power_avg >
4352 priv->user_txpower_limit)
4353 priv->user_txpower_limit =
4354 eeprom_ch_info[ch].max_power_avg;
4355
4356 ch_info++;
4357 }
4358 }
4359
6440adb5 4360 /* Set up txpower settings in driver for all channels */
b481de9c
ZY		 4361 if (iwl3945_txpower_set_from_eeprom(priv))
4362 return -EIO;
4363
4364 return 0;
4365}
4366
849e0dce
RC		 4367/*
4368 * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4369 */
4a8a4322 4370static void iwl3945_free_channel_map(struct iwl_priv *priv)
849e0dce
RC		 4371{
4372 kfree(priv->channel_info);
4373 priv->channel_count = 0;
4374}
4375
b481de9c
ZY		 4376/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4377 * sending probe req. This should be set long enough to hear probe responses
4378 * from more than one AP. */
f9340520
AK		 4379#define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
4380#define IWL_ACTIVE_DWELL_TIME_52 (20)
4381
4382#define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
4383#define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
b481de9c
ZY		 4384
4385/* For faster active scanning, scan will move to the next channel if fewer than
4386 * PLCP_QUIET_THRESH packets are heard on this channel within
4387 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4388 * time if it's a quiet channel (nothing responded to our probe, and there's
4389 * no other traffic).
4390 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4391#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
f9340520 4392#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
b481de9c
ZY		 4393
4394/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4395 * Must be set longer than active dwell time.
4396 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4397#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4398#define IWL_PASSIVE_DWELL_TIME_52 (10)
4399#define IWL_PASSIVE_DWELL_BASE (100)
4400#define IWL_CHANNEL_TUNE_TIME 5
4401
e720ce9d 4402#define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
f9340520 4403
4a8a4322 4404static inline u16 iwl3945_get_active_dwell_time(struct iwl_priv *priv,
f9340520
AK		 4405 enum ieee80211_band band,
4406 u8 n_probes)
b481de9c 4407{
8318d78a 4408 if (band == IEEE80211_BAND_5GHZ)
f9340520
AK		 4409 return IWL_ACTIVE_DWELL_TIME_52 +
4410 IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
b481de9c 4411 else
f9340520
AK		 4412 return IWL_ACTIVE_DWELL_TIME_24 +
4413 IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
b481de9c
ZY		 4414}
4415
4a8a4322 4416static u16 iwl3945_get_passive_dwell_time(struct iwl_priv *priv,
8318d78a 4417 enum ieee80211_band band)
b481de9c 4418{
8318d78a 4419 u16 passive = (band == IEEE80211_BAND_2GHZ) ?
b481de9c
ZY		 4420 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4421 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4422
bb8c093b 4423 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 4424 /* If we're associated, we clamp the maximum passive
4425 * dwell time to be 98% of the beacon interval (minus
4426 * 2 * channel tune time) */
4427 passive = priv->beacon_int;
4428 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4429 passive = IWL_PASSIVE_DWELL_BASE;
4430 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4431 }
4432
b481de9c
ZY		 4433 return passive;
4434}
4435
4a8a4322 4436static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 4437 enum ieee80211_band band,
f9340520 4438 u8 is_active, u8 n_probes,
bb8c093b 4439 struct iwl3945_scan_channel *scan_ch)
b481de9c
ZY		 4440{
4441 const struct ieee80211_channel *channels = NULL;
8318d78a 4442 const struct ieee80211_supported_band *sband;
d20b3c65 4443 const struct iwl_channel_info *ch_info;
b481de9c
ZY		 4444 u16 passive_dwell = 0;
4445 u16 active_dwell = 0;
4446 int added, i;
4447
cbba18c6 4448 sband = iwl_get_hw_mode(priv, band);
8318d78a 4449 if (!sband)
b481de9c
ZY		 4450 return 0;
4451
8318d78a 4452 channels = sband->channels;
b481de9c 4453
f9340520 4454 active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
8318d78a 4455 passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
b481de9c 4456
8f4807a1
AK		 4457 if (passive_dwell <= active_dwell)
4458 passive_dwell = active_dwell + 1;
4459
8318d78a 4460 for (i = 0, added = 0; i < sband->n_channels; i++) {
182e2e66
JB		 4461 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4462 continue;
4463
8318d78a 4464 scan_ch->channel = channels[i].hw_value;
b481de9c 4465
8318d78a 4466 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
b481de9c 4467 if (!is_channel_valid(ch_info)) {
66b5004d 4468 IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
b481de9c
ZY		 4469 scan_ch->channel);
4470 continue;
4471 }
4472
011a0330
AK		 4473 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4474 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4475 /* If passive , set up for auto-switch
4476 * and use long active_dwell time.
4477 */
b481de9c 4478 if (!is_active || is_channel_passive(ch_info) ||
011a0330 4479 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 4480 scan_ch->type = 0; /* passive */
011a0330
AK		 4481 if (IWL_UCODE_API(priv->ucode_ver) == 1)
4482 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
4483 } else {
b481de9c 4484 scan_ch->type = 1; /* active */
011a0330 4485 }
b481de9c 4486
011a0330
AK		 4487 /* Set direct probe bits. These may be used both for active
4488 * scan channels (probes gets sent right away),
4489 * or for passive channels (probes get se sent only after
4490 * hearing clear Rx packet).*/
4491 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
4492 if (n_probes)
4493 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
4494 } else {
4495 /* uCode v1 does not allow setting direct probe bits on
4496 * passive channel. */
4497 if ((scan_ch->type & 1) && n_probes)
4498 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
4499 }
b481de9c 4500
9fbab516 4501 /* Set txpower levels to defaults */
b481de9c
ZY		 4502 scan_ch->tpc.dsp_atten = 110;
4503 /* scan_pwr_info->tpc.dsp_atten; */
4504
4505 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 4506 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4507 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4508 else {
4509 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4510 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 4511 * power level:
8a1b0245 4512 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY		 4513 */
4514 }
4515
4516 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
4517 scan_ch->channel,
4518 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
4519 (scan_ch->type & 1) ?
4520 active_dwell : passive_dwell);
4521
4522 scan_ch++;
4523 added++;
4524 }
4525
4526 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
4527 return added;
4528}
4529
4a8a4322 4530static void iwl3945_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY		 4531 struct ieee80211_rate *rates)
4532{
4533 int i;
4534
4535 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB		 4536 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
4537 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4538 rates[i].hw_value_short = i;
4539 rates[i].flags = 0;
d9829a67 4540 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 4541 /*
8318d78a 4542 * If CCK != 1M then set short preamble rate flag.
b481de9c 4543 */
bb8c093b 4544 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 4545 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 4546 }
b481de9c
ZY		 4547 }
4548}
4549
4550/**
bb8c093b 4551 * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 4552 */
4a8a4322 4553static int iwl3945_init_geos(struct iwl_priv *priv)
b481de9c 4554{
d20b3c65 4555 struct iwl_channel_info *ch;
8211ef78 4556 struct ieee80211_supported_band *sband;
b481de9c
ZY		 4557 struct ieee80211_channel *channels;
4558 struct ieee80211_channel *geo_ch;
4559 struct ieee80211_rate *rates;
4560 int i = 0;
b481de9c 4561
8318d78a
JB		 4562 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
4563 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY		 4564 IWL_DEBUG_INFO("Geography modes already initialized.\n");
4565 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4566 return 0;
4567 }
4568
b481de9c
ZY		 4569 channels = kzalloc(sizeof(struct ieee80211_channel) *
4570 priv->channel_count, GFP_KERNEL);
8318d78a 4571 if (!channels)
b481de9c 4572 return -ENOMEM;
b481de9c 4573
8211ef78 4574 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY		 4575 GFP_KERNEL);
4576 if (!rates) {
b481de9c
ZY		 4577 kfree(channels);
4578 return -ENOMEM;
4579 }
4580
b481de9c 4581 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78
TW		 4582 sband = &priv->bands[IEEE80211_BAND_5GHZ];
4583 sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
4584 /* just OFDM */
4585 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
4586 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
4587
4588 sband = &priv->bands[IEEE80211_BAND_2GHZ];
4589 sband->channels = channels;
4590 /* OFDM & CCK */
4591 sband->bitrates = rates;
4592 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c
ZY		 4593
4594 priv->ieee_channels = channels;
4595 priv->ieee_rates = rates;
4596
bb8c093b 4597 iwl3945_init_hw_rates(priv, rates);
b481de9c 4598
8211ef78 4599 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY		 4600 ch = &priv->channel_info[i];
4601
8211ef78
TW		 4602 /* FIXME: might be removed if scan is OK*/
4603 if (!is_channel_valid(ch))
b481de9c 4604 continue;
b481de9c
ZY		 4605
4606 if (is_channel_a_band(ch))
8211ef78 4607 sband = &priv->bands[IEEE80211_BAND_5GHZ];
8318d78a 4608 else
8211ef78 4609 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 4610
8211ef78
TW		 4611 geo_ch = &sband->channels[sband->n_channels++];
4612
4613 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB		 4614 geo_ch->max_power = ch->max_power_avg;
4615 geo_ch->max_antenna_gain = 0xff;
7b72304d 4616 geo_ch->hw_value = ch->channel;
b481de9c
ZY		 4617
4618 if (is_channel_valid(ch)) {
8318d78a
JB		 4619 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
4620 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 4621
8318d78a
JB		 4622 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
4623 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY		 4624
4625 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 4626 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY		 4627
4628 if (ch->max_power_avg > priv->max_channel_txpower_limit)
4629 priv->max_channel_txpower_limit =
4630 ch->max_power_avg;
8211ef78 4631 } else {
8318d78a 4632 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW		 4633 }
4634
4635 /* Save flags for reg domain usage */
4636 geo_ch->orig_flags = geo_ch->flags;
4637
4638 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
4639 ch->channel, geo_ch->center_freq,
4640 is_channel_a_band(ch) ? "5.2" : "2.4",
4641 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
4642 "restricted" : "valid",
4643 geo_ch->flags);
b481de9c
ZY		 4644 }
4645
82b9a121
TW		 4646 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
4647 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW		 4648 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
4649 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
4650 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 4651 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY		 4652 }
4653
978785a3 4654 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB		 4655 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
4656 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 4657
e0e0a67e
JL		 4658 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
4659 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
4660 &priv->bands[IEEE80211_BAND_2GHZ];
4661 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
4662 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
4663 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 4664
b481de9c
ZY		 4665 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4666
4667 return 0;
4668}
4669
849e0dce
RC		 4670/*
4671 * iwl3945_free_geos - undo allocations in iwl3945_init_geos
4672 */
4a8a4322 4673static void iwl3945_free_geos(struct iwl_priv *priv)
849e0dce 4674{
849e0dce
RC		 4675 kfree(priv->ieee_channels);
4676 kfree(priv->ieee_rates);
4677 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
4678}
4679
b481de9c
ZY		 4680/******************************************************************************
4681 *
4682 * uCode download functions
4683 *
4684 ******************************************************************************/
4685
4a8a4322 4686static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 4687{
98c92211
TW		 4688 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
4689 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
4690 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
4691 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
4692 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
4693 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 4694}
4695
4696/**
bb8c093b 4697 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 4698 * looking at all data.
4699 */
4a8a4322 4700static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 4701{
4702 u32 val;
4703 u32 save_len = len;
4704 int rc = 0;
4705 u32 errcnt;
4706
4707 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
4708
5d49f498 4709 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 4710 if (rc)
4711 return rc;
4712
5d49f498 4713 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 4714 IWL39_RTC_INST_LOWER_BOUND);
b481de9c
ZY		 4715
4716 errcnt = 0;
4717 for (; len > 0; len -= sizeof(u32), image++) {
4718 /* read data comes through single port, auto-incr addr */
4719 /* NOTE: Use the debugless read so we don't flood kernel log
4720 * if IWL_DL_IO is set */
5d49f498 4721 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c 4722 if (val != le32_to_cpu(*image)) {
15b1687c 4723 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY		 4724 "offset 0x%x, is 0x%x, s/b 0x%x\n",
4725 save_len - len, val, le32_to_cpu(*image));
4726 rc = -EIO;
4727 errcnt++;
4728 if (errcnt >= 20)
4729 break;
4730 }
4731 }
4732
5d49f498 4733 iwl_release_nic_access(priv);
b481de9c
ZY		 4734
4735 if (!errcnt)
bc434dd2 4736 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY		 4737
4738 return rc;
4739}
4740
4741
4742/**
bb8c093b 4743 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 4744 * using sample data 100 bytes apart. If these sample points are good,
4745 * it's a pretty good bet that everything between them is good, too.
4746 */
4a8a4322 4747static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 4748{
4749 u32 val;
4750 int rc = 0;
4751 u32 errcnt = 0;
4752 u32 i;
4753
4754 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
4755
5d49f498 4756 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 4757 if (rc)
4758 return rc;
4759
4760 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
4761 /* read data comes through single port, auto-incr addr */
4762 /* NOTE: Use the debugless read so we don't flood kernel log
4763 * if IWL_DL_IO is set */
5d49f498 4764 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 4765 i + IWL39_RTC_INST_LOWER_BOUND);
5d49f498 4766 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 4767 if (val != le32_to_cpu(*image)) {
4768#if 0 /* Enable this if you want to see details */
15b1687c 4769 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY		 4770 "offset 0x%x, is 0x%x, s/b 0x%x\n",
4771 i, val, *image);
4772#endif
4773 rc = -EIO;
4774 errcnt++;
4775 if (errcnt >= 3)
4776 break;
4777 }
4778 }
4779
5d49f498 4780 iwl_release_nic_access(priv);
b481de9c
ZY		 4781
4782 return rc;
4783}
4784
4785
4786/**
bb8c093b 4787 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 4788 * and verify its contents
4789 */
4a8a4322 4790static int iwl3945_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY		 4791{
4792 __le32 *image;
4793 u32 len;
4794 int rc = 0;
4795
4796 /* Try bootstrap */
4797 image = (__le32 *)priv->ucode_boot.v_addr;
4798 len = priv->ucode_boot.len;
bb8c093b 4799 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 4800 if (rc == 0) {
4801 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
4802 return 0;
4803 }
4804
4805 /* Try initialize */
4806 image = (__le32 *)priv->ucode_init.v_addr;
4807 len = priv->ucode_init.len;
bb8c093b 4808 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 4809 if (rc == 0) {
4810 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
4811 return 0;
4812 }
4813
4814 /* Try runtime/protocol */
4815 image = (__le32 *)priv->ucode_code.v_addr;
4816 len = priv->ucode_code.len;
bb8c093b 4817 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 4818 if (rc == 0) {
4819 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
4820 return 0;
4821 }
4822
15b1687c 4823 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b481de9c 4824
9fbab516
BC		 4825 /* Since nothing seems to match, show first several data entries in
4826 * instruction SRAM, so maybe visual inspection will give a clue.
4827 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 4828 image = (__le32 *)priv->ucode_boot.v_addr;
4829 len = priv->ucode_boot.len;
bb8c093b 4830 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY		 4831
4832 return rc;
4833}
4834
4a8a4322 4835static void iwl3945_nic_start(struct iwl_priv *priv)
b481de9c
ZY		 4836{
4837 /* Remove all resets to allow NIC to operate */
5d49f498 4838 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 4839}
4840
4841/**
bb8c093b 4842 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 4843 *
4844 * Copy into buffers for card to fetch via bus-mastering
4845 */
4a8a4322 4846static int iwl3945_read_ucode(struct iwl_priv *priv)
b481de9c 4847{
a78fe754 4848 struct iwl_ucode *ucode;
a0987a8d 4849 int ret = -EINVAL, index;
b481de9c
ZY		 4850 const struct firmware *ucode_raw;
4851 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC		 4852 const char *name_pre = priv->cfg->fw_name_pre;
4853 const unsigned int api_max = priv->cfg->ucode_api_max;
4854 const unsigned int api_min = priv->cfg->ucode_api_min;
4855 char buf[25];
b481de9c
ZY		 4856 u8 *src;
4857 size_t len;
a0987a8d 4858 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY		 4859
4860 /* Ask kernel firmware_class module to get the boot firmware off disk.
4861 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC		 4862 for (index = api_max; index >= api_min; index--) {
4863 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
4864 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
4865 if (ret < 0) {
15b1687c 4866 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC		 4867 buf, ret);
4868 if (ret == -ENOENT)
4869 continue;
4870 else
4871 goto error;
4872 } else {
4873 if (index < api_max)
15b1687c
WT		 4874 IWL_ERR(priv, "Loaded firmware %s, "
4875 "which is deprecated. "
4876 " Please use API v%u instead.\n",
a0987a8d
RC		 4877 buf, api_max);
4878 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
4879 buf, ucode_raw->size);
4880 break;
4881 }
b481de9c
ZY		 4882 }
4883
a0987a8d
RC		 4884 if (ret < 0)
4885 goto error;
b481de9c
ZY		 4886
4887 /* Make sure that we got at least our header! */
4888 if (ucode_raw->size < sizeof(*ucode)) {
15b1687c 4889 IWL_ERR(priv, "File size way too small!\n");
90e759d1 4890 ret = -EINVAL;
b481de9c
ZY		 4891 goto err_release;
4892 }
4893
4894 /* Data from ucode file: header followed by uCode images */
4895 ucode = (void *)ucode_raw->data;
4896
c02b3acd 4897 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 4898 api_ver = IWL_UCODE_API(priv->ucode_ver);
b481de9c
ZY		 4899 inst_size = le32_to_cpu(ucode->inst_size);
4900 data_size = le32_to_cpu(ucode->data_size);
4901 init_size = le32_to_cpu(ucode->init_size);
4902 init_data_size = le32_to_cpu(ucode->init_data_size);
4903 boot_size = le32_to_cpu(ucode->boot_size);
4904
a0987a8d
RC		 4905 /* api_ver should match the api version forming part of the
4906 * firmware filename ... but we don't check for that and only rely
4907 * on the API version read from firware header from here on forward */
4908
4909 if (api_ver < api_min || api_ver > api_max) {
15b1687c 4910 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC		 4911 "Driver supports v%u, firmware is v%u.\n",
4912 api_max, api_ver);
4913 priv->ucode_ver = 0;
4914 ret = -EINVAL;
4915 goto err_release;
4916 }
4917 if (api_ver != api_max)
15b1687c 4918 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
a0987a8d
RC		 4919 "got %u. New firmware can be obtained "
4920 "from http://www.intellinuxwireless.org.\n",
4921 api_max, api_ver);
4922
978785a3
TW		 4923 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
4924 IWL_UCODE_MAJOR(priv->ucode_ver),
4925 IWL_UCODE_MINOR(priv->ucode_ver),
4926 IWL_UCODE_API(priv->ucode_ver),
4927 IWL_UCODE_SERIAL(priv->ucode_ver));
4928
a0987a8d
RC		 4929 IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
4930 priv->ucode_ver);
bc434dd2
IS		 4931 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
4932 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
4933 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
4934 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
4935 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
b481de9c 4936
a0987a8d 4937
b481de9c
ZY		 4938 /* Verify size of file vs. image size info in file's header */
4939 if (ucode_raw->size < sizeof(*ucode) +
4940 inst_size + data_size + init_size +
4941 init_data_size + boot_size) {
4942
4943 IWL_DEBUG_INFO("uCode file size %d too small\n",
4944 (int)ucode_raw->size);
90e759d1 4945 ret = -EINVAL;
b481de9c
ZY		 4946 goto err_release;
4947 }
4948
4949 /* Verify that uCode images will fit in card's SRAM */
250bdd21 4950 if (inst_size > IWL39_MAX_INST_SIZE) {
90e759d1
TW		 4951 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
4952 inst_size);
4953 ret = -EINVAL;
b481de9c
ZY		 4954 goto err_release;
4955 }
4956
250bdd21 4957 if (data_size > IWL39_MAX_DATA_SIZE) {
90e759d1
TW		 4958 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
4959 data_size);
4960 ret = -EINVAL;
b481de9c
ZY		 4961 goto err_release;
4962 }
250bdd21 4963 if (init_size > IWL39_MAX_INST_SIZE) {
90e759d1
TW		 4964 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
4965 init_size);
4966 ret = -EINVAL;
b481de9c
ZY		 4967 goto err_release;
4968 }
250bdd21 4969 if (init_data_size > IWL39_MAX_DATA_SIZE) {
90e759d1
TW		 4970 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
4971 init_data_size);
4972 ret = -EINVAL;
b481de9c
ZY		 4973 goto err_release;
4974 }
250bdd21 4975 if (boot_size > IWL39_MAX_BSM_SIZE) {
90e759d1
TW		 4976 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
4977 boot_size);
4978 ret = -EINVAL;
b481de9c
ZY		 4979 goto err_release;
4980 }
4981
4982 /* Allocate ucode buffers for card's bus-master loading ... */
4983
4984 /* Runtime instructions and 2 copies of data:
4985 * 1) unmodified from disk
4986 * 2) backup cache for save/restore during power-downs */
4987 priv->ucode_code.len = inst_size;
98c92211 4988 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 4989
4990 priv->ucode_data.len = data_size;
98c92211 4991 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 4992
4993 priv->ucode_data_backup.len = data_size;
98c92211 4994 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 4995
90e759d1
TW		 4996 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
4997 !priv->ucode_data_backup.v_addr)
4998 goto err_pci_alloc;
b481de9c
ZY		 4999
5000 /* Initialization instructions and data */
90e759d1
TW		 5001 if (init_size && init_data_size) {
5002 priv->ucode_init.len = init_size;
98c92211 5003 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 5004
5005 priv->ucode_init_data.len = init_data_size;
98c92211 5006 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 5007
5008 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5009 goto err_pci_alloc;
5010 }
b481de9c
ZY		 5011
5012 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 5013 if (boot_size) {
5014 priv->ucode_boot.len = boot_size;
98c92211 5015 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5016
90e759d1
TW		 5017 if (!priv->ucode_boot.v_addr)
5018 goto err_pci_alloc;
5019 }
b481de9c
ZY		 5020
5021 /* Copy images into buffers for card's bus-master reads ... */
5022
5023 /* Runtime instructions (first block of data in file) */
5024 src = &ucode->data[0];
5025 len = priv->ucode_code.len;
90e759d1 5026 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 5027 memcpy(priv->ucode_code.v_addr, src, len);
5028 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5029 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5030
5031 /* Runtime data (2nd block)
bb8c093b 5032 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
b481de9c
ZY		 5033 src = &ucode->data[inst_size];
5034 len = priv->ucode_data.len;
90e759d1 5035 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 5036 memcpy(priv->ucode_data.v_addr, src, len);
5037 memcpy(priv->ucode_data_backup.v_addr, src, len);
5038
5039 /* Initialization instructions (3rd block) */
5040 if (init_size) {
5041 src = &ucode->data[inst_size + data_size];
5042 len = priv->ucode_init.len;
90e759d1
TW		 5043 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5044 len);
b481de9c
ZY		 5045 memcpy(priv->ucode_init.v_addr, src, len);
5046 }
5047
5048 /* Initialization data (4th block) */
5049 if (init_data_size) {
5050 src = &ucode->data[inst_size + data_size + init_size];
5051 len = priv->ucode_init_data.len;
5052 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5053 (int)len);
5054 memcpy(priv->ucode_init_data.v_addr, src, len);
5055 }
5056
5057 /* Bootstrap instructions (5th block) */
5058 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5059 len = priv->ucode_boot.len;
5060 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5061 (int)len);
5062 memcpy(priv->ucode_boot.v_addr, src, len);
5063
5064 /* We have our copies now, allow OS release its copies */
5065 release_firmware(ucode_raw);
5066 return 0;
5067
5068 err_pci_alloc:
15b1687c 5069 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 5070 ret = -ENOMEM;
bb8c093b 5071 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 5072
5073 err_release:
5074 release_firmware(ucode_raw);
5075
5076 error:
90e759d1 5077 return ret;
b481de9c
ZY		 5078}
5079
5080
5081/**
bb8c093b 5082 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 5083 *
5084 * Tell initialization uCode where to find runtime uCode.
5085 *
5086 * BSM registers initially contain pointers to initialization uCode.
5087 * We need to replace them to load runtime uCode inst and data,
5088 * and to save runtime data when powering down.
5089 */
4a8a4322 5090static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY		 5091{
5092 dma_addr_t pinst;
5093 dma_addr_t pdata;
5094 int rc = 0;
5095 unsigned long flags;
5096
5097 /* bits 31:0 for 3945 */
5098 pinst = priv->ucode_code.p_addr;
5099 pdata = priv->ucode_data_backup.p_addr;
5100
5101 spin_lock_irqsave(&priv->lock, flags);
5d49f498 5102 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 5103 if (rc) {
5104 spin_unlock_irqrestore(&priv->lock, flags);
5105 return rc;
5106 }
5107
5108 /* Tell bootstrap uCode where to find image to load */
5d49f498
AK		 5109 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5110 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5111 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 5112 priv->ucode_data.len);
5113
a96a27f9 5114 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 5115 * that all new ptr/size info is in place */
5d49f498 5116 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 5117 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5118
5d49f498 5119 iwl_release_nic_access(priv);
b481de9c
ZY		 5120
5121 spin_unlock_irqrestore(&priv->lock, flags);
5122
5123 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5124
5125 return rc;
5126}
5127
5128/**
bb8c093b 5129 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 5130 *
5131 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5132 *
b481de9c 5133 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 5134 */
4a8a4322 5135static void iwl3945_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY		 5136{
5137 /* Check alive response for "valid" sign from uCode */
5138 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5139 /* We had an error bringing up the hardware, so take it
5140 * all the way back down so we can try again */
5141 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5142 goto restart;
5143 }
5144
5145 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5146 * This is a paranoid check, because we would not have gotten the
5147 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5148 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5149 /* Runtime instruction load was bad;
5150 * take it all the way back down so we can try again */
5151 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5152 goto restart;
5153 }
5154
5155 /* Send pointers to protocol/runtime uCode image ... init code will
5156 * load and launch runtime uCode, which will send us another "Alive"
5157 * notification. */
5158 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5159 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY		 5160 /* Runtime instruction load won't happen;
5161 * take it all the way back down so we can try again */
5162 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5163 goto restart;
5164 }
5165 return;
5166
5167 restart:
5168 queue_work(priv->workqueue, &priv->restart);
5169}
5170
5171
9bdf5eca
MA		 5172/* temporary */
5173static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
5174 struct sk_buff *skb);
5175
b481de9c 5176/**
bb8c093b 5177 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 5178 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5179 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 5180 */
4a8a4322 5181static void iwl3945_alive_start(struct iwl_priv *priv)
b481de9c
ZY		 5182{
5183 int rc = 0;
5184 int thermal_spin = 0;
5185 u32 rfkill;
5186
5187 IWL_DEBUG_INFO("Runtime Alive received.\n");
5188
5189 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5190 /* We had an error bringing up the hardware, so take it
5191 * all the way back down so we can try again */
5192 IWL_DEBUG_INFO("Alive failed.\n");
5193 goto restart;
5194 }
5195
5196 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5197 * This is a paranoid check, because we would not have gotten the
5198 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5199 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY		 5200 /* Runtime instruction load was bad;
5201 * take it all the way back down so we can try again */
5202 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5203 goto restart;
5204 }
5205
bb8c093b 5206 iwl3945_clear_stations_table(priv);
b481de9c 5207
5d49f498 5208 rc = iwl_grab_nic_access(priv);
b481de9c 5209 if (rc) {
39aadf8c 5210 IWL_WARN(priv, "Can not read RFKILL status from adapter\n");
b481de9c
ZY		 5211 return;
5212 }
5213
5d49f498 5214 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
b481de9c 5215 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
5d49f498 5216 iwl_release_nic_access(priv);
b481de9c
ZY		 5217
5218 if (rfkill & 0x1) {
5219 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 5220 /* if RFKILL is not on, then wait for thermal
b481de9c 5221 * sensor in adapter to kick in */
bb8c093b 5222 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY		 5223 thermal_spin++;
5224 udelay(10);
5225 }
5226
5227 if (thermal_spin)
5228 IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5229 thermal_spin * 10);
5230 } else
5231 set_bit(STATUS_RF_KILL_HW, &priv->status);
5232
9fbab516 5233 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY		 5234 set_bit(STATUS_ALIVE, &priv->status);
5235
5236 /* Clear out the uCode error bit if it is set */
5237 clear_bit(STATUS_FW_ERROR, &priv->status);
5238
775a6e27 5239 if (iwl_is_rfkill(priv))
b481de9c
ZY		 5240 return;
5241
36d6825b 5242 ieee80211_wake_queues(priv->hw);
b481de9c
ZY		 5243
5244 priv->active_rate = priv->rates_mask;
5245 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5246
bb8c093b 5247 iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5248
bb8c093b
CH		 5249 if (iwl3945_is_associated(priv)) {
5250 struct iwl3945_rxon_cmd *active_rxon =
f2c7e521 5251 (struct iwl3945_rxon_cmd *)(&priv->active39_rxon);
b481de9c 5252
f2c7e521
AK		 5253 memcpy(&priv->staging39_rxon, &priv->active39_rxon,
5254 sizeof(priv->staging39_rxon));
b481de9c
ZY		 5255 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5256 } else {
5257 /* Initialize our rx_config data */
60294de3 5258 iwl3945_connection_init_rx_config(priv, priv->iw_mode);
f2c7e521 5259 memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
b481de9c
ZY		 5260 }
5261
9fbab516 5262 /* Configure Bluetooth device coexistence support */
bb8c093b 5263 iwl3945_send_bt_config(priv);
b481de9c
ZY		 5264
5265 /* Configure the adapter for unassociated operation */
bb8c093b 5266 iwl3945_commit_rxon(priv);
b481de9c 5267
b481de9c
ZY		 5268 iwl3945_reg_txpower_periodic(priv);
5269
fe00b5a5
RC		 5270 iwl3945_led_register(priv);
5271
b481de9c 5272 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5273 set_bit(STATUS_READY, &priv->status);
5a66926a 5274 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 5275
5276 if (priv->error_recovering)
bb8c093b 5277 iwl3945_error_recovery(priv);
b481de9c 5278
9bdf5eca
MA		 5279 /* reassociate for ADHOC mode */
5280 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
5281 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
5282 priv->vif);
5283 if (beacon)
5284 iwl3945_mac_beacon_update(priv->hw, beacon);
5285 }
5286
b481de9c
ZY		 5287 return;
5288
5289 restart:
5290 queue_work(priv->workqueue, &priv->restart);
5291}
5292
4a8a4322 5293static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 5294
4a8a4322 5295static void __iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY		 5296{
5297 unsigned long flags;
5298 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5299 struct ieee80211_conf *conf = NULL;
5300
5301 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5302
5303 conf = ieee80211_get_hw_conf(priv->hw);
5304
5305 if (!exit_pending)
5306 set_bit(STATUS_EXIT_PENDING, &priv->status);
5307
ab53d8af 5308 iwl3945_led_unregister(priv);
bb8c093b 5309 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5310
5311 /* Unblock any waiting calls */
5312 wake_up_interruptible_all(&priv->wait_command_queue);
5313
b481de9c
ZY		 5314 /* Wipe out the EXIT_PENDING status bit if we are not actually
5315 * exiting the module */
5316 if (!exit_pending)
5317 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5318
5319 /* stop and reset the on-board processor */
5d49f498 5320 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 5321
5322 /* tell the device to stop sending interrupts */
0359facc 5323 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5324 iwl3945_disable_interrupts(priv);
0359facc
MA		 5325 spin_unlock_irqrestore(&priv->lock, flags);
5326 iwl_synchronize_irq(priv);
b481de9c
ZY		 5327
5328 if (priv->mac80211_registered)
5329 ieee80211_stop_queues(priv->hw);
5330
bb8c093b 5331 /* If we have not previously called iwl3945_init() then
b481de9c 5332 * clear all bits but the RF Kill and SUSPEND bits and return */
775a6e27 5333 if (!iwl_is_init(priv)) {
b481de9c
ZY		 5334 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5335 STATUS_RF_KILL_HW |
5336 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5337 STATUS_RF_KILL_SW |
9788864e
RC		 5338 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5339 STATUS_GEO_CONFIGURED |
b481de9c 5340 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
ebef2008
AK		 5341 STATUS_IN_SUSPEND |
5342 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5343 STATUS_EXIT_PENDING;
b481de9c
ZY		 5344 goto exit;
5345 }
5346
5347 /* ...otherwise clear out all the status bits but the RF Kill and
5348 * SUSPEND bits and continue taking the NIC down. */
5349 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5350 STATUS_RF_KILL_HW |
5351 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5352 STATUS_RF_KILL_SW |
9788864e
RC		 5353 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5354 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5355 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5356 STATUS_IN_SUSPEND |
5357 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK		 5358 STATUS_FW_ERROR |
5359 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5360 STATUS_EXIT_PENDING;
b481de9c
ZY		 5361
5362 spin_lock_irqsave(&priv->lock, flags);
5d49f498 5363 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 5364 spin_unlock_irqrestore(&priv->lock, flags);
5365
bb8c093b
CH		 5366 iwl3945_hw_txq_ctx_stop(priv);
5367 iwl3945_hw_rxq_stop(priv);
b481de9c
ZY		 5368
5369 spin_lock_irqsave(&priv->lock, flags);
5d49f498
AK		 5370 if (!iwl_grab_nic_access(priv)) {
5371 iwl_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5372 APMG_CLK_VAL_DMA_CLK_RQT);
5d49f498 5373 iwl_release_nic_access(priv);
b481de9c
ZY		 5374 }
5375 spin_unlock_irqrestore(&priv->lock, flags);
5376
5377 udelay(5);
5378
01ec616d 5379 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 5380 exit:
3d24a9f7 5381 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY		 5382
5383 if (priv->ibss_beacon)
5384 dev_kfree_skb(priv->ibss_beacon);
5385 priv->ibss_beacon = NULL;
5386
5387 /* clear out any free frames */
bb8c093b 5388 iwl3945_clear_free_frames(priv);
b481de9c
ZY		 5389}
5390
4a8a4322 5391static void iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY		 5392{
5393 mutex_lock(&priv->mutex);
bb8c093b 5394 __iwl3945_down(priv);
b481de9c 5395 mutex_unlock(&priv->mutex);
b24d22b1 5396
bb8c093b 5397 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY		 5398}
5399
5400#define MAX_HW_RESTARTS 5
5401
4a8a4322 5402static int __iwl3945_up(struct iwl_priv *priv)
b481de9c
ZY		 5403{
5404 int rc, i;
5405
5406 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 5407 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 5408 return -EIO;
5409 }
5410
5411 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
39aadf8c 5412 IWL_WARN(priv, "Radio disabled by SW RF kill (module "
b481de9c 5413 "parameter)\n");
e655b9f0
ZY		 5414 return -ENODEV;
5415 }
5416
e903fbd4 5417 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 5418 IWL_ERR(priv, "ucode not available for device bring up\n");
e903fbd4
RC		 5419 return -EIO;
5420 }
5421
e655b9f0 5422 /* If platform's RF_KILL switch is NOT set to KILL */
5d49f498 5423 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY		 5424 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5425 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5426 else {
5427 set_bit(STATUS_RF_KILL_HW, &priv->status);
5428 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
39aadf8c 5429 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
e655b9f0
ZY		 5430 return -ENODEV;
5431 }
b481de9c 5432 }
80fcc9e2 5433
5d49f498 5434 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 5435
bb8c093b 5436 rc = iwl3945_hw_nic_init(priv);
b481de9c 5437 if (rc) {
15b1687c 5438 IWL_ERR(priv, "Unable to int nic\n");
b481de9c
ZY		 5439 return rc;
5440 }
5441
5442 /* make sure rfkill handshake bits are cleared */
5d49f498
AK		 5443 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5444 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 5445 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5446
5447 /* clear (again), then enable host interrupts */
5d49f498 5448 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
bb8c093b 5449 iwl3945_enable_interrupts(priv);
b481de9c
ZY		 5450
5451 /* really make sure rfkill handshake bits are cleared */
5d49f498
AK		 5452 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5453 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 5454
5455 /* Copy original ucode data image from disk into backup cache.
5456 * This will be used to initialize the on-board processor's
5457 * data SRAM for a clean start when the runtime program first loads. */
5458 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 5459 priv->ucode_data.len);
b481de9c 5460
e655b9f0
ZY		 5461 /* We return success when we resume from suspend and rf_kill is on. */
5462 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
5463 return 0;
5464
b481de9c
ZY		 5465 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5466
bb8c093b 5467 iwl3945_clear_stations_table(priv);
b481de9c
ZY		 5468
5469 /* load bootstrap state machine,
5470 * load bootstrap program into processor's memory,
5471 * prepare to load the "initialize" uCode */
0164b9b4 5472 priv->cfg->ops->lib->load_ucode(priv);
b481de9c
ZY		 5473
5474 if (rc) {
15b1687c
WT		 5475 IWL_ERR(priv,
5476 "Unable to set up bootstrap uCode: %d\n", rc);
b481de9c
ZY		 5477 continue;
5478 }
5479
5480 /* start card; "initialize" will load runtime ucode */
bb8c093b 5481 iwl3945_nic_start(priv);
b481de9c 5482
b481de9c
ZY		 5483 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
5484
5485 return 0;
5486 }
5487
5488 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 5489 __iwl3945_down(priv);
ebef2008 5490 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 5491
5492 /* tried to restart and config the device for as long as our
5493 * patience could withstand */
15b1687c 5494 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY		 5495 return -EIO;
5496}
5497
5498
5499/*****************************************************************************
5500 *
5501 * Workqueue callbacks
5502 *
5503 *****************************************************************************/
5504
bb8c093b 5505static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 5506{
4a8a4322
AK		 5507 struct iwl_priv *priv =
5508 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 5509
5510 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5511 return;
5512
5513 mutex_lock(&priv->mutex);
bb8c093b 5514 iwl3945_init_alive_start(priv);
b481de9c
ZY		 5515 mutex_unlock(&priv->mutex);
5516}
5517
bb8c093b 5518static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 5519{
4a8a4322
AK		 5520 struct iwl_priv *priv =
5521 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 5522
5523 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5524 return;
5525
5526 mutex_lock(&priv->mutex);
bb8c093b 5527 iwl3945_alive_start(priv);
b481de9c
ZY		 5528 mutex_unlock(&priv->mutex);
5529}
5530
bb8c093b 5531static void iwl3945_bg_rf_kill(struct work_struct *work)
b481de9c 5532{
4a8a4322 5533 struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill);
b481de9c
ZY		 5534
5535 wake_up_interruptible(&priv->wait_command_queue);
5536
5537 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5538 return;
5539
5540 mutex_lock(&priv->mutex);
5541
775a6e27 5542 if (!iwl_is_rfkill(priv)) {
b481de9c
ZY		 5543 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
5544 "HW and/or SW RF Kill no longer active, restarting "
5545 "device\n");
5546 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
5547 queue_work(priv->workqueue, &priv->restart);
5548 } else {
5549
5550 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
5551 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
5552 "disabled by SW switch\n");
5553 else
39aadf8c 5554 IWL_WARN(priv, "Radio Frequency Kill Switch is On:\n"
b481de9c
ZY		 5555 "Kill switch must be turned off for "
5556 "wireless networking to work.\n");
5557 }
ebef2008 5558
b481de9c 5559 mutex_unlock(&priv->mutex);
80fcc9e2 5560 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 5561}
5562
5563#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
5564
bb8c093b 5565static void iwl3945_bg_scan_check(struct work_struct *data)
b481de9c 5566{
4a8a4322
AK		 5567 struct iwl_priv *priv =
5568 container_of(data, struct iwl_priv, scan_check.work);
b481de9c
ZY		 5569
5570 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5571 return;
5572
5573 mutex_lock(&priv->mutex);
5574 if (test_bit(STATUS_SCANNING, &priv->status) ||
5575 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
5576 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
5577 "Scan completion watchdog resetting adapter (%dms)\n",
5578 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
15e869d8 5579
b481de9c 5580 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 5581 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 5582 }
5583 mutex_unlock(&priv->mutex);
5584}
5585
bb8c093b 5586static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 5587{
4a8a4322
AK		 5588 struct iwl_priv *priv =
5589 container_of(data, struct iwl_priv, request_scan);
c2d79b48 5590 struct iwl_host_cmd cmd = {
b481de9c 5591 .id = REPLY_SCAN_CMD,
bb8c093b 5592 .len = sizeof(struct iwl3945_scan_cmd),
b481de9c
ZY		 5593 .meta.flags = CMD_SIZE_HUGE,
5594 };
5595 int rc = 0;
bb8c093b 5596 struct iwl3945_scan_cmd *scan;
b481de9c 5597 struct ieee80211_conf *conf = NULL;
f9340520 5598 u8 n_probes = 2;
8318d78a 5599 enum ieee80211_band band;
9387b7ca 5600 DECLARE_SSID_BUF(ssid);
b481de9c
ZY		 5601
5602 conf = ieee80211_get_hw_conf(priv->hw);
5603
5604 mutex_lock(&priv->mutex);
5605
775a6e27 5606 if (!iwl_is_ready(priv)) {
39aadf8c 5607 IWL_WARN(priv, "request scan called when driver not ready.\n");
b481de9c
ZY		 5608 goto done;
5609 }
5610
a96a27f9 5611 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY		 5612 * was given the chance to run... */
5613 if (!test_bit(STATUS_SCANNING, &priv->status))
5614 goto done;
5615
5616 /* This should never be called or scheduled if there is currently
5617 * a scan active in the hardware. */
5618 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
5619 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
5620 "Ignoring second request.\n");
5621 rc = -EIO;
5622 goto done;
5623 }
5624
5625 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5626 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
5627 goto done;
5628 }
5629
5630 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
5631 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
5632 goto done;
5633 }
5634
775a6e27 5635 if (iwl_is_rfkill(priv)) {
b481de9c
ZY		 5636 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
5637 goto done;
5638 }
5639
5640 if (!test_bit(STATUS_READY, &priv->status)) {
5641 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
5642 goto done;
5643 }
5644
5645 if (!priv->scan_bands) {
5646 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
5647 goto done;
5648 }
5649
f2c7e521
AK		 5650 if (!priv->scan39) {
5651 priv->scan39 = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c 5652 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
f2c7e521 5653 if (!priv->scan39) {
b481de9c
ZY		 5654 rc = -ENOMEM;
5655 goto done;
5656 }
5657 }
f2c7e521 5658 scan = priv->scan39;
bb8c093b 5659 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 5660
5661 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
5662 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
5663
bb8c093b 5664 if (iwl3945_is_associated(priv)) {
b481de9c
ZY		 5665 u16 interval = 0;
5666 u32 extra;
5667 u32 suspend_time = 100;
5668 u32 scan_suspend_time = 100;
5669 unsigned long flags;
5670
5671 IWL_DEBUG_INFO("Scanning while associated...\n");
5672
5673 spin_lock_irqsave(&priv->lock, flags);
5674 interval = priv->beacon_int;
5675 spin_unlock_irqrestore(&priv->lock, flags);
5676
5677 scan->suspend_time = 0;
15e869d8 5678 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 5679 if (!interval)
5680 interval = suspend_time;
5681 /*
5682 * suspend time format:
5683 * 0-19: beacon interval in usec (time before exec.)
5684 * 20-23: 0
5685 * 24-31: number of beacons (suspend between channels)
5686 */
5687
5688 extra = (suspend_time / interval) << 24;
5689 scan_suspend_time = 0xFF0FFFFF &
5690 (extra | ((suspend_time % interval) * 1024));
5691
5692 scan->suspend_time = cpu_to_le32(scan_suspend_time);
5693 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
5694 scan_suspend_time, interval);
5695 }
5696
5697 /* We should add the ability for user to lock to PASSIVE ONLY */
5698 if (priv->one_direct_scan) {
5699 IWL_DEBUG_SCAN
5700 ("Kicking off one direct scan for '%s'\n",
9387b7ca
JL		 5701 print_ssid(ssid, priv->direct_ssid,
5702 priv->direct_ssid_len));
b481de9c
ZY		 5703 scan->direct_scan[0].id = WLAN_EID_SSID;
5704 scan->direct_scan[0].len = priv->direct_ssid_len;
5705 memcpy(scan->direct_scan[0].ssid,
5706 priv->direct_ssid, priv->direct_ssid_len);
f9340520 5707 n_probes++;
f9340520 5708 } else
786b4557 5709 IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
b481de9c
ZY		 5710
5711 /* We don't build a direct scan probe request; the uCode will do
5712 * that based on the direct_mask added to each channel entry */
5713 scan->tx_cmd.len = cpu_to_le16(
bb8c093b 5714 iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
430cfe95 5715 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
b481de9c 5716 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
3832ec9d 5717 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 5718 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
5719
5720 /* flags + rate selection */
5721
66b5004d 5722 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY		 5723 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
5724 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
5725 scan->good_CRC_th = 0;
8318d78a 5726 band = IEEE80211_BAND_2GHZ;
66b5004d 5727 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c
ZY		 5728 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
5729 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 5730 band = IEEE80211_BAND_5GHZ;
66b5004d 5731 } else {
39aadf8c 5732 IWL_WARN(priv, "Invalid scan band count\n");
b481de9c
ZY		 5733 goto done;
5734 }
5735
5736 /* select Rx antennas */
5737 scan->flags |= iwl3945_get_antenna_flags(priv);
5738
05c914fe 5739 if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
b481de9c
ZY		 5740 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
5741
f9340520
AK		 5742 scan->channel_count =
5743 iwl3945_get_channels_for_scan(priv, band, 1, /* active */
5744 n_probes,
5745 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 5746
14b54336
RC		 5747 if (scan->channel_count == 0) {
5748 IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
5749 goto done;
5750 }
5751
b481de9c 5752 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 5753 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY		 5754 cmd.data = scan;
5755 scan->len = cpu_to_le16(cmd.len);
5756
5757 set_bit(STATUS_SCAN_HW, &priv->status);
bb8c093b 5758 rc = iwl3945_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 5759 if (rc)
5760 goto done;
5761
5762 queue_delayed_work(priv->workqueue, &priv->scan_check,
5763 IWL_SCAN_CHECK_WATCHDOG);
5764
5765 mutex_unlock(&priv->mutex);
5766 return;
5767
5768 done:
2420ebc1
MA		 5769 /* can not perform scan make sure we clear scanning
5770 * bits from status so next scan request can be performed.
5771 * if we dont clear scanning status bit here all next scan
5772 * will fail
5773 */
5774 clear_bit(STATUS_SCAN_HW, &priv->status);
5775 clear_bit(STATUS_SCANNING, &priv->status);
5776
01ebd063 5777 /* inform mac80211 scan aborted */
b481de9c
ZY		 5778 queue_work(priv->workqueue, &priv->scan_completed);
5779 mutex_unlock(&priv->mutex);
5780}
5781
bb8c093b 5782static void iwl3945_bg_up(struct work_struct *data)
b481de9c 5783{
4a8a4322 5784 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY		 5785
5786 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5787 return;
5788
5789 mutex_lock(&priv->mutex);
bb8c093b 5790 __iwl3945_up(priv);
b481de9c 5791 mutex_unlock(&priv->mutex);
80fcc9e2 5792 iwl3945_rfkill_set_hw_state(priv);
b481de9c
ZY		 5793}
5794
bb8c093b 5795static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 5796{
4a8a4322 5797 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 5798
5799 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5800 return;
5801
bb8c093b 5802 iwl3945_down(priv);
b481de9c
ZY		 5803 queue_work(priv->workqueue, &priv->up);
5804}
5805
bb8c093b 5806static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 5807{
4a8a4322
AK		 5808 struct iwl_priv *priv =
5809 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 5810
5811 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5812 return;
5813
5814 mutex_lock(&priv->mutex);
bb8c093b 5815 iwl3945_rx_replenish(priv);
b481de9c
ZY		 5816 mutex_unlock(&priv->mutex);
5817}
5818
7878a5a4
MA		 5819#define IWL_DELAY_NEXT_SCAN (HZ*2)
5820
4a8a4322 5821static void iwl3945_post_associate(struct iwl_priv *priv)
b481de9c 5822{
b481de9c
ZY		 5823 int rc = 0;
5824 struct ieee80211_conf *conf = NULL;
5825
05c914fe 5826 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 5827 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 5828 return;
5829 }
5830
5831
e174961c 5832 IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
f2c7e521 5833 priv->assoc_id, priv->active39_rxon.bssid_addr);
b481de9c
ZY		 5834
5835 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5836 return;
5837
322a9811 5838 if (!priv->vif || !priv->is_open)
6ef89d0a 5839 return;
322a9811 5840
bb8c093b 5841 iwl3945_scan_cancel_timeout(priv, 200);
15e869d8 5842
b481de9c
ZY		 5843 conf = ieee80211_get_hw_conf(priv->hw);
5844
f2c7e521 5845 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 5846 iwl3945_commit_rxon(priv);
b481de9c 5847
28afaf91 5848 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
bb8c093b
CH		 5849 iwl3945_setup_rxon_timing(priv);
5850 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 5851 sizeof(priv->rxon_timing), &priv->rxon_timing);
5852 if (rc)
39aadf8c 5853 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY		 5854 "Attempting to continue.\n");
5855
f2c7e521 5856 priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 5857
f2c7e521 5858 priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c
ZY		 5859
5860 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
5861 priv->assoc_id, priv->beacon_int);
5862
5863 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
f2c7e521 5864 priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 5865 else
f2c7e521 5866 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 5867
f2c7e521 5868 if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c 5869 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
f2c7e521 5870 priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 5871 else
f2c7e521 5872 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 5873
05c914fe 5874 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
f2c7e521 5875 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 5876
5877 }
5878
bb8c093b 5879 iwl3945_commit_rxon(priv);
b481de9c
ZY		 5880
5881 switch (priv->iw_mode) {
05c914fe 5882 case NL80211_IFTYPE_STATION:
bb8c093b 5883 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 5884 break;
5885
05c914fe 5886 case NL80211_IFTYPE_ADHOC:
b481de9c 5887
ce546fd2 5888 priv->assoc_id = 1;
bb8c093b 5889 iwl3945_add_station(priv, priv->bssid, 0, 0);
b481de9c 5890 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 5891 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY		 5892 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
5893 CMD_ASYNC);
bb8c093b
CH		 5894 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
5895 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 5896
5897 break;
5898
5899 default:
15b1687c 5900 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 5901 __func__, priv->iw_mode);
b481de9c
ZY		 5902 break;
5903 }
5904
bb8c093b 5905 iwl3945_activate_qos(priv, 0);
292ae174 5906
7878a5a4
MA		 5907 /* we have just associated, don't start scan too early */
5908 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK		 5909}
5910
bb8c093b 5911static void iwl3945_bg_abort_scan(struct work_struct *work)
b481de9c 5912{
4a8a4322 5913 struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan);
b481de9c 5914
775a6e27 5915 if (!iwl_is_ready(priv))
b481de9c
ZY		 5916 return;
5917
5918 mutex_lock(&priv->mutex);
5919
5920 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 5921 iwl3945_send_scan_abort(priv);
b481de9c
ZY		 5922
5923 mutex_unlock(&priv->mutex);
5924}
5925
e8975581 5926static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
76bb77e0 5927
bb8c093b 5928static void iwl3945_bg_scan_completed(struct work_struct *work)
b481de9c 5929{
4a8a4322
AK		 5930 struct iwl_priv *priv =
5931 container_of(work, struct iwl_priv, scan_completed);
b481de9c
ZY		 5932
5933 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
5934
5935 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5936 return;
5937
a0646470 5938 if (test_bit(STATUS_CONF_PENDING, &priv->status))
e8975581 5939 iwl3945_mac_config(priv->hw, 0);
76bb77e0 5940
b481de9c
ZY		 5941 ieee80211_scan_completed(priv->hw);
5942
5943 /* Since setting the TXPOWER may have been deferred while
5944 * performing the scan, fire one off */
5945 mutex_lock(&priv->mutex);
bb8c093b 5946 iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 5947 mutex_unlock(&priv->mutex);
5948}
5949
5950/*****************************************************************************
5951 *
5952 * mac80211 entry point functions
5953 *
5954 *****************************************************************************/
5955
5a66926a
ZY		 5956#define UCODE_READY_TIMEOUT (2 * HZ)
5957
bb8c093b 5958static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 5959{
4a8a4322 5960 struct iwl_priv *priv = hw->priv;
5a66926a 5961 int ret;
b481de9c
ZY		 5962
5963 IWL_DEBUG_MAC80211("enter\n");
5964
5a66926a 5965 if (pci_enable_device(priv->pci_dev)) {
15b1687c 5966 IWL_ERR(priv, "Fail to pci_enable_device\n");
5a66926a
ZY		 5967 return -ENODEV;
5968 }
5969 pci_restore_state(priv->pci_dev);
5970 pci_enable_msi(priv->pci_dev);
5971
5972 ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
5973 DRV_NAME, priv);
5974 if (ret) {
15b1687c 5975 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
5a66926a
ZY		 5976 goto out_disable_msi;
5977 }
5978
b481de9c
ZY		 5979 /* we should be verifying the device is ready to be opened */
5980 mutex_lock(&priv->mutex);
5981
f2c7e521 5982 memset(&priv->staging39_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
5a66926a
ZY		 5983 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
5984 * ucode filename and max sizes are card-specific. */
5985
5986 if (!priv->ucode_code.len) {
5987 ret = iwl3945_read_ucode(priv);
5988 if (ret) {
15b1687c 5989 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a
ZY		 5990 mutex_unlock(&priv->mutex);
5991 goto out_release_irq;
5992 }
5993 }
b481de9c 5994
e655b9f0 5995 ret = __iwl3945_up(priv);
b481de9c
ZY		 5996
5997 mutex_unlock(&priv->mutex);
5a66926a 5998
80fcc9e2
AG		 5999 iwl3945_rfkill_set_hw_state(priv);
6000
e655b9f0
ZY		 6001 if (ret)
6002 goto out_release_irq;
6003
6004 IWL_DEBUG_INFO("Start UP work.\n");
6005
6006 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6007 return 0;
6008
5a66926a
ZY		 6009 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6010 * mac80211 will not be run successfully. */
6011 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6012 test_bit(STATUS_READY, &priv->status),
6013 UCODE_READY_TIMEOUT);
6014 if (!ret) {
6015 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c
WT		 6016 IWL_ERR(priv,
6017 "Wait for START_ALIVE timeout after %dms.\n",
6018 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5a66926a
ZY		 6019 ret = -ETIMEDOUT;
6020 goto out_release_irq;
6021 }
6022 }
6023
e655b9f0 6024 priv->is_open = 1;
b481de9c
ZY		 6025 IWL_DEBUG_MAC80211("leave\n");
6026 return 0;
5a66926a
ZY		 6027
6028out_release_irq:
6029 free_irq(priv->pci_dev->irq, priv);
6030out_disable_msi:
6031 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY		 6032 pci_disable_device(priv->pci_dev);
6033 priv->is_open = 0;
6034 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6035 return ret;
b481de9c
ZY		 6036}
6037
bb8c093b 6038static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 6039{
4a8a4322 6040 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 6041
6042 IWL_DEBUG_MAC80211("enter\n");
6ef89d0a 6043
e655b9f0
ZY		 6044 if (!priv->is_open) {
6045 IWL_DEBUG_MAC80211("leave - skip\n");
6046 return;
6047 }
6048
b481de9c 6049 priv->is_open = 0;
5a66926a 6050
775a6e27 6051 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY		 6052 /* stop mac, cancel any scan request and clear
6053 * RXON_FILTER_ASSOC_MSK BIT
6054 */
5a66926a
ZY		 6055 mutex_lock(&priv->mutex);
6056 iwl3945_scan_cancel_timeout(priv, 100);
fde3571f 6057 mutex_unlock(&priv->mutex);
fde3571f
MA		 6058 }
6059
5a66926a
ZY		 6060 iwl3945_down(priv);
6061
6062 flush_workqueue(priv->workqueue);
6063 free_irq(priv->pci_dev->irq, priv);
6064 pci_disable_msi(priv->pci_dev);
6065 pci_save_state(priv->pci_dev);
6066 pci_disable_device(priv->pci_dev);
6ef89d0a 6067
b481de9c 6068 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6069}
6070
e039fa4a 6071static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6072{
4a8a4322 6073 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 6074
6075 IWL_DEBUG_MAC80211("enter\n");
6076
b481de9c 6077 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 6078 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 6079
e039fa4a 6080 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY		 6081 dev_kfree_skb_any(skb);
6082
6083 IWL_DEBUG_MAC80211("leave\n");
637f8837 6084 return NETDEV_TX_OK;
b481de9c
ZY		 6085}
6086
bb8c093b 6087static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6088 struct ieee80211_if_init_conf *conf)
6089{
4a8a4322 6090 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 6091 unsigned long flags;
6092
32bfd35d 6093 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6094
32bfd35d
JB		 6095 if (priv->vif) {
6096 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
864792e3 6097 return -EOPNOTSUPP;
b481de9c
ZY		 6098 }
6099
6100 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6101 priv->vif = conf->vif;
60294de3 6102 priv->iw_mode = conf->type;
b481de9c
ZY		 6103
6104 spin_unlock_irqrestore(&priv->lock, flags);
6105
6106 mutex_lock(&priv->mutex);
864792e3
TW		 6107
6108 if (conf->mac_addr) {
e174961c 6109 IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
864792e3
TW		 6110 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6111 }
6112
775a6e27 6113 if (iwl_is_ready(priv))
5a66926a 6114 iwl3945_set_mode(priv, conf->type);
b481de9c 6115
b481de9c
ZY		 6116 mutex_unlock(&priv->mutex);
6117
5a66926a 6118 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6119 return 0;
6120}
6121
6122/**
bb8c093b 6123 * iwl3945_mac_config - mac80211 config callback
b481de9c
ZY		 6124 *
6125 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6126 * be set inappropriately and the driver currently sets the hardware up to
6127 * use it whenever needed.
6128 */
e8975581 6129static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
b481de9c 6130{
4a8a4322 6131 struct iwl_priv *priv = hw->priv;
d20b3c65 6132 const struct iwl_channel_info *ch_info;
e8975581 6133 struct ieee80211_conf *conf = &hw->conf;
b481de9c 6134 unsigned long flags;
76bb77e0 6135 int ret = 0;
b481de9c
ZY		 6136
6137 mutex_lock(&priv->mutex);
8318d78a 6138 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6139
775a6e27 6140 if (!iwl_is_ready(priv)) {
b481de9c 6141 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY		 6142 ret = -EIO;
6143 goto out;
b481de9c
ZY		 6144 }
6145
df878d8f 6146 if (unlikely(!iwl3945_mod_params.disable_hw_scan &&
b481de9c 6147 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY		 6148 IWL_DEBUG_MAC80211("leave - scanning\n");
6149 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6150 mutex_unlock(&priv->mutex);
a0646470 6151 return 0;
b481de9c
ZY		 6152 }
6153
6154 spin_lock_irqsave(&priv->lock, flags);
6155
8318d78a
JB		 6156 ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
6157 conf->channel->hw_value);
b481de9c 6158 if (!is_channel_valid(ch_info)) {
66b5004d 6159 IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
8318d78a 6160 conf->channel->hw_value, conf->channel->band);
b481de9c
ZY		 6161 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6162 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY		 6163 ret = -EINVAL;
6164 goto out;
b481de9c
ZY		 6165 }
6166
8318d78a 6167 iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
b481de9c 6168
8318d78a 6169 iwl3945_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY		 6170
6171 /* The list of supported rates and rate mask can be different
6172 * for each phymode; since the phymode may have changed, reset
6173 * the rate mask to what mac80211 lists */
bb8c093b 6174 iwl3945_set_rate(priv);
b481de9c
ZY		 6175
6176 spin_unlock_irqrestore(&priv->lock, flags);
6177
6178#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6179 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6180 iwl3945_hw_channel_switch(priv, conf->channel);
76bb77e0 6181 goto out;
b481de9c
ZY		 6182 }
6183#endif
6184
bb8c093b 6185 iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 6186
6187 if (!conf->radio_enabled) {
6188 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6189 goto out;
b481de9c
ZY		 6190 }
6191
775a6e27 6192 if (iwl_is_rfkill(priv)) {
b481de9c 6193 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY		 6194 ret = -EIO;
6195 goto out;
b481de9c
ZY		 6196 }
6197
bb8c093b 6198 iwl3945_set_rate(priv);
b481de9c 6199
f2c7e521
AK		 6200 if (memcmp(&priv->active39_rxon,
6201 &priv->staging39_rxon, sizeof(priv->staging39_rxon)))
bb8c093b 6202 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6203 else
6204 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6205
6206 IWL_DEBUG_MAC80211("leave\n");
6207
76bb77e0 6208out:
a0646470 6209 clear_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6210 mutex_unlock(&priv->mutex);
76bb77e0 6211 return ret;
b481de9c
ZY		 6212}
6213
4a8a4322 6214static void iwl3945_config_ap(struct iwl_priv *priv)
b481de9c
ZY		 6215{
6216 int rc = 0;
6217
d986bcd1 6218 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 6219 return;
6220
6221 /* The following should be done only at AP bring up */
5d1e2325 6222 if (!(iwl3945_is_associated(priv))) {
b481de9c
ZY		 6223
6224 /* RXON - unassoc (to set timing command) */
f2c7e521 6225 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6226 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6227
6228 /* RXON Timing */
28afaf91 6229 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
bb8c093b
CH		 6230 iwl3945_setup_rxon_timing(priv);
6231 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY		 6232 sizeof(priv->rxon_timing), &priv->rxon_timing);
6233 if (rc)
39aadf8c 6234 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY		 6235 "Attempting to continue.\n");
6236
6237 /* FIXME: what should be the assoc_id for AP? */
f2c7e521 6238 priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 6239 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
f2c7e521 6240 priv->staging39_rxon.flags |=
b481de9c
ZY		 6241 RXON_FLG_SHORT_PREAMBLE_MSK;
6242 else
f2c7e521 6243 priv->staging39_rxon.flags &=
b481de9c
ZY		 6244 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6245
f2c7e521 6246 if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c
ZY		 6247 if (priv->assoc_capability &
6248 WLAN_CAPABILITY_SHORT_SLOT_TIME)
f2c7e521 6249 priv->staging39_rxon.flags |=
b481de9c
ZY		 6250 RXON_FLG_SHORT_SLOT_MSK;
6251 else
f2c7e521 6252 priv->staging39_rxon.flags &=
b481de9c
ZY		 6253 ~RXON_FLG_SHORT_SLOT_MSK;
6254
05c914fe 6255 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
f2c7e521 6256 priv->staging39_rxon.flags &=
b481de9c
ZY		 6257 ~RXON_FLG_SHORT_SLOT_MSK;
6258 }
6259 /* restore RXON assoc */
f2c7e521 6260 priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b 6261 iwl3945_commit_rxon(priv);
b5323d36 6262 iwl3945_add_station(priv, iwl_bcast_addr, 0, 0);
556f8db7 6263 }
bb8c093b 6264 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY		 6265
6266 /* FIXME - we need to add code here to detect a totally new
6267 * configuration, reset the AP, unassoc, rxon timing, assoc,
6268 * clear sta table, add BCAST sta... */
6269}
6270
32bfd35d
JB		 6271static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
6272 struct ieee80211_vif *vif,
4a8a4322 6273 struct ieee80211_if_conf *conf)
b481de9c 6274{
4a8a4322 6275 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 6276 int rc;
6277
6278 if (conf == NULL)
6279 return -EIO;
6280
b716bb91
EG		 6281 if (priv->vif != vif) {
6282 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
b716bb91
EG		 6283 return 0;
6284 }
6285
9d139c81 6286 /* handle this temporarily here */
05c914fe 6287 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
9d139c81
JB		 6288 conf->changed & IEEE80211_IFCC_BEACON) {
6289 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
6290 if (!beacon)
6291 return -ENOMEM;
9bdf5eca 6292 mutex_lock(&priv->mutex);
9d139c81 6293 rc = iwl3945_mac_beacon_update(hw, beacon);
9bdf5eca 6294 mutex_unlock(&priv->mutex);
9d139c81
JB		 6295 if (rc)
6296 return rc;
6297 }
6298
775a6e27 6299 if (!iwl_is_alive(priv))
5a66926a
ZY		 6300 return -EAGAIN;
6301
b481de9c
ZY		 6302 mutex_lock(&priv->mutex);
6303
b481de9c 6304 if (conf->bssid)
e174961c 6305 IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
b481de9c 6306
4150c572
JB		 6307/*
6308 * very dubious code was here; the probe filtering flag is never set:
6309 *
b481de9c
ZY		 6310 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6311 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6312 */
b481de9c 6313
05c914fe 6314 if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY		 6315 if (!conf->bssid) {
6316 conf->bssid = priv->mac_addr;
6317 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
e174961c
JB		 6318 IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
6319 conf->bssid);
b481de9c
ZY		 6320 }
6321 if (priv->ibss_beacon)
6322 dev_kfree_skb(priv->ibss_beacon);
6323
9d139c81 6324 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
b481de9c
ZY		 6325 }
6326
775a6e27 6327 if (iwl_is_rfkill(priv))
fde3571f
MA		 6328 goto done;
6329
b481de9c
ZY		 6330 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6331 !is_multicast_ether_addr(conf->bssid)) {
6332 /* If there is currently a HW scan going on in the background
6333 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6334 if (iwl3945_scan_cancel_timeout(priv, 100)) {
39aadf8c 6335 IWL_WARN(priv, "Aborted scan still in progress "
b481de9c
ZY		 6336 "after 100ms\n");
6337 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6338 mutex_unlock(&priv->mutex);
6339 return -EAGAIN;
6340 }
f2c7e521 6341 memcpy(priv->staging39_rxon.bssid_addr, conf->bssid, ETH_ALEN);
b481de9c
ZY		 6342
6343 /* TODO: Audit driver for usage of these members and see
6344 * if mac80211 deprecates them (priv->bssid looks like it
6345 * shouldn't be there, but I haven't scanned the IBSS code
6346 * to verify) - jpk */
6347 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6348
05c914fe 6349 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b 6350 iwl3945_config_ap(priv);
b481de9c 6351 else {
bb8c093b 6352 rc = iwl3945_commit_rxon(priv);
05c914fe 6353 if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
bb8c093b 6354 iwl3945_add_station(priv,
f2c7e521 6355 priv->active39_rxon.bssid_addr, 1, 0);
b481de9c
ZY		 6356 }
6357
6358 } else {
bb8c093b 6359 iwl3945_scan_cancel_timeout(priv, 100);
f2c7e521 6360 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6361 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6362 }
6363
fde3571f 6364 done:
b481de9c
ZY		 6365 IWL_DEBUG_MAC80211("leave\n");
6366 mutex_unlock(&priv->mutex);
6367
6368 return 0;
6369}
6370
bb8c093b 6371static void iwl3945_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 6372 unsigned int changed_flags,
6373 unsigned int *total_flags,
6374 int mc_count, struct dev_addr_list *mc_list)
6375{
4a8a4322 6376 struct iwl_priv *priv = hw->priv;
f2c7e521 6377 __le32 *filter_flags = &priv->staging39_rxon.filter_flags;
25b3f57c 6378
352bc8de
ZY		 6379 IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
6380 changed_flags, *total_flags);
6381
6382 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
6383 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
6384 *filter_flags |= RXON_FILTER_PROMISC_MSK;
6385 else
6386 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
6387 }
6388 if (changed_flags & FIF_ALLMULTI) {
6389 if (*total_flags & FIF_ALLMULTI)
6390 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
6391 else
6392 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
6393 }
6394 if (changed_flags & FIF_CONTROL) {
6395 if (*total_flags & FIF_CONTROL)
6396 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
6397 else
6398 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
5ec03976 6399 }
352bc8de
ZY		 6400 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
6401 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
6402 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
6403 else
6404 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
6405 }
6406
6407 /* We avoid iwl_commit_rxon here to commit the new filter flags
6408 * since mac80211 will call ieee80211_hw_config immediately.
6409 * (mc_list is not supported at this time). Otherwise, we need to
6410 * queue a background iwl_commit_rxon work.
6411 */
6412
6413 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
25b3f57c 6414 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4150c572
JB		 6415}
6416
bb8c093b 6417static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6418 struct ieee80211_if_init_conf *conf)
6419{
4a8a4322 6420 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 6421
6422 IWL_DEBUG_MAC80211("enter\n");
6423
6424 mutex_lock(&priv->mutex);
6ef89d0a 6425
775a6e27 6426 if (iwl_is_ready_rf(priv)) {
fde3571f 6427 iwl3945_scan_cancel_timeout(priv, 100);
f2c7e521 6428 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
fde3571f
MA		 6429 iwl3945_commit_rxon(priv);
6430 }
32bfd35d
JB		 6431 if (priv->vif == conf->vif) {
6432 priv->vif = NULL;
b481de9c 6433 memset(priv->bssid, 0, ETH_ALEN);
b481de9c
ZY		 6434 }
6435 mutex_unlock(&priv->mutex);
6436
6437 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6438}
6439
cd56d331
AK		 6440#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
6441
6442static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
6443 struct ieee80211_vif *vif,
6444 struct ieee80211_bss_conf *bss_conf,
6445 u32 changes)
6446{
4a8a4322 6447 struct iwl_priv *priv = hw->priv;
cd56d331
AK		 6448
6449 IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
6450
6451 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
6452 IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
6453 bss_conf->use_short_preamble);
6454 if (bss_conf->use_short_preamble)
f2c7e521 6455 priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
cd56d331 6456 else
f2c7e521 6457 priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
cd56d331
AK		 6458 }
6459
6460 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
6461 IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
6462 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
f2c7e521 6463 priv->staging39_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
cd56d331 6464 else
f2c7e521 6465 priv->staging39_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
cd56d331
AK		 6466 }
6467
6468 if (changes & BSS_CHANGED_ASSOC) {
6469 IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
6470 /* This should never happen as this function should
6471 * never be called from interrupt context. */
6472 if (WARN_ON_ONCE(in_interrupt()))
6473 return;
6474 if (bss_conf->assoc) {
6475 priv->assoc_id = bss_conf->aid;
6476 priv->beacon_int = bss_conf->beacon_int;
28afaf91 6477 priv->timestamp = bss_conf->timestamp;
cd56d331
AK		 6478 priv->assoc_capability = bss_conf->assoc_capability;
6479 priv->next_scan_jiffies = jiffies +
6480 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
6481 mutex_lock(&priv->mutex);
6482 iwl3945_post_associate(priv);
6483 mutex_unlock(&priv->mutex);
6484 } else {
6485 priv->assoc_id = 0;
6486 IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
6487 }
6488 } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
6489 IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
6490 iwl3945_send_rxon_assoc(priv);
6491 }
6492
6493}
6494
bb8c093b 6495static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 6496{
6497 int rc = 0;
6498 unsigned long flags;
4a8a4322 6499 struct iwl_priv *priv = hw->priv;
9387b7ca 6500 DECLARE_SSID_BUF(ssid_buf);
b481de9c
ZY		 6501
6502 IWL_DEBUG_MAC80211("enter\n");
6503
15e869d8 6504 mutex_lock(&priv->mutex);
b481de9c
ZY		 6505 spin_lock_irqsave(&priv->lock, flags);
6506
775a6e27 6507 if (!iwl_is_ready_rf(priv)) {
b481de9c
ZY		 6508 rc = -EIO;
6509 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
6510 goto out_unlock;
6511 }
6512
7878a5a4
MA		 6513 /* we don't schedule scan within next_scan_jiffies period */
6514 if (priv->next_scan_jiffies &&
6515 time_after(priv->next_scan_jiffies, jiffies)) {
6516 rc = -EAGAIN;
6517 goto out_unlock;
6518 }
15dbf1b7
BM		 6519 /* if we just finished scan ask for delay for a broadcast scan */
6520 if ((len == 0) && priv->last_scan_jiffies &&
6521 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
6522 jiffies)) {
b481de9c
ZY		 6523 rc = -EAGAIN;
6524 goto out_unlock;
6525 }
6526 if (len) {
7878a5a4 6527 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
9387b7ca 6528 print_ssid(ssid_buf, ssid, len), (int)len);
b481de9c
ZY		 6529
6530 priv->one_direct_scan = 1;
6531 priv->direct_ssid_len = (u8)
6532 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
6533 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
6ef89d0a
MA		 6534 } else
6535 priv->one_direct_scan = 0;
b481de9c 6536
bb8c093b 6537 rc = iwl3945_scan_initiate(priv);
b481de9c
ZY		 6538
6539 IWL_DEBUG_MAC80211("leave\n");
6540
6541out_unlock:
6542 spin_unlock_irqrestore(&priv->lock, flags);
15e869d8 6543 mutex_unlock(&priv->mutex);
b481de9c
ZY		 6544
6545 return rc;
6546}
6547
bb8c093b 6548static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 6549 const u8 *local_addr, const u8 *addr,
6550 struct ieee80211_key_conf *key)
6551{
4a8a4322 6552 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 6553 int rc = 0;
6554 u8 sta_id;
6555
6556 IWL_DEBUG_MAC80211("enter\n");
6557
df878d8f 6558 if (iwl3945_mod_params.sw_crypto) {
b481de9c
ZY		 6559 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
6560 return -EOPNOTSUPP;
6561 }
6562
6563 if (is_zero_ether_addr(addr))
6564 /* only support pairwise keys */
6565 return -EOPNOTSUPP;
6566
bb8c093b 6567 sta_id = iwl3945_hw_find_station(priv, addr);
b481de9c 6568 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 6569 IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
6570 addr);
b481de9c
ZY		 6571 return -EINVAL;
6572 }
6573
6574 mutex_lock(&priv->mutex);
6575
bb8c093b 6576 iwl3945_scan_cancel_timeout(priv, 100);
15e869d8 6577
b481de9c
ZY		 6578 switch (cmd) {
6579 case SET_KEY:
bb8c093b 6580 rc = iwl3945_update_sta_key_info(priv, key, sta_id);
b481de9c 6581 if (!rc) {
bb8c093b
CH		 6582 iwl3945_set_rxon_hwcrypto(priv, 1);
6583 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6584 key->hw_key_idx = sta_id;
6585 IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
6586 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
6587 }
6588 break;
6589 case DISABLE_KEY:
bb8c093b 6590 rc = iwl3945_clear_sta_key_info(priv, sta_id);
b481de9c 6591 if (!rc) {
bb8c093b
CH		 6592 iwl3945_set_rxon_hwcrypto(priv, 0);
6593 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6594 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
6595 }
6596 break;
6597 default:
6598 rc = -EINVAL;
6599 }
6600
6601 IWL_DEBUG_MAC80211("leave\n");
6602 mutex_unlock(&priv->mutex);
6603
6604 return rc;
6605}
6606
e100bb64 6607static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
b481de9c
ZY		 6608 const struct ieee80211_tx_queue_params *params)
6609{
4a8a4322 6610 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 6611 unsigned long flags;
6612 int q;
b481de9c
ZY		 6613
6614 IWL_DEBUG_MAC80211("enter\n");
6615
775a6e27 6616 if (!iwl_is_ready_rf(priv)) {
b481de9c
ZY		 6617 IWL_DEBUG_MAC80211("leave - RF not ready\n");
6618 return -EIO;
6619 }
6620
6621 if (queue >= AC_NUM) {
6622 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
6623 return 0;
6624 }
6625
b481de9c
ZY		 6626 q = AC_NUM - 1 - queue;
6627
6628 spin_lock_irqsave(&priv->lock, flags);
6629
6630 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
6631 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
6632 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
6633 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 6634 cpu_to_le16((params->txop * 32));
b481de9c
ZY		 6635
6636 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
6637 priv->qos_data.qos_active = 1;
6638
6639 spin_unlock_irqrestore(&priv->lock, flags);
6640
6641 mutex_lock(&priv->mutex);
05c914fe 6642 if (priv->iw_mode == NL80211_IFTYPE_AP)
bb8c093b
CH		 6643 iwl3945_activate_qos(priv, 1);
6644 else if (priv->assoc_id && iwl3945_is_associated(priv))
6645 iwl3945_activate_qos(priv, 0);
b481de9c
ZY		 6646
6647 mutex_unlock(&priv->mutex);
6648
b481de9c
ZY		 6649 IWL_DEBUG_MAC80211("leave\n");
6650 return 0;
6651}
6652
bb8c093b 6653static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 6654 struct ieee80211_tx_queue_stats *stats)
6655{
4a8a4322 6656 struct iwl_priv *priv = hw->priv;
b481de9c 6657 int i, avail;
188cf6c7 6658 struct iwl_tx_queue *txq;
d20b3c65 6659 struct iwl_queue *q;
b481de9c
ZY		 6660 unsigned long flags;
6661
6662 IWL_DEBUG_MAC80211("enter\n");
6663
775a6e27 6664 if (!iwl_is_ready_rf(priv)) {
b481de9c
ZY		 6665 IWL_DEBUG_MAC80211("leave - RF not ready\n");
6666 return -EIO;
6667 }
6668
6669 spin_lock_irqsave(&priv->lock, flags);
6670
6671 for (i = 0; i < AC_NUM; i++) {
188cf6c7 6672 txq = &priv->txq[i];
b481de9c 6673 q = &txq->q;
d20b3c65 6674 avail = iwl_queue_space(q);
b481de9c 6675
57ffc589
JB		 6676 stats[i].len = q->n_window - avail;
6677 stats[i].limit = q->n_window - q->high_mark;
6678 stats[i].count = q->n_window;
b481de9c
ZY		 6679
6680 }
6681 spin_unlock_irqrestore(&priv->lock, flags);
6682
6683 IWL_DEBUG_MAC80211("leave\n");
6684
6685 return 0;
6686}
6687
bb8c093b 6688static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 6689{
4a8a4322 6690 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 6691 unsigned long flags;
6692
6693 mutex_lock(&priv->mutex);
6694 IWL_DEBUG_MAC80211("enter\n");
6695
775a6e27 6696 iwl_reset_qos(priv);
292ae174 6697
b481de9c
ZY		 6698 spin_lock_irqsave(&priv->lock, flags);
6699 priv->assoc_id = 0;
6700 priv->assoc_capability = 0;
6701 priv->call_post_assoc_from_beacon = 0;
6702
6703 /* new association get rid of ibss beacon skb */
6704 if (priv->ibss_beacon)
6705 dev_kfree_skb(priv->ibss_beacon);
6706
6707 priv->ibss_beacon = NULL;
6708
6709 priv->beacon_int = priv->hw->conf.beacon_int;
28afaf91 6710 priv->timestamp = 0;
05c914fe 6711 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
b481de9c
ZY		 6712 priv->beacon_int = 0;
6713
6714 spin_unlock_irqrestore(&priv->lock, flags);
6715
775a6e27 6716 if (!iwl_is_ready_rf(priv)) {
fde3571f
MA		 6717 IWL_DEBUG_MAC80211("leave - not ready\n");
6718 mutex_unlock(&priv->mutex);
6719 return;
6720 }
6721
15e869d8
MA		 6722 /* we are restarting association process
6723 * clear RXON_FILTER_ASSOC_MSK bit
6724 */
05c914fe 6725 if (priv->iw_mode != NL80211_IFTYPE_AP) {
bb8c093b 6726 iwl3945_scan_cancel_timeout(priv, 100);
f2c7e521 6727 priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6728 iwl3945_commit_rxon(priv);
15e869d8
MA		 6729 }
6730
b481de9c 6731 /* Per mac80211.h: This is only used in IBSS mode... */
05c914fe 6732 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
15e869d8 6733
b481de9c
ZY		 6734 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
6735 mutex_unlock(&priv->mutex);
6736 return;
b481de9c
ZY		 6737 }
6738
bb8c093b 6739 iwl3945_set_rate(priv);
b481de9c
ZY		 6740
6741 mutex_unlock(&priv->mutex);
6742
6743 IWL_DEBUG_MAC80211("leave\n");
6744
6745}
6746
e039fa4a 6747static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 6748{
4a8a4322 6749 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 6750 unsigned long flags;
6751
b481de9c
ZY		 6752 IWL_DEBUG_MAC80211("enter\n");
6753
775a6e27 6754 if (!iwl_is_ready_rf(priv)) {
b481de9c 6755 IWL_DEBUG_MAC80211("leave - RF not ready\n");
b481de9c
ZY		 6756 return -EIO;
6757 }
6758
05c914fe 6759 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
b481de9c 6760 IWL_DEBUG_MAC80211("leave - not IBSS\n");
b481de9c
ZY		 6761 return -EIO;
6762 }
6763
6764 spin_lock_irqsave(&priv->lock, flags);
6765
6766 if (priv->ibss_beacon)
6767 dev_kfree_skb(priv->ibss_beacon);
6768
6769 priv->ibss_beacon = skb;
6770
6771 priv->assoc_id = 0;
6772
6773 IWL_DEBUG_MAC80211("leave\n");
6774 spin_unlock_irqrestore(&priv->lock, flags);
6775
775a6e27 6776 iwl_reset_qos(priv);
b481de9c 6777
dc4b1e7d 6778 iwl3945_post_associate(priv);
b481de9c 6779
b481de9c
ZY		 6780
6781 return 0;
6782}
6783
6784/*****************************************************************************
6785 *
6786 * sysfs attributes
6787 *
6788 *****************************************************************************/
6789
c8b0e6e1 6790#ifdef CONFIG_IWL3945_DEBUG
b481de9c
ZY		 6791
6792/*
6793 * The following adds a new attribute to the sysfs representation
6794 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
6795 * used for controlling the debug level.
6796 *
6797 * See the level definitions in iwl for details.
6798 */
40b8ec0b
SO		 6799static ssize_t show_debug_level(struct device *d,
6800 struct device_attribute *attr, char *buf)
b481de9c 6801{
4a8a4322 6802 struct iwl_priv *priv = d->driver_data;
40b8ec0b
SO		 6803
6804 return sprintf(buf, "0x%08X\n", priv->debug_level);
b481de9c 6805}
40b8ec0b
SO		 6806static ssize_t store_debug_level(struct device *d,
6807 struct device_attribute *attr,
b481de9c
ZY		 6808 const char *buf, size_t count)
6809{
4a8a4322 6810 struct iwl_priv *priv = d->driver_data;
40b8ec0b
SO		 6811 unsigned long val;
6812 int ret;
b481de9c 6813
40b8ec0b
SO		 6814 ret = strict_strtoul(buf, 0, &val);
6815 if (ret)
978785a3 6816 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
b481de9c 6817 else
40b8ec0b 6818 priv->debug_level = val;
b481de9c
ZY		 6819
6820 return strnlen(buf, count);
6821}
6822
40b8ec0b
SO		 6823static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
6824 show_debug_level, store_debug_level);
b481de9c 6825
c8b0e6e1 6826#endif /* CONFIG_IWL3945_DEBUG */
b481de9c 6827
b481de9c
ZY		 6828static ssize_t show_temperature(struct device *d,
6829 struct device_attribute *attr, char *buf)
6830{
4a8a4322 6831 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c 6832
775a6e27 6833 if (!iwl_is_alive(priv))
b481de9c
ZY		 6834 return -EAGAIN;
6835
bb8c093b 6836 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY		 6837}
6838
6839static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
6840
b481de9c
ZY		 6841static ssize_t show_tx_power(struct device *d,
6842 struct device_attribute *attr, char *buf)
6843{
4a8a4322 6844 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY		 6845 return sprintf(buf, "%d\n", priv->user_txpower_limit);
6846}
6847
6848static ssize_t store_tx_power(struct device *d,
6849 struct device_attribute *attr,
6850 const char *buf, size_t count)
6851{
4a8a4322 6852 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY		 6853 char *p = (char *)buf;
6854 u32 val;
6855
6856 val = simple_strtoul(p, &p, 10);
6857 if (p == buf)
978785a3 6858 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
b481de9c 6859 else
bb8c093b 6860 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 6861
6862 return count;
6863}
6864
6865static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
6866
6867static ssize_t show_flags(struct device *d,
6868 struct device_attribute *attr, char *buf)
6869{
4a8a4322 6870 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c 6871
f2c7e521 6872 return sprintf(buf, "0x%04X\n", priv->active39_rxon.flags);
b481de9c
ZY		 6873}
6874
6875static ssize_t store_flags(struct device *d,
6876 struct device_attribute *attr,
6877 const char *buf, size_t count)
6878{
4a8a4322 6879 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY		 6880 u32 flags = simple_strtoul(buf, NULL, 0);
6881
6882 mutex_lock(&priv->mutex);
f2c7e521 6883 if (le32_to_cpu(priv->staging39_rxon.flags) != flags) {
b481de9c 6884 /* Cancel any currently running scans... */
bb8c093b 6885 if (iwl3945_scan_cancel_timeout(priv, 100))
39aadf8c 6886 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c
ZY		 6887 else {
6888 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
6889 flags);
f2c7e521 6890 priv->staging39_rxon.flags = cpu_to_le32(flags);
bb8c093b 6891 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6892 }
6893 }
6894 mutex_unlock(&priv->mutex);
6895
6896 return count;
6897}
6898
6899static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
6900
6901static ssize_t show_filter_flags(struct device *d,
6902 struct device_attribute *attr, char *buf)
6903{
4a8a4322 6904 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY		 6905
6906 return sprintf(buf, "0x%04X\n",
f2c7e521 6907 le32_to_cpu(priv->active39_rxon.filter_flags));
b481de9c
ZY		 6908}
6909
6910static ssize_t store_filter_flags(struct device *d,
6911 struct device_attribute *attr,
6912 const char *buf, size_t count)
6913{
4a8a4322 6914 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY		 6915 u32 filter_flags = simple_strtoul(buf, NULL, 0);
6916
6917 mutex_lock(&priv->mutex);
f2c7e521 6918 if (le32_to_cpu(priv->staging39_rxon.filter_flags) != filter_flags) {
b481de9c 6919 /* Cancel any currently running scans... */
bb8c093b 6920 if (iwl3945_scan_cancel_timeout(priv, 100))
39aadf8c 6921 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c
ZY		 6922 else {
6923 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
6924 "0x%04X\n", filter_flags);
f2c7e521 6925 priv->staging39_rxon.filter_flags =
b481de9c 6926 cpu_to_le32(filter_flags);
bb8c093b 6927 iwl3945_commit_rxon(priv);
b481de9c
ZY		 6928 }
6929 }
6930 mutex_unlock(&priv->mutex);
6931
6932 return count;
6933}
6934
6935static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
6936 store_filter_flags);
6937
c8b0e6e1 6938#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 6939
6940static ssize_t show_measurement(struct device *d,
6941 struct device_attribute *attr, char *buf)
6942{
4a8a4322 6943 struct iwl_priv *priv = dev_get_drvdata(d);
600c0e11 6944 struct iwl_spectrum_notification measure_report;
b481de9c 6945 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 6946 u8 *data = (u8 *)&measure_report;
b481de9c
ZY		 6947 unsigned long flags;
6948
6949 spin_lock_irqsave(&priv->lock, flags);
6950 if (!(priv->measurement_status & MEASUREMENT_READY)) {
6951 spin_unlock_irqrestore(&priv->lock, flags);
6952 return 0;
6953 }
6954 memcpy(&measure_report, &priv->measure_report, size);
6955 priv->measurement_status = 0;
6956 spin_unlock_irqrestore(&priv->lock, flags);
6957
6958 while (size && (PAGE_SIZE - len)) {
6959 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
6960 PAGE_SIZE - len, 1);
6961 len = strlen(buf);
6962 if (PAGE_SIZE - len)
6963 buf[len++] = '\n';
6964
6965 ofs += 16;
6966 size -= min(size, 16U);
6967 }
6968
6969 return len;
6970}
6971
6972static ssize_t store_measurement(struct device *d,
6973 struct device_attribute *attr,
6974 const char *buf, size_t count)
6975{
4a8a4322 6976 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 6977 struct ieee80211_measurement_params params = {
f2c7e521 6978 .channel = le16_to_cpu(priv->active39_rxon.channel),
b481de9c
ZY		 6979 .start_time = cpu_to_le64(priv->last_tsf),
6980 .duration = cpu_to_le16(1),
6981 };
6982 u8 type = IWL_MEASURE_BASIC;
6983 u8 buffer[32];
6984 u8 channel;
6985
6986 if (count) {
6987 char *p = buffer;
6988 strncpy(buffer, buf, min(sizeof(buffer), count));
6989 channel = simple_strtoul(p, NULL, 0);
6990 if (channel)
6991 params.channel = channel;
6992
6993 p = buffer;
6994 while (*p && *p != ' ')
6995 p++;
6996 if (*p)
6997 type = simple_strtoul(p + 1, NULL, 0);
6998 }
6999
7000 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7001 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7002 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY		 7003
7004 return count;
7005}
7006
7007static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7008 show_measurement, store_measurement);
c8b0e6e1 7009#endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
b481de9c 7010
b481de9c
ZY		 7011static ssize_t store_retry_rate(struct device *d,
7012 struct device_attribute *attr,
7013 const char *buf, size_t count)
7014{
4a8a4322 7015 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7016
7017 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7018 if (priv->retry_rate <= 0)
7019 priv->retry_rate = 1;
7020
7021 return count;
7022}
7023
7024static ssize_t show_retry_rate(struct device *d,
7025 struct device_attribute *attr, char *buf)
7026{
4a8a4322 7027 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7028 return sprintf(buf, "%d", priv->retry_rate);
7029}
7030
7031static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7032 store_retry_rate);
7033
7034static ssize_t store_power_level(struct device *d,
7035 struct device_attribute *attr,
7036 const char *buf, size_t count)
7037{
4a8a4322 7038 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7039 int rc;
7040 int mode;
7041
7042 mode = simple_strtoul(buf, NULL, 0);
7043 mutex_lock(&priv->mutex);
7044
775a6e27 7045 if (!iwl_is_ready(priv)) {
b481de9c
ZY		 7046 rc = -EAGAIN;
7047 goto out;
7048 }
7049
1125eff3
SO		 7050 if ((mode < 1) || (mode > IWL39_POWER_LIMIT) ||
7051 (mode == IWL39_POWER_AC))
7052 mode = IWL39_POWER_AC;
b481de9c
ZY		 7053 else
7054 mode |= IWL_POWER_ENABLED;
7055
7056 if (mode != priv->power_mode) {
bb8c093b 7057 rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 7058 if (rc) {
7059 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7060 goto out;
7061 }
7062 priv->power_mode = mode;
7063 }
7064
7065 rc = count;
7066
7067 out:
7068 mutex_unlock(&priv->mutex);
7069 return rc;
7070}
7071
7072#define MAX_WX_STRING 80
7073
7074/* Values are in microsecond */
7075static const s32 timeout_duration[] = {
7076 350000,
7077 250000,
7078 75000,
7079 37000,
7080 25000,
7081};
7082static const s32 period_duration[] = {
7083 400000,
7084 700000,
7085 1000000,
7086 1000000,
7087 1000000
7088};
7089
7090static ssize_t show_power_level(struct device *d,
7091 struct device_attribute *attr, char *buf)
7092{
4a8a4322 7093 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7094 int level = IWL_POWER_LEVEL(priv->power_mode);
7095 char *p = buf;
7096
7097 p += sprintf(p, "%d ", level);
7098 switch (level) {
7099 case IWL_POWER_MODE_CAM:
1125eff3 7100 case IWL39_POWER_AC:
b481de9c
ZY		 7101 p += sprintf(p, "(AC)");
7102 break;
1125eff3 7103 case IWL39_POWER_BATTERY:
b481de9c
ZY		 7104 p += sprintf(p, "(BATTERY)");
7105 break;
7106 default:
7107 p += sprintf(p,
7108 "(Timeout %dms, Period %dms)",
7109 timeout_duration[level - 1] / 1000,
7110 period_duration[level - 1] / 1000);
7111 }
7112
7113 if (!(priv->power_mode & IWL_POWER_ENABLED))
7114 p += sprintf(p, " OFF\n");
7115 else
7116 p += sprintf(p, " \n");
7117
3ac7f146 7118 return p - buf + 1;
b481de9c
ZY		 7119
7120}
7121
7122static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7123 store_power_level);
7124
7125static ssize_t show_channels(struct device *d,
7126 struct device_attribute *attr, char *buf)
7127{
8318d78a
JB		 7128 /* all this shit doesn't belong into sysfs anyway */
7129 return 0;
b481de9c
ZY		 7130}
7131
7132static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7133
7134static ssize_t show_statistics(struct device *d,
7135 struct device_attribute *attr, char *buf)
7136{
4a8a4322 7137 struct iwl_priv *priv = dev_get_drvdata(d);
bb8c093b 7138 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 7139 u32 len = 0, ofs = 0;
f2c7e521 7140 u8 *data = (u8 *)&priv->statistics_39;
b481de9c
ZY		 7141 int rc = 0;
7142
775a6e27 7143 if (!iwl_is_alive(priv))
b481de9c
ZY		 7144 return -EAGAIN;
7145
7146 mutex_lock(&priv->mutex);
bb8c093b 7147 rc = iwl3945_send_statistics_request(priv);
b481de9c
ZY		 7148 mutex_unlock(&priv->mutex);
7149
7150 if (rc) {
7151 len = sprintf(buf,
7152 "Error sending statistics request: 0x%08X\n", rc);
7153 return len;
7154 }
7155
7156 while (size && (PAGE_SIZE - len)) {
7157 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7158 PAGE_SIZE - len, 1);
7159 len = strlen(buf);
7160 if (PAGE_SIZE - len)
7161 buf[len++] = '\n';
7162
7163 ofs += 16;
7164 size -= min(size, 16U);
7165 }
7166
7167 return len;
7168}
7169
7170static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7171
7172static ssize_t show_antenna(struct device *d,
7173 struct device_attribute *attr, char *buf)
7174{
4a8a4322 7175 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 7176
775a6e27 7177 if (!iwl_is_alive(priv))
b481de9c
ZY		 7178 return -EAGAIN;
7179
7180 return sprintf(buf, "%d\n", priv->antenna);
7181}
7182
7183static ssize_t store_antenna(struct device *d,
7184 struct device_attribute *attr,
7185 const char *buf, size_t count)
7186{
7187 int ant;
4a8a4322 7188 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7189
7190 if (count == 0)
7191 return 0;
7192
7193 if (sscanf(buf, "%1i", &ant) != 1) {
7194 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7195 return count;
7196 }
7197
7198 if ((ant >= 0) && (ant <= 2)) {
7199 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7200 priv->antenna = (enum iwl3945_antenna)ant;
b481de9c
ZY		 7201 } else
7202 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7203
7204
7205 return count;
7206}
7207
7208static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7209
7210static ssize_t show_status(struct device *d,
7211 struct device_attribute *attr, char *buf)
7212{
4a8a4322 7213 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
775a6e27 7214 if (!iwl_is_alive(priv))
b481de9c
ZY		 7215 return -EAGAIN;
7216 return sprintf(buf, "0x%08x\n", (int)priv->status);
7217}
7218
7219static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7220
7221static ssize_t dump_error_log(struct device *d,
7222 struct device_attribute *attr,
7223 const char *buf, size_t count)
7224{
7225 char *p = (char *)buf;
7226
7227 if (p[0] == '1')
4a8a4322 7228 iwl3945_dump_nic_error_log((struct iwl_priv *)d->driver_data);
b481de9c
ZY		 7229
7230 return strnlen(buf, count);
7231}
7232
7233static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7234
7235static ssize_t dump_event_log(struct device *d,
7236 struct device_attribute *attr,
7237 const char *buf, size_t count)
7238{
7239 char *p = (char *)buf;
7240
7241 if (p[0] == '1')
4a8a4322 7242 iwl3945_dump_nic_event_log((struct iwl_priv *)d->driver_data);
b481de9c
ZY		 7243
7244 return strnlen(buf, count);
7245}
7246
7247static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7248
7249/*****************************************************************************
7250 *
a96a27f9 7251 * driver setup and tear down
b481de9c
ZY		 7252 *
7253 *****************************************************************************/
7254
4a8a4322 7255static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 7256{
7257 priv->workqueue = create_workqueue(DRV_NAME);
7258
7259 init_waitqueue_head(&priv->wait_command_queue);
7260
bb8c093b
CH		 7261 INIT_WORK(&priv->up, iwl3945_bg_up);
7262 INIT_WORK(&priv->restart, iwl3945_bg_restart);
7263 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
7264 INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
7265 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
7266 INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
7267 INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
7268 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH		 7269 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
7270 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
7271 INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
7272
7273 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY		 7274
7275 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7276 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 7277}
7278
4a8a4322 7279static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 7280{
bb8c093b 7281 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 7282
e47eb6ad 7283 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 7284 cancel_delayed_work(&priv->scan_check);
7285 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY		 7286 cancel_work_sync(&priv->beacon_update);
7287}
7288
bb8c093b 7289static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY		 7290 &dev_attr_antenna.attr,
7291 &dev_attr_channels.attr,
7292 &dev_attr_dump_errors.attr,
7293 &dev_attr_dump_events.attr,
7294 &dev_attr_flags.attr,
7295 &dev_attr_filter_flags.attr,
c8b0e6e1 7296#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7297 &dev_attr_measurement.attr,
7298#endif
7299 &dev_attr_power_level.attr,
b481de9c 7300 &dev_attr_retry_rate.attr,
b481de9c
ZY		 7301 &dev_attr_statistics.attr,
7302 &dev_attr_status.attr,
7303 &dev_attr_temperature.attr,
b481de9c 7304 &dev_attr_tx_power.attr,
40b8ec0b
SO		 7305#ifdef CONFIG_IWL3945_DEBUG
7306 &dev_attr_debug_level.attr,
7307#endif
b481de9c
ZY		 7308 NULL
7309};
7310
bb8c093b 7311static struct attribute_group iwl3945_attribute_group = {
b481de9c 7312 .name = NULL, /* put in device directory */
bb8c093b 7313 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY		 7314};
7315
bb8c093b
CH		 7316static struct ieee80211_ops iwl3945_hw_ops = {
7317 .tx = iwl3945_mac_tx,
7318 .start = iwl3945_mac_start,
7319 .stop = iwl3945_mac_stop,
7320 .add_interface = iwl3945_mac_add_interface,
7321 .remove_interface = iwl3945_mac_remove_interface,
7322 .config = iwl3945_mac_config,
7323 .config_interface = iwl3945_mac_config_interface,
7324 .configure_filter = iwl3945_configure_filter,
7325 .set_key = iwl3945_mac_set_key,
bb8c093b
CH		 7326 .get_tx_stats = iwl3945_mac_get_tx_stats,
7327 .conf_tx = iwl3945_mac_conf_tx,
bb8c093b 7328 .reset_tsf = iwl3945_mac_reset_tsf,
cd56d331 7329 .bss_info_changed = iwl3945_bss_info_changed,
bb8c093b 7330 .hw_scan = iwl3945_mac_hw_scan
b481de9c
ZY		 7331};
7332
e52119c5 7333static int iwl3945_init_drv(struct iwl_priv *priv)
90a30a02
KA		 7334{
7335 int ret;
7336
7337 priv->retry_rate = 1;
7338 priv->ibss_beacon = NULL;
7339
7340 spin_lock_init(&priv->lock);
7341 spin_lock_init(&priv->power_data.lock);
7342 spin_lock_init(&priv->sta_lock);
7343 spin_lock_init(&priv->hcmd_lock);
7344
7345 INIT_LIST_HEAD(&priv->free_frames);
7346
7347 mutex_init(&priv->mutex);
7348
7349 /* Clear the driver's (not device's) station table */
7350 iwl3945_clear_stations_table(priv);
7351
7352 priv->data_retry_limit = -1;
7353 priv->ieee_channels = NULL;
7354 priv->ieee_rates = NULL;
7355 priv->band = IEEE80211_BAND_2GHZ;
7356
7357 priv->iw_mode = NL80211_IFTYPE_STATION;
7358
7359 iwl_reset_qos(priv);
7360
7361 priv->qos_data.qos_active = 0;
7362 priv->qos_data.qos_cap.val = 0;
7363
7364 priv->rates_mask = IWL_RATES_MASK;
7365 /* If power management is turned on, default to AC mode */
7366 priv->power_mode = IWL_POWER_AC;
7367 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
7368
7369 ret = iwl3945_init_channel_map(priv);
7370 if (ret) {
7371 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
7372 goto err;
7373 }
7374
7375 ret = iwl3945_init_geos(priv);
7376 if (ret) {
7377 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
7378 goto err_free_channel_map;
7379 }
7380
7381 return 0;
7382
7383err_free_channel_map:
7384 iwl3945_free_channel_map(priv);
7385err:
7386 return ret;
7387}
7388
bb8c093b 7389static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 7390{
7391 int err = 0;
4a8a4322 7392 struct iwl_priv *priv;
b481de9c 7393 struct ieee80211_hw *hw;
c0f20d91 7394 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 7395 unsigned long flags;
b481de9c 7396
cee53ddb
KA		 7397 /***********************
7398 * 1. Allocating HW data
7399 * ********************/
7400
b481de9c
ZY		 7401 /* mac80211 allocates memory for this device instance, including
7402 * space for this driver's private structure */
90a30a02 7403 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
b481de9c 7404 if (hw == NULL) {
a3139c59 7405 printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
b481de9c
ZY		 7406 err = -ENOMEM;
7407 goto out;
7408 }
b481de9c 7409 priv = hw->priv;
90a30a02 7410 SET_IEEE80211_DEV(hw, &pdev->dev);
6440adb5 7411
df878d8f
KA		 7412 if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) ||
7413 (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) {
15b1687c
WT		 7414 IWL_ERR(priv,
7415 "invalid queues_num, should be between %d and %d\n",
7416 IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
a3139c59
SO		 7417 err = -EINVAL;
7418 goto out;
7419 }
7420
90a30a02
KA		 7421 /*
7422 * Disabling hardware scan means that mac80211 will perform scans
7423 * "the hard way", rather than using device's scan.
7424 */
df878d8f 7425 if (iwl3945_mod_params.disable_hw_scan) {
40b8ec0b
SO		 7426 IWL_DEBUG_INFO("Disabling hw_scan\n");
7427 iwl3945_hw_ops.hw_scan = NULL;
7428 }
7429
90a30a02 7430
cee53ddb 7431 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
90a30a02
KA		 7432 priv->cfg = cfg;
7433 priv->pci_dev = pdev;
cee53ddb 7434
c8b0e6e1 7435#ifdef CONFIG_IWL3945_DEBUG
df878d8f 7436 priv->debug_level = iwl3945_mod_params.debug;
b481de9c
ZY		 7437 atomic_set(&priv->restrict_refcnt, 0);
7438#endif
90a30a02
KA		 7439 hw->rate_control_algorithm = "iwl-3945-rs";
7440 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
7441
7442 /* Select antenna (may be helpful if only one antenna is connected) */
7443 priv->antenna = (enum iwl3945_antenna)iwl3945_mod_params.antenna;
b481de9c 7444
566bfe5a 7445 /* Tell mac80211 our characteristics */
605a0bd6 7446 hw->flags = IEEE80211_HW_SIGNAL_DBM |
566bfe5a 7447 IEEE80211_HW_NOISE_DBM;
b481de9c 7448
f59ac048 7449 hw->wiphy->interface_modes =
f59ac048
LR		 7450 BIT(NL80211_IFTYPE_STATION) |
7451 BIT(NL80211_IFTYPE_ADHOC);
7452
ea4a82dc
LR		 7453 hw->wiphy->fw_handles_regulatory = true;
7454
6440adb5 7455 /* 4 EDCA QOS priorities */
b481de9c
ZY		 7456 hw->queues = 4;
7457
cee53ddb
KA		 7458 /***************************
7459 * 2. Initializing PCI bus
7460 * *************************/
b481de9c
ZY		 7461 if (pci_enable_device(pdev)) {
7462 err = -ENODEV;
7463 goto out_ieee80211_free_hw;
7464 }
7465
7466 pci_set_master(pdev);
7467
b481de9c
ZY		 7468 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
7469 if (!err)
7470 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
7471 if (err) {
978785a3 7472 IWL_WARN(priv, "No suitable DMA available.\n");
b481de9c
ZY		 7473 goto out_pci_disable_device;
7474 }
7475
7476 pci_set_drvdata(pdev, priv);
7477 err = pci_request_regions(pdev, DRV_NAME);
7478 if (err)
7479 goto out_pci_disable_device;
6440adb5 7480
cee53ddb
KA		 7481 /***********************
7482 * 3. Read REV Register
7483 * ********************/
b481de9c
ZY		 7484 priv->hw_base = pci_iomap(pdev, 0, 0);
7485 if (!priv->hw_base) {
7486 err = -ENODEV;
7487 goto out_pci_release_regions;
7488 }
7489
7490 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
7491 (unsigned long long) pci_resource_len(pdev, 0));
7492 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
7493
cee53ddb
KA		 7494 /* We disable the RETRY_TIMEOUT register (0x41) to keep
7495 * PCI Tx retries from interfering with C3 CPU state */
7496 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 7497
90a30a02
KA		 7498 /* amp init */
7499 err = priv->cfg->ops->lib->apm_ops.init(priv);
cee53ddb 7500 if (err < 0) {
90a30a02
KA		 7501 IWL_DEBUG_INFO("Failed to init APMG\n");
7502 goto out_iounmap;
cee53ddb 7503 }
b481de9c 7504
cee53ddb
KA		 7505 /***********************
7506 * 4. Read EEPROM
7507 * ********************/
90a30a02 7508
cee53ddb
KA		 7509 /* Read the EEPROM */
7510 err = iwl3945_eeprom_init(priv);
7511 if (err) {
15b1687c 7512 IWL_ERR(priv, "Unable to init EEPROM\n");
cee53ddb
KA		 7513 goto out_remove_sysfs;
7514 }
7515 /* MAC Address location in EEPROM same for 3945/4965 */
7516 get_eeprom_mac(priv, priv->mac_addr);
7517 IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
7518 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 7519
cee53ddb
KA		 7520 /***********************
7521 * 5. Setup HW Constants
7522 * ********************/
b481de9c 7523 /* Device-specific setup */
3832ec9d 7524 if (iwl3945_hw_set_hw_params(priv)) {
15b1687c 7525 IWL_ERR(priv, "failed to set hw settings\n");
b481de9c
ZY		 7526 goto out_iounmap;
7527 }
7528
cee53ddb
KA		 7529 /***********************
7530 * 6. Setup priv
7531 * ********************/
cee53ddb 7532
90a30a02 7533 err = iwl3945_init_drv(priv);
b481de9c 7534 if (err) {
90a30a02
KA		 7535 IWL_ERR(priv, "initializing driver failed\n");
7536 goto out_free_geos;
b481de9c
ZY		 7537 }
7538
978785a3
TW		 7539 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
7540 priv->cfg->name);
cee53ddb
KA		 7541
7542 /***********************************
7543 * 7. Initialize Module Parameters
7544 * **********************************/
7545
7546 /* Initialize module parameter values here */
7547 /* Disable radio (SW RF KILL) via parameter when loading driver */
df878d8f 7548 if (iwl3945_mod_params.disable) {
cee53ddb
KA		 7549 set_bit(STATUS_RF_KILL_SW, &priv->status);
7550 IWL_DEBUG_INFO("Radio disabled.\n");
849e0dce
RC		 7551 }
7552
cee53ddb
KA		 7553
7554 /***********************
7555 * 8. Setup Services
7556 * ********************/
7557
7558 spin_lock_irqsave(&priv->lock, flags);
7559 iwl3945_disable_interrupts(priv);
7560 spin_unlock_irqrestore(&priv->lock, flags);
7561
7562 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 7563 if (err) {
15b1687c 7564 IWL_ERR(priv, "failed to create sysfs device attributes\n");
90a30a02 7565 goto out_release_irq;
849e0dce 7566 }
849e0dce 7567
cee53ddb
KA		 7568 iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
7569 iwl3945_setup_deferred_work(priv);
7570 iwl3945_setup_rx_handlers(priv);
7571
7572 /***********************
7573 * 9. Conclude
7574 * ********************/
7575 pci_save_state(pdev);
7576 pci_disable_device(pdev);
7577
7578 /*********************************
7579 * 10. Setup and Register mac80211
7580 * *******************************/
7581
5a66926a
ZY		 7582 err = ieee80211_register_hw(priv->hw);
7583 if (err) {
15b1687c 7584 IWL_ERR(priv, "Failed to register network device: %d\n", err);
cee53ddb 7585 goto out_remove_sysfs;
5a66926a 7586 }
b481de9c 7587
5a66926a
ZY		 7588 priv->hw->conf.beacon_int = 100;
7589 priv->mac80211_registered = 1;
cee53ddb 7590
ebef2008
AK		 7591 err = iwl3945_rfkill_init(priv);
7592 if (err)
15b1687c 7593 IWL_ERR(priv, "Unable to initialize RFKILL system. "
ebef2008
AK		 7594 "Ignoring error: %d\n", err);
7595
b481de9c
ZY		 7596 return 0;
7597
cee53ddb
KA		 7598 out_remove_sysfs:
7599 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce
RC		 7600 out_free_geos:
7601 iwl3945_free_geos(priv);
b481de9c
ZY		 7602
7603 out_release_irq:
b481de9c
ZY		 7604 destroy_workqueue(priv->workqueue);
7605 priv->workqueue = NULL;
3832ec9d 7606 iwl3945_unset_hw_params(priv);
b481de9c
ZY		 7607
7608 out_iounmap:
7609 pci_iounmap(pdev, priv->hw_base);
7610 out_pci_release_regions:
7611 pci_release_regions(pdev);
7612 out_pci_disable_device:
7613 pci_disable_device(pdev);
7614 pci_set_drvdata(pdev, NULL);
7615 out_ieee80211_free_hw:
7616 ieee80211_free_hw(priv->hw);
7617 out:
7618 return err;
7619}
7620
c83dbf68 7621static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 7622{
4a8a4322 7623 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 7624 unsigned long flags;
b481de9c
ZY		 7625
7626 if (!priv)
7627 return;
7628
7629 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
7630
b481de9c 7631 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 7632
d552bfb6
KA		 7633 if (priv->mac80211_registered) {
7634 ieee80211_unregister_hw(priv->hw);
7635 priv->mac80211_registered = 0;
7636 } else {
7637 iwl3945_down(priv);
7638 }
b481de9c 7639
0359facc
MA		 7640 /* make sure we flush any pending irq or
7641 * tasklet for the driver
7642 */
7643 spin_lock_irqsave(&priv->lock, flags);
7644 iwl3945_disable_interrupts(priv);
7645 spin_unlock_irqrestore(&priv->lock, flags);
7646
7647 iwl_synchronize_irq(priv);
7648
bb8c093b 7649 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 7650
ebef2008 7651 iwl3945_rfkill_unregister(priv);
bb8c093b 7652 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY		 7653
7654 if (priv->rxq.bd)
51af3d3f 7655 iwl_rx_queue_free(priv, &priv->rxq);
bb8c093b 7656 iwl3945_hw_txq_ctx_free(priv);
b481de9c 7657
3832ec9d 7658 iwl3945_unset_hw_params(priv);
bb8c093b 7659 iwl3945_clear_stations_table(priv);
b481de9c 7660
6ef89d0a
MA		 7661 /*netif_stop_queue(dev); */
7662 flush_workqueue(priv->workqueue);
7663
bb8c093b 7664 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY		 7665 * priv->workqueue... so we can't take down the workqueue
7666 * until now... */
7667 destroy_workqueue(priv->workqueue);
7668 priv->workqueue = NULL;
7669
b481de9c
ZY		 7670 pci_iounmap(pdev, priv->hw_base);
7671 pci_release_regions(pdev);
7672 pci_disable_device(pdev);
7673 pci_set_drvdata(pdev, NULL);
7674
849e0dce
RC		 7675 iwl3945_free_channel_map(priv);
7676 iwl3945_free_geos(priv);
f2c7e521 7677 kfree(priv->scan39);
b481de9c
ZY		 7678 if (priv->ibss_beacon)
7679 dev_kfree_skb(priv->ibss_beacon);
7680
7681 ieee80211_free_hw(priv->hw);
7682}
7683
7684#ifdef CONFIG_PM
7685
bb8c093b 7686static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 7687{
4a8a4322 7688 struct iwl_priv *priv = pci_get_drvdata(pdev);
b481de9c 7689
e655b9f0
ZY		 7690 if (priv->is_open) {
7691 set_bit(STATUS_IN_SUSPEND, &priv->status);
7692 iwl3945_mac_stop(priv->hw);
7693 priv->is_open = 1;
7694 }
b481de9c 7695
b481de9c
ZY		 7696 pci_set_power_state(pdev, PCI_D3hot);
7697
b481de9c
ZY		 7698 return 0;
7699}
7700
bb8c093b 7701static int iwl3945_pci_resume(struct pci_dev *pdev)
b481de9c 7702{
4a8a4322 7703 struct iwl_priv *priv = pci_get_drvdata(pdev);
b481de9c 7704
b481de9c 7705 pci_set_power_state(pdev, PCI_D0);
b481de9c 7706
e655b9f0
ZY		 7707 if (priv->is_open)
7708 iwl3945_mac_start(priv->hw);
b481de9c 7709
e655b9f0 7710 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 7711 return 0;
7712}
7713
7714#endif /* CONFIG_PM */
7715
ebef2008 7716/*************** RFKILL FUNCTIONS **********/
80fcc9e2 7717#ifdef CONFIG_IWL3945_RFKILL
ebef2008
AK		 7718/* software rf-kill from user */
7719static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
7720{
4a8a4322 7721 struct iwl_priv *priv = data;
ebef2008
AK		 7722 int err = 0;
7723
80fcc9e2 7724 if (!priv->rfkill)
ebef2008
AK		 7725 return 0;
7726
7727 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
7728 return 0;
7729
a96a27f9 7730 IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
ebef2008
AK		 7731 mutex_lock(&priv->mutex);
7732
7733 switch (state) {
acdfe9b4 7734 case RFKILL_STATE_UNBLOCKED:
775a6e27 7735 if (iwl_is_rfkill_hw(priv)) {
ebef2008 7736 err = -EBUSY;
80fcc9e2
AG		 7737 goto out_unlock;
7738 }
7739 iwl3945_radio_kill_sw(priv, 0);
ebef2008 7740 break;
acdfe9b4 7741 case RFKILL_STATE_SOFT_BLOCKED:
ebef2008 7742 iwl3945_radio_kill_sw(priv, 1);
ebef2008 7743 break;
acdfe9b4 7744 default:
39aadf8c 7745 IWL_WARN(priv, "received unexpected RFKILL state %d\n", state);
acdfe9b4 7746 break;
ebef2008 7747 }
80fcc9e2 7748out_unlock:
ebef2008
AK		 7749 mutex_unlock(&priv->mutex);
7750
7751 return err;
7752}
7753
4a8a4322 7754int iwl3945_rfkill_init(struct iwl_priv *priv)
ebef2008
AK		 7755{
7756 struct device *device = wiphy_dev(priv->hw->wiphy);
7757 int ret = 0;
7758
7759 BUG_ON(device == NULL);
7760
7761 IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
80fcc9e2
AG		 7762 priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
7763 if (!priv->rfkill) {
15b1687c 7764 IWL_ERR(priv, "Unable to allocate rfkill device.\n");
ebef2008
AK		 7765 ret = -ENOMEM;
7766 goto error;
7767 }
7768
80fcc9e2
AG		 7769 priv->rfkill->name = priv->cfg->name;
7770 priv->rfkill->data = priv;
7771 priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
7772 priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
7773 priv->rfkill->user_claim_unsupported = 1;
ebef2008 7774
80fcc9e2
AG		 7775 priv->rfkill->dev.class->suspend = NULL;
7776 priv->rfkill->dev.class->resume = NULL;
ebef2008 7777
80fcc9e2 7778 ret = rfkill_register(priv->rfkill);
ebef2008 7779 if (ret) {
15b1687c 7780 IWL_ERR(priv, "Unable to register rfkill: %d\n", ret);
80fcc9e2 7781 goto freed_rfkill;
ebef2008
AK		 7782 }
7783
7784 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
7785 return ret;
7786
ebef2008 7787freed_rfkill:
80fcc9e2
AG		 7788 if (priv->rfkill != NULL)
7789 rfkill_free(priv->rfkill);
7790 priv->rfkill = NULL;
ebef2008
AK		 7791
7792error:
7793 IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
7794 return ret;
7795}
7796
4a8a4322 7797void iwl3945_rfkill_unregister(struct iwl_priv *priv)
ebef2008 7798{
80fcc9e2
AG		 7799 if (priv->rfkill)
7800 rfkill_unregister(priv->rfkill);
ebef2008 7801
80fcc9e2 7802 priv->rfkill = NULL;
ebef2008
AK		 7803}
7804
7805/* set rf-kill to the right state. */
4a8a4322 7806void iwl3945_rfkill_set_hw_state(struct iwl_priv *priv)
ebef2008
AK		 7807{
7808
80fcc9e2
AG		 7809 if (!priv->rfkill)
7810 return;
7811
775a6e27 7812 if (iwl_is_rfkill_hw(priv)) {
80fcc9e2 7813 rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
ebef2008 7814 return;
80fcc9e2 7815 }
ebef2008 7816
775a6e27 7817 if (!iwl_is_rfkill_sw(priv))
80fcc9e2 7818 rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
ebef2008 7819 else
80fcc9e2 7820 rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
ebef2008
AK		 7821}
7822#endif
7823
b481de9c
ZY		 7824/*****************************************************************************
7825 *
7826 * driver and module entry point
7827 *
7828 *****************************************************************************/
7829
bb8c093b 7830static struct pci_driver iwl3945_driver = {
b481de9c 7831 .name = DRV_NAME,
bb8c093b
CH		 7832 .id_table = iwl3945_hw_card_ids,
7833 .probe = iwl3945_pci_probe,
7834 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 7835#ifdef CONFIG_PM
bb8c093b
CH		 7836 .suspend = iwl3945_pci_suspend,
7837 .resume = iwl3945_pci_resume,
b481de9c
ZY		 7838#endif
7839};
7840
bb8c093b 7841static int __init iwl3945_init(void)
b481de9c
ZY		 7842{
7843
7844 int ret;
7845 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
7846 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC		 7847
7848 ret = iwl3945_rate_control_register();
7849 if (ret) {
a3139c59
SO		 7850 printk(KERN_ERR DRV_NAME
7851 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 7852 return ret;
7853 }
7854
bb8c093b 7855 ret = pci_register_driver(&iwl3945_driver);
b481de9c 7856 if (ret) {
a3139c59 7857 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 7858 goto error_register;
b481de9c 7859 }
b481de9c
ZY		 7860
7861 return ret;
897e1cf2 7862
897e1cf2
RC		 7863error_register:
7864 iwl3945_rate_control_unregister();
7865 return ret;
b481de9c
ZY		 7866}
7867
bb8c093b 7868static void __exit iwl3945_exit(void)
b481de9c 7869{
bb8c093b 7870 pci_unregister_driver(&iwl3945_driver);
897e1cf2 7871 iwl3945_rate_control_unregister();
b481de9c
ZY		 7872}
7873
a0987a8d 7874MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 7875
df878d8f 7876module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
b481de9c 7877MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
df878d8f 7878module_param_named(disable, iwl3945_mod_params.disable, int, 0444);
b481de9c 7879MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
df878d8f 7880module_param_named(hwcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
b481de9c
ZY		 7881MODULE_PARM_DESC(hwcrypto,
7882 "using hardware crypto engine (default 0 [software])\n");
df878d8f 7883module_param_named(debug, iwl3945_mod_params.debug, uint, 0444);
b481de9c 7884MODULE_PARM_DESC(debug, "debug output mask");
df878d8f 7885module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
b481de9c
ZY		 7886MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
7887
df878d8f 7888module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444);
b481de9c
ZY		 7889MODULE_PARM_DESC(queues_num, "number of hw queues.");
7890
bb8c093b
CH		 7891module_exit(iwl3945_exit);
7892module_init(iwl3945_init);
Linux kernel - Deliverables
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