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iwlwifi: hw names cleanup
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl4965-base.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/version.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
b481de9c
ZY		 41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
b481de9c
ZY		 44#include <net/mac80211.h>
45
46#include <asm/div64.h>
47
6bc913bd 48#include "iwl-eeprom.h"
82b9a121 49#include "iwl-core.h"
b481de9c 50#include "iwl-4965.h"
3395f6e9 51#include "iwl-io.h"
b481de9c
ZY		 52#include "iwl-helpers.h"
53
c79dd5b5 54static int iwl4965_tx_queue_update_write_ptr(struct iwl_priv *priv,
bb8c093b 55 struct iwl4965_tx_queue *txq);
416e1438 56
b481de9c
ZY		 57/******************************************************************************
58 *
59 * module boiler plate
60 *
61 ******************************************************************************/
62
b481de9c
ZY		 63/*
64 * module name, copyright, version, etc.
65 * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
66 */
67
68#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link 4965AGN driver for Linux"
69
0a6857e7 70#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 71#define VD "d"
72#else
73#define VD
74#endif
75
c8b0e6e1 76#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
b481de9c
ZY		 77#define VS "s"
78#else
79#define VS
80#endif
81
df48c323 82#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 83
b481de9c
ZY		 84
85MODULE_DESCRIPTION(DRV_DESCRIPTION);
86MODULE_VERSION(DRV_VERSION);
87MODULE_AUTHOR(DRV_COPYRIGHT);
88MODULE_LICENSE("GPL");
89
90__le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
91{
92 u16 fc = le16_to_cpu(hdr->frame_control);
93 int hdr_len = ieee80211_get_hdrlen(fc);
94
95 if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
96 return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
97 return NULL;
98}
99
8318d78a 100static const struct ieee80211_supported_band *iwl4965_get_hw_mode(
c79dd5b5 101 struct iwl_priv *priv, enum ieee80211_band band)
b481de9c 102{
8318d78a 103 return priv->hw->wiphy->bands[band];
b481de9c
ZY		 104}
105
bb8c093b 106static int iwl4965_is_empty_essid(const char *essid, int essid_len)
b481de9c
ZY		 107{
108 /* Single white space is for Linksys APs */
109 if (essid_len == 1 && essid[0] == ' ')
110 return 1;
111
112 /* Otherwise, if the entire essid is 0, we assume it is hidden */
113 while (essid_len) {
114 essid_len--;
115 if (essid[essid_len] != '\0')
116 return 0;
117 }
118
119 return 1;
120}
121
bb8c093b 122static const char *iwl4965_escape_essid(const char *essid, u8 essid_len)
b481de9c
ZY		 123{
124 static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
125 const char *s = essid;
126 char *d = escaped;
127
bb8c093b 128 if (iwl4965_is_empty_essid(essid, essid_len)) {
b481de9c
ZY		 129 memcpy(escaped, "<hidden>", sizeof("<hidden>"));
130 return escaped;
131 }
132
133 essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
134 while (essid_len--) {
135 if (*s == '\0') {
136 *d++ = '\\';
137 *d++ = '0';
138 s++;
139 } else
140 *d++ = *s++;
141 }
142 *d = '\0';
143 return escaped;
144}
145
b481de9c
ZY		 146/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
147 * DMA services
148 *
149 * Theory of operation
150 *
6440adb5
CB		 151 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
152 * of buffer descriptors, each of which points to one or more data buffers for
153 * the device to read from or fill. Driver and device exchange status of each
154 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
155 * entries in each circular buffer, to protect against confusing empty and full
156 * queue states.
157 *
158 * The device reads or writes the data in the queues via the device's several
159 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
b481de9c
ZY		 160 *
161 * For Tx queue, there are low mark and high mark limits. If, after queuing
162 * the packet for Tx, free space become < low mark, Tx queue stopped. When
163 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
164 * Tx queue resumed.
165 *
6440adb5
CB		 166 * The 4965 operates with up to 17 queues: One receive queue, one transmit
167 * queue (#4) for sending commands to the device firmware, and 15 other
168 * Tx queues that may be mapped to prioritized Tx DMA/FIFO channels.
e3851447
BC		 169 *
170 * See more detailed info in iwl-4965-hw.h.
b481de9c
ZY		 171 ***************************************************/
172
fe01b477 173int iwl4965_queue_space(const struct iwl4965_queue *q)
b481de9c 174{
fc4b6853 175 int s = q->read_ptr - q->write_ptr;
b481de9c 176
fc4b6853 177 if (q->read_ptr > q->write_ptr)
b481de9c
ZY		 178 s -= q->n_bd;
179
180 if (s <= 0)
181 s += q->n_window;
182 /* keep some reserve to not confuse empty and full situations */
183 s -= 2;
184 if (s < 0)
185 s = 0;
186 return s;
187}
188
b481de9c 189
bb8c093b 190static inline int x2_queue_used(const struct iwl4965_queue *q, int i)
b481de9c 191{
fc4b6853
TW		 192 return q->write_ptr > q->read_ptr ?
193 (i >= q->read_ptr && i < q->write_ptr) :
194 !(i < q->read_ptr && i >= q->write_ptr);
b481de9c
ZY		 195}
196
bb8c093b 197static inline u8 get_cmd_index(struct iwl4965_queue *q, u32 index, int is_huge)
b481de9c 198{
6440adb5 199 /* This is for scan command, the big buffer at end of command array */
b481de9c 200 if (is_huge)
6440adb5 201 return q->n_window; /* must be power of 2 */
b481de9c 202
6440adb5 203 /* Otherwise, use normal size buffers */
b481de9c
ZY		 204 return index & (q->n_window - 1);
205}
206
6440adb5
CB		 207/**
208 * iwl4965_queue_init - Initialize queue's high/low-water and read/write indexes
209 */
c79dd5b5 210static int iwl4965_queue_init(struct iwl_priv *priv, struct iwl4965_queue *q,
b481de9c
ZY		 211 int count, int slots_num, u32 id)
212{
213 q->n_bd = count;
214 q->n_window = slots_num;
215 q->id = id;
216
c54b679d
TW		 217 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
218 * and iwl_queue_dec_wrap are broken. */
b481de9c
ZY		 219 BUG_ON(!is_power_of_2(count));
220
221 /* slots_num must be power-of-two size, otherwise
222 * get_cmd_index is broken. */
223 BUG_ON(!is_power_of_2(slots_num));
224
225 q->low_mark = q->n_window / 4;
226 if (q->low_mark < 4)
227 q->low_mark = 4;
228
229 q->high_mark = q->n_window / 8;
230 if (q->high_mark < 2)
231 q->high_mark = 2;
232
fc4b6853 233 q->write_ptr = q->read_ptr = 0;
b481de9c
ZY		 234
235 return 0;
236}
237
6440adb5
CB		 238/**
239 * iwl4965_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
240 */
c79dd5b5 241static int iwl4965_tx_queue_alloc(struct iwl_priv *priv,
bb8c093b 242 struct iwl4965_tx_queue *txq, u32 id)
b481de9c
ZY		 243{
244 struct pci_dev *dev = priv->pci_dev;
245
6440adb5
CB		 246 /* Driver private data, only for Tx (not command) queues,
247 * not shared with device. */
b481de9c
ZY		 248 if (id != IWL_CMD_QUEUE_NUM) {
249 txq->txb = kmalloc(sizeof(txq->txb[0]) *
250 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
251 if (!txq->txb) {
01ebd063 252 IWL_ERROR("kmalloc for auxiliary BD "
b481de9c
ZY		 253 "structures failed\n");
254 goto error;
255 }
256 } else
257 txq->txb = NULL;
258
6440adb5
CB		 259 /* Circular buffer of transmit frame descriptors (TFDs),
260 * shared with device */
b481de9c
ZY		 261 txq->bd = pci_alloc_consistent(dev,
262 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
263 &txq->q.dma_addr);
264
265 if (!txq->bd) {
266 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
267 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
268 goto error;
269 }
270 txq->q.id = id;
271
272 return 0;
273
274 error:
275 if (txq->txb) {
276 kfree(txq->txb);
277 txq->txb = NULL;
278 }
279
280 return -ENOMEM;
281}
282
8b6eaea8
CB		 283/**
284 * iwl4965_tx_queue_init - Allocate and initialize one tx/cmd queue
285 */
c79dd5b5 286int iwl4965_tx_queue_init(struct iwl_priv *priv,
bb8c093b 287 struct iwl4965_tx_queue *txq, int slots_num, u32 txq_id)
b481de9c
ZY		 288{
289 struct pci_dev *dev = priv->pci_dev;
290 int len;
291 int rc = 0;
292
8b6eaea8
CB		 293 /*
294 * Alloc buffer array for commands (Tx or other types of commands).
295 * For the command queue (#4), allocate command space + one big
296 * command for scan, since scan command is very huge; the system will
297 * not have two scans at the same time, so only one is needed.
bb54244b 298 * For normal Tx queues (all other queues), no super-size command
8b6eaea8
CB		 299 * space is needed.
300 */
857485c0 301 len = sizeof(struct iwl_cmd) * slots_num;
b481de9c
ZY		 302 if (txq_id == IWL_CMD_QUEUE_NUM)
303 len += IWL_MAX_SCAN_SIZE;
304 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
305 if (!txq->cmd)
306 return -ENOMEM;
307
8b6eaea8 308 /* Alloc driver data array and TFD circular buffer */
bb8c093b 309 rc = iwl4965_tx_queue_alloc(priv, txq, txq_id);
b481de9c
ZY		 310 if (rc) {
311 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
312
313 return -ENOMEM;
314 }
315 txq->need_update = 0;
316
317 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
c54b679d 318 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
b481de9c 319 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
8b6eaea8
CB		 320
321 /* Initialize queue's high/low-water marks, and head/tail indexes */
bb8c093b 322 iwl4965_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
b481de9c 323
8b6eaea8 324 /* Tell device where to find queue */
bb8c093b 325 iwl4965_hw_tx_queue_init(priv, txq);
b481de9c
ZY		 326
327 return 0;
328}
329
330/**
bb8c093b 331 * iwl4965_tx_queue_free - Deallocate DMA queue.
b481de9c
ZY		 332 * @txq: Transmit queue to deallocate.
333 *
334 * Empty queue by removing and destroying all BD's.
6440adb5
CB		 335 * Free all buffers.
336 * 0-fill, but do not free "txq" descriptor structure.
b481de9c 337 */
c79dd5b5 338void iwl4965_tx_queue_free(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c 339{
bb8c093b 340 struct iwl4965_queue *q = &txq->q;
b481de9c
ZY		 341 struct pci_dev *dev = priv->pci_dev;
342 int len;
343
344 if (q->n_bd == 0)
345 return;
346
347 /* first, empty all BD's */
fc4b6853 348 for (; q->write_ptr != q->read_ptr;
c54b679d 349 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
bb8c093b 350 iwl4965_hw_txq_free_tfd(priv, txq);
b481de9c 351
857485c0 352 len = sizeof(struct iwl_cmd) * q->n_window;
b481de9c
ZY		 353 if (q->id == IWL_CMD_QUEUE_NUM)
354 len += IWL_MAX_SCAN_SIZE;
355
6440adb5 356 /* De-alloc array of command/tx buffers */
b481de9c
ZY		 357 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
358
6440adb5 359 /* De-alloc circular buffer of TFDs */
b481de9c 360 if (txq->q.n_bd)
bb8c093b 361 pci_free_consistent(dev, sizeof(struct iwl4965_tfd_frame) *
b481de9c
ZY		 362 txq->q.n_bd, txq->bd, txq->q.dma_addr);
363
6440adb5 364 /* De-alloc array of per-TFD driver data */
b481de9c
ZY		 365 if (txq->txb) {
366 kfree(txq->txb);
367 txq->txb = NULL;
368 }
369
6440adb5 370 /* 0-fill queue descriptor structure */
b481de9c
ZY		 371 memset(txq, 0, sizeof(*txq));
372}
373
bb8c093b 374const u8 iwl4965_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
b481de9c
ZY		 375
376/*************** STATION TABLE MANAGEMENT ****
9fbab516 377 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 378 * the functionality provided here
379 */
380
381/**************************************************************/
382
01ebd063 383#if 0 /* temporary disable till we add real remove station */
6440adb5
CB		 384/**
385 * iwl4965_remove_station - Remove driver's knowledge of station.
386 *
387 * NOTE: This does not remove station from device's station table.
388 */
c79dd5b5 389static u8 iwl4965_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 390{
391 int index = IWL_INVALID_STATION;
392 int i;
393 unsigned long flags;
394
395 spin_lock_irqsave(&priv->sta_lock, flags);
396
397 if (is_ap)
398 index = IWL_AP_ID;
399 else if (is_broadcast_ether_addr(addr))
400 index = priv->hw_setting.bcast_sta_id;
401 else
402 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
403 if (priv->stations[i].used &&
404 !compare_ether_addr(priv->stations[i].sta.sta.addr,
405 addr)) {
406 index = i;
407 break;
408 }
409
410 if (unlikely(index == IWL_INVALID_STATION))
411 goto out;
412
413 if (priv->stations[index].used) {
414 priv->stations[index].used = 0;
415 priv->num_stations--;
416 }
417
418 BUG_ON(priv->num_stations < 0);
419
420out:
421 spin_unlock_irqrestore(&priv->sta_lock, flags);
422 return 0;
423}
556f8db7 424#endif
b481de9c 425
6440adb5
CB		 426/**
427 * iwl4965_add_station_flags - Add station to tables in driver and device
428 */
c79dd5b5 429u8 iwl4965_add_station_flags(struct iwl_priv *priv, const u8 *addr,
67d62035 430 int is_ap, u8 flags, void *ht_data)
b481de9c
ZY		 431{
432 int i;
433 int index = IWL_INVALID_STATION;
bb8c093b 434 struct iwl4965_station_entry *station;
b481de9c 435 unsigned long flags_spin;
0795af57 436 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 437
438 spin_lock_irqsave(&priv->sta_lock, flags_spin);
439 if (is_ap)
440 index = IWL_AP_ID;
441 else if (is_broadcast_ether_addr(addr))
442 index = priv->hw_setting.bcast_sta_id;
443 else
444 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
445 if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
446 addr)) {
447 index = i;
448 break;
449 }
450
451 if (!priv->stations[i].used &&
452 index == IWL_INVALID_STATION)
453 index = i;
454 }
455
456
9fbab516
BC		 457 /* These two conditions have the same outcome, but keep them separate
458 since they have different meanings */
b481de9c
ZY		 459 if (unlikely(index == IWL_INVALID_STATION)) {
460 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
461 return index;
462 }
463
464 if (priv->stations[index].used &&
465 !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
466 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
467 return index;
468 }
469
470
0795af57 471 IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
b481de9c
ZY		 472 station = &priv->stations[index];
473 station->used = 1;
474 priv->num_stations++;
475
6440adb5 476 /* Set up the REPLY_ADD_STA command to send to device */
bb8c093b 477 memset(&station->sta, 0, sizeof(struct iwl4965_addsta_cmd));
b481de9c
ZY		 478 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
479 station->sta.mode = 0;
480 station->sta.sta.sta_id = index;
481 station->sta.station_flags = 0;
482
c8b0e6e1 483#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 484 /* BCAST station and IBSS stations do not work in HT mode */
485 if (index != priv->hw_setting.bcast_sta_id &&
486 priv->iw_mode != IEEE80211_IF_TYPE_IBSS)
67d62035
RR		 487 iwl4965_set_ht_add_station(priv, index,
488 (struct ieee80211_ht_info *) ht_data);
c8b0e6e1 489#endif /*CONFIG_IWL4965_HT*/
b481de9c
ZY		 490
491 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
6440adb5
CB		 492
493 /* Add station to device's station table */
bb8c093b 494 iwl4965_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 495 return index;
496
497}
498
499/*************** DRIVER STATUS FUNCTIONS *****/
500
c79dd5b5 501static inline int iwl4965_is_ready(struct iwl_priv *priv)
b481de9c
ZY		 502{
503 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
504 * set but EXIT_PENDING is not */
505 return test_bit(STATUS_READY, &priv->status) &&
506 test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
507 !test_bit(STATUS_EXIT_PENDING, &priv->status);
508}
509
c79dd5b5 510static inline int iwl4965_is_alive(struct iwl_priv *priv)
b481de9c
ZY		 511{
512 return test_bit(STATUS_ALIVE, &priv->status);
513}
514
c79dd5b5 515static inline int iwl4965_is_init(struct iwl_priv *priv)
b481de9c
ZY		 516{
517 return test_bit(STATUS_INIT, &priv->status);
518}
519
c79dd5b5 520static inline int iwl4965_is_rfkill(struct iwl_priv *priv)
b481de9c
ZY		 521{
522 return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
523 test_bit(STATUS_RF_KILL_SW, &priv->status);
524}
525
c79dd5b5 526static inline int iwl4965_is_ready_rf(struct iwl_priv *priv)
b481de9c
ZY		 527{
528
bb8c093b 529 if (iwl4965_is_rfkill(priv))
b481de9c
ZY		 530 return 0;
531
bb8c093b 532 return iwl4965_is_ready(priv);
b481de9c
ZY		 533}
534
535/*************** HOST COMMAND QUEUE FUNCTIONS *****/
536
b481de9c 537/**
bb8c093b 538 * iwl4965_enqueue_hcmd - enqueue a uCode command
b481de9c
ZY		 539 * @priv: device private data point
540 * @cmd: a point to the ucode command structure
541 *
542 * The function returns < 0 values to indicate the operation is
543 * failed. On success, it turns the index (> 0) of command in the
544 * command queue.
545 */
857485c0 546int iwl4965_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
b481de9c 547{
bb8c093b
CH		 548 struct iwl4965_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
549 struct iwl4965_queue *q = &txq->q;
550 struct iwl4965_tfd_frame *tfd;
b481de9c 551 u32 *control_flags;
857485c0 552 struct iwl_cmd *out_cmd;
b481de9c
ZY		 553 u32 idx;
554 u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
555 dma_addr_t phys_addr;
556 int ret;
557 unsigned long flags;
558
559 /* If any of the command structures end up being larger than
560 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
561 * we will need to increase the size of the TFD entries */
562 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
563 !(cmd->meta.flags & CMD_SIZE_HUGE));
564
c342a1b9
GG		 565 if (iwl4965_is_rfkill(priv)) {
566 IWL_DEBUG_INFO("Not sending command - RF KILL");
567 return -EIO;
568 }
569
bb8c093b 570 if (iwl4965_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
b481de9c
ZY		 571 IWL_ERROR("No space for Tx\n");
572 return -ENOSPC;
573 }
574
575 spin_lock_irqsave(&priv->hcmd_lock, flags);
576
fc4b6853 577 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 578 memset(tfd, 0, sizeof(*tfd));
579
580 control_flags = (u32 *) tfd;
581
fc4b6853 582 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
b481de9c
ZY		 583 out_cmd = &txq->cmd[idx];
584
585 out_cmd->hdr.cmd = cmd->id;
586 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
587 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
588
589 /* At this point, the out_cmd now has all of the incoming cmd
590 * information */
591
592 out_cmd->hdr.flags = 0;
593 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
fc4b6853 594 INDEX_TO_SEQ(q->write_ptr));
b481de9c
ZY		 595 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
596 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
597
598 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
857485c0 599 offsetof(struct iwl_cmd, hdr);
bb8c093b 600 iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
b481de9c
ZY		 601
602 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
603 "%d bytes at %d[%d]:%d\n",
604 get_cmd_string(out_cmd->hdr.cmd),
605 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
fc4b6853 606 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
b481de9c
ZY		 607
608 txq->need_update = 1;
6440adb5
CB		 609
610 /* Set up entry in queue's byte count circular buffer */
b481de9c 611 ret = iwl4965_tx_queue_update_wr_ptr(priv, txq, 0);
6440adb5
CB		 612
613 /* Increment and update queue's write index */
c54b679d 614 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 615 iwl4965_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 616
617 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
618 return ret ? ret : idx;
619}
620
deb09c43
EG		 621static void iwl4965_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
622{
623 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
624
625 if (hw_decrypt)
626 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
627 else
628 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
629
630}
631
c79dd5b5 632int iwl4965_send_statistics_request(struct iwl_priv *priv)
b481de9c 633{
857485c0
TW		 634 u32 flags = 0;
635 return iwl_send_cmd_pdu(priv, REPLY_STATISTICS_CMD,
636 sizeof(flags), &flags);
b481de9c
ZY		 637}
638
639/**
bb8c093b 640 * iwl4965_rxon_add_station - add station into station table.
b481de9c
ZY		 641 *
642 * there is only one AP station with id= IWL_AP_ID
9fbab516
BC		 643 * NOTE: mutex must be held before calling this fnction
644 */
c79dd5b5 645static int iwl4965_rxon_add_station(struct iwl_priv *priv,
b481de9c
ZY		 646 const u8 *addr, int is_ap)
647{
556f8db7 648 u8 sta_id;
b481de9c 649
6440adb5 650 /* Add station to device's station table */
67d62035
RR		 651#ifdef CONFIG_IWL4965_HT
652 struct ieee80211_conf *conf = &priv->hw->conf;
653 struct ieee80211_ht_info *cur_ht_config = &conf->ht_conf;
654
655 if ((is_ap) &&
656 (conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) &&
657 (priv->iw_mode == IEEE80211_IF_TYPE_STA))
658 sta_id = iwl4965_add_station_flags(priv, addr, is_ap,
659 0, cur_ht_config);
660 else
661#endif /* CONFIG_IWL4965_HT */
662 sta_id = iwl4965_add_station_flags(priv, addr, is_ap,
663 0, NULL);
6440adb5
CB		 664
665 /* Set up default rate scaling table in device's station table */
b481de9c
ZY		 666 iwl4965_add_station(priv, addr, is_ap);
667
556f8db7 668 return sta_id;
b481de9c
ZY		 669}
670
b481de9c 671/**
bb8c093b 672 * iwl4965_check_rxon_cmd - validate RXON structure is valid
b481de9c
ZY		 673 *
674 * NOTE: This is really only useful during development and can eventually
675 * be #ifdef'd out once the driver is stable and folks aren't actively
676 * making changes
677 */
bb8c093b 678static int iwl4965_check_rxon_cmd(struct iwl4965_rxon_cmd *rxon)
b481de9c
ZY		 679{
680 int error = 0;
681 int counter = 1;
682
683 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
684 error |= le32_to_cpu(rxon->flags &
685 (RXON_FLG_TGJ_NARROW_BAND_MSK |
686 RXON_FLG_RADAR_DETECT_MSK));
687 if (error)
688 IWL_WARNING("check 24G fields %d | %d\n",
689 counter++, error);
690 } else {
691 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
692 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
693 if (error)
694 IWL_WARNING("check 52 fields %d | %d\n",
695 counter++, error);
696 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
697 if (error)
698 IWL_WARNING("check 52 CCK %d | %d\n",
699 counter++, error);
700 }
701 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
702 if (error)
703 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
704
705 /* make sure basic rates 6Mbps and 1Mbps are supported */
706 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
707 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
708 if (error)
709 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
710
711 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
712 if (error)
713 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
714
715 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
716 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
717 if (error)
718 IWL_WARNING("check CCK and short slot %d | %d\n",
719 counter++, error);
720
721 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
722 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
723 if (error)
724 IWL_WARNING("check CCK & auto detect %d | %d\n",
725 counter++, error);
726
727 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
728 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
729 if (error)
730 IWL_WARNING("check TGG and auto detect %d | %d\n",
731 counter++, error);
732
733 if (error)
734 IWL_WARNING("Tuning to channel %d\n",
735 le16_to_cpu(rxon->channel));
736
737 if (error) {
bb8c093b 738 IWL_ERROR("Not a valid iwl4965_rxon_assoc_cmd field values\n");
b481de9c
ZY		 739 return -1;
740 }
741 return 0;
742}
743
744/**
9fbab516 745 * iwl4965_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
01ebd063 746 * @priv: staging_rxon is compared to active_rxon
b481de9c 747 *
9fbab516
BC		 748 * If the RXON structure is changing enough to require a new tune,
749 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
750 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
b481de9c 751 */
c79dd5b5 752static int iwl4965_full_rxon_required(struct iwl_priv *priv)
b481de9c
ZY		 753{
754
755 /* These items are only settable from the full RXON command */
756 if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
757 compare_ether_addr(priv->staging_rxon.bssid_addr,
758 priv->active_rxon.bssid_addr) ||
759 compare_ether_addr(priv->staging_rxon.node_addr,
760 priv->active_rxon.node_addr) ||
761 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
762 priv->active_rxon.wlap_bssid_addr) ||
763 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
764 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
765 (priv->staging_rxon.air_propagation !=
766 priv->active_rxon.air_propagation) ||
767 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
768 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
769 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
770 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
771 (priv->staging_rxon.rx_chain != priv->active_rxon.rx_chain) ||
772 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
773 return 1;
774
775 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
776 * be updated with the RXON_ASSOC command -- however only some
777 * flag transitions are allowed using RXON_ASSOC */
778
779 /* Check if we are not switching bands */
780 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
781 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
782 return 1;
783
784 /* Check if we are switching association toggle */
785 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
786 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
787 return 1;
788
789 return 0;
790}
791
c79dd5b5 792static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
b481de9c
ZY		 793{
794 int rc = 0;
bb8c093b
CH		 795 struct iwl4965_rx_packet *res = NULL;
796 struct iwl4965_rxon_assoc_cmd rxon_assoc;
857485c0 797 struct iwl_host_cmd cmd = {
b481de9c
ZY		 798 .id = REPLY_RXON_ASSOC,
799 .len = sizeof(rxon_assoc),
800 .meta.flags = CMD_WANT_SKB,
801 .data = &rxon_assoc,
802 };
bb8c093b
CH		 803 const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
804 const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
b481de9c
ZY		 805
806 if ((rxon1->flags == rxon2->flags) &&
807 (rxon1->filter_flags == rxon2->filter_flags) &&
808 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
809 (rxon1->ofdm_ht_single_stream_basic_rates ==
810 rxon2->ofdm_ht_single_stream_basic_rates) &&
811 (rxon1->ofdm_ht_dual_stream_basic_rates ==
812 rxon2->ofdm_ht_dual_stream_basic_rates) &&
813 (rxon1->rx_chain == rxon2->rx_chain) &&
814 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
815 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
816 return 0;
817 }
818
819 rxon_assoc.flags = priv->staging_rxon.flags;
820 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
821 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
822 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
823 rxon_assoc.reserved = 0;
824 rxon_assoc.ofdm_ht_single_stream_basic_rates =
825 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
826 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
827 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
828 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
829
857485c0 830 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 831 if (rc)
832 return rc;
833
bb8c093b 834 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 835 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
836 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
837 rc = -EIO;
838 }
839
840 priv->alloc_rxb_skb--;
841 dev_kfree_skb_any(cmd.meta.u.skb);
842
843 return rc;
844}
845
846/**
bb8c093b 847 * iwl4965_commit_rxon - commit staging_rxon to hardware
b481de9c 848 *
01ebd063 849 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 850 * the active_rxon structure is updated with the new data. This
851 * function correctly transitions out of the RXON_ASSOC_MSK state if
852 * a HW tune is required based on the RXON structure changes.
853 */
c79dd5b5 854static int iwl4965_commit_rxon(struct iwl_priv *priv)
b481de9c
ZY		 855{
856 /* cast away the const for active_rxon in this function */
bb8c093b 857 struct iwl4965_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
0795af57 858 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 859 int rc = 0;
860
bb8c093b 861 if (!iwl4965_is_alive(priv))
b481de9c
ZY		 862 return -1;
863
864 /* always get timestamp with Rx frame */
865 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
866
bb8c093b 867 rc = iwl4965_check_rxon_cmd(&priv->staging_rxon);
b481de9c
ZY		 868 if (rc) {
869 IWL_ERROR("Invalid RXON configuration. Not committing.\n");
870 return -EINVAL;
871 }
872
873 /* If we don't need to send a full RXON, we can use
bb8c093b 874 * iwl4965_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 875 * and other flags for the current radio configuration. */
bb8c093b
CH		 876 if (!iwl4965_full_rxon_required(priv)) {
877 rc = iwl4965_send_rxon_assoc(priv);
b481de9c
ZY		 878 if (rc) {
879 IWL_ERROR("Error setting RXON_ASSOC "
880 "configuration (%d).\n", rc);
881 return rc;
882 }
883
884 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
885
886 return 0;
887 }
888
889 /* station table will be cleared */
890 priv->assoc_station_added = 0;
891
c8b0e6e1 892#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 893 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
894 if (!priv->error_recovering)
895 priv->start_calib = 0;
896
897 iwl4965_init_sensitivity(priv, CMD_ASYNC, 1);
c8b0e6e1 898#endif /* CONFIG_IWL4965_SENSITIVITY */
b481de9c
ZY		 899
900 /* If we are currently associated and the new config requires
901 * an RXON_ASSOC and the new config wants the associated mask enabled,
902 * we must clear the associated from the active configuration
903 * before we apply the new config */
3109ece1 904 if (iwl_is_associated(priv) &&
b481de9c
ZY		 905 (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
906 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
907 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
908
857485c0 909 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
bb8c093b 910 sizeof(struct iwl4965_rxon_cmd),
b481de9c
ZY		 911 &priv->active_rxon);
912
913 /* If the mask clearing failed then we set
914 * active_rxon back to what it was previously */
915 if (rc) {
916 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
917 IWL_ERROR("Error clearing ASSOC_MSK on current "
918 "configuration (%d).\n", rc);
919 return rc;
920 }
b481de9c
ZY		 921 }
922
923 IWL_DEBUG_INFO("Sending RXON\n"
924 "* with%s RXON_FILTER_ASSOC_MSK\n"
925 "* channel = %d\n"
0795af57 926 "* bssid = %s\n",
b481de9c
ZY		 927 ((priv->staging_rxon.filter_flags &
928 RXON_FILTER_ASSOC_MSK) ? "" : "out"),
929 le16_to_cpu(priv->staging_rxon.channel),
0795af57 930 print_mac(mac, priv->staging_rxon.bssid_addr));
b481de9c 931
deb09c43 932 iwl4965_set_rxon_hwcrypto(priv, priv->cfg->mod_params->hw_crypto);
b481de9c 933 /* Apply the new configuration */
857485c0 934 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
bb8c093b 935 sizeof(struct iwl4965_rxon_cmd), &priv->staging_rxon);
b481de9c
ZY		 936 if (rc) {
937 IWL_ERROR("Error setting new configuration (%d).\n", rc);
938 return rc;
939 }
940
bf85ea4f 941 iwlcore_clear_stations_table(priv);
556f8db7 942
c8b0e6e1 943#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 944 if (!priv->error_recovering)
945 priv->start_calib = 0;
946
947 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
948 iwl4965_init_sensitivity(priv, CMD_ASYNC, 1);
c8b0e6e1 949#endif /* CONFIG_IWL4965_SENSITIVITY */
b481de9c
ZY		 950
951 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
952
953 /* If we issue a new RXON command which required a tune then we must
954 * send a new TXPOWER command or we won't be able to Tx any frames */
bb8c093b 955 rc = iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY		 956 if (rc) {
957 IWL_ERROR("Error setting Tx power (%d).\n", rc);
958 return rc;
959 }
960
961 /* Add the broadcast address so we can send broadcast frames */
bb8c093b 962 if (iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0) ==
b481de9c
ZY		 963 IWL_INVALID_STATION) {
964 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
965 return -EIO;
966 }
967
968 /* If we have set the ASSOC_MSK and we are in BSS mode then
969 * add the IWL_AP_ID to the station rate table */
3109ece1 970 if (iwl_is_associated(priv) &&
b481de9c 971 (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
bb8c093b 972 if (iwl4965_rxon_add_station(priv, priv->active_rxon.bssid_addr, 1)
b481de9c
ZY		 973 == IWL_INVALID_STATION) {
974 IWL_ERROR("Error adding AP address for transmit.\n");
975 return -EIO;
976 }
977 priv->assoc_station_added = 1;
978 }
979
980 return 0;
981}
982
c79dd5b5 983static int iwl4965_send_bt_config(struct iwl_priv *priv)
b481de9c 984{
bb8c093b 985 struct iwl4965_bt_cmd bt_cmd = {
b481de9c
ZY		 986 .flags = 3,
987 .lead_time = 0xAA,
988 .max_kill = 1,
989 .kill_ack_mask = 0,
990 .kill_cts_mask = 0,
991 };
992
857485c0 993 return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
bb8c093b 994 sizeof(struct iwl4965_bt_cmd), &bt_cmd);
b481de9c
ZY		 995}
996
c79dd5b5 997static int iwl4965_send_scan_abort(struct iwl_priv *priv)
b481de9c
ZY		 998{
999 int rc = 0;
bb8c093b 1000 struct iwl4965_rx_packet *res;
857485c0 1001 struct iwl_host_cmd cmd = {
b481de9c
ZY		 1002 .id = REPLY_SCAN_ABORT_CMD,
1003 .meta.flags = CMD_WANT_SKB,
1004 };
1005
1006 /* If there isn't a scan actively going on in the hardware
1007 * then we are in between scan bands and not actually
1008 * actively scanning, so don't send the abort command */
1009 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1010 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1011 return 0;
1012 }
1013
857485c0 1014 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 1015 if (rc) {
1016 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1017 return rc;
1018 }
1019
bb8c093b 1020 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1021 if (res->u.status != CAN_ABORT_STATUS) {
1022 /* The scan abort will return 1 for success or
1023 * 2 for "failure". A failure condition can be
1024 * due to simply not being in an active scan which
1025 * can occur if we send the scan abort before we
1026 * the microcode has notified us that a scan is
1027 * completed. */
1028 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1029 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1030 clear_bit(STATUS_SCAN_HW, &priv->status);
1031 }
1032
1033 dev_kfree_skb_any(cmd.meta.u.skb);
1034
1035 return rc;
1036}
1037
c79dd5b5 1038static int iwl4965_card_state_sync_callback(struct iwl_priv *priv,
857485c0 1039 struct iwl_cmd *cmd,
b481de9c
ZY		 1040 struct sk_buff *skb)
1041{
1042 return 1;
1043}
1044
1045/*
1046 * CARD_STATE_CMD
1047 *
9fbab516 1048 * Use: Sets the device's internal card state to enable, disable, or halt
b481de9c
ZY		 1049 *
1050 * When in the 'enable' state the card operates as normal.
1051 * When in the 'disable' state, the card enters into a low power mode.
1052 * When in the 'halt' state, the card is shut down and must be fully
1053 * restarted to come back on.
1054 */
c79dd5b5 1055static int iwl4965_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
b481de9c 1056{
857485c0 1057 struct iwl_host_cmd cmd = {
b481de9c
ZY		 1058 .id = REPLY_CARD_STATE_CMD,
1059 .len = sizeof(u32),
1060 .data = &flags,
1061 .meta.flags = meta_flag,
1062 };
1063
1064 if (meta_flag & CMD_ASYNC)
bb8c093b 1065 cmd.meta.u.callback = iwl4965_card_state_sync_callback;
b481de9c 1066
857485c0 1067 return iwl_send_cmd(priv, &cmd);
b481de9c
ZY		 1068}
1069
c79dd5b5 1070static int iwl4965_add_sta_sync_callback(struct iwl_priv *priv,
857485c0 1071 struct iwl_cmd *cmd, struct sk_buff *skb)
b481de9c 1072{
bb8c093b 1073 struct iwl4965_rx_packet *res = NULL;
b481de9c
ZY		 1074
1075 if (!skb) {
1076 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1077 return 1;
1078 }
1079
bb8c093b 1080 res = (struct iwl4965_rx_packet *)skb->data;
b481de9c
ZY		 1081 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1082 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1083 res->hdr.flags);
1084 return 1;
1085 }
1086
1087 switch (res->u.add_sta.status) {
1088 case ADD_STA_SUCCESS_MSK:
1089 break;
1090 default:
1091 break;
1092 }
1093
1094 /* We didn't cache the SKB; let the caller free it */
1095 return 1;
1096}
1097
c79dd5b5 1098int iwl4965_send_add_station(struct iwl_priv *priv,
bb8c093b 1099 struct iwl4965_addsta_cmd *sta, u8 flags)
b481de9c 1100{
bb8c093b 1101 struct iwl4965_rx_packet *res = NULL;
b481de9c 1102 int rc = 0;
857485c0 1103 struct iwl_host_cmd cmd = {
b481de9c 1104 .id = REPLY_ADD_STA,
bb8c093b 1105 .len = sizeof(struct iwl4965_addsta_cmd),
b481de9c
ZY		 1106 .meta.flags = flags,
1107 .data = sta,
1108 };
1109
1110 if (flags & CMD_ASYNC)
bb8c093b 1111 cmd.meta.u.callback = iwl4965_add_sta_sync_callback;
b481de9c
ZY		 1112 else
1113 cmd.meta.flags |= CMD_WANT_SKB;
1114
857485c0 1115 rc = iwl_send_cmd(priv, &cmd);
b481de9c
ZY		 1116
1117 if (rc || (flags & CMD_ASYNC))
1118 return rc;
1119
bb8c093b 1120 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 1121 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1122 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1123 res->hdr.flags);
1124 rc = -EIO;
1125 }
1126
1127 if (rc == 0) {
1128 switch (res->u.add_sta.status) {
1129 case ADD_STA_SUCCESS_MSK:
1130 IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1131 break;
1132 default:
1133 rc = -EIO;
1134 IWL_WARNING("REPLY_ADD_STA failed\n");
1135 break;
1136 }
1137 }
1138
1139 priv->alloc_rxb_skb--;
1140 dev_kfree_skb_any(cmd.meta.u.skb);
1141
1142 return rc;
1143}
1144
deb09c43 1145static int iwl4965_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
b481de9c
ZY		 1146 struct ieee80211_key_conf *keyconf,
1147 u8 sta_id)
1148{
1149 unsigned long flags;
1150 __le16 key_flags = 0;
1151
deb09c43
EG		 1152 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
1153 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1154
1155 if (sta_id == priv->hw_setting.bcast_sta_id)
1156 key_flags |= STA_KEY_MULTICAST_MSK;
1157
1158 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1159 keyconf->hw_key_idx = keyconf->keyidx;
1160
1161 key_flags &= ~STA_KEY_FLG_INVALID;
1162
b481de9c
ZY		 1163 spin_lock_irqsave(&priv->sta_lock, flags);
1164 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1165 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
deb09c43 1166
b481de9c
ZY		 1167 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1168 keyconf->keylen);
1169
1170 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1171 keyconf->keylen);
deb09c43
EG		 1172
1173 priv->stations[sta_id].sta.key.key_offset
1174 = (sta_id % STA_KEY_MAX_NUM);/*FIXME*/
b481de9c
ZY		 1175 priv->stations[sta_id].sta.key.key_flags = key_flags;
1176 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1177 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1178
1179 spin_unlock_irqrestore(&priv->sta_lock, flags);
1180
1181 IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
deb09c43
EG		 1182 return iwl4965_send_add_station(priv,
1183 &priv->stations[sta_id].sta, CMD_ASYNC);
1184}
1185
1186static int iwl4965_set_tkip_dynamic_key_info(struct iwl_priv *priv,
1187 struct ieee80211_key_conf *keyconf,
1188 u8 sta_id)
1189{
2bc75089
EG		 1190 unsigned long flags;
1191 int ret = 0;
1192
1193 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1194 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1195 keyconf->hw_key_idx = keyconf->keyidx;
1196
1197 spin_lock_irqsave(&priv->sta_lock, flags);
1198
1199 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1200 priv->stations[sta_id].keyinfo.conf = keyconf;
1201 priv->stations[sta_id].keyinfo.keylen = 16;
1202
1203 /* This copy is acutally not needed: we get the key with each TX */
1204 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, 16);
1205
1206 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key, 16);
1207
1208 spin_unlock_irqrestore(&priv->sta_lock, flags);
1209
1210 return ret;
b481de9c
ZY		 1211}
1212
c79dd5b5 1213static int iwl4965_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
b481de9c
ZY		 1214{
1215 unsigned long flags;
1216
1217 spin_lock_irqsave(&priv->sta_lock, flags);
bb8c093b
CH		 1218 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl4965_hw_key));
1219 memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl4965_keyinfo));
b481de9c
ZY		 1220 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1221 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1222 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1223 spin_unlock_irqrestore(&priv->sta_lock, flags);
1224
1225 IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
bb8c093b 1226 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY		 1227 return 0;
1228}
1229
deb09c43
EG		 1230static int iwl4965_set_dynamic_key(struct iwl_priv *priv,
1231 struct ieee80211_key_conf *key, u8 sta_id)
1232{
1233 int ret;
1234
1235 switch (key->alg) {
1236 case ALG_CCMP:
1237 ret = iwl4965_set_ccmp_dynamic_key_info(priv, key, sta_id);
1238 break;
1239 case ALG_TKIP:
1240 ret = iwl4965_set_tkip_dynamic_key_info(priv, key, sta_id);
1241 break;
1242 case ALG_WEP:
1243 ret = -EOPNOTSUPP;
1244 break;
1245 default:
1246 IWL_ERROR("Unknown alg: %s alg = %d\n", __func__, key->alg);
1247 ret = -EINVAL;
1248 }
1249
1250 return ret;
1251}
1252
1253static int iwl4965_remove_static_key(struct iwl_priv *priv)
1254{
1255 int ret = -EOPNOTSUPP;
1256
1257 return ret;
1258}
1259
1260static int iwl4965_set_static_key(struct iwl_priv *priv,
1261 struct ieee80211_key_conf *key)
1262{
1263 if (key->alg == ALG_WEP)
1264 return -EOPNOTSUPP;
1265
1266 IWL_ERROR("Static key invalid: alg %d\n", key->alg);
1267 return -EINVAL;
1268}
1269
c79dd5b5 1270static void iwl4965_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 1271{
1272 struct list_head *element;
1273
1274 IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1275 priv->frames_count);
1276
1277 while (!list_empty(&priv->free_frames)) {
1278 element = priv->free_frames.next;
1279 list_del(element);
bb8c093b 1280 kfree(list_entry(element, struct iwl4965_frame, list));
b481de9c
ZY		 1281 priv->frames_count--;
1282 }
1283
1284 if (priv->frames_count) {
1285 IWL_WARNING("%d frames still in use. Did we lose one?\n",
1286 priv->frames_count);
1287 priv->frames_count = 0;
1288 }
1289}
1290
c79dd5b5 1291static struct iwl4965_frame *iwl4965_get_free_frame(struct iwl_priv *priv)
b481de9c 1292{
bb8c093b 1293 struct iwl4965_frame *frame;
b481de9c
ZY		 1294 struct list_head *element;
1295 if (list_empty(&priv->free_frames)) {
1296 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1297 if (!frame) {
1298 IWL_ERROR("Could not allocate frame!\n");
1299 return NULL;
1300 }
1301
1302 priv->frames_count++;
1303 return frame;
1304 }
1305
1306 element = priv->free_frames.next;
1307 list_del(element);
bb8c093b 1308 return list_entry(element, struct iwl4965_frame, list);
b481de9c
ZY		 1309}
1310
c79dd5b5 1311static void iwl4965_free_frame(struct iwl_priv *priv, struct iwl4965_frame *frame)
b481de9c
ZY		 1312{
1313 memset(frame, 0, sizeof(*frame));
1314 list_add(&frame->list, &priv->free_frames);
1315}
1316
c79dd5b5 1317unsigned int iwl4965_fill_beacon_frame(struct iwl_priv *priv,
b481de9c
ZY		 1318 struct ieee80211_hdr *hdr,
1319 const u8 *dest, int left)
1320{
1321
3109ece1 1322 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
b481de9c
ZY		 1323 ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
1324 (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
1325 return 0;
1326
1327 if (priv->ibss_beacon->len > left)
1328 return 0;
1329
1330 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1331
1332 return priv->ibss_beacon->len;
1333}
1334
bb8c093b 1335static u8 iwl4965_rate_get_lowest_plcp(int rate_mask)
b481de9c
ZY		 1336{
1337 u8 i;
1338
1339 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
bb8c093b 1340 i = iwl4965_rates[i].next_ieee) {
b481de9c 1341 if (rate_mask & (1 << i))
bb8c093b 1342 return iwl4965_rates[i].plcp;
b481de9c
ZY		 1343 }
1344
1345 return IWL_RATE_INVALID;
1346}
1347
c79dd5b5 1348static int iwl4965_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 1349{
bb8c093b 1350 struct iwl4965_frame *frame;
b481de9c
ZY		 1351 unsigned int frame_size;
1352 int rc;
1353 u8 rate;
1354
bb8c093b 1355 frame = iwl4965_get_free_frame(priv);
b481de9c
ZY		 1356
1357 if (!frame) {
1358 IWL_ERROR("Could not obtain free frame buffer for beacon "
1359 "command.\n");
1360 return -ENOMEM;
1361 }
1362
1363 if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
bb8c093b 1364 rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic &
b481de9c
ZY		 1365 0xFF0);
1366 if (rate == IWL_INVALID_RATE)
1367 rate = IWL_RATE_6M_PLCP;
1368 } else {
bb8c093b 1369 rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
b481de9c
ZY		 1370 if (rate == IWL_INVALID_RATE)
1371 rate = IWL_RATE_1M_PLCP;
1372 }
1373
bb8c093b 1374 frame_size = iwl4965_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 1375
857485c0 1376 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 1377 &frame->u.cmd[0]);
1378
bb8c093b 1379 iwl4965_free_frame(priv, frame);
b481de9c
ZY		 1380
1381 return rc;
1382}
1383
b481de9c
ZY		 1384/******************************************************************************
1385 *
1386 * Misc. internal state and helper functions
1387 *
1388 ******************************************************************************/
b481de9c 1389
c79dd5b5 1390static void iwl4965_unset_hw_setting(struct iwl_priv *priv)
b481de9c
ZY		 1391{
1392 if (priv->hw_setting.shared_virt)
1393 pci_free_consistent(priv->pci_dev,
bb8c093b 1394 sizeof(struct iwl4965_shared),
b481de9c
ZY		 1395 priv->hw_setting.shared_virt,
1396 priv->hw_setting.shared_phys);
1397}
1398
1399/**
bb8c093b 1400 * iwl4965_supported_rate_to_ie - fill in the supported rate in IE field
b481de9c
ZY		 1401 *
1402 * return : set the bit for each supported rate insert in ie
1403 */
bb8c093b 1404static u16 iwl4965_supported_rate_to_ie(u8 *ie, u16 supported_rate,
c7c46676 1405 u16 basic_rate, int *left)
b481de9c
ZY		 1406{
1407 u16 ret_rates = 0, bit;
1408 int i;
c7c46676
TW		 1409 u8 *cnt = ie;
1410 u8 *rates = ie + 1;
b481de9c
ZY		 1411
1412 for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1413 if (bit & supported_rate) {
1414 ret_rates |= bit;
bb8c093b 1415 rates[*cnt] = iwl4965_rates[i].ieee |
c7c46676
TW		 1416 ((bit & basic_rate) ? 0x80 : 0x00);
1417 (*cnt)++;
1418 (*left)--;
1419 if ((*left <= 0) ||
1420 (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
b481de9c
ZY		 1421 break;
1422 }
1423 }
1424
1425 return ret_rates;
1426}
1427
b481de9c 1428/**
bb8c093b 1429 * iwl4965_fill_probe_req - fill in all required fields and IE for probe request
b481de9c 1430 */
c79dd5b5 1431static u16 iwl4965_fill_probe_req(struct iwl_priv *priv,
78330fdd
TW		 1432 enum ieee80211_band band,
1433 struct ieee80211_mgmt *frame,
1434 int left, int is_direct)
b481de9c
ZY		 1435{
1436 int len = 0;
1437 u8 *pos = NULL;
bee488db 1438 u16 active_rates, ret_rates, cck_rates, active_rate_basic;
8fb88032 1439#ifdef CONFIG_IWL4965_HT
78330fdd
TW		 1440 const struct ieee80211_supported_band *sband =
1441 iwl4965_get_hw_mode(priv, band);
8fb88032 1442#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 1443
1444 /* Make sure there is enough space for the probe request,
1445 * two mandatory IEs and the data */
1446 left -= 24;
1447 if (left < 0)
1448 return 0;
1449 len += 24;
1450
1451 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
bb8c093b 1452 memcpy(frame->da, iwl4965_broadcast_addr, ETH_ALEN);
b481de9c 1453 memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
bb8c093b 1454 memcpy(frame->bssid, iwl4965_broadcast_addr, ETH_ALEN);
b481de9c
ZY		 1455 frame->seq_ctrl = 0;
1456
1457 /* fill in our indirect SSID IE */
1458 /* ...next IE... */
1459
1460 left -= 2;
1461 if (left < 0)
1462 return 0;
1463 len += 2;
1464 pos = &(frame->u.probe_req.variable[0]);
1465 *pos++ = WLAN_EID_SSID;
1466 *pos++ = 0;
1467
1468 /* fill in our direct SSID IE... */
1469 if (is_direct) {
1470 /* ...next IE... */
1471 left -= 2 + priv->essid_len;
1472 if (left < 0)
1473 return 0;
1474 /* ... fill it in... */
1475 *pos++ = WLAN_EID_SSID;
1476 *pos++ = priv->essid_len;
1477 memcpy(pos, priv->essid, priv->essid_len);
1478 pos += priv->essid_len;
1479 len += 2 + priv->essid_len;
1480 }
1481
1482 /* fill in supported rate */
1483 /* ...next IE... */
1484 left -= 2;
1485 if (left < 0)
1486 return 0;
c7c46676 1487
b481de9c
ZY		 1488 /* ... fill it in... */
1489 *pos++ = WLAN_EID_SUPP_RATES;
1490 *pos = 0;
c7c46676 1491
bee488db 1492 /* exclude 60M rate */
1493 active_rates = priv->rates_mask;
1494 active_rates &= ~IWL_RATE_60M_MASK;
1495
1496 active_rate_basic = active_rates & IWL_BASIC_RATES_MASK;
b481de9c 1497
c7c46676 1498 cck_rates = IWL_CCK_RATES_MASK & active_rates;
bb8c093b 1499 ret_rates = iwl4965_supported_rate_to_ie(pos, cck_rates,
bee488db 1500 active_rate_basic, &left);
c7c46676
TW		 1501 active_rates &= ~ret_rates;
1502
bb8c093b 1503 ret_rates = iwl4965_supported_rate_to_ie(pos, active_rates,
bee488db 1504 active_rate_basic, &left);
c7c46676
TW		 1505 active_rates &= ~ret_rates;
1506
b481de9c
ZY		 1507 len += 2 + *pos;
1508 pos += (*pos) + 1;
c7c46676 1509 if (active_rates == 0)
b481de9c
ZY		 1510 goto fill_end;
1511
1512 /* fill in supported extended rate */
1513 /* ...next IE... */
1514 left -= 2;
1515 if (left < 0)
1516 return 0;
1517 /* ... fill it in... */
1518 *pos++ = WLAN_EID_EXT_SUPP_RATES;
1519 *pos = 0;
bb8c093b 1520 iwl4965_supported_rate_to_ie(pos, active_rates,
bee488db 1521 active_rate_basic, &left);
b481de9c
ZY		 1522 if (*pos > 0)
1523 len += 2 + *pos;
1524
c8b0e6e1 1525#ifdef CONFIG_IWL4965_HT
78330fdd
TW		 1526 if (sband && sband->ht_info.ht_supported) {
1527 struct ieee80211_ht_cap *ht_cap;
b481de9c
ZY		 1528 pos += (*pos) + 1;
1529 *pos++ = WLAN_EID_HT_CAPABILITY;
8fb88032 1530 *pos++ = sizeof(struct ieee80211_ht_cap);
78330fdd
TW		 1531 ht_cap = (struct ieee80211_ht_cap *)pos;
1532 ht_cap->cap_info = cpu_to_le16(sband->ht_info.cap);
1533 memcpy(ht_cap->supp_mcs_set, sband->ht_info.supp_mcs_set, 16);
1534 ht_cap->ampdu_params_info =(sband->ht_info.ampdu_factor &
1535 IEEE80211_HT_CAP_AMPDU_FACTOR) |
1536 ((sband->ht_info.ampdu_density << 2) &
1537 IEEE80211_HT_CAP_AMPDU_DENSITY);
8fb88032 1538 len += 2 + sizeof(struct ieee80211_ht_cap);
b481de9c 1539 }
c8b0e6e1 1540#endif /*CONFIG_IWL4965_HT */
b481de9c
ZY		 1541
1542 fill_end:
1543 return (u16)len;
1544}
1545
1546/*
1547 * QoS support
1548*/
c79dd5b5 1549static int iwl4965_send_qos_params_command(struct iwl_priv *priv,
bb8c093b 1550 struct iwl4965_qosparam_cmd *qos)
b481de9c
ZY		 1551{
1552
857485c0 1553 return iwl_send_cmd_pdu(priv, REPLY_QOS_PARAM,
bb8c093b 1554 sizeof(struct iwl4965_qosparam_cmd), qos);
b481de9c
ZY		 1555}
1556
c79dd5b5 1557static void iwl4965_activate_qos(struct iwl_priv *priv, u8 force)
b481de9c
ZY		 1558{
1559 unsigned long flags;
1560
b481de9c
ZY		 1561 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1562 return;
1563
1564 if (!priv->qos_data.qos_enable)
1565 return;
1566
1567 spin_lock_irqsave(&priv->lock, flags);
1568 priv->qos_data.def_qos_parm.qos_flags = 0;
1569
1570 if (priv->qos_data.qos_cap.q_AP.queue_request &&
1571 !priv->qos_data.qos_cap.q_AP.txop_request)
1572 priv->qos_data.def_qos_parm.qos_flags |=
1573 QOS_PARAM_FLG_TXOP_TYPE_MSK;
b481de9c
ZY		 1574 if (priv->qos_data.qos_active)
1575 priv->qos_data.def_qos_parm.qos_flags |=
1576 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1577
c8b0e6e1 1578#ifdef CONFIG_IWL4965_HT
fd105e79 1579 if (priv->current_ht_config.is_ht)
f1f1f5c7 1580 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
c8b0e6e1 1581#endif /* CONFIG_IWL4965_HT */
f1f1f5c7 1582
b481de9c
ZY		 1583 spin_unlock_irqrestore(&priv->lock, flags);
1584
3109ece1 1585 if (force || iwl_is_associated(priv)) {
f1f1f5c7
TW		 1586 IWL_DEBUG_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
1587 priv->qos_data.qos_active,
1588 priv->qos_data.def_qos_parm.qos_flags);
b481de9c 1589
bb8c093b 1590 iwl4965_send_qos_params_command(priv,
b481de9c
ZY		 1591 &(priv->qos_data.def_qos_parm));
1592 }
1593}
1594
b481de9c
ZY		 1595/*
1596 * Power management (not Tx power!) functions
1597 */
1598#define MSEC_TO_USEC 1024
1599
1600#define NOSLP __constant_cpu_to_le16(0), 0, 0
1601#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
1602#define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1603#define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1604 __constant_cpu_to_le32(X1), \
1605 __constant_cpu_to_le32(X2), \
1606 __constant_cpu_to_le32(X3), \
1607 __constant_cpu_to_le32(X4)}
1608
1609
1610/* default power management (not Tx power) table values */
1611/* for tim 0-10 */
bb8c093b 1612static struct iwl4965_power_vec_entry range_0[IWL_POWER_AC] = {
b481de9c
ZY		 1613 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1614 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1615 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1616 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1617 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1618 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1619};
1620
1621/* for tim > 10 */
bb8c093b 1622static struct iwl4965_power_vec_entry range_1[IWL_POWER_AC] = {
b481de9c
ZY		 1623 {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1624 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1625 SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1626 {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1627 SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1628 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1629 SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1630 {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1631 {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1632 SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1633};
1634
c79dd5b5 1635int iwl4965_power_init_handle(struct iwl_priv *priv)
b481de9c
ZY		 1636{
1637 int rc = 0, i;
bb8c093b
CH		 1638 struct iwl4965_power_mgr *pow_data;
1639 int size = sizeof(struct iwl4965_power_vec_entry) * IWL_POWER_AC;
b481de9c
ZY		 1640 u16 pci_pm;
1641
1642 IWL_DEBUG_POWER("Initialize power \n");
1643
1644 pow_data = &(priv->power_data);
1645
1646 memset(pow_data, 0, sizeof(*pow_data));
1647
1648 pow_data->active_index = IWL_POWER_RANGE_0;
1649 pow_data->dtim_val = 0xffff;
1650
1651 memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1652 memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1653
1654 rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1655 if (rc != 0)
1656 return 0;
1657 else {
bb8c093b 1658 struct iwl4965_powertable_cmd *cmd;
b481de9c
ZY		 1659
1660 IWL_DEBUG_POWER("adjust power command flags\n");
1661
1662 for (i = 0; i < IWL_POWER_AC; i++) {
1663 cmd = &pow_data->pwr_range_0[i].cmd;
1664
1665 if (pci_pm & 0x1)
1666 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1667 else
1668 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1669 }
1670 }
1671 return rc;
1672}
1673
c79dd5b5 1674static int iwl4965_update_power_cmd(struct iwl_priv *priv,
bb8c093b 1675 struct iwl4965_powertable_cmd *cmd, u32 mode)
b481de9c
ZY		 1676{
1677 int rc = 0, i;
1678 u8 skip;
1679 u32 max_sleep = 0;
bb8c093b 1680 struct iwl4965_power_vec_entry *range;
b481de9c 1681 u8 period = 0;
bb8c093b 1682 struct iwl4965_power_mgr *pow_data;
b481de9c
ZY		 1683
1684 if (mode > IWL_POWER_INDEX_5) {
1685 IWL_DEBUG_POWER("Error invalid power mode \n");
1686 return -1;
1687 }
1688 pow_data = &(priv->power_data);
1689
1690 if (pow_data->active_index == IWL_POWER_RANGE_0)
1691 range = &pow_data->pwr_range_0[0];
1692 else
1693 range = &pow_data->pwr_range_1[1];
1694
bb8c093b 1695 memcpy(cmd, &range[mode].cmd, sizeof(struct iwl4965_powertable_cmd));
b481de9c
ZY		 1696
1697#ifdef IWL_MAC80211_DISABLE
1698 if (priv->assoc_network != NULL) {
1699 unsigned long flags;
1700
1701 period = priv->assoc_network->tim.tim_period;
1702 }
1703#endif /*IWL_MAC80211_DISABLE */
1704 skip = range[mode].no_dtim;
1705
1706 if (period == 0) {
1707 period = 1;
1708 skip = 0;
1709 }
1710
1711 if (skip == 0) {
1712 max_sleep = period;
1713 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1714 } else {
1715 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1716 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1717 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1718 }
1719
1720 for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1721 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1722 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1723 }
1724
1725 IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1726 IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1727 IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1728 IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1729 le32_to_cpu(cmd->sleep_interval[0]),
1730 le32_to_cpu(cmd->sleep_interval[1]),
1731 le32_to_cpu(cmd->sleep_interval[2]),
1732 le32_to_cpu(cmd->sleep_interval[3]),
1733 le32_to_cpu(cmd->sleep_interval[4]));
1734
1735 return rc;
1736}
1737
c79dd5b5 1738static int iwl4965_send_power_mode(struct iwl_priv *priv, u32 mode)
b481de9c 1739{
9a62f73b 1740 u32 uninitialized_var(final_mode);
b481de9c 1741 int rc;
bb8c093b 1742 struct iwl4965_powertable_cmd cmd;
b481de9c
ZY		 1743
1744 /* If on battery, set to 3,
01ebd063 1745 * if plugged into AC power, set to CAM ("continuously aware mode"),
b481de9c
ZY		 1746 * else user level */
1747 switch (mode) {
1748 case IWL_POWER_BATTERY:
1749 final_mode = IWL_POWER_INDEX_3;
1750 break;
1751 case IWL_POWER_AC:
1752 final_mode = IWL_POWER_MODE_CAM;
1753 break;
1754 default:
1755 final_mode = mode;
1756 break;
1757 }
1758
1759 cmd.keep_alive_beacons = 0;
1760
bb8c093b 1761 iwl4965_update_power_cmd(priv, &cmd, final_mode);
b481de9c 1762
857485c0 1763 rc = iwl_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 1764
1765 if (final_mode == IWL_POWER_MODE_CAM)
1766 clear_bit(STATUS_POWER_PMI, &priv->status);
1767 else
1768 set_bit(STATUS_POWER_PMI, &priv->status);
1769
1770 return rc;
1771}
1772
c79dd5b5 1773int iwl4965_is_network_packet(struct iwl_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 1774{
1775 /* Filter incoming packets to determine if they are targeted toward
1776 * this network, discarding packets coming from ourselves */
1777 switch (priv->iw_mode) {
1778 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
1779 /* packets from our adapter are dropped (echo) */
1780 if (!compare_ether_addr(header->addr2, priv->mac_addr))
1781 return 0;
1782 /* {broad,multi}cast packets to our IBSS go through */
1783 if (is_multicast_ether_addr(header->addr1))
1784 return !compare_ether_addr(header->addr3, priv->bssid);
1785 /* packets to our adapter go through */
1786 return !compare_ether_addr(header->addr1, priv->mac_addr);
1787 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
1788 /* packets from our adapter are dropped (echo) */
1789 if (!compare_ether_addr(header->addr3, priv->mac_addr))
1790 return 0;
1791 /* {broad,multi}cast packets to our BSS go through */
1792 if (is_multicast_ether_addr(header->addr1))
1793 return !compare_ether_addr(header->addr2, priv->bssid);
1794 /* packets to our adapter go through */
1795 return !compare_ether_addr(header->addr1, priv->mac_addr);
69dc5d9d
TW		 1796 default:
1797 break;
b481de9c
ZY		 1798 }
1799
1800 return 1;
1801}
1802
1803#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1804
bb8c093b 1805static const char *iwl4965_get_tx_fail_reason(u32 status)
b481de9c
ZY		 1806{
1807 switch (status & TX_STATUS_MSK) {
1808 case TX_STATUS_SUCCESS:
1809 return "SUCCESS";
1810 TX_STATUS_ENTRY(SHORT_LIMIT);
1811 TX_STATUS_ENTRY(LONG_LIMIT);
1812 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1813 TX_STATUS_ENTRY(MGMNT_ABORT);
1814 TX_STATUS_ENTRY(NEXT_FRAG);
1815 TX_STATUS_ENTRY(LIFE_EXPIRE);
1816 TX_STATUS_ENTRY(DEST_PS);
1817 TX_STATUS_ENTRY(ABORTED);
1818 TX_STATUS_ENTRY(BT_RETRY);
1819 TX_STATUS_ENTRY(STA_INVALID);
1820 TX_STATUS_ENTRY(FRAG_DROPPED);
1821 TX_STATUS_ENTRY(TID_DISABLE);
1822 TX_STATUS_ENTRY(FRAME_FLUSHED);
1823 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1824 TX_STATUS_ENTRY(TX_LOCKED);
1825 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1826 }
1827
1828 return "UNKNOWN";
1829}
1830
1831/**
bb8c093b 1832 * iwl4965_scan_cancel - Cancel any currently executing HW scan
b481de9c
ZY		 1833 *
1834 * NOTE: priv->mutex is not required before calling this function
1835 */
c79dd5b5 1836static int iwl4965_scan_cancel(struct iwl_priv *priv)
b481de9c
ZY		 1837{
1838 if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1839 clear_bit(STATUS_SCANNING, &priv->status);
1840 return 0;
1841 }
1842
1843 if (test_bit(STATUS_SCANNING, &priv->status)) {
1844 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1845 IWL_DEBUG_SCAN("Queuing scan abort.\n");
1846 set_bit(STATUS_SCAN_ABORTING, &priv->status);
1847 queue_work(priv->workqueue, &priv->abort_scan);
1848
1849 } else
1850 IWL_DEBUG_SCAN("Scan abort already in progress.\n");
1851
1852 return test_bit(STATUS_SCANNING, &priv->status);
1853 }
1854
1855 return 0;
1856}
1857
1858/**
bb8c093b 1859 * iwl4965_scan_cancel_timeout - Cancel any currently executing HW scan
b481de9c
ZY		 1860 * @ms: amount of time to wait (in milliseconds) for scan to abort
1861 *
1862 * NOTE: priv->mutex must be held before calling this function
1863 */
c79dd5b5 1864static int iwl4965_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms)
b481de9c
ZY		 1865{
1866 unsigned long now = jiffies;
1867 int ret;
1868
bb8c093b 1869 ret = iwl4965_scan_cancel(priv);
b481de9c
ZY		 1870 if (ret && ms) {
1871 mutex_unlock(&priv->mutex);
1872 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
1873 test_bit(STATUS_SCANNING, &priv->status))
1874 msleep(1);
1875 mutex_lock(&priv->mutex);
1876
1877 return test_bit(STATUS_SCANNING, &priv->status);
1878 }
1879
1880 return ret;
1881}
1882
c79dd5b5 1883static void iwl4965_sequence_reset(struct iwl_priv *priv)
b481de9c
ZY		 1884{
1885 /* Reset ieee stats */
1886
1887 /* We don't reset the net_device_stats (ieee->stats) on
1888 * re-association */
1889
1890 priv->last_seq_num = -1;
1891 priv->last_frag_num = -1;
1892 priv->last_packet_time = 0;
1893
bb8c093b 1894 iwl4965_scan_cancel(priv);
b481de9c
ZY		 1895}
1896
1897#define MAX_UCODE_BEACON_INTERVAL 4096
1898#define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
1899
bb8c093b 1900static __le16 iwl4965_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 1901{
1902 u16 new_val = 0;
1903 u16 beacon_factor = 0;
1904
1905 beacon_factor =
1906 (beacon_val + MAX_UCODE_BEACON_INTERVAL)
1907 / MAX_UCODE_BEACON_INTERVAL;
1908 new_val = beacon_val / beacon_factor;
1909
1910 return cpu_to_le16(new_val);
1911}
1912
c79dd5b5 1913static void iwl4965_setup_rxon_timing(struct iwl_priv *priv)
b481de9c
ZY		 1914{
1915 u64 interval_tm_unit;
1916 u64 tsf, result;
1917 unsigned long flags;
1918 struct ieee80211_conf *conf = NULL;
1919 u16 beacon_int = 0;
1920
1921 conf = ieee80211_get_hw_conf(priv->hw);
1922
1923 spin_lock_irqsave(&priv->lock, flags);
3109ece1
TW		 1924 priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp >> 32);
1925 priv->rxon_timing.timestamp.dw[0] =
1926 cpu_to_le32(priv->timestamp & 0xFFFFFFFF);
b481de9c
ZY		 1927
1928 priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
1929
3109ece1 1930 tsf = priv->timestamp;
b481de9c
ZY		 1931
1932 beacon_int = priv->beacon_int;
1933 spin_unlock_irqrestore(&priv->lock, flags);
1934
1935 if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
1936 if (beacon_int == 0) {
1937 priv->rxon_timing.beacon_interval = cpu_to_le16(100);
1938 priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
1939 } else {
1940 priv->rxon_timing.beacon_interval =
1941 cpu_to_le16(beacon_int);
1942 priv->rxon_timing.beacon_interval =
bb8c093b 1943 iwl4965_adjust_beacon_interval(
b481de9c
ZY		 1944 le16_to_cpu(priv->rxon_timing.beacon_interval));
1945 }
1946
1947 priv->rxon_timing.atim_window = 0;
1948 } else {
1949 priv->rxon_timing.beacon_interval =
bb8c093b 1950 iwl4965_adjust_beacon_interval(conf->beacon_int);
b481de9c
ZY		 1951 /* TODO: we need to get atim_window from upper stack
1952 * for now we set to 0 */
1953 priv->rxon_timing.atim_window = 0;
1954 }
1955
1956 interval_tm_unit =
1957 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
1958 result = do_div(tsf, interval_tm_unit);
1959 priv->rxon_timing.beacon_init_val =
1960 cpu_to_le32((u32) ((u64) interval_tm_unit - result));
1961
1962 IWL_DEBUG_ASSOC
1963 ("beacon interval %d beacon timer %d beacon tim %d\n",
1964 le16_to_cpu(priv->rxon_timing.beacon_interval),
1965 le32_to_cpu(priv->rxon_timing.beacon_init_val),
1966 le16_to_cpu(priv->rxon_timing.atim_window));
1967}
1968
c79dd5b5 1969static int iwl4965_scan_initiate(struct iwl_priv *priv)
b481de9c
ZY		 1970{
1971 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
1972 IWL_ERROR("APs don't scan.\n");
1973 return 0;
1974 }
1975
bb8c093b 1976 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY		 1977 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
1978 return -EIO;
1979 }
1980
1981 if (test_bit(STATUS_SCANNING, &priv->status)) {
1982 IWL_DEBUG_SCAN("Scan already in progress.\n");
1983 return -EAGAIN;
1984 }
1985
1986 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1987 IWL_DEBUG_SCAN("Scan request while abort pending. "
1988 "Queuing.\n");
1989 return -EAGAIN;
1990 }
1991
1992 IWL_DEBUG_INFO("Starting scan...\n");
1993 priv->scan_bands = 2;
1994 set_bit(STATUS_SCANNING, &priv->status);
1995 priv->scan_start = jiffies;
1996 priv->scan_pass_start = priv->scan_start;
1997
1998 queue_work(priv->workqueue, &priv->request_scan);
1999
2000 return 0;
2001}
2002
b481de9c 2003
c79dd5b5 2004static void iwl4965_set_flags_for_phymode(struct iwl_priv *priv,
8318d78a 2005 enum ieee80211_band band)
b481de9c 2006{
8318d78a 2007 if (band == IEEE80211_BAND_5GHZ) {
b481de9c
ZY		 2008 priv->staging_rxon.flags &=
2009 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2010 | RXON_FLG_CCK_MSK);
2011 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2012 } else {
bb8c093b 2013 /* Copied from iwl4965_bg_post_associate() */
b481de9c
ZY		 2014 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2015 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2016 else
2017 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2018
2019 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
2020 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2021
2022 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2023 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2024 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2025 }
2026}
2027
2028/*
01ebd063 2029 * initialize rxon structure with default values from eeprom
b481de9c 2030 */
c79dd5b5 2031static void iwl4965_connection_init_rx_config(struct iwl_priv *priv)
b481de9c 2032{
bf85ea4f 2033 const struct iwl_channel_info *ch_info;
b481de9c
ZY		 2034
2035 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2036
2037 switch (priv->iw_mode) {
2038 case IEEE80211_IF_TYPE_AP:
2039 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2040 break;
2041
2042 case IEEE80211_IF_TYPE_STA:
2043 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2044 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2045 break;
2046
2047 case IEEE80211_IF_TYPE_IBSS:
2048 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2049 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2050 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2051 RXON_FILTER_ACCEPT_GRP_MSK;
2052 break;
2053
2054 case IEEE80211_IF_TYPE_MNTR:
2055 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2056 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2057 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2058 break;
69dc5d9d
TW		 2059 default:
2060 IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
2061 break;
b481de9c
ZY		 2062 }
2063
2064#if 0
2065 /* TODO: Figure out when short_preamble would be set and cache from
2066 * that */
2067 if (!hw_to_local(priv->hw)->short_preamble)
2068 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2069 else
2070 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2071#endif
2072
8622e705 2073 ch_info = iwl_get_channel_info(priv, priv->band,
b481de9c
ZY		 2074 le16_to_cpu(priv->staging_rxon.channel));
2075
2076 if (!ch_info)
2077 ch_info = &priv->channel_info[0];
2078
2079 /*
2080 * in some case A channels are all non IBSS
2081 * in this case force B/G channel
2082 */
2083 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
2084 !(is_channel_ibss(ch_info)))
2085 ch_info = &priv->channel_info[0];
2086
2087 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
8318d78a 2088 priv->band = ch_info->band;
b481de9c 2089
8318d78a 2090 iwl4965_set_flags_for_phymode(priv, priv->band);
b481de9c
ZY		 2091
2092 priv->staging_rxon.ofdm_basic_rates =
2093 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2094 priv->staging_rxon.cck_basic_rates =
2095 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2096
2097 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
2098 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
2099 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2100 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
2101 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
2102 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
2103 iwl4965_set_rxon_chain(priv);
2104}
2105
c79dd5b5 2106static int iwl4965_set_mode(struct iwl_priv *priv, int mode)
b481de9c 2107{
b481de9c 2108 if (mode == IEEE80211_IF_TYPE_IBSS) {
bf85ea4f 2109 const struct iwl_channel_info *ch_info;
b481de9c 2110
8622e705 2111 ch_info = iwl_get_channel_info(priv,
8318d78a 2112 priv->band,
b481de9c
ZY		 2113 le16_to_cpu(priv->staging_rxon.channel));
2114
2115 if (!ch_info || !is_channel_ibss(ch_info)) {
2116 IWL_ERROR("channel %d not IBSS channel\n",
2117 le16_to_cpu(priv->staging_rxon.channel));
2118 return -EINVAL;
2119 }
2120 }
2121
b481de9c
ZY		 2122 priv->iw_mode = mode;
2123
bb8c093b 2124 iwl4965_connection_init_rx_config(priv);
b481de9c
ZY		 2125 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2126
bf85ea4f 2127 iwlcore_clear_stations_table(priv);
b481de9c 2128
fde3571f
MA		 2129 /* dont commit rxon if rf-kill is on*/
2130 if (!iwl4965_is_ready_rf(priv))
2131 return -EAGAIN;
2132
2133 cancel_delayed_work(&priv->scan_check);
2134 if (iwl4965_scan_cancel_timeout(priv, 100)) {
2135 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2136 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2137 return -EAGAIN;
2138 }
2139
bb8c093b 2140 iwl4965_commit_rxon(priv);
b481de9c
ZY		 2141
2142 return 0;
2143}
2144
c79dd5b5 2145static void iwl4965_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
b481de9c 2146 struct ieee80211_tx_control *ctl,
857485c0 2147 struct iwl_cmd *cmd,
b481de9c 2148 struct sk_buff *skb_frag,
deb09c43 2149 int sta_id)
b481de9c 2150{
deb09c43 2151 struct iwl4965_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
b481de9c
ZY		 2152
2153 switch (keyinfo->alg) {
2154 case ALG_CCMP:
2155 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2156 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
8236e183
MS		 2157 if (ctl->flags & IEEE80211_TXCTL_AMPDU)
2158 cmd->cmd.tx.tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
b481de9c
ZY		 2159 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
2160 break;
2161
2162 case ALG_TKIP:
b481de9c 2163 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2bc75089
EG		 2164 ieee80211_get_tkip_key(keyinfo->conf, skb_frag,
2165 IEEE80211_TKIP_P2_KEY, cmd->cmd.tx.key);
2166 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
b481de9c
ZY		 2167 break;
2168
2169 case ALG_WEP:
2170 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
2171 (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
2172
2173 if (keyinfo->keylen == 13)
2174 cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2175
2176 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2177
2178 IWL_DEBUG_TX("Configuring packet for WEP encryption "
2179 "with key %d\n", ctl->key_idx);
2180 break;
2181
b481de9c
ZY		 2182 default:
2183 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2184 break;
2185 }
2186}
2187
2188/*
2189 * handle build REPLY_TX command notification.
2190 */
c79dd5b5 2191static void iwl4965_build_tx_cmd_basic(struct iwl_priv *priv,
857485c0 2192 struct iwl_cmd *cmd,
b481de9c
ZY		 2193 struct ieee80211_tx_control *ctrl,
2194 struct ieee80211_hdr *hdr,
2195 int is_unicast, u8 std_id)
2196{
2197 __le16 *qc;
2198 u16 fc = le16_to_cpu(hdr->frame_control);
2199 __le32 tx_flags = cmd->cmd.tx.tx_flags;
2200
2201 cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2202 if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
2203 tx_flags |= TX_CMD_FLG_ACK_MSK;
2204 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
2205 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2206 if (ieee80211_is_probe_response(fc) &&
2207 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2208 tx_flags |= TX_CMD_FLG_TSF_MSK;
2209 } else {
2210 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2211 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2212 }
2213
87e4f7df
TW		 2214 if (ieee80211_is_back_request(fc))
2215 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
2216
2217
b481de9c
ZY		 2218 cmd->cmd.tx.sta_id = std_id;
2219 if (ieee80211_get_morefrag(hdr))
2220 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2221
2222 qc = ieee80211_get_qos_ctrl(hdr);
2223 if (qc) {
2224 cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
2225 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
2226 } else
2227 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2228
2229 if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
2230 tx_flags |= TX_CMD_FLG_RTS_MSK;
2231 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
2232 } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
2233 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2234 tx_flags |= TX_CMD_FLG_CTS_MSK;
2235 }
2236
2237 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2238 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2239
2240 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
2241 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
2242 if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
2243 (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
bc434dd2 2244 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 2245 else
bc434dd2 2246 cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 2247 } else {
b481de9c 2248 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
ab53d8af 2249 }
b481de9c
ZY		 2250
2251 cmd->cmd.tx.driver_txop = 0;
2252 cmd->cmd.tx.tx_flags = tx_flags;
2253 cmd->cmd.tx.next_frame_len = 0;
2254}
19758bef
TW		 2255static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2256{
2257 /* 0 - mgmt, 1 - cnt, 2 - data */
2258 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2259 priv->tx_stats[idx].cnt++;
2260 priv->tx_stats[idx].bytes += len;
2261}
6440adb5
CB		 2262/**
2263 * iwl4965_get_sta_id - Find station's index within station table
2264 *
2265 * If new IBSS station, create new entry in station table
2266 */
c79dd5b5 2267static int iwl4965_get_sta_id(struct iwl_priv *priv,
9fbab516 2268 struct ieee80211_hdr *hdr)
b481de9c
ZY		 2269{
2270 int sta_id;
2271 u16 fc = le16_to_cpu(hdr->frame_control);
0795af57 2272 DECLARE_MAC_BUF(mac);
b481de9c 2273
6440adb5 2274 /* If this frame is broadcast or management, use broadcast station id */
b481de9c
ZY		 2275 if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2276 is_multicast_ether_addr(hdr->addr1))
2277 return priv->hw_setting.bcast_sta_id;
2278
2279 switch (priv->iw_mode) {
2280
6440adb5
CB		 2281 /* If we are a client station in a BSS network, use the special
2282 * AP station entry (that's the only station we communicate with) */
b481de9c
ZY		 2283 case IEEE80211_IF_TYPE_STA:
2284 return IWL_AP_ID;
2285
2286 /* If we are an AP, then find the station, or use BCAST */
2287 case IEEE80211_IF_TYPE_AP:
bb8c093b 2288 sta_id = iwl4965_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2289 if (sta_id != IWL_INVALID_STATION)
2290 return sta_id;
2291 return priv->hw_setting.bcast_sta_id;
2292
6440adb5
CB		 2293 /* If this frame is going out to an IBSS network, find the station,
2294 * or create a new station table entry */
b481de9c 2295 case IEEE80211_IF_TYPE_IBSS:
bb8c093b 2296 sta_id = iwl4965_hw_find_station(priv, hdr->addr1);
b481de9c
ZY		 2297 if (sta_id != IWL_INVALID_STATION)
2298 return sta_id;
2299
6440adb5 2300 /* Create new station table entry */
67d62035
RR		 2301 sta_id = iwl4965_add_station_flags(priv, hdr->addr1,
2302 0, CMD_ASYNC, NULL);
b481de9c
ZY		 2303
2304 if (sta_id != IWL_INVALID_STATION)
2305 return sta_id;
2306
0795af57 2307 IWL_DEBUG_DROP("Station %s not in station map. "
b481de9c 2308 "Defaulting to broadcast...\n",
0795af57 2309 print_mac(mac, hdr->addr1));
0a6857e7 2310 iwl_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
b481de9c
ZY		 2311 return priv->hw_setting.bcast_sta_id;
2312
2313 default:
01ebd063 2314 IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
b481de9c
ZY		 2315 return priv->hw_setting.bcast_sta_id;
2316 }
2317}
2318
2319/*
2320 * start REPLY_TX command process
2321 */
c79dd5b5 2322static int iwl4965_tx_skb(struct iwl_priv *priv,
b481de9c
ZY		 2323 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2324{
2325 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
bb8c093b 2326 struct iwl4965_tfd_frame *tfd;
b481de9c
ZY		 2327 u32 *control_flags;
2328 int txq_id = ctl->queue;
bb8c093b
CH		 2329 struct iwl4965_tx_queue *txq = NULL;
2330 struct iwl4965_queue *q = NULL;
b481de9c
ZY		 2331 dma_addr_t phys_addr;
2332 dma_addr_t txcmd_phys;
87e4f7df 2333 dma_addr_t scratch_phys;
857485c0 2334 struct iwl_cmd *out_cmd = NULL;
b481de9c
ZY		 2335 u16 len, idx, len_org;
2336 u8 id, hdr_len, unicast;
2337 u8 sta_id;
2338 u16 seq_number = 0;
2339 u16 fc;
2340 __le16 *qc;
2341 u8 wait_write_ptr = 0;
2342 unsigned long flags;
2343 int rc;
2344
2345 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2346 if (iwl4965_is_rfkill(priv)) {
b481de9c
ZY		 2347 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2348 goto drop_unlock;
2349 }
2350
32bfd35d
JB		 2351 if (!priv->vif) {
2352 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
b481de9c
ZY		 2353 goto drop_unlock;
2354 }
2355
8318d78a 2356 if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) {
b481de9c
ZY		 2357 IWL_ERROR("ERROR: No TX rate available.\n");
2358 goto drop_unlock;
2359 }
2360
2361 unicast = !is_multicast_ether_addr(hdr->addr1);
2362 id = 0;
2363
2364 fc = le16_to_cpu(hdr->frame_control);
2365
0a6857e7 2366#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 2367 if (ieee80211_is_auth(fc))
2368 IWL_DEBUG_TX("Sending AUTH frame\n");
2369 else if (ieee80211_is_assoc_request(fc))
2370 IWL_DEBUG_TX("Sending ASSOC frame\n");
2371 else if (ieee80211_is_reassoc_request(fc))
2372 IWL_DEBUG_TX("Sending REASSOC frame\n");
2373#endif
2374
7878a5a4 2375 /* drop all data frame if we are not associated */
76f3915b 2376 if (((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) &&
3109ece1 2377 (!iwl_is_associated(priv) ||
a6477249 2378 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id) ||
76f3915b 2379 !priv->assoc_station_added)) {
3109ece1 2380 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
b481de9c
ZY		 2381 goto drop_unlock;
2382 }
2383
2384 spin_unlock_irqrestore(&priv->lock, flags);
2385
2386 hdr_len = ieee80211_get_hdrlen(fc);
6440adb5
CB		 2387
2388 /* Find (or create) index into station table for destination station */
bb8c093b 2389 sta_id = iwl4965_get_sta_id(priv, hdr);
b481de9c 2390 if (sta_id == IWL_INVALID_STATION) {
0795af57
JP		 2391 DECLARE_MAC_BUF(mac);
2392
2393 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
2394 print_mac(mac, hdr->addr1));
b481de9c
ZY		 2395 goto drop;
2396 }
2397
2398 IWL_DEBUG_RATE("station Id %d\n", sta_id);
2399
2400 qc = ieee80211_get_qos_ctrl(hdr);
2401 if (qc) {
2402 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2403 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2404 IEEE80211_SCTL_SEQ;
2405 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2406 (hdr->seq_ctrl &
2407 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2408 seq_number += 0x10;
c8b0e6e1 2409#ifdef CONFIG_IWL4965_HT
b481de9c 2410 /* aggregation is on for this <sta,tid> */
fe01b477 2411 if (ctl->flags & IEEE80211_TXCTL_AMPDU)
b481de9c 2412 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
fe01b477 2413 priv->stations[sta_id].tid[tid].tfds_in_queue++;
c8b0e6e1 2414#endif /* CONFIG_IWL4965_HT */
b481de9c 2415 }
6440adb5
CB		 2416
2417 /* Descriptor for chosen Tx queue */
b481de9c
ZY		 2418 txq = &priv->txq[txq_id];
2419 q = &txq->q;
2420
2421 spin_lock_irqsave(&priv->lock, flags);
2422
6440adb5 2423 /* Set up first empty TFD within this queue's circular TFD buffer */
fc4b6853 2424 tfd = &txq->bd[q->write_ptr];
b481de9c
ZY		 2425 memset(tfd, 0, sizeof(*tfd));
2426 control_flags = (u32 *) tfd;
fc4b6853 2427 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 2428
6440adb5 2429 /* Set up driver data for this TFD */
bb8c093b 2430 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl4965_tx_info));
fc4b6853
TW		 2431 txq->txb[q->write_ptr].skb[0] = skb;
2432 memcpy(&(txq->txb[q->write_ptr].status.control),
b481de9c 2433 ctl, sizeof(struct ieee80211_tx_control));
6440adb5
CB		 2434
2435 /* Set up first empty entry in queue's array of Tx/cmd buffers */
b481de9c
ZY		 2436 out_cmd = &txq->cmd[idx];
2437 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2438 memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
6440adb5
CB		 2439
2440 /*
2441 * Set up the Tx-command (not MAC!) header.
2442 * Store the chosen Tx queue and TFD index within the sequence field;
2443 * after Tx, uCode's Tx response will return this value so driver can
2444 * locate the frame within the tx queue and do post-tx processing.
2445 */
b481de9c
ZY		 2446 out_cmd->hdr.cmd = REPLY_TX;
2447 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 2448 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB		 2449
2450 /* Copy MAC header from skb into command buffer */
b481de9c
ZY		 2451 memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2452
6440adb5
CB		 2453 /*
2454 * Use the first empty entry in this queue's command buffer array
2455 * to contain the Tx command and MAC header concatenated together
2456 * (payload data will be in another buffer).
2457 * Size of this varies, due to varying MAC header length.
2458 * If end is not dword aligned, we'll have 2 extra bytes at the end
2459 * of the MAC header (device reads on dword boundaries).
2460 * We'll tell device about this padding later.
2461 */
b481de9c 2462 len = priv->hw_setting.tx_cmd_len +
857485c0 2463 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY		 2464
2465 len_org = len;
2466 len = (len + 3) & ~3;
2467
2468 if (len_org != len)
2469 len_org = 1;
2470 else
2471 len_org = 0;
2472
6440adb5
CB		 2473 /* Physical address of this Tx command's header (not MAC header!),
2474 * within command buffer array. */
857485c0
TW		 2475 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl_cmd) * idx +
2476 offsetof(struct iwl_cmd, hdr);
b481de9c 2477
6440adb5
CB		 2478 /* Add buffer containing Tx command and MAC(!) header to TFD's
2479 * first entry */
bb8c093b 2480 iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
b481de9c
ZY		 2481
2482 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
deb09c43 2483 iwl4965_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, sta_id);
b481de9c 2484
6440adb5
CB		 2485 /* Set up TFD's 2nd entry to point directly to remainder of skb,
2486 * if any (802.11 null frames have no payload). */
b481de9c
ZY		 2487 len = skb->len - hdr_len;
2488 if (len) {
2489 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2490 len, PCI_DMA_TODEVICE);
bb8c093b 2491 iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
b481de9c
ZY		 2492 }
2493
6440adb5 2494 /* Tell 4965 about any 2-byte padding after MAC header */
b481de9c
ZY		 2495 if (len_org)
2496 out_cmd->cmd.tx.tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
2497
6440adb5 2498 /* Total # bytes to be transmitted */
b481de9c
ZY		 2499 len = (u16)skb->len;
2500 out_cmd->cmd.tx.len = cpu_to_le16(len);
2501
2502 /* TODO need this for burst mode later on */
bb8c093b 2503 iwl4965_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
b481de9c
ZY		 2504
2505 /* set is_hcca to 0; it probably will never be implemented */
bb8c093b 2506 iwl4965_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
b481de9c 2507
19758bef
TW		 2508 iwl_update_tx_stats(priv, fc, len);
2509
857485c0 2510 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
87e4f7df
TW		 2511 offsetof(struct iwl4965_tx_cmd, scratch);
2512 out_cmd->cmd.tx.dram_lsb_ptr = cpu_to_le32(scratch_phys);
2513 out_cmd->cmd.tx.dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys);
2514
b481de9c
ZY		 2515 if (!ieee80211_get_morefrag(hdr)) {
2516 txq->need_update = 1;
2517 if (qc) {
2518 u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
2519 priv->stations[sta_id].tid[tid].seq_number = seq_number;
2520 }
2521 } else {
2522 wait_write_ptr = 1;
2523 txq->need_update = 0;
2524 }
2525
0a6857e7 2526 iwl_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
b481de9c
ZY		 2527 sizeof(out_cmd->cmd.tx));
2528
0a6857e7 2529 iwl_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
b481de9c
ZY		 2530 ieee80211_get_hdrlen(fc));
2531
6440adb5 2532 /* Set up entry for this TFD in Tx byte-count array */
b481de9c
ZY		 2533 iwl4965_tx_queue_update_wr_ptr(priv, txq, len);
2534
6440adb5 2535 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 2536 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
bb8c093b 2537 rc = iwl4965_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2538 spin_unlock_irqrestore(&priv->lock, flags);
2539
2540 if (rc)
2541 return rc;
2542
bb8c093b 2543 if ((iwl4965_queue_space(q) < q->high_mark)
b481de9c
ZY		 2544 && priv->mac80211_registered) {
2545 if (wait_write_ptr) {
2546 spin_lock_irqsave(&priv->lock, flags);
2547 txq->need_update = 1;
bb8c093b 2548 iwl4965_tx_queue_update_write_ptr(priv, txq);
b481de9c
ZY		 2549 spin_unlock_irqrestore(&priv->lock, flags);
2550 }
2551
2552 ieee80211_stop_queue(priv->hw, ctl->queue);
2553 }
2554
2555 return 0;
2556
2557drop_unlock:
2558 spin_unlock_irqrestore(&priv->lock, flags);
2559drop:
2560 return -1;
2561}
2562
c79dd5b5 2563static void iwl4965_set_rate(struct iwl_priv *priv)
b481de9c 2564{
8318d78a 2565 const struct ieee80211_supported_band *hw = NULL;
b481de9c
ZY		 2566 struct ieee80211_rate *rate;
2567 int i;
2568
8318d78a 2569 hw = iwl4965_get_hw_mode(priv, priv->band);
c4ba9621
SA		 2570 if (!hw) {
2571 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2572 return;
2573 }
b481de9c
ZY		 2574
2575 priv->active_rate = 0;
2576 priv->active_rate_basic = 0;
2577
8318d78a
JB		 2578 for (i = 0; i < hw->n_bitrates; i++) {
2579 rate = &(hw->bitrates[i]);
2580 if (rate->hw_value < IWL_RATE_COUNT)
2581 priv->active_rate |= (1 << rate->hw_value);
b481de9c
ZY		 2582 }
2583
2584 IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2585 priv->active_rate, priv->active_rate_basic);
2586
2587 /*
2588 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2589 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2590 * OFDM
2591 */
2592 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2593 priv->staging_rxon.cck_basic_rates =
2594 ((priv->active_rate_basic &
2595 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2596 else
2597 priv->staging_rxon.cck_basic_rates =
2598 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2599
2600 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2601 priv->staging_rxon.ofdm_basic_rates =
2602 ((priv->active_rate_basic &
2603 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2604 IWL_FIRST_OFDM_RATE) & 0xFF;
2605 else
2606 priv->staging_rxon.ofdm_basic_rates =
2607 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2608}
2609
ad97edd2 2610void iwl4965_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
b481de9c
ZY		 2611{
2612 unsigned long flags;
2613
2614 if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2615 return;
2616
2617 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2618 disable_radio ? "OFF" : "ON");
2619
2620 if (disable_radio) {
bb8c093b 2621 iwl4965_scan_cancel(priv);
b481de9c
ZY		 2622 /* FIXME: This is a workaround for AP */
2623 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
2624 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 2625 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 2626 CSR_UCODE_SW_BIT_RFKILL);
2627 spin_unlock_irqrestore(&priv->lock, flags);
ad97edd2
MA		 2628 /* call the host command only if no hw rf-kill set */
2629 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
2630 iwl4965_send_card_state(priv,
2631 CARD_STATE_CMD_DISABLE,
2632 0);
b481de9c 2633 set_bit(STATUS_RF_KILL_SW, &priv->status);
ad97edd2
MA		 2634
2635 /* make sure mac80211 stop sending Tx frame */
2636 if (priv->mac80211_registered)
2637 ieee80211_stop_queues(priv->hw);
b481de9c
ZY		 2638 }
2639 return;
2640 }
2641
2642 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 2643 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2644
2645 clear_bit(STATUS_RF_KILL_SW, &priv->status);
2646 spin_unlock_irqrestore(&priv->lock, flags);
2647
2648 /* wake up ucode */
2649 msleep(10);
2650
2651 spin_lock_irqsave(&priv->lock, flags);
3395f6e9
TW		 2652 iwl_read32(priv, CSR_UCODE_DRV_GP1);
2653 if (!iwl_grab_nic_access(priv))
2654 iwl_release_nic_access(priv);
b481de9c
ZY		 2655 spin_unlock_irqrestore(&priv->lock, flags);
2656
2657 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2658 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2659 "disabled by HW switch\n");
2660 return;
2661 }
2662
2663 queue_work(priv->workqueue, &priv->restart);
2664 return;
2665}
2666
c79dd5b5 2667void iwl4965_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
b481de9c
ZY		 2668 u32 decrypt_res, struct ieee80211_rx_status *stats)
2669{
2670 u16 fc =
2671 le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2672
2673 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2674 return;
2675
2676 if (!(fc & IEEE80211_FCTL_PROTECTED))
2677 return;
2678
2679 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2680 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2681 case RX_RES_STATUS_SEC_TYPE_TKIP:
17e476b8
EG		 2682 /* The uCode has got a bad phase 1 Key, pushes the packet.
2683 * Decryption will be done in SW. */
2684 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2685 RX_RES_STATUS_BAD_KEY_TTAK)
2686 break;
2687
b481de9c
ZY		 2688 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2689 RX_RES_STATUS_BAD_ICV_MIC)
2690 stats->flag |= RX_FLAG_MMIC_ERROR;
2691 case RX_RES_STATUS_SEC_TYPE_WEP:
2692 case RX_RES_STATUS_SEC_TYPE_CCMP:
2693 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2694 RX_RES_STATUS_DECRYPT_OK) {
2695 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2696 stats->flag |= RX_FLAG_DECRYPTED;
2697 }
2698 break;
2699
2700 default:
2701 break;
2702 }
2703}
2704
b481de9c
ZY		 2705
2706#define IWL_PACKET_RETRY_TIME HZ
2707
c79dd5b5 2708int iwl4965_is_duplicate_packet(struct iwl_priv *priv, struct ieee80211_hdr *header)
b481de9c
ZY		 2709{
2710 u16 sc = le16_to_cpu(header->seq_ctrl);
2711 u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
2712 u16 frag = sc & IEEE80211_SCTL_FRAG;
2713 u16 *last_seq, *last_frag;
2714 unsigned long *last_time;
2715
2716 switch (priv->iw_mode) {
2717 case IEEE80211_IF_TYPE_IBSS:{
2718 struct list_head *p;
bb8c093b 2719 struct iwl4965_ibss_seq *entry = NULL;
b481de9c
ZY		 2720 u8 *mac = header->addr2;
2721 int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
2722
2723 __list_for_each(p, &priv->ibss_mac_hash[index]) {
bb8c093b 2724 entry = list_entry(p, struct iwl4965_ibss_seq, list);
b481de9c
ZY		 2725 if (!compare_ether_addr(entry->mac, mac))
2726 break;
2727 }
2728 if (p == &priv->ibss_mac_hash[index]) {
2729 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
2730 if (!entry) {
bc434dd2 2731 IWL_ERROR("Cannot malloc new mac entry\n");
b481de9c
ZY		 2732 return 0;
2733 }
2734 memcpy(entry->mac, mac, ETH_ALEN);
2735 entry->seq_num = seq;
2736 entry->frag_num = frag;
2737 entry->packet_time = jiffies;
bc434dd2 2738 list_add(&entry->list, &priv->ibss_mac_hash[index]);
b481de9c
ZY		 2739 return 0;
2740 }
2741 last_seq = &entry->seq_num;
2742 last_frag = &entry->frag_num;
2743 last_time = &entry->packet_time;
2744 break;
2745 }
2746 case IEEE80211_IF_TYPE_STA:
2747 last_seq = &priv->last_seq_num;
2748 last_frag = &priv->last_frag_num;
2749 last_time = &priv->last_packet_time;
2750 break;
2751 default:
2752 return 0;
2753 }
2754 if ((*last_seq == seq) &&
2755 time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
2756 if (*last_frag == frag)
2757 goto drop;
2758 if (*last_frag + 1 != frag)
2759 /* out-of-order fragment */
2760 goto drop;
2761 } else
2762 *last_seq = seq;
2763
2764 *last_frag = frag;
2765 *last_time = jiffies;
2766 return 0;
2767
2768 drop:
2769 return 1;
2770}
2771
c8b0e6e1 2772#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
b481de9c
ZY		 2773
2774#include "iwl-spectrum.h"
2775
2776#define BEACON_TIME_MASK_LOW 0x00FFFFFF
2777#define BEACON_TIME_MASK_HIGH 0xFF000000
2778#define TIME_UNIT 1024
2779
2780/*
2781 * extended beacon time format
2782 * time in usec will be changed into a 32-bit value in 8:24 format
2783 * the high 1 byte is the beacon counts
2784 * the lower 3 bytes is the time in usec within one beacon interval
2785 */
2786
bb8c093b 2787static u32 iwl4965_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY		 2788{
2789 u32 quot;
2790 u32 rem;
2791 u32 interval = beacon_interval * 1024;
2792
2793 if (!interval || !usec)
2794 return 0;
2795
2796 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
2797 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
2798
2799 return (quot << 24) + rem;
2800}
2801
2802/* base is usually what we get from ucode with each received frame,
2803 * the same as HW timer counter counting down
2804 */
2805
bb8c093b 2806static __le32 iwl4965_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY		 2807{
2808 u32 base_low = base & BEACON_TIME_MASK_LOW;
2809 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
2810 u32 interval = beacon_interval * TIME_UNIT;
2811 u32 res = (base & BEACON_TIME_MASK_HIGH) +
2812 (addon & BEACON_TIME_MASK_HIGH);
2813
2814 if (base_low > addon_low)
2815 res += base_low - addon_low;
2816 else if (base_low < addon_low) {
2817 res += interval + base_low - addon_low;
2818 res += (1 << 24);
2819 } else
2820 res += (1 << 24);
2821
2822 return cpu_to_le32(res);
2823}
2824
c79dd5b5 2825static int iwl4965_get_measurement(struct iwl_priv *priv,
b481de9c
ZY		 2826 struct ieee80211_measurement_params *params,
2827 u8 type)
2828{
bb8c093b
CH		 2829 struct iwl4965_spectrum_cmd spectrum;
2830 struct iwl4965_rx_packet *res;
857485c0 2831 struct iwl_host_cmd cmd = {
b481de9c
ZY		 2832 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
2833 .data = (void *)&spectrum,
2834 .meta.flags = CMD_WANT_SKB,
2835 };
2836 u32 add_time = le64_to_cpu(params->start_time);
2837 int rc;
2838 int spectrum_resp_status;
2839 int duration = le16_to_cpu(params->duration);
2840
3109ece1 2841 if (iwl_is_associated(priv))
b481de9c 2842 add_time =
bb8c093b 2843 iwl4965_usecs_to_beacons(
b481de9c
ZY		 2844 le64_to_cpu(params->start_time) - priv->last_tsf,
2845 le16_to_cpu(priv->rxon_timing.beacon_interval));
2846
2847 memset(&spectrum, 0, sizeof(spectrum));
2848
2849 spectrum.channel_count = cpu_to_le16(1);
2850 spectrum.flags =
2851 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
2852 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
2853 cmd.len = sizeof(spectrum);
2854 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
2855
3109ece1 2856 if (iwl_is_associated(priv))
b481de9c 2857 spectrum.start_time =
bb8c093b 2858 iwl4965_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY		 2859 add_time,
2860 le16_to_cpu(priv->rxon_timing.beacon_interval));
2861 else
2862 spectrum.start_time = 0;
2863
2864 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
2865 spectrum.channels[0].channel = params->channel;
2866 spectrum.channels[0].type = type;
2867 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
2868 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
2869 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
2870
857485c0 2871 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY		 2872 if (rc)
2873 return rc;
2874
bb8c093b 2875 res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
b481de9c
ZY		 2876 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
2877 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
2878 rc = -EIO;
2879 }
2880
2881 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
2882 switch (spectrum_resp_status) {
2883 case 0: /* Command will be handled */
2884 if (res->u.spectrum.id != 0xff) {
2885 IWL_DEBUG_INFO
2886 ("Replaced existing measurement: %d\n",
2887 res->u.spectrum.id);
2888 priv->measurement_status &= ~MEASUREMENT_READY;
2889 }
2890 priv->measurement_status |= MEASUREMENT_ACTIVE;
2891 rc = 0;
2892 break;
2893
2894 case 1: /* Command will not be handled */
2895 rc = -EAGAIN;
2896 break;
2897 }
2898
2899 dev_kfree_skb_any(cmd.meta.u.skb);
2900
2901 return rc;
2902}
2903#endif
2904
c79dd5b5 2905static void iwl4965_txstatus_to_ieee(struct iwl_priv *priv,
bb8c093b 2906 struct iwl4965_tx_info *tx_sta)
b481de9c
ZY		 2907{
2908
2909 tx_sta->status.ack_signal = 0;
2910 tx_sta->status.excessive_retries = 0;
2911 tx_sta->status.queue_length = 0;
2912 tx_sta->status.queue_number = 0;
2913
2914 if (in_interrupt())
2915 ieee80211_tx_status_irqsafe(priv->hw,
2916 tx_sta->skb[0], &(tx_sta->status));
2917 else
2918 ieee80211_tx_status(priv->hw,
2919 tx_sta->skb[0], &(tx_sta->status));
2920
2921 tx_sta->skb[0] = NULL;
2922}
2923
2924/**
6440adb5 2925 * iwl4965_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
b481de9c 2926 *
6440adb5
CB		 2927 * When FW advances 'R' index, all entries between old and new 'R' index
2928 * need to be reclaimed. As result, some free space forms. If there is
2929 * enough free space (> low mark), wake the stack that feeds us.
b481de9c 2930 */
c79dd5b5 2931int iwl4965_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
b481de9c 2932{
bb8c093b
CH		 2933 struct iwl4965_tx_queue *txq = &priv->txq[txq_id];
2934 struct iwl4965_queue *q = &txq->q;
b481de9c
ZY		 2935 int nfreed = 0;
2936
2937 if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
2938 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
2939 "is out of range [0-%d] %d %d.\n", txq_id,
fc4b6853 2940 index, q->n_bd, q->write_ptr, q->read_ptr);
b481de9c
ZY		 2941 return 0;
2942 }
2943
c54b679d 2944 for (index = iwl_queue_inc_wrap(index, q->n_bd);
fc4b6853 2945 q->read_ptr != index;
c54b679d 2946 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
b481de9c 2947 if (txq_id != IWL_CMD_QUEUE_NUM) {
bb8c093b 2948 iwl4965_txstatus_to_ieee(priv,
fc4b6853 2949 &(txq->txb[txq->q.read_ptr]));
bb8c093b 2950 iwl4965_hw_txq_free_tfd(priv, txq);
b481de9c
ZY		 2951 } else if (nfreed > 1) {
2952 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
fc4b6853 2953 q->write_ptr, q->read_ptr);
b481de9c
ZY		 2954 queue_work(priv->workqueue, &priv->restart);
2955 }
2956 nfreed++;
2957 }
2958
fe01b477 2959/* if (iwl4965_queue_space(q) > q->low_mark && (txq_id >= 0) &&
b481de9c
ZY		 2960 (txq_id != IWL_CMD_QUEUE_NUM) &&
2961 priv->mac80211_registered)
fe01b477 2962 ieee80211_wake_queue(priv->hw, txq_id); */
b481de9c
ZY		 2963
2964
2965 return nfreed;
2966}
2967
bb8c093b 2968static int iwl4965_is_tx_success(u32 status)
b481de9c
ZY		 2969{
2970 status &= TX_STATUS_MSK;
2971 return (status == TX_STATUS_SUCCESS)
2972 || (status == TX_STATUS_DIRECT_DONE);
2973}
2974
2975/******************************************************************************
2976 *
2977 * Generic RX handler implementations
2978 *
2979 ******************************************************************************/
c8b0e6e1 2980#ifdef CONFIG_IWL4965_HT
b481de9c 2981
c79dd5b5 2982static inline int iwl4965_get_ra_sta_id(struct iwl_priv *priv,
b481de9c
ZY		 2983 struct ieee80211_hdr *hdr)
2984{
2985 if (priv->iw_mode == IEEE80211_IF_TYPE_STA)
2986 return IWL_AP_ID;
2987 else {
2988 u8 *da = ieee80211_get_DA(hdr);
bb8c093b 2989 return iwl4965_hw_find_station(priv, da);
b481de9c
ZY		 2990 }
2991}
2992
bb8c093b 2993static struct ieee80211_hdr *iwl4965_tx_queue_get_hdr(
c79dd5b5 2994 struct iwl_priv *priv, int txq_id, int idx)
b481de9c
ZY		 2995{
2996 if (priv->txq[txq_id].txb[idx].skb[0])
2997 return (struct ieee80211_hdr *)priv->txq[txq_id].
2998 txb[idx].skb[0]->data;
2999 return NULL;
3000}
3001
bb8c093b 3002static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
b481de9c
ZY		 3003{
3004 __le32 *scd_ssn = (__le32 *)((u32 *)&tx_resp->status +
3005 tx_resp->frame_count);
3006 return le32_to_cpu(*scd_ssn) & MAX_SN;
3007
3008}
6440adb5
CB		 3009
3010/**
3011 * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue
3012 */
c79dd5b5 3013static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
bb8c093b 3014 struct iwl4965_ht_agg *agg,
fe01b477 3015 struct iwl4965_tx_resp_agg *tx_resp,
b481de9c
ZY		 3016 u16 start_idx)
3017{
fe01b477
RR		 3018 u16 status;
3019 struct agg_tx_status *frame_status = &tx_resp->status;
b481de9c
ZY		 3020 struct ieee80211_tx_status *tx_status = NULL;
3021 struct ieee80211_hdr *hdr = NULL;
3022 int i, sh;
3023 int txq_id, idx;
3024 u16 seq;
3025
3026 if (agg->wait_for_ba)
6440adb5 3027 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
b481de9c
ZY		 3028
3029 agg->frame_count = tx_resp->frame_count;
3030 agg->start_idx = start_idx;
3031 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
fe01b477 3032 agg->bitmap = 0;
b481de9c 3033
6440adb5 3034 /* # frames attempted by Tx command */
b481de9c 3035 if (agg->frame_count == 1) {
6440adb5 3036 /* Only one frame was attempted; no block-ack will arrive */
fe01b477
RR		 3037 status = le16_to_cpu(frame_status[0].status);
3038 seq = le16_to_cpu(frame_status[0].sequence);
3039 idx = SEQ_TO_INDEX(seq);
3040 txq_id = SEQ_TO_QUEUE(seq);
b481de9c 3041
b481de9c 3042 /* FIXME: code repetition */
fe01b477
RR		 3043 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
3044 agg->frame_count, agg->start_idx, idx);
b481de9c 3045
fe01b477 3046 tx_status = &(priv->txq[txq_id].txb[idx].status);
b481de9c
ZY		 3047 tx_status->retry_count = tx_resp->failure_frame;
3048 tx_status->queue_number = status & 0xff;
fe01b477
RR		 3049 tx_status->queue_length = tx_resp->failure_rts;
3050 tx_status->control.flags &= ~IEEE80211_TXCTL_AMPDU;
bb8c093b 3051 tx_status->flags = iwl4965_is_tx_success(status)?
b481de9c 3052 IEEE80211_TX_STATUS_ACK : 0;
4c424e4c
RR		 3053 iwl4965_hwrate_to_tx_control(priv,
3054 le32_to_cpu(tx_resp->rate_n_flags),
3055 &tx_status->control);
b481de9c
ZY		 3056 /* FIXME: code repetition end */
3057
3058 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
3059 status & 0xff, tx_resp->failure_frame);
3060 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n",
bb8c093b 3061 iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags));
b481de9c
ZY		 3062
3063 agg->wait_for_ba = 0;
3064 } else {
6440adb5 3065 /* Two or more frames were attempted; expect block-ack */
b481de9c
ZY		 3066 u64 bitmap = 0;
3067 int start = agg->start_idx;
3068
6440adb5 3069 /* Construct bit-map of pending frames within Tx window */
b481de9c
ZY		 3070 for (i = 0; i < agg->frame_count; i++) {
3071 u16 sc;
fe01b477
RR		 3072 status = le16_to_cpu(frame_status[i].status);
3073 seq = le16_to_cpu(frame_status[i].sequence);
b481de9c
ZY		 3074 idx = SEQ_TO_INDEX(seq);
3075 txq_id = SEQ_TO_QUEUE(seq);
3076
3077 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
3078 AGG_TX_STATE_ABORT_MSK))
3079 continue;
3080
3081 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
3082 agg->frame_count, txq_id, idx);
3083
bb8c093b 3084 hdr = iwl4965_tx_queue_get_hdr(priv, txq_id, idx);
b481de9c
ZY		 3085
3086 sc = le16_to_cpu(hdr->seq_ctrl);
3087 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
3088 IWL_ERROR("BUG_ON idx doesn't match seq control"
3089 " idx=%d, seq_idx=%d, seq=%d\n",
3090 idx, SEQ_TO_SN(sc),
3091 hdr->seq_ctrl);
3092 return -1;
3093 }
3094
3095 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
3096 i, idx, SEQ_TO_SN(sc));
3097
3098 sh = idx - start;
3099 if (sh > 64) {
3100 sh = (start - idx) + 0xff;
3101 bitmap = bitmap << sh;
3102 sh = 0;
3103 start = idx;
3104 } else if (sh < -64)
3105 sh = 0xff - (start - idx);
3106 else if (sh < 0) {
3107 sh = start - idx;
3108 start = idx;
3109 bitmap = bitmap << sh;
3110 sh = 0;
3111 }
3112 bitmap |= (1 << sh);
3113 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
3114 start, (u32)(bitmap & 0xFFFFFFFF));
3115 }
3116
fe01b477 3117 agg->bitmap = bitmap;
b481de9c
ZY		 3118 agg->start_idx = start;
3119 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
fe01b477 3120 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
b481de9c 3121 agg->frame_count, agg->start_idx,
06501d29 3122 (unsigned long long)agg->bitmap);
b481de9c
ZY		 3123
3124 if (bitmap)
3125 agg->wait_for_ba = 1;
3126 }
3127 return 0;
3128}
3129#endif
b481de9c 3130
6440adb5
CB		 3131/**
3132 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
3133 */
c79dd5b5 3134static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
bb8c093b 3135 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3136{
bb8c093b 3137 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3138 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3139 int txq_id = SEQ_TO_QUEUE(sequence);
3140 int index = SEQ_TO_INDEX(sequence);
bb8c093b 3141 struct iwl4965_tx_queue *txq = &priv->txq[txq_id];
b481de9c 3142 struct ieee80211_tx_status *tx_status;
bb8c093b 3143 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
b481de9c 3144 u32 status = le32_to_cpu(tx_resp->status);
c8b0e6e1 3145#ifdef CONFIG_IWL4965_HT
fe01b477
RR		 3146 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
3147 struct ieee80211_hdr *hdr;
3148 __le16 *qc;
b481de9c
ZY		 3149#endif
3150
3151 if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
3152 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
3153 "is out of range [0-%d] %d %d\n", txq_id,
fc4b6853
TW		 3154 index, txq->q.n_bd, txq->q.write_ptr,
3155 txq->q.read_ptr);
b481de9c
ZY		 3156 return;
3157 }
3158
c8b0e6e1 3159#ifdef CONFIG_IWL4965_HT
fe01b477
RR		 3160 hdr = iwl4965_tx_queue_get_hdr(priv, txq_id, index);
3161 qc = ieee80211_get_qos_ctrl(hdr);
3162
3163 if (qc)
3164 tid = le16_to_cpu(*qc) & 0xf;
3165
3166 sta_id = iwl4965_get_ra_sta_id(priv, hdr);
3167 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
3168 IWL_ERROR("Station not known\n");
3169 return;
3170 }
3171
b481de9c 3172 if (txq->sched_retry) {
bb8c093b 3173 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
bb8c093b 3174 struct iwl4965_ht_agg *agg = NULL;
b481de9c 3175
fe01b477 3176 if (!qc)
b481de9c 3177 return;
b481de9c
ZY		 3178
3179 agg = &priv->stations[sta_id].tid[tid].agg;
3180
fe01b477
RR		 3181 iwl4965_tx_status_reply_tx(priv, agg,
3182 (struct iwl4965_tx_resp_agg *)tx_resp, index);
b481de9c
ZY		 3183
3184 if ((tx_resp->frame_count == 1) &&
bb8c093b 3185 !iwl4965_is_tx_success(status)) {
b481de9c
ZY		 3186 /* TODO: send BAR */
3187 }
3188
fe01b477
RR		 3189 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
3190 int freed;
c54b679d 3191 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
b481de9c
ZY		 3192 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
3193 "%d index %d\n", scd_ssn , index);
fe01b477
RR		 3194 freed = iwl4965_tx_queue_reclaim(priv, txq_id, index);
3195 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3196
3197 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3198 txq_id >= 0 && priv->mac80211_registered &&
3199 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3200 ieee80211_wake_queue(priv->hw, txq_id);
3201
3202 iwl4965_check_empty_hw_queue(priv, sta_id, tid, txq_id);
b481de9c
ZY		 3203 }
3204 } else {
c8b0e6e1 3205#endif /* CONFIG_IWL4965_HT */
fc4b6853 3206 tx_status = &(txq->txb[txq->q.read_ptr].status);
b481de9c
ZY		 3207
3208 tx_status->retry_count = tx_resp->failure_frame;
3209 tx_status->queue_number = status;
3210 tx_status->queue_length = tx_resp->bt_kill_count;
3211 tx_status->queue_length |= tx_resp->failure_rts;
b481de9c 3212 tx_status->flags =
bb8c093b 3213 iwl4965_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
4c424e4c
RR		 3214 iwl4965_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
3215 &tx_status->control);
b481de9c 3216
b481de9c 3217 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags 0x%x "
bb8c093b 3218 "retries %d\n", txq_id, iwl4965_get_tx_fail_reason(status),
b481de9c
ZY		 3219 status, le32_to_cpu(tx_resp->rate_n_flags),
3220 tx_resp->failure_frame);
3221
3222 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
fe01b477
RR		 3223 if (index != -1) {
3224 int freed = iwl4965_tx_queue_reclaim(priv, txq_id, index);
3225#ifdef CONFIG_IWL4965_HT
3226 if (tid != MAX_TID_COUNT)
3227 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3228 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3229 (txq_id >= 0) &&
3230 priv->mac80211_registered)
3231 ieee80211_wake_queue(priv->hw, txq_id);
3232 if (tid != MAX_TID_COUNT)
3233 iwl4965_check_empty_hw_queue(priv, sta_id, tid, txq_id);
3234#endif
3235 }
c8b0e6e1 3236#ifdef CONFIG_IWL4965_HT
b481de9c 3237 }
c8b0e6e1 3238#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 3239
3240 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
3241 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
3242}
3243
3244
c79dd5b5 3245static void iwl4965_rx_reply_alive(struct iwl_priv *priv,
bb8c093b 3246 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3247{
bb8c093b
CH		 3248 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3249 struct iwl4965_alive_resp *palive;
b481de9c
ZY		 3250 struct delayed_work *pwork;
3251
3252 palive = &pkt->u.alive_frame;
3253
3254 IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
3255 "0x%01X 0x%01X\n",
3256 palive->is_valid, palive->ver_type,
3257 palive->ver_subtype);
3258
3259 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3260 IWL_DEBUG_INFO("Initialization Alive received.\n");
3261 memcpy(&priv->card_alive_init,
3262 &pkt->u.alive_frame,
bb8c093b 3263 sizeof(struct iwl4965_init_alive_resp));
b481de9c
ZY		 3264 pwork = &priv->init_alive_start;
3265 } else {
3266 IWL_DEBUG_INFO("Runtime Alive received.\n");
3267 memcpy(&priv->card_alive, &pkt->u.alive_frame,
bb8c093b 3268 sizeof(struct iwl4965_alive_resp));
b481de9c
ZY		 3269 pwork = &priv->alive_start;
3270 }
3271
3272 /* We delay the ALIVE response by 5ms to
3273 * give the HW RF Kill time to activate... */
3274 if (palive->is_valid == UCODE_VALID_OK)
3275 queue_delayed_work(priv->workqueue, pwork,
3276 msecs_to_jiffies(5));
3277 else
3278 IWL_WARNING("uCode did not respond OK.\n");
3279}
3280
c79dd5b5 3281static void iwl4965_rx_reply_add_sta(struct iwl_priv *priv,
bb8c093b 3282 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3283{
bb8c093b 3284 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3285
3286 IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
3287 return;
3288}
3289
c79dd5b5 3290static void iwl4965_rx_reply_error(struct iwl_priv *priv,
bb8c093b 3291 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3292{
bb8c093b 3293 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3294
3295 IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3296 "seq 0x%04X ser 0x%08X\n",
3297 le32_to_cpu(pkt->u.err_resp.error_type),
3298 get_cmd_string(pkt->u.err_resp.cmd_id),
3299 pkt->u.err_resp.cmd_id,
3300 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3301 le32_to_cpu(pkt->u.err_resp.error_info));
3302}
3303
3304#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3305
c79dd5b5 3306static void iwl4965_rx_csa(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3307{
bb8c093b
CH		 3308 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3309 struct iwl4965_rxon_cmd *rxon = (void *)&priv->active_rxon;
3310 struct iwl4965_csa_notification *csa = &(pkt->u.csa_notif);
b481de9c
ZY		 3311 IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3312 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3313 rxon->channel = csa->channel;
3314 priv->staging_rxon.channel = csa->channel;
3315}
3316
c79dd5b5 3317static void iwl4965_rx_spectrum_measure_notif(struct iwl_priv *priv,
bb8c093b 3318 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3319{
c8b0e6e1 3320#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
bb8c093b
CH		 3321 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3322 struct iwl4965_spectrum_notification *report = &(pkt->u.spectrum_notif);
b481de9c
ZY		 3323
3324 if (!report->state) {
3325 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3326 "Spectrum Measure Notification: Start\n");
3327 return;
3328 }
3329
3330 memcpy(&priv->measure_report, report, sizeof(*report));
3331 priv->measurement_status |= MEASUREMENT_READY;
3332#endif
3333}
3334
c79dd5b5 3335static void iwl4965_rx_pm_sleep_notif(struct iwl_priv *priv,
bb8c093b 3336 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3337{
0a6857e7 3338#ifdef CONFIG_IWLWIFI_DEBUG
bb8c093b
CH		 3339 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3340 struct iwl4965_sleep_notification *sleep = &(pkt->u.sleep_notif);
b481de9c
ZY		 3341 IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3342 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3343#endif
3344}
3345
c79dd5b5 3346static void iwl4965_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
bb8c093b 3347 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3348{
bb8c093b 3349 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3350 IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3351 "notification for %s:\n",
3352 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
0a6857e7 3353 iwl_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 3354}
3355
bb8c093b 3356static void iwl4965_bg_beacon_update(struct work_struct *work)
b481de9c 3357{
c79dd5b5
TW		 3358 struct iwl_priv *priv =
3359 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 3360 struct sk_buff *beacon;
3361
3362 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
32bfd35d 3363 beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL);
b481de9c
ZY		 3364
3365 if (!beacon) {
3366 IWL_ERROR("update beacon failed\n");
3367 return;
3368 }
3369
3370 mutex_lock(&priv->mutex);
3371 /* new beacon skb is allocated every time; dispose previous.*/
3372 if (priv->ibss_beacon)
3373 dev_kfree_skb(priv->ibss_beacon);
3374
3375 priv->ibss_beacon = beacon;
3376 mutex_unlock(&priv->mutex);
3377
bb8c093b 3378 iwl4965_send_beacon_cmd(priv);
b481de9c
ZY		 3379}
3380
c79dd5b5 3381static void iwl4965_rx_beacon_notif(struct iwl_priv *priv,
bb8c093b 3382 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3383{
0a6857e7 3384#ifdef CONFIG_IWLWIFI_DEBUG
bb8c093b
CH		 3385 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3386 struct iwl4965_beacon_notif *beacon = &(pkt->u.beacon_status);
3387 u8 rate = iwl4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c
ZY		 3388
3389 IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3390 "tsf %d %d rate %d\n",
3391 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3392 beacon->beacon_notify_hdr.failure_frame,
3393 le32_to_cpu(beacon->ibss_mgr_status),
3394 le32_to_cpu(beacon->high_tsf),
3395 le32_to_cpu(beacon->low_tsf), rate);
3396#endif
3397
3398 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
3399 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3400 queue_work(priv->workqueue, &priv->beacon_update);
3401}
3402
3403/* Service response to REPLY_SCAN_CMD (0x80) */
c79dd5b5 3404static void iwl4965_rx_reply_scan(struct iwl_priv *priv,
bb8c093b 3405 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3406{
0a6857e7 3407#ifdef CONFIG_IWLWIFI_DEBUG
bb8c093b
CH		 3408 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3409 struct iwl4965_scanreq_notification *notif =
3410 (struct iwl4965_scanreq_notification *)pkt->u.raw;
b481de9c
ZY		 3411
3412 IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3413#endif
3414}
3415
3416/* Service SCAN_START_NOTIFICATION (0x82) */
c79dd5b5 3417static void iwl4965_rx_scan_start_notif(struct iwl_priv *priv,
bb8c093b 3418 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3419{
bb8c093b
CH		 3420 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3421 struct iwl4965_scanstart_notification *notif =
3422 (struct iwl4965_scanstart_notification *)pkt->u.raw;
b481de9c
ZY		 3423 priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3424 IWL_DEBUG_SCAN("Scan start: "
3425 "%d [802.11%s] "
3426 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3427 notif->channel,
3428 notif->band ? "bg" : "a",
3429 notif->tsf_high,
3430 notif->tsf_low, notif->status, notif->beacon_timer);
3431}
3432
3433/* Service SCAN_RESULTS_NOTIFICATION (0x83) */
c79dd5b5 3434static void iwl4965_rx_scan_results_notif(struct iwl_priv *priv,
bb8c093b 3435 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3436{
bb8c093b
CH		 3437 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3438 struct iwl4965_scanresults_notification *notif =
3439 (struct iwl4965_scanresults_notification *)pkt->u.raw;
b481de9c
ZY		 3440
3441 IWL_DEBUG_SCAN("Scan ch.res: "
3442 "%d [802.11%s] "
3443 "(TSF: 0x%08X:%08X) - %d "
3444 "elapsed=%lu usec (%dms since last)\n",
3445 notif->channel,
3446 notif->band ? "bg" : "a",
3447 le32_to_cpu(notif->tsf_high),
3448 le32_to_cpu(notif->tsf_low),
3449 le32_to_cpu(notif->statistics[0]),
3450 le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3451 jiffies_to_msecs(elapsed_jiffies
3452 (priv->last_scan_jiffies, jiffies)));
3453
3454 priv->last_scan_jiffies = jiffies;
7878a5a4 3455 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3456}
3457
3458/* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
c79dd5b5 3459static void iwl4965_rx_scan_complete_notif(struct iwl_priv *priv,
bb8c093b 3460 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3461{
bb8c093b
CH		 3462 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3463 struct iwl4965_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
b481de9c
ZY		 3464
3465 IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3466 scan_notif->scanned_channels,
3467 scan_notif->tsf_low,
3468 scan_notif->tsf_high, scan_notif->status);
3469
3470 /* The HW is no longer scanning */
3471 clear_bit(STATUS_SCAN_HW, &priv->status);
3472
3473 /* The scan completion notification came in, so kill that timer... */
3474 cancel_delayed_work(&priv->scan_check);
3475
3476 IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
3477 (priv->scan_bands == 2) ? "2.4" : "5.2",
3478 jiffies_to_msecs(elapsed_jiffies
3479 (priv->scan_pass_start, jiffies)));
3480
3481 /* Remove this scanned band from the list
3482 * of pending bands to scan */
3483 priv->scan_bands--;
3484
3485 /* If a request to abort was given, or the scan did not succeed
3486 * then we reset the scan state machine and terminate,
3487 * re-queuing another scan if one has been requested */
3488 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3489 IWL_DEBUG_INFO("Aborted scan completed.\n");
3490 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3491 } else {
3492 /* If there are more bands on this scan pass reschedule */
3493 if (priv->scan_bands > 0)
3494 goto reschedule;
3495 }
3496
3497 priv->last_scan_jiffies = jiffies;
7878a5a4 3498 priv->next_scan_jiffies = 0;
b481de9c
ZY		 3499 IWL_DEBUG_INFO("Setting scan to off\n");
3500
3501 clear_bit(STATUS_SCANNING, &priv->status);
3502
3503 IWL_DEBUG_INFO("Scan took %dms\n",
3504 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3505
3506 queue_work(priv->workqueue, &priv->scan_completed);
3507
3508 return;
3509
3510reschedule:
3511 priv->scan_pass_start = jiffies;
3512 queue_work(priv->workqueue, &priv->request_scan);
3513}
3514
3515/* Handle notification from uCode that card's power state is changing
3516 * due to software, hardware, or critical temperature RFKILL */
c79dd5b5 3517static void iwl4965_rx_card_state_notif(struct iwl_priv *priv,
bb8c093b 3518 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3519{
bb8c093b 3520 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3521 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3522 unsigned long status = priv->status;
3523
3524 IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3525 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3526 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3527
3528 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3529 RF_CARD_DISABLED)) {
3530
3395f6e9 3531 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 3532 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3533
3395f6e9
TW		 3534 if (!iwl_grab_nic_access(priv)) {
3535 iwl_write_direct32(
b481de9c
ZY		 3536 priv, HBUS_TARG_MBX_C,
3537 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
3538
3395f6e9 3539 iwl_release_nic_access(priv);
b481de9c
ZY		 3540 }
3541
3542 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 3543 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 3544 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3395f6e9
TW		 3545 if (!iwl_grab_nic_access(priv)) {
3546 iwl_write_direct32(
b481de9c
ZY		 3547 priv, HBUS_TARG_MBX_C,
3548 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
3549
3395f6e9 3550 iwl_release_nic_access(priv);
b481de9c
ZY		 3551 }
3552 }
3553
3554 if (flags & RF_CARD_DISABLED) {
3395f6e9 3555 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c 3556 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
3395f6e9
TW		 3557 iwl_read32(priv, CSR_UCODE_DRV_GP1);
3558 if (!iwl_grab_nic_access(priv))
3559 iwl_release_nic_access(priv);
b481de9c
ZY		 3560 }
3561 }
3562
3563 if (flags & HW_CARD_DISABLED)
3564 set_bit(STATUS_RF_KILL_HW, &priv->status);
3565 else
3566 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3567
3568
3569 if (flags & SW_CARD_DISABLED)
3570 set_bit(STATUS_RF_KILL_SW, &priv->status);
3571 else
3572 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3573
3574 if (!(flags & RXON_CARD_DISABLED))
bb8c093b 3575 iwl4965_scan_cancel(priv);
b481de9c
ZY		 3576
3577 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3578 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3579 (test_bit(STATUS_RF_KILL_SW, &status) !=
3580 test_bit(STATUS_RF_KILL_SW, &priv->status)))
3581 queue_work(priv->workqueue, &priv->rf_kill);
3582 else
3583 wake_up_interruptible(&priv->wait_command_queue);
3584}
3585
3586/**
bb8c093b 3587 * iwl4965_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 3588 *
3589 * Setup the RX handlers for each of the reply types sent from the uCode
3590 * to the host.
3591 *
3592 * This function chains into the hardware specific files for them to setup
3593 * any hardware specific handlers as well.
3594 */
c79dd5b5 3595static void iwl4965_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 3596{
bb8c093b
CH		 3597 priv->rx_handlers[REPLY_ALIVE] = iwl4965_rx_reply_alive;
3598 priv->rx_handlers[REPLY_ADD_STA] = iwl4965_rx_reply_add_sta;
3599 priv->rx_handlers[REPLY_ERROR] = iwl4965_rx_reply_error;
3600 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl4965_rx_csa;
b481de9c 3601 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
bb8c093b
CH		 3602 iwl4965_rx_spectrum_measure_notif;
3603 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl4965_rx_pm_sleep_notif;
b481de9c 3604 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
bb8c093b
CH		 3605 iwl4965_rx_pm_debug_statistics_notif;
3606 priv->rx_handlers[BEACON_NOTIFICATION] = iwl4965_rx_beacon_notif;
b481de9c 3607
9fbab516
BC		 3608 /*
3609 * The same handler is used for both the REPLY to a discrete
3610 * statistics request from the host as well as for the periodic
3611 * statistics notifications (after received beacons) from the uCode.
b481de9c 3612 */
bb8c093b
CH		 3613 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl4965_hw_rx_statistics;
3614 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl4965_hw_rx_statistics;
b481de9c 3615
bb8c093b
CH		 3616 priv->rx_handlers[REPLY_SCAN_CMD] = iwl4965_rx_reply_scan;
3617 priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl4965_rx_scan_start_notif;
b481de9c 3618 priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
bb8c093b 3619 iwl4965_rx_scan_results_notif;
b481de9c 3620 priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
bb8c093b
CH		 3621 iwl4965_rx_scan_complete_notif;
3622 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl4965_rx_card_state_notif;
3623 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
b481de9c 3624
9fbab516 3625 /* Set up hardware specific Rx handlers */
bb8c093b 3626 iwl4965_hw_rx_handler_setup(priv);
b481de9c
ZY		 3627}
3628
3629/**
bb8c093b 3630 * iwl4965_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
b481de9c
ZY		 3631 * @rxb: Rx buffer to reclaim
3632 *
3633 * If an Rx buffer has an async callback associated with it the callback
3634 * will be executed. The attached skb (if present) will only be freed
3635 * if the callback returns 1
3636 */
c79dd5b5 3637static void iwl4965_tx_cmd_complete(struct iwl_priv *priv,
bb8c093b 3638 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3639{
bb8c093b 3640 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3641 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3642 int txq_id = SEQ_TO_QUEUE(sequence);
3643 int index = SEQ_TO_INDEX(sequence);
3644 int huge = sequence & SEQ_HUGE_FRAME;
3645 int cmd_index;
857485c0 3646 struct iwl_cmd *cmd;
b481de9c
ZY		 3647
3648 /* If a Tx command is being handled and it isn't in the actual
3649 * command queue then there a command routing bug has been introduced
3650 * in the queue management code. */
3651 if (txq_id != IWL_CMD_QUEUE_NUM)
3652 IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
3653 txq_id, pkt->hdr.cmd);
3654 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3655
3656 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3657 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3658
3659 /* Input error checking is done when commands are added to queue. */
3660 if (cmd->meta.flags & CMD_WANT_SKB) {
3661 cmd->meta.source->u.skb = rxb->skb;
3662 rxb->skb = NULL;
3663 } else if (cmd->meta.u.callback &&
3664 !cmd->meta.u.callback(priv, cmd, rxb->skb))
3665 rxb->skb = NULL;
3666
bb8c093b 3667 iwl4965_tx_queue_reclaim(priv, txq_id, index);
b481de9c
ZY		 3668
3669 if (!(cmd->meta.flags & CMD_ASYNC)) {
3670 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3671 wake_up_interruptible(&priv->wait_command_queue);
3672 }
3673}
3674
3675/************************** RX-FUNCTIONS ****************************/
3676/*
3677 * Rx theory of operation
3678 *
9fbab516
BC		 3679 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
3680 * each of which point to Receive Buffers to be filled by 4965. These get
3681 * used not only for Rx frames, but for any command response or notification
3682 * from the 4965. The driver and 4965 manage the Rx buffers by means
3683 * of indexes into the circular buffer.
b481de9c
ZY		 3684 *
3685 * Rx Queue Indexes
3686 * The host/firmware share two index registers for managing the Rx buffers.
3687 *
3688 * The READ index maps to the first position that the firmware may be writing
3689 * to -- the driver can read up to (but not including) this position and get
3690 * good data.
3691 * The READ index is managed by the firmware once the card is enabled.
3692 *
3693 * The WRITE index maps to the last position the driver has read from -- the
3694 * position preceding WRITE is the last slot the firmware can place a packet.
3695 *
3696 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3697 * WRITE = READ.
3698 *
9fbab516 3699 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY		 3700 * INDEX position, and WRITE to the last (READ - 1 wrapped)
3701 *
9fbab516 3702 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY		 3703 * and fire the RX interrupt. The driver can then query the READ index and
3704 * process as many packets as possible, moving the WRITE index forward as it
3705 * resets the Rx queue buffers with new memory.
3706 *
3707 * The management in the driver is as follows:
3708 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
3709 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 3710 * to replenish the iwl->rxq->rx_free.
bb8c093b 3711 * + In iwl4965_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY		 3712 * iwl->rxq is replenished and the READ INDEX is updated (updating the
3713 * 'processed' and 'read' driver indexes as well)
3714 * + A received packet is processed and handed to the kernel network stack,
3715 * detached from the iwl->rxq. The driver 'processed' index is updated.
3716 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3717 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3718 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
3719 * were enough free buffers and RX_STALLED is set it is cleared.
3720 *
3721 *
3722 * Driver sequence:
3723 *
9fbab516
BC		 3724 * iwl4965_rx_queue_alloc() Allocates rx_free
3725 * iwl4965_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 3726 * iwl4965_rx_queue_restock
9fbab516 3727 * iwl4965_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY		 3728 * queue, updates firmware pointers, and updates
3729 * the WRITE index. If insufficient rx_free buffers
bb8c093b 3730 * are available, schedules iwl4965_rx_replenish
b481de9c
ZY		 3731 *
3732 * -- enable interrupts --
9fbab516 3733 * ISR - iwl4965_rx() Detach iwl4965_rx_mem_buffers from pool up to the
b481de9c
ZY		 3734 * READ INDEX, detaching the SKB from the pool.
3735 * Moves the packet buffer from queue to rx_used.
bb8c093b 3736 * Calls iwl4965_rx_queue_restock to refill any empty
b481de9c
ZY		 3737 * slots.
3738 * ...
3739 *
3740 */
3741
3742/**
bb8c093b 3743 * iwl4965_rx_queue_space - Return number of free slots available in queue.
b481de9c 3744 */
bb8c093b 3745static int iwl4965_rx_queue_space(const struct iwl4965_rx_queue *q)
b481de9c
ZY		 3746{
3747 int s = q->read - q->write;
3748 if (s <= 0)
3749 s += RX_QUEUE_SIZE;
3750 /* keep some buffer to not confuse full and empty queue */
3751 s -= 2;
3752 if (s < 0)
3753 s = 0;
3754 return s;
3755}
3756
3757/**
bb8c093b 3758 * iwl4965_rx_queue_update_write_ptr - Update the write pointer for the RX queue
b481de9c 3759 */
c79dd5b5 3760int iwl4965_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl4965_rx_queue *q)
b481de9c
ZY		 3761{
3762 u32 reg = 0;
3763 int rc = 0;
3764 unsigned long flags;
3765
3766 spin_lock_irqsave(&q->lock, flags);
3767
3768 if (q->need_update == 0)
3769 goto exit_unlock;
3770
6440adb5 3771 /* If power-saving is in use, make sure device is awake */
b481de9c 3772 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3395f6e9 3773 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 3774
3775 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3395f6e9 3776 iwl_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 3777 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3778 goto exit_unlock;
3779 }
3780
3395f6e9 3781 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 3782 if (rc)
3783 goto exit_unlock;
3784
6440adb5 3785 /* Device expects a multiple of 8 */
3395f6e9 3786 iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
b481de9c 3787 q->write & ~0x7);
3395f6e9 3788 iwl_release_nic_access(priv);
6440adb5
CB		 3789
3790 /* Else device is assumed to be awake */
b481de9c 3791 } else
6440adb5 3792 /* Device expects a multiple of 8 */
3395f6e9 3793 iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
b481de9c
ZY		 3794
3795
3796 q->need_update = 0;
3797
3798 exit_unlock:
3799 spin_unlock_irqrestore(&q->lock, flags);
3800 return rc;
3801}
3802
3803/**
9fbab516 3804 * iwl4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 3805 */
c79dd5b5 3806static inline __le32 iwl4965_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY		 3807 dma_addr_t dma_addr)
3808{
3809 return cpu_to_le32((u32)(dma_addr >> 8));
3810}
3811
3812
3813/**
bb8c093b 3814 * iwl4965_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 3815 *
9fbab516 3816 * If there are slots in the RX queue that need to be restocked,
b481de9c 3817 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 3818 * as we can, pulling from rx_free.
b481de9c
ZY		 3819 *
3820 * This moves the 'write' index forward to catch up with 'processed', and
3821 * also updates the memory address in the firmware to reference the new
3822 * target buffer.
3823 */
c79dd5b5 3824static int iwl4965_rx_queue_restock(struct iwl_priv *priv)
b481de9c 3825{
bb8c093b 3826 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c 3827 struct list_head *element;
bb8c093b 3828 struct iwl4965_rx_mem_buffer *rxb;
b481de9c
ZY		 3829 unsigned long flags;
3830 int write, rc;
3831
3832 spin_lock_irqsave(&rxq->lock, flags);
3833 write = rxq->write & ~0x7;
bb8c093b 3834 while ((iwl4965_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 3835 /* Get next free Rx buffer, remove from free list */
b481de9c 3836 element = rxq->rx_free.next;
bb8c093b 3837 rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list);
b481de9c 3838 list_del(element);
6440adb5
CB		 3839
3840 /* Point to Rx buffer via next RBD in circular buffer */
bb8c093b 3841 rxq->bd[rxq->write] = iwl4965_dma_addr2rbd_ptr(priv, rxb->dma_addr);
b481de9c
ZY		 3842 rxq->queue[rxq->write] = rxb;
3843 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3844 rxq->free_count--;
3845 }
3846 spin_unlock_irqrestore(&rxq->lock, flags);
3847 /* If the pre-allocated buffer pool is dropping low, schedule to
3848 * refill it */
3849 if (rxq->free_count <= RX_LOW_WATERMARK)
3850 queue_work(priv->workqueue, &priv->rx_replenish);
3851
3852
6440adb5
CB		 3853 /* If we've added more space for the firmware to place data, tell it.
3854 * Increment device's write pointer in multiples of 8. */
b481de9c
ZY		 3855 if ((write != (rxq->write & ~0x7))
3856 || (abs(rxq->write - rxq->read) > 7)) {
3857 spin_lock_irqsave(&rxq->lock, flags);
3858 rxq->need_update = 1;
3859 spin_unlock_irqrestore(&rxq->lock, flags);
bb8c093b 3860 rc = iwl4965_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 3861 if (rc)
3862 return rc;
3863 }
3864
3865 return 0;
3866}
3867
3868/**
bb8c093b 3869 * iwl4965_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY		 3870 *
3871 * When moving to rx_free an SKB is allocated for the slot.
3872 *
bb8c093b 3873 * Also restock the Rx queue via iwl4965_rx_queue_restock.
01ebd063 3874 * This is called as a scheduled work item (except for during initialization)
b481de9c 3875 */
c79dd5b5 3876static void iwl4965_rx_allocate(struct iwl_priv *priv)
b481de9c 3877{
bb8c093b 3878 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c 3879 struct list_head *element;
bb8c093b 3880 struct iwl4965_rx_mem_buffer *rxb;
b481de9c
ZY		 3881 unsigned long flags;
3882 spin_lock_irqsave(&rxq->lock, flags);
3883 while (!list_empty(&rxq->rx_used)) {
3884 element = rxq->rx_used.next;
bb8c093b 3885 rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list);
6440adb5
CB		 3886
3887 /* Alloc a new receive buffer */
b481de9c 3888 rxb->skb =
9ee1ba47
RR		 3889 alloc_skb(priv->hw_setting.rx_buf_size,
3890 __GFP_NOWARN | GFP_ATOMIC);
b481de9c
ZY		 3891 if (!rxb->skb) {
3892 if (net_ratelimit())
3893 printk(KERN_CRIT DRV_NAME
3894 ": Can not allocate SKB buffers\n");
3895 /* We don't reschedule replenish work here -- we will
3896 * call the restock method and if it still needs
3897 * more buffers it will schedule replenish */
3898 break;
3899 }
3900 priv->alloc_rxb_skb++;
3901 list_del(element);
6440adb5
CB		 3902
3903 /* Get physical address of RB/SKB */
b481de9c
ZY		 3904 rxb->dma_addr =
3905 pci_map_single(priv->pci_dev, rxb->skb->data,
9ee1ba47 3906 priv->hw_setting.rx_buf_size, PCI_DMA_FROMDEVICE);
b481de9c
ZY		 3907 list_add_tail(&rxb->list, &rxq->rx_free);
3908 rxq->free_count++;
3909 }
3910 spin_unlock_irqrestore(&rxq->lock, flags);
5c0eef96
MA		 3911}
3912
3913/*
3914 * this should be called while priv->lock is locked
3915*/
4fd1f841 3916static void __iwl4965_rx_replenish(void *data)
5c0eef96 3917{
c79dd5b5 3918 struct iwl_priv *priv = data;
5c0eef96
MA		 3919
3920 iwl4965_rx_allocate(priv);
3921 iwl4965_rx_queue_restock(priv);
3922}
3923
3924
3925void iwl4965_rx_replenish(void *data)
3926{
c79dd5b5 3927 struct iwl_priv *priv = data;
5c0eef96
MA		 3928 unsigned long flags;
3929
3930 iwl4965_rx_allocate(priv);
b481de9c
ZY		 3931
3932 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 3933 iwl4965_rx_queue_restock(priv);
b481de9c
ZY		 3934 spin_unlock_irqrestore(&priv->lock, flags);
3935}
3936
3937/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
9fbab516 3938 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
b481de9c
ZY		 3939 * This free routine walks the list of POOL entries and if SKB is set to
3940 * non NULL it is unmapped and freed
3941 */
c79dd5b5 3942static void iwl4965_rx_queue_free(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c
ZY		 3943{
3944 int i;
3945 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3946 if (rxq->pool[i].skb != NULL) {
3947 pci_unmap_single(priv->pci_dev,
3948 rxq->pool[i].dma_addr,
9ee1ba47
RR		 3949 priv->hw_setting.rx_buf_size,
3950 PCI_DMA_FROMDEVICE);
b481de9c
ZY		 3951 dev_kfree_skb(rxq->pool[i].skb);
3952 }
3953 }
3954
3955 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3956 rxq->dma_addr);
3957 rxq->bd = NULL;
3958}
3959
c79dd5b5 3960int iwl4965_rx_queue_alloc(struct iwl_priv *priv)
b481de9c 3961{
bb8c093b 3962 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 3963 struct pci_dev *dev = priv->pci_dev;
3964 int i;
3965
3966 spin_lock_init(&rxq->lock);
3967 INIT_LIST_HEAD(&rxq->rx_free);
3968 INIT_LIST_HEAD(&rxq->rx_used);
6440adb5
CB		 3969
3970 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
b481de9c
ZY		 3971 rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3972 if (!rxq->bd)
3973 return -ENOMEM;
6440adb5 3974
b481de9c
ZY		 3975 /* Fill the rx_used queue with _all_ of the Rx buffers */
3976 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3977 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
6440adb5 3978
b481de9c
ZY		 3979 /* Set us so that we have processed and used all buffers, but have
3980 * not restocked the Rx queue with fresh buffers */
3981 rxq->read = rxq->write = 0;
3982 rxq->free_count = 0;
3983 rxq->need_update = 0;
3984 return 0;
3985}
3986
c79dd5b5 3987void iwl4965_rx_queue_reset(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c
ZY		 3988{
3989 unsigned long flags;
3990 int i;
3991 spin_lock_irqsave(&rxq->lock, flags);
3992 INIT_LIST_HEAD(&rxq->rx_free);
3993 INIT_LIST_HEAD(&rxq->rx_used);
3994 /* Fill the rx_used queue with _all_ of the Rx buffers */
3995 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3996 /* In the reset function, these buffers may have been allocated
3997 * to an SKB, so we need to unmap and free potential storage */
3998 if (rxq->pool[i].skb != NULL) {
3999 pci_unmap_single(priv->pci_dev,
4000 rxq->pool[i].dma_addr,
9ee1ba47
RR		 4001 priv->hw_setting.rx_buf_size,
4002 PCI_DMA_FROMDEVICE);
b481de9c
ZY		 4003 priv->alloc_rxb_skb--;
4004 dev_kfree_skb(rxq->pool[i].skb);
4005 rxq->pool[i].skb = NULL;
4006 }
4007 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
4008 }
4009
4010 /* Set us so that we have processed and used all buffers, but have
4011 * not restocked the Rx queue with fresh buffers */
4012 rxq->read = rxq->write = 0;
4013 rxq->free_count = 0;
4014 spin_unlock_irqrestore(&rxq->lock, flags);
4015}
4016
4017/* Convert linear signal-to-noise ratio into dB */
4018static u8 ratio2dB[100] = {
4019/* 0 1 2 3 4 5 6 7 8 9 */
4020 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
4021 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
4022 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
4023 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
4024 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
4025 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
4026 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
4027 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
4028 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
4029 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
4030};
4031
4032/* Calculates a relative dB value from a ratio of linear
4033 * (i.e. not dB) signal levels.
4034 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 4035int iwl4965_calc_db_from_ratio(int sig_ratio)
b481de9c 4036{
c899a575
AB		 4037 /* 1000:1 or higher just report as 60 dB */
4038 if (sig_ratio >= 1000)
b481de9c
ZY		 4039 return 60;
4040
c899a575 4041 /* 100:1 or higher, divide by 10 and use table,
b481de9c 4042 * add 20 dB to make up for divide by 10 */
c899a575 4043 if (sig_ratio >= 100)
b481de9c
ZY		 4044 return (20 + (int)ratio2dB[sig_ratio/10]);
4045
4046 /* We shouldn't see this */
4047 if (sig_ratio < 1)
4048 return 0;
4049
4050 /* Use table for ratios 1:1 - 99:1 */
4051 return (int)ratio2dB[sig_ratio];
4052}
4053
4054#define PERFECT_RSSI (-20) /* dBm */
4055#define WORST_RSSI (-95) /* dBm */
4056#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
4057
4058/* Calculate an indication of rx signal quality (a percentage, not dBm!).
4059 * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
4060 * about formulas used below. */
bb8c093b 4061int iwl4965_calc_sig_qual(int rssi_dbm, int noise_dbm)
b481de9c
ZY		 4062{
4063 int sig_qual;
4064 int degradation = PERFECT_RSSI - rssi_dbm;
4065
4066 /* If we get a noise measurement, use signal-to-noise ratio (SNR)
4067 * as indicator; formula is (signal dbm - noise dbm).
4068 * SNR at or above 40 is a great signal (100%).
4069 * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
4070 * Weakest usable signal is usually 10 - 15 dB SNR. */
4071 if (noise_dbm) {
4072 if (rssi_dbm - noise_dbm >= 40)
4073 return 100;
4074 else if (rssi_dbm < noise_dbm)
4075 return 0;
4076 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
4077
4078 /* Else use just the signal level.
4079 * This formula is a least squares fit of data points collected and
4080 * compared with a reference system that had a percentage (%) display
4081 * for signal quality. */
4082 } else
4083 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
4084 (15 * RSSI_RANGE + 62 * degradation)) /
4085 (RSSI_RANGE * RSSI_RANGE);
4086
4087 if (sig_qual > 100)
4088 sig_qual = 100;
4089 else if (sig_qual < 1)
4090 sig_qual = 0;
4091
4092 return sig_qual;
4093}
4094
4095/**
9fbab516 4096 * iwl4965_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 4097 *
4098 * Uses the priv->rx_handlers callback function array to invoke
4099 * the appropriate handlers, including command responses,
4100 * frame-received notifications, and other notifications.
4101 */
c79dd5b5 4102static void iwl4965_rx_handle(struct iwl_priv *priv)
b481de9c 4103{
bb8c093b
CH		 4104 struct iwl4965_rx_mem_buffer *rxb;
4105 struct iwl4965_rx_packet *pkt;
4106 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 4107 u32 r, i;
4108 int reclaim;
4109 unsigned long flags;
5c0eef96 4110 u8 fill_rx = 0;
d68ab680 4111 u32 count = 8;
b481de9c 4112
6440adb5
CB		 4113 /* uCode's read index (stored in shared DRAM) indicates the last Rx
4114 * buffer that the driver may process (last buffer filled by ucode). */
bb8c093b 4115 r = iwl4965_hw_get_rx_read(priv);
b481de9c
ZY		 4116 i = rxq->read;
4117
4118 /* Rx interrupt, but nothing sent from uCode */
4119 if (i == r)
4120 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
4121
5c0eef96
MA		 4122 if (iwl4965_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
4123 fill_rx = 1;
4124
b481de9c
ZY		 4125 while (i != r) {
4126 rxb = rxq->queue[i];
4127
9fbab516 4128 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 4129 * then a bug has been introduced in the queue refilling
4130 * routines -- catch it here */
4131 BUG_ON(rxb == NULL);
4132
4133 rxq->queue[i] = NULL;
4134
4135 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
9ee1ba47 4136 priv->hw_setting.rx_buf_size,
b481de9c 4137 PCI_DMA_FROMDEVICE);
bb8c093b 4138 pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY		 4139
4140 /* Reclaim a command buffer only if this packet is a response
4141 * to a (driver-originated) command.
4142 * If the packet (e.g. Rx frame) originated from uCode,
4143 * there is no command buffer to reclaim.
4144 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4145 * but apparently a few don't get set; catch them here. */
4146 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
4147 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 4148 (pkt->hdr.cmd != REPLY_RX) &&
cfe01709 4149 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 4150 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
4151 (pkt->hdr.cmd != REPLY_TX);
4152
4153 /* Based on type of command response or notification,
4154 * handle those that need handling via function in
bb8c093b 4155 * rx_handlers table. See iwl4965_setup_rx_handlers() */
b481de9c
ZY		 4156 if (priv->rx_handlers[pkt->hdr.cmd]) {
4157 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4158 "r = %d, i = %d, %s, 0x%02x\n", r, i,
4159 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4160 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
4161 } else {
4162 /* No handling needed */
4163 IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
4164 "r %d i %d No handler needed for %s, 0x%02x\n",
4165 r, i, get_cmd_string(pkt->hdr.cmd),
4166 pkt->hdr.cmd);
4167 }
4168
4169 if (reclaim) {
9fbab516 4170 /* Invoke any callbacks, transfer the skb to caller, and
857485c0 4171 * fire off the (possibly) blocking iwl_send_cmd()
b481de9c
ZY		 4172 * as we reclaim the driver command queue */
4173 if (rxb && rxb->skb)
bb8c093b 4174 iwl4965_tx_cmd_complete(priv, rxb);
b481de9c
ZY		 4175 else
4176 IWL_WARNING("Claim null rxb?\n");
4177 }
4178
4179 /* For now we just don't re-use anything. We can tweak this
4180 * later to try and re-use notification packets and SKBs that
4181 * fail to Rx correctly */
4182 if (rxb->skb != NULL) {
4183 priv->alloc_rxb_skb--;
4184 dev_kfree_skb_any(rxb->skb);
4185 rxb->skb = NULL;
4186 }
4187
4188 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
9ee1ba47
RR		 4189 priv->hw_setting.rx_buf_size,
4190 PCI_DMA_FROMDEVICE);
b481de9c
ZY		 4191 spin_lock_irqsave(&rxq->lock, flags);
4192 list_add_tail(&rxb->list, &priv->rxq.rx_used);
4193 spin_unlock_irqrestore(&rxq->lock, flags);
4194 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 4195 /* If there are a lot of unused frames,
4196 * restock the Rx queue so ucode wont assert. */
4197 if (fill_rx) {
4198 count++;
4199 if (count >= 8) {
4200 priv->rxq.read = i;
4201 __iwl4965_rx_replenish(priv);
4202 count = 0;
4203 }
4204 }
b481de9c
ZY		 4205 }
4206
4207 /* Backtrack one entry */
4208 priv->rxq.read = i;
bb8c093b 4209 iwl4965_rx_queue_restock(priv);
b481de9c
ZY		 4210}
4211
6440adb5
CB		 4212/**
4213 * iwl4965_tx_queue_update_write_ptr - Send new write index to hardware
4214 */
c79dd5b5 4215static int iwl4965_tx_queue_update_write_ptr(struct iwl_priv *priv,
bb8c093b 4216 struct iwl4965_tx_queue *txq)
b481de9c
ZY		 4217{
4218 u32 reg = 0;
4219 int rc = 0;
4220 int txq_id = txq->q.id;
4221
4222 if (txq->need_update == 0)
4223 return rc;
4224
4225 /* if we're trying to save power */
4226 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
4227 /* wake up nic if it's powered down ...
4228 * uCode will wake up, and interrupt us again, so next
4229 * time we'll skip this part. */
3395f6e9 4230 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
b481de9c
ZY		 4231
4232 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
4233 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
3395f6e9 4234 iwl_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 4235 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
4236 return rc;
4237 }
4238
4239 /* restore this queue's parameters in nic hardware. */
3395f6e9 4240 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 4241 if (rc)
4242 return rc;
3395f6e9 4243 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
fc4b6853 4244 txq->q.write_ptr | (txq_id << 8));
3395f6e9 4245 iwl_release_nic_access(priv);
b481de9c
ZY		 4246
4247 /* else not in power-save mode, uCode will never sleep when we're
4248 * trying to tx (during RFKILL, we're not trying to tx). */
4249 } else
3395f6e9 4250 iwl_write32(priv, HBUS_TARG_WRPTR,
fc4b6853 4251 txq->q.write_ptr | (txq_id << 8));
b481de9c
ZY		 4252
4253 txq->need_update = 0;
4254
4255 return rc;
4256}
4257
0a6857e7 4258#ifdef CONFIG_IWLWIFI_DEBUG
bb8c093b 4259static void iwl4965_print_rx_config_cmd(struct iwl4965_rxon_cmd *rxon)
b481de9c 4260{
0795af57
JP		 4261 DECLARE_MAC_BUF(mac);
4262
b481de9c 4263 IWL_DEBUG_RADIO("RX CONFIG:\n");
0a6857e7 4264 iwl_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
b481de9c
ZY		 4265 IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4266 IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4267 IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
4268 le32_to_cpu(rxon->filter_flags));
4269 IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4270 IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
4271 rxon->ofdm_basic_rates);
4272 IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
0795af57
JP		 4273 IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
4274 print_mac(mac, rxon->node_addr));
4275 IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
4276 print_mac(mac, rxon->bssid_addr));
b481de9c
ZY		 4277 IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4278}
4279#endif
4280
c79dd5b5 4281static void iwl4965_enable_interrupts(struct iwl_priv *priv)
b481de9c
ZY		 4282{
4283 IWL_DEBUG_ISR("Enabling interrupts\n");
4284 set_bit(STATUS_INT_ENABLED, &priv->status);
3395f6e9 4285 iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
b481de9c
ZY		 4286}
4287
0359facc
MA		 4288/* call this function to flush any scheduled tasklet */
4289static inline void iwl_synchronize_irq(struct iwl_priv *priv)
4290{
4291 /* wait to make sure we flush pedding tasklet*/
4292 synchronize_irq(priv->pci_dev->irq);
4293 tasklet_kill(&priv->irq_tasklet);
4294}
4295
c79dd5b5 4296static inline void iwl4965_disable_interrupts(struct iwl_priv *priv)
b481de9c
ZY		 4297{
4298 clear_bit(STATUS_INT_ENABLED, &priv->status);
4299
4300 /* disable interrupts from uCode/NIC to host */
3395f6e9 4301 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4302
4303 /* acknowledge/clear/reset any interrupts still pending
4304 * from uCode or flow handler (Rx/Tx DMA) */
3395f6e9
TW		 4305 iwl_write32(priv, CSR_INT, 0xffffffff);
4306 iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
b481de9c
ZY		 4307 IWL_DEBUG_ISR("Disabled interrupts\n");
4308}
4309
4310static const char *desc_lookup(int i)
4311{
4312 switch (i) {
4313 case 1:
4314 return "FAIL";
4315 case 2:
4316 return "BAD_PARAM";
4317 case 3:
4318 return "BAD_CHECKSUM";
4319 case 4:
4320 return "NMI_INTERRUPT";
4321 case 5:
4322 return "SYSASSERT";
4323 case 6:
4324 return "FATAL_ERROR";
4325 }
4326
4327 return "UNKNOWN";
4328}
4329
4330#define ERROR_START_OFFSET (1 * sizeof(u32))
4331#define ERROR_ELEM_SIZE (7 * sizeof(u32))
4332
c79dd5b5 4333static void iwl4965_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY		 4334{
4335 u32 data2, line;
4336 u32 desc, time, count, base, data1;
4337 u32 blink1, blink2, ilink1, ilink2;
4338 int rc;
4339
4340 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4341
bb8c093b 4342 if (!iwl4965_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4343 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4344 return;
4345 }
4346
3395f6e9 4347 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 4348 if (rc) {
4349 IWL_WARNING("Can not read from adapter at this time.\n");
4350 return;
4351 }
4352
3395f6e9 4353 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY		 4354
4355 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4356 IWL_ERROR("Start IWL Error Log Dump:\n");
2acae16e 4357 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
b481de9c
ZY		 4358 }
4359
3395f6e9
TW		 4360 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
4361 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
4362 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
4363 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
4364 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
4365 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
4366 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
4367 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
4368 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
b481de9c
ZY		 4369
4370 IWL_ERROR("Desc Time "
4371 "data1 data2 line\n");
4372 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
4373 desc_lookup(desc), desc, time, data1, data2, line);
4374 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
4375 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
4376 ilink1, ilink2);
4377
3395f6e9 4378 iwl_release_nic_access(priv);
b481de9c
ZY		 4379}
4380
4381#define EVENT_START_OFFSET (4 * sizeof(u32))
4382
4383/**
bb8c093b 4384 * iwl4965_print_event_log - Dump error event log to syslog
b481de9c 4385 *
3395f6e9 4386 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
b481de9c 4387 */
c79dd5b5 4388static void iwl4965_print_event_log(struct iwl_priv *priv, u32 start_idx,
b481de9c
ZY		 4389 u32 num_events, u32 mode)
4390{
4391 u32 i;
4392 u32 base; /* SRAM byte address of event log header */
4393 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4394 u32 ptr; /* SRAM byte address of log data */
4395 u32 ev, time, data; /* event log data */
4396
4397 if (num_events == 0)
4398 return;
4399
4400 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4401
4402 if (mode == 0)
4403 event_size = 2 * sizeof(u32);
4404 else
4405 event_size = 3 * sizeof(u32);
4406
4407 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4408
4409 /* "time" is actually "data" for mode 0 (no timestamp).
4410 * place event id # at far right for easier visual parsing. */
4411 for (i = 0; i < num_events; i++) {
3395f6e9 4412 ev = iwl_read_targ_mem(priv, ptr);
b481de9c 4413 ptr += sizeof(u32);
3395f6e9 4414 time = iwl_read_targ_mem(priv, ptr);
b481de9c
ZY		 4415 ptr += sizeof(u32);
4416 if (mode == 0)
4417 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4418 else {
3395f6e9 4419 data = iwl_read_targ_mem(priv, ptr);
b481de9c
ZY		 4420 ptr += sizeof(u32);
4421 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4422 }
4423 }
4424}
4425
c79dd5b5 4426static void iwl4965_dump_nic_event_log(struct iwl_priv *priv)
b481de9c
ZY		 4427{
4428 int rc;
4429 u32 base; /* SRAM byte address of event log header */
4430 u32 capacity; /* event log capacity in # entries */
4431 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
4432 u32 num_wraps; /* # times uCode wrapped to top of log */
4433 u32 next_entry; /* index of next entry to be written by uCode */
4434 u32 size; /* # entries that we'll print */
4435
4436 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 4437 if (!iwl4965_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 4438 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4439 return;
4440 }
4441
3395f6e9 4442 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 4443 if (rc) {
4444 IWL_WARNING("Can not read from adapter at this time.\n");
4445 return;
4446 }
4447
4448 /* event log header */
3395f6e9
TW		 4449 capacity = iwl_read_targ_mem(priv, base);
4450 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
4451 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
4452 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c
ZY		 4453
4454 size = num_wraps ? capacity : next_entry;
4455
4456 /* bail out if nothing in log */
4457 if (size == 0) {
583fab37 4458 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
3395f6e9 4459 iwl_release_nic_access(priv);
b481de9c
ZY		 4460 return;
4461 }
4462
583fab37 4463 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
b481de9c
ZY		 4464 size, num_wraps);
4465
4466 /* if uCode has wrapped back to top of log, start at the oldest entry,
4467 * i.e the next one that uCode would fill. */
4468 if (num_wraps)
bb8c093b 4469 iwl4965_print_event_log(priv, next_entry,
b481de9c
ZY		 4470 capacity - next_entry, mode);
4471
4472 /* (then/else) start at top of log */
bb8c093b 4473 iwl4965_print_event_log(priv, 0, next_entry, mode);
b481de9c 4474
3395f6e9 4475 iwl_release_nic_access(priv);
b481de9c
ZY		 4476}
4477
4478/**
bb8c093b 4479 * iwl4965_irq_handle_error - called for HW or SW error interrupt from card
b481de9c 4480 */
c79dd5b5 4481static void iwl4965_irq_handle_error(struct iwl_priv *priv)
b481de9c 4482{
bb8c093b 4483 /* Set the FW error flag -- cleared on iwl4965_down */
b481de9c
ZY		 4484 set_bit(STATUS_FW_ERROR, &priv->status);
4485
4486 /* Cancel currently queued command. */
4487 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4488
0a6857e7
TW		 4489#ifdef CONFIG_IWLWIFI_DEBUG
4490 if (iwl_debug_level & IWL_DL_FW_ERRORS) {
bb8c093b
CH		 4491 iwl4965_dump_nic_error_log(priv);
4492 iwl4965_dump_nic_event_log(priv);
4493 iwl4965_print_rx_config_cmd(&priv->staging_rxon);
b481de9c
ZY		 4494 }
4495#endif
4496
4497 wake_up_interruptible(&priv->wait_command_queue);
4498
4499 /* Keep the restart process from trying to send host
4500 * commands by clearing the INIT status bit */
4501 clear_bit(STATUS_READY, &priv->status);
4502
4503 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4504 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4505 "Restarting adapter due to uCode error.\n");
4506
3109ece1 4507 if (iwl_is_associated(priv)) {
b481de9c
ZY		 4508 memcpy(&priv->recovery_rxon, &priv->active_rxon,
4509 sizeof(priv->recovery_rxon));
4510 priv->error_recovering = 1;
4511 }
4512 queue_work(priv->workqueue, &priv->restart);
4513 }
4514}
4515
c79dd5b5 4516static void iwl4965_error_recovery(struct iwl_priv *priv)
b481de9c
ZY		 4517{
4518 unsigned long flags;
4519
4520 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4521 sizeof(priv->staging_rxon));
4522 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 4523 iwl4965_commit_rxon(priv);
b481de9c 4524
bb8c093b 4525 iwl4965_rxon_add_station(priv, priv->bssid, 1);
b481de9c
ZY		 4526
4527 spin_lock_irqsave(&priv->lock, flags);
4528 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4529 priv->error_recovering = 0;
4530 spin_unlock_irqrestore(&priv->lock, flags);
4531}
4532
c79dd5b5 4533static void iwl4965_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY		 4534{
4535 u32 inta, handled = 0;
4536 u32 inta_fh;
4537 unsigned long flags;
0a6857e7 4538#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 4539 u32 inta_mask;
4540#endif
4541
4542 spin_lock_irqsave(&priv->lock, flags);
4543
4544 /* Ack/clear/reset pending uCode interrupts.
4545 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4546 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW		 4547 inta = iwl_read32(priv, CSR_INT);
4548 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 4549
4550 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4551 * Any new interrupts that happen after this, either while we're
4552 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW		 4553 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
4554 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 4555
0a6857e7
TW		 4556#ifdef CONFIG_IWLWIFI_DEBUG
4557 if (iwl_debug_level & IWL_DL_ISR) {
9fbab516 4558 /* just for debug */
3395f6e9 4559 inta_mask = iwl_read32(priv, CSR_INT_MASK);
b481de9c
ZY		 4560 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4561 inta, inta_mask, inta_fh);
4562 }
4563#endif
4564
4565 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4566 * atomic, make sure that inta covers all the interrupts that
4567 * we've discovered, even if FH interrupt came in just after
4568 * reading CSR_INT. */
6f83eaa1 4569 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 4570 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 4571 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY		 4572 inta |= CSR_INT_BIT_FH_TX;
4573
4574 /* Now service all interrupt bits discovered above. */
4575 if (inta & CSR_INT_BIT_HW_ERR) {
4576 IWL_ERROR("Microcode HW error detected. Restarting.\n");
4577
4578 /* Tell the device to stop sending interrupts */
bb8c093b 4579 iwl4965_disable_interrupts(priv);
b481de9c 4580
bb8c093b 4581 iwl4965_irq_handle_error(priv);
b481de9c
ZY		 4582
4583 handled |= CSR_INT_BIT_HW_ERR;
4584
4585 spin_unlock_irqrestore(&priv->lock, flags);
4586
4587 return;
4588 }
4589
0a6857e7
TW		 4590#ifdef CONFIG_IWLWIFI_DEBUG
4591 if (iwl_debug_level & (IWL_DL_ISR)) {
b481de9c 4592 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e
JP		 4593 if (inta & CSR_INT_BIT_SCD)
4594 IWL_DEBUG_ISR("Scheduler finished to transmit "
4595 "the frame/frames.\n");
b481de9c
ZY		 4596
4597 /* Alive notification via Rx interrupt will do the real work */
4598 if (inta & CSR_INT_BIT_ALIVE)
4599 IWL_DEBUG_ISR("Alive interrupt\n");
4600 }
4601#endif
4602 /* Safely ignore these bits for debug checks below */
25c03d8e 4603 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 4604
9fbab516 4605 /* HW RF KILL switch toggled */
b481de9c
ZY		 4606 if (inta & CSR_INT_BIT_RF_KILL) {
4607 int hw_rf_kill = 0;
3395f6e9 4608 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 4609 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4610 hw_rf_kill = 1;
4611
4612 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4613 "RF_KILL bit toggled to %s.\n",
4614 hw_rf_kill ? "disable radio":"enable radio");
4615
4616 /* Queue restart only if RF_KILL switch was set to "kill"
4617 * when we loaded driver, and is now set to "enable".
4618 * After we're Alive, RF_KILL gets handled by
3230455d 4619 * iwl4965_rx_card_state_notif() */
53e49093
ZY		 4620 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4621 clear_bit(STATUS_RF_KILL_HW, &priv->status);
b481de9c 4622 queue_work(priv->workqueue, &priv->restart);
53e49093 4623 }
b481de9c
ZY		 4624
4625 handled |= CSR_INT_BIT_RF_KILL;
4626 }
4627
9fbab516 4628 /* Chip got too hot and stopped itself */
b481de9c
ZY		 4629 if (inta & CSR_INT_BIT_CT_KILL) {
4630 IWL_ERROR("Microcode CT kill error detected.\n");
4631 handled |= CSR_INT_BIT_CT_KILL;
4632 }
4633
4634 /* Error detected by uCode */
4635 if (inta & CSR_INT_BIT_SW_ERR) {
4636 IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
4637 inta);
bb8c093b 4638 iwl4965_irq_handle_error(priv);
b481de9c
ZY		 4639 handled |= CSR_INT_BIT_SW_ERR;
4640 }
4641
4642 /* uCode wakes up after power-down sleep */
4643 if (inta & CSR_INT_BIT_WAKEUP) {
4644 IWL_DEBUG_ISR("Wakeup interrupt\n");
bb8c093b
CH		 4645 iwl4965_rx_queue_update_write_ptr(priv, &priv->rxq);
4646 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4647 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4648 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4649 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4650 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4651 iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 4652
4653 handled |= CSR_INT_BIT_WAKEUP;
4654 }
4655
4656 /* All uCode command responses, including Tx command responses,
4657 * Rx "responses" (frame-received notification), and other
4658 * notifications from uCode come through here*/
4659 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 4660 iwl4965_rx_handle(priv);
b481de9c
ZY		 4661 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4662 }
4663
4664 if (inta & CSR_INT_BIT_FH_TX) {
4665 IWL_DEBUG_ISR("Tx interrupt\n");
4666 handled |= CSR_INT_BIT_FH_TX;
4667 }
4668
4669 if (inta & ~handled)
4670 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4671
4672 if (inta & ~CSR_INI_SET_MASK) {
4673 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4674 inta & ~CSR_INI_SET_MASK);
4675 IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
4676 }
4677
4678 /* Re-enable all interrupts */
0359facc
MA		 4679 /* only Re-enable if diabled by irq */
4680 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4681 iwl4965_enable_interrupts(priv);
b481de9c 4682
0a6857e7
TW		 4683#ifdef CONFIG_IWLWIFI_DEBUG
4684 if (iwl_debug_level & (IWL_DL_ISR)) {
3395f6e9
TW		 4685 inta = iwl_read32(priv, CSR_INT);
4686 inta_mask = iwl_read32(priv, CSR_INT_MASK);
4687 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4688 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4689 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4690 }
4691#endif
4692 spin_unlock_irqrestore(&priv->lock, flags);
4693}
4694
bb8c093b 4695static irqreturn_t iwl4965_isr(int irq, void *data)
b481de9c 4696{
c79dd5b5 4697 struct iwl_priv *priv = data;
b481de9c
ZY		 4698 u32 inta, inta_mask;
4699 u32 inta_fh;
4700 if (!priv)
4701 return IRQ_NONE;
4702
4703 spin_lock(&priv->lock);
4704
4705 /* Disable (but don't clear!) interrupts here to avoid
4706 * back-to-back ISRs and sporadic interrupts from our NIC.
4707 * If we have something to service, the tasklet will re-enable ints.
4708 * If we *don't* have something, we'll re-enable before leaving here. */
3395f6e9
TW		 4709 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
4710 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 4711
4712 /* Discover which interrupts are active/pending */
3395f6e9
TW		 4713 inta = iwl_read32(priv, CSR_INT);
4714 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 4715
4716 /* Ignore interrupt if there's nothing in NIC to service.
4717 * This may be due to IRQ shared with another device,
4718 * or due to sporadic interrupts thrown from our NIC. */
4719 if (!inta && !inta_fh) {
4720 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4721 goto none;
4722 }
4723
4724 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
66fbb541
ON		 4725 /* Hardware disappeared. It might have already raised
4726 * an interrupt */
b481de9c 4727 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
66fbb541 4728 goto unplugged;
b481de9c
ZY		 4729 }
4730
4731 IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4732 inta, inta_mask, inta_fh);
4733
25c03d8e
JP		 4734 inta &= ~CSR_INT_BIT_SCD;
4735
bb8c093b 4736 /* iwl4965_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP		 4737 if (likely(inta || inta_fh))
4738 tasklet_schedule(&priv->irq_tasklet);
b481de9c 4739
66fbb541
ON		 4740 unplugged:
4741 spin_unlock(&priv->lock);
b481de9c
ZY		 4742 return IRQ_HANDLED;
4743
4744 none:
4745 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA		 4746 /* only Re-enable if diabled by irq */
4747 if (test_bit(STATUS_INT_ENABLED, &priv->status))
4748 iwl4965_enable_interrupts(priv);
b481de9c
ZY		 4749 spin_unlock(&priv->lock);
4750 return IRQ_NONE;
4751}
4752
b481de9c
ZY		 4753/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4754 * sending probe req. This should be set long enough to hear probe responses
4755 * from more than one AP. */
4756#define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
4757#define IWL_ACTIVE_DWELL_TIME_52 (10)
4758
4759/* For faster active scanning, scan will move to the next channel if fewer than
4760 * PLCP_QUIET_THRESH packets are heard on this channel within
4761 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
4762 * time if it's a quiet channel (nothing responded to our probe, and there's
4763 * no other traffic).
4764 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4765#define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
4766#define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
4767
4768/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4769 * Must be set longer than active dwell time.
4770 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4771#define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
4772#define IWL_PASSIVE_DWELL_TIME_52 (10)
4773#define IWL_PASSIVE_DWELL_BASE (100)
4774#define IWL_CHANNEL_TUNE_TIME 5
4775
c79dd5b5 4776static inline u16 iwl4965_get_active_dwell_time(struct iwl_priv *priv,
8318d78a 4777 enum ieee80211_band band)
b481de9c 4778{
8318d78a 4779 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4780 return IWL_ACTIVE_DWELL_TIME_52;
4781 else
4782 return IWL_ACTIVE_DWELL_TIME_24;
4783}
4784
c79dd5b5 4785static u16 iwl4965_get_passive_dwell_time(struct iwl_priv *priv,
8318d78a 4786 enum ieee80211_band band)
b481de9c 4787{
8318d78a
JB		 4788 u16 active = iwl4965_get_active_dwell_time(priv, band);
4789 u16 passive = (band != IEEE80211_BAND_5GHZ) ?
b481de9c
ZY		 4790 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4791 IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4792
3109ece1 4793 if (iwl_is_associated(priv)) {
b481de9c
ZY		 4794 /* If we're associated, we clamp the maximum passive
4795 * dwell time to be 98% of the beacon interval (minus
4796 * 2 * channel tune time) */
4797 passive = priv->beacon_int;
4798 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4799 passive = IWL_PASSIVE_DWELL_BASE;
4800 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4801 }
4802
4803 if (passive <= active)
4804 passive = active + 1;
4805
4806 return passive;
4807}
4808
c79dd5b5 4809static int iwl4965_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 4810 enum ieee80211_band band,
b481de9c 4811 u8 is_active, u8 direct_mask,
bb8c093b 4812 struct iwl4965_scan_channel *scan_ch)
b481de9c
ZY		 4813{
4814 const struct ieee80211_channel *channels = NULL;
8318d78a 4815 const struct ieee80211_supported_band *sband;
bf85ea4f 4816 const struct iwl_channel_info *ch_info;
b481de9c
ZY		 4817 u16 passive_dwell = 0;
4818 u16 active_dwell = 0;
4819 int added, i;
4820
8318d78a
JB		 4821 sband = iwl4965_get_hw_mode(priv, band);
4822 if (!sband)
b481de9c
ZY		 4823 return 0;
4824
8318d78a 4825 channels = sband->channels;
b481de9c 4826
8318d78a
JB		 4827 active_dwell = iwl4965_get_active_dwell_time(priv, band);
4828 passive_dwell = iwl4965_get_passive_dwell_time(priv, band);
b481de9c 4829
8318d78a
JB		 4830 for (i = 0, added = 0; i < sband->n_channels; i++) {
4831 if (ieee80211_frequency_to_channel(channels[i].center_freq) ==
b481de9c 4832 le16_to_cpu(priv->active_rxon.channel)) {
3109ece1 4833 if (iwl_is_associated(priv)) {
b481de9c
ZY		 4834 IWL_DEBUG_SCAN
4835 ("Skipping current channel %d\n",
4836 le16_to_cpu(priv->active_rxon.channel));
4837 continue;
4838 }
4839 } else if (priv->only_active_channel)
4840 continue;
4841
8318d78a 4842 scan_ch->channel = ieee80211_frequency_to_channel(channels[i].center_freq);
b481de9c 4843
8622e705 4844 ch_info = iwl_get_channel_info(priv, band,
9fbab516 4845 scan_ch->channel);
b481de9c
ZY		 4846 if (!is_channel_valid(ch_info)) {
4847 IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
4848 scan_ch->channel);
4849 continue;
4850 }
4851
4852 if (!is_active || is_channel_passive(ch_info) ||
8318d78a 4853 (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
b481de9c
ZY		 4854 scan_ch->type = 0; /* passive */
4855 else
4856 scan_ch->type = 1; /* active */
4857
4858 if (scan_ch->type & 1)
4859 scan_ch->type |= (direct_mask << 1);
4860
4861 if (is_channel_narrow(ch_info))
4862 scan_ch->type |= (1 << 7);
4863
4864 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4865 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4866
9fbab516 4867 /* Set txpower levels to defaults */
b481de9c
ZY		 4868 scan_ch->tpc.dsp_atten = 110;
4869 /* scan_pwr_info->tpc.dsp_atten; */
4870
4871 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 4872 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4873 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4874 else {
4875 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4876 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 4877 * power level:
8a1b0245 4878 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY		 4879 */
4880 }
4881
4882 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
4883 scan_ch->channel,
4884 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
4885 (scan_ch->type & 1) ?
4886 active_dwell : passive_dwell);
4887
4888 scan_ch++;
4889 added++;
4890 }
4891
4892 IWL_DEBUG_SCAN("total channels to scan %d \n", added);
4893 return added;
4894}
4895
c79dd5b5 4896static void iwl4965_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY		 4897 struct ieee80211_rate *rates)
4898{
4899 int i;
4900
4901 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB		 4902 rates[i].bitrate = iwl4965_rates[i].ieee * 5;
4903 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4904 rates[i].hw_value_short = i;
4905 rates[i].flags = 0;
4906 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 4907 /*
8318d78a 4908 * If CCK != 1M then set short preamble rate flag.
b481de9c 4909 */
35cdeaf4
TW		 4910 rates[i].flags |=
4911 (iwl4965_rates[i].plcp == IWL_RATE_1M_PLCP) ?
4912 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 4913 }
b481de9c 4914 }
b481de9c
ZY		 4915}
4916
4917/**
bb8c093b 4918 * iwl4965_init_geos - Initialize mac80211's geo/channel info based from eeprom
b481de9c 4919 */
bf85ea4f 4920int iwl4965_init_geos(struct iwl_priv *priv)
b481de9c 4921{
bf85ea4f 4922 struct iwl_channel_info *ch;
8211ef78 4923 struct ieee80211_supported_band *sband;
b481de9c
ZY		 4924 struct ieee80211_channel *channels;
4925 struct ieee80211_channel *geo_ch;
4926 struct ieee80211_rate *rates;
4927 int i = 0;
b481de9c 4928
8318d78a
JB		 4929 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
4930 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
b481de9c
ZY		 4931 IWL_DEBUG_INFO("Geography modes already initialized.\n");
4932 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4933 return 0;
4934 }
4935
b481de9c
ZY		 4936 channels = kzalloc(sizeof(struct ieee80211_channel) *
4937 priv->channel_count, GFP_KERNEL);
8318d78a 4938 if (!channels)
b481de9c 4939 return -ENOMEM;
b481de9c 4940
8211ef78 4941 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
b481de9c
ZY		 4942 GFP_KERNEL);
4943 if (!rates) {
b481de9c
ZY		 4944 kfree(channels);
4945 return -ENOMEM;
4946 }
4947
b481de9c 4948 /* 5.2GHz channels start after the 2.4GHz channels */
8211ef78 4949 sband = &priv->bands[IEEE80211_BAND_5GHZ];
bf85ea4f 4950 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
8211ef78
TW		 4951 /* just OFDM */
4952 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
4953 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
8318d78a 4954
1ea87396 4955 iwl4965_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ);
78330fdd 4956
8211ef78
TW		 4957 sband = &priv->bands[IEEE80211_BAND_2GHZ];
4958 sband->channels = channels;
4959 /* OFDM & CCK */
4960 sband->bitrates = rates;
4961 sband->n_bitrates = IWL_RATE_COUNT;
b481de9c 4962
1ea87396 4963 iwl4965_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ);
78330fdd 4964
b481de9c
ZY		 4965 priv->ieee_channels = channels;
4966 priv->ieee_rates = rates;
4967
bb8c093b 4968 iwl4965_init_hw_rates(priv, rates);
b481de9c 4969
8211ef78 4970 for (i = 0; i < priv->channel_count; i++) {
b481de9c
ZY		 4971 ch = &priv->channel_info[i];
4972
8211ef78
TW		 4973 /* FIXME: might be removed if scan is OK */
4974 if (!is_channel_valid(ch))
b481de9c 4975 continue;
b481de9c 4976
8211ef78
TW		 4977 if (is_channel_a_band(ch))
4978 sband = &priv->bands[IEEE80211_BAND_5GHZ];
4979 else
4980 sband = &priv->bands[IEEE80211_BAND_2GHZ];
b481de9c 4981
8211ef78
TW		 4982 geo_ch = &sband->channels[sband->n_channels++];
4983
4984 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
8318d78a
JB		 4985 geo_ch->max_power = ch->max_power_avg;
4986 geo_ch->max_antenna_gain = 0xff;
7b72304d 4987 geo_ch->hw_value = ch->channel;
b481de9c
ZY		 4988
4989 if (is_channel_valid(ch)) {
8318d78a
JB		 4990 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
4991 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
b481de9c 4992
8318d78a
JB		 4993 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
4994 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
b481de9c
ZY		 4995
4996 if (ch->flags & EEPROM_CHANNEL_RADAR)
8318d78a 4997 geo_ch->flags |= IEEE80211_CHAN_RADAR;
b481de9c
ZY		 4998
4999 if (ch->max_power_avg > priv->max_channel_txpower_limit)
5000 priv->max_channel_txpower_limit =
5001 ch->max_power_avg;
8211ef78 5002 } else {
8318d78a 5003 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
8211ef78
TW		 5004 }
5005
5006 /* Save flags for reg domain usage */
5007 geo_ch->orig_flags = geo_ch->flags;
5008
5009 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
5010 ch->channel, geo_ch->center_freq,
5011 is_channel_a_band(ch) ? "5.2" : "2.4",
5012 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
5013 "restricted" : "valid",
5014 geo_ch->flags);
b481de9c
ZY		 5015 }
5016
82b9a121
TW		 5017 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
5018 priv->cfg->sku & IWL_SKU_A) {
b481de9c
ZY		 5019 printk(KERN_INFO DRV_NAME
5020 ": Incorrectly detected BG card as ABG. Please send "
5021 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
5022 priv->pci_dev->device, priv->pci_dev->subsystem_device);
82b9a121 5023 priv->cfg->sku &= ~IWL_SKU_A;
b481de9c
ZY		 5024 }
5025
5026 printk(KERN_INFO DRV_NAME
5027 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
8318d78a
JB		 5028 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
5029 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
b481de9c 5030
e0e0a67e
JL		 5031 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
5032 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
5033 &priv->bands[IEEE80211_BAND_2GHZ];
5034 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
5035 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
5036 &priv->bands[IEEE80211_BAND_5GHZ];
b481de9c 5037
b481de9c
ZY		 5038 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
5039
5040 return 0;
5041}
5042
849e0dce
RC		 5043/*
5044 * iwl4965_free_geos - undo allocations in iwl4965_init_geos
5045 */
bf85ea4f 5046void iwl4965_free_geos(struct iwl_priv *priv)
849e0dce 5047{
849e0dce
RC		 5048 kfree(priv->ieee_channels);
5049 kfree(priv->ieee_rates);
5050 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5051}
5052
b481de9c
ZY		 5053/******************************************************************************
5054 *
5055 * uCode download functions
5056 *
5057 ******************************************************************************/
5058
c79dd5b5 5059static void iwl4965_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 5060{
98c92211
TW		 5061 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5062 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5063 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5064 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5065 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5066 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 5067}
5068
5069/**
bb8c093b 5070 * iwl4965_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5071 * looking at all data.
5072 */
c79dd5b5 5073static int iwl4965_verify_inst_full(struct iwl_priv *priv, __le32 *image,
9fbab516 5074 u32 len)
b481de9c
ZY		 5075{
5076 u32 val;
5077 u32 save_len = len;
5078 int rc = 0;
5079 u32 errcnt;
5080
5081 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5082
3395f6e9 5083 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 5084 if (rc)
5085 return rc;
5086
3395f6e9 5087 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
b481de9c
ZY		 5088
5089 errcnt = 0;
5090 for (; len > 0; len -= sizeof(u32), image++) {
5091 /* read data comes through single port, auto-incr addr */
5092 /* NOTE: Use the debugless read so we don't flood kernel log
5093 * if IWL_DL_IO is set */
3395f6e9 5094 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5095 if (val != le32_to_cpu(*image)) {
5096 IWL_ERROR("uCode INST section is invalid at "
5097 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5098 save_len - len, val, le32_to_cpu(*image));
5099 rc = -EIO;
5100 errcnt++;
5101 if (errcnt >= 20)
5102 break;
5103 }
5104 }
5105
3395f6e9 5106 iwl_release_nic_access(priv);
b481de9c
ZY		 5107
5108 if (!errcnt)
5109 IWL_DEBUG_INFO
5110 ("ucode image in INSTRUCTION memory is good\n");
5111
5112 return rc;
5113}
5114
5115
5116/**
bb8c093b 5117 * iwl4965_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY		 5118 * using sample data 100 bytes apart. If these sample points are good,
5119 * it's a pretty good bet that everything between them is good, too.
5120 */
c79dd5b5 5121static int iwl4965_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY		 5122{
5123 u32 val;
5124 int rc = 0;
5125 u32 errcnt = 0;
5126 u32 i;
5127
5128 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5129
3395f6e9 5130 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 5131 if (rc)
5132 return rc;
5133
5134 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5135 /* read data comes through single port, auto-incr addr */
5136 /* NOTE: Use the debugless read so we don't flood kernel log
5137 * if IWL_DL_IO is set */
3395f6e9 5138 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
b481de9c 5139 i + RTC_INST_LOWER_BOUND);
3395f6e9 5140 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY		 5141 if (val != le32_to_cpu(*image)) {
5142#if 0 /* Enable this if you want to see details */
5143 IWL_ERROR("uCode INST section is invalid at "
5144 "offset 0x%x, is 0x%x, s/b 0x%x\n",
5145 i, val, *image);
5146#endif
5147 rc = -EIO;
5148 errcnt++;
5149 if (errcnt >= 3)
5150 break;
5151 }
5152 }
5153
3395f6e9 5154 iwl_release_nic_access(priv);
b481de9c
ZY		 5155
5156 return rc;
5157}
5158
5159
5160/**
bb8c093b 5161 * iwl4965_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY		 5162 * and verify its contents
5163 */
c79dd5b5 5164static int iwl4965_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY		 5165{
5166 __le32 *image;
5167 u32 len;
5168 int rc = 0;
5169
5170 /* Try bootstrap */
5171 image = (__le32 *)priv->ucode_boot.v_addr;
5172 len = priv->ucode_boot.len;
bb8c093b 5173 rc = iwl4965_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5174 if (rc == 0) {
5175 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5176 return 0;
5177 }
5178
5179 /* Try initialize */
5180 image = (__le32 *)priv->ucode_init.v_addr;
5181 len = priv->ucode_init.len;
bb8c093b 5182 rc = iwl4965_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5183 if (rc == 0) {
5184 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5185 return 0;
5186 }
5187
5188 /* Try runtime/protocol */
5189 image = (__le32 *)priv->ucode_code.v_addr;
5190 len = priv->ucode_code.len;
bb8c093b 5191 rc = iwl4965_verify_inst_sparse(priv, image, len);
b481de9c
ZY		 5192 if (rc == 0) {
5193 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5194 return 0;
5195 }
5196
5197 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5198
9fbab516
BC		 5199 /* Since nothing seems to match, show first several data entries in
5200 * instruction SRAM, so maybe visual inspection will give a clue.
5201 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY		 5202 image = (__le32 *)priv->ucode_boot.v_addr;
5203 len = priv->ucode_boot.len;
bb8c093b 5204 rc = iwl4965_verify_inst_full(priv, image, len);
b481de9c
ZY		 5205
5206 return rc;
5207}
5208
5209
5210/* check contents of special bootstrap uCode SRAM */
c79dd5b5 5211static int iwl4965_verify_bsm(struct iwl_priv *priv)
b481de9c
ZY		 5212{
5213 __le32 *image = priv->ucode_boot.v_addr;
5214 u32 len = priv->ucode_boot.len;
5215 u32 reg;
5216 u32 val;
5217
5218 IWL_DEBUG_INFO("Begin verify bsm\n");
5219
5220 /* verify BSM SRAM contents */
3395f6e9 5221 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
b481de9c
ZY		 5222 for (reg = BSM_SRAM_LOWER_BOUND;
5223 reg < BSM_SRAM_LOWER_BOUND + len;
5224 reg += sizeof(u32), image ++) {
3395f6e9 5225 val = iwl_read_prph(priv, reg);
b481de9c
ZY		 5226 if (val != le32_to_cpu(*image)) {
5227 IWL_ERROR("BSM uCode verification failed at "
5228 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5229 BSM_SRAM_LOWER_BOUND,
5230 reg - BSM_SRAM_LOWER_BOUND, len,
5231 val, le32_to_cpu(*image));
5232 return -EIO;
5233 }
5234 }
5235
5236 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5237
5238 return 0;
5239}
5240
5241/**
bb8c093b 5242 * iwl4965_load_bsm - Load bootstrap instructions
b481de9c
ZY		 5243 *
5244 * BSM operation:
5245 *
5246 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5247 * in special SRAM that does not power down during RFKILL. When powering back
5248 * up after power-saving sleeps (or during initial uCode load), the BSM loads
5249 * the bootstrap program into the on-board processor, and starts it.
5250 *
5251 * The bootstrap program loads (via DMA) instructions and data for a new
5252 * program from host DRAM locations indicated by the host driver in the
5253 * BSM_DRAM_* registers. Once the new program is loaded, it starts
5254 * automatically.
5255 *
5256 * When initializing the NIC, the host driver points the BSM to the
5257 * "initialize" uCode image. This uCode sets up some internal data, then
5258 * notifies host via "initialize alive" that it is complete.
5259 *
5260 * The host then replaces the BSM_DRAM_* pointer values to point to the
5261 * normal runtime uCode instructions and a backup uCode data cache buffer
5262 * (filled initially with starting data values for the on-board processor),
5263 * then triggers the "initialize" uCode to load and launch the runtime uCode,
5264 * which begins normal operation.
5265 *
5266 * When doing a power-save shutdown, runtime uCode saves data SRAM into
5267 * the backup data cache in DRAM before SRAM is powered down.
5268 *
5269 * When powering back up, the BSM loads the bootstrap program. This reloads
5270 * the runtime uCode instructions and the backup data cache into SRAM,
5271 * and re-launches the runtime uCode from where it left off.
5272 */
c79dd5b5 5273static int iwl4965_load_bsm(struct iwl_priv *priv)
b481de9c
ZY		 5274{
5275 __le32 *image = priv->ucode_boot.v_addr;
5276 u32 len = priv->ucode_boot.len;
5277 dma_addr_t pinst;
5278 dma_addr_t pdata;
5279 u32 inst_len;
5280 u32 data_len;
5281 int rc;
5282 int i;
5283 u32 done;
5284 u32 reg_offset;
5285
5286 IWL_DEBUG_INFO("Begin load bsm\n");
5287
5288 /* make sure bootstrap program is no larger than BSM's SRAM size */
5289 if (len > IWL_MAX_BSM_SIZE)
5290 return -EINVAL;
5291
5292 /* Tell bootstrap uCode where to find the "Initialize" uCode
9fbab516 5293 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
bb8c093b 5294 * NOTE: iwl4965_initialize_alive_start() will replace these values,
b481de9c
ZY		 5295 * after the "initialize" uCode has run, to point to
5296 * runtime/protocol instructions and backup data cache. */
5297 pinst = priv->ucode_init.p_addr >> 4;
5298 pdata = priv->ucode_init_data.p_addr >> 4;
5299 inst_len = priv->ucode_init.len;
5300 data_len = priv->ucode_init_data.len;
5301
3395f6e9 5302 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 5303 if (rc)
5304 return rc;
5305
3395f6e9
TW		 5306 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5307 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5308 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5309 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
b481de9c
ZY		 5310
5311 /* Fill BSM memory with bootstrap instructions */
5312 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5313 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5314 reg_offset += sizeof(u32), image++)
3395f6e9 5315 _iwl_write_prph(priv, reg_offset,
b481de9c
ZY		 5316 le32_to_cpu(*image));
5317
bb8c093b 5318 rc = iwl4965_verify_bsm(priv);
b481de9c 5319 if (rc) {
3395f6e9 5320 iwl_release_nic_access(priv);
b481de9c
ZY		 5321 return rc;
5322 }
5323
5324 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
3395f6e9
TW		 5325 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5326 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
b481de9c 5327 RTC_INST_LOWER_BOUND);
3395f6e9 5328 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
b481de9c
ZY		 5329
5330 /* Load bootstrap code into instruction SRAM now,
5331 * to prepare to load "initialize" uCode */
3395f6e9 5332 iwl_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5333 BSM_WR_CTRL_REG_BIT_START);
5334
5335 /* Wait for load of bootstrap uCode to finish */
5336 for (i = 0; i < 100; i++) {
3395f6e9 5337 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
b481de9c
ZY		 5338 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5339 break;
5340 udelay(10);
5341 }
5342 if (i < 100)
5343 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5344 else {
5345 IWL_ERROR("BSM write did not complete!\n");
5346 return -EIO;
5347 }
5348
5349 /* Enable future boot loads whenever power management unit triggers it
5350 * (e.g. when powering back up after power-save shutdown) */
3395f6e9 5351 iwl_write_prph(priv, BSM_WR_CTRL_REG,
b481de9c
ZY		 5352 BSM_WR_CTRL_REG_BIT_START_EN);
5353
3395f6e9 5354 iwl_release_nic_access(priv);
b481de9c
ZY		 5355
5356 return 0;
5357}
5358
c79dd5b5 5359static void iwl4965_nic_start(struct iwl_priv *priv)
b481de9c
ZY		 5360{
5361 /* Remove all resets to allow NIC to operate */
3395f6e9 5362 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY		 5363}
5364
90e759d1 5365
b481de9c 5366/**
bb8c093b 5367 * iwl4965_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 5368 *
5369 * Copy into buffers for card to fetch via bus-mastering
5370 */
c79dd5b5 5371static int iwl4965_read_ucode(struct iwl_priv *priv)
b481de9c 5372{
bb8c093b 5373 struct iwl4965_ucode *ucode;
90e759d1 5374 int ret;
b481de9c 5375 const struct firmware *ucode_raw;
4bf775cd 5376 const char *name = priv->cfg->fw_name;
b481de9c
ZY		 5377 u8 *src;
5378 size_t len;
5379 u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
5380
5381 /* Ask kernel firmware_class module to get the boot firmware off disk.
5382 * request_firmware() is synchronous, file is in memory on return. */
90e759d1
TW		 5383 ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
5384 if (ret < 0) {
5385 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5386 name, ret);
b481de9c
ZY		 5387 goto error;
5388 }
5389
5390 IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5391 name, ucode_raw->size);
5392
5393 /* Make sure that we got at least our header! */
5394 if (ucode_raw->size < sizeof(*ucode)) {
5395 IWL_ERROR("File size way too small!\n");
90e759d1 5396 ret = -EINVAL;
b481de9c
ZY		 5397 goto err_release;
5398 }
5399
5400 /* Data from ucode file: header followed by uCode images */
5401 ucode = (void *)ucode_raw->data;
5402
5403 ver = le32_to_cpu(ucode->ver);
5404 inst_size = le32_to_cpu(ucode->inst_size);
5405 data_size = le32_to_cpu(ucode->data_size);
5406 init_size = le32_to_cpu(ucode->init_size);
5407 init_data_size = le32_to_cpu(ucode->init_data_size);
5408 boot_size = le32_to_cpu(ucode->boot_size);
5409
5410 IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
5411 IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n",
5412 inst_size);
5413 IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n",
5414 data_size);
5415 IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n",
5416 init_size);
5417 IWL_DEBUG_INFO("f/w package hdr init data size = %u\n",
5418 init_data_size);
5419 IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n",
5420 boot_size);
5421
5422 /* Verify size of file vs. image size info in file's header */
5423 if (ucode_raw->size < sizeof(*ucode) +
5424 inst_size + data_size + init_size +
5425 init_data_size + boot_size) {
5426
5427 IWL_DEBUG_INFO("uCode file size %d too small\n",
5428 (int)ucode_raw->size);
90e759d1 5429 ret = -EINVAL;
b481de9c
ZY		 5430 goto err_release;
5431 }
5432
5433 /* Verify that uCode images will fit in card's SRAM */
5434 if (inst_size > IWL_MAX_INST_SIZE) {
90e759d1
TW		 5435 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5436 inst_size);
5437 ret = -EINVAL;
b481de9c
ZY		 5438 goto err_release;
5439 }
5440
5441 if (data_size > IWL_MAX_DATA_SIZE) {
90e759d1
TW		 5442 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5443 data_size);
5444 ret = -EINVAL;
b481de9c
ZY		 5445 goto err_release;
5446 }
5447 if (init_size > IWL_MAX_INST_SIZE) {
5448 IWL_DEBUG_INFO
90e759d1
TW		 5449 ("uCode init instr len %d too large to fit in\n",
5450 init_size);
5451 ret = -EINVAL;
b481de9c
ZY		 5452 goto err_release;
5453 }
5454 if (init_data_size > IWL_MAX_DATA_SIZE) {
5455 IWL_DEBUG_INFO
90e759d1
TW		 5456 ("uCode init data len %d too large to fit in\n",
5457 init_data_size);
5458 ret = -EINVAL;
b481de9c
ZY		 5459 goto err_release;
5460 }
5461 if (boot_size > IWL_MAX_BSM_SIZE) {
5462 IWL_DEBUG_INFO
90e759d1
TW		 5463 ("uCode boot instr len %d too large to fit in\n",
5464 boot_size);
5465 ret = -EINVAL;
b481de9c
ZY		 5466 goto err_release;
5467 }
5468
5469 /* Allocate ucode buffers for card's bus-master loading ... */
5470
5471 /* Runtime instructions and 2 copies of data:
5472 * 1) unmodified from disk
5473 * 2) backup cache for save/restore during power-downs */
5474 priv->ucode_code.len = inst_size;
98c92211 5475 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 5476
5477 priv->ucode_data.len = data_size;
98c92211 5478 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 5479
5480 priv->ucode_data_backup.len = data_size;
98c92211 5481 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c
ZY		 5482
5483 /* Initialization instructions and data */
90e759d1
TW		 5484 if (init_size && init_data_size) {
5485 priv->ucode_init.len = init_size;
98c92211 5486 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 5487
5488 priv->ucode_init_data.len = init_data_size;
98c92211 5489 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 5490
5491 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5492 goto err_pci_alloc;
5493 }
b481de9c
ZY		 5494
5495 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 5496 if (boot_size) {
5497 priv->ucode_boot.len = boot_size;
98c92211 5498 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 5499
90e759d1
TW		 5500 if (!priv->ucode_boot.v_addr)
5501 goto err_pci_alloc;
5502 }
b481de9c
ZY		 5503
5504 /* Copy images into buffers for card's bus-master reads ... */
5505
5506 /* Runtime instructions (first block of data in file) */
5507 src = &ucode->data[0];
5508 len = priv->ucode_code.len;
90e759d1 5509 IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c
ZY		 5510 memcpy(priv->ucode_code.v_addr, src, len);
5511 IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5512 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5513
5514 /* Runtime data (2nd block)
bb8c093b 5515 * NOTE: Copy into backup buffer will be done in iwl4965_up() */
b481de9c
ZY		 5516 src = &ucode->data[inst_size];
5517 len = priv->ucode_data.len;
90e759d1 5518 IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 5519 memcpy(priv->ucode_data.v_addr, src, len);
5520 memcpy(priv->ucode_data_backup.v_addr, src, len);
5521
5522 /* Initialization instructions (3rd block) */
5523 if (init_size) {
5524 src = &ucode->data[inst_size + data_size];
5525 len = priv->ucode_init.len;
90e759d1
TW		 5526 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5527 len);
b481de9c
ZY		 5528 memcpy(priv->ucode_init.v_addr, src, len);
5529 }
5530
5531 /* Initialization data (4th block) */
5532 if (init_data_size) {
5533 src = &ucode->data[inst_size + data_size + init_size];
5534 len = priv->ucode_init_data.len;
90e759d1
TW		 5535 IWL_DEBUG_INFO("Copying (but not loading) init data len %Zd\n",
5536 len);
b481de9c
ZY		 5537 memcpy(priv->ucode_init_data.v_addr, src, len);
5538 }
5539
5540 /* Bootstrap instructions (5th block) */
5541 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5542 len = priv->ucode_boot.len;
90e759d1 5543 IWL_DEBUG_INFO("Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY		 5544 memcpy(priv->ucode_boot.v_addr, src, len);
5545
5546 /* We have our copies now, allow OS release its copies */
5547 release_firmware(ucode_raw);
5548 return 0;
5549
5550 err_pci_alloc:
5551 IWL_ERROR("failed to allocate pci memory\n");
90e759d1 5552 ret = -ENOMEM;
bb8c093b 5553 iwl4965_dealloc_ucode_pci(priv);
b481de9c
ZY		 5554
5555 err_release:
5556 release_firmware(ucode_raw);
5557
5558 error:
90e759d1 5559 return ret;
b481de9c
ZY		 5560}
5561
5562
5563/**
bb8c093b 5564 * iwl4965_set_ucode_ptrs - Set uCode address location
b481de9c
ZY		 5565 *
5566 * Tell initialization uCode where to find runtime uCode.
5567 *
5568 * BSM registers initially contain pointers to initialization uCode.
5569 * We need to replace them to load runtime uCode inst and data,
5570 * and to save runtime data when powering down.
5571 */
c79dd5b5 5572static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY		 5573{
5574 dma_addr_t pinst;
5575 dma_addr_t pdata;
5576 int rc = 0;
5577 unsigned long flags;
5578
5579 /* bits 35:4 for 4965 */
5580 pinst = priv->ucode_code.p_addr >> 4;
5581 pdata = priv->ucode_data_backup.p_addr >> 4;
5582
5583 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 5584 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 5585 if (rc) {
5586 spin_unlock_irqrestore(&priv->lock, flags);
5587 return rc;
5588 }
5589
5590 /* Tell bootstrap uCode where to find image to load */
3395f6e9
TW		 5591 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5592 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5593 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY		 5594 priv->ucode_data.len);
5595
5596 /* Inst bytecount must be last to set up, bit 31 signals uCode
5597 * that all new ptr/size info is in place */
3395f6e9 5598 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY		 5599 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5600
3395f6e9 5601 iwl_release_nic_access(priv);
b481de9c
ZY		 5602
5603 spin_unlock_irqrestore(&priv->lock, flags);
5604
5605 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5606
5607 return rc;
5608}
5609
5610/**
bb8c093b 5611 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY		 5612 *
5613 * Called after REPLY_ALIVE notification received from "initialize" uCode.
5614 *
5615 * The 4965 "initialize" ALIVE reply contains calibration data for:
5616 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
5617 * (3945 does not contain this data).
5618 *
5619 * Tell "initialize" uCode to go ahead and load the runtime uCode.
5620*/
c79dd5b5 5621static void iwl4965_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY		 5622{
5623 /* Check alive response for "valid" sign from uCode */
5624 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5625 /* We had an error bringing up the hardware, so take it
5626 * all the way back down so we can try again */
5627 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5628 goto restart;
5629 }
5630
5631 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5632 * This is a paranoid check, because we would not have gotten the
5633 * "initialize" alive if code weren't properly loaded. */
bb8c093b 5634 if (iwl4965_verify_ucode(priv)) {
b481de9c
ZY		 5635 /* Runtime instruction load was bad;
5636 * take it all the way back down so we can try again */
5637 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5638 goto restart;
5639 }
5640
5641 /* Calculate temperature */
5642 priv->temperature = iwl4965_get_temperature(priv);
5643
5644 /* Send pointers to protocol/runtime uCode image ... init code will
5645 * load and launch runtime uCode, which will send us another "Alive"
5646 * notification. */
5647 IWL_DEBUG_INFO("Initialization Alive received.\n");
bb8c093b 5648 if (iwl4965_set_ucode_ptrs(priv)) {
b481de9c
ZY		 5649 /* Runtime instruction load won't happen;
5650 * take it all the way back down so we can try again */
5651 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5652 goto restart;
5653 }
5654 return;
5655
5656 restart:
5657 queue_work(priv->workqueue, &priv->restart);
5658}
5659
5660
5661/**
bb8c093b 5662 * iwl4965_alive_start - called after REPLY_ALIVE notification received
b481de9c 5663 * from protocol/runtime uCode (initialization uCode's
bb8c093b 5664 * Alive gets handled by iwl4965_init_alive_start()).
b481de9c 5665 */
c79dd5b5 5666static void iwl4965_alive_start(struct iwl_priv *priv)
b481de9c
ZY		 5667{
5668 int rc = 0;
5669
5670 IWL_DEBUG_INFO("Runtime Alive received.\n");
5671
5672 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5673 /* We had an error bringing up the hardware, so take it
5674 * all the way back down so we can try again */
5675 IWL_DEBUG_INFO("Alive failed.\n");
5676 goto restart;
5677 }
5678
5679 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5680 * This is a paranoid check, because we would not have gotten the
5681 * "runtime" alive if code weren't properly loaded. */
bb8c093b 5682 if (iwl4965_verify_ucode(priv)) {
b481de9c
ZY		 5683 /* Runtime instruction load was bad;
5684 * take it all the way back down so we can try again */
5685 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5686 goto restart;
5687 }
5688
bf85ea4f 5689 iwlcore_clear_stations_table(priv);
b481de9c
ZY		 5690
5691 rc = iwl4965_alive_notify(priv);
5692 if (rc) {
5693 IWL_WARNING("Could not complete ALIVE transition [ntf]: %d\n",
5694 rc);
5695 goto restart;
5696 }
5697
9fbab516 5698 /* After the ALIVE response, we can send host commands to 4965 uCode */
b481de9c
ZY		 5699 set_bit(STATUS_ALIVE, &priv->status);
5700
5701 /* Clear out the uCode error bit if it is set */
5702 clear_bit(STATUS_FW_ERROR, &priv->status);
5703
bb8c093b 5704 if (iwl4965_is_rfkill(priv))
b481de9c
ZY		 5705 return;
5706
5a66926a 5707 ieee80211_start_queues(priv->hw);
b481de9c
ZY		 5708
5709 priv->active_rate = priv->rates_mask;
5710 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5711
bb8c093b 5712 iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
b481de9c 5713
3109ece1 5714 if (iwl_is_associated(priv)) {
bb8c093b
CH		 5715 struct iwl4965_rxon_cmd *active_rxon =
5716 (struct iwl4965_rxon_cmd *)(&priv->active_rxon);
b481de9c
ZY		 5717
5718 memcpy(&priv->staging_rxon, &priv->active_rxon,
5719 sizeof(priv->staging_rxon));
5720 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5721 } else {
5722 /* Initialize our rx_config data */
bb8c093b 5723 iwl4965_connection_init_rx_config(priv);
b481de9c
ZY		 5724 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
5725 }
5726
9fbab516 5727 /* Configure Bluetooth device coexistence support */
bb8c093b 5728 iwl4965_send_bt_config(priv);
b481de9c
ZY		 5729
5730 /* Configure the adapter for unassociated operation */
bb8c093b 5731 iwl4965_commit_rxon(priv);
b481de9c
ZY		 5732
5733 /* At this point, the NIC is initialized and operational */
5734 priv->notif_missed_beacons = 0;
b481de9c
ZY		 5735
5736 iwl4965_rf_kill_ct_config(priv);
5a66926a 5737
b481de9c 5738 IWL_DEBUG_INFO("ALIVE processing complete.\n");
a9f46786 5739 set_bit(STATUS_READY, &priv->status);
5a66926a 5740 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 5741
ab53d8af
MA		 5742 iwl_leds_register(priv);
5743
b481de9c 5744 if (priv->error_recovering)
bb8c093b 5745 iwl4965_error_recovery(priv);
b481de9c 5746
c8381fdc 5747 iwlcore_low_level_notify(priv, IWLCORE_START_EVT);
b481de9c
ZY		 5748 return;
5749
5750 restart:
5751 queue_work(priv->workqueue, &priv->restart);
5752}
5753
c79dd5b5 5754static void iwl4965_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 5755
c79dd5b5 5756static void __iwl4965_down(struct iwl_priv *priv)
b481de9c
ZY		 5757{
5758 unsigned long flags;
5759 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5760 struct ieee80211_conf *conf = NULL;
5761
5762 IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5763
5764 conf = ieee80211_get_hw_conf(priv->hw);
5765
5766 if (!exit_pending)
5767 set_bit(STATUS_EXIT_PENDING, &priv->status);
5768
ab53d8af
MA		 5769 iwl_leds_unregister(priv);
5770
c8381fdc
MA		 5771 iwlcore_low_level_notify(priv, IWLCORE_STOP_EVT);
5772
bf85ea4f 5773 iwlcore_clear_stations_table(priv);
b481de9c
ZY		 5774
5775 /* Unblock any waiting calls */
5776 wake_up_interruptible_all(&priv->wait_command_queue);
5777
b481de9c
ZY		 5778 /* Wipe out the EXIT_PENDING status bit if we are not actually
5779 * exiting the module */
5780 if (!exit_pending)
5781 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5782
5783 /* stop and reset the on-board processor */
3395f6e9 5784 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 5785
5786 /* tell the device to stop sending interrupts */
0359facc 5787 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 5788 iwl4965_disable_interrupts(priv);
0359facc
MA		 5789 spin_unlock_irqrestore(&priv->lock, flags);
5790 iwl_synchronize_irq(priv);
b481de9c
ZY		 5791
5792 if (priv->mac80211_registered)
5793 ieee80211_stop_queues(priv->hw);
5794
bb8c093b 5795 /* If we have not previously called iwl4965_init() then
b481de9c 5796 * clear all bits but the RF Kill and SUSPEND bits and return */
bb8c093b 5797 if (!iwl4965_is_init(priv)) {
b481de9c
ZY		 5798 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5799 STATUS_RF_KILL_HW |
5800 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5801 STATUS_RF_KILL_SW |
9788864e
RC		 5802 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5803 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5804 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5805 STATUS_IN_SUSPEND;
5806 goto exit;
5807 }
5808
5809 /* ...otherwise clear out all the status bits but the RF Kill and
5810 * SUSPEND bits and continue taking the NIC down. */
5811 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5812 STATUS_RF_KILL_HW |
5813 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5814 STATUS_RF_KILL_SW |
9788864e
RC		 5815 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5816 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 5817 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5818 STATUS_IN_SUSPEND |
5819 test_bit(STATUS_FW_ERROR, &priv->status) <<
5820 STATUS_FW_ERROR;
5821
5822 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 5823 iwl_clear_bit(priv, CSR_GP_CNTRL,
9fbab516 5824 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 5825 spin_unlock_irqrestore(&priv->lock, flags);
5826
bb8c093b
CH		 5827 iwl4965_hw_txq_ctx_stop(priv);
5828 iwl4965_hw_rxq_stop(priv);
b481de9c
ZY		 5829
5830 spin_lock_irqsave(&priv->lock, flags);
3395f6e9
TW		 5831 if (!iwl_grab_nic_access(priv)) {
5832 iwl_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 5833 APMG_CLK_VAL_DMA_CLK_RQT);
3395f6e9 5834 iwl_release_nic_access(priv);
b481de9c
ZY		 5835 }
5836 spin_unlock_irqrestore(&priv->lock, flags);
5837
5838 udelay(5);
5839
bb8c093b 5840 iwl4965_hw_nic_stop_master(priv);
3395f6e9 5841 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
bb8c093b 5842 iwl4965_hw_nic_reset(priv);
b481de9c
ZY		 5843
5844 exit:
bb8c093b 5845 memset(&priv->card_alive, 0, sizeof(struct iwl4965_alive_resp));
b481de9c
ZY		 5846
5847 if (priv->ibss_beacon)
5848 dev_kfree_skb(priv->ibss_beacon);
5849 priv->ibss_beacon = NULL;
5850
5851 /* clear out any free frames */
bb8c093b 5852 iwl4965_clear_free_frames(priv);
b481de9c
ZY		 5853}
5854
c79dd5b5 5855static void iwl4965_down(struct iwl_priv *priv)
b481de9c
ZY		 5856{
5857 mutex_lock(&priv->mutex);
bb8c093b 5858 __iwl4965_down(priv);
b481de9c 5859 mutex_unlock(&priv->mutex);
b24d22b1 5860
bb8c093b 5861 iwl4965_cancel_deferred_work(priv);
b481de9c
ZY		 5862}
5863
5864#define MAX_HW_RESTARTS 5
5865
c79dd5b5 5866static int __iwl4965_up(struct iwl_priv *priv)
b481de9c
ZY		 5867{
5868 int rc, i;
b481de9c
ZY		 5869
5870 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5871 IWL_WARNING("Exit pending; will not bring the NIC up\n");
5872 return -EIO;
5873 }
5874
5875 if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
5876 IWL_WARNING("Radio disabled by SW RF kill (module "
5877 "parameter)\n");
ad97edd2 5878 iwl_rfkill_set_hw_state(priv);
e655b9f0
ZY		 5879 return -ENODEV;
5880 }
5881
e903fbd4
RC		 5882 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
5883 IWL_ERROR("ucode not available for device bringup\n");
5884 return -EIO;
5885 }
5886
e655b9f0 5887 /* If platform's RF_KILL switch is NOT set to KILL */
3395f6e9 5888 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY		 5889 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5890 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5891 else {
5892 set_bit(STATUS_RF_KILL_HW, &priv->status);
5893 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
ad97edd2 5894 iwl_rfkill_set_hw_state(priv);
e655b9f0
ZY		 5895 IWL_WARNING("Radio disabled by HW RF Kill switch\n");
5896 return -ENODEV;
5897 }
b481de9c
ZY		 5898 }
5899
ad97edd2 5900 iwl_rfkill_set_hw_state(priv);
3395f6e9 5901 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 5902
bb8c093b 5903 rc = iwl4965_hw_nic_init(priv);
b481de9c
ZY		 5904 if (rc) {
5905 IWL_ERROR("Unable to int nic\n");
5906 return rc;
5907 }
5908
5909 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW		 5910 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5911 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 5912 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5913
5914 /* clear (again), then enable host interrupts */
3395f6e9 5915 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
bb8c093b 5916 iwl4965_enable_interrupts(priv);
b481de9c
ZY		 5917
5918 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW		 5919 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5920 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 5921
5922 /* Copy original ucode data image from disk into backup cache.
5923 * This will be used to initialize the on-board processor's
5924 * data SRAM for a clean start when the runtime program first loads. */
5925 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 5926 priv->ucode_data.len);
b481de9c 5927
e655b9f0
ZY		 5928 /* We return success when we resume from suspend and rf_kill is on. */
5929 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
b481de9c 5930 return 0;
b481de9c
ZY		 5931
5932 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5933
bf85ea4f 5934 iwlcore_clear_stations_table(priv);
b481de9c
ZY		 5935
5936 /* load bootstrap state machine,
5937 * load bootstrap program into processor's memory,
5938 * prepare to load the "initialize" uCode */
bb8c093b 5939 rc = iwl4965_load_bsm(priv);
b481de9c
ZY		 5940
5941 if (rc) {
5942 IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
5943 continue;
5944 }
5945
5946 /* start card; "initialize" will load runtime ucode */
bb8c093b 5947 iwl4965_nic_start(priv);
b481de9c 5948
b481de9c
ZY		 5949 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
5950
5951 return 0;
5952 }
5953
5954 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 5955 __iwl4965_down(priv);
b481de9c
ZY		 5956
5957 /* tried to restart and config the device for as long as our
5958 * patience could withstand */
5959 IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
5960 return -EIO;
5961}
5962
5963
5964/*****************************************************************************
5965 *
5966 * Workqueue callbacks
5967 *
5968 *****************************************************************************/
5969
bb8c093b 5970static void iwl4965_bg_init_alive_start(struct work_struct *data)
b481de9c 5971{
c79dd5b5
TW		 5972 struct iwl_priv *priv =
5973 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 5974
5975 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5976 return;
5977
5978 mutex_lock(&priv->mutex);
bb8c093b 5979 iwl4965_init_alive_start(priv);
b481de9c
ZY		 5980 mutex_unlock(&priv->mutex);
5981}
5982
bb8c093b 5983static void iwl4965_bg_alive_start(struct work_struct *data)
b481de9c 5984{
c79dd5b5
TW		 5985 struct iwl_priv *priv =
5986 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 5987
5988 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5989 return;
5990
5991 mutex_lock(&priv->mutex);
bb8c093b 5992 iwl4965_alive_start(priv);
b481de9c
ZY		 5993 mutex_unlock(&priv->mutex);
5994}
5995
bb8c093b 5996static void iwl4965_bg_rf_kill(struct work_struct *work)
b481de9c 5997{
c79dd5b5 5998 struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill);
b481de9c
ZY		 5999
6000 wake_up_interruptible(&priv->wait_command_queue);
6001
6002 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6003 return;
6004
6005 mutex_lock(&priv->mutex);
6006
bb8c093b 6007 if (!iwl4965_is_rfkill(priv)) {
b481de9c
ZY		 6008 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
6009 "HW and/or SW RF Kill no longer active, restarting "
6010 "device\n");
6011 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6012 queue_work(priv->workqueue, &priv->restart);
6013 } else {
ad97edd2
MA		 6014 /* make sure mac80211 stop sending Tx frame */
6015 if (priv->mac80211_registered)
6016 ieee80211_stop_queues(priv->hw);
b481de9c
ZY		 6017
6018 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
6019 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
6020 "disabled by SW switch\n");
6021 else
6022 IWL_WARNING("Radio Frequency Kill Switch is On:\n"
6023 "Kill switch must be turned off for "
6024 "wireless networking to work.\n");
6025 }
ad97edd2
MA		 6026 iwl_rfkill_set_hw_state(priv);
6027
b481de9c
ZY		 6028 mutex_unlock(&priv->mutex);
6029}
6030
6031#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6032
bb8c093b 6033static void iwl4965_bg_scan_check(struct work_struct *data)
b481de9c 6034{
c79dd5b5
TW		 6035 struct iwl_priv *priv =
6036 container_of(data, struct iwl_priv, scan_check.work);
b481de9c
ZY		 6037
6038 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6039 return;
6040
6041 mutex_lock(&priv->mutex);
6042 if (test_bit(STATUS_SCANNING, &priv->status) ||
6043 test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6044 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6045 "Scan completion watchdog resetting adapter (%dms)\n",
6046 jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
052c4b9f 6047
b481de9c 6048 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
bb8c093b 6049 iwl4965_send_scan_abort(priv);
b481de9c
ZY		 6050 }
6051 mutex_unlock(&priv->mutex);
6052}
6053
bb8c093b 6054static void iwl4965_bg_request_scan(struct work_struct *data)
b481de9c 6055{
c79dd5b5
TW		 6056 struct iwl_priv *priv =
6057 container_of(data, struct iwl_priv, request_scan);
857485c0 6058 struct iwl_host_cmd cmd = {
b481de9c 6059 .id = REPLY_SCAN_CMD,
bb8c093b 6060 .len = sizeof(struct iwl4965_scan_cmd),
b481de9c
ZY		 6061 .meta.flags = CMD_SIZE_HUGE,
6062 };
bb8c093b 6063 struct iwl4965_scan_cmd *scan;
b481de9c 6064 struct ieee80211_conf *conf = NULL;
78330fdd 6065 u16 cmd_len;
8318d78a 6066 enum ieee80211_band band;
78330fdd 6067 u8 direct_mask;
857485c0 6068 int ret = 0;
b481de9c
ZY		 6069
6070 conf = ieee80211_get_hw_conf(priv->hw);
6071
6072 mutex_lock(&priv->mutex);
6073
bb8c093b 6074 if (!iwl4965_is_ready(priv)) {
b481de9c
ZY		 6075 IWL_WARNING("request scan called when driver not ready.\n");
6076 goto done;
6077 }
6078
6079 /* Make sure the scan wasn't cancelled before this queued work
6080 * was given the chance to run... */
6081 if (!test_bit(STATUS_SCANNING, &priv->status))
6082 goto done;
6083
6084 /* This should never be called or scheduled if there is currently
6085 * a scan active in the hardware. */
6086 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6087 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6088 "Ignoring second request.\n");
857485c0 6089 ret = -EIO;
b481de9c
ZY		 6090 goto done;
6091 }
6092
6093 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6094 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6095 goto done;
6096 }
6097
6098 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6099 IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
6100 goto done;
6101 }
6102
bb8c093b 6103 if (iwl4965_is_rfkill(priv)) {
b481de9c
ZY		 6104 IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
6105 goto done;
6106 }
6107
6108 if (!test_bit(STATUS_READY, &priv->status)) {
6109 IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
6110 goto done;
6111 }
6112
6113 if (!priv->scan_bands) {
6114 IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
6115 goto done;
6116 }
6117
6118 if (!priv->scan) {
bb8c093b 6119 priv->scan = kmalloc(sizeof(struct iwl4965_scan_cmd) +
b481de9c
ZY		 6120 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
6121 if (!priv->scan) {
857485c0 6122 ret = -ENOMEM;
b481de9c
ZY		 6123 goto done;
6124 }
6125 }
6126 scan = priv->scan;
bb8c093b 6127 memset(scan, 0, sizeof(struct iwl4965_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY		 6128
6129 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
6130 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
6131
3109ece1 6132 if (iwl_is_associated(priv)) {
b481de9c
ZY		 6133 u16 interval = 0;
6134 u32 extra;
6135 u32 suspend_time = 100;
6136 u32 scan_suspend_time = 100;
6137 unsigned long flags;
6138
6139 IWL_DEBUG_INFO("Scanning while associated...\n");
6140
6141 spin_lock_irqsave(&priv->lock, flags);
6142 interval = priv->beacon_int;
6143 spin_unlock_irqrestore(&priv->lock, flags);
6144
6145 scan->suspend_time = 0;
052c4b9f 6146 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY		 6147 if (!interval)
6148 interval = suspend_time;
6149
6150 extra = (suspend_time / interval) << 22;
6151 scan_suspend_time = (extra |
6152 ((suspend_time % interval) * 1024));
6153 scan->suspend_time = cpu_to_le32(scan_suspend_time);
6154 IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
6155 scan_suspend_time, interval);
6156 }
6157
6158 /* We should add the ability for user to lock to PASSIVE ONLY */
6159 if (priv->one_direct_scan) {
6160 IWL_DEBUG_SCAN
6161 ("Kicking off one direct scan for '%s'\n",
bb8c093b 6162 iwl4965_escape_essid(priv->direct_ssid,
b481de9c
ZY		 6163 priv->direct_ssid_len));
6164 scan->direct_scan[0].id = WLAN_EID_SSID;
6165 scan->direct_scan[0].len = priv->direct_ssid_len;
6166 memcpy(scan->direct_scan[0].ssid,
6167 priv->direct_ssid, priv->direct_ssid_len);
6168 direct_mask = 1;
3109ece1 6169 } else if (!iwl_is_associated(priv) && priv->essid_len) {
b481de9c
ZY		 6170 scan->direct_scan[0].id = WLAN_EID_SSID;
6171 scan->direct_scan[0].len = priv->essid_len;
6172 memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
6173 direct_mask = 1;
857485c0 6174 } else {
b481de9c 6175 direct_mask = 0;
857485c0 6176 }
b481de9c 6177
b481de9c
ZY		 6178 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
6179 scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
6180 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
6181
b481de9c
ZY		 6182
6183 switch (priv->scan_bands) {
6184 case 2:
6185 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
6186 scan->tx_cmd.rate_n_flags =
bb8c093b 6187 iwl4965_hw_set_rate_n_flags(IWL_RATE_1M_PLCP,
b481de9c
ZY		 6188 RATE_MCS_ANT_B_MSK|RATE_MCS_CCK_MSK);
6189
6190 scan->good_CRC_th = 0;
8318d78a 6191 band = IEEE80211_BAND_2GHZ;
b481de9c
ZY		 6192 break;
6193
6194 case 1:
6195 scan->tx_cmd.rate_n_flags =
bb8c093b 6196 iwl4965_hw_set_rate_n_flags(IWL_RATE_6M_PLCP,
b481de9c
ZY		 6197 RATE_MCS_ANT_B_MSK);
6198 scan->good_CRC_th = IWL_GOOD_CRC_TH;
8318d78a 6199 band = IEEE80211_BAND_5GHZ;
b481de9c
ZY		 6200 break;
6201
6202 default:
6203 IWL_WARNING("Invalid scan band count\n");
6204 goto done;
6205 }
6206
78330fdd
TW		 6207 /* We don't build a direct scan probe request; the uCode will do
6208 * that based on the direct_mask added to each channel entry */
6209 cmd_len = iwl4965_fill_probe_req(priv, band,
6210 (struct ieee80211_mgmt *)scan->data,
6211 IWL_MAX_SCAN_SIZE - sizeof(*scan), 0);
6212
6213 scan->tx_cmd.len = cpu_to_le16(cmd_len);
b481de9c
ZY		 6214 /* select Rx chains */
6215
6216 /* Force use of chains B and C (0x6) for scan Rx.
6217 * Avoid A (0x1) because of its off-channel reception on A-band.
6218 * MIMO is not used here, but value is required to make uCode happy. */
6219 scan->rx_chain = RXON_RX_CHAIN_DRIVER_FORCE_MSK |
6220 cpu_to_le16((0x7 << RXON_RX_CHAIN_VALID_POS) |
6221 (0x6 << RXON_RX_CHAIN_FORCE_SEL_POS) |
6222 (0x7 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS));
6223
6224 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
6225 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
6226
26c0f03f 6227 if (direct_mask) {
b481de9c
ZY		 6228 IWL_DEBUG_SCAN
6229 ("Initiating direct scan for %s.\n",
bb8c093b 6230 iwl4965_escape_essid(priv->essid, priv->essid_len));
26c0f03f
RC		 6231 scan->channel_count =
6232 iwl4965_get_channels_for_scan(
6233 priv, band, 1, /* active */
6234 direct_mask,
6235 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
6236 } else {
b481de9c 6237 IWL_DEBUG_SCAN("Initiating indirect scan.\n");
26c0f03f
RC		 6238 scan->channel_count =
6239 iwl4965_get_channels_for_scan(
6240 priv, band, 0, /* passive */
6241 direct_mask,
6242 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
6243 }
b481de9c
ZY		 6244
6245 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 6246 scan->channel_count * sizeof(struct iwl4965_scan_channel);
b481de9c
ZY		 6247 cmd.data = scan;
6248 scan->len = cpu_to_le16(cmd.len);
6249
6250 set_bit(STATUS_SCAN_HW, &priv->status);
857485c0
TW		 6251 ret = iwl_send_cmd_sync(priv, &cmd);
6252 if (ret)
b481de9c
ZY		 6253 goto done;
6254
6255 queue_delayed_work(priv->workqueue, &priv->scan_check,
6256 IWL_SCAN_CHECK_WATCHDOG);
6257
6258 mutex_unlock(&priv->mutex);
6259 return;
6260
6261 done:
01ebd063 6262 /* inform mac80211 scan aborted */
b481de9c
ZY		 6263 queue_work(priv->workqueue, &priv->scan_completed);
6264 mutex_unlock(&priv->mutex);
6265}
6266
bb8c093b 6267static void iwl4965_bg_up(struct work_struct *data)
b481de9c 6268{
c79dd5b5 6269 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY		 6270
6271 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6272 return;
6273
6274 mutex_lock(&priv->mutex);
bb8c093b 6275 __iwl4965_up(priv);
b481de9c
ZY		 6276 mutex_unlock(&priv->mutex);
6277}
6278
bb8c093b 6279static void iwl4965_bg_restart(struct work_struct *data)
b481de9c 6280{
c79dd5b5 6281 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 6282
6283 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6284 return;
6285
bb8c093b 6286 iwl4965_down(priv);
b481de9c
ZY		 6287 queue_work(priv->workqueue, &priv->up);
6288}
6289
bb8c093b 6290static void iwl4965_bg_rx_replenish(struct work_struct *data)
b481de9c 6291{
c79dd5b5
TW		 6292 struct iwl_priv *priv =
6293 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 6294
6295 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6296 return;
6297
6298 mutex_lock(&priv->mutex);
bb8c093b 6299 iwl4965_rx_replenish(priv);
b481de9c
ZY		 6300 mutex_unlock(&priv->mutex);
6301}
6302
7878a5a4
MA		 6303#define IWL_DELAY_NEXT_SCAN (HZ*2)
6304
bb8c093b 6305static void iwl4965_bg_post_associate(struct work_struct *data)
b481de9c 6306{
c79dd5b5 6307 struct iwl_priv *priv = container_of(data, struct iwl_priv,
b481de9c 6308 post_associate.work);
b481de9c 6309 struct ieee80211_conf *conf = NULL;
857485c0 6310 int ret = 0;
0795af57 6311 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6312
6313 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6314 IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
6315 return;
6316 }
6317
0795af57
JP		 6318 IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
6319 priv->assoc_id,
6320 print_mac(mac, priv->active_rxon.bssid_addr));
b481de9c
ZY		 6321
6322
6323 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6324 return;
6325
6326 mutex_lock(&priv->mutex);
6327
32bfd35d 6328 if (!priv->vif || !priv->is_open) {
948c171c
MA		 6329 mutex_unlock(&priv->mutex);
6330 return;
6331 }
bb8c093b 6332 iwl4965_scan_cancel_timeout(priv, 200);
052c4b9f 6333
b481de9c
ZY		 6334 conf = ieee80211_get_hw_conf(priv->hw);
6335
6336 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6337 iwl4965_commit_rxon(priv);
b481de9c 6338
bb8c093b
CH		 6339 memset(&priv->rxon_timing, 0, sizeof(struct iwl4965_rxon_time_cmd));
6340 iwl4965_setup_rxon_timing(priv);
857485c0 6341 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 6342 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 6343 if (ret)
b481de9c
ZY		 6344 IWL_WARNING("REPLY_RXON_TIMING failed - "
6345 "Attempting to continue.\n");
6346
6347 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
6348
c8b0e6e1 6349#ifdef CONFIG_IWL4965_HT
fd105e79
RR		 6350 if (priv->current_ht_config.is_ht)
6351 iwl4965_set_rxon_ht(priv, &priv->current_ht_config);
c8b0e6e1 6352#endif /* CONFIG_IWL4965_HT*/
b481de9c
ZY		 6353 iwl4965_set_rxon_chain(priv);
6354 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6355
6356 IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
6357 priv->assoc_id, priv->beacon_int);
6358
6359 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6360 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
6361 else
6362 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
6363
6364 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6365 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
6366 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
6367 else
6368 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6369
6370 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6371 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
6372
6373 }
6374
bb8c093b 6375 iwl4965_commit_rxon(priv);
b481de9c
ZY		 6376
6377 switch (priv->iw_mode) {
6378 case IEEE80211_IF_TYPE_STA:
bb8c093b 6379 iwl4965_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY		 6380 break;
6381
6382 case IEEE80211_IF_TYPE_IBSS:
6383
6384 /* clear out the station table */
bf85ea4f 6385 iwlcore_clear_stations_table(priv);
b481de9c 6386
bb8c093b
CH		 6387 iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0);
6388 iwl4965_rxon_add_station(priv, priv->bssid, 0);
6389 iwl4965_rate_scale_init(priv->hw, IWL_STA_ID);
6390 iwl4965_send_beacon_cmd(priv);
b481de9c
ZY		 6391
6392 break;
6393
6394 default:
6395 IWL_ERROR("%s Should not be called in %d mode\n",
6396 __FUNCTION__, priv->iw_mode);
6397 break;
6398 }
6399
bb8c093b 6400 iwl4965_sequence_reset(priv);
b481de9c 6401
c8b0e6e1 6402#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 6403 /* Enable Rx differential gain and sensitivity calibrations */
6404 iwl4965_chain_noise_reset(priv);
6405 priv->start_calib = 1;
c8b0e6e1 6406#endif /* CONFIG_IWL4965_SENSITIVITY */
b481de9c
ZY		 6407
6408 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6409 priv->assoc_station_added = 1;
6410
bb8c093b 6411 iwl4965_activate_qos(priv, 0);
292ae174 6412
7878a5a4
MA		 6413 /* we have just associated, don't start scan too early */
6414 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
b481de9c
ZY		 6415 mutex_unlock(&priv->mutex);
6416}
6417
bb8c093b 6418static void iwl4965_bg_abort_scan(struct work_struct *work)
b481de9c 6419{
c79dd5b5 6420 struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan);
b481de9c 6421
bb8c093b 6422 if (!iwl4965_is_ready(priv))
b481de9c
ZY		 6423 return;
6424
6425 mutex_lock(&priv->mutex);
6426
6427 set_bit(STATUS_SCAN_ABORTING, &priv->status);
bb8c093b 6428 iwl4965_send_scan_abort(priv);
b481de9c
ZY		 6429
6430 mutex_unlock(&priv->mutex);
6431}
6432
76bb77e0
ZY		 6433static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
6434
bb8c093b 6435static void iwl4965_bg_scan_completed(struct work_struct *work)
b481de9c 6436{
c79dd5b5
TW		 6437 struct iwl_priv *priv =
6438 container_of(work, struct iwl_priv, scan_completed);
b481de9c
ZY		 6439
6440 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
6441
6442 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6443 return;
6444
a0646470
ZY		 6445 if (test_bit(STATUS_CONF_PENDING, &priv->status))
6446 iwl4965_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
76bb77e0 6447
b481de9c
ZY		 6448 ieee80211_scan_completed(priv->hw);
6449
6450 /* Since setting the TXPOWER may have been deferred while
6451 * performing the scan, fire one off */
6452 mutex_lock(&priv->mutex);
bb8c093b 6453 iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY		 6454 mutex_unlock(&priv->mutex);
6455}
6456
6457/*****************************************************************************
6458 *
6459 * mac80211 entry point functions
6460 *
6461 *****************************************************************************/
6462
5a66926a
ZY		 6463#define UCODE_READY_TIMEOUT (2 * HZ)
6464
bb8c093b 6465static int iwl4965_mac_start(struct ieee80211_hw *hw)
b481de9c 6466{
c79dd5b5 6467 struct iwl_priv *priv = hw->priv;
5a66926a 6468 int ret;
b481de9c
ZY		 6469
6470 IWL_DEBUG_MAC80211("enter\n");
6471
5a66926a
ZY		 6472 if (pci_enable_device(priv->pci_dev)) {
6473 IWL_ERROR("Fail to pci_enable_device\n");
6474 return -ENODEV;
6475 }
6476 pci_restore_state(priv->pci_dev);
6477 pci_enable_msi(priv->pci_dev);
6478
6479 ret = request_irq(priv->pci_dev->irq, iwl4965_isr, IRQF_SHARED,
6480 DRV_NAME, priv);
6481 if (ret) {
6482 IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
6483 goto out_disable_msi;
6484 }
6485
b481de9c
ZY		 6486 /* we should be verifying the device is ready to be opened */
6487 mutex_lock(&priv->mutex);
6488
5a66926a
ZY		 6489 memset(&priv->staging_rxon, 0, sizeof(struct iwl4965_rxon_cmd));
6490 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
6491 * ucode filename and max sizes are card-specific. */
b481de9c 6492
5a66926a
ZY		 6493 if (!priv->ucode_code.len) {
6494 ret = iwl4965_read_ucode(priv);
6495 if (ret) {
6496 IWL_ERROR("Could not read microcode: %d\n", ret);
6497 mutex_unlock(&priv->mutex);
6498 goto out_release_irq;
6499 }
6500 }
b481de9c 6501
e655b9f0 6502 ret = __iwl4965_up(priv);
5a66926a 6503
b481de9c 6504 mutex_unlock(&priv->mutex);
5a66926a 6505
e655b9f0
ZY		 6506 if (ret)
6507 goto out_release_irq;
6508
6509 IWL_DEBUG_INFO("Start UP work done.\n");
6510
6511 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
6512 return 0;
6513
5a66926a
ZY		 6514 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
6515 * mac80211 will not be run successfully. */
6516 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
6517 test_bit(STATUS_READY, &priv->status),
6518 UCODE_READY_TIMEOUT);
6519 if (!ret) {
6520 if (!test_bit(STATUS_READY, &priv->status)) {
6521 IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
6522 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6523 ret = -ETIMEDOUT;
6524 goto out_release_irq;
6525 }
6526 }
6527
e655b9f0 6528 priv->is_open = 1;
b481de9c
ZY		 6529 IWL_DEBUG_MAC80211("leave\n");
6530 return 0;
5a66926a
ZY		 6531
6532out_release_irq:
6533 free_irq(priv->pci_dev->irq, priv);
6534out_disable_msi:
6535 pci_disable_msi(priv->pci_dev);
e655b9f0
ZY		 6536 pci_disable_device(priv->pci_dev);
6537 priv->is_open = 0;
6538 IWL_DEBUG_MAC80211("leave - failed\n");
5a66926a 6539 return ret;
b481de9c
ZY		 6540}
6541
bb8c093b 6542static void iwl4965_mac_stop(struct ieee80211_hw *hw)
b481de9c 6543{
c79dd5b5 6544 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 6545
6546 IWL_DEBUG_MAC80211("enter\n");
948c171c 6547
e655b9f0
ZY		 6548 if (!priv->is_open) {
6549 IWL_DEBUG_MAC80211("leave - skip\n");
6550 return;
6551 }
6552
b481de9c 6553 priv->is_open = 0;
5a66926a
ZY		 6554
6555 if (iwl4965_is_ready_rf(priv)) {
e655b9f0
ZY		 6556 /* stop mac, cancel any scan request and clear
6557 * RXON_FILTER_ASSOC_MSK BIT
6558 */
5a66926a
ZY		 6559 mutex_lock(&priv->mutex);
6560 iwl4965_scan_cancel_timeout(priv, 100);
6561 cancel_delayed_work(&priv->post_associate);
fde3571f 6562 mutex_unlock(&priv->mutex);
fde3571f
MA		 6563 }
6564
5a66926a
ZY		 6565 iwl4965_down(priv);
6566
6567 flush_workqueue(priv->workqueue);
6568 free_irq(priv->pci_dev->irq, priv);
6569 pci_disable_msi(priv->pci_dev);
6570 pci_save_state(priv->pci_dev);
6571 pci_disable_device(priv->pci_dev);
948c171c 6572
b481de9c 6573 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6574}
6575
bb8c093b 6576static int iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY		 6577 struct ieee80211_tx_control *ctl)
6578{
c79dd5b5 6579 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 6580
6581 IWL_DEBUG_MAC80211("enter\n");
6582
6583 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
6584 IWL_DEBUG_MAC80211("leave - monitor\n");
6585 return -1;
6586 }
6587
6588 IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
8318d78a 6589 ctl->tx_rate->bitrate);
b481de9c 6590
bb8c093b 6591 if (iwl4965_tx_skb(priv, skb, ctl))
b481de9c
ZY		 6592 dev_kfree_skb_any(skb);
6593
6594 IWL_DEBUG_MAC80211("leave\n");
6595 return 0;
6596}
6597
bb8c093b 6598static int iwl4965_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6599 struct ieee80211_if_init_conf *conf)
6600{
c79dd5b5 6601 struct iwl_priv *priv = hw->priv;
b481de9c 6602 unsigned long flags;
0795af57 6603 DECLARE_MAC_BUF(mac);
b481de9c 6604
32bfd35d 6605 IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
b481de9c 6606
32bfd35d
JB		 6607 if (priv->vif) {
6608 IWL_DEBUG_MAC80211("leave - vif != NULL\n");
75849d28 6609 return -EOPNOTSUPP;
b481de9c
ZY		 6610 }
6611
6612 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 6613 priv->vif = conf->vif;
b481de9c
ZY		 6614
6615 spin_unlock_irqrestore(&priv->lock, flags);
6616
6617 mutex_lock(&priv->mutex);
864792e3
TW		 6618
6619 if (conf->mac_addr) {
6620 IWL_DEBUG_MAC80211("Set %s\n", print_mac(mac, conf->mac_addr));
6621 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6622 }
b481de9c 6623
5a66926a
ZY		 6624 if (iwl4965_is_ready(priv))
6625 iwl4965_set_mode(priv, conf->type);
6626
b481de9c
ZY		 6627 mutex_unlock(&priv->mutex);
6628
5a66926a 6629 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 6630 return 0;
6631}
6632
6633/**
bb8c093b 6634 * iwl4965_mac_config - mac80211 config callback
b481de9c
ZY		 6635 *
6636 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
6637 * be set inappropriately and the driver currently sets the hardware up to
6638 * use it whenever needed.
6639 */
bb8c093b 6640static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
b481de9c 6641{
c79dd5b5 6642 struct iwl_priv *priv = hw->priv;
bf85ea4f 6643 const struct iwl_channel_info *ch_info;
b481de9c 6644 unsigned long flags;
76bb77e0 6645 int ret = 0;
b481de9c
ZY		 6646
6647 mutex_lock(&priv->mutex);
8318d78a 6648 IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
b481de9c 6649
12342c47
ZY		 6650 priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
6651
bb8c093b 6652 if (!iwl4965_is_ready(priv)) {
b481de9c 6653 IWL_DEBUG_MAC80211("leave - not ready\n");
76bb77e0
ZY		 6654 ret = -EIO;
6655 goto out;
b481de9c
ZY		 6656 }
6657
1ea87396 6658 if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
b481de9c 6659 test_bit(STATUS_SCANNING, &priv->status))) {
a0646470
ZY		 6660 IWL_DEBUG_MAC80211("leave - scanning\n");
6661 set_bit(STATUS_CONF_PENDING, &priv->status);
b481de9c 6662 mutex_unlock(&priv->mutex);
a0646470 6663 return 0;
b481de9c
ZY		 6664 }
6665
6666 spin_lock_irqsave(&priv->lock, flags);
6667
8622e705 6668 ch_info = iwl_get_channel_info(priv, conf->channel->band,
8318d78a 6669 ieee80211_frequency_to_channel(conf->channel->center_freq));
b481de9c 6670 if (!is_channel_valid(ch_info)) {
b481de9c
ZY		 6671 IWL_DEBUG_MAC80211("leave - invalid channel\n");
6672 spin_unlock_irqrestore(&priv->lock, flags);
76bb77e0
ZY		 6673 ret = -EINVAL;
6674 goto out;
b481de9c
ZY		 6675 }
6676
c8b0e6e1 6677#ifdef CONFIG_IWL4965_HT
78330fdd 6678 /* if we are switching from ht to 2.4 clear flags
b481de9c
ZY		 6679 * from any ht related info since 2.4 does not
6680 * support ht */
78330fdd 6681 if ((le16_to_cpu(priv->staging_rxon.channel) != conf->channel->hw_value)
b481de9c
ZY		 6682#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6683 && !(conf->flags & IEEE80211_CONF_CHANNEL_SWITCH)
6684#endif
6685 )
6686 priv->staging_rxon.flags = 0;
c8b0e6e1 6687#endif /* CONFIG_IWL4965_HT */
b481de9c 6688
bf85ea4f 6689 iwlcore_set_rxon_channel(priv, conf->channel->band,
8318d78a 6690 ieee80211_frequency_to_channel(conf->channel->center_freq));
b481de9c 6691
8318d78a 6692 iwl4965_set_flags_for_phymode(priv, conf->channel->band);
b481de9c
ZY		 6693
6694 /* The list of supported rates and rate mask can be different
8318d78a 6695 * for each band; since the band may have changed, reset
b481de9c 6696 * the rate mask to what mac80211 lists */
bb8c093b 6697 iwl4965_set_rate(priv);
b481de9c
ZY		 6698
6699 spin_unlock_irqrestore(&priv->lock, flags);
6700
6701#ifdef IEEE80211_CONF_CHANNEL_SWITCH
6702 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
bb8c093b 6703 iwl4965_hw_channel_switch(priv, conf->channel);
76bb77e0 6704 goto out;
b481de9c
ZY		 6705 }
6706#endif
6707
ad97edd2
MA		 6708 if (priv->cfg->ops->lib->radio_kill_sw)
6709 priv->cfg->ops->lib->radio_kill_sw(priv, !conf->radio_enabled);
b481de9c
ZY		 6710
6711 if (!conf->radio_enabled) {
6712 IWL_DEBUG_MAC80211("leave - radio disabled\n");
76bb77e0 6713 goto out;
b481de9c
ZY		 6714 }
6715
bb8c093b 6716 if (iwl4965_is_rfkill(priv)) {
b481de9c 6717 IWL_DEBUG_MAC80211("leave - RF kill\n");
76bb77e0
ZY		 6718 ret = -EIO;
6719 goto out;
b481de9c
ZY		 6720 }
6721
bb8c093b 6722 iwl4965_set_rate(priv);
b481de9c
ZY		 6723
6724 if (memcmp(&priv->active_rxon,
6725 &priv->staging_rxon, sizeof(priv->staging_rxon)))
bb8c093b 6726 iwl4965_commit_rxon(priv);
b481de9c
ZY		 6727 else
6728 IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
6729
6730 IWL_DEBUG_MAC80211("leave\n");
6731
a0646470
ZY		 6732out:
6733 clear_bit(STATUS_CONF_PENDING, &priv->status);
5a66926a 6734 mutex_unlock(&priv->mutex);
76bb77e0 6735 return ret;
b481de9c
ZY		 6736}
6737
c79dd5b5 6738static void iwl4965_config_ap(struct iwl_priv *priv)
b481de9c 6739{
857485c0 6740 int ret = 0;
b481de9c 6741
d986bcd1 6742 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 6743 return;
6744
6745 /* The following should be done only at AP bring up */
6746 if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
6747
6748 /* RXON - unassoc (to set timing command) */
6749 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6750 iwl4965_commit_rxon(priv);
b481de9c
ZY		 6751
6752 /* RXON Timing */
bb8c093b
CH		 6753 memset(&priv->rxon_timing, 0, sizeof(struct iwl4965_rxon_time_cmd));
6754 iwl4965_setup_rxon_timing(priv);
857485c0 6755 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 6756 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 6757 if (ret)
b481de9c
ZY		 6758 IWL_WARNING("REPLY_RXON_TIMING failed - "
6759 "Attempting to continue.\n");
6760
6761 iwl4965_set_rxon_chain(priv);
6762
6763 /* FIXME: what should be the assoc_id for AP? */
6764 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
6765 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
6766 priv->staging_rxon.flags |=
6767 RXON_FLG_SHORT_PREAMBLE_MSK;
6768 else
6769 priv->staging_rxon.flags &=
6770 ~RXON_FLG_SHORT_PREAMBLE_MSK;
6771
6772 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
6773 if (priv->assoc_capability &
6774 WLAN_CAPABILITY_SHORT_SLOT_TIME)
6775 priv->staging_rxon.flags |=
6776 RXON_FLG_SHORT_SLOT_MSK;
6777 else
6778 priv->staging_rxon.flags &=
6779 ~RXON_FLG_SHORT_SLOT_MSK;
6780
6781 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
6782 priv->staging_rxon.flags &=
6783 ~RXON_FLG_SHORT_SLOT_MSK;
6784 }
6785 /* restore RXON assoc */
6786 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
bb8c093b 6787 iwl4965_commit_rxon(priv);
bb8c093b 6788 iwl4965_activate_qos(priv, 1);
bb8c093b 6789 iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0);
e1493deb 6790 }
bb8c093b 6791 iwl4965_send_beacon_cmd(priv);
b481de9c
ZY		 6792
6793 /* FIXME - we need to add code here to detect a totally new
6794 * configuration, reset the AP, unassoc, rxon timing, assoc,
6795 * clear sta table, add BCAST sta... */
6796}
6797
32bfd35d
JB		 6798static int iwl4965_mac_config_interface(struct ieee80211_hw *hw,
6799 struct ieee80211_vif *vif,
b481de9c
ZY		 6800 struct ieee80211_if_conf *conf)
6801{
c79dd5b5 6802 struct iwl_priv *priv = hw->priv;
0795af57 6803 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 6804 unsigned long flags;
6805 int rc;
6806
6807 if (conf == NULL)
6808 return -EIO;
6809
b716bb91
EG		 6810 if (priv->vif != vif) {
6811 IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
6812 mutex_unlock(&priv->mutex);
6813 return 0;
6814 }
6815
b481de9c
ZY		 6816 if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
6817 (!conf->beacon || !conf->ssid_len)) {
6818 IWL_DEBUG_MAC80211
6819 ("Leaving in AP mode because HostAPD is not ready.\n");
6820 return 0;
6821 }
6822
5a66926a
ZY		 6823 if (!iwl4965_is_alive(priv))
6824 return -EAGAIN;
6825
b481de9c
ZY		 6826 mutex_lock(&priv->mutex);
6827
b481de9c 6828 if (conf->bssid)
0795af57
JP		 6829 IWL_DEBUG_MAC80211("bssid: %s\n",
6830 print_mac(mac, conf->bssid));
b481de9c 6831
4150c572
JB		 6832/*
6833 * very dubious code was here; the probe filtering flag is never set:
6834 *
b481de9c
ZY		 6835 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
6836 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 6837 */
b481de9c
ZY		 6838
6839 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
6840 if (!conf->bssid) {
6841 conf->bssid = priv->mac_addr;
6842 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
0795af57
JP		 6843 IWL_DEBUG_MAC80211("bssid was set to: %s\n",
6844 print_mac(mac, conf->bssid));
b481de9c
ZY		 6845 }
6846 if (priv->ibss_beacon)
6847 dev_kfree_skb(priv->ibss_beacon);
6848
6849 priv->ibss_beacon = conf->beacon;
6850 }
6851
fde3571f
MA		 6852 if (iwl4965_is_rfkill(priv))
6853 goto done;
6854
b481de9c
ZY		 6855 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
6856 !is_multicast_ether_addr(conf->bssid)) {
6857 /* If there is currently a HW scan going on in the background
6858 * then we need to cancel it else the RXON below will fail. */
bb8c093b 6859 if (iwl4965_scan_cancel_timeout(priv, 100)) {
b481de9c
ZY		 6860 IWL_WARNING("Aborted scan still in progress "
6861 "after 100ms\n");
6862 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
6863 mutex_unlock(&priv->mutex);
6864 return -EAGAIN;
6865 }
6866 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
6867
6868 /* TODO: Audit driver for usage of these members and see
6869 * if mac80211 deprecates them (priv->bssid looks like it
6870 * shouldn't be there, but I haven't scanned the IBSS code
6871 * to verify) - jpk */
6872 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6873
6874 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b 6875 iwl4965_config_ap(priv);
b481de9c 6876 else {
bb8c093b 6877 rc = iwl4965_commit_rxon(priv);
b481de9c 6878 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
bb8c093b 6879 iwl4965_rxon_add_station(
b481de9c
ZY		 6880 priv, priv->active_rxon.bssid_addr, 1);
6881 }
6882
6883 } else {
bb8c093b 6884 iwl4965_scan_cancel_timeout(priv, 100);
b481de9c 6885 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 6886 iwl4965_commit_rxon(priv);
b481de9c
ZY		 6887 }
6888
fde3571f 6889 done:
b481de9c
ZY		 6890 spin_lock_irqsave(&priv->lock, flags);
6891 if (!conf->ssid_len)
6892 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
6893 else
6894 memcpy(priv->essid, conf->ssid, conf->ssid_len);
6895
6896 priv->essid_len = conf->ssid_len;
6897 spin_unlock_irqrestore(&priv->lock, flags);
6898
6899 IWL_DEBUG_MAC80211("leave\n");
6900 mutex_unlock(&priv->mutex);
6901
6902 return 0;
6903}
6904
bb8c093b 6905static void iwl4965_configure_filter(struct ieee80211_hw *hw,
4150c572
JB		 6906 unsigned int changed_flags,
6907 unsigned int *total_flags,
6908 int mc_count, struct dev_addr_list *mc_list)
6909{
6910 /*
6911 * XXX: dummy
bb8c093b 6912 * see also iwl4965_connection_init_rx_config
4150c572
JB		 6913 */
6914 *total_flags = 0;
6915}
6916
bb8c093b 6917static void iwl4965_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 6918 struct ieee80211_if_init_conf *conf)
6919{
c79dd5b5 6920 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 6921
6922 IWL_DEBUG_MAC80211("enter\n");
6923
6924 mutex_lock(&priv->mutex);
948c171c 6925
fde3571f
MA		 6926 if (iwl4965_is_ready_rf(priv)) {
6927 iwl4965_scan_cancel_timeout(priv, 100);
6928 cancel_delayed_work(&priv->post_associate);
6929 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
6930 iwl4965_commit_rxon(priv);
6931 }
32bfd35d
JB		 6932 if (priv->vif == conf->vif) {
6933 priv->vif = NULL;
b481de9c
ZY		 6934 memset(priv->bssid, 0, ETH_ALEN);
6935 memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
6936 priv->essid_len = 0;
6937 }
6938 mutex_unlock(&priv->mutex);
6939
6940 IWL_DEBUG_MAC80211("leave\n");
6941
6942}
471b3efd 6943
98952d5d
TW		 6944
6945#ifdef CONFIG_IWL4965_HT
6946static void iwl4965_ht_conf(struct iwl_priv *priv,
6947 struct ieee80211_bss_conf *bss_conf)
6948{
6949 struct ieee80211_ht_info *ht_conf = bss_conf->ht_conf;
6950 struct ieee80211_ht_bss_info *ht_bss_conf = bss_conf->ht_bss_conf;
6951 struct iwl_ht_info *iwl_conf = &priv->current_ht_config;
6952
6953 IWL_DEBUG_MAC80211("enter: \n");
6954
6955 iwl_conf->is_ht = bss_conf->assoc_ht;
6956
6957 if (!iwl_conf->is_ht)
6958 return;
6959
6960 priv->ps_mode = (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2);
6961
6962 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20)
6963 iwl_conf->sgf |= 0x1;
6964 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40)
6965 iwl_conf->sgf |= 0x2;
6966
6967 iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD);
6968 iwl_conf->max_amsdu_size =
6969 !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU);
6970
6971 iwl_conf->supported_chan_width =
6972 !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH);
6973 iwl_conf->extension_chan_offset =
6974 ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_SEC_OFFSET;
6975 /* If no above or below channel supplied disable FAT channel */
6976 if (iwl_conf->extension_chan_offset != IWL_EXT_CHANNEL_OFFSET_ABOVE &&
6977 iwl_conf->extension_chan_offset != IWL_EXT_CHANNEL_OFFSET_BELOW)
6978 iwl_conf->supported_chan_width = 0;
6979
6980 iwl_conf->tx_mimo_ps_mode =
6981 (u8)((ht_conf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2);
6982 memcpy(iwl_conf->supp_mcs_set, ht_conf->supp_mcs_set, 16);
6983
6984 iwl_conf->control_channel = ht_bss_conf->primary_channel;
6985 iwl_conf->tx_chan_width =
6986 !!(ht_bss_conf->bss_cap & IEEE80211_HT_IE_CHA_WIDTH);
6987 iwl_conf->ht_protection =
6988 ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_HT_PROTECTION;
6989 iwl_conf->non_GF_STA_present =
6990 !!(ht_bss_conf->bss_op_mode & IEEE80211_HT_IE_NON_GF_STA_PRSNT);
6991
6992 IWL_DEBUG_MAC80211("control channel %d\n", iwl_conf->control_channel);
6993 IWL_DEBUG_MAC80211("leave\n");
6994}
6995#else
6996static inline void iwl4965_ht_conf(struct iwl_priv *priv,
6997 struct ieee80211_bss_conf *bss_conf)
6998{
6999}
7000#endif
7001
3109ece1 7002#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
471b3efd
JB		 7003static void iwl4965_bss_info_changed(struct ieee80211_hw *hw,
7004 struct ieee80211_vif *vif,
7005 struct ieee80211_bss_conf *bss_conf,
7006 u32 changes)
220173b0 7007{
c79dd5b5 7008 struct iwl_priv *priv = hw->priv;
220173b0 7009
3109ece1
TW		 7010 IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
7011
471b3efd 7012 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
3109ece1
TW		 7013 IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
7014 bss_conf->use_short_preamble);
471b3efd 7015 if (bss_conf->use_short_preamble)
220173b0
TW		 7016 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
7017 else
7018 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
7019 }
7020
471b3efd 7021 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
3109ece1 7022 IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
8318d78a 7023 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
220173b0
TW		 7024 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
7025 else
7026 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
7027 }
7028
98952d5d 7029 if (changes & BSS_CHANGED_HT) {
3109ece1 7030 IWL_DEBUG_MAC80211("HT %d\n", bss_conf->assoc_ht);
98952d5d
TW		 7031 iwl4965_ht_conf(priv, bss_conf);
7032 iwl4965_set_rxon_chain(priv);
7033 }
7034
471b3efd 7035 if (changes & BSS_CHANGED_ASSOC) {
3109ece1
TW		 7036 IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
7037 if (bss_conf->assoc) {
7038 priv->assoc_id = bss_conf->aid;
7039 priv->beacon_int = bss_conf->beacon_int;
7040 priv->timestamp = bss_conf->timestamp;
7041 priv->assoc_capability = bss_conf->assoc_capability;
7042 priv->next_scan_jiffies = jiffies +
7043 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
7044 queue_work(priv->workqueue, &priv->post_associate.work);
7045 } else {
7046 priv->assoc_id = 0;
7047 IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
7048 }
7049 } else if (changes && iwl_is_associated(priv) && priv->assoc_id) {
7050 IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
7051 iwl4965_send_rxon_assoc(priv);
471b3efd
JB		 7052 }
7053
220173b0 7054}
b481de9c 7055
bb8c093b 7056static int iwl4965_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
b481de9c
ZY		 7057{
7058 int rc = 0;
7059 unsigned long flags;
c79dd5b5 7060 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 7061
7062 IWL_DEBUG_MAC80211("enter\n");
7063
052c4b9f 7064 mutex_lock(&priv->mutex);
b481de9c
ZY		 7065 spin_lock_irqsave(&priv->lock, flags);
7066
bb8c093b 7067 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY		 7068 rc = -EIO;
7069 IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
7070 goto out_unlock;
7071 }
7072
7073 if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
7074 rc = -EIO;
7075 IWL_ERROR("ERROR: APs don't scan\n");
7076 goto out_unlock;
7077 }
7078
7878a5a4
MA		 7079 /* we don't schedule scan within next_scan_jiffies period */
7080 if (priv->next_scan_jiffies &&
7081 time_after(priv->next_scan_jiffies, jiffies)) {
7082 rc = -EAGAIN;
7083 goto out_unlock;
7084 }
b481de9c 7085 /* if we just finished scan ask for delay */
7878a5a4
MA		 7086 if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
7087 IWL_DELAY_NEXT_SCAN, jiffies)) {
b481de9c
ZY		 7088 rc = -EAGAIN;
7089 goto out_unlock;
7090 }
7091 if (len) {
7878a5a4 7092 IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
bb8c093b 7093 iwl4965_escape_essid(ssid, len), (int)len);
b481de9c
ZY		 7094
7095 priv->one_direct_scan = 1;
7096 priv->direct_ssid_len = (u8)
7097 min((u8) len, (u8) IW_ESSID_MAX_SIZE);
7098 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
948c171c
MA		 7099 } else
7100 priv->one_direct_scan = 0;
b481de9c 7101
bb8c093b 7102 rc = iwl4965_scan_initiate(priv);
b481de9c
ZY		 7103
7104 IWL_DEBUG_MAC80211("leave\n");
7105
7106out_unlock:
7107 spin_unlock_irqrestore(&priv->lock, flags);
052c4b9f 7108 mutex_unlock(&priv->mutex);
b481de9c
ZY		 7109
7110 return rc;
7111}
7112
ab885f8c
EG		 7113static void iwl4965_mac_update_tkip_key(struct ieee80211_hw *hw,
7114 struct ieee80211_key_conf *keyconf, const u8 *addr,
7115 u32 iv32, u16 *phase1key)
7116{
7117 struct iwl_priv *priv = hw->priv;
7118 u8 sta_id = IWL_INVALID_STATION;
7119 unsigned long flags;
7120 __le16 key_flags = 0;
7121 int i;
7122 DECLARE_MAC_BUF(mac);
7123
7124 IWL_DEBUG_MAC80211("enter\n");
7125
7126 sta_id = iwl4965_hw_find_station(priv, addr);
7127 if (sta_id == IWL_INVALID_STATION) {
7128 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
7129 print_mac(mac, addr));
7130 return;
7131 }
7132
7133 iwl4965_scan_cancel_timeout(priv, 100);
7134
7135 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
7136 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
7137 key_flags &= ~STA_KEY_FLG_INVALID;
7138
7139 if (sta_id == priv->hw_setting.bcast_sta_id)
7140 key_flags |= STA_KEY_MULTICAST_MSK;
7141
7142 spin_lock_irqsave(&priv->sta_lock, flags);
7143
7144 priv->stations[sta_id].sta.key.key_offset =
7145 (sta_id % STA_KEY_MAX_NUM);/* FIXME */
7146 priv->stations[sta_id].sta.key.key_flags = key_flags;
7147 priv->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
7148
7149 for (i = 0; i < 5; i++)
7150 priv->stations[sta_id].sta.key.tkip_rx_ttak[i] =
7151 cpu_to_le16(phase1key[i]);
7152
7153 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
7154 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
7155
7156 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
7157
7158 spin_unlock_irqrestore(&priv->sta_lock, flags);
7159
7160 IWL_DEBUG_MAC80211("leave\n");
7161}
7162
bb8c093b 7163static int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
b481de9c
ZY		 7164 const u8 *local_addr, const u8 *addr,
7165 struct ieee80211_key_conf *key)
7166{
c79dd5b5 7167 struct iwl_priv *priv = hw->priv;
0795af57 7168 DECLARE_MAC_BUF(mac);
deb09c43
EG		 7169 int ret = 0;
7170 u8 sta_id = IWL_INVALID_STATION;
7171 u8 static_key;
b481de9c
ZY		 7172
7173 IWL_DEBUG_MAC80211("enter\n");
7174
1ea87396 7175 if (!priv->cfg->mod_params->hw_crypto) {
b481de9c
ZY		 7176 IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
7177 return -EOPNOTSUPP;
7178 }
7179
7180 if (is_zero_ether_addr(addr))
7181 /* only support pairwise keys */
7182 return -EOPNOTSUPP;
7183
deb09c43
EG		 7184 /* FIXME: need to differenciate between static and dynamic key
7185 * in the level of mac80211 */
3109ece1 7186 static_key = !iwl_is_associated(priv);
b481de9c 7187
deb09c43
EG		 7188 if (!static_key) {
7189 sta_id = iwl4965_hw_find_station(priv, addr);
7190 if (sta_id == IWL_INVALID_STATION) {
7191 IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
7192 print_mac(mac, addr));
7193 return -EINVAL;
7194 }
7195 }
b481de9c 7196
bb8c093b 7197 iwl4965_scan_cancel_timeout(priv, 100);
052c4b9f 7198
b481de9c 7199 switch (cmd) {
deb09c43
EG		 7200 case SET_KEY:
7201 if (static_key)
7202 ret = iwl4965_set_static_key(priv, key);
7203 else
7204 ret = iwl4965_set_dynamic_key(priv, key, sta_id);
7205
7206 IWL_DEBUG_MAC80211("enable hwcrypto key\n");
b481de9c
ZY		 7207 break;
7208 case DISABLE_KEY:
deb09c43
EG		 7209 if (static_key)
7210 ret = iwl4965_remove_static_key(priv);
7211 else
7212 ret = iwl4965_clear_sta_key_info(priv, sta_id);
7213
7214 IWL_DEBUG_MAC80211("disable hwcrypto key\n");
b481de9c
ZY		 7215 break;
7216 default:
deb09c43 7217 ret = -EINVAL;
b481de9c
ZY		 7218 }
7219
7220 IWL_DEBUG_MAC80211("leave\n");
b481de9c 7221
deb09c43 7222 return ret;
b481de9c
ZY		 7223}
7224
bb8c093b 7225static int iwl4965_mac_conf_tx(struct ieee80211_hw *hw, int queue,
b481de9c
ZY		 7226 const struct ieee80211_tx_queue_params *params)
7227{
c79dd5b5 7228 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 7229 unsigned long flags;
7230 int q;
b481de9c
ZY		 7231
7232 IWL_DEBUG_MAC80211("enter\n");
7233
bb8c093b 7234 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY		 7235 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7236 return -EIO;
7237 }
7238
7239 if (queue >= AC_NUM) {
7240 IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
7241 return 0;
7242 }
7243
b481de9c
ZY		 7244 if (!priv->qos_data.qos_enable) {
7245 priv->qos_data.qos_active = 0;
7246 IWL_DEBUG_MAC80211("leave - qos not enabled\n");
7247 return 0;
7248 }
7249 q = AC_NUM - 1 - queue;
7250
7251 spin_lock_irqsave(&priv->lock, flags);
7252
7253 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
7254 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
7255 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
7256 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 7257 cpu_to_le16((params->txop * 32));
b481de9c
ZY		 7258
7259 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
7260 priv->qos_data.qos_active = 1;
7261
7262 spin_unlock_irqrestore(&priv->lock, flags);
7263
7264 mutex_lock(&priv->mutex);
7265 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
bb8c093b 7266 iwl4965_activate_qos(priv, 1);
3109ece1 7267 else if (priv->assoc_id && iwl_is_associated(priv))
bb8c093b 7268 iwl4965_activate_qos(priv, 0);
b481de9c
ZY		 7269
7270 mutex_unlock(&priv->mutex);
7271
b481de9c
ZY		 7272 IWL_DEBUG_MAC80211("leave\n");
7273 return 0;
7274}
7275
bb8c093b 7276static int iwl4965_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7277 struct ieee80211_tx_queue_stats *stats)
7278{
c79dd5b5 7279 struct iwl_priv *priv = hw->priv;
b481de9c 7280 int i, avail;
bb8c093b
CH		 7281 struct iwl4965_tx_queue *txq;
7282 struct iwl4965_queue *q;
b481de9c
ZY		 7283 unsigned long flags;
7284
7285 IWL_DEBUG_MAC80211("enter\n");
7286
bb8c093b 7287 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY		 7288 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7289 return -EIO;
7290 }
7291
7292 spin_lock_irqsave(&priv->lock, flags);
7293
7294 for (i = 0; i < AC_NUM; i++) {
7295 txq = &priv->txq[i];
7296 q = &txq->q;
bb8c093b 7297 avail = iwl4965_queue_space(q);
b481de9c
ZY		 7298
7299 stats->data[i].len = q->n_window - avail;
7300 stats->data[i].limit = q->n_window - q->high_mark;
7301 stats->data[i].count = q->n_window;
7302
7303 }
7304 spin_unlock_irqrestore(&priv->lock, flags);
7305
7306 IWL_DEBUG_MAC80211("leave\n");
7307
7308 return 0;
7309}
7310
bb8c093b 7311static int iwl4965_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 7312 struct ieee80211_low_level_stats *stats)
7313{
7314 IWL_DEBUG_MAC80211("enter\n");
7315 IWL_DEBUG_MAC80211("leave\n");
7316
7317 return 0;
7318}
7319
bb8c093b 7320static u64 iwl4965_mac_get_tsf(struct ieee80211_hw *hw)
b481de9c
ZY		 7321{
7322 IWL_DEBUG_MAC80211("enter\n");
7323 IWL_DEBUG_MAC80211("leave\n");
7324
7325 return 0;
7326}
7327
bb8c093b 7328static void iwl4965_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 7329{
c79dd5b5 7330 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 7331 unsigned long flags;
7332
7333 mutex_lock(&priv->mutex);
7334 IWL_DEBUG_MAC80211("enter\n");
7335
7336 priv->lq_mngr.lq_ready = 0;
c8b0e6e1 7337#ifdef CONFIG_IWL4965_HT
b481de9c 7338 spin_lock_irqsave(&priv->lock, flags);
fd105e79 7339 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info));
b481de9c 7340 spin_unlock_irqrestore(&priv->lock, flags);
c8b0e6e1 7341#endif /* CONFIG_IWL4965_HT */
b481de9c 7342
bf85ea4f 7343 iwlcore_reset_qos(priv);
b481de9c
ZY		 7344
7345 cancel_delayed_work(&priv->post_associate);
7346
7347 spin_lock_irqsave(&priv->lock, flags);
7348 priv->assoc_id = 0;
7349 priv->assoc_capability = 0;
b481de9c
ZY		 7350 priv->assoc_station_added = 0;
7351
7352 /* new association get rid of ibss beacon skb */
7353 if (priv->ibss_beacon)
7354 dev_kfree_skb(priv->ibss_beacon);
7355
7356 priv->ibss_beacon = NULL;
7357
7358 priv->beacon_int = priv->hw->conf.beacon_int;
3109ece1 7359 priv->timestamp = 0;
b481de9c
ZY		 7360 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
7361 priv->beacon_int = 0;
7362
7363 spin_unlock_irqrestore(&priv->lock, flags);
7364
fde3571f
MA		 7365 if (!iwl4965_is_ready_rf(priv)) {
7366 IWL_DEBUG_MAC80211("leave - not ready\n");
7367 mutex_unlock(&priv->mutex);
7368 return;
7369 }
7370
052c4b9f 7371 /* we are restarting association process
7372 * clear RXON_FILTER_ASSOC_MSK bit
7373 */
7374 if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
bb8c093b 7375 iwl4965_scan_cancel_timeout(priv, 100);
052c4b9f 7376 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
bb8c093b 7377 iwl4965_commit_rxon(priv);
052c4b9f 7378 }
7379
b481de9c
ZY		 7380 /* Per mac80211.h: This is only used in IBSS mode... */
7381 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
052c4b9f 7382
b481de9c
ZY		 7383 IWL_DEBUG_MAC80211("leave - not in IBSS\n");
7384 mutex_unlock(&priv->mutex);
7385 return;
7386 }
7387
b481de9c
ZY		 7388 priv->only_active_channel = 0;
7389
bb8c093b 7390 iwl4965_set_rate(priv);
b481de9c
ZY		 7391
7392 mutex_unlock(&priv->mutex);
7393
7394 IWL_DEBUG_MAC80211("leave\n");
b481de9c
ZY		 7395}
7396
bb8c093b 7397static int iwl4965_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
b481de9c
ZY		 7398 struct ieee80211_tx_control *control)
7399{
c79dd5b5 7400 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 7401 unsigned long flags;
7402
7403 mutex_lock(&priv->mutex);
7404 IWL_DEBUG_MAC80211("enter\n");
7405
bb8c093b 7406 if (!iwl4965_is_ready_rf(priv)) {
b481de9c
ZY		 7407 IWL_DEBUG_MAC80211("leave - RF not ready\n");
7408 mutex_unlock(&priv->mutex);
7409 return -EIO;
7410 }
7411
7412 if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
7413 IWL_DEBUG_MAC80211("leave - not IBSS\n");
7414 mutex_unlock(&priv->mutex);
7415 return -EIO;
7416 }
7417
7418 spin_lock_irqsave(&priv->lock, flags);
7419
7420 if (priv->ibss_beacon)
7421 dev_kfree_skb(priv->ibss_beacon);
7422
7423 priv->ibss_beacon = skb;
7424
7425 priv->assoc_id = 0;
7426
7427 IWL_DEBUG_MAC80211("leave\n");
7428 spin_unlock_irqrestore(&priv->lock, flags);
7429
bf85ea4f 7430 iwlcore_reset_qos(priv);
b481de9c
ZY		 7431
7432 queue_work(priv->workqueue, &priv->post_associate.work);
7433
7434 mutex_unlock(&priv->mutex);
7435
7436 return 0;
7437}
7438
b481de9c
ZY		 7439/*****************************************************************************
7440 *
7441 * sysfs attributes
7442 *
7443 *****************************************************************************/
7444
0a6857e7 7445#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 7446
7447/*
7448 * The following adds a new attribute to the sysfs representation
7449 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
7450 * used for controlling the debug level.
7451 *
7452 * See the level definitions in iwl for details.
7453 */
7454
7455static ssize_t show_debug_level(struct device_driver *d, char *buf)
7456{
0a6857e7 7457 return sprintf(buf, "0x%08X\n", iwl_debug_level);
b481de9c
ZY		 7458}
7459static ssize_t store_debug_level(struct device_driver *d,
7460 const char *buf, size_t count)
7461{
7462 char *p = (char *)buf;
7463 u32 val;
7464
7465 val = simple_strtoul(p, &p, 0);
7466 if (p == buf)
7467 printk(KERN_INFO DRV_NAME
7468 ": %s is not in hex or decimal form.\n", buf);
7469 else
0a6857e7 7470 iwl_debug_level = val;
b481de9c
ZY		 7471
7472 return strnlen(buf, count);
7473}
7474
7475static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
7476 show_debug_level, store_debug_level);
7477
0a6857e7 7478#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 7479
b481de9c
ZY		 7480
7481static ssize_t show_temperature(struct device *d,
7482 struct device_attribute *attr, char *buf)
7483{
c79dd5b5 7484 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c 7485
bb8c093b 7486 if (!iwl4965_is_alive(priv))
b481de9c
ZY		 7487 return -EAGAIN;
7488
bb8c093b 7489 return sprintf(buf, "%d\n", iwl4965_hw_get_temperature(priv));
b481de9c
ZY		 7490}
7491
7492static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
7493
7494static ssize_t show_rs_window(struct device *d,
7495 struct device_attribute *attr,
7496 char *buf)
7497{
c79dd5b5 7498 struct iwl_priv *priv = d->driver_data;
bb8c093b 7499 return iwl4965_fill_rs_info(priv->hw, buf, IWL_AP_ID);
b481de9c
ZY		 7500}
7501static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
7502
7503static ssize_t show_tx_power(struct device *d,
7504 struct device_attribute *attr, char *buf)
7505{
c79dd5b5 7506 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY		 7507 return sprintf(buf, "%d\n", priv->user_txpower_limit);
7508}
7509
7510static ssize_t store_tx_power(struct device *d,
7511 struct device_attribute *attr,
7512 const char *buf, size_t count)
7513{
c79dd5b5 7514 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY		 7515 char *p = (char *)buf;
7516 u32 val;
7517
7518 val = simple_strtoul(p, &p, 10);
7519 if (p == buf)
7520 printk(KERN_INFO DRV_NAME
7521 ": %s is not in decimal form.\n", buf);
7522 else
bb8c093b 7523 iwl4965_hw_reg_set_txpower(priv, val);
b481de9c
ZY		 7524
7525 return count;
7526}
7527
7528static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
7529
7530static ssize_t show_flags(struct device *d,
7531 struct device_attribute *attr, char *buf)
7532{
c79dd5b5 7533 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY		 7534
7535 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
7536}
7537
7538static ssize_t store_flags(struct device *d,
7539 struct device_attribute *attr,
7540 const char *buf, size_t count)
7541{
c79dd5b5 7542 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY		 7543 u32 flags = simple_strtoul(buf, NULL, 0);
7544
7545 mutex_lock(&priv->mutex);
7546 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
7547 /* Cancel any currently running scans... */
bb8c093b 7548 if (iwl4965_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7549 IWL_WARNING("Could not cancel scan.\n");
7550 else {
7551 IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
7552 flags);
7553 priv->staging_rxon.flags = cpu_to_le32(flags);
bb8c093b 7554 iwl4965_commit_rxon(priv);
b481de9c
ZY		 7555 }
7556 }
7557 mutex_unlock(&priv->mutex);
7558
7559 return count;
7560}
7561
7562static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
7563
7564static ssize_t show_filter_flags(struct device *d,
7565 struct device_attribute *attr, char *buf)
7566{
c79dd5b5 7567 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY		 7568
7569 return sprintf(buf, "0x%04X\n",
7570 le32_to_cpu(priv->active_rxon.filter_flags));
7571}
7572
7573static ssize_t store_filter_flags(struct device *d,
7574 struct device_attribute *attr,
7575 const char *buf, size_t count)
7576{
c79dd5b5 7577 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY		 7578 u32 filter_flags = simple_strtoul(buf, NULL, 0);
7579
7580 mutex_lock(&priv->mutex);
7581 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
7582 /* Cancel any currently running scans... */
bb8c093b 7583 if (iwl4965_scan_cancel_timeout(priv, 100))
b481de9c
ZY		 7584 IWL_WARNING("Could not cancel scan.\n");
7585 else {
7586 IWL_DEBUG_INFO("Committing rxon.filter_flags = "
7587 "0x%04X\n", filter_flags);
7588 priv->staging_rxon.filter_flags =
7589 cpu_to_le32(filter_flags);
bb8c093b 7590 iwl4965_commit_rxon(priv);
b481de9c
ZY		 7591 }
7592 }
7593 mutex_unlock(&priv->mutex);
7594
7595 return count;
7596}
7597
7598static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
7599 store_filter_flags);
7600
c8b0e6e1 7601#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7602
7603static ssize_t show_measurement(struct device *d,
7604 struct device_attribute *attr, char *buf)
7605{
c79dd5b5 7606 struct iwl_priv *priv = dev_get_drvdata(d);
bb8c093b 7607 struct iwl4965_spectrum_notification measure_report;
b481de9c
ZY		 7608 u32 size = sizeof(measure_report), len = 0, ofs = 0;
7609 u8 *data = (u8 *) & measure_report;
7610 unsigned long flags;
7611
7612 spin_lock_irqsave(&priv->lock, flags);
7613 if (!(priv->measurement_status & MEASUREMENT_READY)) {
7614 spin_unlock_irqrestore(&priv->lock, flags);
7615 return 0;
7616 }
7617 memcpy(&measure_report, &priv->measure_report, size);
7618 priv->measurement_status = 0;
7619 spin_unlock_irqrestore(&priv->lock, flags);
7620
7621 while (size && (PAGE_SIZE - len)) {
7622 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7623 PAGE_SIZE - len, 1);
7624 len = strlen(buf);
7625 if (PAGE_SIZE - len)
7626 buf[len++] = '\n';
7627
7628 ofs += 16;
7629 size -= min(size, 16U);
7630 }
7631
7632 return len;
7633}
7634
7635static ssize_t store_measurement(struct device *d,
7636 struct device_attribute *attr,
7637 const char *buf, size_t count)
7638{
c79dd5b5 7639 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7640 struct ieee80211_measurement_params params = {
7641 .channel = le16_to_cpu(priv->active_rxon.channel),
7642 .start_time = cpu_to_le64(priv->last_tsf),
7643 .duration = cpu_to_le16(1),
7644 };
7645 u8 type = IWL_MEASURE_BASIC;
7646 u8 buffer[32];
7647 u8 channel;
7648
7649 if (count) {
7650 char *p = buffer;
7651 strncpy(buffer, buf, min(sizeof(buffer), count));
7652 channel = simple_strtoul(p, NULL, 0);
7653 if (channel)
7654 params.channel = channel;
7655
7656 p = buffer;
7657 while (*p && *p != ' ')
7658 p++;
7659 if (*p)
7660 type = simple_strtoul(p + 1, NULL, 0);
7661 }
7662
7663 IWL_DEBUG_INFO("Invoking measurement of type %d on "
7664 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 7665 iwl4965_get_measurement(priv, &params, type);
b481de9c
ZY		 7666
7667 return count;
7668}
7669
7670static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
7671 show_measurement, store_measurement);
c8b0e6e1 7672#endif /* CONFIG_IWL4965_SPECTRUM_MEASUREMENT */
b481de9c
ZY		 7673
7674static ssize_t store_retry_rate(struct device *d,
7675 struct device_attribute *attr,
7676 const char *buf, size_t count)
7677{
c79dd5b5 7678 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7679
7680 priv->retry_rate = simple_strtoul(buf, NULL, 0);
7681 if (priv->retry_rate <= 0)
7682 priv->retry_rate = 1;
7683
7684 return count;
7685}
7686
7687static ssize_t show_retry_rate(struct device *d,
7688 struct device_attribute *attr, char *buf)
7689{
c79dd5b5 7690 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7691 return sprintf(buf, "%d", priv->retry_rate);
7692}
7693
7694static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
7695 store_retry_rate);
7696
7697static ssize_t store_power_level(struct device *d,
7698 struct device_attribute *attr,
7699 const char *buf, size_t count)
7700{
c79dd5b5 7701 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7702 int rc;
7703 int mode;
7704
7705 mode = simple_strtoul(buf, NULL, 0);
7706 mutex_lock(&priv->mutex);
7707
bb8c093b 7708 if (!iwl4965_is_ready(priv)) {
b481de9c
ZY		 7709 rc = -EAGAIN;
7710 goto out;
7711 }
7712
7713 if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
7714 mode = IWL_POWER_AC;
7715 else
7716 mode |= IWL_POWER_ENABLED;
7717
7718 if (mode != priv->power_mode) {
bb8c093b 7719 rc = iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(mode));
b481de9c
ZY		 7720 if (rc) {
7721 IWL_DEBUG_MAC80211("failed setting power mode.\n");
7722 goto out;
7723 }
7724 priv->power_mode = mode;
7725 }
7726
7727 rc = count;
7728
7729 out:
7730 mutex_unlock(&priv->mutex);
7731 return rc;
7732}
7733
7734#define MAX_WX_STRING 80
7735
7736/* Values are in microsecond */
7737static const s32 timeout_duration[] = {
7738 350000,
7739 250000,
7740 75000,
7741 37000,
7742 25000,
7743};
7744static const s32 period_duration[] = {
7745 400000,
7746 700000,
7747 1000000,
7748 1000000,
7749 1000000
7750};
7751
7752static ssize_t show_power_level(struct device *d,
7753 struct device_attribute *attr, char *buf)
7754{
c79dd5b5 7755 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7756 int level = IWL_POWER_LEVEL(priv->power_mode);
7757 char *p = buf;
7758
7759 p += sprintf(p, "%d ", level);
7760 switch (level) {
7761 case IWL_POWER_MODE_CAM:
7762 case IWL_POWER_AC:
7763 p += sprintf(p, "(AC)");
7764 break;
7765 case IWL_POWER_BATTERY:
7766 p += sprintf(p, "(BATTERY)");
7767 break;
7768 default:
7769 p += sprintf(p,
7770 "(Timeout %dms, Period %dms)",
7771 timeout_duration[level - 1] / 1000,
7772 period_duration[level - 1] / 1000);
7773 }
7774
7775 if (!(priv->power_mode & IWL_POWER_ENABLED))
7776 p += sprintf(p, " OFF\n");
7777 else
7778 p += sprintf(p, " \n");
7779
7780 return (p - buf + 1);
7781
7782}
7783
7784static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
7785 store_power_level);
7786
7787static ssize_t show_channels(struct device *d,
7788 struct device_attribute *attr, char *buf)
7789{
8318d78a
JB		 7790 /* all this shit doesn't belong into sysfs anyway */
7791 return 0;
b481de9c
ZY		 7792}
7793
7794static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
7795
7796static ssize_t show_statistics(struct device *d,
7797 struct device_attribute *attr, char *buf)
7798{
c79dd5b5 7799 struct iwl_priv *priv = dev_get_drvdata(d);
bb8c093b 7800 u32 size = sizeof(struct iwl4965_notif_statistics);
b481de9c
ZY		 7801 u32 len = 0, ofs = 0;
7802 u8 *data = (u8 *) & priv->statistics;
7803 int rc = 0;
7804
bb8c093b 7805 if (!iwl4965_is_alive(priv))
b481de9c
ZY		 7806 return -EAGAIN;
7807
7808 mutex_lock(&priv->mutex);
bb8c093b 7809 rc = iwl4965_send_statistics_request(priv);
b481de9c
ZY		 7810 mutex_unlock(&priv->mutex);
7811
7812 if (rc) {
7813 len = sprintf(buf,
7814 "Error sending statistics request: 0x%08X\n", rc);
7815 return len;
7816 }
7817
7818 while (size && (PAGE_SIZE - len)) {
7819 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
7820 PAGE_SIZE - len, 1);
7821 len = strlen(buf);
7822 if (PAGE_SIZE - len)
7823 buf[len++] = '\n';
7824
7825 ofs += 16;
7826 size -= min(size, 16U);
7827 }
7828
7829 return len;
7830}
7831
7832static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
7833
7834static ssize_t show_antenna(struct device *d,
7835 struct device_attribute *attr, char *buf)
7836{
c79dd5b5 7837 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 7838
bb8c093b 7839 if (!iwl4965_is_alive(priv))
b481de9c
ZY		 7840 return -EAGAIN;
7841
7842 return sprintf(buf, "%d\n", priv->antenna);
7843}
7844
7845static ssize_t store_antenna(struct device *d,
7846 struct device_attribute *attr,
7847 const char *buf, size_t count)
7848{
7849 int ant;
c79dd5b5 7850 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY		 7851
7852 if (count == 0)
7853 return 0;
7854
7855 if (sscanf(buf, "%1i", &ant) != 1) {
7856 IWL_DEBUG_INFO("not in hex or decimal form.\n");
7857 return count;
7858 }
7859
7860 if ((ant >= 0) && (ant <= 2)) {
7861 IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
bb8c093b 7862 priv->antenna = (enum iwl4965_antenna)ant;
b481de9c
ZY		 7863 } else
7864 IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
7865
7866
7867 return count;
7868}
7869
7870static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
7871
7872static ssize_t show_status(struct device *d,
7873 struct device_attribute *attr, char *buf)
7874{
c79dd5b5 7875 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
bb8c093b 7876 if (!iwl4965_is_alive(priv))
b481de9c
ZY		 7877 return -EAGAIN;
7878 return sprintf(buf, "0x%08x\n", (int)priv->status);
7879}
7880
7881static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
7882
7883static ssize_t dump_error_log(struct device *d,
7884 struct device_attribute *attr,
7885 const char *buf, size_t count)
7886{
7887 char *p = (char *)buf;
7888
7889 if (p[0] == '1')
c79dd5b5 7890 iwl4965_dump_nic_error_log((struct iwl_priv *)d->driver_data);
b481de9c
ZY		 7891
7892 return strnlen(buf, count);
7893}
7894
7895static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
7896
7897static ssize_t dump_event_log(struct device *d,
7898 struct device_attribute *attr,
7899 const char *buf, size_t count)
7900{
7901 char *p = (char *)buf;
7902
7903 if (p[0] == '1')
c79dd5b5 7904 iwl4965_dump_nic_event_log((struct iwl_priv *)d->driver_data);
b481de9c
ZY		 7905
7906 return strnlen(buf, count);
7907}
7908
7909static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
7910
7911/*****************************************************************************
7912 *
7913 * driver setup and teardown
7914 *
7915 *****************************************************************************/
7916
c79dd5b5 7917static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 7918{
7919 priv->workqueue = create_workqueue(DRV_NAME);
7920
7921 init_waitqueue_head(&priv->wait_command_queue);
7922
bb8c093b
CH		 7923 INIT_WORK(&priv->up, iwl4965_bg_up);
7924 INIT_WORK(&priv->restart, iwl4965_bg_restart);
7925 INIT_WORK(&priv->rx_replenish, iwl4965_bg_rx_replenish);
7926 INIT_WORK(&priv->scan_completed, iwl4965_bg_scan_completed);
7927 INIT_WORK(&priv->request_scan, iwl4965_bg_request_scan);
7928 INIT_WORK(&priv->abort_scan, iwl4965_bg_abort_scan);
7929 INIT_WORK(&priv->rf_kill, iwl4965_bg_rf_kill);
7930 INIT_WORK(&priv->beacon_update, iwl4965_bg_beacon_update);
7931 INIT_DELAYED_WORK(&priv->post_associate, iwl4965_bg_post_associate);
7932 INIT_DELAYED_WORK(&priv->init_alive_start, iwl4965_bg_init_alive_start);
7933 INIT_DELAYED_WORK(&priv->alive_start, iwl4965_bg_alive_start);
7934 INIT_DELAYED_WORK(&priv->scan_check, iwl4965_bg_scan_check);
7935
7936 iwl4965_hw_setup_deferred_work(priv);
b481de9c
ZY		 7937
7938 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 7939 iwl4965_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 7940}
7941
c79dd5b5 7942static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 7943{
bb8c093b 7944 iwl4965_hw_cancel_deferred_work(priv);
b481de9c 7945
3ae6a054 7946 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY		 7947 cancel_delayed_work(&priv->scan_check);
7948 cancel_delayed_work(&priv->alive_start);
7949 cancel_delayed_work(&priv->post_associate);
7950 cancel_work_sync(&priv->beacon_update);
7951}
7952
bb8c093b 7953static struct attribute *iwl4965_sysfs_entries[] = {
b481de9c
ZY		 7954 &dev_attr_antenna.attr,
7955 &dev_attr_channels.attr,
7956 &dev_attr_dump_errors.attr,
7957 &dev_attr_dump_events.attr,
7958 &dev_attr_flags.attr,
7959 &dev_attr_filter_flags.attr,
c8b0e6e1 7960#ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
b481de9c
ZY		 7961 &dev_attr_measurement.attr,
7962#endif
7963 &dev_attr_power_level.attr,
7964 &dev_attr_retry_rate.attr,
b481de9c
ZY		 7965 &dev_attr_rs_window.attr,
7966 &dev_attr_statistics.attr,
7967 &dev_attr_status.attr,
7968 &dev_attr_temperature.attr,
b481de9c
ZY		 7969 &dev_attr_tx_power.attr,
7970
7971 NULL
7972};
7973
bb8c093b 7974static struct attribute_group iwl4965_attribute_group = {
b481de9c 7975 .name = NULL, /* put in device directory */
bb8c093b 7976 .attrs = iwl4965_sysfs_entries,
b481de9c
ZY		 7977};
7978
bb8c093b
CH		 7979static struct ieee80211_ops iwl4965_hw_ops = {
7980 .tx = iwl4965_mac_tx,
7981 .start = iwl4965_mac_start,
7982 .stop = iwl4965_mac_stop,
7983 .add_interface = iwl4965_mac_add_interface,
7984 .remove_interface = iwl4965_mac_remove_interface,
7985 .config = iwl4965_mac_config,
7986 .config_interface = iwl4965_mac_config_interface,
7987 .configure_filter = iwl4965_configure_filter,
7988 .set_key = iwl4965_mac_set_key,
ab885f8c 7989 .update_tkip_key = iwl4965_mac_update_tkip_key,
bb8c093b
CH		 7990 .get_stats = iwl4965_mac_get_stats,
7991 .get_tx_stats = iwl4965_mac_get_tx_stats,
7992 .conf_tx = iwl4965_mac_conf_tx,
7993 .get_tsf = iwl4965_mac_get_tsf,
7994 .reset_tsf = iwl4965_mac_reset_tsf,
7995 .beacon_update = iwl4965_mac_beacon_update,
471b3efd 7996 .bss_info_changed = iwl4965_bss_info_changed,
c8b0e6e1 7997#ifdef CONFIG_IWL4965_HT
9ab46173 7998 .ampdu_action = iwl4965_mac_ampdu_action,
c8b0e6e1 7999#endif /* CONFIG_IWL4965_HT */
bb8c093b 8000 .hw_scan = iwl4965_mac_hw_scan
b481de9c
ZY		 8001};
8002
bb8c093b 8003static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 8004{
8005 int err = 0;
c79dd5b5 8006 struct iwl_priv *priv;
b481de9c 8007 struct ieee80211_hw *hw;
82b9a121 8008 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 8009 unsigned long flags;
5a66926a 8010 DECLARE_MAC_BUF(mac);
b481de9c 8011
316c30d9
AK		 8012 /************************
8013 * 1. Allocating HW data
8014 ************************/
8015
6440adb5
CB		 8016 /* Disabling hardware scan means that mac80211 will perform scans
8017 * "the hard way", rather than using device's scan. */
1ea87396 8018 if (cfg->mod_params->disable_hw_scan) {
b481de9c 8019 IWL_DEBUG_INFO("Disabling hw_scan\n");
bb8c093b 8020 iwl4965_hw_ops.hw_scan = NULL;
b481de9c
ZY		 8021 }
8022
1d0a082d
AK		 8023 hw = iwl_alloc_all(cfg, &iwl4965_hw_ops);
8024 if (!hw) {
b481de9c
ZY		 8025 err = -ENOMEM;
8026 goto out;
8027 }
1d0a082d
AK		 8028 priv = hw->priv;
8029 /* At this point both hw and priv are allocated. */
8030
b481de9c
ZY		 8031 SET_IEEE80211_DEV(hw, &pdev->dev);
8032
8033 IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
82b9a121 8034 priv->cfg = cfg;
b481de9c 8035 priv->pci_dev = pdev;
316c30d9 8036
0a6857e7 8037#ifdef CONFIG_IWLWIFI_DEBUG
1ea87396 8038 iwl_debug_level = priv->cfg->mod_params->debug;
b481de9c
ZY		 8039 atomic_set(&priv->restrict_refcnt, 0);
8040#endif
b481de9c 8041
316c30d9
AK		 8042 /**************************
8043 * 2. Initializing PCI bus
8044 **************************/
8045 if (pci_enable_device(pdev)) {
8046 err = -ENODEV;
8047 goto out_ieee80211_free_hw;
8048 }
8049
8050 pci_set_master(pdev);
8051
8052 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8053 if (!err)
8054 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
8055 if (err) {
8056 printk(KERN_WARNING DRV_NAME
8057 ": No suitable DMA available.\n");
8058 goto out_pci_disable_device;
8059 }
8060
8061 err = pci_request_regions(pdev, DRV_NAME);
8062 if (err)
8063 goto out_pci_disable_device;
8064
8065 pci_set_drvdata(pdev, priv);
8066
8067 /* We disable the RETRY_TIMEOUT register (0x41) to keep
8068 * PCI Tx retries from interfering with C3 CPU state */
8069 pci_write_config_byte(pdev, 0x41, 0x00);
8070
8071 /***********************
8072 * 3. Read REV register
8073 ***********************/
8074 priv->hw_base = pci_iomap(pdev, 0, 0);
8075 if (!priv->hw_base) {
8076 err = -ENODEV;
8077 goto out_pci_release_regions;
8078 }
8079
8080 IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
8081 (unsigned long long) pci_resource_len(pdev, 0));
8082 IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
8083
8084 printk(KERN_INFO DRV_NAME
8085 ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
8086
8087 /*****************
8088 * 4. Read EEPROM
8089 *****************/
8090 /* nic init */
3395f6e9 8091 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
316c30d9
AK		 8092 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
8093
3395f6e9
TW		 8094 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
8095 err = iwl_poll_bit(priv, CSR_GP_CNTRL,
316c30d9
AK		 8096 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
8097 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
8098 if (err < 0) {
8099 IWL_DEBUG_INFO("Failed to init the card\n");
8100 goto out_iounmap;
8101 }
8102 /* Read the EEPROM */
8103 err = iwl_eeprom_init(priv);
8104 if (err) {
8105 IWL_ERROR("Unable to init EEPROM\n");
8106 goto out_iounmap;
8107 }
8108 /* MAC Address location in EEPROM same for 3945/4965 */
8109 iwl_eeprom_get_mac(priv, priv->mac_addr);
8110 IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
8111 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
8112
8113 /************************
8114 * 5. Setup HW constants
8115 ************************/
8116 /* Device-specific setup */
8117 if (iwl4965_hw_set_hw_setting(priv)) {
8118 IWL_ERROR("failed to set hw settings\n");
8119 goto out_iounmap;
8120 }
8121
8122 /*******************
8123 * 6. Setup hw/priv
8124 *******************/
b481de9c 8125
bf85ea4f
AK		 8126 err = iwl_setup(priv);
8127 if (err)
316c30d9 8128 goto out_unset_hw_settings;
bf85ea4f 8129 /* At this point both hw and priv are initialized. */
316c30d9
AK		 8130
8131 /**********************************
8132 * 7. Initialize module parameters
8133 **********************************/
8134
8135 /* Disable radio (SW RF KILL) via parameter when loading driver */
1ea87396 8136 if (priv->cfg->mod_params->disable) {
316c30d9
AK		 8137 set_bit(STATUS_RF_KILL_SW, &priv->status);
8138 IWL_DEBUG_INFO("Radio disabled.\n");
8139 }
8140
1ea87396 8141 if (priv->cfg->mod_params->enable_qos)
316c30d9
AK		 8142 priv->qos_data.qos_enable = 1;
8143
8144 /********************
8145 * 8. Setup services
8146 ********************/
0359facc 8147 spin_lock_irqsave(&priv->lock, flags);
316c30d9 8148 iwl4965_disable_interrupts(priv);
0359facc 8149 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9
AK		 8150
8151 err = sysfs_create_group(&pdev->dev.kobj, &iwl4965_attribute_group);
8152 if (err) {
8153 IWL_ERROR("failed to create sysfs device attributes\n");
bf85ea4f 8154 goto out_unset_hw_settings;
316c30d9
AK		 8155 }
8156
8157 err = iwl_dbgfs_register(priv, DRV_NAME);
8158 if (err) {
8159 IWL_ERROR("failed to create debugfs files\n");
8160 goto out_remove_sysfs;
8161 }
8162
8163 iwl4965_setup_deferred_work(priv);
8164 iwl4965_setup_rx_handlers(priv);
8165
8166 /********************
8167 * 9. Conclude
8168 ********************/
5a66926a
ZY		 8169 pci_save_state(pdev);
8170 pci_disable_device(pdev);
b481de9c 8171
c8381fdc
MA		 8172 /* notify iwlcore to init */
8173 iwlcore_low_level_notify(priv, IWLCORE_INIT_EVT);
b481de9c
ZY		 8174 return 0;
8175
316c30d9
AK		 8176 out_remove_sysfs:
8177 sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group);
316c30d9 8178 out_unset_hw_settings:
bb8c093b 8179 iwl4965_unset_hw_setting(priv);
b481de9c
ZY		 8180 out_iounmap:
8181 pci_iounmap(pdev, priv->hw_base);
8182 out_pci_release_regions:
8183 pci_release_regions(pdev);
316c30d9 8184 pci_set_drvdata(pdev, NULL);
b481de9c
ZY		 8185 out_pci_disable_device:
8186 pci_disable_device(pdev);
b481de9c
ZY		 8187 out_ieee80211_free_hw:
8188 ieee80211_free_hw(priv->hw);
8189 out:
8190 return err;
8191}
8192
c83dbf68 8193static void __devexit iwl4965_pci_remove(struct pci_dev *pdev)
b481de9c 8194{
c79dd5b5 8195 struct iwl_priv *priv = pci_get_drvdata(pdev);
b481de9c
ZY		 8196 struct list_head *p, *q;
8197 int i;
0359facc 8198 unsigned long flags;
b481de9c
ZY		 8199
8200 if (!priv)
8201 return;
8202
8203 IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
8204
c4f55232
RR		 8205 if (priv->mac80211_registered) {
8206 ieee80211_unregister_hw(priv->hw);
8207 priv->mac80211_registered = 0;
8208 }
8209
b481de9c 8210 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 8211
bb8c093b 8212 iwl4965_down(priv);
b481de9c 8213
0359facc
MA		 8214 /* make sure we flush any pending irq or
8215 * tasklet for the driver
8216 */
8217 spin_lock_irqsave(&priv->lock, flags);
8218 iwl4965_disable_interrupts(priv);
8219 spin_unlock_irqrestore(&priv->lock, flags);
8220
8221 iwl_synchronize_irq(priv);
8222
b481de9c
ZY		 8223 /* Free MAC hash list for ADHOC */
8224 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
8225 list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
8226 list_del(p);
bb8c093b 8227 kfree(list_entry(p, struct iwl4965_ibss_seq, list));
b481de9c
ZY		 8228 }
8229 }
8230
c8381fdc 8231 iwlcore_low_level_notify(priv, IWLCORE_REMOVE_EVT);
712b6cf5 8232 iwl_dbgfs_unregister(priv);
bb8c093b 8233 sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group);
b481de9c 8234
bb8c093b 8235 iwl4965_dealloc_ucode_pci(priv);
b481de9c
ZY		 8236
8237 if (priv->rxq.bd)
bb8c093b
CH		 8238 iwl4965_rx_queue_free(priv, &priv->rxq);
8239 iwl4965_hw_txq_ctx_free(priv);
b481de9c 8240
bb8c093b 8241 iwl4965_unset_hw_setting(priv);
bf85ea4f 8242 iwlcore_clear_stations_table(priv);
b481de9c 8243
b481de9c 8244
948c171c
MA		 8245 /*netif_stop_queue(dev); */
8246 flush_workqueue(priv->workqueue);
8247
bb8c093b 8248 /* ieee80211_unregister_hw calls iwl4965_mac_stop, which flushes
b481de9c
ZY		 8249 * priv->workqueue... so we can't take down the workqueue
8250 * until now... */
8251 destroy_workqueue(priv->workqueue);
8252 priv->workqueue = NULL;
8253
b481de9c
ZY		 8254 pci_iounmap(pdev, priv->hw_base);
8255 pci_release_regions(pdev);
8256 pci_disable_device(pdev);
8257 pci_set_drvdata(pdev, NULL);
8258
bf85ea4f 8259 iwl_free_channel_map(priv);
849e0dce 8260 iwl4965_free_geos(priv);
b481de9c
ZY		 8261
8262 if (priv->ibss_beacon)
8263 dev_kfree_skb(priv->ibss_beacon);
8264
8265 ieee80211_free_hw(priv->hw);
8266}
8267
8268#ifdef CONFIG_PM
8269
bb8c093b 8270static int iwl4965_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 8271{
c79dd5b5 8272 struct iwl_priv *priv = pci_get_drvdata(pdev);
b481de9c 8273
e655b9f0
ZY		 8274 if (priv->is_open) {
8275 set_bit(STATUS_IN_SUSPEND, &priv->status);
8276 iwl4965_mac_stop(priv->hw);
8277 priv->is_open = 1;
8278 }
b481de9c 8279
b481de9c
ZY		 8280 pci_set_power_state(pdev, PCI_D3hot);
8281
b481de9c
ZY		 8282 return 0;
8283}
8284
bb8c093b 8285static int iwl4965_pci_resume(struct pci_dev *pdev)
b481de9c 8286{
c79dd5b5 8287 struct iwl_priv *priv = pci_get_drvdata(pdev);
b481de9c 8288
b481de9c 8289 pci_set_power_state(pdev, PCI_D0);
b481de9c 8290
e655b9f0
ZY		 8291 if (priv->is_open)
8292 iwl4965_mac_start(priv->hw);
b481de9c 8293
e655b9f0 8294 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 8295 return 0;
8296}
8297
8298#endif /* CONFIG_PM */
8299
8300/*****************************************************************************
8301 *
8302 * driver and module entry point
8303 *
8304 *****************************************************************************/
8305
bb8c093b 8306static struct pci_driver iwl4965_driver = {
b481de9c 8307 .name = DRV_NAME,
bb8c093b
CH		 8308 .id_table = iwl4965_hw_card_ids,
8309 .probe = iwl4965_pci_probe,
8310 .remove = __devexit_p(iwl4965_pci_remove),
b481de9c 8311#ifdef CONFIG_PM
bb8c093b
CH		 8312 .suspend = iwl4965_pci_suspend,
8313 .resume = iwl4965_pci_resume,
b481de9c
ZY		 8314#endif
8315};
8316
bb8c093b 8317static int __init iwl4965_init(void)
b481de9c
ZY		 8318{
8319
8320 int ret;
8321 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
8322 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC		 8323
8324 ret = iwl4965_rate_control_register();
8325 if (ret) {
8326 IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
8327 return ret;
8328 }
8329
bb8c093b 8330 ret = pci_register_driver(&iwl4965_driver);
b481de9c
ZY		 8331 if (ret) {
8332 IWL_ERROR("Unable to initialize PCI module\n");
897e1cf2 8333 goto error_register;
b481de9c 8334 }
0a6857e7 8335#ifdef CONFIG_IWLWIFI_DEBUG
bb8c093b 8336 ret = driver_create_file(&iwl4965_driver.driver, &driver_attr_debug_level);
b481de9c
ZY		 8337 if (ret) {
8338 IWL_ERROR("Unable to create driver sysfs file\n");
897e1cf2 8339 goto error_debug;
b481de9c
ZY		 8340 }
8341#endif
8342
8343 return ret;
897e1cf2
RC		 8344
8345#ifdef CONFIG_IWLWIFI_DEBUG
8346error_debug:
8347 pci_unregister_driver(&iwl4965_driver);
8348#endif
8349error_register:
8350 iwl4965_rate_control_unregister();
8351 return ret;
b481de9c
ZY		 8352}
8353
bb8c093b 8354static void __exit iwl4965_exit(void)
b481de9c 8355{
0a6857e7 8356#ifdef CONFIG_IWLWIFI_DEBUG
bb8c093b 8357 driver_remove_file(&iwl4965_driver.driver, &driver_attr_debug_level);
b481de9c 8358#endif
bb8c093b 8359 pci_unregister_driver(&iwl4965_driver);
897e1cf2 8360 iwl4965_rate_control_unregister();
b481de9c
ZY		 8361}
8362
bb8c093b
CH		 8363module_exit(iwl4965_exit);
8364module_init(iwl4965_init);
Linux kernel - Deliverables
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