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8ca151b5 JB |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 9 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
8ca151b5 JB |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
23 | * USA | |
24 | * | |
25 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 26 | * in the file called COPYING. |
8ca151b5 JB |
27 | * |
28 | * Contact Information: | |
29 | * Intel Linux Wireless <ilw@linux.intel.com> | |
30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
31 | * | |
32 | * BSD LICENSE | |
33 | * | |
51368bf7 | 34 | * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 35 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
8ca151b5 JB |
36 | * All rights reserved. |
37 | * | |
38 | * Redistribution and use in source and binary forms, with or without | |
39 | * modification, are permitted provided that the following conditions | |
40 | * are met: | |
41 | * | |
42 | * * Redistributions of source code must retain the above copyright | |
43 | * notice, this list of conditions and the following disclaimer. | |
44 | * * Redistributions in binary form must reproduce the above copyright | |
45 | * notice, this list of conditions and the following disclaimer in | |
46 | * the documentation and/or other materials provided with the | |
47 | * distribution. | |
48 | * * Neither the name Intel Corporation nor the names of its | |
49 | * contributors may be used to endorse or promote products derived | |
50 | * from this software without specific prior written permission. | |
51 | * | |
52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
63 | * | |
64 | *****************************************************************************/ | |
1214755c | 65 | #include <linux/firmware.h> |
90d4f7db | 66 | #include <linux/rtnetlink.h> |
7f0344c2 JD |
67 | #include <linux/pci.h> |
68 | #include <linux/acpi.h> | |
8ca151b5 | 69 | #include "iwl-trans.h" |
c2a2b28b | 70 | #include "iwl-csr.h" |
8ca151b5 JB |
71 | #include "mvm.h" |
72 | #include "iwl-eeprom-parse.h" | |
73 | #include "iwl-eeprom-read.h" | |
74 | #include "iwl-nvm-parse.h" | |
8ba2d7a1 | 75 | #include "iwl-prph.h" |
8ca151b5 | 76 | |
1fd4afe2 | 77 | /* Default NVM size to read */ |
1214755c | 78 | #define IWL_NVM_DEFAULT_CHUNK_SIZE (2*1024) |
f251c07c | 79 | #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 |
5dd9c68a | 80 | #define IWL_MAX_NVM_8000_SECTION_SIZE 0x1ffc |
1fd4afe2 | 81 | |
1214755c EH |
82 | #define NVM_WRITE_OPCODE 1 |
83 | #define NVM_READ_OPCODE 0 | |
84 | ||
d6aeb354 EH |
85 | /* load nvm chunk response */ |
86 | enum { | |
87 | READ_NVM_CHUNK_SUCCEED = 0, | |
88 | READ_NVM_CHUNK_NOT_VALID_ADDRESS = 1 | |
89 | }; | |
90 | ||
1214755c EH |
91 | /* |
92 | * prepare the NVM host command w/ the pointers to the nvm buffer | |
93 | * and send it to fw | |
94 | */ | |
95 | static int iwl_nvm_write_chunk(struct iwl_mvm *mvm, u16 section, | |
96 | u16 offset, u16 length, const u8 *data) | |
8ca151b5 | 97 | { |
1214755c EH |
98 | struct iwl_nvm_access_cmd nvm_access_cmd = { |
99 | .offset = cpu_to_le16(offset), | |
100 | .length = cpu_to_le16(length), | |
101 | .type = cpu_to_le16(section), | |
102 | .op_code = NVM_WRITE_OPCODE, | |
103 | }; | |
104 | struct iwl_host_cmd cmd = { | |
105 | .id = NVM_ACCESS_CMD, | |
106 | .len = { sizeof(struct iwl_nvm_access_cmd), length }, | |
a1022927 | 107 | .flags = CMD_SEND_IN_RFKILL, |
1214755c EH |
108 | .data = { &nvm_access_cmd, data }, |
109 | /* data may come from vmalloc, so use _DUP */ | |
110 | .dataflags = { 0, IWL_HCMD_DFL_DUP }, | |
111 | }; | |
112 | ||
113 | return iwl_mvm_send_cmd(mvm, &cmd); | |
8ca151b5 JB |
114 | } |
115 | ||
116 | static int iwl_nvm_read_chunk(struct iwl_mvm *mvm, u16 section, | |
117 | u16 offset, u16 length, u8 *data) | |
118 | { | |
1214755c EH |
119 | struct iwl_nvm_access_cmd nvm_access_cmd = { |
120 | .offset = cpu_to_le16(offset), | |
121 | .length = cpu_to_le16(length), | |
122 | .type = cpu_to_le16(section), | |
123 | .op_code = NVM_READ_OPCODE, | |
124 | }; | |
b9545b48 | 125 | struct iwl_nvm_access_resp *nvm_resp; |
8ca151b5 JB |
126 | struct iwl_rx_packet *pkt; |
127 | struct iwl_host_cmd cmd = { | |
128 | .id = NVM_ACCESS_CMD, | |
a1022927 | 129 | .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, |
8ca151b5 JB |
130 | .data = { &nvm_access_cmd, }, |
131 | }; | |
132 | int ret, bytes_read, offset_read; | |
133 | u8 *resp_data; | |
134 | ||
b9545b48 | 135 | cmd.len[0] = sizeof(struct iwl_nvm_access_cmd); |
8ca151b5 JB |
136 | |
137 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
138 | if (ret) | |
139 | return ret; | |
140 | ||
141 | pkt = cmd.resp_pkt; | |
142 | if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { | |
143 | IWL_ERR(mvm, "Bad return from NVM_ACCES_COMMAND (0x%08X)\n", | |
144 | pkt->hdr.flags); | |
145 | ret = -EIO; | |
146 | goto exit; | |
147 | } | |
148 | ||
149 | /* Extract NVM response */ | |
150 | nvm_resp = (void *)pkt->data; | |
b9545b48 EG |
151 | ret = le16_to_cpu(nvm_resp->status); |
152 | bytes_read = le16_to_cpu(nvm_resp->length); | |
153 | offset_read = le16_to_cpu(nvm_resp->offset); | |
154 | resp_data = nvm_resp->data; | |
8ca151b5 | 155 | if (ret) { |
d6aeb354 EH |
156 | if ((offset != 0) && |
157 | (ret == READ_NVM_CHUNK_NOT_VALID_ADDRESS)) { | |
158 | /* | |
159 | * meaning of NOT_VALID_ADDRESS: | |
160 | * driver try to read chunk from address that is | |
161 | * multiple of 2K and got an error since addr is empty. | |
162 | * meaning of (offset != 0): driver already | |
163 | * read valid data from another chunk so this case | |
164 | * is not an error. | |
165 | */ | |
166 | IWL_DEBUG_EEPROM(mvm->trans->dev, | |
167 | "NVM access command failed on offset 0x%x since that section size is multiple 2K\n", | |
168 | offset); | |
169 | ret = 0; | |
170 | } else { | |
171 | IWL_DEBUG_EEPROM(mvm->trans->dev, | |
172 | "NVM access command failed with status %d (device: %s)\n", | |
173 | ret, mvm->cfg->name); | |
174 | ret = -EIO; | |
175 | } | |
8ca151b5 JB |
176 | goto exit; |
177 | } | |
178 | ||
179 | if (offset_read != offset) { | |
180 | IWL_ERR(mvm, "NVM ACCESS response with invalid offset %d\n", | |
181 | offset_read); | |
182 | ret = -EINVAL; | |
183 | goto exit; | |
184 | } | |
185 | ||
186 | /* Write data to NVM */ | |
187 | memcpy(data + offset, resp_data, bytes_read); | |
188 | ret = bytes_read; | |
189 | ||
190 | exit: | |
191 | iwl_free_resp(&cmd); | |
192 | return ret; | |
193 | } | |
194 | ||
1214755c EH |
195 | static int iwl_nvm_write_section(struct iwl_mvm *mvm, u16 section, |
196 | const u8 *data, u16 length) | |
197 | { | |
198 | int offset = 0; | |
199 | ||
200 | /* copy data in chunks of 2k (and remainder if any) */ | |
201 | ||
202 | while (offset < length) { | |
203 | int chunk_size, ret; | |
204 | ||
205 | chunk_size = min(IWL_NVM_DEFAULT_CHUNK_SIZE, | |
206 | length - offset); | |
207 | ||
208 | ret = iwl_nvm_write_chunk(mvm, section, offset, | |
209 | chunk_size, data + offset); | |
210 | if (ret < 0) | |
211 | return ret; | |
212 | ||
213 | offset += chunk_size; | |
214 | } | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
8ca151b5 JB |
219 | /* |
220 | * Reads an NVM section completely. | |
221 | * NICs prior to 7000 family doesn't have a real NVM, but just read | |
222 | * section 0 which is the EEPROM. Because the EEPROM reading is unlimited | |
223 | * by uCode, we need to manually check in this case that we don't | |
224 | * overflow and try to read more than the EEPROM size. | |
225 | * For 7000 family NICs, we supply the maximal size we can read, and | |
226 | * the uCode fills the response with as much data as we can, | |
227 | * without overflowing, so no check is needed. | |
228 | */ | |
229 | static int iwl_nvm_read_section(struct iwl_mvm *mvm, u16 section, | |
5daddc99 | 230 | u8 *data, u32 size_read) |
8ca151b5 JB |
231 | { |
232 | u16 length, offset = 0; | |
233 | int ret; | |
8ca151b5 | 234 | |
1fd4afe2 DS |
235 | /* Set nvm section read length */ |
236 | length = IWL_NVM_DEFAULT_CHUNK_SIZE; | |
237 | ||
8ca151b5 JB |
238 | ret = length; |
239 | ||
240 | /* Read the NVM until exhausted (reading less than requested) */ | |
241 | while (ret == length) { | |
5daddc99 LK |
242 | /* Check no memory assumptions fail and cause an overflow */ |
243 | if ((size_read + offset + length) > | |
244 | mvm->cfg->base_params->eeprom_size) { | |
245 | IWL_ERR(mvm, "EEPROM size is too small for NVM\n"); | |
246 | return -ENOBUFS; | |
247 | } | |
248 | ||
8ca151b5 JB |
249 | ret = iwl_nvm_read_chunk(mvm, section, offset, length, data); |
250 | if (ret < 0) { | |
d6aeb354 EH |
251 | IWL_DEBUG_EEPROM(mvm->trans->dev, |
252 | "Cannot read NVM from section %d offset %d, length %d\n", | |
253 | section, offset, length); | |
8ca151b5 JB |
254 | return ret; |
255 | } | |
256 | offset += ret; | |
8ca151b5 JB |
257 | } |
258 | ||
07fd7d28 JB |
259 | IWL_DEBUG_EEPROM(mvm->trans->dev, |
260 | "NVM section %d read completed\n", section); | |
8ca151b5 JB |
261 | return offset; |
262 | } | |
263 | ||
264 | static struct iwl_nvm_data * | |
265 | iwl_parse_nvm_sections(struct iwl_mvm *mvm) | |
266 | { | |
267 | struct iwl_nvm_section *sections = mvm->nvm_sections; | |
ce500071 | 268 | const __le16 *hw, *sw, *calib, *regulatory, *mac_override, *phy_sku; |
5dd9c68a | 269 | bool lar_enabled; |
8ba2d7a1 | 270 | u32 mac_addr0, mac_addr1; |
8ca151b5 JB |
271 | |
272 | /* Checking for required sections */ | |
77db0a3c EH |
273 | if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) { |
274 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || | |
275 | !mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data) { | |
abf09c56 | 276 | IWL_ERR(mvm, "Can't parse empty OTP/NVM sections\n"); |
77db0a3c EH |
277 | return NULL; |
278 | } | |
279 | } else { | |
9f32e017 | 280 | /* SW and REGULATORY sections are mandatory */ |
77db0a3c | 281 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data || |
77db0a3c EH |
282 | !mvm->nvm_sections[NVM_SECTION_TYPE_REGULATORY].data) { |
283 | IWL_ERR(mvm, | |
abf09c56 | 284 | "Can't parse empty family 8000 OTP/NVM sections\n"); |
77db0a3c EH |
285 | return NULL; |
286 | } | |
9f32e017 | 287 | /* MAC_OVERRIDE or at least HW section must exist */ |
bb926924 | 288 | if (!mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data && |
9f32e017 EH |
289 | !mvm->nvm_sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data) { |
290 | IWL_ERR(mvm, | |
291 | "Can't parse mac_address, empty sections\n"); | |
292 | return NULL; | |
293 | } | |
ce500071 | 294 | |
ce500071 | 295 | /* PHY_SKU section is mandatory in B0 */ |
5dd9c68a | 296 | if (!mvm->nvm_sections[NVM_SECTION_TYPE_PHY_SKU].data) { |
ce500071 EH |
297 | IWL_ERR(mvm, |
298 | "Can't parse phy_sku in B0, empty sections\n"); | |
299 | return NULL; | |
300 | } | |
8ca151b5 JB |
301 | } |
302 | ||
303 | if (WARN_ON(!mvm->cfg)) | |
304 | return NULL; | |
305 | ||
8ba2d7a1 EH |
306 | /* read the mac address from WFMP registers */ |
307 | mac_addr0 = iwl_trans_read_prph(mvm->trans, WFMP_MAC_ADDR_0); | |
308 | mac_addr1 = iwl_trans_read_prph(mvm->trans, WFMP_MAC_ADDR_1); | |
309 | ||
ae2b21b0 | 310 | hw = (const __le16 *)sections[mvm->cfg->nvm_hw_section_num].data; |
8ca151b5 JB |
311 | sw = (const __le16 *)sections[NVM_SECTION_TYPE_SW].data; |
312 | calib = (const __le16 *)sections[NVM_SECTION_TYPE_CALIBRATION].data; | |
77db0a3c EH |
313 | regulatory = (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY].data; |
314 | mac_override = | |
315 | (const __le16 *)sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data; | |
ce500071 | 316 | phy_sku = (const __le16 *)sections[NVM_SECTION_TYPE_PHY_SKU].data; |
77db0a3c | 317 | |
5711cac4 AN |
318 | lar_enabled = !iwlwifi_mod_params.lar_disable && |
319 | (mvm->fw->ucode_capa.capa[0] & | |
320 | IWL_UCODE_TLV_CAPA_LAR_SUPPORT); | |
321 | ||
9ce4fa72 | 322 | return iwl_parse_nvm_data(mvm->trans->dev, mvm->cfg, hw, sw, calib, |
ce500071 | 323 | regulatory, mac_override, phy_sku, |
5711cac4 | 324 | mvm->fw->valid_tx_ant, mvm->fw->valid_rx_ant, |
5dd9c68a | 325 | lar_enabled, mac_addr0, mac_addr1); |
8ca151b5 JB |
326 | } |
327 | ||
1214755c EH |
328 | #define MAX_NVM_FILE_LEN 16384 |
329 | ||
330 | /* | |
81a67e32 EL |
331 | * Reads external NVM from a file into mvm->nvm_sections |
332 | * | |
1214755c EH |
333 | * HOW TO CREATE THE NVM FILE FORMAT: |
334 | * ------------------------------ | |
335 | * 1. create hex file, format: | |
336 | * 3800 -> header | |
337 | * 0000 -> header | |
338 | * 5a40 -> data | |
339 | * | |
340 | * rev - 6 bit (word1) | |
341 | * len - 10 bit (word1) | |
342 | * id - 4 bit (word2) | |
343 | * rsv - 12 bit (word2) | |
344 | * | |
345 | * 2. flip 8bits with 8 bits per line to get the right NVM file format | |
346 | * | |
347 | * 3. create binary file from the hex file | |
348 | * | |
349 | * 4. save as "iNVM_xxx.bin" under /lib/firmware | |
350 | */ | |
81a67e32 | 351 | static int iwl_mvm_read_external_nvm(struct iwl_mvm *mvm) |
1214755c | 352 | { |
81a67e32 EL |
353 | int ret, section_size; |
354 | u16 section_id; | |
1214755c EH |
355 | const struct firmware *fw_entry; |
356 | const struct { | |
357 | __le16 word1; | |
358 | __le16 word2; | |
359 | u8 data[]; | |
360 | } *file_sec; | |
81a67e32 | 361 | const u8 *eof, *temp; |
f251c07c | 362 | int max_section_size; |
a4e5df28 | 363 | const __le32 *dword_buff; |
1214755c EH |
364 | |
365 | #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) | |
366 | #define NVM_WORD2_ID(x) (x >> 12) | |
77db0a3c EH |
367 | #define NVM_WORD2_LEN_FAMILY_8000(x) (2 * ((x & 0xFF) << 8 | x >> 8)) |
368 | #define NVM_WORD1_ID_FAMILY_8000(x) (x >> 4) | |
a4e5df28 IK |
369 | #define NVM_HEADER_0 (0x2A504C54) |
370 | #define NVM_HEADER_1 (0x4E564D2A) | |
371 | #define NVM_HEADER_SIZE (4 * sizeof(u32)) | |
1214755c | 372 | |
81a67e32 EL |
373 | IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from external NVM\n"); |
374 | ||
f251c07c LK |
375 | /* Maximal size depends on HW family and step */ |
376 | if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) | |
377 | max_section_size = IWL_MAX_NVM_SECTION_SIZE; | |
5dd9c68a EG |
378 | else |
379 | max_section_size = IWL_MAX_NVM_8000_SECTION_SIZE; | |
f251c07c | 380 | |
1214755c EH |
381 | /* |
382 | * Obtain NVM image via request_firmware. Since we already used | |
383 | * request_firmware_nowait() for the firmware binary load and only | |
384 | * get here after that we assume the NVM request can be satisfied | |
385 | * synchronously. | |
386 | */ | |
e02a9d60 | 387 | ret = request_firmware(&fw_entry, mvm->nvm_file_name, |
1214755c EH |
388 | mvm->trans->dev); |
389 | if (ret) { | |
390 | IWL_ERR(mvm, "ERROR: %s isn't available %d\n", | |
e02a9d60 | 391 | mvm->nvm_file_name, ret); |
1214755c EH |
392 | return ret; |
393 | } | |
394 | ||
395 | IWL_INFO(mvm, "Loaded NVM file %s (%zu bytes)\n", | |
e02a9d60 | 396 | mvm->nvm_file_name, fw_entry->size); |
1214755c | 397 | |
1214755c EH |
398 | if (fw_entry->size > MAX_NVM_FILE_LEN) { |
399 | IWL_ERR(mvm, "NVM file too large\n"); | |
400 | ret = -EINVAL; | |
401 | goto out; | |
402 | } | |
403 | ||
404 | eof = fw_entry->data + fw_entry->size; | |
a4e5df28 IK |
405 | dword_buff = (__le32 *)fw_entry->data; |
406 | ||
407 | /* some NVM file will contain a header. | |
408 | * The header is identified by 2 dwords header as follow: | |
409 | * dword[0] = 0x2A504C54 | |
410 | * dword[1] = 0x4E564D2A | |
411 | * | |
412 | * This header must be skipped when providing the NVM data to the FW. | |
413 | */ | |
414 | if (fw_entry->size > NVM_HEADER_SIZE && | |
415 | dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && | |
416 | dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { | |
417 | file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE); | |
418 | IWL_INFO(mvm, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); | |
419 | IWL_INFO(mvm, "NVM Manufacturing date %08X\n", | |
420 | le32_to_cpu(dword_buff[3])); | |
d383c740 EH |
421 | |
422 | /* nvm file validation, dword_buff[2] holds the file version */ | |
423 | if ((CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_C_STEP && | |
424 | le32_to_cpu(dword_buff[2]) < 0xE4A) || | |
425 | (CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_B_STEP && | |
426 | le32_to_cpu(dword_buff[2]) >= 0xE4A)) { | |
427 | ret = -EFAULT; | |
428 | goto out; | |
429 | } | |
a4e5df28 IK |
430 | } else { |
431 | file_sec = (void *)fw_entry->data; | |
432 | } | |
1214755c EH |
433 | |
434 | while (true) { | |
435 | if (file_sec->data > eof) { | |
436 | IWL_ERR(mvm, | |
437 | "ERROR - NVM file too short for section header\n"); | |
438 | ret = -EINVAL; | |
439 | break; | |
440 | } | |
441 | ||
442 | /* check for EOF marker */ | |
443 | if (!file_sec->word1 && !file_sec->word2) { | |
444 | ret = 0; | |
445 | break; | |
446 | } | |
447 | ||
77db0a3c EH |
448 | if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) { |
449 | section_size = | |
450 | 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); | |
451 | section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); | |
452 | } else { | |
453 | section_size = 2 * NVM_WORD2_LEN_FAMILY_8000( | |
454 | le16_to_cpu(file_sec->word2)); | |
455 | section_id = NVM_WORD1_ID_FAMILY_8000( | |
456 | le16_to_cpu(file_sec->word1)); | |
457 | } | |
1214755c | 458 | |
f251c07c | 459 | if (section_size > max_section_size) { |
1214755c EH |
460 | IWL_ERR(mvm, "ERROR - section too large (%d)\n", |
461 | section_size); | |
462 | ret = -EINVAL; | |
463 | break; | |
464 | } | |
465 | ||
466 | if (!section_size) { | |
467 | IWL_ERR(mvm, "ERROR - section empty\n"); | |
468 | ret = -EINVAL; | |
469 | break; | |
470 | } | |
471 | ||
472 | if (file_sec->data + section_size > eof) { | |
473 | IWL_ERR(mvm, | |
474 | "ERROR - NVM file too short for section (%d bytes)\n", | |
475 | section_size); | |
476 | ret = -EINVAL; | |
477 | break; | |
478 | } | |
479 | ||
ae2b21b0 | 480 | if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, |
a4a12478 EL |
481 | "Invalid NVM section ID %d\n", section_id)) { |
482 | ret = -EINVAL; | |
483 | break; | |
484 | } | |
485 | ||
81a67e32 EL |
486 | temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); |
487 | if (!temp) { | |
488 | ret = -ENOMEM; | |
489 | break; | |
490 | } | |
81a67e32 EL |
491 | mvm->nvm_sections[section_id].data = temp; |
492 | mvm->nvm_sections[section_id].length = section_size; | |
1214755c EH |
493 | |
494 | /* advance to the next section */ | |
495 | file_sec = (void *)(file_sec->data + section_size); | |
496 | } | |
497 | out: | |
498 | release_firmware(fw_entry); | |
499 | return ret; | |
500 | } | |
501 | ||
81a67e32 EL |
502 | /* Loads the NVM data stored in mvm->nvm_sections into the NIC */ |
503 | int iwl_mvm_load_nvm_to_nic(struct iwl_mvm *mvm) | |
504 | { | |
05159fcc | 505 | int i, ret = 0; |
81a67e32 EL |
506 | struct iwl_nvm_section *sections = mvm->nvm_sections; |
507 | ||
508 | IWL_DEBUG_EEPROM(mvm->trans->dev, "'Write to NVM\n"); | |
509 | ||
099d8f20 EG |
510 | for (i = 0; i < ARRAY_SIZE(mvm->nvm_sections); i++) { |
511 | if (!mvm->nvm_sections[i].data || !mvm->nvm_sections[i].length) | |
512 | continue; | |
513 | ret = iwl_nvm_write_section(mvm, i, sections[i].data, | |
514 | sections[i].length); | |
81a67e32 EL |
515 | if (ret < 0) { |
516 | IWL_ERR(mvm, "iwl_mvm_send_cmd failed: %d\n", ret); | |
517 | break; | |
518 | } | |
519 | } | |
520 | return ret; | |
521 | } | |
522 | ||
14b485f0 | 523 | int iwl_nvm_init(struct iwl_mvm *mvm, bool read_nvm_from_nic) |
8ca151b5 | 524 | { |
d6aeb354 | 525 | int ret, section; |
5daddc99 | 526 | u32 size_read = 0; |
8ca151b5 | 527 | u8 *nvm_buffer, *temp; |
d383c740 EH |
528 | const char *nvm_file_B = mvm->cfg->default_nvm_file_B_step; |
529 | const char *nvm_file_C = mvm->cfg->default_nvm_file_C_step; | |
8ca151b5 | 530 | |
ae2b21b0 EH |
531 | if (WARN_ON_ONCE(mvm->cfg->nvm_hw_section_num >= NVM_MAX_NUM_SECTIONS)) |
532 | return -EINVAL; | |
533 | ||
26481bf4 | 534 | /* load NVM values from nic */ |
14b485f0 | 535 | if (read_nvm_from_nic) { |
81a67e32 EL |
536 | /* Read From FW NVM */ |
537 | IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from NVM\n"); | |
538 | ||
81a67e32 EL |
539 | nvm_buffer = kmalloc(mvm->cfg->base_params->eeprom_size, |
540 | GFP_KERNEL); | |
541 | if (!nvm_buffer) | |
542 | return -ENOMEM; | |
d6aeb354 | 543 | for (section = 0; section < NVM_MAX_NUM_SECTIONS; section++) { |
81a67e32 | 544 | /* we override the constness for initial read */ |
5daddc99 LK |
545 | ret = iwl_nvm_read_section(mvm, section, nvm_buffer, |
546 | size_read); | |
81a67e32 | 547 | if (ret < 0) |
d6aeb354 | 548 | continue; |
5daddc99 | 549 | size_read += ret; |
81a67e32 EL |
550 | temp = kmemdup(nvm_buffer, ret, GFP_KERNEL); |
551 | if (!temp) { | |
552 | ret = -ENOMEM; | |
553 | break; | |
554 | } | |
555 | mvm->nvm_sections[section].data = temp; | |
556 | mvm->nvm_sections[section].length = ret; | |
086f7368 EG |
557 | |
558 | #ifdef CONFIG_IWLWIFI_DEBUGFS | |
559 | switch (section) { | |
086f7368 EG |
560 | case NVM_SECTION_TYPE_SW: |
561 | mvm->nvm_sw_blob.data = temp; | |
562 | mvm->nvm_sw_blob.size = ret; | |
563 | break; | |
564 | case NVM_SECTION_TYPE_CALIBRATION: | |
565 | mvm->nvm_calib_blob.data = temp; | |
566 | mvm->nvm_calib_blob.size = ret; | |
567 | break; | |
568 | case NVM_SECTION_TYPE_PRODUCTION: | |
569 | mvm->nvm_prod_blob.data = temp; | |
570 | mvm->nvm_prod_blob.size = ret; | |
571 | break; | |
572 | default: | |
ae2b21b0 EH |
573 | if (section == mvm->cfg->nvm_hw_section_num) { |
574 | mvm->nvm_hw_blob.data = temp; | |
575 | mvm->nvm_hw_blob.size = ret; | |
576 | break; | |
577 | } | |
086f7368 EG |
578 | } |
579 | #endif | |
8ca151b5 | 580 | } |
bdce40f0 EH |
581 | if (!size_read) |
582 | IWL_ERR(mvm, "OTP is blank\n"); | |
81a67e32 | 583 | kfree(nvm_buffer); |
8ca151b5 JB |
584 | } |
585 | ||
26481bf4 | 586 | /* load external NVM if configured */ |
e02a9d60 | 587 | if (mvm->nvm_file_name) { |
d383c740 | 588 | /* read External NVM file - take the default */ |
26481bf4 | 589 | ret = iwl_mvm_read_external_nvm(mvm); |
d383c740 EH |
590 | if (ret) { |
591 | /* choose the nvm_file name according to the | |
592 | * HW step | |
593 | */ | |
594 | if (CSR_HW_REV_STEP(mvm->trans->hw_rev) == | |
595 | SILICON_B_STEP) | |
596 | mvm->nvm_file_name = nvm_file_B; | |
597 | else | |
598 | mvm->nvm_file_name = nvm_file_C; | |
599 | ||
600 | if (ret == -EFAULT && mvm->nvm_file_name) { | |
601 | /* in case nvm file was failed try again */ | |
602 | ret = iwl_mvm_read_external_nvm(mvm); | |
603 | if (ret) | |
604 | return ret; | |
605 | } else { | |
606 | return ret; | |
607 | } | |
608 | } | |
26481bf4 EH |
609 | } |
610 | ||
611 | /* parse the relevant nvm sections */ | |
b9545b48 | 612 | mvm->nvm_data = iwl_parse_nvm_sections(mvm); |
82598b4f JB |
613 | if (!mvm->nvm_data) |
614 | return -ENODATA; | |
2a831e08 EH |
615 | IWL_DEBUG_EEPROM(mvm->trans->dev, "nvm version = %x\n", |
616 | mvm->nvm_data->nvm_version); | |
8ca151b5 | 617 | |
82598b4f | 618 | return 0; |
8ca151b5 | 619 | } |
dcaf9f5e AN |
620 | |
621 | struct iwl_mcc_update_resp * | |
8ba2d7a1 EH |
622 | iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2, |
623 | enum iwl_mcc_source src_id) | |
dcaf9f5e AN |
624 | { |
625 | struct iwl_mcc_update_cmd mcc_update_cmd = { | |
626 | .mcc = cpu_to_le16(alpha2[0] << 8 | alpha2[1]), | |
8ba2d7a1 | 627 | .source_id = (u8)src_id, |
dcaf9f5e AN |
628 | }; |
629 | struct iwl_mcc_update_resp *mcc_resp, *resp_cp = NULL; | |
630 | struct iwl_rx_packet *pkt; | |
631 | struct iwl_host_cmd cmd = { | |
632 | .id = MCC_UPDATE_CMD, | |
633 | .flags = CMD_WANT_SKB, | |
634 | .data = { &mcc_update_cmd }, | |
635 | }; | |
636 | ||
637 | int ret; | |
638 | u32 status; | |
639 | int resp_len, n_channels; | |
640 | u16 mcc; | |
641 | ||
642 | if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) | |
643 | return ERR_PTR(-EOPNOTSUPP); | |
644 | ||
645 | cmd.len[0] = sizeof(struct iwl_mcc_update_cmd); | |
646 | ||
8ba2d7a1 EH |
647 | IWL_DEBUG_LAR(mvm, "send MCC update to FW with '%c%c' src = %d\n", |
648 | alpha2[0], alpha2[1], src_id); | |
dcaf9f5e AN |
649 | |
650 | ret = iwl_mvm_send_cmd(mvm, &cmd); | |
651 | if (ret) | |
652 | return ERR_PTR(ret); | |
653 | ||
654 | pkt = cmd.resp_pkt; | |
655 | if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { | |
656 | IWL_ERR(mvm, "Bad return from MCC_UPDATE_COMMAND (0x%08X)\n", | |
657 | pkt->hdr.flags); | |
658 | ret = -EIO; | |
659 | goto exit; | |
660 | } | |
661 | ||
662 | /* Extract MCC response */ | |
663 | mcc_resp = (void *)pkt->data; | |
664 | status = le32_to_cpu(mcc_resp->status); | |
665 | ||
dcaf9f5e AN |
666 | mcc = le16_to_cpu(mcc_resp->mcc); |
667 | ||
668 | /* W/A for a FW/NVM issue - returns 0x00 for the world domain */ | |
669 | if (mcc == 0) { | |
670 | mcc = 0x3030; /* "00" - world */ | |
671 | mcc_resp->mcc = cpu_to_le16(mcc); | |
672 | } | |
673 | ||
674 | n_channels = __le32_to_cpu(mcc_resp->n_channels); | |
675 | IWL_DEBUG_LAR(mvm, | |
676 | "MCC response status: 0x%x. new MCC: 0x%x ('%c%c') change: %d n_chans: %d\n", | |
677 | status, mcc, mcc >> 8, mcc & 0xff, | |
47c8b154 | 678 | !!(status == MCC_RESP_NEW_CHAN_PROFILE), n_channels); |
dcaf9f5e AN |
679 | |
680 | resp_len = sizeof(*mcc_resp) + n_channels * sizeof(__le32); | |
681 | resp_cp = kmemdup(mcc_resp, resp_len, GFP_KERNEL); | |
682 | if (!resp_cp) { | |
683 | ret = -ENOMEM; | |
684 | goto exit; | |
685 | } | |
686 | ||
687 | ret = 0; | |
688 | exit: | |
689 | iwl_free_resp(&cmd); | |
690 | if (ret) | |
691 | return ERR_PTR(ret); | |
692 | return resp_cp; | |
693 | } | |
90d4f7db | 694 | |
7f0344c2 JD |
695 | #ifdef CONFIG_ACPI |
696 | #define WRD_METHOD "WRDD" | |
697 | #define WRDD_WIFI (0x07) | |
698 | #define WRDD_WIGIG (0x10) | |
699 | ||
700 | static u32 iwl_mvm_wrdd_get_mcc(struct iwl_mvm *mvm, union acpi_object *wrdd) | |
701 | { | |
702 | union acpi_object *mcc_pkg, *domain_type, *mcc_value; | |
703 | u32 i; | |
704 | ||
705 | if (wrdd->type != ACPI_TYPE_PACKAGE || | |
706 | wrdd->package.count < 2 || | |
707 | wrdd->package.elements[0].type != ACPI_TYPE_INTEGER || | |
708 | wrdd->package.elements[0].integer.value != 0) { | |
709 | IWL_DEBUG_LAR(mvm, "Unsupported wrdd structure\n"); | |
710 | return 0; | |
711 | } | |
712 | ||
713 | for (i = 1 ; i < wrdd->package.count ; ++i) { | |
714 | mcc_pkg = &wrdd->package.elements[i]; | |
715 | ||
716 | if (mcc_pkg->type != ACPI_TYPE_PACKAGE || | |
717 | mcc_pkg->package.count < 2 || | |
718 | mcc_pkg->package.elements[0].type != ACPI_TYPE_INTEGER || | |
719 | mcc_pkg->package.elements[1].type != ACPI_TYPE_INTEGER) { | |
720 | mcc_pkg = NULL; | |
721 | continue; | |
722 | } | |
723 | ||
724 | domain_type = &mcc_pkg->package.elements[0]; | |
725 | if (domain_type->integer.value == WRDD_WIFI) | |
726 | break; | |
727 | ||
728 | mcc_pkg = NULL; | |
729 | } | |
730 | ||
731 | if (mcc_pkg) { | |
732 | mcc_value = &mcc_pkg->package.elements[1]; | |
733 | return mcc_value->integer.value; | |
734 | } | |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
739 | static int iwl_mvm_get_bios_mcc(struct iwl_mvm *mvm, char *mcc) | |
740 | { | |
741 | acpi_handle root_handle; | |
742 | acpi_handle handle; | |
743 | struct acpi_buffer wrdd = {ACPI_ALLOCATE_BUFFER, NULL}; | |
744 | acpi_status status; | |
745 | u32 mcc_val; | |
746 | struct pci_dev *pdev = to_pci_dev(mvm->dev); | |
747 | ||
748 | root_handle = ACPI_HANDLE(&pdev->dev); | |
749 | if (!root_handle) { | |
750 | IWL_DEBUG_LAR(mvm, | |
751 | "Could not retrieve root port ACPI handle\n"); | |
752 | return -ENOENT; | |
753 | } | |
754 | ||
755 | /* Get the method's handle */ | |
756 | status = acpi_get_handle(root_handle, (acpi_string)WRD_METHOD, &handle); | |
757 | if (ACPI_FAILURE(status)) { | |
758 | IWL_DEBUG_LAR(mvm, "WRD method not found\n"); | |
759 | return -ENOENT; | |
760 | } | |
761 | ||
762 | /* Call WRDD with no arguments */ | |
763 | status = acpi_evaluate_object(handle, NULL, NULL, &wrdd); | |
764 | if (ACPI_FAILURE(status)) { | |
765 | IWL_DEBUG_LAR(mvm, "WRDC invocation failed (0x%x)\n", status); | |
766 | return -ENOENT; | |
767 | } | |
768 | ||
769 | mcc_val = iwl_mvm_wrdd_get_mcc(mvm, wrdd.pointer); | |
770 | kfree(wrdd.pointer); | |
771 | if (!mcc_val) | |
772 | return -ENOENT; | |
773 | ||
774 | mcc[0] = (mcc_val >> 8) & 0xff; | |
775 | mcc[1] = mcc_val & 0xff; | |
776 | mcc[2] = '\0'; | |
777 | return 0; | |
778 | } | |
779 | #else /* CONFIG_ACPI */ | |
780 | static int iwl_mvm_get_bios_mcc(struct iwl_mvm *mvm, char *mcc) | |
781 | { | |
782 | return -ENOENT; | |
783 | } | |
784 | #endif | |
785 | ||
90d4f7db AN |
786 | int iwl_mvm_init_mcc(struct iwl_mvm *mvm) |
787 | { | |
d0d15197 MG |
788 | bool tlv_lar; |
789 | bool nvm_lar; | |
8ba2d7a1 EH |
790 | int retval; |
791 | struct ieee80211_regdomain *regd; | |
7f0344c2 | 792 | char mcc[3]; |
d0d15197 MG |
793 | |
794 | if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_8000) { | |
795 | tlv_lar = mvm->fw->ucode_capa.capa[0] & | |
796 | IWL_UCODE_TLV_CAPA_LAR_SUPPORT; | |
797 | nvm_lar = mvm->nvm_data->lar_enabled; | |
798 | if (tlv_lar != nvm_lar) | |
799 | IWL_INFO(mvm, | |
800 | "Conflict between TLV & NVM regarding enabling LAR (TLV = %s NVM =%s)\n", | |
801 | tlv_lar ? "enabled" : "disabled", | |
802 | nvm_lar ? "enabled" : "disabled"); | |
803 | } | |
804 | ||
90d4f7db AN |
805 | if (!iwl_mvm_is_lar_supported(mvm)) |
806 | return 0; | |
807 | ||
808 | /* | |
809 | * During HW restart, only replay the last set MCC to FW. Otherwise, | |
810 | * queue an update to cfg80211 to retrieve the default alpha2 from FW. | |
811 | */ | |
812 | if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) { | |
813 | /* This should only be called during vif up and hold RTNL */ | |
8ba2d7a1 | 814 | return iwl_mvm_init_fw_regd(mvm); |
90d4f7db AN |
815 | } |
816 | ||
817 | /* | |
8ba2d7a1 EH |
818 | * Driver regulatory hint for initial update, this also informs the |
819 | * firmware we support wifi location updates. | |
88931cc9 AN |
820 | * Disallow scans that might crash the FW while the LAR regdomain |
821 | * is not set. | |
90d4f7db | 822 | */ |
88931cc9 | 823 | mvm->lar_regdom_set = false; |
8ba2d7a1 | 824 | |
47c8b154 | 825 | regd = iwl_mvm_get_current_regdomain(mvm, NULL); |
8ba2d7a1 EH |
826 | if (IS_ERR_OR_NULL(regd)) |
827 | return -EIO; | |
828 | ||
7f0344c2 JD |
829 | if (iwl_mvm_is_wifi_mcc_supported(mvm) && |
830 | !iwl_mvm_get_bios_mcc(mvm, mcc)) { | |
831 | kfree(regd); | |
832 | regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, | |
47c8b154 | 833 | MCC_SOURCE_BIOS, NULL); |
7f0344c2 JD |
834 | if (IS_ERR_OR_NULL(regd)) |
835 | return -EIO; | |
836 | } | |
837 | ||
8ba2d7a1 EH |
838 | retval = regulatory_set_wiphy_regd_sync_rtnl(mvm->hw->wiphy, regd); |
839 | kfree(regd); | |
840 | return retval; | |
88931cc9 AN |
841 | } |
842 | ||
843 | int iwl_mvm_rx_chub_update_mcc(struct iwl_mvm *mvm, | |
844 | struct iwl_rx_cmd_buffer *rxb, | |
845 | struct iwl_device_cmd *cmd) | |
846 | { | |
847 | struct iwl_rx_packet *pkt = rxb_addr(rxb); | |
848 | struct iwl_mcc_chub_notif *notif = (void *)pkt->data; | |
8ba2d7a1 | 849 | enum iwl_mcc_source src; |
88931cc9 | 850 | char mcc[3]; |
8ba2d7a1 EH |
851 | struct ieee80211_regdomain *regd; |
852 | ||
853 | lockdep_assert_held(&mvm->mutex); | |
88931cc9 AN |
854 | |
855 | if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm))) | |
8ba2d7a1 | 856 | return 0; |
88931cc9 AN |
857 | |
858 | mcc[0] = notif->mcc >> 8; | |
859 | mcc[1] = notif->mcc & 0xff; | |
860 | mcc[2] = '\0'; | |
8ba2d7a1 | 861 | src = notif->source_id; |
88931cc9 AN |
862 | |
863 | IWL_DEBUG_LAR(mvm, | |
8ba2d7a1 EH |
864 | "RX: received chub update mcc cmd (mcc '%s' src %d)\n", |
865 | mcc, src); | |
47c8b154 | 866 | regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, src, NULL); |
8ba2d7a1 EH |
867 | if (IS_ERR_OR_NULL(regd)) |
868 | return 0; | |
869 | ||
870 | regulatory_set_wiphy_regd(mvm->hw->wiphy, regd); | |
871 | kfree(regd); | |
872 | ||
88931cc9 | 873 | return 0; |
90d4f7db | 874 | } |