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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
51368bf7 | 3 | * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
ed277c93 | 37 | #include "iwl-op-mode.h" |
6468a01a | 38 | #include "internal.h" |
6238b008 | 39 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
1023fdc4 | 40 | #include "dvm/commands.h" |
1053d35f | 41 | |
522376d2 EG |
42 | #define IWL_TX_CRC_SIZE 4 |
43 | #define IWL_TX_DELIMITER_SIZE 4 | |
44 | ||
f02831be EG |
45 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
46 | * DMA services | |
47 | * | |
48 | * Theory of operation | |
49 | * | |
50 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
51 | * of buffer descriptors, each of which points to one or more data buffers for | |
52 | * the device to read from or fill. Driver and device exchange status of each | |
53 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
54 | * entries in each circular buffer, to protect against confusing empty and full | |
55 | * queue states. | |
56 | * | |
57 | * The device reads or writes the data in the queues via the device's several | |
58 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
59 | * | |
60 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
61 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
62 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
63 | * Tx queue resumed. | |
64 | * | |
65 | ***************************************************/ | |
66 | static int iwl_queue_space(const struct iwl_queue *q) | |
67 | { | |
a9b29246 IY |
68 | unsigned int max; |
69 | unsigned int used; | |
f02831be | 70 | |
a9b29246 IY |
71 | /* |
72 | * To avoid ambiguity between empty and completely full queues, there | |
73 | * should always be less than q->n_bd elements in the queue. | |
74 | * If q->n_window is smaller than q->n_bd, there is no need to reserve | |
75 | * any queue entries for this purpose. | |
76 | */ | |
77 | if (q->n_window < q->n_bd) | |
78 | max = q->n_window; | |
79 | else | |
80 | max = q->n_bd - 1; | |
f02831be | 81 | |
a9b29246 IY |
82 | /* |
83 | * q->n_bd is a power of 2, so the following is equivalent to modulo by | |
84 | * q->n_bd and is well defined for negative dividends. | |
85 | */ | |
86 | used = (q->write_ptr - q->read_ptr) & (q->n_bd - 1); | |
87 | ||
88 | if (WARN_ON(used > max)) | |
89 | return 0; | |
90 | ||
91 | return max - used; | |
f02831be EG |
92 | } |
93 | ||
94 | /* | |
95 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
96 | */ | |
97 | static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) | |
98 | { | |
99 | q->n_bd = count; | |
100 | q->n_window = slots_num; | |
101 | q->id = id; | |
102 | ||
103 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
104 | * and iwl_queue_dec_wrap are broken. */ | |
105 | if (WARN_ON(!is_power_of_2(count))) | |
106 | return -EINVAL; | |
107 | ||
108 | /* slots_num must be power-of-two size, otherwise | |
109 | * get_cmd_index is broken. */ | |
110 | if (WARN_ON(!is_power_of_2(slots_num))) | |
111 | return -EINVAL; | |
112 | ||
113 | q->low_mark = q->n_window / 4; | |
114 | if (q->low_mark < 4) | |
115 | q->low_mark = 4; | |
116 | ||
117 | q->high_mark = q->n_window / 8; | |
118 | if (q->high_mark < 2) | |
119 | q->high_mark = 2; | |
120 | ||
121 | q->write_ptr = 0; | |
122 | q->read_ptr = 0; | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
f02831be EG |
127 | static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, |
128 | struct iwl_dma_ptr *ptr, size_t size) | |
129 | { | |
130 | if (WARN_ON(ptr->addr)) | |
131 | return -EINVAL; | |
132 | ||
133 | ptr->addr = dma_alloc_coherent(trans->dev, size, | |
134 | &ptr->dma, GFP_KERNEL); | |
135 | if (!ptr->addr) | |
136 | return -ENOMEM; | |
137 | ptr->size = size; | |
138 | return 0; | |
139 | } | |
140 | ||
141 | static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, | |
142 | struct iwl_dma_ptr *ptr) | |
143 | { | |
144 | if (unlikely(!ptr->addr)) | |
145 | return; | |
146 | ||
147 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); | |
148 | memset(ptr, 0, sizeof(*ptr)); | |
149 | } | |
150 | ||
151 | static void iwl_pcie_txq_stuck_timer(unsigned long data) | |
152 | { | |
153 | struct iwl_txq *txq = (void *)data; | |
154 | struct iwl_queue *q = &txq->q; | |
155 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; | |
156 | struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); | |
157 | u32 scd_sram_addr = trans_pcie->scd_base_addr + | |
158 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
159 | u8 buf[16]; | |
160 | int i; | |
161 | ||
162 | spin_lock(&txq->lock); | |
163 | /* check if triggered erroneously */ | |
164 | if (txq->q.read_ptr == txq->q.write_ptr) { | |
165 | spin_unlock(&txq->lock); | |
166 | return; | |
167 | } | |
168 | spin_unlock(&txq->lock); | |
169 | ||
170 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, | |
171 | jiffies_to_msecs(trans_pcie->wd_timeout)); | |
172 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
173 | txq->q.read_ptr, txq->q.write_ptr); | |
174 | ||
4fd442db | 175 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); |
f02831be EG |
176 | |
177 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
178 | ||
179 | for (i = 0; i < FH_TCSR_CHNL_NUM; i++) | |
180 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i, | |
181 | iwl_read_direct32(trans, FH_TX_TRB_REG(i))); | |
182 | ||
183 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
184 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i)); | |
185 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
186 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
187 | u32 tbl_dw = | |
4fd442db EG |
188 | iwl_trans_read_mem32(trans, |
189 | trans_pcie->scd_base_addr + | |
190 | SCD_TRANS_TBL_OFFSET_QUEUE(i)); | |
f02831be EG |
191 | |
192 | if (i & 0x1) | |
193 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
194 | else | |
195 | tbl_dw = tbl_dw & 0x0000FFFF; | |
196 | ||
197 | IWL_ERR(trans, | |
198 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
199 | i, active ? "" : "in", fifo, tbl_dw, | |
200 | iwl_read_prph(trans, | |
201 | SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1), | |
202 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(i))); | |
203 | } | |
204 | ||
205 | for (i = q->read_ptr; i != q->write_ptr; | |
38c0f334 | 206 | i = iwl_queue_inc_wrap(i, q->n_bd)) |
f02831be | 207 | IWL_ERR(trans, "scratch %d = 0x%08x\n", i, |
38c0f334 | 208 | le32_to_cpu(txq->scratchbufs[i].scratch)); |
f02831be | 209 | |
cfadc3ff | 210 | iwl_write_prph(trans, DEVICE_SET_NMI_REG, 1); |
f02831be EG |
211 | } |
212 | ||
990aa6d7 EG |
213 | /* |
214 | * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
48d42c42 | 215 | */ |
f02831be EG |
216 | static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
217 | struct iwl_txq *txq, u16 byte_cnt) | |
48d42c42 | 218 | { |
105183b1 | 219 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
20d3b647 | 220 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
221 | int write_ptr = txq->q.write_ptr; |
222 | int txq_id = txq->q.id; | |
223 | u8 sec_ctl = 0; | |
224 | u8 sta_id = 0; | |
225 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
226 | __le16 bc_ent; | |
132f98c2 | 227 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 228 | (void *) txq->entries[txq->q.write_ptr].cmd->payload; |
48d42c42 | 229 | |
105183b1 EG |
230 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
231 | ||
48d42c42 EG |
232 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
233 | ||
132f98c2 EG |
234 | sta_id = tx_cmd->sta_id; |
235 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
236 | |
237 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
238 | case TX_CMD_SEC_CCM: | |
4325f6ca | 239 | len += IEEE80211_CCMP_MIC_LEN; |
48d42c42 EG |
240 | break; |
241 | case TX_CMD_SEC_TKIP: | |
4325f6ca | 242 | len += IEEE80211_TKIP_ICV_LEN; |
48d42c42 EG |
243 | break; |
244 | case TX_CMD_SEC_WEP: | |
4325f6ca | 245 | len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; |
48d42c42 EG |
246 | break; |
247 | } | |
248 | ||
046db346 EG |
249 | if (trans_pcie->bc_table_dword) |
250 | len = DIV_ROUND_UP(len, 4); | |
251 | ||
252 | bc_ent = cpu_to_le16(len | (sta_id << 12)); | |
48d42c42 EG |
253 | |
254 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
255 | ||
256 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
257 | scd_bc_tbl[txq_id]. | |
258 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
259 | } | |
260 | ||
f02831be EG |
261 | static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
262 | struct iwl_txq *txq) | |
263 | { | |
264 | struct iwl_trans_pcie *trans_pcie = | |
265 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
266 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; | |
267 | int txq_id = txq->q.id; | |
268 | int read_ptr = txq->q.read_ptr; | |
269 | u8 sta_id = 0; | |
270 | __le16 bc_ent; | |
271 | struct iwl_tx_cmd *tx_cmd = | |
272 | (void *)txq->entries[txq->q.read_ptr].cmd->payload; | |
273 | ||
274 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
275 | ||
276 | if (txq_id != trans_pcie->cmd_queue) | |
277 | sta_id = tx_cmd->sta_id; | |
278 | ||
279 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
280 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
281 | ||
282 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
283 | scd_bc_tbl[txq_id]. | |
284 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
285 | } | |
286 | ||
990aa6d7 EG |
287 | /* |
288 | * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware | |
fd4abac5 | 289 | */ |
ea68f460 JB |
290 | static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, |
291 | struct iwl_txq *txq) | |
fd4abac5 | 292 | { |
23e76d1a | 293 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
fd4abac5 | 294 | u32 reg = 0; |
fd4abac5 TW |
295 | int txq_id = txq->q.id; |
296 | ||
ea68f460 | 297 | lockdep_assert_held(&txq->lock); |
fd4abac5 | 298 | |
5045388c EP |
299 | /* |
300 | * explicitly wake up the NIC if: | |
301 | * 1. shadow registers aren't enabled | |
302 | * 2. NIC is woken up for CMD regardless of shadow outside this function | |
303 | * 3. there is a chance that the NIC is asleep | |
304 | */ | |
305 | if (!trans->cfg->base_params->shadow_reg_enable && | |
306 | txq_id != trans_pcie->cmd_queue && | |
307 | test_bit(STATUS_TPOWER_PMI, &trans->status)) { | |
f81c1f48 | 308 | /* |
5045388c EP |
309 | * wake up nic if it's powered down ... |
310 | * uCode will wake up, and interrupt us again, so next | |
311 | * time we'll skip this part. | |
f81c1f48 | 312 | */ |
5045388c EP |
313 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
314 | ||
315 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
316 | IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", | |
317 | txq_id, reg); | |
318 | iwl_set_bit(trans, CSR_GP_CNTRL, | |
319 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
ea68f460 | 320 | txq->need_update = true; |
5045388c EP |
321 | return; |
322 | } | |
f81c1f48 | 323 | } |
5045388c EP |
324 | |
325 | /* | |
326 | * if not in power-save mode, uCode will never sleep when we're | |
327 | * trying to tx (during RFKILL, we're not trying to tx). | |
328 | */ | |
329 | IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr); | |
330 | iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8)); | |
ea68f460 | 331 | } |
5045388c | 332 | |
ea68f460 JB |
333 | void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) |
334 | { | |
335 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
336 | int i; | |
337 | ||
338 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
339 | struct iwl_txq *txq = &trans_pcie->txq[i]; | |
340 | ||
341 | spin_lock(&txq->lock); | |
342 | if (trans_pcie->txq[i].need_update) { | |
343 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
344 | trans_pcie->txq[i].need_update = false; | |
345 | } | |
346 | spin_unlock(&txq->lock); | |
347 | } | |
fd4abac5 | 348 | } |
fd4abac5 | 349 | |
f02831be | 350 | static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
351 | { |
352 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
353 | ||
354 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
355 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
356 | addr |= | |
357 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
358 | ||
359 | return addr; | |
360 | } | |
361 | ||
f02831be | 362 | static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
363 | { |
364 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
365 | ||
366 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
367 | } | |
368 | ||
f02831be EG |
369 | static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, |
370 | dma_addr_t addr, u16 len) | |
214d14d4 JB |
371 | { |
372 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
373 | u16 hi_n_len = len << 4; | |
374 | ||
375 | put_unaligned_le32(addr, &tb->lo); | |
376 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
377 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
378 | ||
379 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
380 | ||
381 | tfd->num_tbs = idx + 1; | |
382 | } | |
383 | ||
f02831be | 384 | static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd) |
214d14d4 JB |
385 | { |
386 | return tfd->num_tbs & 0x1f; | |
387 | } | |
388 | ||
f02831be | 389 | static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, |
98891754 JB |
390 | struct iwl_cmd_meta *meta, |
391 | struct iwl_tfd *tfd) | |
214d14d4 | 392 | { |
214d14d4 JB |
393 | int i; |
394 | int num_tbs; | |
395 | ||
214d14d4 | 396 | /* Sanity check on number of chunks */ |
f02831be | 397 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); |
214d14d4 JB |
398 | |
399 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 400 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
401 | /* @todo issue fatal error, it is quite serious situation */ |
402 | return; | |
403 | } | |
404 | ||
38c0f334 | 405 | /* first TB is never freed - it's the scratchbuf data */ |
214d14d4 | 406 | |
214d14d4 | 407 | for (i = 1; i < num_tbs; i++) |
f02831be | 408 | dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i), |
98891754 JB |
409 | iwl_pcie_tfd_tb_get_len(tfd, i), |
410 | DMA_TO_DEVICE); | |
ebed633c EG |
411 | |
412 | tfd->num_tbs = 0; | |
4ce7cc2b JB |
413 | } |
414 | ||
990aa6d7 EG |
415 | /* |
416 | * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 417 | * @trans - transport private data |
4ce7cc2b | 418 | * @txq - tx queue |
ebed633c | 419 | * @dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
420 | * |
421 | * Does NOT advance any TFD circular buffer read/write indexes | |
422 | * Does NOT free the TFD itself (which is within circular buffer) | |
423 | */ | |
98891754 | 424 | static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) |
4ce7cc2b JB |
425 | { |
426 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 427 | |
ebed633c EG |
428 | /* rd_ptr is bounded by n_bd and idx is bounded by n_window */ |
429 | int rd_ptr = txq->q.read_ptr; | |
430 | int idx = get_cmd_index(&txq->q, rd_ptr); | |
431 | ||
015c15e1 JB |
432 | lockdep_assert_held(&txq->lock); |
433 | ||
ebed633c | 434 | /* We have only q->n_window txq->entries, but we use q->n_bd tfds */ |
98891754 | 435 | iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]); |
214d14d4 JB |
436 | |
437 | /* free SKB */ | |
bf8440e6 | 438 | if (txq->entries) { |
214d14d4 JB |
439 | struct sk_buff *skb; |
440 | ||
ebed633c | 441 | skb = txq->entries[idx].skb; |
214d14d4 | 442 | |
909e9b23 EG |
443 | /* Can be called from irqs-disabled context |
444 | * If skb is not NULL, it means that the whole queue is being | |
445 | * freed and that the queue is not empty - free the skb | |
446 | */ | |
214d14d4 | 447 | if (skb) { |
ed277c93 | 448 | iwl_op_mode_free_skb(trans->op_mode, skb); |
ebed633c | 449 | txq->entries[idx].skb = NULL; |
214d14d4 JB |
450 | } |
451 | } | |
452 | } | |
453 | ||
f02831be EG |
454 | static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
455 | dma_addr_t addr, u16 len, u8 reset) | |
214d14d4 JB |
456 | { |
457 | struct iwl_queue *q; | |
458 | struct iwl_tfd *tfd, *tfd_tmp; | |
459 | u32 num_tbs; | |
460 | ||
461 | q = &txq->q; | |
4ce7cc2b | 462 | tfd_tmp = txq->tfds; |
214d14d4 JB |
463 | tfd = &tfd_tmp[q->write_ptr]; |
464 | ||
f02831be EG |
465 | if (reset) |
466 | memset(tfd, 0, sizeof(*tfd)); | |
467 | ||
468 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); | |
469 | ||
470 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
471 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
472 | IWL_ERR(trans, "Error can not send more than %d chunks\n", | |
473 | IWL_NUM_OF_TBS); | |
474 | return -EINVAL; | |
475 | } | |
476 | ||
1092b9bc EP |
477 | if (WARN(addr & ~IWL_TX_DMA_MASK, |
478 | "Unaligned address = %llx\n", (unsigned long long)addr)) | |
f02831be EG |
479 | return -EINVAL; |
480 | ||
f02831be EG |
481 | iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len); |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | static int iwl_pcie_txq_alloc(struct iwl_trans *trans, | |
487 | struct iwl_txq *txq, int slots_num, | |
488 | u32 txq_id) | |
489 | { | |
490 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
491 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; | |
38c0f334 | 492 | size_t scratchbuf_sz; |
f02831be EG |
493 | int i; |
494 | ||
495 | if (WARN_ON(txq->entries || txq->tfds)) | |
496 | return -EINVAL; | |
497 | ||
498 | setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, | |
499 | (unsigned long)txq); | |
500 | txq->trans_pcie = trans_pcie; | |
501 | ||
502 | txq->q.n_window = slots_num; | |
503 | ||
504 | txq->entries = kcalloc(slots_num, | |
505 | sizeof(struct iwl_pcie_txq_entry), | |
506 | GFP_KERNEL); | |
507 | ||
508 | if (!txq->entries) | |
509 | goto error; | |
510 | ||
511 | if (txq_id == trans_pcie->cmd_queue) | |
512 | for (i = 0; i < slots_num; i++) { | |
513 | txq->entries[i].cmd = | |
514 | kmalloc(sizeof(struct iwl_device_cmd), | |
515 | GFP_KERNEL); | |
516 | if (!txq->entries[i].cmd) | |
517 | goto error; | |
518 | } | |
519 | ||
520 | /* Circular buffer of transmit frame descriptors (TFDs), | |
521 | * shared with device */ | |
522 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, | |
523 | &txq->q.dma_addr, GFP_KERNEL); | |
d0320f75 | 524 | if (!txq->tfds) |
f02831be | 525 | goto error; |
38c0f334 JB |
526 | |
527 | BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs)); | |
528 | BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) != | |
529 | sizeof(struct iwl_cmd_header) + | |
530 | offsetof(struct iwl_tx_cmd, scratch)); | |
531 | ||
532 | scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num; | |
533 | ||
534 | txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz, | |
535 | &txq->scratchbufs_dma, | |
536 | GFP_KERNEL); | |
537 | if (!txq->scratchbufs) | |
538 | goto err_free_tfds; | |
539 | ||
f02831be EG |
540 | txq->q.id = txq_id; |
541 | ||
542 | return 0; | |
38c0f334 JB |
543 | err_free_tfds: |
544 | dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr); | |
f02831be EG |
545 | error: |
546 | if (txq->entries && txq_id == trans_pcie->cmd_queue) | |
547 | for (i = 0; i < slots_num; i++) | |
548 | kfree(txq->entries[i].cmd); | |
549 | kfree(txq->entries); | |
550 | txq->entries = NULL; | |
551 | ||
552 | return -ENOMEM; | |
553 | ||
554 | } | |
555 | ||
556 | static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, | |
557 | int slots_num, u32 txq_id) | |
558 | { | |
559 | int ret; | |
560 | ||
43aa616f | 561 | txq->need_update = false; |
f02831be EG |
562 | |
563 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
564 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
565 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
566 | ||
567 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
568 | ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num, | |
569 | txq_id); | |
570 | if (ret) | |
571 | return ret; | |
572 | ||
573 | spin_lock_init(&txq->lock); | |
574 | ||
575 | /* | |
576 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
577 | * given Tx queue, and enable the DMA channel used for that queue. | |
578 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
579 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
580 | txq->q.dma_addr >> 8); | |
581 | ||
582 | return 0; | |
583 | } | |
584 | ||
585 | /* | |
586 | * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's | |
587 | */ | |
588 | static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) | |
589 | { | |
590 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
591 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
592 | struct iwl_queue *q = &txq->q; | |
f02831be EG |
593 | |
594 | if (!q->n_bd) | |
595 | return; | |
596 | ||
f02831be EG |
597 | spin_lock_bh(&txq->lock); |
598 | while (q->write_ptr != q->read_ptr) { | |
b967613d EG |
599 | IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", |
600 | txq_id, q->read_ptr); | |
98891754 | 601 | iwl_pcie_txq_free_tfd(trans, txq); |
f02831be EG |
602 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
603 | } | |
b967613d | 604 | txq->active = false; |
f02831be | 605 | spin_unlock_bh(&txq->lock); |
8a487b1a EG |
606 | |
607 | /* just in case - this queue may have been stopped */ | |
608 | iwl_wake_queue(trans, txq); | |
f02831be EG |
609 | } |
610 | ||
611 | /* | |
612 | * iwl_pcie_txq_free - Deallocate DMA queue. | |
613 | * @txq: Transmit queue to deallocate. | |
614 | * | |
615 | * Empty queue by removing and destroying all BD's. | |
616 | * Free all buffers. | |
617 | * 0-fill, but do not free "txq" descriptor structure. | |
618 | */ | |
619 | static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) | |
620 | { | |
621 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
622 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
623 | struct device *dev = trans->dev; | |
624 | int i; | |
625 | ||
626 | if (WARN_ON(!txq)) | |
627 | return; | |
628 | ||
629 | iwl_pcie_txq_unmap(trans, txq_id); | |
630 | ||
631 | /* De-alloc array of command/tx buffers */ | |
632 | if (txq_id == trans_pcie->cmd_queue) | |
633 | for (i = 0; i < txq->q.n_window; i++) { | |
634 | kfree(txq->entries[i].cmd); | |
f02831be EG |
635 | kfree(txq->entries[i].free_buf); |
636 | } | |
637 | ||
638 | /* De-alloc circular buffer of TFDs */ | |
639 | if (txq->q.n_bd) { | |
640 | dma_free_coherent(dev, sizeof(struct iwl_tfd) * | |
641 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
d21fa2da | 642 | txq->q.dma_addr = 0; |
38c0f334 JB |
643 | |
644 | dma_free_coherent(dev, | |
645 | sizeof(*txq->scratchbufs) * txq->q.n_window, | |
646 | txq->scratchbufs, txq->scratchbufs_dma); | |
f02831be EG |
647 | } |
648 | ||
649 | kfree(txq->entries); | |
650 | txq->entries = NULL; | |
651 | ||
652 | del_timer_sync(&txq->stuck_timer); | |
653 | ||
654 | /* 0-fill queue descriptor structure */ | |
655 | memset(txq, 0, sizeof(*txq)); | |
656 | } | |
657 | ||
658 | /* | |
659 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
660 | */ | |
661 | static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask) | |
662 | { | |
663 | struct iwl_trans_pcie __maybe_unused *trans_pcie = | |
664 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
665 | ||
666 | iwl_write_prph(trans, SCD_TXFACT, mask); | |
667 | } | |
668 | ||
669 | void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) | |
670 | { | |
671 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
22dc3c95 | 672 | int nq = trans->cfg->base_params->num_of_queues; |
f02831be EG |
673 | int chan; |
674 | u32 reg_val; | |
22dc3c95 JB |
675 | int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - |
676 | SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); | |
f02831be EG |
677 | |
678 | /* make sure all queue are not stopped/used */ | |
679 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
680 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
681 | ||
682 | trans_pcie->scd_base_addr = | |
683 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); | |
684 | ||
685 | WARN_ON(scd_base_addr != 0 && | |
686 | scd_base_addr != trans_pcie->scd_base_addr); | |
687 | ||
22dc3c95 JB |
688 | /* reset context data, TX status and translation data */ |
689 | iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + | |
690 | SCD_CONTEXT_MEM_LOWER_BOUND, | |
691 | NULL, clear_dwords); | |
f02831be EG |
692 | |
693 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, | |
694 | trans_pcie->scd_bc_tbls.dma >> 10); | |
695 | ||
696 | /* The chain extension of the SCD doesn't work well. This feature is | |
697 | * enabled by default by the HW, so we need to disable it manually. | |
698 | */ | |
e03bbb62 EG |
699 | if (trans->cfg->base_params->scd_chain_ext_wa) |
700 | iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); | |
f02831be EG |
701 | |
702 | iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, | |
703 | trans_pcie->cmd_fifo); | |
704 | ||
705 | /* Activate all Tx DMA/FIFO channels */ | |
706 | iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7)); | |
707 | ||
708 | /* Enable DMA channel */ | |
709 | for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) | |
710 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
711 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
712 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
713 | ||
714 | /* Update FH chicken bits */ | |
715 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); | |
716 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
717 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
718 | ||
719 | /* Enable L1-Active */ | |
3073d8c0 EH |
720 | if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) |
721 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
722 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
f02831be EG |
723 | } |
724 | ||
ddaf5a5b JB |
725 | void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) |
726 | { | |
727 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
728 | int txq_id; | |
729 | ||
730 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
731 | txq_id++) { | |
732 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
733 | ||
734 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
735 | txq->q.dma_addr >> 8); | |
736 | iwl_pcie_txq_unmap(trans, txq_id); | |
737 | txq->q.read_ptr = 0; | |
738 | txq->q.write_ptr = 0; | |
739 | } | |
740 | ||
741 | /* Tell NIC where to find the "keep warm" buffer */ | |
742 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
743 | trans_pcie->kw.dma >> 4); | |
744 | ||
745 | iwl_pcie_tx_start(trans, trans_pcie->scd_base_addr); | |
746 | } | |
747 | ||
f02831be EG |
748 | /* |
749 | * iwl_pcie_tx_stop - Stop all Tx DMA channels | |
750 | */ | |
751 | int iwl_pcie_tx_stop(struct iwl_trans *trans) | |
752 | { | |
753 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
754 | int ch, txq_id, ret; | |
f02831be EG |
755 | |
756 | /* Turn off all Tx DMA fifos */ | |
7b70bd63 | 757 | spin_lock(&trans_pcie->irq_lock); |
f02831be EG |
758 | |
759 | iwl_pcie_txq_set_sched(trans, 0); | |
760 | ||
761 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
762 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { | |
763 | iwl_write_direct32(trans, | |
764 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
765 | ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG, | |
766 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000); | |
767 | if (ret < 0) | |
768 | IWL_ERR(trans, | |
769 | "Failing on timeout while stopping DMA channel %d [0x%08x]\n", | |
770 | ch, | |
771 | iwl_read_direct32(trans, | |
772 | FH_TSSR_TX_STATUS_REG)); | |
773 | } | |
7b70bd63 | 774 | spin_unlock(&trans_pcie->irq_lock); |
f02831be | 775 | |
fba1c627 EG |
776 | /* |
777 | * This function can be called before the op_mode disabled the | |
778 | * queues. This happens when we have an rfkill interrupt. | |
779 | * Since we stop Tx altogether - mark the queues as stopped. | |
780 | */ | |
781 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
782 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
783 | ||
784 | /* This can happen: start_hw, stop_device */ | |
785 | if (!trans_pcie->txq) | |
f02831be | 786 | return 0; |
f02831be EG |
787 | |
788 | /* Unmap DMA from host system and free skb's */ | |
789 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
790 | txq_id++) | |
791 | iwl_pcie_txq_unmap(trans, txq_id); | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | /* | |
797 | * iwl_trans_tx_free - Free TXQ Context | |
798 | * | |
799 | * Destroy all TX DMA queues and structures | |
800 | */ | |
801 | void iwl_pcie_tx_free(struct iwl_trans *trans) | |
802 | { | |
803 | int txq_id; | |
804 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
805 | ||
806 | /* Tx queues */ | |
807 | if (trans_pcie->txq) { | |
808 | for (txq_id = 0; | |
809 | txq_id < trans->cfg->base_params->num_of_queues; txq_id++) | |
810 | iwl_pcie_txq_free(trans, txq_id); | |
811 | } | |
812 | ||
813 | kfree(trans_pcie->txq); | |
814 | trans_pcie->txq = NULL; | |
815 | ||
816 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); | |
817 | ||
818 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); | |
819 | } | |
820 | ||
821 | /* | |
822 | * iwl_pcie_tx_alloc - allocate TX context | |
823 | * Allocate all Tx DMA structures and initialize them | |
824 | */ | |
825 | static int iwl_pcie_tx_alloc(struct iwl_trans *trans) | |
826 | { | |
827 | int ret; | |
828 | int txq_id, slots_num; | |
829 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
830 | ||
831 | u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * | |
832 | sizeof(struct iwlagn_scd_bc_tbl); | |
833 | ||
834 | /*It is not allowed to alloc twice, so warn when this happens. | |
835 | * We cannot rely on the previous allocation, so free and fail */ | |
836 | if (WARN_ON(trans_pcie->txq)) { | |
837 | ret = -EINVAL; | |
838 | goto error; | |
839 | } | |
840 | ||
841 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, | |
842 | scd_bc_tbls_size); | |
843 | if (ret) { | |
844 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); | |
845 | goto error; | |
846 | } | |
847 | ||
848 | /* Alloc keep-warm buffer */ | |
849 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); | |
850 | if (ret) { | |
851 | IWL_ERR(trans, "Keep Warm allocation failed\n"); | |
852 | goto error; | |
853 | } | |
854 | ||
855 | trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, | |
856 | sizeof(struct iwl_txq), GFP_KERNEL); | |
857 | if (!trans_pcie->txq) { | |
858 | IWL_ERR(trans, "Not enough memory for txq\n"); | |
2ab9ba0f | 859 | ret = -ENOMEM; |
f02831be EG |
860 | goto error; |
861 | } | |
862 | ||
863 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
864 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
865 | txq_id++) { | |
866 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
867 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
868 | ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id], | |
869 | slots_num, txq_id); | |
870 | if (ret) { | |
871 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); | |
872 | goto error; | |
873 | } | |
874 | } | |
875 | ||
876 | return 0; | |
877 | ||
878 | error: | |
879 | iwl_pcie_tx_free(trans); | |
880 | ||
881 | return ret; | |
882 | } | |
883 | int iwl_pcie_tx_init(struct iwl_trans *trans) | |
884 | { | |
885 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
886 | int ret; | |
887 | int txq_id, slots_num; | |
f02831be EG |
888 | bool alloc = false; |
889 | ||
890 | if (!trans_pcie->txq) { | |
891 | ret = iwl_pcie_tx_alloc(trans); | |
892 | if (ret) | |
893 | goto error; | |
894 | alloc = true; | |
895 | } | |
896 | ||
7b70bd63 | 897 | spin_lock(&trans_pcie->irq_lock); |
f02831be EG |
898 | |
899 | /* Turn off all Tx DMA fifos */ | |
900 | iwl_write_prph(trans, SCD_TXFACT, 0); | |
901 | ||
902 | /* Tell NIC where to find the "keep warm" buffer */ | |
903 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
904 | trans_pcie->kw.dma >> 4); | |
905 | ||
7b70bd63 | 906 | spin_unlock(&trans_pcie->irq_lock); |
f02831be EG |
907 | |
908 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
909 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
910 | txq_id++) { | |
911 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
912 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
913 | ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id], | |
914 | slots_num, txq_id); | |
915 | if (ret) { | |
916 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); | |
917 | goto error; | |
918 | } | |
919 | } | |
920 | ||
921 | return 0; | |
922 | error: | |
923 | /*Upon error, free only if we allocated something */ | |
924 | if (alloc) | |
925 | iwl_pcie_tx_free(trans); | |
926 | return ret; | |
927 | } | |
928 | ||
929 | static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie, | |
930 | struct iwl_txq *txq) | |
931 | { | |
932 | if (!trans_pcie->wd_timeout) | |
933 | return; | |
934 | ||
935 | /* | |
936 | * if empty delete timer, otherwise move timer forward | |
937 | * since we're making progress on this queue | |
938 | */ | |
939 | if (txq->q.read_ptr == txq->q.write_ptr) | |
940 | del_timer(&txq->stuck_timer); | |
941 | else | |
942 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
943 | } | |
944 | ||
945 | /* Frees buffers until index _not_ inclusive */ | |
f6d497cd EG |
946 | void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
947 | struct sk_buff_head *skbs) | |
f02831be EG |
948 | { |
949 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
950 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
f6d497cd EG |
951 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ |
952 | int tfd_num = ssn & (txq->q.n_bd - 1); | |
f02831be EG |
953 | struct iwl_queue *q = &txq->q; |
954 | int last_to_free; | |
f02831be EG |
955 | |
956 | /* This function is not meant to release cmd queue*/ | |
957 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) | |
f6d497cd | 958 | return; |
214d14d4 | 959 | |
2bfb5092 | 960 | spin_lock_bh(&txq->lock); |
f6d497cd | 961 | |
b967613d EG |
962 | if (!txq->active) { |
963 | IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", | |
964 | txq_id, ssn); | |
965 | goto out; | |
966 | } | |
967 | ||
f6d497cd EG |
968 | if (txq->q.read_ptr == tfd_num) |
969 | goto out; | |
970 | ||
971 | IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", | |
972 | txq_id, txq->q.read_ptr, tfd_num, ssn); | |
214d14d4 | 973 | |
f02831be EG |
974 | /*Since we free until index _not_ inclusive, the one before index is |
975 | * the last we will free. This one must be used */ | |
f6d497cd | 976 | last_to_free = iwl_queue_dec_wrap(tfd_num, q->n_bd); |
f02831be | 977 | |
6ca6ebc1 | 978 | if (!iwl_queue_used(q, last_to_free)) { |
f02831be EG |
979 | IWL_ERR(trans, |
980 | "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", | |
981 | __func__, txq_id, last_to_free, q->n_bd, | |
982 | q->write_ptr, q->read_ptr); | |
f6d497cd | 983 | goto out; |
214d14d4 JB |
984 | } |
985 | ||
f02831be | 986 | if (WARN_ON(!skb_queue_empty(skbs))) |
f6d497cd | 987 | goto out; |
214d14d4 | 988 | |
f02831be | 989 | for (; |
f6d497cd | 990 | q->read_ptr != tfd_num; |
f02831be | 991 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { |
214d14d4 | 992 | |
f02831be EG |
993 | if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL)) |
994 | continue; | |
214d14d4 | 995 | |
f02831be | 996 | __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb); |
214d14d4 | 997 | |
f02831be | 998 | txq->entries[txq->q.read_ptr].skb = NULL; |
fd4abac5 | 999 | |
f02831be | 1000 | iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); |
fd4abac5 | 1001 | |
98891754 | 1002 | iwl_pcie_txq_free_tfd(trans, txq); |
f02831be | 1003 | } |
fd4abac5 | 1004 | |
f02831be EG |
1005 | iwl_pcie_txq_progress(trans_pcie, txq); |
1006 | ||
f6d497cd EG |
1007 | if (iwl_queue_space(&txq->q) > txq->q.low_mark) |
1008 | iwl_wake_queue(trans, txq); | |
1009 | out: | |
2bfb5092 | 1010 | spin_unlock_bh(&txq->lock); |
1053d35f RR |
1011 | } |
1012 | ||
f02831be EG |
1013 | /* |
1014 | * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd | |
1015 | * | |
1016 | * When FW advances 'R' index, all entries between old and new 'R' index | |
1017 | * need to be reclaimed. As result, some free space forms. If there is | |
1018 | * enough free space (> low mark), wake the stack that feeds us. | |
1019 | */ | |
1020 | static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) | |
48d42c42 | 1021 | { |
f02831be EG |
1022 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1023 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
1024 | struct iwl_queue *q = &txq->q; | |
b9439491 | 1025 | unsigned long flags; |
f02831be | 1026 | int nfreed = 0; |
48d42c42 | 1027 | |
f02831be | 1028 | lockdep_assert_held(&txq->lock); |
48d42c42 | 1029 | |
6ca6ebc1 | 1030 | if ((idx >= q->n_bd) || (!iwl_queue_used(q, idx))) { |
f02831be EG |
1031 | IWL_ERR(trans, |
1032 | "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", | |
1033 | __func__, txq_id, idx, q->n_bd, | |
1034 | q->write_ptr, q->read_ptr); | |
1035 | return; | |
1036 | } | |
48d42c42 | 1037 | |
f02831be EG |
1038 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
1039 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
48d42c42 | 1040 | |
f02831be EG |
1041 | if (nfreed++ > 0) { |
1042 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", | |
1043 | idx, q->write_ptr, q->read_ptr); | |
cfadc3ff | 1044 | iwl_write_prph(trans, DEVICE_SET_NMI_REG, 1); |
f02831be EG |
1045 | } |
1046 | } | |
1047 | ||
e7f76340 EG |
1048 | if (trans->cfg->base_params->apmg_wake_up_wa && |
1049 | q->read_ptr == q->write_ptr) { | |
b9439491 EG |
1050 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
1051 | WARN_ON(!trans_pcie->cmd_in_flight); | |
1052 | trans_pcie->cmd_in_flight = false; | |
1053 | __iwl_trans_pcie_clear_bit(trans, | |
1054 | CSR_GP_CNTRL, | |
1055 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1056 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); | |
1057 | } | |
1058 | ||
f02831be | 1059 | iwl_pcie_txq_progress(trans_pcie, txq); |
48d42c42 EG |
1060 | } |
1061 | ||
f02831be | 1062 | static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, |
1ce8658c | 1063 | u16 txq_id) |
48d42c42 | 1064 | { |
20d3b647 | 1065 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
1066 | u32 tbl_dw_addr; |
1067 | u32 tbl_dw; | |
1068 | u16 scd_q2ratid; | |
1069 | ||
1070 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
1071 | ||
105183b1 | 1072 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
1073 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
1074 | ||
4fd442db | 1075 | tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); |
48d42c42 EG |
1076 | |
1077 | if (txq_id & 0x1) | |
1078 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
1079 | else | |
1080 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
1081 | ||
4fd442db | 1082 | iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
1083 | |
1084 | return 0; | |
1085 | } | |
1086 | ||
f02831be EG |
1087 | static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans, |
1088 | u16 txq_id) | |
48d42c42 EG |
1089 | { |
1090 | /* Simply stop the queue, but don't change any configuration; | |
1091 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1042db2a | 1092 | iwl_write_prph(trans, |
48d42c42 EG |
1093 | SCD_QUEUE_STATUS_BITS(txq_id), |
1094 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
1095 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
1096 | } | |
1097 | ||
bd5f6a34 EG |
1098 | /* Receiver address (actually, Rx station's index into station table), |
1099 | * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ | |
1100 | #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) | |
1101 | ||
f02831be EG |
1102 | void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo, |
1103 | int sta_id, int tid, int frame_limit, u16 ssn) | |
48d42c42 | 1104 | { |
9eae88fa | 1105 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
4beaf6c2 | 1106 | |
9eae88fa JB |
1107 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
1108 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 1109 | |
48d42c42 | 1110 | /* Stop this Tx queue before configuring it */ |
f02831be | 1111 | iwl_pcie_txq_set_inactive(trans, txq_id); |
48d42c42 | 1112 | |
4beaf6c2 EG |
1113 | /* Set this queue as a chain-building queue unless it is CMD queue */ |
1114 | if (txq_id != trans_pcie->cmd_queue) | |
1115 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); | |
1116 | ||
1117 | /* If this queue is mapped to a certain station: it is an AGG queue */ | |
881acd89 | 1118 | if (sta_id >= 0) { |
4beaf6c2 | 1119 | u16 ra_tid = BUILD_RAxTID(sta_id, tid); |
48d42c42 | 1120 | |
4beaf6c2 | 1121 | /* Map receiver-address / traffic-ID to this queue */ |
f02831be | 1122 | iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); |
48d42c42 | 1123 | |
4beaf6c2 EG |
1124 | /* enable aggregations for the queue */ |
1125 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
68972c46 | 1126 | trans_pcie->txq[txq_id].ampdu = true; |
1ce8658c EG |
1127 | } else { |
1128 | /* | |
1129 | * disable aggregations for the queue, this will also make the | |
1130 | * ra_tid mapping configuration irrelevant since it is now a | |
1131 | * non-AGG queue. | |
1132 | */ | |
1133 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
f4772520 EG |
1134 | |
1135 | ssn = trans_pcie->txq[txq_id].q.read_ptr; | |
4beaf6c2 | 1136 | } |
48d42c42 EG |
1137 | |
1138 | /* Place first TFD at index corresponding to start sequence number. | |
1139 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
1140 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
1141 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
1ce8658c EG |
1142 | |
1143 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, | |
1144 | (ssn & 0xff) | (txq_id << 8)); | |
1145 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); | |
48d42c42 EG |
1146 | |
1147 | /* Set up Tx window size and frame limit for this queue */ | |
4fd442db | 1148 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + |
4beaf6c2 | 1149 | SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); |
4fd442db | 1150 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + |
9eae88fa JB |
1151 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
1152 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
1153 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
1154 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1155 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
48d42c42 | 1156 | |
48d42c42 | 1157 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ |
1ce8658c EG |
1158 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), |
1159 | (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
1160 | (fifo << SCD_QUEUE_STTS_REG_POS_TXF) | | |
1161 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
1162 | SCD_QUEUE_STTS_REG_MSK); | |
b967613d | 1163 | trans_pcie->txq[txq_id].active = true; |
1ce8658c EG |
1164 | IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n", |
1165 | txq_id, fifo, ssn & 0xff); | |
4beaf6c2 EG |
1166 | } |
1167 | ||
f02831be | 1168 | void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id) |
288712a6 | 1169 | { |
8ad71bef | 1170 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
986ea6c9 EG |
1171 | u32 stts_addr = trans_pcie->scd_base_addr + |
1172 | SCD_TX_STTS_QUEUE_OFFSET(txq_id); | |
1173 | static const u32 zero_val[4] = {}; | |
288712a6 | 1174 | |
fba1c627 EG |
1175 | /* |
1176 | * Upon HW Rfkill - we stop the device, and then stop the queues | |
1177 | * in the op_mode. Just for the sake of the simplicity of the op_mode, | |
1178 | * allow the op_mode to call txq_disable after it already called | |
1179 | * stop_device. | |
1180 | */ | |
9eae88fa | 1181 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
fba1c627 EG |
1182 | WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), |
1183 | "queue %d not used", txq_id); | |
9eae88fa | 1184 | return; |
48d42c42 EG |
1185 | } |
1186 | ||
f02831be | 1187 | iwl_pcie_txq_set_inactive(trans, txq_id); |
ac928f8d | 1188 | |
4fd442db EG |
1189 | iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, |
1190 | ARRAY_SIZE(zero_val)); | |
986ea6c9 | 1191 | |
990aa6d7 | 1192 | iwl_pcie_txq_unmap(trans, txq_id); |
68972c46 | 1193 | trans_pcie->txq[txq_id].ampdu = false; |
6c3fd3f0 | 1194 | |
1ce8658c | 1195 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
48d42c42 EG |
1196 | } |
1197 | ||
fd4abac5 TW |
1198 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
1199 | ||
990aa6d7 | 1200 | /* |
f02831be | 1201 | * iwl_pcie_enqueue_hcmd - enqueue a uCode command |
fd4abac5 | 1202 | * @priv: device private data point |
e89044d7 | 1203 | * @cmd: a pointer to the ucode command structure |
fd4abac5 | 1204 | * |
e89044d7 EP |
1205 | * The function returns < 0 values to indicate the operation |
1206 | * failed. On success, it returns the index (>= 0) of command in the | |
fd4abac5 TW |
1207 | * command queue. |
1208 | */ | |
f02831be EG |
1209 | static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, |
1210 | struct iwl_host_cmd *cmd) | |
fd4abac5 | 1211 | { |
8ad71bef | 1212 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1213 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 1214 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
1215 | struct iwl_device_cmd *out_cmd; |
1216 | struct iwl_cmd_meta *out_meta; | |
b9439491 | 1217 | unsigned long flags; |
f4feb8ac | 1218 | void *dup_buf = NULL; |
fd4abac5 | 1219 | dma_addr_t phys_addr; |
f4feb8ac | 1220 | int idx; |
38c0f334 | 1221 | u16 copy_size, cmd_size, scratch_size; |
4ce7cc2b | 1222 | bool had_nocopy = false; |
b9439491 | 1223 | int i, ret; |
96791422 | 1224 | u32 cmd_pos; |
1afbfb60 JB |
1225 | const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; |
1226 | u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; | |
fd4abac5 | 1227 | |
4ce7cc2b JB |
1228 | copy_size = sizeof(out_cmd->hdr); |
1229 | cmd_size = sizeof(out_cmd->hdr); | |
1230 | ||
1231 | /* need one for the header if the first is NOCOPY */ | |
1afbfb60 | 1232 | BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); |
4ce7cc2b | 1233 | |
1afbfb60 | 1234 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 JB |
1235 | cmddata[i] = cmd->data[i]; |
1236 | cmdlen[i] = cmd->len[i]; | |
1237 | ||
4ce7cc2b JB |
1238 | if (!cmd->len[i]) |
1239 | continue; | |
8a964f44 | 1240 | |
38c0f334 JB |
1241 | /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */ |
1242 | if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { | |
1243 | int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; | |
8a964f44 JB |
1244 | |
1245 | if (copy > cmdlen[i]) | |
1246 | copy = cmdlen[i]; | |
1247 | cmdlen[i] -= copy; | |
1248 | cmddata[i] += copy; | |
1249 | copy_size += copy; | |
1250 | } | |
1251 | ||
4ce7cc2b JB |
1252 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { |
1253 | had_nocopy = true; | |
f4feb8ac JB |
1254 | if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { |
1255 | idx = -EINVAL; | |
1256 | goto free_dup_buf; | |
1257 | } | |
1258 | } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { | |
1259 | /* | |
1260 | * This is also a chunk that isn't copied | |
1261 | * to the static buffer so set had_nocopy. | |
1262 | */ | |
1263 | had_nocopy = true; | |
1264 | ||
1265 | /* only allowed once */ | |
1266 | if (WARN_ON(dup_buf)) { | |
1267 | idx = -EINVAL; | |
1268 | goto free_dup_buf; | |
1269 | } | |
1270 | ||
8a964f44 | 1271 | dup_buf = kmemdup(cmddata[i], cmdlen[i], |
f4feb8ac JB |
1272 | GFP_ATOMIC); |
1273 | if (!dup_buf) | |
1274 | return -ENOMEM; | |
4ce7cc2b JB |
1275 | } else { |
1276 | /* NOCOPY must not be followed by normal! */ | |
f4feb8ac JB |
1277 | if (WARN_ON(had_nocopy)) { |
1278 | idx = -EINVAL; | |
1279 | goto free_dup_buf; | |
1280 | } | |
8a964f44 | 1281 | copy_size += cmdlen[i]; |
4ce7cc2b JB |
1282 | } |
1283 | cmd_size += cmd->len[i]; | |
1284 | } | |
fd4abac5 | 1285 | |
3e41ace5 JB |
1286 | /* |
1287 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
1288 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
1289 | * allocated into separate TFDs, then we will need to | |
1290 | * increase the size of the buffers. | |
3e41ace5 | 1291 | */ |
2a79e45e JB |
1292 | if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, |
1293 | "Command %s (%#x) is too large (%d bytes)\n", | |
990aa6d7 | 1294 | get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) { |
f4feb8ac JB |
1295 | idx = -EINVAL; |
1296 | goto free_dup_buf; | |
1297 | } | |
fd4abac5 | 1298 | |
015c15e1 | 1299 | spin_lock_bh(&txq->lock); |
3598e177 | 1300 | |
c2acea8e | 1301 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 1302 | spin_unlock_bh(&txq->lock); |
3598e177 | 1303 | |
6d8f6eeb | 1304 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 1305 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
f4feb8ac JB |
1306 | idx = -ENOSPC; |
1307 | goto free_dup_buf; | |
fd4abac5 TW |
1308 | } |
1309 | ||
4ce7cc2b | 1310 | idx = get_cmd_index(q, q->write_ptr); |
bf8440e6 JB |
1311 | out_cmd = txq->entries[idx].cmd; |
1312 | out_meta = &txq->entries[idx].meta; | |
c2acea8e | 1313 | |
8ce73f3a | 1314 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
1315 | if (cmd->flags & CMD_WANT_SKB) |
1316 | out_meta->source = cmd; | |
fd4abac5 | 1317 | |
4ce7cc2b | 1318 | /* set up the header */ |
fd4abac5 | 1319 | |
4ce7cc2b | 1320 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 1321 | out_cmd->hdr.flags = 0; |
cefeaa5f | 1322 | out_cmd->hdr.sequence = |
c6f600fc | 1323 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | |
cefeaa5f | 1324 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
1325 | |
1326 | /* and copy the data that needs to be copied */ | |
96791422 | 1327 | cmd_pos = offsetof(struct iwl_device_cmd, payload); |
8a964f44 | 1328 | copy_size = sizeof(out_cmd->hdr); |
1afbfb60 | 1329 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 JB |
1330 | int copy = 0; |
1331 | ||
cc904c71 | 1332 | if (!cmd->len[i]) |
4ce7cc2b | 1333 | continue; |
8a964f44 | 1334 | |
38c0f334 JB |
1335 | /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */ |
1336 | if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { | |
1337 | copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; | |
8a964f44 JB |
1338 | |
1339 | if (copy > cmd->len[i]) | |
1340 | copy = cmd->len[i]; | |
1341 | } | |
1342 | ||
1343 | /* copy everything if not nocopy/dup */ | |
1344 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | | |
1345 | IWL_HCMD_DFL_DUP))) | |
1346 | copy = cmd->len[i]; | |
1347 | ||
1348 | if (copy) { | |
1349 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); | |
1350 | cmd_pos += copy; | |
1351 | copy_size += copy; | |
1352 | } | |
96791422 EG |
1353 | } |
1354 | ||
d9fb6465 | 1355 | IWL_DEBUG_HC(trans, |
20d3b647 | 1356 | "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", |
990aa6d7 | 1357 | get_cmd_string(trans_pcie, out_cmd->hdr.cmd), |
20d3b647 JB |
1358 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), |
1359 | cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); | |
4ce7cc2b | 1360 | |
38c0f334 JB |
1361 | /* start the TFD with the scratchbuf */ |
1362 | scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE); | |
1363 | memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size); | |
1364 | iwl_pcie_txq_build_tfd(trans, txq, | |
1365 | iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr), | |
1366 | scratch_size, 1); | |
1367 | ||
1368 | /* map first command fragment, if any remains */ | |
1369 | if (copy_size > scratch_size) { | |
1370 | phys_addr = dma_map_single(trans->dev, | |
1371 | ((u8 *)&out_cmd->hdr) + scratch_size, | |
1372 | copy_size - scratch_size, | |
1373 | DMA_TO_DEVICE); | |
1374 | if (dma_mapping_error(trans->dev, phys_addr)) { | |
1375 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1376 | &txq->tfds[q->write_ptr]); | |
1377 | idx = -ENOMEM; | |
1378 | goto out; | |
1379 | } | |
8a964f44 | 1380 | |
38c0f334 JB |
1381 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, |
1382 | copy_size - scratch_size, 0); | |
2c46f72e JB |
1383 | } |
1384 | ||
8a964f44 | 1385 | /* map the remaining (adjusted) nocopy/dup fragments */ |
1afbfb60 | 1386 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 | 1387 | const void *data = cmddata[i]; |
f4feb8ac | 1388 | |
8a964f44 | 1389 | if (!cmdlen[i]) |
4ce7cc2b | 1390 | continue; |
f4feb8ac JB |
1391 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
1392 | IWL_HCMD_DFL_DUP))) | |
4ce7cc2b | 1393 | continue; |
f4feb8ac JB |
1394 | if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) |
1395 | data = dup_buf; | |
1396 | phys_addr = dma_map_single(trans->dev, (void *)data, | |
98891754 | 1397 | cmdlen[i], DMA_TO_DEVICE); |
1042db2a | 1398 | if (dma_mapping_error(trans->dev, phys_addr)) { |
f02831be | 1399 | iwl_pcie_tfd_unmap(trans, out_meta, |
98891754 | 1400 | &txq->tfds[q->write_ptr]); |
4ce7cc2b JB |
1401 | idx = -ENOMEM; |
1402 | goto out; | |
1403 | } | |
1404 | ||
8a964f44 | 1405 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], 0); |
4ce7cc2b | 1406 | } |
df833b1d | 1407 | |
afaf6b57 | 1408 | out_meta->flags = cmd->flags; |
f4feb8ac JB |
1409 | if (WARN_ON_ONCE(txq->entries[idx].free_buf)) |
1410 | kfree(txq->entries[idx].free_buf); | |
1411 | txq->entries[idx].free_buf = dup_buf; | |
2c46f72e | 1412 | |
8a964f44 | 1413 | trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr); |
df833b1d | 1414 | |
7c5ba4a8 JB |
1415 | /* start timer if queue currently empty */ |
1416 | if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout) | |
1417 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1418 | ||
b9439491 EG |
1419 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
1420 | ||
1421 | /* | |
1422 | * wake up the NIC to make sure that the firmware will see the host | |
1423 | * command - we will let the NIC sleep once all the host commands | |
e7f76340 EG |
1424 | * returned. This needs to be done only on NICs that have |
1425 | * apmg_wake_up_wa set. | |
b9439491 | 1426 | */ |
e7f76340 EG |
1427 | if (trans->cfg->base_params->apmg_wake_up_wa && |
1428 | !trans_pcie->cmd_in_flight) { | |
b9439491 EG |
1429 | trans_pcie->cmd_in_flight = true; |
1430 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, | |
1431 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1432 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
1433 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
1434 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
1435 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), | |
1436 | 15000); | |
1437 | if (ret < 0) { | |
1438 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
1439 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1440 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); | |
1441 | trans_pcie->cmd_in_flight = false; | |
1442 | idx = -EIO; | |
1443 | goto out; | |
1444 | } | |
1445 | } | |
1446 | ||
fd4abac5 TW |
1447 | /* Increment and update queue's write index */ |
1448 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
990aa6d7 | 1449 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
fd4abac5 | 1450 | |
b9439491 EG |
1451 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
1452 | ||
2c46f72e | 1453 | out: |
015c15e1 | 1454 | spin_unlock_bh(&txq->lock); |
f4feb8ac JB |
1455 | free_dup_buf: |
1456 | if (idx < 0) | |
1457 | kfree(dup_buf); | |
7bfedc59 | 1458 | return idx; |
fd4abac5 TW |
1459 | } |
1460 | ||
990aa6d7 EG |
1461 | /* |
1462 | * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them | |
17b88929 | 1463 | * @rxb: Rx buffer to reclaim |
247c61d6 EG |
1464 | * @handler_status: return value of the handler of the command |
1465 | * (put in setup_rx_handlers) | |
17b88929 TW |
1466 | * |
1467 | * If an Rx buffer has an async callback associated with it the callback | |
1468 | * will be executed. The attached skb (if present) will only be freed | |
1469 | * if the callback returns 1 | |
1470 | */ | |
990aa6d7 EG |
1471 | void iwl_pcie_hcmd_complete(struct iwl_trans *trans, |
1472 | struct iwl_rx_cmd_buffer *rxb, int handler_status) | |
17b88929 | 1473 | { |
2f301227 | 1474 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
1475 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
1476 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1477 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1478 | int cmd_index; |
c2acea8e JB |
1479 | struct iwl_device_cmd *cmd; |
1480 | struct iwl_cmd_meta *meta; | |
8ad71bef | 1481 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1482 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
1483 | |
1484 | /* If a Tx command is being handled and it isn't in the actual | |
1485 | * command queue then there a command routing bug has been introduced | |
1486 | * in the queue management code. */ | |
c6f600fc | 1487 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 1488 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
20d3b647 JB |
1489 | txq_id, trans_pcie->cmd_queue, sequence, |
1490 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
1491 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 1492 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 1493 | return; |
01ef9323 | 1494 | } |
17b88929 | 1495 | |
2bfb5092 | 1496 | spin_lock_bh(&txq->lock); |
015c15e1 | 1497 | |
4ce7cc2b | 1498 | cmd_index = get_cmd_index(&txq->q, index); |
bf8440e6 JB |
1499 | cmd = txq->entries[cmd_index].cmd; |
1500 | meta = &txq->entries[cmd_index].meta; | |
17b88929 | 1501 | |
98891754 | 1502 | iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]); |
c33de625 | 1503 | |
17b88929 | 1504 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 1505 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 1506 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 1507 | |
65b94a4a JB |
1508 | meta->source->resp_pkt = pkt; |
1509 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 1510 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 1511 | meta->source->handler_status = handler_status; |
247c61d6 | 1512 | } |
2624e96c | 1513 | |
f02831be | 1514 | iwl_pcie_cmdq_reclaim(trans, txq_id, index); |
17b88929 | 1515 | |
c2acea8e | 1516 | if (!(meta->flags & CMD_ASYNC)) { |
eb7ff77e | 1517 | if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { |
05c89b91 WYG |
1518 | IWL_WARN(trans, |
1519 | "HCMD_ACTIVE already clear for command %s\n", | |
990aa6d7 | 1520 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
05c89b91 | 1521 | } |
eb7ff77e | 1522 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
6d8f6eeb | 1523 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1524 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
f946b529 | 1525 | wake_up(&trans_pcie->wait_command_queue); |
17b88929 | 1526 | } |
3598e177 | 1527 | |
dd487449 | 1528 | meta->flags = 0; |
3598e177 | 1529 | |
2bfb5092 | 1530 | spin_unlock_bh(&txq->lock); |
17b88929 | 1531 | } |
253a634c | 1532 | |
9439eac7 | 1533 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
253a634c | 1534 | |
f02831be EG |
1535 | static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, |
1536 | struct iwl_host_cmd *cmd) | |
253a634c | 1537 | { |
d9fb6465 | 1538 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1539 | int ret; |
1540 | ||
1541 | /* An asynchronous command can not expect an SKB to be set. */ | |
1542 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
1543 | return -EINVAL; | |
1544 | ||
f02831be | 1545 | ret = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c | 1546 | if (ret < 0) { |
721c32f7 | 1547 | IWL_ERR(trans, |
b36b110c | 1548 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1549 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1550 | return ret; |
1551 | } | |
1552 | return 0; | |
1553 | } | |
1554 | ||
f02831be EG |
1555 | static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, |
1556 | struct iwl_host_cmd *cmd) | |
253a634c | 1557 | { |
8ad71bef | 1558 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1559 | int cmd_idx; |
1560 | int ret; | |
1561 | ||
6d8f6eeb | 1562 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
990aa6d7 | 1563 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1564 | |
eb7ff77e AN |
1565 | if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, |
1566 | &trans->status), | |
bcbb8c9c JB |
1567 | "Command %s: a command is already active!\n", |
1568 | get_cmd_string(trans_pcie, cmd->id))) | |
2cc39c94 | 1569 | return -EIO; |
2cc39c94 | 1570 | |
6d8f6eeb | 1571 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1572 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1573 | |
f02831be | 1574 | cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c EG |
1575 | if (cmd_idx < 0) { |
1576 | ret = cmd_idx; | |
eb7ff77e | 1577 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
721c32f7 | 1578 | IWL_ERR(trans, |
b36b110c | 1579 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1580 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1581 | return ret; |
1582 | } | |
1583 | ||
b9439491 EG |
1584 | ret = wait_event_timeout(trans_pcie->wait_command_queue, |
1585 | !test_bit(STATUS_SYNC_HCMD_ACTIVE, | |
1586 | &trans->status), | |
1587 | HOST_COMPLETE_TIMEOUT); | |
253a634c | 1588 | if (!ret) { |
6dde8c48 JB |
1589 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
1590 | struct iwl_queue *q = &txq->q; | |
d10630af | 1591 | |
6dde8c48 JB |
1592 | IWL_ERR(trans, "Error sending %s: time out after %dms.\n", |
1593 | get_cmd_string(trans_pcie, cmd->id), | |
1594 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
253a634c | 1595 | |
6dde8c48 JB |
1596 | IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", |
1597 | q->read_ptr, q->write_ptr); | |
d10630af | 1598 | |
eb7ff77e | 1599 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
6dde8c48 JB |
1600 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
1601 | get_cmd_string(trans_pcie, cmd->id)); | |
1602 | ret = -ETIMEDOUT; | |
42550a53 | 1603 | |
cfadc3ff | 1604 | iwl_write_prph(trans, DEVICE_SET_NMI_REG, 1); |
2a988e98 | 1605 | iwl_trans_fw_error(trans); |
42550a53 | 1606 | |
6dde8c48 | 1607 | goto cancel; |
253a634c EG |
1608 | } |
1609 | ||
eb7ff77e | 1610 | if (test_bit(STATUS_FW_ERROR, &trans->status)) { |
d18aa87f | 1611 | IWL_ERR(trans, "FW error in SYNC CMD %s\n", |
990aa6d7 | 1612 | get_cmd_string(trans_pcie, cmd->id)); |
b656fa33 | 1613 | dump_stack(); |
d18aa87f JB |
1614 | ret = -EIO; |
1615 | goto cancel; | |
1616 | } | |
1617 | ||
1094fa26 | 1618 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
eb7ff77e | 1619 | test_bit(STATUS_RFKILL, &trans->status)) { |
f946b529 EG |
1620 | IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); |
1621 | ret = -ERFKILL; | |
1622 | goto cancel; | |
1623 | } | |
1624 | ||
65b94a4a | 1625 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 1626 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
990aa6d7 | 1627 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
1628 | ret = -EIO; |
1629 | goto cancel; | |
1630 | } | |
1631 | ||
1632 | return 0; | |
1633 | ||
1634 | cancel: | |
1635 | if (cmd->flags & CMD_WANT_SKB) { | |
1636 | /* | |
1637 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1638 | * TX cmd queue. Otherwise in case the cmd comes | |
1639 | * in later, it will possibly set an invalid | |
1640 | * address (cmd->meta.source). | |
1641 | */ | |
bf8440e6 JB |
1642 | trans_pcie->txq[trans_pcie->cmd_queue]. |
1643 | entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; | |
253a634c | 1644 | } |
9cac4943 | 1645 | |
65b94a4a JB |
1646 | if (cmd->resp_pkt) { |
1647 | iwl_free_resp(cmd); | |
1648 | cmd->resp_pkt = NULL; | |
253a634c EG |
1649 | } |
1650 | ||
1651 | return ret; | |
1652 | } | |
1653 | ||
f02831be | 1654 | int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 1655 | { |
4f59334b | 1656 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
eb7ff77e | 1657 | test_bit(STATUS_RFKILL, &trans->status)) { |
754d7d9e EG |
1658 | IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", |
1659 | cmd->id); | |
f946b529 | 1660 | return -ERFKILL; |
754d7d9e | 1661 | } |
f946b529 | 1662 | |
253a634c | 1663 | if (cmd->flags & CMD_ASYNC) |
f02831be | 1664 | return iwl_pcie_send_hcmd_async(trans, cmd); |
253a634c | 1665 | |
f946b529 | 1666 | /* We still can fail on RFKILL that can be asserted while we wait */ |
f02831be | 1667 | return iwl_pcie_send_hcmd_sync(trans, cmd); |
253a634c EG |
1668 | } |
1669 | ||
f02831be EG |
1670 | int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
1671 | struct iwl_device_cmd *dev_cmd, int txq_id) | |
a0eaad71 | 1672 | { |
8ad71bef | 1673 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
f02831be EG |
1674 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
1675 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; | |
1676 | struct iwl_cmd_meta *out_meta; | |
1677 | struct iwl_txq *txq; | |
1678 | struct iwl_queue *q; | |
38c0f334 JB |
1679 | dma_addr_t tb0_phys, tb1_phys, scratch_phys; |
1680 | void *tb1_addr; | |
1681 | u16 len, tb1_len, tb2_len; | |
ea68f460 | 1682 | bool wait_write_ptr; |
f02831be EG |
1683 | __le16 fc = hdr->frame_control; |
1684 | u8 hdr_len = ieee80211_hdrlen(fc); | |
68972c46 | 1685 | u16 wifi_seq; |
f02831be EG |
1686 | |
1687 | txq = &trans_pcie->txq[txq_id]; | |
1688 | q = &txq->q; | |
a0eaad71 | 1689 | |
961de6a5 JB |
1690 | if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), |
1691 | "TX on unused queue %d\n", txq_id)) | |
f02831be | 1692 | return -EINVAL; |
39644e9a | 1693 | |
f02831be | 1694 | spin_lock(&txq->lock); |
015c15e1 | 1695 | |
f02831be EG |
1696 | /* In AGG mode, the index in the ring must correspond to the WiFi |
1697 | * sequence number. This is a HW requirements to help the SCD to parse | |
1698 | * the BA. | |
1699 | * Check here that the packets are in the right place on the ring. | |
1700 | */ | |
9a886586 | 1701 | wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); |
1092b9bc | 1702 | WARN_ONCE(txq->ampdu && |
68972c46 | 1703 | (wifi_seq & 0xff) != q->write_ptr, |
f02831be EG |
1704 | "Q: %d WiFi Seq %d tfdNum %d", |
1705 | txq_id, wifi_seq, q->write_ptr); | |
f02831be EG |
1706 | |
1707 | /* Set up driver data for this TFD */ | |
1708 | txq->entries[q->write_ptr].skb = skb; | |
1709 | txq->entries[q->write_ptr].cmd = dev_cmd; | |
1710 | ||
f02831be EG |
1711 | dev_cmd->hdr.sequence = |
1712 | cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
1713 | INDEX_TO_SEQ(q->write_ptr))); | |
1714 | ||
38c0f334 JB |
1715 | tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr); |
1716 | scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + | |
1717 | offsetof(struct iwl_tx_cmd, scratch); | |
1718 | ||
1719 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
1720 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
1721 | ||
f02831be EG |
1722 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ |
1723 | out_meta = &txq->entries[q->write_ptr].meta; | |
a0eaad71 | 1724 | |
f02831be | 1725 | /* |
38c0f334 JB |
1726 | * The second TB (tb1) points to the remainder of the TX command |
1727 | * and the 802.11 header - dword aligned size | |
1728 | * (This calculation modifies the TX command, so do it before the | |
1729 | * setup of the first TB) | |
f02831be | 1730 | */ |
38c0f334 JB |
1731 | len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + |
1732 | hdr_len - IWL_HCMD_SCRATCHBUF_SIZE; | |
1092b9bc | 1733 | tb1_len = ALIGN(len, 4); |
f02831be EG |
1734 | |
1735 | /* Tell NIC about any 2-byte padding after MAC header */ | |
38c0f334 | 1736 | if (tb1_len != len) |
f02831be EG |
1737 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; |
1738 | ||
38c0f334 JB |
1739 | /* The first TB points to the scratchbuf data - min_copy bytes */ |
1740 | memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr, | |
1741 | IWL_HCMD_SCRATCHBUF_SIZE); | |
1742 | iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, | |
1743 | IWL_HCMD_SCRATCHBUF_SIZE, 1); | |
f02831be | 1744 | |
38c0f334 JB |
1745 | /* there must be data left over for TB1 or this code must be changed */ |
1746 | BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE); | |
1747 | ||
1748 | /* map the data for TB1 */ | |
1749 | tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE; | |
1750 | tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); | |
1751 | if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) | |
1752 | goto out_err; | |
1753 | iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, 0); | |
a0eaad71 | 1754 | |
38c0f334 JB |
1755 | /* |
1756 | * Set up TFD's third entry to point directly to remainder | |
1757 | * of skb, if any (802.11 null frames have no payload). | |
1758 | */ | |
1759 | tb2_len = skb->len - hdr_len; | |
1760 | if (tb2_len > 0) { | |
1761 | dma_addr_t tb2_phys = dma_map_single(trans->dev, | |
1762 | skb->data + hdr_len, | |
1763 | tb2_len, DMA_TO_DEVICE); | |
1764 | if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { | |
1765 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1766 | &txq->tfds[q->write_ptr]); | |
f02831be EG |
1767 | goto out_err; |
1768 | } | |
38c0f334 | 1769 | iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, 0); |
f02831be | 1770 | } |
a0eaad71 | 1771 | |
f02831be EG |
1772 | /* Set up entry for this TFD in Tx byte-count array */ |
1773 | iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); | |
a0eaad71 | 1774 | |
f02831be EG |
1775 | trace_iwlwifi_dev_tx(trans->dev, skb, |
1776 | &txq->tfds[txq->q.write_ptr], | |
1777 | sizeof(struct iwl_tfd), | |
38c0f334 JB |
1778 | &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len, |
1779 | skb->data + hdr_len, tb2_len); | |
f02831be | 1780 | trace_iwlwifi_dev_tx_data(trans->dev, skb, |
38c0f334 JB |
1781 | skb->data + hdr_len, tb2_len); |
1782 | ||
ea68f460 | 1783 | wait_write_ptr = ieee80211_has_morefrags(fc); |
7c5ba4a8 | 1784 | |
f02831be EG |
1785 | /* start timer if queue currently empty */ |
1786 | if (txq->need_update && q->read_ptr == q->write_ptr && | |
1787 | trans_pcie->wd_timeout) | |
1788 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1789 | ||
1790 | /* Tell device the write index *just past* this latest filled TFD */ | |
1791 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
ea68f460 JB |
1792 | if (!wait_write_ptr) |
1793 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
f02831be EG |
1794 | |
1795 | /* | |
1796 | * At this point the frame is "transmitted" successfully | |
43aa616f | 1797 | * and we will get a TX status notification eventually. |
f02831be EG |
1798 | */ |
1799 | if (iwl_queue_space(q) < q->high_mark) { | |
ea68f460 | 1800 | if (wait_write_ptr) |
f02831be | 1801 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
ea68f460 | 1802 | else |
f02831be | 1803 | iwl_stop_queue(trans, txq); |
f02831be EG |
1804 | } |
1805 | spin_unlock(&txq->lock); | |
1806 | return 0; | |
1807 | out_err: | |
1808 | spin_unlock(&txq->lock); | |
1809 | return -1; | |
a0eaad71 | 1810 | } |