[deliverable/linux.git] / drivers / net / wireless / iwmc3200wifi / tx.c

/*
 * Intel Wireless Multicomm 3200 WiFi driver
 *
 * Copyright (C) 2009 Intel Corporation. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *   * Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *   * Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in
 *     the documentation and/or other materials provided with the
 *     distribution.
 *   * Neither the name of Intel Corporation nor the names of its
 *     contributors may be used to endorse or promote products derived
 *     from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *
 * Intel Corporation <ilw@linux.intel.com>
 * Samuel Ortiz <samuel.ortiz@intel.com>
 * Zhu Yi <yi.zhu@intel.com>
 *
 */

/*
 * iwm Tx theory of operation:
 *
 * 1) We receive a 802.3 frame from the stack
 * 2) We convert it to a 802.11 frame [iwm_xmit_frame]
 * 3) We queue it to its corresponding tx queue [iwm_xmit_frame]
 * 4) We schedule the tx worker. There is one worker per tx
 *    queue. [iwm_xmit_frame]
 * 5) The tx worker is scheduled
 * 6) We go through every queued skb on the tx queue, and for each
 *    and every one of them: [iwm_tx_worker]
 *    a) We check if we have enough Tx credits (see below for a Tx
 *       credits description) for the frame length. [iwm_tx_worker]
 *    b) If we do, we aggregate the Tx frame into a UDMA one, by
 *       concatenating one REPLY_TX command per Tx frame. [iwm_tx_worker]
 *    c) When we run out of credits, or when we reach the maximum
 *       concatenation size, we actually send the concatenated UDMA
 *       frame. [iwm_tx_worker]
 *
 * When we run out of Tx credits, the skbs are filling the tx queue,
 * and eventually we will stop the netdev queue. [iwm_tx_worker]
 * The tx queue is emptied as we're getting new tx credits, by
 * scheduling the tx_worker. [iwm_tx_credit_inc]
 * The netdev queue is started again when we have enough tx credits,
 * and when our tx queue has some reasonable amout of space available
 * (i.e. half of the max size). [iwm_tx_worker]
 */

#include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/ieee80211.h>

#include "iwm.h"
#include "debug.h"
#include "commands.h"
#include "hal.h"
#include "umac.h"
#include "bus.h"

#define IWM_UMAC_PAGE_ALLOC_WRAP 0xffff

#define BYTES_TO_PAGES(n)	 (1 + ((n) >> ilog2(IWM_UMAC_PAGE_SIZE)) - \
				 (((n) & (IWM_UMAC_PAGE_SIZE - 1)) == 0))

#define pool_id_to_queue(id)	 ((id < IWM_TX_CMD_QUEUE) ? id : id - 1)
#define queue_to_pool_id(q)	 ((q < IWM_TX_CMD_QUEUE) ? q : q + 1)

/* require to hold tx_credit lock */
static int iwm_tx_credit_get(struct iwm_tx_credit *tx_credit, int id)
{
	struct pool_entry *pool = &tx_credit->pools[id];
	struct spool_entry *spool = &tx_credit->spools[pool->sid];
	int spool_pages;

	/* number of pages can be taken from spool by this pool */
	spool_pages = spool->max_pages - spool->alloc_pages +
		      max(pool->min_pages - pool->alloc_pages, 0);

	return min(pool->max_pages - pool->alloc_pages, spool_pages);
}

static bool iwm_tx_credit_ok(struct iwm_priv *iwm, int id, int nb)
{
	u32 npages = BYTES_TO_PAGES(nb);

	if (npages <= iwm_tx_credit_get(&iwm->tx_credit, id))
		return 1;

	set_bit(id, &iwm->tx_credit.full_pools_map);

	IWM_DBG_TX(iwm, DBG, "LINK: stop txq[%d], available credit: %d\n",
		   pool_id_to_queue(id),
		   iwm_tx_credit_get(&iwm->tx_credit, id));

	return 0;
}

void iwm_tx_credit_inc(struct iwm_priv *iwm, int id, int total_freed_pages)
{
	struct pool_entry *pool;
	struct spool_entry *spool;
	int freed_pages;
	int queue;

	BUG_ON(id >= IWM_MACS_OUT_GROUPS);

	pool = &iwm->tx_credit.pools[id];
	spool = &iwm->tx_credit.spools[pool->sid];

	freed_pages = total_freed_pages - pool->total_freed_pages;
	IWM_DBG_TX(iwm, DBG, "Free %d pages for pool[%d]\n", freed_pages, id);

	if (!freed_pages) {
		IWM_DBG_TX(iwm, DBG, "No pages are freed by UMAC\n");
		return;
	} else if (freed_pages < 0)
		freed_pages += IWM_UMAC_PAGE_ALLOC_WRAP + 1;

	if (pool->alloc_pages > pool->min_pages) {
		int spool_pages = pool->alloc_pages - pool->min_pages;
		spool_pages = min(spool_pages, freed_pages);
		spool->alloc_pages -= spool_pages;
	}

	pool->alloc_pages -= freed_pages;
	pool->total_freed_pages = total_freed_pages;

	IWM_DBG_TX(iwm, DBG, "Pool[%d] pages alloc: %d, total_freed: %d, "
		   "Spool[%d] pages alloc: %d\n", id, pool->alloc_pages,
		   pool->total_freed_pages, pool->sid, spool->alloc_pages);

	if (test_bit(id, &iwm->tx_credit.full_pools_map) &&
	    (pool->alloc_pages < pool->max_pages / 2)) {
		clear_bit(id, &iwm->tx_credit.full_pools_map);

		queue = pool_id_to_queue(id);

		IWM_DBG_TX(iwm, DBG, "LINK: start txq[%d], available "
			   "credit: %d\n", queue,
			   iwm_tx_credit_get(&iwm->tx_credit, id));
		queue_work(iwm->txq[queue].wq, &iwm->txq[queue].worker);
	}
}

static void iwm_tx_credit_dec(struct iwm_priv *iwm, int id, int alloc_pages)
{
	struct pool_entry *pool;
	struct spool_entry *spool;
	int spool_pages;

	IWM_DBG_TX(iwm, DBG, "Allocate %d pages for pool[%d]\n",
		   alloc_pages, id);

	BUG_ON(id >= IWM_MACS_OUT_GROUPS);

	pool = &iwm->tx_credit.pools[id];
	spool = &iwm->tx_credit.spools[pool->sid];

	spool_pages = pool->alloc_pages + alloc_pages - pool->min_pages;

	if (pool->alloc_pages >= pool->min_pages)
		spool->alloc_pages += alloc_pages;
	else if (spool_pages > 0)
		spool->alloc_pages += spool_pages;

	pool->alloc_pages += alloc_pages;

	IWM_DBG_TX(iwm, DBG, "Pool[%d] pages alloc: %d, total_freed: %d, "
		   "Spool[%d] pages alloc: %d\n", id, pool->alloc_pages,
		   pool->total_freed_pages, pool->sid, spool->alloc_pages);
}

int iwm_tx_credit_alloc(struct iwm_priv *iwm, int id, int nb)
{
	u32 npages = BYTES_TO_PAGES(nb);
	int ret = 0;

	spin_lock(&iwm->tx_credit.lock);

	if (!iwm_tx_credit_ok(iwm, id, nb)) {
		IWM_DBG_TX(iwm, DBG, "No credit avaliable for pool[%d]\n", id);
		ret = -ENOSPC;
		goto out;
	}

	iwm_tx_credit_dec(iwm, id, npages);

 out:
	spin_unlock(&iwm->tx_credit.lock);
	return ret;
}

/*
 * Since we're on an SDIO or USB bus, we are not sharing memory
 * for storing to be transmitted frames. The host needs to push
 * them upstream. As a consequence there needs to be a way for
 * the target to let us know if it can actually take more TX frames
 * or not. This is what Tx credits are for.
 *
 * For each Tx HW queue, we have a Tx pool, and then we have one
 * unique super pool (spool), which is actually a global pool of
 * all the UMAC pages.
 * For each Tx pool we have a min_pages, a max_pages fields, and a
 * alloc_pages fields. The alloc_pages tracks the number of pages
 * currently allocated from the tx pool.
 * Here are the rules to check if given a tx frame we have enough
 * tx credits for it:
 * 1) We translate the frame length into a number of UMAC pages.
 *    Let's call them n_pages.
 * 2) For the corresponding tx pool, we check if n_pages +
 *    pool->alloc_pages is higher than pool->min_pages. min_pages
 *    represent a set of pre-allocated pages on the tx pool. If
 *    that's the case, then we need to allocate those pages from
 *    the spool. We can do so until we reach spool->max_pages.
 * 3) Each tx pool is not allowed to allocate more than pool->max_pages
 *    from the spool, so once we're over min_pages, we can allocate
 *    pages from the spool, but not more than max_pages.
 *
 * When the tx code path needs to send a tx frame, it checks first
 * if it has enough tx credits, following those rules. [iwm_tx_credit_get]
 * If it does, it then updates the pool and spool counters and
 * then send the frame. [iwm_tx_credit_alloc and iwm_tx_credit_dec]
 * On the other side, when the UMAC is done transmitting frames, it
 * will send a credit update notification to the host. This is when
 * the pool and spool counters gets to be decreased. [iwm_tx_credit_inc,
 * called from rx.c:iwm_ntf_tx_credit_update]
 *
 */
void iwm_tx_credit_init_pools(struct iwm_priv *iwm,
			      struct iwm_umac_notif_alive *alive)
{
	int i, sid, pool_pages;

	spin_lock(&iwm->tx_credit.lock);

	iwm->tx_credit.pool_nr = le16_to_cpu(alive->page_grp_count);
	iwm->tx_credit.full_pools_map = 0;
	memset(&iwm->tx_credit.spools[0], 0, sizeof(struct spool_entry));

	IWM_DBG_TX(iwm, DBG, "Pools number is %d\n", iwm->tx_credit.pool_nr);

	for (i = 0; i < iwm->tx_credit.pool_nr; i++) {
		__le32 page_grp_state = alive->page_grp_state[i];

		iwm->tx_credit.pools[i].id = GET_VAL32(page_grp_state,
				UMAC_ALIVE_PAGE_STS_GRP_NUM);
		iwm->tx_credit.pools[i].sid = GET_VAL32(page_grp_state,
				UMAC_ALIVE_PAGE_STS_SGRP_NUM);
		iwm->tx_credit.pools[i].min_pages = GET_VAL32(page_grp_state,
				UMAC_ALIVE_PAGE_STS_GRP_MIN_SIZE);
		iwm->tx_credit.pools[i].max_pages = GET_VAL32(page_grp_state,
				UMAC_ALIVE_PAGE_STS_GRP_MAX_SIZE);
		iwm->tx_credit.pools[i].alloc_pages = 0;
		iwm->tx_credit.pools[i].total_freed_pages = 0;

		sid = iwm->tx_credit.pools[i].sid;
		pool_pages = iwm->tx_credit.pools[i].min_pages;

		if (iwm->tx_credit.spools[sid].max_pages == 0) {
			iwm->tx_credit.spools[sid].id = sid;
			iwm->tx_credit.spools[sid].max_pages =
				GET_VAL32(page_grp_state,
					  UMAC_ALIVE_PAGE_STS_SGRP_MAX_SIZE);
			iwm->tx_credit.spools[sid].alloc_pages = 0;
		}

		iwm->tx_credit.spools[sid].alloc_pages += pool_pages;

		IWM_DBG_TX(iwm, DBG, "Pool idx: %d, id: %d, sid: %d, capacity "
			   "min: %d, max: %d, pool alloc: %d, total_free: %d, "
			   "super poll alloc: %d\n",
			   i, iwm->tx_credit.pools[i].id,
			   iwm->tx_credit.pools[i].sid,
			   iwm->tx_credit.pools[i].min_pages,
			   iwm->tx_credit.pools[i].max_pages,
			   iwm->tx_credit.pools[i].alloc_pages,
			   iwm->tx_credit.pools[i].total_freed_pages,
			   iwm->tx_credit.spools[sid].alloc_pages);
	}

	spin_unlock(&iwm->tx_credit.lock);
}

#define IWM_UDMA_HDR_LEN	sizeof(struct iwm_umac_wifi_out_hdr)

static int iwm_tx_build_packet(struct iwm_priv *iwm, struct sk_buff *skb,
			       int pool_id, u8 *buf)
{
	struct iwm_umac_wifi_out_hdr *hdr = (struct iwm_umac_wifi_out_hdr *)buf;
	struct iwm_udma_wifi_cmd udma_cmd;
	struct iwm_umac_cmd umac_cmd;
	struct iwm_tx_info *tx_info = skb_to_tx_info(skb);

	udma_cmd.count = cpu_to_le16(skb->len +
				     sizeof(struct iwm_umac_fw_cmd_hdr));
	/* set EOP to 0 here. iwm_udma_wifi_hdr_set_eop() will be
	 * called later to set EOP for the last packet. */
	udma_cmd.eop = 0;
	udma_cmd.credit_group = pool_id;
	udma_cmd.ra_tid = tx_info->sta << 4 | tx_info->tid;
	udma_cmd.lmac_offset = 0;

	umac_cmd.id = REPLY_TX;
	umac_cmd.count = cpu_to_le16(skb->len);
	umac_cmd.color = tx_info->color;
	umac_cmd.resp = 0;
	umac_cmd.seq_num = cpu_to_le16(iwm_alloc_wifi_cmd_seq(iwm));

	iwm_build_udma_wifi_hdr(iwm, &hdr->hw_hdr, &udma_cmd);
	iwm_build_umac_hdr(iwm, &hdr->sw_hdr, &umac_cmd);

	memcpy(buf + sizeof(*hdr), skb->data, skb->len);

	return umac_cmd.seq_num;
}

static int iwm_tx_send_concat_packets(struct iwm_priv *iwm,
				      struct iwm_tx_queue *txq)
{
	int ret;

	if (!txq->concat_count)
		return 0;

	IWM_DBG_TX(iwm, DBG, "Send concatenated Tx: queue %d, %d bytes\n",
		   txq->id, txq->concat_count);

	/* mark EOP for the last packet */
	iwm_udma_wifi_hdr_set_eop(iwm, txq->concat_ptr, 1);

	ret = iwm_bus_send_chunk(iwm, txq->concat_buf, txq->concat_count);

	txq->concat_count = 0;
	txq->concat_ptr = txq->concat_buf;

	return ret;
}

void iwm_tx_worker(struct work_struct *work)
{
	struct iwm_priv *iwm;
	struct iwm_tx_info *tx_info = NULL;
	struct sk_buff *skb;
	struct iwm_tx_queue *txq;
	struct iwm_sta_info *sta_info;
	struct iwm_tid_info *tid_info;
	int cmdlen, ret, pool_id;

	txq = container_of(work, struct iwm_tx_queue, worker);
	iwm = container_of(txq, struct iwm_priv, txq[txq->id]);

	pool_id = queue_to_pool_id(txq->id);

	while (!test_bit(pool_id, &iwm->tx_credit.full_pools_map) &&
	       !skb_queue_empty(&txq->queue)) {

		spin_lock_bh(&txq->lock);
		skb = skb_dequeue(&txq->queue);
		spin_unlock_bh(&txq->lock);

		tx_info = skb_to_tx_info(skb);
		sta_info = &iwm->sta_table[tx_info->sta];
		if (!sta_info->valid) {
			IWM_ERR(iwm, "Trying to send a frame to unknown STA\n");
			kfree_skb(skb);
			continue;
		}

		tid_info = &sta_info->tid_info[tx_info->tid];

		mutex_lock(&tid_info->mutex);

		/*
		 * If the RAxTID is stopped, we queue the skb to the stopped
		 * queue.
		 * Whenever we'll get a UMAC notification to resume the tx flow
		 * for this RAxTID, we'll merge back the stopped queue into the
		 * regular queue. See iwm_ntf_stop_resume_tx() from rx.c.
		 */
		if (tid_info->stopped) {
			IWM_DBG_TX(iwm, DBG, "%dx%d stopped\n",
				   tx_info->sta, tx_info->tid);
			spin_lock_bh(&txq->lock);
			skb_queue_tail(&txq->stopped_queue, skb);
			spin_unlock_bh(&txq->lock);

			mutex_unlock(&tid_info->mutex);
			continue;
		}

		cmdlen = IWM_UDMA_HDR_LEN + skb->len;

		IWM_DBG_TX(iwm, DBG, "Tx frame on queue %d: skb: 0x%p, sta: "
			   "%d, color: %d\n", txq->id, skb, tx_info->sta,
			   tx_info->color);

		if (txq->concat_count + cmdlen > IWM_HAL_CONCATENATE_BUF_SIZE)
			iwm_tx_send_concat_packets(iwm, txq);

		ret = iwm_tx_credit_alloc(iwm, pool_id, cmdlen);
		if (ret) {
			IWM_DBG_TX(iwm, DBG, "not enough tx_credit for queue "
				   "%d, Tx worker stopped\n", txq->id);
			spin_lock_bh(&txq->lock);
			skb_queue_head(&txq->queue, skb);
			spin_unlock_bh(&txq->lock);

			mutex_unlock(&tid_info->mutex);
			break;
		}

		txq->concat_ptr = txq->concat_buf + txq->concat_count;
		tid_info->last_seq_num =
			iwm_tx_build_packet(iwm, skb, pool_id, txq->concat_ptr);
		txq->concat_count += ALIGN(cmdlen, 16);

		mutex_unlock(&tid_info->mutex);

		kfree_skb(skb);
	}

	iwm_tx_send_concat_packets(iwm, txq);

	if (__netif_subqueue_stopped(iwm_to_ndev(iwm), txq->id) &&
	    !test_bit(pool_id, &iwm->tx_credit.full_pools_map) &&
	    (skb_queue_len(&txq->queue) < IWM_TX_LIST_SIZE / 2)) {
		IWM_DBG_TX(iwm, DBG, "LINK: start netif_subqueue[%d]", txq->id);
		netif_wake_subqueue(iwm_to_ndev(iwm), txq->id);
	}
}

int iwm_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
{
	struct iwm_priv *iwm = ndev_to_iwm(netdev);
	struct net_device *ndev = iwm_to_ndev(iwm);
	struct wireless_dev *wdev = iwm_to_wdev(iwm);
	struct iwm_tx_info *tx_info;
	struct iwm_tx_queue *txq;
	struct iwm_sta_info *sta_info;
	u8 *dst_addr, sta_id;
	u16 queue;
	int ret;


	if (!test_bit(IWM_STATUS_ASSOCIATED, &iwm->status)) {
		IWM_DBG_TX(iwm, DBG, "LINK: stop netif_all_queues: "
			   "not associated\n");
		netif_tx_stop_all_queues(netdev);
		goto drop;
	}

	queue = skb_get_queue_mapping(skb);
	BUG_ON(queue >= IWM_TX_DATA_QUEUES); /* no iPAN yet */

	txq = &iwm->txq[queue];

	/* No free space for Tx, tx_worker is too slow */
	if ((skb_queue_len(&txq->queue) > IWM_TX_LIST_SIZE) ||
	    (skb_queue_len(&txq->stopped_queue) > IWM_TX_LIST_SIZE)) {
		IWM_DBG_TX(iwm, DBG, "LINK: stop netif_subqueue[%d]\n", queue);
		netif_stop_subqueue(netdev, queue);
		return NETDEV_TX_BUSY;
	}

	ret = ieee80211_data_from_8023(skb, netdev->dev_addr, wdev->iftype,
				       iwm->bssid, 0);
	if (ret) {
		IWM_ERR(iwm, "build wifi header failed\n");
		goto drop;
	}

	dst_addr = ((struct ieee80211_hdr *)(skb->data))->addr1;

	for (sta_id = 0; sta_id < IWM_STA_TABLE_NUM; sta_id++) {
		sta_info = &iwm->sta_table[sta_id];
		if (sta_info->valid &&
		    !memcmp(dst_addr, sta_info->addr, ETH_ALEN))
			break;
	}

	if (sta_id == IWM_STA_TABLE_NUM) {
		IWM_ERR(iwm, "STA %pM not found in sta_table, Tx ignored\n",
			dst_addr);
		goto drop;
	}

	tx_info = skb_to_tx_info(skb);
	tx_info->sta = sta_id;
	tx_info->color = sta_info->color;
	/* UMAC uses TID 8 (vs. 0) for non QoS packets */
	if (sta_info->qos)
		tx_info->tid = skb->priority;
	else
		tx_info->tid = IWM_UMAC_MGMT_TID;

	spin_lock_bh(&iwm->txq[queue].lock);
	skb_queue_tail(&iwm->txq[queue].queue, skb);
	spin_unlock_bh(&iwm->txq[queue].lock);

	queue_work(iwm->txq[queue].wq, &iwm->txq[queue].worker);

	ndev->stats.tx_packets++;
	ndev->stats.tx_bytes += skb->len;
	return NETDEV_TX_OK;

 drop:
	ndev->stats.tx_dropped++;
	dev_kfree_skb_any(skb);
	return NETDEV_TX_OK;
}
Commit	Line	Data
bb9f8692 ZY	1	/*
	2	* Intel Wireless Multicomm 3200 WiFi driver
	3	*
	4	* Copyright (C) 2009 Intel Corporation. All rights reserved.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in
	14	* the documentation and/or other materials provided with the
	15	* distribution.
	16	* * Neither the name of Intel Corporation nor the names of its
	17	* contributors may be used to endorse or promote products derived
	18	* from this software without specific prior written permission.
	19	*
	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	21	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	22	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	23	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	24	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	25	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	26	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	27	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	28	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	30	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*
	32	*
	33	* Intel Corporation <ilw@linux.intel.com>
	34	* Samuel Ortiz <samuel.ortiz@intel.com>
	35	* Zhu Yi <yi.zhu@intel.com>
	36	*
	37	*/
	38
	39	/*
	40	* iwm Tx theory of operation:
	41	*
	42	* 1) We receive a 802.3 frame from the stack
	43	* 2) We convert it to a 802.11 frame [iwm_xmit_frame]
	44	* 3) We queue it to its corresponding tx queue [iwm_xmit_frame]
	45	* 4) We schedule the tx worker. There is one worker per tx
	46	* queue. [iwm_xmit_frame]
	47	* 5) The tx worker is scheduled
	48	* 6) We go through every queued skb on the tx queue, and for each
	49	* and every one of them: [iwm_tx_worker]
	50	* a) We check if we have enough Tx credits (see below for a Tx
	51	* credits description) for the frame length. [iwm_tx_worker]
	52	* b) If we do, we aggregate the Tx frame into a UDMA one, by
	53	* concatenating one REPLY_TX command per Tx frame. [iwm_tx_worker]
	54	* c) When we run out of credits, or when we reach the maximum
	55	* concatenation size, we actually send the concatenated UDMA
	56	* frame. [iwm_tx_worker]
	57	*
	58	* When we run out of Tx credits, the skbs are filling the tx queue,
	59	* and eventually we will stop the netdev queue. [iwm_tx_worker]
	60	* The tx queue is emptied as we're getting new tx credits, by
	61	* scheduling the tx_worker. [iwm_tx_credit_inc]
	62	* The netdev queue is started again when we have enough tx credits,
	63	* and when our tx queue has some reasonable amout of space available
	64	* (i.e. half of the max size). [iwm_tx_worker]
65	*/
66
67	#include <linux/skbuff.h>
68	#include <linux/netdevice.h>
69	#include <linux/ieee80211.h>
70
71	#include "iwm.h"
72	#include "debug.h"
73	#include "commands.h"
74	#include "hal.h"
75	#include "umac.h"
76	#include "bus.h"
77
78	#define IWM_UMAC_PAGE_ALLOC_WRAP 0xffff
79
80	#define BYTES_TO_PAGES(n) (1 + ((n) >> ilog2(IWM_UMAC_PAGE_SIZE)) - \
81	(((n) & (IWM_UMAC_PAGE_SIZE - 1)) == 0))
82
83	#define pool_id_to_queue(id) ((id < IWM_TX_CMD_QUEUE) ? id : id - 1)
84	#define queue_to_pool_id(q) ((q < IWM_TX_CMD_QUEUE) ? q : q + 1)
85
86	/* require to hold tx_credit lock */
87	static int iwm_tx_credit_get(struct iwm_tx_credit *tx_credit, int id)
88	{
89	struct pool_entry *pool = &tx_credit->pools[id];
90	struct spool_entry *spool = &tx_credit->spools[pool->sid];
91	int spool_pages;
92
93	/* number of pages can be taken from spool by this pool */
94	spool_pages = spool->max_pages - spool->alloc_pages +
95	max(pool->min_pages - pool->alloc_pages, 0);
96
97	return min(pool->max_pages - pool->alloc_pages, spool_pages);
98	}
99
100	static bool iwm_tx_credit_ok(struct iwm_priv *iwm, int id, int nb)
101	{
102	u32 npages = BYTES_TO_PAGES(nb);
103
104	if (npages <= iwm_tx_credit_get(&iwm->tx_credit, id))
105	return 1;
106
107	set_bit(id, &iwm->tx_credit.full_pools_map);
108
109	IWM_DBG_TX(iwm, DBG, "LINK: stop txq[%d], available credit: %d\n",
110	pool_id_to_queue(id),
111	iwm_tx_credit_get(&iwm->tx_credit, id));
112
113	return 0;
114	}
115
116	void iwm_tx_credit_inc(struct iwm_priv *iwm, int id, int total_freed_pages)
117	{
118	struct pool_entry *pool;
119	struct spool_entry *spool;
120	int freed_pages;
121	int queue;
122
123	BUG_ON(id >= IWM_MACS_OUT_GROUPS);
124
125	pool = &iwm->tx_credit.pools[id];
126	spool = &iwm->tx_credit.spools[pool->sid];
127
128	freed_pages = total_freed_pages - pool->total_freed_pages;
129	IWM_DBG_TX(iwm, DBG, "Free %d pages for pool[%d]\n", freed_pages, id);
130
131	if (!freed_pages) {
132	IWM_DBG_TX(iwm, DBG, "No pages are freed by UMAC\n");
133	return;
134	} else if (freed_pages < 0)
135	freed_pages += IWM_UMAC_PAGE_ALLOC_WRAP + 1;
136
137	if (pool->alloc_pages > pool->min_pages) {
138	int spool_pages = pool->alloc_pages - pool->min_pages;
139	spool_pages = min(spool_pages, freed_pages);
140	spool->alloc_pages -= spool_pages;
141	}
142
143	pool->alloc_pages -= freed_pages;
144	pool->total_freed_pages = total_freed_pages;
145
146	IWM_DBG_TX(iwm, DBG, "Pool[%d] pages alloc: %d, total_freed: %d, "
147	"Spool[%d] pages alloc: %d\n", id, pool->alloc_pages,
148	pool->total_freed_pages, pool->sid, spool->alloc_pages);
149
150	if (test_bit(id, &iwm->tx_credit.full_pools_map) &&
151	(pool->alloc_pages < pool->max_pages / 2)) {
152	clear_bit(id, &iwm->tx_credit.full_pools_map);
153
154	queue = pool_id_to_queue(id);
155
156	IWM_DBG_TX(iwm, DBG, "LINK: start txq[%d], available "
157	"credit: %d\n", queue,
158	iwm_tx_credit_get(&iwm->tx_credit, id));
159	queue_work(iwm->txq[queue].wq, &iwm->txq[queue].worker);
160	}
161	}
162
163	static void iwm_tx_credit_dec(struct iwm_priv *iwm, int id, int alloc_pages)
164	{
165	struct pool_entry *pool;
166	struct spool_entry *spool;
167	int spool_pages;
168
169	IWM_DBG_TX(iwm, DBG, "Allocate %d pages for pool[%d]\n",
170	alloc_pages, id);
171
172	BUG_ON(id >= IWM_MACS_OUT_GROUPS);
173
174	pool = &iwm->tx_credit.pools[id];
175	spool = &iwm->tx_credit.spools[pool->sid];
176
177	spool_pages = pool->alloc_pages + alloc_pages - pool->min_pages;
178
179	if (pool->alloc_pages >= pool->min_pages)
180	spool->alloc_pages += alloc_pages;
181	else if (spool_pages > 0)
182	spool->alloc_pages += spool_pages;
183
184	pool->alloc_pages += alloc_pages;
185
186	IWM_DBG_TX(iwm, DBG, "Pool[%d] pages alloc: %d, total_freed: %d, "
187	"Spool[%d] pages alloc: %d\n", id, pool->alloc_pages,
188	pool->total_freed_pages, pool->sid, spool->alloc_pages);
189	}
190
191	int iwm_tx_credit_alloc(struct iwm_priv *iwm, int id, int nb)
192	{
193	u32 npages = BYTES_TO_PAGES(nb);
194	int ret = 0;
195
196	spin_lock(&iwm->tx_credit.lock);
197
198	if (!iwm_tx_credit_ok(iwm, id, nb)) {
199	IWM_DBG_TX(iwm, DBG, "No credit avaliable for pool[%d]\n", id);
200	ret = -ENOSPC;
201	goto out;
202	}
203
204	iwm_tx_credit_dec(iwm, id, npages);
205
206	out:
207	spin_unlock(&iwm->tx_credit.lock);
208	return ret;
209	}
210
211	/*
212	* Since we're on an SDIO or USB bus, we are not sharing memory
213	* for storing to be transmitted frames. The host needs to push
214	* them upstream. As a consequence there needs to be a way for
215	* the target to let us know if it can actually take more TX frames
216	* or not. This is what Tx credits are for.
217	*
218	* For each Tx HW queue, we have a Tx pool, and then we have one
219	* unique super pool (spool), which is actually a global pool of
220	* all the UMAC pages.
221	* For each Tx pool we have a min_pages, a max_pages fields, and a
222	* alloc_pages fields. The alloc_pages tracks the number of pages
223	* currently allocated from the tx pool.
224	* Here are the rules to check if given a tx frame we have enough
225	* tx credits for it:
226	* 1) We translate the frame length into a number of UMAC pages.
227	* Let's call them n_pages.
228	* 2) For the corresponding tx pool, we check if n_pages +
229	* pool->alloc_pages is higher than pool->min_pages. min_pages
230	* represent a set of pre-allocated pages on the tx pool. If
231	* that's the case, then we need to allocate those pages from
232	* the spool. We can do so until we reach spool->max_pages.
233	* 3) Each tx pool is not allowed to allocate more than pool->max_pages
234	* from the spool, so once we're over min_pages, we can allocate
235	* pages from the spool, but not more than max_pages.
236	*
237	* When the tx code path needs to send a tx frame, it checks first
238	* if it has enough tx credits, following those rules. [iwm_tx_credit_get]
239	* If it does, it then updates the pool and spool counters and
240	* then send the frame. [iwm_tx_credit_alloc and iwm_tx_credit_dec]
241	* On the other side, when the UMAC is done transmitting frames, it
242	* will send a credit update notification to the host. This is when
243	* the pool and spool counters gets to be decreased. [iwm_tx_credit_inc,
244	* called from rx.c:iwm_ntf_tx_credit_update]
245	*
246	*/
247	void iwm_tx_credit_init_pools(struct iwm_priv *iwm,
248	struct iwm_umac_notif_alive *alive)
249	{
250	int i, sid, pool_pages;
251
252	spin_lock(&iwm->tx_credit.lock);
253
254	iwm->tx_credit.pool_nr = le16_to_cpu(alive->page_grp_count);
255	iwm->tx_credit.full_pools_map = 0;
256	memset(&iwm->tx_credit.spools[0], 0, sizeof(struct spool_entry));
257
258	IWM_DBG_TX(iwm, DBG, "Pools number is %d\n", iwm->tx_credit.pool_nr);
259
260	for (i = 0; i < iwm->tx_credit.pool_nr; i++) {
261	__le32 page_grp_state = alive->page_grp_state[i];
262
263	iwm->tx_credit.pools[i].id = GET_VAL32(page_grp_state,
264	UMAC_ALIVE_PAGE_STS_GRP_NUM);
265	iwm->tx_credit.pools[i].sid = GET_VAL32(page_grp_state,
266	UMAC_ALIVE_PAGE_STS_SGRP_NUM);
267	iwm->tx_credit.pools[i].min_pages = GET_VAL32(page_grp_state,
268	UMAC_ALIVE_PAGE_STS_GRP_MIN_SIZE);
269	iwm->tx_credit.pools[i].max_pages = GET_VAL32(page_grp_state,
270	UMAC_ALIVE_PAGE_STS_GRP_MAX_SIZE);
271	iwm->tx_credit.pools[i].alloc_pages = 0;
272	iwm->tx_credit.pools[i].total_freed_pages = 0;
273
274	sid = iwm->tx_credit.pools[i].sid;
275	pool_pages = iwm->tx_credit.pools[i].min_pages;
276
277	if (iwm->tx_credit.spools[sid].max_pages == 0) {
278	iwm->tx_credit.spools[sid].id = sid;
279	iwm->tx_credit.spools[sid].max_pages =
280	GET_VAL32(page_grp_state,
281	UMAC_ALIVE_PAGE_STS_SGRP_MAX_SIZE);
282	iwm->tx_credit.spools[sid].alloc_pages = 0;
283	}
284
285	iwm->tx_credit.spools[sid].alloc_pages += pool_pages;
286
287	IWM_DBG_TX(iwm, DBG, "Pool idx: %d, id: %d, sid: %d, capacity "
288	"min: %d, max: %d, pool alloc: %d, total_free: %d, "
289	"super poll alloc: %d\n",
290	i, iwm->tx_credit.pools[i].id,
291	iwm->tx_credit.pools[i].sid,
292	iwm->tx_credit.pools[i].min_pages,
293	iwm->tx_credit.pools[i].max_pages,
294	iwm->tx_credit.pools[i].alloc_pages,
295	iwm->tx_credit.pools[i].total_freed_pages,
296	iwm->tx_credit.spools[sid].alloc_pages);
297	}
298
299	spin_unlock(&iwm->tx_credit.lock);
300	}
301
302	#define IWM_UDMA_HDR_LEN sizeof(struct iwm_umac_wifi_out_hdr)
303
304	static int iwm_tx_build_packet(struct iwm_priv iwm, struct sk_buff skb,
305	int pool_id, u8 *buf)
306	{
307	struct iwm_umac_wifi_out_hdr hdr = (struct iwm_umac_wifi_out_hdr )buf;
308	struct iwm_udma_wifi_cmd udma_cmd;
309	struct iwm_umac_cmd umac_cmd;
310	struct iwm_tx_info *tx_info = skb_to_tx_info(skb);
311
312	udma_cmd.count = cpu_to_le16(skb->len +
313	sizeof(struct iwm_umac_fw_cmd_hdr));
314	/* set EOP to 0 here. iwm_udma_wifi_hdr_set_eop() will be
315	* called later to set EOP for the last packet. */
316	udma_cmd.eop = 0;
317	udma_cmd.credit_group = pool_id;
318	udma_cmd.ra_tid = tx_info->sta << 4 \| tx_info->tid;
319	udma_cmd.lmac_offset = 0;
320
321	umac_cmd.id = REPLY_TX;
322	umac_cmd.count = cpu_to_le16(skb->len);
323	umac_cmd.color = tx_info->color;
324	umac_cmd.resp = 0;
325	umac_cmd.seq_num = cpu_to_le16(iwm_alloc_wifi_cmd_seq(iwm));
326
327	iwm_build_udma_wifi_hdr(iwm, &hdr->hw_hdr, &udma_cmd);
328	iwm_build_umac_hdr(iwm, &hdr->sw_hdr, &umac_cmd);
329
330	memcpy(buf + sizeof(*hdr), skb->data, skb->len);
331
a7af530d	332	return umac_cmd.seq_num;
bb9f8692 ZY	333	}
	334
	335	static int iwm_tx_send_concat_packets(struct iwm_priv *iwm,
	336	struct iwm_tx_queue *txq)
	337	{
	338	int ret;
	339
	340	if (!txq->concat_count)
	341	return 0;
	342
	343	IWM_DBG_TX(iwm, DBG, "Send concatenated Tx: queue %d, %d bytes\n",
	344	txq->id, txq->concat_count);
	345
	346	/* mark EOP for the last packet */
	347	iwm_udma_wifi_hdr_set_eop(iwm, txq->concat_ptr, 1);
	348
	349	ret = iwm_bus_send_chunk(iwm, txq->concat_buf, txq->concat_count);
	350
	351	txq->concat_count = 0;
	352	txq->concat_ptr = txq->concat_buf;
	353
	354	return ret;
	355	}
	356
bb9f8692 ZY	357	void iwm_tx_worker(struct work_struct *work)
	358	{
	359	struct iwm_priv *iwm;
	360	struct iwm_tx_info *tx_info = NULL;
	361	struct sk_buff *skb;
bb9f8692	362	struct iwm_tx_queue *txq;
a7af530d SO	363	struct iwm_sta_info *sta_info;
	364	struct iwm_tid_info *tid_info;
	365	int cmdlen, ret, pool_id;
bb9f8692 ZY	366
	367	txq = container_of(work, struct iwm_tx_queue, worker);
	368	iwm = container_of(txq, struct iwm_priv, txq[txq->id]);
	369
	370	pool_id = queue_to_pool_id(txq->id);
	371
	372	while (!test_bit(pool_id, &iwm->tx_credit.full_pools_map) &&
	373	!skb_queue_empty(&txq->queue)) {
	374
a7af530d	375	spin_lock_bh(&txq->lock);
bb9f8692	376	skb = skb_dequeue(&txq->queue);
a7af530d SO	377	spin_unlock_bh(&txq->lock);
a7af530d SO	378
bb9f8692	379	tx_info = skb_to_tx_info(skb);
a7af530d SO	380	sta_info = &iwm->sta_table[tx_info->sta];
	381	if (!sta_info->valid) {
	382	IWM_ERR(iwm, "Trying to send a frame to unknown STA\n");
	383	kfree_skb(skb);
	384	continue;
	385	}
	386
	387	tid_info = &sta_info->tid_info[tx_info->tid];
	388
	389	mutex_lock(&tid_info->mutex);
	390
	391	/*
	392	* If the RAxTID is stopped, we queue the skb to the stopped
	393	* queue.
	394	* Whenever we'll get a UMAC notification to resume the tx flow
	395	* for this RAxTID, we'll merge back the stopped queue into the
	396	* regular queue. See iwm_ntf_stop_resume_tx() from rx.c.
	397	*/
	398	if (tid_info->stopped) {
	399	IWM_DBG_TX(iwm, DBG, "%dx%d stopped\n",
	400	tx_info->sta, tx_info->tid);
	401	spin_lock_bh(&txq->lock);
	402	skb_queue_tail(&txq->stopped_queue, skb);
	403	spin_unlock_bh(&txq->lock);
	404
	405	mutex_unlock(&tid_info->mutex);
	406	continue;
	407	}
	408
bb9f8692 ZY	409	cmdlen = IWM_UDMA_HDR_LEN + skb->len;
	410
	411	IWM_DBG_TX(iwm, DBG, "Tx frame on queue %d: skb: 0x%p, sta: "
	412	"%d, color: %d\n", txq->id, skb, tx_info->sta,
	413	tx_info->color);
	414
bb9f8692 ZY	415	if (txq->concat_count + cmdlen > IWM_HAL_CONCATENATE_BUF_SIZE)
	416	iwm_tx_send_concat_packets(iwm, txq);
	417
	418	ret = iwm_tx_credit_alloc(iwm, pool_id, cmdlen);
	419	if (ret) {
	420	IWM_DBG_TX(iwm, DBG, "not enough tx_credit for queue "
	421	"%d, Tx worker stopped\n", txq->id);
a7af530d	422	spin_lock_bh(&txq->lock);
bb9f8692	423	skb_queue_head(&txq->queue, skb);
a7af530d SO	424	spin_unlock_bh(&txq->lock);
	425
	426	mutex_unlock(&tid_info->mutex);
bb9f8692 ZY	427	break;
	428	}
	429
	430	txq->concat_ptr = txq->concat_buf + txq->concat_count;
a7af530d SO	431	tid_info->last_seq_num =
a7af530d SO	432	iwm_tx_build_packet(iwm, skb, pool_id, txq->concat_ptr);
bb9f8692	433	txq->concat_count += ALIGN(cmdlen, 16);
a7af530d SO	434
a7af530d SO	435	mutex_unlock(&tid_info->mutex);
6b65b6ad	436
bb9f8692 ZY	437	kfree_skb(skb);
	438	}
	439
	440	iwm_tx_send_concat_packets(iwm, txq);
	441
	442	if (__netif_subqueue_stopped(iwm_to_ndev(iwm), txq->id) &&
	443	!test_bit(pool_id, &iwm->tx_credit.full_pools_map) &&
	444	(skb_queue_len(&txq->queue) < IWM_TX_LIST_SIZE / 2)) {
	445	IWM_DBG_TX(iwm, DBG, "LINK: start netif_subqueue[%d]", txq->id);
	446	netif_wake_subqueue(iwm_to_ndev(iwm), txq->id);
	447	}
	448	}
	449
	450	int iwm_xmit_frame(struct sk_buff skb, struct net_device netdev)
	451	{
	452	struct iwm_priv *iwm = ndev_to_iwm(netdev);
	453	struct net_device *ndev = iwm_to_ndev(iwm);
	454	struct wireless_dev *wdev = iwm_to_wdev(iwm);
bb9f8692 ZY	455	struct iwm_tx_info *tx_info;
	456	struct iwm_tx_queue *txq;
	457	struct iwm_sta_info *sta_info;
a7af530d	458	u8 *dst_addr, sta_id;
bb9f8692 ZY	459	u16 queue;
	460	int ret;
	461
a7af530d	462
bb9f8692 ZY	463	if (!test_bit(IWM_STATUS_ASSOCIATED, &iwm->status)) {
	464	IWM_DBG_TX(iwm, DBG, "LINK: stop netif_all_queues: "
	465	"not associated\n");
	466	netif_tx_stop_all_queues(netdev);
	467	goto drop;
	468	}
	469
	470	queue = skb_get_queue_mapping(skb);
	471	BUG_ON(queue >= IWM_TX_DATA_QUEUES); /* no iPAN yet */
	472
	473	txq = &iwm->txq[queue];
	474
	475	/* No free space for Tx, tx_worker is too slow */
a7af530d SO	476	if ((skb_queue_len(&txq->queue) > IWM_TX_LIST_SIZE) \|\|
a7af530d SO	477	(skb_queue_len(&txq->stopped_queue) > IWM_TX_LIST_SIZE)) {
bb9f8692 ZY	478	IWM_DBG_TX(iwm, DBG, "LINK: stop netif_subqueue[%d]\n", queue);
	479	netif_stop_subqueue(netdev, queue);
	480	return NETDEV_TX_BUSY;
	481	}
	482
	483	ret = ieee80211_data_from_8023(skb, netdev->dev_addr, wdev->iftype,
	484	iwm->bssid, 0);
	485	if (ret) {
	486	IWM_ERR(iwm, "build wifi header failed\n");
	487	goto drop;
	488	}
	489
	490	dst_addr = ((struct ieee80211_hdr *)(skb->data))->addr1;
	491
	492	for (sta_id = 0; sta_id < IWM_STA_TABLE_NUM; sta_id++) {
	493	sta_info = &iwm->sta_table[sta_id];
	494	if (sta_info->valid &&
	495	!memcmp(dst_addr, sta_info->addr, ETH_ALEN))
	496	break;
	497	}
	498
	499	if (sta_id == IWM_STA_TABLE_NUM) {
	500	IWM_ERR(iwm, "STA %pM not found in sta_table, Tx ignored\n",
	501	dst_addr);
	502	goto drop;
	503	}
	504
	505	tx_info = skb_to_tx_info(skb);
	506	tx_info->sta = sta_id;
	507	tx_info->color = sta_info->color;
	508	/* UMAC uses TID 8 (vs. 0) for non QoS packets */
	509	if (sta_info->qos)
	510	tx_info->tid = skb->priority;
	511	else
	512	tx_info->tid = IWM_UMAC_MGMT_TID;
	513
a7af530d	514	spin_lock_bh(&iwm->txq[queue].lock);
bb9f8692	515	skb_queue_tail(&iwm->txq[queue].queue, skb);
a7af530d	516	spin_unlock_bh(&iwm->txq[queue].lock);
bb9f8692 ZY	517
	518	queue_work(iwm->txq[queue].wq, &iwm->txq[queue].worker);
	519
	520	ndev->stats.tx_packets++;
	521	ndev->stats.tx_bytes += skb->len;
	522	return NETDEV_TX_OK;
	523
	524	drop:
	525	ndev->stats.tx_dropped++;
	526	dev_kfree_skb_any(skb);
	527	return NETDEV_TX_OK;
	528	}