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mwifiex: Fix request_irq() failure handling
[deliverable/linux.git] / drivers / net / wireless / marvell / mwifiex / pcie.c
CommitLineData
d930faee
AK		 1/*
2 * Marvell Wireless LAN device driver: PCIE specific handling
3 *
65da33f5 4 * Copyright (C) 2011-2014, Marvell International Ltd.
d930faee
AK		 5 *
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
13 *
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
18 */
19
20#include <linux/firmware.h>
21
22#include "decl.h"
23#include "ioctl.h"
24#include "util.h"
25#include "fw.h"
26#include "main.h"
27#include "wmm.h"
28#include "11n.h"
29#include "pcie.h"
30
31#define PCIE_VERSION "1.0"
32#define DRV_NAME "Marvell mwifiex PCIe"
33
34static u8 user_rmmod;
35
36static struct mwifiex_if_ops pcie_ops;
37
38static struct semaphore add_remove_card_sem;
d930faee 39
fc331460
AP		 40static int
41mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb,
dbccc92b 42 size_t size, int flags)
d930faee 43{
fc331460 44 struct pcie_service_card *card = adapter->card;
dbccc92b 45 struct mwifiex_dma_mapping mapping;
d930faee 46
dbccc92b
AD		 47 mapping.addr = pci_map_single(card->dev, skb->data, size, flags);
48 if (pci_dma_mapping_error(card->dev, mapping.addr)) {
acebe8c1 49 mwifiex_dbg(adapter, ERROR, "failed to map pci memory!\n");
fc331460
AP		 50 return -1;
51 }
dbccc92b 52 mapping.len = size;
bca463e8 53 mwifiex_store_mapping(skb, &mapping);
fc331460 54 return 0;
d930faee
AK		 55}
56
dbccc92b
AD		 57static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter,
58 struct sk_buff *skb, int flags)
59{
60 struct pcie_service_card *card = adapter->card;
61 struct mwifiex_dma_mapping mapping;
62
bca463e8 63 mwifiex_get_mapping(skb, &mapping);
dbccc92b
AD		 64 pci_unmap_single(card->dev, mapping.addr, mapping.len, flags);
65}
66
d930faee
AK		 67/*
68 * This function reads sleep cookie and checks if FW is ready
69 */
70static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter)
71{
72 u32 *cookie_addr;
73 struct pcie_service_card *card = adapter->card;
52301a81
AP		 74 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
75
76 if (!reg->sleep_cookie)
77 return true;
d930faee 78
fc331460
AP		 79 if (card->sleep_cookie_vbase) {
80 cookie_addr = (u32 *)card->sleep_cookie_vbase;
acebe8c1
ZL		 81 mwifiex_dbg(adapter, INFO,
82 "info: ACCESS_HW: sleep cookie=0x%x\n",
83 *cookie_addr);
d930faee
AK		 84 if (*cookie_addr == FW_AWAKE_COOKIE)
85 return true;
86 }
87
88 return false;
89}
90
3266d732 91#ifdef CONFIG_PM_SLEEP
fcca8d5a
BZ		 92/*
93 * Kernel needs to suspend all functions separately. Therefore all
94 * registered functions must have drivers with suspend and resume
95 * methods. Failing that the kernel simply removes the whole card.
96 *
97 * If already not suspended, this function allocates and sends a host
98 * sleep activate request to the firmware and turns off the traffic.
99 */
3266d732 100static int mwifiex_pcie_suspend(struct device *dev)
fcca8d5a
BZ		 101{
102 struct mwifiex_adapter *adapter;
103 struct pcie_service_card *card;
104 int hs_actived;
3266d732 105 struct pci_dev *pdev = to_pci_dev(dev);
fcca8d5a
BZ		 106
107 if (pdev) {
b2a31204 108 card = pci_get_drvdata(pdev);
fcca8d5a
BZ		 109 if (!card || !card->adapter) {
110 pr_err("Card or adapter structure is not valid\n");
111 return 0;
112 }
113 } else {
114 pr_err("PCIE device is not specified\n");
115 return 0;
116 }
117
118 adapter = card->adapter;
119
120 hs_actived = mwifiex_enable_hs(adapter);
121
122 /* Indicate device suspended */
123 adapter->is_suspended = true;
c0dbba66 124 adapter->hs_enabling = false;
fcca8d5a
BZ		 125
126 return 0;
127}
128
129/*
130 * Kernel needs to suspend all functions separately. Therefore all
131 * registered functions must have drivers with suspend and resume
132 * methods. Failing that the kernel simply removes the whole card.
133 *
134 * If already not resumed, this function turns on the traffic and
135 * sends a host sleep cancel request to the firmware.
136 */
3266d732 137static int mwifiex_pcie_resume(struct device *dev)
fcca8d5a
BZ		 138{
139 struct mwifiex_adapter *adapter;
140 struct pcie_service_card *card;
3266d732 141 struct pci_dev *pdev = to_pci_dev(dev);
fcca8d5a
BZ		 142
143 if (pdev) {
b2a31204 144 card = pci_get_drvdata(pdev);
fcca8d5a
BZ		 145 if (!card || !card->adapter) {
146 pr_err("Card or adapter structure is not valid\n");
147 return 0;
148 }
149 } else {
150 pr_err("PCIE device is not specified\n");
151 return 0;
152 }
153
154 adapter = card->adapter;
155
156 if (!adapter->is_suspended) {
acebe8c1
ZL		 157 mwifiex_dbg(adapter, WARN,
158 "Device already resumed\n");
fcca8d5a
BZ		 159 return 0;
160 }
161
162 adapter->is_suspended = false;
163
164 mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA),
165 MWIFIEX_ASYNC_CMD);
166
167 return 0;
168}
8509e820 169#endif
fcca8d5a 170
d930faee
AK		 171/*
172 * This function probes an mwifiex device and registers it. It allocates
173 * the card structure, enables PCIE function number and initiates the
174 * device registration and initialization procedure by adding a logical
175 * interface.
176 */
177static int mwifiex_pcie_probe(struct pci_dev *pdev,
178 const struct pci_device_id *ent)
179{
180 struct pcie_service_card *card;
181
182 pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n",
f57c1edc 183 pdev->vendor, pdev->device, pdev->revision);
d930faee
AK		 184
185 card = kzalloc(sizeof(struct pcie_service_card), GFP_KERNEL);
e404decb 186 if (!card)
d930faee 187 return -ENOMEM;
d930faee
AK		 188
189 card->dev = pdev;
190
dd04e6ac
AP		 191 if (ent->driver_data) {
192 struct mwifiex_pcie_device *data = (void *)ent->driver_data;
dd04e6ac
AP		 193 card->pcie.reg = data->reg;
194 card->pcie.blksz_fw_dl = data->blksz_fw_dl;
828cf222 195 card->pcie.tx_buf_size = data->tx_buf_size;
b4e8aebb 196 card->pcie.can_dump_fw = data->can_dump_fw;
50632092
XH		 197 card->pcie.mem_type_mapping_tbl = data->mem_type_mapping_tbl;
198 card->pcie.num_mem_types = data->num_mem_types;
1fe192d8 199 card->pcie.can_ext_scan = data->can_ext_scan;
dd04e6ac
AP		 200 }
201
d930faee
AK		 202 if (mwifiex_add_card(card, &add_remove_card_sem, &pcie_ops,
203 MWIFIEX_PCIE)) {
204 pr_err("%s failed\n", __func__);
d930faee
AK		 205 return -1;
206 }
207
208 return 0;
209}
210
211/*
212 * This function removes the interface and frees up the card structure.
213 */
214static void mwifiex_pcie_remove(struct pci_dev *pdev)
215{
216 struct pcie_service_card *card;
217 struct mwifiex_adapter *adapter;
f57c1edc 218 struct mwifiex_private *priv;
d930faee
AK		 219
220 card = pci_get_drvdata(pdev);
221 if (!card)
222 return;
223
224 adapter = card->adapter;
225 if (!adapter || !adapter->priv_num)
226 return;
227
228 if (user_rmmod) {
3266d732 229#ifdef CONFIG_PM_SLEEP
d930faee 230 if (adapter->is_suspended)
3266d732 231 mwifiex_pcie_resume(&pdev->dev);
d930faee
AK		 232#endif
233
848819f4 234 mwifiex_deauthenticate_all(adapter);
d930faee 235
f57c1edc 236 priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY);
d930faee 237
f57c1edc
YAP		 238 mwifiex_disable_auto_ds(priv);
239
240 mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN);
d930faee
AK		 241 }
242
243 mwifiex_remove_card(card->adapter, &add_remove_card_sem);
d930faee
AK		 244}
245
43ba6b9f
AK		 246static void mwifiex_pcie_shutdown(struct pci_dev *pdev)
247{
248 user_rmmod = 1;
249 mwifiex_pcie_remove(pdev);
250
251 return;
252}
253
9baa3c34 254static const struct pci_device_id mwifiex_ids[] = {
d930faee
AK		 255 {
256 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8766P,
257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6d85ef00 258 .driver_data = (unsigned long)&mwifiex_pcie8766,
d930faee 259 },
ca8f2112
AP		 260 {
261 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8897,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6d85ef00
ZL		 263 .driver_data = (unsigned long)&mwifiex_pcie8897,
264 },
265 {
266 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997,
267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 .driver_data = (unsigned long)&mwifiex_pcie8997,
ca8f2112 269 },
a362e16b
SL		 270 {
271 PCIE_VENDOR_ID_V2_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997,
272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 .driver_data = (unsigned long)&mwifiex_pcie8997,
274 },
d930faee
AK		 275 {},
276};
277
278MODULE_DEVICE_TABLE(pci, mwifiex_ids);
279
3266d732
SK		 280#ifdef CONFIG_PM_SLEEP
281/* Power Management Hooks */
282static SIMPLE_DEV_PM_OPS(mwifiex_pcie_pm_ops, mwifiex_pcie_suspend,
283 mwifiex_pcie_resume);
284#endif
285
d930faee
AK		 286/* PCI Device Driver */
287static struct pci_driver __refdata mwifiex_pcie = {
288 .name = "mwifiex_pcie",
289 .id_table = mwifiex_ids,
290 .probe = mwifiex_pcie_probe,
291 .remove = mwifiex_pcie_remove,
3266d732
SK		 292#ifdef CONFIG_PM_SLEEP
293 .driver = {
294 .pm = &mwifiex_pcie_pm_ops,
295 },
d930faee 296#endif
43ba6b9f 297 .shutdown = mwifiex_pcie_shutdown,
d930faee
AK		 298};
299
300/*
301 * This function writes data into PCIE card register.
302 */
303static int mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data)
304{
305 struct pcie_service_card *card = adapter->card;
306
307 iowrite32(data, card->pci_mmap1 + reg);
308
309 return 0;
310}
311
312/*
313 * This function reads data from PCIE card register.
314 */
315static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data)
316{
317 struct pcie_service_card *card = adapter->card;
318
319 *data = ioread32(card->pci_mmap1 + reg);
af051483
XH		 320 if (*data == 0xffffffff)
321 return 0xffffffff;
d930faee
AK		 322
323 return 0;
324}
325
92c2538f
AK		 326/* This function reads u8 data from PCIE card register. */
327static int mwifiex_read_reg_byte(struct mwifiex_adapter *adapter,
328 int reg, u8 *data)
329{
330 struct pcie_service_card *card = adapter->card;
331
332 *data = ioread8(card->pci_mmap1 + reg);
333
334 return 0;
335}
336
d930faee 337/*
c0880a29 338 * This function adds delay loop to ensure FW is awake before proceeding.
d930faee 339 */
c0880a29 340static void mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter *adapter)
d930faee
AK		 341{
342 int i = 0;
343
c0880a29 344 while (mwifiex_pcie_ok_to_access_hw(adapter)) {
d930faee 345 i++;
e7891ba2 346 usleep_range(10, 20);
d930faee 347 /* 50ms max wait */
3e7a4ff7 348 if (i == 5000)
d930faee
AK		 349 break;
350 }
351
c0880a29
AP		 352 return;
353}
354
c4bc980f
AP		 355static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter,
356 u32 max_delay_loop_cnt)
357{
358 struct pcie_service_card *card = adapter->card;
359 u8 *buffer;
360 u32 sleep_cookie, count;
361
362 for (count = 0; count < max_delay_loop_cnt; count++) {
363 buffer = card->cmdrsp_buf->data - INTF_HEADER_LEN;
364 sleep_cookie = *(u32 *)buffer;
365
366 if (sleep_cookie == MWIFIEX_DEF_SLEEP_COOKIE) {
acebe8c1
ZL		 367 mwifiex_dbg(adapter, INFO,
368 "sleep cookie found at count %d\n", count);
c4bc980f
AP		 369 break;
370 }
371 usleep_range(20, 30);
372 }
373
374 if (count >= max_delay_loop_cnt)
acebe8c1
ZL		 375 mwifiex_dbg(adapter, INFO,
376 "max count reached while accessing sleep cookie\n");
c4bc980f
AP		 377}
378
c0880a29
AP		 379/* This function wakes up the card by reading fw_status register. */
380static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter)
381{
382 u32 fw_status;
383 struct pcie_service_card *card = adapter->card;
384 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
385
acebe8c1
ZL		 386 mwifiex_dbg(adapter, EVENT,
387 "event: Wakeup device...\n");
d930faee 388
c0880a29
AP		 389 if (reg->sleep_cookie)
390 mwifiex_pcie_dev_wakeup_delay(adapter);
391
392 /* Reading fw_status register will wakeup device */
393 if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status)) {
acebe8c1
ZL		 394 mwifiex_dbg(adapter, ERROR,
395 "Reading fw_status register failed\n");
d930faee
AK		 396 return -1;
397 }
398
c0880a29
AP		 399 if (reg->sleep_cookie) {
400 mwifiex_pcie_dev_wakeup_delay(adapter);
acebe8c1
ZL		 401 mwifiex_dbg(adapter, INFO,
402 "PCIE wakeup: Setting PS_STATE_AWAKE\n");
c0880a29
AP		 403 adapter->ps_state = PS_STATE_AWAKE;
404 }
d930faee
AK		 405
406 return 0;
407}
408
409/*
410 * This function is called after the card has woken up.
411 *
412 * The card configuration register is reset.
413 */
414static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter)
415{
acebe8c1
ZL		 416 mwifiex_dbg(adapter, CMD,
417 "cmd: Wakeup device completed\n");
d930faee
AK		 418
419 return 0;
420}
421
422/*
423 * This function disables the host interrupt.
424 *
425 * The host interrupt mask is read, the disable bit is reset and
426 * written back to the card host interrupt mask register.
427 */
428static int mwifiex_pcie_disable_host_int(struct mwifiex_adapter *adapter)
429{
430 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
431 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
432 0x00000000)) {
acebe8c1
ZL		 433 mwifiex_dbg(adapter, ERROR,
434 "Disable host interrupt failed\n");
d930faee
AK		 435 return -1;
436 }
437 }
438
439 return 0;
440}
441
d41376ca
BN		 442static void mwifiex_pcie_disable_host_int_noerr(struct mwifiex_adapter *adapter)
443{
444 WARN_ON(mwifiex_pcie_disable_host_int(adapter));
445}
446
d930faee
AK		 447/*
448 * This function enables the host interrupt.
449 *
450 * The host interrupt enable mask is written to the card
451 * host interrupt mask register.
452 */
453static int mwifiex_pcie_enable_host_int(struct mwifiex_adapter *adapter)
454{
455 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
456 /* Simply write the mask to the register */
457 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
458 HOST_INTR_MASK)) {
acebe8c1
ZL		 459 mwifiex_dbg(adapter, ERROR,
460 "Enable host interrupt failed\n");
d930faee
AK		 461 return -1;
462 }
463 }
464
465 return 0;
466}
467
468/*
0732484b
AP		 469 * This function initializes TX buffer ring descriptors
470 */
471static int mwifiex_init_txq_ring(struct mwifiex_adapter *adapter)
472{
473 struct pcie_service_card *card = adapter->card;
ca8f2112 474 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
0732484b 475 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 476 struct mwifiex_pfu_buf_desc *desc2;
0732484b
AP		 477 int i;
478
479 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
480 card->tx_buf_list[i] = NULL;
ca8f2112
AP		 481 if (reg->pfu_enabled) {
482 card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
483 (sizeof(*desc2) * i);
484 desc2 = card->txbd_ring[i];
485 memset(desc2, 0, sizeof(*desc2));
486 } else {
487 card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
488 (sizeof(*desc) * i);
489 desc = card->txbd_ring[i];
490 memset(desc, 0, sizeof(*desc));
491 }
0732484b
AP		 492 }
493
494 return 0;
495}
496
497/* This function initializes RX buffer ring descriptors. Each SKB is allocated
498 * here and after mapping PCI memory, its physical address is assigned to
499 * PCIE Rx buffer descriptor's physical address.
500 */
501static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter)
502{
503 struct pcie_service_card *card = adapter->card;
ca8f2112 504 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
0732484b
AP		 505 struct sk_buff *skb;
506 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 507 struct mwifiex_pfu_buf_desc *desc2;
0732484b
AP		 508 dma_addr_t buf_pa;
509 int i;
510
511 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
512 /* Allocate skb here so that firmware can DMA data from it */
62159944 513 skb = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE,
5c87a55a 514 GFP_KERNEL);
0732484b 515 if (!skb) {
acebe8c1
ZL		 516 mwifiex_dbg(adapter, ERROR,
517 "Unable to allocate skb for RX ring.\n");
0732484b
AP		 518 kfree(card->rxbd_ring_vbase);
519 return -ENOMEM;
520 }
521
522 if (mwifiex_map_pci_memory(adapter, skb,
523 MWIFIEX_RX_DATA_BUF_SIZE,
524 PCI_DMA_FROMDEVICE))
525 return -1;
526
dbccc92b 527 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
0732484b 528
acebe8c1
ZL		 529 mwifiex_dbg(adapter, INFO,
530 "info: RX ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
531 skb, skb->len, skb->data, (u32)buf_pa,
532 (u32)((u64)buf_pa >> 32));
0732484b
AP		 533
534 card->rx_buf_list[i] = skb;
ca8f2112
AP		 535 if (reg->pfu_enabled) {
536 card->rxbd_ring[i] = (void *)card->rxbd_ring_vbase +
537 (sizeof(*desc2) * i);
538 desc2 = card->rxbd_ring[i];
539 desc2->paddr = buf_pa;
540 desc2->len = (u16)skb->len;
541 desc2->frag_len = (u16)skb->len;
542 desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop;
543 desc2->offset = 0;
544 } else {
545 card->rxbd_ring[i] = (void *)(card->rxbd_ring_vbase +
546 (sizeof(*desc) * i));
547 desc = card->rxbd_ring[i];
548 desc->paddr = buf_pa;
549 desc->len = (u16)skb->len;
550 desc->flags = 0;
551 }
0732484b
AP		 552 }
553
554 return 0;
555}
556
557/* This function initializes event buffer ring descriptors. Each SKB is
558 * allocated here and after mapping PCI memory, its physical address is assigned
559 * to PCIE Rx buffer descriptor's physical address
560 */
561static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter)
562{
563 struct pcie_service_card *card = adapter->card;
e05dc3e9 564 struct mwifiex_evt_buf_desc *desc;
0732484b
AP		 565 struct sk_buff *skb;
566 dma_addr_t buf_pa;
567 int i;
568
569 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
570 /* Allocate skb here so that firmware can DMA data from it */
571 skb = dev_alloc_skb(MAX_EVENT_SIZE);
572 if (!skb) {
acebe8c1
ZL		 573 mwifiex_dbg(adapter, ERROR,
574 "Unable to allocate skb for EVENT buf.\n");
0732484b
AP		 575 kfree(card->evtbd_ring_vbase);
576 return -ENOMEM;
577 }
578 skb_put(skb, MAX_EVENT_SIZE);
579
580 if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE,
581 PCI_DMA_FROMDEVICE))
582 return -1;
583
dbccc92b 584 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
0732484b 585
acebe8c1
ZL		 586 mwifiex_dbg(adapter, EVENT,
587 "info: EVT ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
588 skb, skb->len, skb->data, (u32)buf_pa,
589 (u32)((u64)buf_pa >> 32));
0732484b
AP		 590
591 card->evt_buf_list[i] = skb;
592 card->evtbd_ring[i] = (void *)(card->evtbd_ring_vbase +
593 (sizeof(*desc) * i));
0732484b
AP		 594 desc = card->evtbd_ring[i];
595 desc->paddr = buf_pa;
596 desc->len = (u16)skb->len;
597 desc->flags = 0;
598 }
599
600 return 0;
601}
602
603/* This function cleans up TX buffer rings. If any of the buffer list has valid
604 * SKB address, associated SKB is freed.
605 */
606static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter)
607{
608 struct pcie_service_card *card = adapter->card;
ca8f2112 609 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
0732484b
AP		 610 struct sk_buff *skb;
611 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 612 struct mwifiex_pfu_buf_desc *desc2;
0732484b
AP		 613 int i;
614
615 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
ca8f2112
AP		 616 if (reg->pfu_enabled) {
617 desc2 = card->txbd_ring[i];
618 if (card->tx_buf_list[i]) {
619 skb = card->tx_buf_list[i];
dbccc92b
AD		 620 mwifiex_unmap_pci_memory(adapter, skb,
621 PCI_DMA_TODEVICE);
ca8f2112
AP		 622 dev_kfree_skb_any(skb);
623 }
624 memset(desc2, 0, sizeof(*desc2));
625 } else {
626 desc = card->txbd_ring[i];
627 if (card->tx_buf_list[i]) {
628 skb = card->tx_buf_list[i];
dbccc92b
AD		 629 mwifiex_unmap_pci_memory(adapter, skb,
630 PCI_DMA_TODEVICE);
ca8f2112
AP		 631 dev_kfree_skb_any(skb);
632 }
633 memset(desc, 0, sizeof(*desc));
0732484b
AP		 634 }
635 card->tx_buf_list[i] = NULL;
0732484b
AP		 636 }
637
638 return;
639}
640
641/* This function cleans up RX buffer rings. If any of the buffer list has valid
642 * SKB address, associated SKB is freed.
643 */
644static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter)
645{
646 struct pcie_service_card *card = adapter->card;
ca8f2112 647 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
0732484b 648 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 649 struct mwifiex_pfu_buf_desc *desc2;
0732484b
AP		 650 struct sk_buff *skb;
651 int i;
652
653 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
ca8f2112
AP		 654 if (reg->pfu_enabled) {
655 desc2 = card->rxbd_ring[i];
656 if (card->rx_buf_list[i]) {
657 skb = card->rx_buf_list[i];
dbccc92b
AD		 658 mwifiex_unmap_pci_memory(adapter, skb,
659 PCI_DMA_FROMDEVICE);
ca8f2112
AP		 660 dev_kfree_skb_any(skb);
661 }
662 memset(desc2, 0, sizeof(*desc2));
663 } else {
664 desc = card->rxbd_ring[i];
665 if (card->rx_buf_list[i]) {
666 skb = card->rx_buf_list[i];
dbccc92b
AD		 667 mwifiex_unmap_pci_memory(adapter, skb,
668 PCI_DMA_FROMDEVICE);
ca8f2112
AP		 669 dev_kfree_skb_any(skb);
670 }
671 memset(desc, 0, sizeof(*desc));
0732484b 672 }
ca8f2112 673 card->rx_buf_list[i] = NULL;
0732484b
AP		 674 }
675
676 return;
677}
678
679/* This function cleans up event buffer rings. If any of the buffer list has
680 * valid SKB address, associated SKB is freed.
681 */
682static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter)
683{
684 struct pcie_service_card *card = adapter->card;
e05dc3e9 685 struct mwifiex_evt_buf_desc *desc;
0732484b
AP		 686 struct sk_buff *skb;
687 int i;
688
689 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
690 desc = card->evtbd_ring[i];
691 if (card->evt_buf_list[i]) {
692 skb = card->evt_buf_list[i];
dbccc92b
AD		 693 mwifiex_unmap_pci_memory(adapter, skb,
694 PCI_DMA_FROMDEVICE);
0732484b
AP		 695 dev_kfree_skb_any(skb);
696 }
697 card->evt_buf_list[i] = NULL;
698 memset(desc, 0, sizeof(*desc));
699 }
700
701 return;
702}
703
704/* This function creates buffer descriptor ring for TX
d930faee
AK		 705 */
706static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter)
707{
708 struct pcie_service_card *card = adapter->card;
dd04e6ac 709 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 710
711 /*
712 * driver maintaines the write pointer and firmware maintaines the read
713 * pointer. The write pointer starts at 0 (zero) while the read pointer
714 * starts at zero with rollover bit set
715 */
716 card->txbd_wrptr = 0;
ca8f2112
AP		 717
718 if (reg->pfu_enabled)
719 card->txbd_rdptr = 0;
720 else
721 card->txbd_rdptr |= reg->tx_rollover_ind;
d930faee
AK		 722
723 /* allocate shared memory for the BD ring and divide the same in to
724 several descriptors */
ca8f2112
AP		 725 if (reg->pfu_enabled)
726 card->txbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) *
727 MWIFIEX_MAX_TXRX_BD;
728 else
729 card->txbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) *
730 MWIFIEX_MAX_TXRX_BD;
731
acebe8c1
ZL		 732 mwifiex_dbg(adapter, INFO,
733 "info: txbd_ring: Allocating %d bytes\n",
734 card->txbd_ring_size);
fc331460
AP		 735 card->txbd_ring_vbase = pci_alloc_consistent(card->dev,
736 card->txbd_ring_size,
737 &card->txbd_ring_pbase);
d930faee 738 if (!card->txbd_ring_vbase) {
acebe8c1
ZL		 739 mwifiex_dbg(adapter, ERROR,
740 "allocate consistent memory (%d bytes) failed!\n",
741 card->txbd_ring_size);
8c53e42d 742 return -ENOMEM;
d930faee 743 }
acebe8c1
ZL		 744 mwifiex_dbg(adapter, DATA,
745 "info: txbd_ring - base: %p, pbase: %#x:%x, len: %x\n",
746 card->txbd_ring_vbase, (unsigned int)card->txbd_ring_pbase,
747 (u32)((u64)card->txbd_ring_pbase >> 32),
748 card->txbd_ring_size);
d930faee 749
0732484b 750 return mwifiex_init_txq_ring(adapter);
d930faee
AK		 751}
752
753static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter)
754{
755 struct pcie_service_card *card = adapter->card;
dd04e6ac 756 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 757
0732484b 758 mwifiex_cleanup_txq_ring(adapter);
d930faee 759
fc331460
AP		 760 if (card->txbd_ring_vbase)
761 pci_free_consistent(card->dev, card->txbd_ring_size,
762 card->txbd_ring_vbase,
763 card->txbd_ring_pbase);
d930faee
AK		 764 card->txbd_ring_size = 0;
765 card->txbd_wrptr = 0;
dd04e6ac 766 card->txbd_rdptr = 0 | reg->tx_rollover_ind;
d930faee 767 card->txbd_ring_vbase = NULL;
fc331460 768 card->txbd_ring_pbase = 0;
d930faee
AK		 769
770 return 0;
771}
772
773/*
774 * This function creates buffer descriptor ring for RX
775 */
776static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter)
777{
778 struct pcie_service_card *card = adapter->card;
dd04e6ac 779 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 780
781 /*
782 * driver maintaines the read pointer and firmware maintaines the write
783 * pointer. The write pointer starts at 0 (zero) while the read pointer
784 * starts at zero with rollover bit set
785 */
786 card->rxbd_wrptr = 0;
dd04e6ac 787 card->rxbd_rdptr = reg->rx_rollover_ind;
d930faee 788
ca8f2112
AP		 789 if (reg->pfu_enabled)
790 card->rxbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) *
791 MWIFIEX_MAX_TXRX_BD;
792 else
793 card->rxbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) *
794 MWIFIEX_MAX_TXRX_BD;
795
acebe8c1
ZL		 796 mwifiex_dbg(adapter, INFO,
797 "info: rxbd_ring: Allocating %d bytes\n",
798 card->rxbd_ring_size);
fc331460
AP		 799 card->rxbd_ring_vbase = pci_alloc_consistent(card->dev,
800 card->rxbd_ring_size,
801 &card->rxbd_ring_pbase);
d930faee 802 if (!card->rxbd_ring_vbase) {
acebe8c1
ZL		 803 mwifiex_dbg(adapter, ERROR,
804 "allocate consistent memory (%d bytes) failed!\n",
805 card->rxbd_ring_size);
8c53e42d 806 return -ENOMEM;
d930faee 807 }
d930faee 808
acebe8c1
ZL		 809 mwifiex_dbg(adapter, DATA,
810 "info: rxbd_ring - base: %p, pbase: %#x:%x, len: %#x\n",
811 card->rxbd_ring_vbase, (u32)card->rxbd_ring_pbase,
812 (u32)((u64)card->rxbd_ring_pbase >> 32),
813 card->rxbd_ring_size);
d930faee 814
0732484b 815 return mwifiex_init_rxq_ring(adapter);
d930faee
AK		 816}
817
818/*
819 * This function deletes Buffer descriptor ring for RX
820 */
821static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter)
822{
823 struct pcie_service_card *card = adapter->card;
dd04e6ac 824 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 825
0732484b 826 mwifiex_cleanup_rxq_ring(adapter);
d930faee 827
fc331460
AP		 828 if (card->rxbd_ring_vbase)
829 pci_free_consistent(card->dev, card->rxbd_ring_size,
830 card->rxbd_ring_vbase,
831 card->rxbd_ring_pbase);
d930faee
AK		 832 card->rxbd_ring_size = 0;
833 card->rxbd_wrptr = 0;
dd04e6ac 834 card->rxbd_rdptr = 0 | reg->rx_rollover_ind;
d930faee 835 card->rxbd_ring_vbase = NULL;
fc331460 836 card->rxbd_ring_pbase = 0;
d930faee
AK		 837
838 return 0;
839}
840
841/*
842 * This function creates buffer descriptor ring for Events
843 */
844static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter)
845{
846 struct pcie_service_card *card = adapter->card;
dd04e6ac 847 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 848
849 /*
850 * driver maintaines the read pointer and firmware maintaines the write
851 * pointer. The write pointer starts at 0 (zero) while the read pointer
852 * starts at zero with rollover bit set
853 */
854 card->evtbd_wrptr = 0;
dd04e6ac 855 card->evtbd_rdptr = reg->evt_rollover_ind;
d930faee 856
e05dc3e9 857 card->evtbd_ring_size = sizeof(struct mwifiex_evt_buf_desc) *
ca8f2112
AP		 858 MWIFIEX_MAX_EVT_BD;
859
acebe8c1
ZL		 860 mwifiex_dbg(adapter, INFO,
861 "info: evtbd_ring: Allocating %d bytes\n",
f57c1edc 862 card->evtbd_ring_size);
fc331460
AP		 863 card->evtbd_ring_vbase = pci_alloc_consistent(card->dev,
864 card->evtbd_ring_size,
865 &card->evtbd_ring_pbase);
d930faee 866 if (!card->evtbd_ring_vbase) {
acebe8c1
ZL		 867 mwifiex_dbg(adapter, ERROR,
868 "allocate consistent memory (%d bytes) failed!\n",
869 card->evtbd_ring_size);
8c53e42d 870 return -ENOMEM;
d930faee 871 }
d930faee 872
acebe8c1
ZL		 873 mwifiex_dbg(adapter, EVENT,
874 "info: CMDRSP/EVT bd_ring - base: %p pbase: %#x:%x len: %#x\n",
875 card->evtbd_ring_vbase, (u32)card->evtbd_ring_pbase,
876 (u32)((u64)card->evtbd_ring_pbase >> 32),
877 card->evtbd_ring_size);
d930faee 878
0732484b 879 return mwifiex_pcie_init_evt_ring(adapter);
d930faee
AK		 880}
881
882/*
883 * This function deletes Buffer descriptor ring for Events
884 */
885static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter)
886{
887 struct pcie_service_card *card = adapter->card;
dd04e6ac 888 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 889
0732484b 890 mwifiex_cleanup_evt_ring(adapter);
d930faee 891
fc331460
AP		 892 if (card->evtbd_ring_vbase)
893 pci_free_consistent(card->dev, card->evtbd_ring_size,
894 card->evtbd_ring_vbase,
895 card->evtbd_ring_pbase);
d930faee 896 card->evtbd_wrptr = 0;
dd04e6ac 897 card->evtbd_rdptr = 0 | reg->evt_rollover_ind;
d930faee
AK		 898 card->evtbd_ring_size = 0;
899 card->evtbd_ring_vbase = NULL;
fc331460 900 card->evtbd_ring_pbase = 0;
d930faee
AK		 901
902 return 0;
903}
904
905/*
906 * This function allocates a buffer for CMDRSP
907 */
908static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter)
909{
910 struct pcie_service_card *card = adapter->card;
911 struct sk_buff *skb;
912
913 /* Allocate memory for receiving command response data */
914 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE);
915 if (!skb) {
acebe8c1
ZL		 916 mwifiex_dbg(adapter, ERROR,
917 "Unable to allocate skb for command response data.\n");
d930faee
AK		 918 return -ENOMEM;
919 }
d930faee 920 skb_put(skb, MWIFIEX_UPLD_SIZE);
fc331460
AP		 921 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
922 PCI_DMA_FROMDEVICE))
923 return -1;
d930faee 924
fc331460 925 card->cmdrsp_buf = skb;
d930faee
AK		 926
927 return 0;
928}
929
930/*
931 * This function deletes a buffer for CMDRSP
932 */
933static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter)
934{
935 struct pcie_service_card *card;
936
937 if (!adapter)
938 return 0;
939
940 card = adapter->card;
941
fc331460 942 if (card && card->cmdrsp_buf) {
dbccc92b
AD		 943 mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf,
944 PCI_DMA_FROMDEVICE);
d930faee 945 dev_kfree_skb_any(card->cmdrsp_buf);
fc331460 946 }
d930faee 947
fc331460 948 if (card && card->cmd_buf) {
dbccc92b
AD		 949 mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
950 PCI_DMA_TODEVICE);
fc331460 951 }
d930faee
AK		 952 return 0;
953}
954
955/*
956 * This function allocates a buffer for sleep cookie
957 */
958static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter)
959{
d930faee
AK		 960 struct pcie_service_card *card = adapter->card;
961
fc331460
AP		 962 card->sleep_cookie_vbase = pci_alloc_consistent(card->dev, sizeof(u32),
963 &card->sleep_cookie_pbase);
964 if (!card->sleep_cookie_vbase) {
acebe8c1
ZL		 965 mwifiex_dbg(adapter, ERROR,
966 "pci_alloc_consistent failed!\n");
d930faee
AK		 967 return -ENOMEM;
968 }
d930faee 969 /* Init val of Sleep Cookie */
fc331460 970 *(u32 *)card->sleep_cookie_vbase = FW_AWAKE_COOKIE;
d930faee 971
acebe8c1
ZL		 972 mwifiex_dbg(adapter, INFO,
973 "alloc_scook: sleep cookie=0x%x\n",
974 *((u32 *)card->sleep_cookie_vbase));
d930faee
AK		 975
976 return 0;
977}
978
979/*
980 * This function deletes buffer for sleep cookie
981 */
982static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter)
983{
984 struct pcie_service_card *card;
985
986 if (!adapter)
987 return 0;
988
989 card = adapter->card;
990
fc331460
AP		 991 if (card && card->sleep_cookie_vbase) {
992 pci_free_consistent(card->dev, sizeof(u32),
993 card->sleep_cookie_vbase,
994 card->sleep_cookie_pbase);
995 card->sleep_cookie_vbase = NULL;
d930faee
AK		 996 }
997
998 return 0;
999}
1000
fbd7e7ac
AP		 1001/* This function flushes the TX buffer descriptor ring
1002 * This function defined as handler is also called while cleaning TXRX
1003 * during disconnect/ bss stop.
1004 */
1005static int mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter *adapter)
1006{
1007 struct pcie_service_card *card = adapter->card;
fbd7e7ac 1008
48f4d916 1009 if (!mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) {
fbd7e7ac
AP		 1010 card->txbd_flush = 1;
1011 /* write pointer already set at last send
1012 * send dnld-rdy intr again, wait for completion.
1013 */
1014 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1015 CPU_INTR_DNLD_RDY)) {
acebe8c1
ZL		 1016 mwifiex_dbg(adapter, ERROR,
1017 "failed to assert dnld-rdy interrupt.\n");
fbd7e7ac
AP		 1018 return -1;
1019 }
1020 }
1021 return 0;
1022}
1023
d930faee 1024/*
e7f767a7 1025 * This function unmaps and frees downloaded data buffer
d930faee 1026 */
e7f767a7 1027static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter)
d930faee 1028{
e7f767a7 1029 struct sk_buff *skb;
ca8f2112 1030 u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0;
e05dc3e9 1031 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 1032 struct mwifiex_pfu_buf_desc *desc2;
d930faee 1033 struct pcie_service_card *card = adapter->card;
dd04e6ac 1034 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 1035
1036 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1037 mwifiex_pm_wakeup_card(adapter);
1038
1039 /* Read the TX ring read pointer set by firmware */
dd04e6ac 1040 if (mwifiex_read_reg(adapter, reg->tx_rdptr, &rdptr)) {
acebe8c1
ZL		 1041 mwifiex_dbg(adapter, ERROR,
1042 "SEND COMP: failed to read reg->tx_rdptr\n");
d930faee
AK		 1043 return -1;
1044 }
1045
acebe8c1
ZL		 1046 mwifiex_dbg(adapter, DATA,
1047 "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n",
1048 card->txbd_rdptr, rdptr);
d930faee 1049
ca8f2112 1050 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr;
e7f767a7 1051 /* free from previous txbd_rdptr to current txbd_rdptr */
dd04e6ac
AP		 1052 while (((card->txbd_rdptr & reg->tx_mask) !=
1053 (rdptr & reg->tx_mask)) ||
1054 ((card->txbd_rdptr & reg->tx_rollover_ind) !=
1055 (rdptr & reg->tx_rollover_ind))) {
ca8f2112
AP		 1056 wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >>
1057 reg->tx_start_ptr;
e7f767a7
AP		 1058
1059 skb = card->tx_buf_list[wrdoneidx];
dbccc92b 1060
e7f767a7 1061 if (skb) {
acebe8c1
ZL		 1062 mwifiex_dbg(adapter, DATA,
1063 "SEND COMP: Detach skb %p at txbd_rdidx=%d\n",
1064 skb, wrdoneidx);
dbccc92b
AD		 1065 mwifiex_unmap_pci_memory(adapter, skb,
1066 PCI_DMA_TODEVICE);
e7f767a7
AP		 1067
1068 unmap_count++;
1069
1070 if (card->txbd_flush)
1071 mwifiex_write_data_complete(adapter, skb, 0,
1072 -1);
1073 else
1074 mwifiex_write_data_complete(adapter, skb, 0, 0);
1075 }
1076
1077 card->tx_buf_list[wrdoneidx] = NULL;
ca8f2112
AP		 1078
1079 if (reg->pfu_enabled) {
45d18c56 1080 desc2 = card->txbd_ring[wrdoneidx];
ca8f2112
AP		 1081 memset(desc2, 0, sizeof(*desc2));
1082 } else {
1083 desc = card->txbd_ring[wrdoneidx];
1084 memset(desc, 0, sizeof(*desc));
1085 }
1086 switch (card->dev->device) {
1087 case PCIE_DEVICE_ID_MARVELL_88W8766P:
1088 card->txbd_rdptr++;
1089 break;
1090 case PCIE_DEVICE_ID_MARVELL_88W8897:
6d85ef00 1091 case PCIE_DEVICE_ID_MARVELL_88W8997:
ca8f2112
AP		 1092 card->txbd_rdptr += reg->ring_tx_start_ptr;
1093 break;
1094 }
1095
e7f767a7 1096
dd04e6ac 1097 if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs)
e7f767a7 1098 card->txbd_rdptr = ((card->txbd_rdptr &
dd04e6ac
AP		 1099 reg->tx_rollover_ind) ^
1100 reg->tx_rollover_ind);
e7f767a7
AP		 1101 }
1102
1103 if (unmap_count)
1104 adapter->data_sent = false;
1105
1106 if (card->txbd_flush) {
3d482038 1107 if (mwifiex_pcie_txbd_empty(card, card->txbd_rdptr))
e7f767a7
AP		 1108 card->txbd_flush = 0;
1109 else
1110 mwifiex_clean_pcie_ring_buf(adapter);
1111 }
1112
1113 return 0;
1114}
1115
1116/* This function sends data buffer to device. First 4 bytes of payload
1117 * are filled with payload length and payload type. Then this payload
1118 * is mapped to PCI device memory. Tx ring pointers are advanced accordingly.
1119 * Download ready interrupt to FW is deffered if Tx ring is not full and
1120 * additional payload can be accomodated.
8d767dcb 1121 * Caller must ensure tx_param parameter to this function is not NULL.
e7f767a7
AP		 1122 */
1123static int
1124mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb,
1125 struct mwifiex_tx_param *tx_param)
1126{
1127 struct pcie_service_card *card = adapter->card;
dd04e6ac 1128 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
ca8f2112 1129 u32 wrindx, num_tx_buffs, rx_val;
e7f767a7
AP		 1130 int ret;
1131 dma_addr_t buf_pa;
9931078e
BZ		 1132 struct mwifiex_pcie_buf_desc *desc = NULL;
1133 struct mwifiex_pfu_buf_desc *desc2 = NULL;
e7f767a7
AP		 1134 __le16 *tmp;
1135
1136 if (!(skb->data && skb->len)) {
acebe8c1
ZL		 1137 mwifiex_dbg(adapter, ERROR,
1138 "%s(): invalid parameter <%p, %#x>\n",
1139 __func__, skb->data, skb->len);
e7f767a7
AP		 1140 return -1;
1141 }
1142
1143 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1144 mwifiex_pm_wakeup_card(adapter);
1145
ca8f2112 1146 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr;
acebe8c1
ZL		 1147 mwifiex_dbg(adapter, DATA,
1148 "info: SEND DATA: <Rd: %#x, Wr: %#x>\n",
e7f767a7
AP		 1149 card->txbd_rdptr, card->txbd_wrptr);
1150 if (mwifiex_pcie_txbd_not_full(card)) {
d930faee
AK		 1151 u8 *payload;
1152
1153 adapter->data_sent = true;
e7f767a7 1154 payload = skb->data;
d930faee
AK		 1155 tmp = (__le16 *)&payload[0];
1156 *tmp = cpu_to_le16((u16)skb->len);
1157 tmp = (__le16 *)&payload[2];
1158 *tmp = cpu_to_le16(MWIFIEX_TYPE_DATA);
e7f767a7 1159
dbccc92b 1160 if (mwifiex_map_pci_memory(adapter, skb, skb->len,
e7f767a7
AP		 1161 PCI_DMA_TODEVICE))
1162 return -1;
1163
ca8f2112 1164 wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr;
dbccc92b 1165 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
e7f767a7 1166 card->tx_buf_list[wrindx] = skb;
d930faee 1167
ca8f2112 1168 if (reg->pfu_enabled) {
45d18c56 1169 desc2 = card->txbd_ring[wrindx];
ca8f2112
AP		 1170 desc2->paddr = buf_pa;
1171 desc2->len = (u16)skb->len;
1172 desc2->frag_len = (u16)skb->len;
1173 desc2->offset = 0;
1174 desc2->flags = MWIFIEX_BD_FLAG_FIRST_DESC |
1175 MWIFIEX_BD_FLAG_LAST_DESC;
1176 } else {
1177 desc = card->txbd_ring[wrindx];
1178 desc->paddr = buf_pa;
1179 desc->len = (u16)skb->len;
1180 desc->flags = MWIFIEX_BD_FLAG_FIRST_DESC |
1181 MWIFIEX_BD_FLAG_LAST_DESC;
1182 }
1183
1184 switch (card->dev->device) {
1185 case PCIE_DEVICE_ID_MARVELL_88W8766P:
1186 card->txbd_wrptr++;
1187 break;
1188 case PCIE_DEVICE_ID_MARVELL_88W8897:
6d85ef00 1189 case PCIE_DEVICE_ID_MARVELL_88W8997:
ca8f2112
AP		 1190 card->txbd_wrptr += reg->ring_tx_start_ptr;
1191 break;
1192 }
1193
1194 if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs)
d930faee 1195 card->txbd_wrptr = ((card->txbd_wrptr &
dd04e6ac
AP		 1196 reg->tx_rollover_ind) ^
1197 reg->tx_rollover_ind);
d930faee 1198
ca8f2112 1199 rx_val = card->rxbd_rdptr & reg->rx_wrap_mask;
dd04e6ac
AP		 1200 /* Write the TX ring write pointer in to reg->tx_wrptr */
1201 if (mwifiex_write_reg(adapter, reg->tx_wrptr,
ca8f2112 1202 card->txbd_wrptr | rx_val)) {
acebe8c1
ZL		 1203 mwifiex_dbg(adapter, ERROR,
1204 "SEND DATA: failed to write reg->tx_wrptr\n");
e7f767a7
AP		 1205 ret = -1;
1206 goto done_unmap;
d930faee 1207 }
e7f767a7
AP		 1208 if ((mwifiex_pcie_txbd_not_full(card)) &&
1209 tx_param->next_pkt_len) {
1210 /* have more packets and TxBD still can hold more */
acebe8c1
ZL		 1211 mwifiex_dbg(adapter, DATA,
1212 "SEND DATA: delay dnld-rdy interrupt.\n");
e7f767a7
AP		 1213 adapter->data_sent = false;
1214 } else {
1215 /* Send the TX ready interrupt */
1216 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1217 CPU_INTR_DNLD_RDY)) {
acebe8c1
ZL		 1218 mwifiex_dbg(adapter, ERROR,
1219 "SEND DATA: failed to assert dnld-rdy interrupt.\n");
e7f767a7
AP		 1220 ret = -1;
1221 goto done_unmap;
1222 }
d930faee 1223 }
acebe8c1
ZL		 1224 mwifiex_dbg(adapter, DATA,
1225 "info: SEND DATA: Updated <Rd: %#x, Wr:\t"
1226 "%#x> and sent packet to firmware successfully\n",
1227 card->txbd_rdptr, card->txbd_wrptr);
d930faee 1228 } else {
acebe8c1
ZL		 1229 mwifiex_dbg(adapter, DATA,
1230 "info: TX Ring full, can't send packets to fw\n");
d930faee
AK		 1231 adapter->data_sent = true;
1232 /* Send the TX ready interrupt */
1233 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1234 CPU_INTR_DNLD_RDY))
acebe8c1
ZL		 1235 mwifiex_dbg(adapter, ERROR,
1236 "SEND DATA: failed to assert door-bell intr\n");
d930faee
AK		 1237 return -EBUSY;
1238 }
1239
e7f767a7
AP		 1240 return -EINPROGRESS;
1241done_unmap:
dbccc92b 1242 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
e7f767a7 1243 card->tx_buf_list[wrindx] = NULL;
ca8f2112
AP		 1244 if (reg->pfu_enabled)
1245 memset(desc2, 0, sizeof(*desc2));
1246 else
1247 memset(desc, 0, sizeof(*desc));
1248
e7f767a7 1249 return ret;
d930faee
AK		 1250}
1251
1252/*
1253 * This function handles received buffer ring and
1254 * dispatches packets to upper
1255 */
1256static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter)
1257{
1258 struct pcie_service_card *card = adapter->card;
dd04e6ac 1259 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
ca8f2112 1260 u32 wrptr, rd_index, tx_val;
e7f767a7 1261 dma_addr_t buf_pa;
d930faee
AK		 1262 int ret = 0;
1263 struct sk_buff *skb_tmp = NULL;
e05dc3e9 1264 struct mwifiex_pcie_buf_desc *desc;
ca8f2112 1265 struct mwifiex_pfu_buf_desc *desc2;
d930faee 1266
e7f767a7
AP		 1267 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1268 mwifiex_pm_wakeup_card(adapter);
1269
d930faee 1270 /* Read the RX ring Write pointer set by firmware */
dd04e6ac 1271 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) {
acebe8c1
ZL		 1272 mwifiex_dbg(adapter, ERROR,
1273 "RECV DATA: failed to read reg->rx_wrptr\n");
d930faee
AK		 1274 ret = -1;
1275 goto done;
1276 }
e7f767a7 1277 card->rxbd_wrptr = wrptr;
d930faee 1278
dd04e6ac
AP		 1279 while (((wrptr & reg->rx_mask) !=
1280 (card->rxbd_rdptr & reg->rx_mask)) ||
1281 ((wrptr & reg->rx_rollover_ind) ==
1282 (card->rxbd_rdptr & reg->rx_rollover_ind))) {
d930faee
AK		 1283 struct sk_buff *skb_data;
1284 u16 rx_len;
e7f767a7 1285 __le16 pkt_len;
d930faee 1286
dd04e6ac 1287 rd_index = card->rxbd_rdptr & reg->rx_mask;
d930faee
AK		 1288 skb_data = card->rx_buf_list[rd_index];
1289
bb8e6a1e
AK		 1290 /* If skb allocation was failed earlier for Rx packet,
1291 * rx_buf_list[rd_index] would have been left with a NULL.
1292 */
1293 if (!skb_data)
1294 return -ENOMEM;
1295
dbccc92b 1296 mwifiex_unmap_pci_memory(adapter, skb_data, PCI_DMA_FROMDEVICE);
e7f767a7
AP		 1297 card->rx_buf_list[rd_index] = NULL;
1298
d930faee 1299 /* Get data length from interface header -
e7f767a7
AP		 1300 * first 2 bytes for len, next 2 bytes is for type
1301 */
1302 pkt_len = *((__le16 *)skb_data->data);
1303 rx_len = le16_to_cpu(pkt_len);
42a028aa
AP		 1304 if (WARN_ON(rx_len <= INTF_HEADER_LEN ||
1305 rx_len > MWIFIEX_RX_DATA_BUF_SIZE)) {
acebe8c1
ZL		 1306 mwifiex_dbg(adapter, ERROR,
1307 "Invalid RX len %d, Rd=%#x, Wr=%#x\n",
1308 rx_len, card->rxbd_rdptr, wrptr);
42a028aa
AP		 1309 dev_kfree_skb_any(skb_data);
1310 } else {
1311 skb_put(skb_data, rx_len);
acebe8c1
ZL		 1312 mwifiex_dbg(adapter, DATA,
1313 "info: RECV DATA: Rd=%#x, Wr=%#x, Len=%d\n",
1314 card->rxbd_rdptr, wrptr, rx_len);
42a028aa 1315 skb_pull(skb_data, INTF_HEADER_LEN);
6e251174 1316 if (adapter->rx_work_enabled) {
6e251174 1317 skb_queue_tail(&adapter->rx_data_q, skb_data);
6e251174
AP		 1318 adapter->data_received = true;
1319 atomic_inc(&adapter->rx_pending);
1320 } else {
1321 mwifiex_handle_rx_packet(adapter, skb_data);
1322 }
42a028aa 1323 }
e7f767a7 1324
62159944 1325 skb_tmp = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE,
5c87a55a 1326 GFP_KERNEL);
d930faee 1327 if (!skb_tmp) {
acebe8c1
ZL		 1328 mwifiex_dbg(adapter, ERROR,
1329 "Unable to allocate skb.\n");
e7f767a7 1330 return -ENOMEM;
d930faee
AK		 1331 }
1332
e7f767a7
AP		 1333 if (mwifiex_map_pci_memory(adapter, skb_tmp,
1334 MWIFIEX_RX_DATA_BUF_SIZE,
1335 PCI_DMA_FROMDEVICE))
1336 return -1;
1337
dbccc92b 1338 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp);
e7f767a7 1339
acebe8c1
ZL		 1340 mwifiex_dbg(adapter, INFO,
1341 "RECV DATA: Attach new sk_buff %p at rxbd_rdidx=%d\n",
1342 skb_tmp, rd_index);
e7f767a7 1343 card->rx_buf_list[rd_index] = skb_tmp;
ca8f2112
AP		 1344
1345 if (reg->pfu_enabled) {
45d18c56 1346 desc2 = card->rxbd_ring[rd_index];
ca8f2112
AP		 1347 desc2->paddr = buf_pa;
1348 desc2->len = skb_tmp->len;
1349 desc2->frag_len = skb_tmp->len;
1350 desc2->offset = 0;
1351 desc2->flags = reg->ring_flag_sop | reg->ring_flag_eop;
1352 } else {
1353 desc = card->rxbd_ring[rd_index];
1354 desc->paddr = buf_pa;
1355 desc->len = skb_tmp->len;
1356 desc->flags = 0;
1357 }
d930faee 1358
dd04e6ac 1359 if ((++card->rxbd_rdptr & reg->rx_mask) ==
d930faee
AK		 1360 MWIFIEX_MAX_TXRX_BD) {
1361 card->rxbd_rdptr = ((card->rxbd_rdptr &
dd04e6ac
AP		 1362 reg->rx_rollover_ind) ^
1363 reg->rx_rollover_ind);
d930faee 1364 }
acebe8c1
ZL		 1365 mwifiex_dbg(adapter, DATA,
1366 "info: RECV DATA: <Rd: %#x, Wr: %#x>\n",
1367 card->rxbd_rdptr, wrptr);
d930faee 1368
ca8f2112 1369 tx_val = card->txbd_wrptr & reg->tx_wrap_mask;
dd04e6ac
AP		 1370 /* Write the RX ring read pointer in to reg->rx_rdptr */
1371 if (mwifiex_write_reg(adapter, reg->rx_rdptr,
ca8f2112 1372 card->rxbd_rdptr | tx_val)) {
acebe8c1
ZL		 1373 mwifiex_dbg(adapter, DATA,
1374 "RECV DATA: failed to write reg->rx_rdptr\n");
d930faee
AK		 1375 ret = -1;
1376 goto done;
1377 }
1378
1379 /* Read the RX ring Write pointer set by firmware */
dd04e6ac 1380 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) {
acebe8c1
ZL		 1381 mwifiex_dbg(adapter, ERROR,
1382 "RECV DATA: failed to read reg->rx_wrptr\n");
d930faee
AK		 1383 ret = -1;
1384 goto done;
1385 }
acebe8c1
ZL		 1386 mwifiex_dbg(adapter, DATA,
1387 "info: RECV DATA: Rcvd packet from fw successfully\n");
e7f767a7 1388 card->rxbd_wrptr = wrptr;
d930faee
AK		 1389 }
1390
1391done:
d930faee
AK		 1392 return ret;
1393}
1394
1395/*
1396 * This function downloads the boot command to device
1397 */
1398static int
1399mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb)
1400{
fc331460
AP		 1401 dma_addr_t buf_pa;
1402 struct pcie_service_card *card = adapter->card;
dd04e6ac 1403 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 1404
fc331460 1405 if (!(skb->data && skb->len)) {
acebe8c1
ZL		 1406 mwifiex_dbg(adapter, ERROR,
1407 "Invalid parameter in %s <%p. len %d>\n",
1408 __func__, skb->data, skb->len);
d930faee
AK		 1409 return -1;
1410 }
1411
3a968d76 1412 if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE))
fc331460
AP		 1413 return -1;
1414
dbccc92b 1415 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
fc331460 1416
dd04e6ac
AP		 1417 /* Write the lower 32bits of the physical address to low command
1418 * address scratch register
1419 */
1420 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)buf_pa)) {
acebe8c1
ZL		 1421 mwifiex_dbg(adapter, ERROR,
1422 "%s: failed to write download command to boot code.\n",
1423 __func__);
dbccc92b 1424 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
d930faee
AK		 1425 return -1;
1426 }
1427
dd04e6ac
AP		 1428 /* Write the upper 32bits of the physical address to high command
1429 * address scratch register
1430 */
1431 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi,
fc331460 1432 (u32)((u64)buf_pa >> 32))) {
acebe8c1
ZL		 1433 mwifiex_dbg(adapter, ERROR,
1434 "%s: failed to write download command to boot code.\n",
1435 __func__);
dbccc92b 1436 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
d930faee
AK		 1437 return -1;
1438 }
1439
dd04e6ac
AP		 1440 /* Write the command length to cmd_size scratch register */
1441 if (mwifiex_write_reg(adapter, reg->cmd_size, skb->len)) {
acebe8c1
ZL		 1442 mwifiex_dbg(adapter, ERROR,
1443 "%s: failed to write command len to cmd_size scratch reg\n",
1444 __func__);
dbccc92b 1445 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
d930faee
AK		 1446 return -1;
1447 }
1448
1449 /* Ring the door bell */
1450 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1451 CPU_INTR_DOOR_BELL)) {
acebe8c1
ZL		 1452 mwifiex_dbg(adapter, ERROR,
1453 "%s: failed to assert door-bell intr\n", __func__);
dbccc92b 1454 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
d930faee
AK		 1455 return -1;
1456 }
1457
1458 return 0;
1459}
1460
c6d1d87a
AP		 1461/* This function init rx port in firmware which in turn enables to receive data
1462 * from device before transmitting any packet.
1463 */
1464static int mwifiex_pcie_init_fw_port(struct mwifiex_adapter *adapter)
1465{
1466 struct pcie_service_card *card = adapter->card;
dd04e6ac 1467 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
ca8f2112 1468 int tx_wrap = card->txbd_wrptr & reg->tx_wrap_mask;
c6d1d87a 1469
dd04e6ac 1470 /* Write the RX ring read pointer in to reg->rx_rdptr */
ca8f2112
AP		 1471 if (mwifiex_write_reg(adapter, reg->rx_rdptr, card->rxbd_rdptr |
1472 tx_wrap)) {
acebe8c1
ZL		 1473 mwifiex_dbg(adapter, ERROR,
1474 "RECV DATA: failed to write reg->rx_rdptr\n");
c6d1d87a
AP		 1475 return -1;
1476 }
1477 return 0;
1478}
1479
1480/* This function downloads commands to the device
d930faee
AK		 1481 */
1482static int
1483mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb)
1484{
1485 struct pcie_service_card *card = adapter->card;
dd04e6ac 1486 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 1487 int ret = 0;
fc331460
AP		 1488 dma_addr_t cmd_buf_pa, cmdrsp_buf_pa;
1489 u8 *payload = (u8 *)skb->data;
d930faee
AK		 1490
1491 if (!(skb->data && skb->len)) {
acebe8c1
ZL		 1492 mwifiex_dbg(adapter, ERROR,
1493 "Invalid parameter in %s <%p, %#x>\n",
1494 __func__, skb->data, skb->len);
d930faee
AK		 1495 return -1;
1496 }
1497
1498 /* Make sure a command response buffer is available */
1499 if (!card->cmdrsp_buf) {
acebe8c1
ZL		 1500 mwifiex_dbg(adapter, ERROR,
1501 "No response buffer available, send command failed\n");
d930faee
AK		 1502 return -EBUSY;
1503 }
1504
fc331460
AP		 1505 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1506 mwifiex_pm_wakeup_card(adapter);
d930faee
AK		 1507
1508 adapter->cmd_sent = true;
fc331460
AP		 1509
1510 *(__le16 *)&payload[0] = cpu_to_le16((u16)skb->len);
1511 *(__le16 *)&payload[2] = cpu_to_le16(MWIFIEX_TYPE_CMD);
1512
1513 if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE))
1514 return -1;
1515
1516 card->cmd_buf = skb;
d930faee
AK		 1517
1518 /* To send a command, the driver will:
1519 1. Write the 64bit physical address of the data buffer to
dd04e6ac 1520 cmd response address low + cmd response address high
d930faee
AK		 1521 2. Ring the door bell (i.e. set the door bell interrupt)
1522
1523 In response to door bell interrupt, the firmware will perform
1524 the DMA of the command packet (first header to obtain the total
1525 length and then rest of the command).
1526 */
1527
1528 if (card->cmdrsp_buf) {
dbccc92b 1529 cmdrsp_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmdrsp_buf);
d930faee
AK		 1530 /* Write the lower 32bits of the cmdrsp buffer physical
1531 address */
dd04e6ac 1532 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo,
fc331460 1533 (u32)cmdrsp_buf_pa)) {
acebe8c1
ZL		 1534 mwifiex_dbg(adapter, ERROR,
1535 "Failed to write download cmd to boot code.\n");
d930faee
AK		 1536 ret = -1;
1537 goto done;
1538 }
1539 /* Write the upper 32bits of the cmdrsp buffer physical
1540 address */
dd04e6ac 1541 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi,
fc331460 1542 (u32)((u64)cmdrsp_buf_pa >> 32))) {
acebe8c1
ZL		 1543 mwifiex_dbg(adapter, ERROR,
1544 "Failed to write download cmd to boot code.\n");
d930faee
AK		 1545 ret = -1;
1546 goto done;
1547 }
1548 }
1549
dbccc92b 1550 cmd_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmd_buf);
dd04e6ac
AP		 1551 /* Write the lower 32bits of the physical address to reg->cmd_addr_lo */
1552 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo,
1553 (u32)cmd_buf_pa)) {
acebe8c1
ZL		 1554 mwifiex_dbg(adapter, ERROR,
1555 "Failed to write download cmd to boot code.\n");
d930faee
AK		 1556 ret = -1;
1557 goto done;
1558 }
dd04e6ac
AP		 1559 /* Write the upper 32bits of the physical address to reg->cmd_addr_hi */
1560 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi,
fc331460 1561 (u32)((u64)cmd_buf_pa >> 32))) {
acebe8c1
ZL		 1562 mwifiex_dbg(adapter, ERROR,
1563 "Failed to write download cmd to boot code.\n");
d930faee
AK		 1564 ret = -1;
1565 goto done;
1566 }
1567
dd04e6ac
AP		 1568 /* Write the command length to reg->cmd_size */
1569 if (mwifiex_write_reg(adapter, reg->cmd_size,
1570 card->cmd_buf->len)) {
acebe8c1
ZL		 1571 mwifiex_dbg(adapter, ERROR,
1572 "Failed to write cmd len to reg->cmd_size\n");
d930faee
AK		 1573 ret = -1;
1574 goto done;
1575 }
1576
1577 /* Ring the door bell */
1578 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1579 CPU_INTR_DOOR_BELL)) {
acebe8c1
ZL		 1580 mwifiex_dbg(adapter, ERROR,
1581 "Failed to assert door-bell intr\n");
d930faee
AK		 1582 ret = -1;
1583 goto done;
1584 }
1585
1586done:
1587 if (ret)
1588 adapter->cmd_sent = false;
1589
1590 return 0;
1591}
1592
1593/*
1594 * This function handles command complete interrupt
1595 */
1596static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter)
1597{
1598 struct pcie_service_card *card = adapter->card;
dd04e6ac 1599 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
f57c1edc 1600 struct sk_buff *skb = card->cmdrsp_buf;
d930faee 1601 int count = 0;
fc331460
AP		 1602 u16 rx_len;
1603 __le16 pkt_len;
d930faee 1604
acebe8c1
ZL		 1605 mwifiex_dbg(adapter, CMD,
1606 "info: Rx CMD Response\n");
d930faee 1607
dbccc92b 1608 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_FROMDEVICE);
fc331460 1609
189b3299
AD		 1610 /* Unmap the command as a response has been received. */
1611 if (card->cmd_buf) {
1612 mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
1613 PCI_DMA_TODEVICE);
1614 card->cmd_buf = NULL;
1615 }
1616
fc331460
AP		 1617 pkt_len = *((__le16 *)skb->data);
1618 rx_len = le16_to_cpu(pkt_len);
1619 skb_trim(skb, rx_len);
1620 skb_pull(skb, INTF_HEADER_LEN);
1621
d930faee 1622 if (!adapter->curr_cmd) {
d930faee 1623 if (adapter->ps_state == PS_STATE_SLEEP_CFM) {
f57c1edc
YAP		 1624 mwifiex_process_sleep_confirm_resp(adapter, skb->data,
1625 skb->len);
1c97560f
AK		 1626 mwifiex_pcie_enable_host_int(adapter);
1627 if (mwifiex_write_reg(adapter,
1628 PCIE_CPU_INT_EVENT,
1629 CPU_INTR_SLEEP_CFM_DONE)) {
acebe8c1
ZL		 1630 mwifiex_dbg(adapter, ERROR,
1631 "Write register failed\n");
1c97560f
AK		 1632 return -1;
1633 }
c4bc980f
AP		 1634 mwifiex_delay_for_sleep_cookie(adapter,
1635 MWIFIEX_MAX_DELAY_COUNT);
52301a81
AP		 1636 while (reg->sleep_cookie && (count++ < 10) &&
1637 mwifiex_pcie_ok_to_access_hw(adapter))
e7891ba2 1638 usleep_range(50, 60);
d930faee 1639 } else {
acebe8c1
ZL		 1640 mwifiex_dbg(adapter, ERROR,
1641 "There is no command but got cmdrsp\n");
d930faee 1642 }
f57c1edc
YAP		 1643 memcpy(adapter->upld_buf, skb->data,
1644 min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len));
0f49d64c 1645 skb_push(skb, INTF_HEADER_LEN);
fc331460
AP		 1646 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1647 PCI_DMA_FROMDEVICE))
1648 return -1;
d930faee 1649 } else if (mwifiex_pcie_ok_to_access_hw(adapter)) {
f57c1edc 1650 adapter->curr_cmd->resp_skb = skb;
d930faee
AK		 1651 adapter->cmd_resp_received = true;
1652 /* Take the pointer and set it to CMD node and will
1653 return in the response complete callback */
1654 card->cmdrsp_buf = NULL;
1655
1656 /* Clear the cmd-rsp buffer address in scratch registers. This
1657 will prevent firmware from writing to the same response
1658 buffer again. */
dd04e6ac 1659 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0)) {
acebe8c1
ZL		 1660 mwifiex_dbg(adapter, ERROR,
1661 "cmd_done: failed to clear cmd_rsp_addr_lo\n");
d930faee
AK		 1662 return -1;
1663 }
1664 /* Write the upper 32bits of the cmdrsp buffer physical
1665 address */
dd04e6ac 1666 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0)) {
acebe8c1
ZL		 1667 mwifiex_dbg(adapter, ERROR,
1668 "cmd_done: failed to clear cmd_rsp_addr_hi\n");
d930faee
AK		 1669 return -1;
1670 }
1671 }
1672
1673 return 0;
1674}
1675
1676/*
1677 * Command Response processing complete handler
1678 */
1679static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter,
1680 struct sk_buff *skb)
1681{
1682 struct pcie_service_card *card = adapter->card;
1683
1684 if (skb) {
1685 card->cmdrsp_buf = skb;
1686 skb_push(card->cmdrsp_buf, INTF_HEADER_LEN);
fc331460
AP		 1687 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1688 PCI_DMA_FROMDEVICE))
1689 return -1;
1690 }
1691
d930faee
AK		 1692 return 0;
1693}
1694
1695/*
1696 * This function handles firmware event ready interrupt
1697 */
1698static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter)
1699{
1700 struct pcie_service_card *card = adapter->card;
dd04e6ac 1701 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 1702 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK;
1703 u32 wrptr, event;
e05dc3e9 1704 struct mwifiex_evt_buf_desc *desc;
fc331460
AP		 1705
1706 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1707 mwifiex_pm_wakeup_card(adapter);
d930faee
AK		 1708
1709 if (adapter->event_received) {
acebe8c1
ZL		 1710 mwifiex_dbg(adapter, EVENT,
1711 "info: Event being processed,\t"
1712 "do not process this interrupt just yet\n");
d930faee
AK		 1713 return 0;
1714 }
1715
1716 if (rdptr >= MWIFIEX_MAX_EVT_BD) {
acebe8c1
ZL		 1717 mwifiex_dbg(adapter, ERROR,
1718 "info: Invalid read pointer...\n");
d930faee
AK		 1719 return -1;
1720 }
1721
1722 /* Read the event ring write pointer set by firmware */
dd04e6ac 1723 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) {
acebe8c1
ZL		 1724 mwifiex_dbg(adapter, ERROR,
1725 "EventReady: failed to read reg->evt_wrptr\n");
d930faee
AK		 1726 return -1;
1727 }
1728
acebe8c1
ZL		 1729 mwifiex_dbg(adapter, EVENT,
1730 "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>",
1731 card->evtbd_rdptr, wrptr);
f57c1edc
YAP		 1732 if (((wrptr & MWIFIEX_EVTBD_MASK) != (card->evtbd_rdptr
1733 & MWIFIEX_EVTBD_MASK)) ||
dd04e6ac
AP		 1734 ((wrptr & reg->evt_rollover_ind) ==
1735 (card->evtbd_rdptr & reg->evt_rollover_ind))) {
d930faee
AK		 1736 struct sk_buff *skb_cmd;
1737 __le16 data_len = 0;
1738 u16 evt_len;
1739
acebe8c1
ZL		 1740 mwifiex_dbg(adapter, INFO,
1741 "info: Read Index: %d\n", rdptr);
d930faee 1742 skb_cmd = card->evt_buf_list[rdptr];
dbccc92b 1743 mwifiex_unmap_pci_memory(adapter, skb_cmd, PCI_DMA_FROMDEVICE);
fc331460 1744
d930faee
AK		 1745 /* Take the pointer and set it to event pointer in adapter
1746 and will return back after event handling callback */
1747 card->evt_buf_list[rdptr] = NULL;
e05dc3e9
AP		 1748 desc = card->evtbd_ring[rdptr];
1749 memset(desc, 0, sizeof(*desc));
d930faee
AK		 1750
1751 event = *(u32 *) &skb_cmd->data[INTF_HEADER_LEN];
1752 adapter->event_cause = event;
1753 /* The first 4bytes will be the event transfer header
1754 len is 2 bytes followed by type which is 2 bytes */
1755 memcpy(&data_len, skb_cmd->data, sizeof(__le16));
1756 evt_len = le16_to_cpu(data_len);
868093a9 1757 skb_trim(skb_cmd, evt_len);
d930faee 1758 skb_pull(skb_cmd, INTF_HEADER_LEN);
acebe8c1
ZL		 1759 mwifiex_dbg(adapter, EVENT,
1760 "info: Event length: %d\n", evt_len);
d930faee
AK		 1761
1762 if ((evt_len > 0) && (evt_len < MAX_EVENT_SIZE))
1763 memcpy(adapter->event_body, skb_cmd->data +
1764 MWIFIEX_EVENT_HEADER_LEN, evt_len -
1765 MWIFIEX_EVENT_HEADER_LEN);
1766
1767 adapter->event_received = true;
1768 adapter->event_skb = skb_cmd;
1769
1770 /* Do not update the event read pointer here, wait till the
1771 buffer is released. This is just to make things simpler,
1772 we need to find a better method of managing these buffers.
1773 */
2703a668
AP		 1774 } else {
1775 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1776 CPU_INTR_EVENT_DONE)) {
acebe8c1
ZL		 1777 mwifiex_dbg(adapter, ERROR,
1778 "Write register failed\n");
2703a668
AP		 1779 return -1;
1780 }
d930faee
AK		 1781 }
1782
1783 return 0;
1784}
1785
1786/*
1787 * Event processing complete handler
1788 */
1789static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter,
1790 struct sk_buff *skb)
1791{
1792 struct pcie_service_card *card = adapter->card;
dd04e6ac 1793 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 1794 int ret = 0;
1795 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK;
1796 u32 wrptr;
e05dc3e9 1797 struct mwifiex_evt_buf_desc *desc;
d930faee
AK		 1798
1799 if (!skb)
1800 return 0;
1801
1eb54c8a 1802 if (rdptr >= MWIFIEX_MAX_EVT_BD) {
acebe8c1
ZL		 1803 mwifiex_dbg(adapter, ERROR,
1804 "event_complete: Invalid rdptr 0x%x\n",
1805 rdptr);
8c53e42d 1806 return -EINVAL;
1eb54c8a 1807 }
d930faee
AK		 1808
1809 /* Read the event ring write pointer set by firmware */
dd04e6ac 1810 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) {
acebe8c1
ZL		 1811 mwifiex_dbg(adapter, ERROR,
1812 "event_complete: failed to read reg->evt_wrptr\n");
8c53e42d 1813 return -1;
d930faee
AK		 1814 }
1815
1816 if (!card->evt_buf_list[rdptr]) {
1817 skb_push(skb, INTF_HEADER_LEN);
2728cecd 1818 skb_put(skb, MAX_EVENT_SIZE - skb->len);
fc331460
AP		 1819 if (mwifiex_map_pci_memory(adapter, skb,
1820 MAX_EVENT_SIZE,
1821 PCI_DMA_FROMDEVICE))
1822 return -1;
d930faee 1823 card->evt_buf_list[rdptr] = skb;
e05dc3e9 1824 desc = card->evtbd_ring[rdptr];
dbccc92b 1825 desc->paddr = MWIFIEX_SKB_DMA_ADDR(skb);
e05dc3e9
AP		 1826 desc->len = (u16)skb->len;
1827 desc->flags = 0;
d930faee
AK		 1828 skb = NULL;
1829 } else {
acebe8c1
ZL		 1830 mwifiex_dbg(adapter, ERROR,
1831 "info: ERROR: buf still valid at index %d, <%p, %p>\n",
1832 rdptr, card->evt_buf_list[rdptr], skb);
d930faee
AK		 1833 }
1834
1835 if ((++card->evtbd_rdptr & MWIFIEX_EVTBD_MASK) == MWIFIEX_MAX_EVT_BD) {
1836 card->evtbd_rdptr = ((card->evtbd_rdptr &
dd04e6ac
AP		 1837 reg->evt_rollover_ind) ^
1838 reg->evt_rollover_ind);
d930faee
AK		 1839 }
1840
acebe8c1
ZL		 1841 mwifiex_dbg(adapter, EVENT,
1842 "info: Updated <Rd: 0x%x, Wr: 0x%x>",
1843 card->evtbd_rdptr, wrptr);
d930faee 1844
dd04e6ac
AP		 1845 /* Write the event ring read pointer in to reg->evt_rdptr */
1846 if (mwifiex_write_reg(adapter, reg->evt_rdptr,
1847 card->evtbd_rdptr)) {
acebe8c1
ZL		 1848 mwifiex_dbg(adapter, ERROR,
1849 "event_complete: failed to read reg->evt_rdptr\n");
8c53e42d 1850 return -1;
d930faee
AK		 1851 }
1852
acebe8c1
ZL		 1853 mwifiex_dbg(adapter, EVENT,
1854 "info: Check Events Again\n");
d930faee
AK		 1855 ret = mwifiex_pcie_process_event_ready(adapter);
1856
1857 return ret;
1858}
1859
1860/*
1861 * This function downloads the firmware to the card.
1862 *
1863 * Firmware is downloaded to the card in blocks. Every block download
1864 * is tested for CRC errors, and retried a number of times before
1865 * returning failure.
1866 */
1867static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter,
1868 struct mwifiex_fw_image *fw)
1869{
1870 int ret;
1871 u8 *firmware = fw->fw_buf;
1872 u32 firmware_len = fw->fw_len;
1873 u32 offset = 0;
1874 struct sk_buff *skb;
1875 u32 txlen, tx_blocks = 0, tries, len;
1876 u32 block_retry_cnt = 0;
fc331460 1877 struct pcie_service_card *card = adapter->card;
dd04e6ac 1878 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 1879
1880 if (!firmware || !firmware_len) {
acebe8c1
ZL		 1881 mwifiex_dbg(adapter, ERROR,
1882 "No firmware image found! Terminating download\n");
d930faee
AK		 1883 return -1;
1884 }
1885
acebe8c1
ZL		 1886 mwifiex_dbg(adapter, INFO,
1887 "info: Downloading FW image (%d bytes)\n",
1888 firmware_len);
d930faee
AK		 1889
1890 if (mwifiex_pcie_disable_host_int(adapter)) {
acebe8c1
ZL		 1891 mwifiex_dbg(adapter, ERROR,
1892 "%s: Disabling interrupts failed.\n", __func__);
d930faee
AK		 1893 return -1;
1894 }
1895
1896 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE);
1897 if (!skb) {
1898 ret = -ENOMEM;
1899 goto done;
1900 }
d930faee
AK		 1901
1902 /* Perform firmware data transfer */
1903 do {
1904 u32 ireg_intr = 0;
1905
1906 /* More data? */
1907 if (offset >= firmware_len)
1908 break;
1909
1910 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
dd04e6ac 1911 ret = mwifiex_read_reg(adapter, reg->cmd_size,
d930faee
AK		 1912 &len);
1913 if (ret) {
acebe8c1
ZL		 1914 mwifiex_dbg(adapter, FATAL,
1915 "Failed reading len from boot code\n");
d930faee
AK		 1916 goto done;
1917 }
1918 if (len)
1919 break;
e7891ba2 1920 usleep_range(10, 20);
d930faee
AK		 1921 }
1922
1923 if (!len) {
1924 break;
1925 } else if (len > MWIFIEX_UPLD_SIZE) {
acebe8c1
ZL		 1926 mwifiex_dbg(adapter, ERROR,
1927 "FW download failure @ %d, invalid length %d\n",
1928 offset, len);
d930faee
AK		 1929 ret = -1;
1930 goto done;
1931 }
1932
1933 txlen = len;
1934
1935 if (len & BIT(0)) {
1936 block_retry_cnt++;
1937 if (block_retry_cnt > MAX_WRITE_IOMEM_RETRY) {
acebe8c1
ZL		 1938 mwifiex_dbg(adapter, ERROR,
1939 "FW download failure @ %d, over max\t"
1940 "retry count\n", offset);
d930faee
AK		 1941 ret = -1;
1942 goto done;
1943 }
acebe8c1
ZL		 1944 mwifiex_dbg(adapter, ERROR,
1945 "FW CRC error indicated by the\t"
1946 "helper: len = 0x%04X, txlen = %d\n",
1947 len, txlen);
d930faee
AK		 1948 len &= ~BIT(0);
1949 /* Setting this to 0 to resend from same offset */
1950 txlen = 0;
1951 } else {
1952 block_retry_cnt = 0;
1953 /* Set blocksize to transfer - checking for
1954 last block */
1955 if (firmware_len - offset < txlen)
1956 txlen = firmware_len - offset;
1957
acebe8c1 1958 mwifiex_dbg(adapter, INFO, ".");
d930faee 1959
dd04e6ac
AP		 1960 tx_blocks = (txlen + card->pcie.blksz_fw_dl - 1) /
1961 card->pcie.blksz_fw_dl;
d930faee
AK		 1962
1963 /* Copy payload to buffer */
1964 memmove(skb->data, &firmware[offset], txlen);
1965 }
1966
1967 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len);
dd04e6ac 1968 skb_trim(skb, tx_blocks * card->pcie.blksz_fw_dl);
d930faee
AK		 1969
1970 /* Send the boot command to device */
1971 if (mwifiex_pcie_send_boot_cmd(adapter, skb)) {
acebe8c1
ZL		 1972 mwifiex_dbg(adapter, ERROR,
1973 "Failed to send firmware download command\n");
d930faee
AK		 1974 ret = -1;
1975 goto done;
1976 }
fc331460 1977
d930faee
AK		 1978 /* Wait for the command done interrupt */
1979 do {
1980 if (mwifiex_read_reg(adapter, PCIE_CPU_INT_STATUS,
1981 &ireg_intr)) {
acebe8c1
ZL		 1982 mwifiex_dbg(adapter, ERROR,
1983 "%s: Failed to read\t"
1984 "interrupt status during fw dnld.\n",
1985 __func__);
dbccc92b
AD		 1986 mwifiex_unmap_pci_memory(adapter, skb,
1987 PCI_DMA_TODEVICE);
d930faee
AK		 1988 ret = -1;
1989 goto done;
1990 }
1991 } while ((ireg_intr & CPU_INTR_DOOR_BELL) ==
1992 CPU_INTR_DOOR_BELL);
fc331460 1993
dbccc92b 1994 mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE);
fc331460 1995
d930faee
AK		 1996 offset += txlen;
1997 } while (true);
1998
acebe8c1
ZL		 1999 mwifiex_dbg(adapter, MSG,
2000 "info: FW download over, size %d bytes\n", offset);
d930faee
AK		 2001
2002 ret = 0;
2003
2004done:
2005 dev_kfree_skb_any(skb);
2006 return ret;
2007}
2008
2009/*
2010 * This function checks the firmware status in card.
d930faee
AK		 2011 */
2012static int
2013mwifiex_check_fw_status(struct mwifiex_adapter *adapter, u32 poll_num)
2014{
2015 int ret = 0;
2fd5c6ed 2016 u32 firmware_stat;
dd04e6ac
AP		 2017 struct pcie_service_card *card = adapter->card;
2018 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 2019 u32 tries;
2020
2021 /* Mask spurios interrupts */
2022 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS_MASK,
f57c1edc 2023 HOST_INTR_MASK)) {
acebe8c1
ZL		 2024 mwifiex_dbg(adapter, ERROR,
2025 "Write register failed\n");
d930faee
AK		 2026 return -1;
2027 }
2028
acebe8c1
ZL		 2029 mwifiex_dbg(adapter, INFO,
2030 "Setting driver ready signature\n");
dd04e6ac
AP		 2031 if (mwifiex_write_reg(adapter, reg->drv_rdy,
2032 FIRMWARE_READY_PCIE)) {
acebe8c1
ZL		 2033 mwifiex_dbg(adapter, ERROR,
2034 "Failed to write driver ready signature\n");
d930faee
AK		 2035 return -1;
2036 }
2037
2038 /* Wait for firmware initialization event */
2039 for (tries = 0; tries < poll_num; tries++) {
dd04e6ac 2040 if (mwifiex_read_reg(adapter, reg->fw_status,
d930faee
AK		 2041 &firmware_stat))
2042 ret = -1;
2043 else
2044 ret = 0;
2045 if (ret)
2046 continue;
2047 if (firmware_stat == FIRMWARE_READY_PCIE) {
2048 ret = 0;
2049 break;
2050 } else {
a76b20e5 2051 msleep(100);
d930faee
AK		 2052 ret = -1;
2053 }
2054 }
2055
2fd5c6ed 2056 return ret;
2057}
2058
2059/* This function checks if WLAN is the winner.
2060 */
2061static int
2062mwifiex_check_winner_status(struct mwifiex_adapter *adapter)
2063{
2064 u32 winner = 0;
2065 int ret = 0;
2066 struct pcie_service_card *card = adapter->card;
2067 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2068
2069 if (mwifiex_read_reg(adapter, reg->fw_status, &winner)) {
2070 ret = -1;
2071 } else if (!winner) {
2072 mwifiex_dbg(adapter, INFO, "PCI-E is the winner\n");
2073 adapter->winner = 1;
2074 } else {
2075 mwifiex_dbg(adapter, ERROR,
2076 "PCI-E is not the winner <%#x,%d>, exit dnld\n",
2077 ret, adapter->winner);
d930faee
AK		 2078 }
2079
2080 return ret;
2081}
2082
2083/*
2084 * This function reads the interrupt status from card.
2085 */
99074fc1
XH		 2086static void mwifiex_interrupt_status(struct mwifiex_adapter *adapter,
2087 int msg_id)
d930faee
AK		 2088{
2089 u32 pcie_ireg;
2090 unsigned long flags;
99074fc1 2091 struct pcie_service_card *card = adapter->card;
d930faee 2092
5781fc29
SL		 2093 if (card->msi_enable) {
2094 spin_lock_irqsave(&adapter->int_lock, flags);
2095 adapter->int_status = 1;
2096 spin_unlock_irqrestore(&adapter->int_lock, flags);
2097 return;
2098 }
2099
d930faee
AK		 2100 if (!mwifiex_pcie_ok_to_access_hw(adapter))
2101 return;
2102
99074fc1
XH		 2103 if (card->msix_enable && msg_id >= 0) {
2104 pcie_ireg = BIT(msg_id);
2105 } else {
2106 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
2107 &pcie_ireg)) {
2108 mwifiex_dbg(adapter, ERROR, "Read register failed\n");
2109 return;
2110 }
2111
2112 if ((pcie_ireg == 0xFFFFFFFF) || !pcie_ireg)
2113 return;
d930faee 2114
d930faee
AK		 2115
2116 mwifiex_pcie_disable_host_int(adapter);
2117
2118 /* Clear the pending interrupts */
2119 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS,
2120 ~pcie_ireg)) {
acebe8c1
ZL		 2121 mwifiex_dbg(adapter, ERROR,
2122 "Write register failed\n");
d930faee
AK		 2123 return;
2124 }
99074fc1
XH		 2125 }
2126
99074fc1
XH		 2127 if (!adapter->pps_uapsd_mode &&
2128 adapter->ps_state == PS_STATE_SLEEP &&
2129 mwifiex_pcie_ok_to_access_hw(adapter)) {
2130 /* Potentially for PCIe we could get other
2131 * interrupts like shared. Don't change power
2132 * state until cookie is set
2133 */
2134 adapter->ps_state = PS_STATE_AWAKE;
2135 adapter->pm_wakeup_fw_try = false;
2136 del_timer(&adapter->wakeup_timer);
d930faee 2137 }
dc896b15
SL		 2138
2139 spin_lock_irqsave(&adapter->int_lock, flags);
2140 adapter->int_status |= pcie_ireg;
2141 spin_unlock_irqrestore(&adapter->int_lock, flags);
2142 mwifiex_dbg(adapter, INTR, "ireg: 0x%08x\n", pcie_ireg);
d930faee
AK		 2143}
2144
2145/*
2146 * Interrupt handler for PCIe root port
2147 *
2148 * This function reads the interrupt status from firmware and assigns
2149 * the main process in workqueue which will handle the interrupt.
2150 */
2151static irqreturn_t mwifiex_pcie_interrupt(int irq, void *context)
2152{
99074fc1
XH		 2153 struct mwifiex_msix_context *ctx = context;
2154 struct pci_dev *pdev = ctx->dev;
d930faee
AK		 2155 struct pcie_service_card *card;
2156 struct mwifiex_adapter *adapter;
2157
2158 if (!pdev) {
91442431 2159 pr_err("info: %s: pdev is NULL\n", __func__);
d930faee
AK		 2160 goto exit;
2161 }
2162
b2a31204 2163 card = pci_get_drvdata(pdev);
d930faee 2164 if (!card || !card->adapter) {
91442431
XH		 2165 pr_err("info: %s: card=%p adapter=%p\n", __func__, card,
2166 card ? card->adapter : NULL);
d930faee
AK		 2167 goto exit;
2168 }
2169 adapter = card->adapter;
2170
2171 if (adapter->surprise_removed)
2172 goto exit;
2173
99074fc1
XH		 2174 if (card->msix_enable)
2175 mwifiex_interrupt_status(adapter, ctx->msg_id);
2176 else
2177 mwifiex_interrupt_status(adapter, -1);
2178
b2713f67 2179 mwifiex_queue_main_work(adapter);
d930faee
AK		 2180
2181exit:
2182 return IRQ_HANDLED;
2183}
2184
2185/*
2186 * This function checks the current interrupt status.
2187 *
2188 * The following interrupts are checked and handled by this function -
2189 * - Data sent
2190 * - Command sent
2191 * - Command received
2192 * - Packets received
2193 * - Events received
2194 *
2195 * In case of Rx packets received, the packets are uploaded from card to
2196 * host and processed accordingly.
2197 */
99074fc1 2198static int mwifiex_process_pcie_int(struct mwifiex_adapter *adapter)
d930faee
AK		 2199{
2200 int ret;
5781fc29 2201 u32 pcie_ireg = 0;
d930faee 2202 unsigned long flags;
5781fc29 2203 struct pcie_service_card *card = adapter->card;
d930faee
AK		 2204
2205 spin_lock_irqsave(&adapter->int_lock, flags);
5781fc29
SL		 2206 if (!card->msi_enable) {
2207 /* Clear out unused interrupts */
2208 pcie_ireg = adapter->int_status;
2209 }
659c4788 2210 adapter->int_status = 0;
d930faee
AK		 2211 spin_unlock_irqrestore(&adapter->int_lock, flags);
2212
5781fc29
SL		 2213 if (card->msi_enable) {
2214 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
2215 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
2216 &pcie_ireg)) {
2217 mwifiex_dbg(adapter, ERROR,
2218 "Read register failed\n");
2219 return -1;
2220 }
2221
2222 if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) {
2223 if (mwifiex_write_reg(adapter,
2224 PCIE_HOST_INT_STATUS,
2225 ~pcie_ireg)) {
2226 mwifiex_dbg(adapter, ERROR,
2227 "Write register failed\n");
2228 return -1;
2229 }
2230 if (!adapter->pps_uapsd_mode &&
2231 adapter->ps_state == PS_STATE_SLEEP) {
2232 adapter->ps_state = PS_STATE_AWAKE;
2233 adapter->pm_wakeup_fw_try = false;
2234 del_timer(&adapter->wakeup_timer);
2235 }
2236 }
2237 }
2238 }
659c4788
AP		 2239 while (pcie_ireg & HOST_INTR_MASK) {
2240 if (pcie_ireg & HOST_INTR_DNLD_DONE) {
2241 pcie_ireg &= ~HOST_INTR_DNLD_DONE;
acebe8c1
ZL		 2242 mwifiex_dbg(adapter, INTR,
2243 "info: TX DNLD Done\n");
e7f767a7
AP		 2244 ret = mwifiex_pcie_send_data_complete(adapter);
2245 if (ret)
2246 return ret;
d930faee 2247 }
659c4788
AP		 2248 if (pcie_ireg & HOST_INTR_UPLD_RDY) {
2249 pcie_ireg &= ~HOST_INTR_UPLD_RDY;
acebe8c1
ZL		 2250 mwifiex_dbg(adapter, INTR,
2251 "info: Rx DATA\n");
d930faee
AK		 2252 ret = mwifiex_pcie_process_recv_data(adapter);
2253 if (ret)
2254 return ret;
2255 }
659c4788
AP		 2256 if (pcie_ireg & HOST_INTR_EVENT_RDY) {
2257 pcie_ireg &= ~HOST_INTR_EVENT_RDY;
acebe8c1
ZL		 2258 mwifiex_dbg(adapter, INTR,
2259 "info: Rx EVENT\n");
d930faee
AK		 2260 ret = mwifiex_pcie_process_event_ready(adapter);
2261 if (ret)
2262 return ret;
2263 }
2264
659c4788
AP		 2265 if (pcie_ireg & HOST_INTR_CMD_DONE) {
2266 pcie_ireg &= ~HOST_INTR_CMD_DONE;
d930faee 2267 if (adapter->cmd_sent) {
acebe8c1
ZL		 2268 mwifiex_dbg(adapter, INTR,
2269 "info: CMD sent Interrupt\n");
d930faee
AK		 2270 adapter->cmd_sent = false;
2271 }
2272 /* Handle command response */
2273 ret = mwifiex_pcie_process_cmd_complete(adapter);
2274 if (ret)
2275 return ret;
2276 }
2277
5781fc29
SL		 2278 if (card->msi_enable) {
2279 spin_lock_irqsave(&adapter->int_lock, flags);
2280 adapter->int_status = 0;
2281 spin_unlock_irqrestore(&adapter->int_lock, flags);
2282 }
2283
d930faee
AK		 2284 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
2285 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
2286 &pcie_ireg)) {
acebe8c1
ZL		 2287 mwifiex_dbg(adapter, ERROR,
2288 "Read register failed\n");
d930faee
AK		 2289 return -1;
2290 }
2291
2292 if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) {
2293 if (mwifiex_write_reg(adapter,
f57c1edc
YAP		 2294 PCIE_HOST_INT_STATUS,
2295 ~pcie_ireg)) {
acebe8c1
ZL		 2296 mwifiex_dbg(adapter, ERROR,
2297 "Write register failed\n");
d930faee
AK		 2298 return -1;
2299 }
d930faee
AK		 2300 }
2301
2302 }
2303 }
acebe8c1
ZL		 2304 mwifiex_dbg(adapter, INTR,
2305 "info: cmd_sent=%d data_sent=%d\n",
2306 adapter->cmd_sent, adapter->data_sent);
5781fc29 2307 if (!card->msi_enable && adapter->ps_state != PS_STATE_SLEEP)
b2fda1f6 2308 mwifiex_pcie_enable_host_int(adapter);
d930faee
AK		 2309
2310 return 0;
2311}
2312
99074fc1
XH		 2313static int mwifiex_process_msix_int(struct mwifiex_adapter *adapter)
2314{
2315 int ret;
2316 u32 pcie_ireg;
2317 unsigned long flags;
2318
2319 spin_lock_irqsave(&adapter->int_lock, flags);
2320 /* Clear out unused interrupts */
2321 pcie_ireg = adapter->int_status;
2322 adapter->int_status = 0;
2323 spin_unlock_irqrestore(&adapter->int_lock, flags);
2324
2325 if (pcie_ireg & HOST_INTR_DNLD_DONE) {
2326 mwifiex_dbg(adapter, INTR,
2327 "info: TX DNLD Done\n");
2328 ret = mwifiex_pcie_send_data_complete(adapter);
2329 if (ret)
2330 return ret;
2331 }
2332 if (pcie_ireg & HOST_INTR_UPLD_RDY) {
2333 mwifiex_dbg(adapter, INTR,
2334 "info: Rx DATA\n");
2335 ret = mwifiex_pcie_process_recv_data(adapter);
2336 if (ret)
2337 return ret;
2338 }
2339 if (pcie_ireg & HOST_INTR_EVENT_RDY) {
2340 mwifiex_dbg(adapter, INTR,
2341 "info: Rx EVENT\n");
2342 ret = mwifiex_pcie_process_event_ready(adapter);
2343 if (ret)
2344 return ret;
2345 }
2346
2347 if (pcie_ireg & HOST_INTR_CMD_DONE) {
2348 if (adapter->cmd_sent) {
2349 mwifiex_dbg(adapter, INTR,
2350 "info: CMD sent Interrupt\n");
2351 adapter->cmd_sent = false;
2352 }
2353 /* Handle command response */
2354 ret = mwifiex_pcie_process_cmd_complete(adapter);
2355 if (ret)
2356 return ret;
2357 }
2358
2359 mwifiex_dbg(adapter, INTR,
2360 "info: cmd_sent=%d data_sent=%d\n",
2361 adapter->cmd_sent, adapter->data_sent);
2362
2363 return 0;
2364}
2365
2366static int mwifiex_process_int_status(struct mwifiex_adapter *adapter)
2367{
2368 struct pcie_service_card *card = adapter->card;
2369
2370 if (card->msix_enable)
2371 return mwifiex_process_msix_int(adapter);
2372 else
2373 return mwifiex_process_pcie_int(adapter);
2374}
2375
d930faee
AK		 2376/*
2377 * This function downloads data from driver to card.
2378 *
2379 * Both commands and data packets are transferred to the card by this
2380 * function.
2381 *
2382 * This function adds the PCIE specific header to the front of the buffer
2383 * before transferring. The header contains the length of the packet and
2384 * the type. The firmware handles the packets based upon this set type.
2385 */
2386static int mwifiex_pcie_host_to_card(struct mwifiex_adapter *adapter, u8 type,
2387 struct sk_buff *skb,
2388 struct mwifiex_tx_param *tx_param)
2389{
fa161cb7 2390 if (!skb) {
acebe8c1
ZL		 2391 mwifiex_dbg(adapter, ERROR,
2392 "Passed NULL skb to %s\n", __func__);
d930faee
AK		 2393 return -1;
2394 }
2395
2396 if (type == MWIFIEX_TYPE_DATA)
e7f767a7 2397 return mwifiex_pcie_send_data(adapter, skb, tx_param);
d930faee
AK		 2398 else if (type == MWIFIEX_TYPE_CMD)
2399 return mwifiex_pcie_send_cmd(adapter, skb);
2400
2401 return 0;
2402}
2403
4646968b
XH		 2404/* Function to dump PCIE scratch registers in case of FW crash
2405 */
2406static int
2407mwifiex_pcie_reg_dump(struct mwifiex_adapter *adapter, char *drv_buf)
2408{
2409 char *p = drv_buf;
2410 char buf[256], *ptr;
2411 int i;
2412 u32 value;
2413 struct pcie_service_card *card = adapter->card;
2414 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2415 int pcie_scratch_reg[] = {PCIE_SCRATCH_12_REG,
2416 PCIE_SCRATCH_13_REG,
2417 PCIE_SCRATCH_14_REG};
2418
2419 if (!p)
2420 return 0;
2421
2422 mwifiex_dbg(adapter, MSG, "PCIE register dump start\n");
2423
2424 if (mwifiex_read_reg(adapter, reg->fw_status, &value)) {
2425 mwifiex_dbg(adapter, ERROR, "failed to read firmware status");
2426 return 0;
2427 }
2428
2429 ptr = buf;
2430 mwifiex_dbg(adapter, MSG, "pcie scratch register:");
2431 for (i = 0; i < ARRAY_SIZE(pcie_scratch_reg); i++) {
2432 mwifiex_read_reg(adapter, pcie_scratch_reg[i], &value);
2433 ptr += sprintf(ptr, "reg:0x%x, value=0x%x\n",
2434 pcie_scratch_reg[i], value);
2435 }
2436
2437 mwifiex_dbg(adapter, MSG, "%s\n", buf);
2438 p += sprintf(p, "%s\n", buf);
2439
2440 mwifiex_dbg(adapter, MSG, "PCIE register dump end\n");
2441
2442 return p - drv_buf;
2443}
2444
92c2538f
AK		 2445/* This function read/write firmware */
2446static enum rdwr_status
2447mwifiex_pcie_rdwr_firmware(struct mwifiex_adapter *adapter, u8 doneflag)
2448{
2449 int ret, tries;
2450 u8 ctrl_data;
0172404d 2451 u32 fw_status;
92c2538f
AK		 2452 struct pcie_service_card *card = adapter->card;
2453 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2454
0172404d
XH		 2455 if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status))
2456 return RDWR_STATUS_FAILURE;
2457
50632092
XH		 2458 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl,
2459 reg->fw_dump_host_ready);
92c2538f 2460 if (ret) {
acebe8c1
ZL		 2461 mwifiex_dbg(adapter, ERROR,
2462 "PCIE write err\n");
92c2538f
AK		 2463 return RDWR_STATUS_FAILURE;
2464 }
2465
2466 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
2467 mwifiex_read_reg_byte(adapter, reg->fw_dump_ctrl, &ctrl_data);
2468 if (ctrl_data == FW_DUMP_DONE)
2469 return RDWR_STATUS_SUCCESS;
2470 if (doneflag && ctrl_data == doneflag)
2471 return RDWR_STATUS_DONE;
50632092 2472 if (ctrl_data != reg->fw_dump_host_ready) {
acebe8c1
ZL		 2473 mwifiex_dbg(adapter, WARN,
2474 "The ctrl reg was changed, re-try again!\n");
24716876 2475 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl,
50632092 2476 reg->fw_dump_host_ready);
92c2538f 2477 if (ret) {
acebe8c1
ZL		 2478 mwifiex_dbg(adapter, ERROR,
2479 "PCIE write err\n");
92c2538f
AK		 2480 return RDWR_STATUS_FAILURE;
2481 }
2482 }
2483 usleep_range(100, 200);
2484 }
2485
acebe8c1 2486 mwifiex_dbg(adapter, ERROR, "Fail to pull ctrl_data\n");
92c2538f
AK		 2487 return RDWR_STATUS_FAILURE;
2488}
2489
2490/* This function dump firmware memory to file */
fc697159 2491static void mwifiex_pcie_fw_dump(struct mwifiex_adapter *adapter)
92c2538f
AK		 2492{
2493 struct pcie_service_card *card = adapter->card;
2494 const struct mwifiex_pcie_card_reg *creg = card->pcie.reg;
2495 unsigned int reg, reg_start, reg_end;
11e70824 2496 u8 *dbg_ptr, *end_ptr, *tmp_ptr, fw_dump_num, dump_num;
56486026 2497 u8 idx, i, read_reg, doneflag = 0;
92c2538f
AK		 2498 enum rdwr_status stat;
2499 u32 memory_size;
24716876 2500 int ret;
92c2538f 2501
b4e8aebb 2502 if (!card->pcie.can_dump_fw)
92c2538f
AK		 2503 return;
2504
50632092
XH		 2505 for (idx = 0; idx < adapter->num_mem_types; idx++) {
2506 struct memory_type_mapping *entry =
2507 &adapter->mem_type_mapping_tbl[idx];
92c2538f
AK		 2508
2509 if (entry->mem_ptr) {
2510 vfree(entry->mem_ptr);
2511 entry->mem_ptr = NULL;
2512 }
2513 entry->mem_size = 0;
2514 }
2515
03f0f7cd 2516 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump start ==\n");
92c2538f
AK		 2517
2518 /* Read the number of the memories which will dump */
2519 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2520 if (stat == RDWR_STATUS_FAILURE)
57670ee8 2521 return;
92c2538f
AK		 2522
2523 reg = creg->fw_dump_start;
11e70824
XH		 2524 mwifiex_read_reg_byte(adapter, reg, &fw_dump_num);
2525
2526 /* W8997 chipset firmware dump will be restore in single region*/
2527 if (fw_dump_num == 0)
2528 dump_num = 1;
2529 else
2530 dump_num = fw_dump_num;
92c2538f
AK		 2531
2532 /* Read the length of every memory which will dump */
2533 for (idx = 0; idx < dump_num; idx++) {
50632092
XH		 2534 struct memory_type_mapping *entry =
2535 &adapter->mem_type_mapping_tbl[idx];
92c2538f 2536 memory_size = 0;
11e70824
XH		 2537 if (fw_dump_num != 0) {
2538 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2539 if (stat == RDWR_STATUS_FAILURE)
2540 return;
2541
2542 reg = creg->fw_dump_start;
2543 for (i = 0; i < 4; i++) {
2544 mwifiex_read_reg_byte(adapter, reg, &read_reg);
2545 memory_size |= (read_reg << (i * 8));
ccf5fa4f 2546 reg++;
11e70824
XH		 2547 }
2548 } else {
2549 memory_size = MWIFIEX_FW_DUMP_MAX_MEMSIZE;
92c2538f
AK		 2550 }
2551
2552 if (memory_size == 0) {
acebe8c1 2553 mwifiex_dbg(adapter, MSG, "Firmware dump Finished!\n");
7e174833 2554 ret = mwifiex_write_reg(adapter, creg->fw_dump_ctrl,
50632092 2555 creg->fw_dump_read_done);
7e174833 2556 if (ret) {
acebe8c1 2557 mwifiex_dbg(adapter, ERROR, "PCIE write err\n");
57670ee8 2558 return;
7e174833 2559 }
92c2538f
AK		 2560 break;
2561 }
2562
acebe8c1
ZL		 2563 mwifiex_dbg(adapter, DUMP,
2564 "%s_SIZE=0x%x\n", entry->mem_name, memory_size);
92c2538f
AK		 2565 entry->mem_ptr = vmalloc(memory_size + 1);
2566 entry->mem_size = memory_size;
2567 if (!entry->mem_ptr) {
acebe8c1
ZL		 2568 mwifiex_dbg(adapter, ERROR,
2569 "Vmalloc %s failed\n", entry->mem_name);
57670ee8 2570 return;
92c2538f
AK		 2571 }
2572 dbg_ptr = entry->mem_ptr;
2573 end_ptr = dbg_ptr + memory_size;
2574
2575 doneflag = entry->done_flag;
acebe8c1
ZL		 2576 mwifiex_dbg(adapter, DUMP, "Start %s output, please wait...\n",
2577 entry->mem_name);
92c2538f
AK		 2578
2579 do {
2580 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2581 if (RDWR_STATUS_FAILURE == stat)
57670ee8 2582 return;
92c2538f
AK		 2583
2584 reg_start = creg->fw_dump_start;
2585 reg_end = creg->fw_dump_end;
2586 for (reg = reg_start; reg <= reg_end; reg++) {
2587 mwifiex_read_reg_byte(adapter, reg, dbg_ptr);
24716876 2588 if (dbg_ptr < end_ptr) {
92c2538f 2589 dbg_ptr++;
56486026 2590 continue;
24716876 2591 }
56486026
XH		 2592 mwifiex_dbg(adapter, ERROR,
2593 "pre-allocated buf not enough\n");
2594 tmp_ptr =
2595 vzalloc(memory_size + MWIFIEX_SIZE_4K);
2596 if (!tmp_ptr)
2597 return;
2598 memcpy(tmp_ptr, entry->mem_ptr, memory_size);
2599 vfree(entry->mem_ptr);
2600 entry->mem_ptr = tmp_ptr;
2601 tmp_ptr = NULL;
2602 dbg_ptr = entry->mem_ptr + memory_size;
2603 memory_size += MWIFIEX_SIZE_4K;
2604 end_ptr = entry->mem_ptr + memory_size;
92c2538f
AK		 2605 }
2606
2607 if (stat != RDWR_STATUS_DONE)
2608 continue;
2609
acebe8c1
ZL		 2610 mwifiex_dbg(adapter, DUMP,
2611 "%s done: size=0x%tx\n",
2612 entry->mem_name, dbg_ptr - entry->mem_ptr);
92c2538f
AK		 2613 break;
2614 } while (true);
2615 }
03f0f7cd 2616 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump end ==\n");
92c2538f
AK		 2617}
2618
fc697159
AK		 2619static void mwifiex_pcie_device_dump_work(struct mwifiex_adapter *adapter)
2620{
2621 mwifiex_drv_info_dump(adapter);
2622 mwifiex_pcie_fw_dump(adapter);
57670ee8 2623 mwifiex_upload_device_dump(adapter);
fc697159
AK		 2624}
2625
2f5872b6
MH		 2626static unsigned long iface_work_flags;
2627static struct mwifiex_adapter *save_adapter;
92c2538f
AK		 2628static void mwifiex_pcie_work(struct work_struct *work)
2629{
fc697159 2630 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
2f5872b6 2631 &iface_work_flags))
fc697159 2632 mwifiex_pcie_device_dump_work(save_adapter);
92c2538f
AK		 2633}
2634
2f5872b6 2635static DECLARE_WORK(pcie_work, mwifiex_pcie_work);
92c2538f 2636/* This function dumps FW information */
fc697159 2637static void mwifiex_pcie_device_dump(struct mwifiex_adapter *adapter)
92c2538f 2638{
2f5872b6 2639 save_adapter = adapter;
fc697159 2640 if (test_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &iface_work_flags))
92c2538f
AK		 2641 return;
2642
fc697159 2643 set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &iface_work_flags);
92c2538f 2644
2f5872b6 2645 schedule_work(&pcie_work);
92c2538f
AK		 2646}
2647
d930faee
AK		 2648/*
2649 * This function initializes the PCI-E host memory space, WCB rings, etc.
2650 *
2651 * The following initializations steps are followed -
2652 * - Allocate TXBD ring buffers
2653 * - Allocate RXBD ring buffers
2654 * - Allocate event BD ring buffers
2655 * - Allocate command response ring buffer
2656 * - Allocate sleep cookie buffer
2657 */
2658static int mwifiex_pcie_init(struct mwifiex_adapter *adapter)
2659{
2660 struct pcie_service_card *card = adapter->card;
2661 int ret;
2662 struct pci_dev *pdev = card->dev;
52301a81 2663 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee
AK		 2664
2665 pci_set_drvdata(pdev, card);
2666
2667 ret = pci_enable_device(pdev);
2668 if (ret)
2669 goto err_enable_dev;
2670
2671 pci_set_master(pdev);
2672
fdb1e28e 2673 pr_notice("try set_consistent_dma_mask(32)\n");
d930faee
AK		 2674 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2675 if (ret) {
fdb1e28e 2676 pr_err("set_dma_mask(32) failed\n");
d930faee
AK		 2677 goto err_set_dma_mask;
2678 }
2679
2680 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2681 if (ret) {
fdb1e28e 2682 pr_err("set_consistent_dma_mask(64) failed\n");
d930faee
AK		 2683 goto err_set_dma_mask;
2684 }
2685
2686 ret = pci_request_region(pdev, 0, DRV_NAME);
2687 if (ret) {
fdb1e28e 2688 pr_err("req_reg(0) error\n");
d930faee
AK		 2689 goto err_req_region0;
2690 }
2691 card->pci_mmap = pci_iomap(pdev, 0, 0);
2692 if (!card->pci_mmap) {
fdb1e28e 2693 pr_err("iomap(0) error\n");
3220712d 2694 ret = -EIO;
d930faee
AK		 2695 goto err_iomap0;
2696 }
2697 ret = pci_request_region(pdev, 2, DRV_NAME);
2698 if (ret) {
fdb1e28e 2699 pr_err("req_reg(2) error\n");
d930faee
AK		 2700 goto err_req_region2;
2701 }
2702 card->pci_mmap1 = pci_iomap(pdev, 2, 0);
2703 if (!card->pci_mmap1) {
fdb1e28e 2704 pr_err("iomap(2) error\n");
3220712d 2705 ret = -EIO;
d930faee
AK		 2706 goto err_iomap2;
2707 }
2708
fdb1e28e
XH		 2709 pr_notice("PCI memory map Virt0: %p PCI memory map Virt2: %p\n",
2710 card->pci_mmap, card->pci_mmap1);
d930faee
AK		 2711
2712 card->cmdrsp_buf = NULL;
2713 ret = mwifiex_pcie_create_txbd_ring(adapter);
2714 if (ret)
2715 goto err_cre_txbd;
2716 ret = mwifiex_pcie_create_rxbd_ring(adapter);
2717 if (ret)
2718 goto err_cre_rxbd;
2719 ret = mwifiex_pcie_create_evtbd_ring(adapter);
2720 if (ret)
2721 goto err_cre_evtbd;
2722 ret = mwifiex_pcie_alloc_cmdrsp_buf(adapter);
2723 if (ret)
2724 goto err_alloc_cmdbuf;
52301a81
AP		 2725 if (reg->sleep_cookie) {
2726 ret = mwifiex_pcie_alloc_sleep_cookie_buf(adapter);
2727 if (ret)
2728 goto err_alloc_cookie;
2729 } else {
2730 card->sleep_cookie_vbase = NULL;
2731 }
d930faee
AK		 2732 return ret;
2733
2734err_alloc_cookie:
2735 mwifiex_pcie_delete_cmdrsp_buf(adapter);
2736err_alloc_cmdbuf:
2737 mwifiex_pcie_delete_evtbd_ring(adapter);
2738err_cre_evtbd:
2739 mwifiex_pcie_delete_rxbd_ring(adapter);
2740err_cre_rxbd:
2741 mwifiex_pcie_delete_txbd_ring(adapter);
2742err_cre_txbd:
2743 pci_iounmap(pdev, card->pci_mmap1);
2744err_iomap2:
2745 pci_release_region(pdev, 2);
2746err_req_region2:
2747 pci_iounmap(pdev, card->pci_mmap);
2748err_iomap0:
2749 pci_release_region(pdev, 0);
2750err_req_region0:
2751err_set_dma_mask:
2752 pci_disable_device(pdev);
2753err_enable_dev:
2754 pci_set_drvdata(pdev, NULL);
2755 return ret;
2756}
2757
2758/*
2759 * This function cleans up the allocated card buffers.
2760 *
2761 * The following are freed by this function -
2762 * - TXBD ring buffers
2763 * - RXBD ring buffers
2764 * - Event BD ring buffers
2765 * - Command response ring buffer
2766 * - Sleep cookie buffer
2767 */
2768static void mwifiex_pcie_cleanup(struct mwifiex_adapter *adapter)
2769{
2770 struct pcie_service_card *card = adapter->card;
2771 struct pci_dev *pdev = card->dev;
dd04e6ac 2772 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
d930faee 2773
d930faee 2774 if (user_rmmod) {
acebe8c1
ZL		 2775 mwifiex_dbg(adapter, INFO,
2776 "Clearing driver ready signature\n");
dd04e6ac 2777 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000))
acebe8c1
ZL		 2778 mwifiex_dbg(adapter, ERROR,
2779 "Failed to write driver not-ready signature\n");
d930faee
AK		 2780 }
2781
2782 if (pdev) {
2783 pci_iounmap(pdev, card->pci_mmap);
2784 pci_iounmap(pdev, card->pci_mmap1);
5b0d9b21 2785 pci_disable_device(pdev);
c380aafb
YAP		 2786 pci_release_region(pdev, 2);
2787 pci_release_region(pdev, 0);
d930faee
AK		 2788 pci_set_drvdata(pdev, NULL);
2789 }
3c59e328 2790 kfree(card);
d930faee
AK		 2791}
2792
7be0f5b5
AP		 2793static int mwifiex_pcie_request_irq(struct mwifiex_adapter *adapter)
2794{
99074fc1 2795 int ret, i, j;
7be0f5b5
AP		 2796 struct pcie_service_card *card = adapter->card;
2797 struct pci_dev *pdev = card->dev;
2798
99074fc1
XH		 2799 if (card->pcie.reg->msix_support) {
2800 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
2801 card->msix_entries[i].entry = i;
2802 ret = pci_enable_msix_exact(pdev, card->msix_entries,
2803 MWIFIEX_NUM_MSIX_VECTORS);
2804 if (!ret) {
2805 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) {
2806 card->msix_ctx[i].dev = pdev;
2807 card->msix_ctx[i].msg_id = i;
2808
2809 ret = request_irq(card->msix_entries[i].vector,
2810 mwifiex_pcie_interrupt, 0,
2811 "MWIFIEX_PCIE_MSIX",
2812 &card->msix_ctx[i]);
2813 if (ret)
2814 break;
2815 }
2816
2817 if (ret) {
2818 mwifiex_dbg(adapter, INFO, "request_irq fail: %d\n",
2819 ret);
2820 for (j = 0; j < i; j++)
2821 free_irq(card->msix_entries[j].vector,
2822 &card->msix_ctx[i]);
2823 pci_disable_msix(pdev);
2824 } else {
2825 mwifiex_dbg(adapter, MSG, "MSIx enabled!");
2826 card->msix_enable = 1;
2827 return 0;
2828 }
2829 }
2830 }
2831
7be0f5b5
AP		 2832 if (pci_enable_msi(pdev) != 0)
2833 pci_disable_msi(pdev);
2834 else
2835 card->msi_enable = 1;
2836
2837 mwifiex_dbg(adapter, INFO, "msi_enable = %d\n", card->msi_enable);
2838
99074fc1
XH		 2839 card->share_irq_ctx.dev = pdev;
2840 card->share_irq_ctx.msg_id = -1;
7be0f5b5 2841 ret = request_irq(pdev->irq, mwifiex_pcie_interrupt, IRQF_SHARED,
99074fc1 2842 "MRVL_PCIE", &card->share_irq_ctx);
7be0f5b5
AP		 2843 if (ret) {
2844 pr_err("request_irq failed: ret=%d\n", ret);
7be0f5b5
AP		 2845 return -1;
2846 }
2847
2848 return 0;
2849}
2850
a362e16b 2851/*
47ce90f9 2852 * This function gets the firmware name for downloading by revision id
a362e16b
SL		 2853 *
2854 * Read revision id register to get revision id
2855 */
2856static void mwifiex_pcie_get_fw_name(struct mwifiex_adapter *adapter)
2857{
2858 int revision_id = 0;
e87650bc 2859 int version;
a362e16b
SL		 2860 struct pcie_service_card *card = adapter->card;
2861
2862 switch (card->dev->device) {
2863 case PCIE_DEVICE_ID_MARVELL_88W8766P:
2864 strcpy(adapter->fw_name, PCIE8766_DEFAULT_FW_NAME);
2865 break;
2866 case PCIE_DEVICE_ID_MARVELL_88W8897:
2867 mwifiex_write_reg(adapter, 0x0c58, 0x80c00000);
2868 mwifiex_read_reg(adapter, 0x0c58, &revision_id);
2869 revision_id &= 0xff00;
2870 switch (revision_id) {
2871 case PCIE8897_A0:
2872 strcpy(adapter->fw_name, PCIE8897_A0_FW_NAME);
2873 break;
2874 case PCIE8897_B0:
2875 strcpy(adapter->fw_name, PCIE8897_B0_FW_NAME);
2876 break;
2877 default:
b9db3978
SL		 2878 strcpy(adapter->fw_name, PCIE8897_DEFAULT_FW_NAME);
2879
a362e16b
SL		 2880 break;
2881 }
c865a700 2882 break;
a362e16b
SL		 2883 case PCIE_DEVICE_ID_MARVELL_88W8997:
2884 mwifiex_read_reg(adapter, 0x0c48, &revision_id);
e87650bc
SL		 2885 mwifiex_read_reg(adapter, 0x0cd0, &version);
2886 version &= 0x7;
a362e16b
SL		 2887 switch (revision_id) {
2888 case PCIE8997_V2:
473dfbfa 2889 if (version == CHIP_VER_PCIEUART)
e87650bc 2890 strcpy(adapter->fw_name,
473dfbfa 2891 PCIEUART8997_FW_NAME_V2);
e87650bc
SL		 2892 else
2893 strcpy(adapter->fw_name,
473dfbfa 2894 PCIEUSB8997_FW_NAME_V2);
a362e16b
SL		 2895 break;
2896 case PCIE8997_Z:
473dfbfa 2897 if (version == CHIP_VER_PCIEUART)
e87650bc 2898 strcpy(adapter->fw_name,
473dfbfa 2899 PCIEUART8997_FW_NAME_Z);
e87650bc
SL		 2900 else
2901 strcpy(adapter->fw_name,
473dfbfa 2902 PCIEUSB8997_FW_NAME_Z);
a362e16b
SL		 2903 break;
2904 default:
b9db3978 2905 strcpy(adapter->fw_name, PCIE8997_DEFAULT_FW_NAME);
a362e16b
SL		 2906 break;
2907 }
2908 default:
2909 break;
2910 }
2911}
2912
d930faee
AK		 2913/*
2914 * This function registers the PCIE device.
2915 *
2916 * PCIE IRQ is claimed, block size is set and driver data is initialized.
2917 */
2918static int mwifiex_register_dev(struct mwifiex_adapter *adapter)
2919{
d930faee
AK		 2920 struct pcie_service_card *card = adapter->card;
2921 struct pci_dev *pdev = card->dev;
2922
2923 /* save adapter pointer in card */
2924 card->adapter = adapter;
fdb1e28e 2925 adapter->dev = &pdev->dev;
d930faee 2926
7be0f5b5 2927 if (mwifiex_pcie_request_irq(adapter))
d930faee 2928 return -1;
d930faee 2929
828cf222 2930 adapter->tx_buf_size = card->pcie.tx_buf_size;
50632092
XH		 2931 adapter->mem_type_mapping_tbl = card->pcie.mem_type_mapping_tbl;
2932 adapter->num_mem_types = card->pcie.num_mem_types;
1fe192d8 2933 adapter->ext_scan = card->pcie.can_ext_scan;
a362e16b 2934 mwifiex_pcie_get_fw_name(adapter);
d930faee
AK		 2935
2936 return 0;
2937}
2938
2939/*
2940 * This function unregisters the PCIE device.
2941 *
2942 * The PCIE IRQ is released, the function is disabled and driver
2943 * data is set to null.
2944 */
2945static void mwifiex_unregister_dev(struct mwifiex_adapter *adapter)
2946{
2947 struct pcie_service_card *card = adapter->card;
52301a81 2948 const struct mwifiex_pcie_card_reg *reg;
141bcf09 2949 struct pci_dev *pdev;
99074fc1 2950 int i;
d930faee
AK		 2951
2952 if (card) {
141bcf09 2953 pdev = card->dev;
99074fc1
XH		 2954 if (card->msix_enable) {
2955 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
2956 synchronize_irq(card->msix_entries[i].vector);
2957
2958 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
2959 free_irq(card->msix_entries[i].vector,
2960 &card->msix_ctx[i]);
2961
2962 card->msix_enable = 0;
2963 pci_disable_msix(pdev);
2964 } else {
2965 mwifiex_dbg(adapter, INFO,
2966 "%s(): calling free_irq()\n", __func__);
2967 free_irq(card->dev->irq, &card->share_irq_ctx);
2968
2969 if (card->msi_enable)
2970 pci_disable_msi(pdev);
2971 }
fc331460 2972
52301a81
AP		 2973 reg = card->pcie.reg;
2974 if (reg->sleep_cookie)
2975 mwifiex_pcie_delete_sleep_cookie_buf(adapter);
2976
fc331460
AP		 2977 mwifiex_pcie_delete_cmdrsp_buf(adapter);
2978 mwifiex_pcie_delete_evtbd_ring(adapter);
2979 mwifiex_pcie_delete_rxbd_ring(adapter);
2980 mwifiex_pcie_delete_txbd_ring(adapter);
2981 card->cmdrsp_buf = NULL;
d930faee
AK		 2982 }
2983}
2984
2985static struct mwifiex_if_ops pcie_ops = {
2986 .init_if = mwifiex_pcie_init,
2987 .cleanup_if = mwifiex_pcie_cleanup,
2988 .check_fw_status = mwifiex_check_fw_status,
2fd5c6ed 2989 .check_winner_status = mwifiex_check_winner_status,
d930faee
AK		 2990 .prog_fw = mwifiex_prog_fw_w_helper,
2991 .register_dev = mwifiex_register_dev,
2992 .unregister_dev = mwifiex_unregister_dev,
2993 .enable_int = mwifiex_pcie_enable_host_int,
d41376ca 2994 .disable_int = mwifiex_pcie_disable_host_int_noerr,
d930faee
AK		 2995 .process_int_status = mwifiex_process_int_status,
2996 .host_to_card = mwifiex_pcie_host_to_card,
2997 .wakeup = mwifiex_pm_wakeup_card,
2998 .wakeup_complete = mwifiex_pm_wakeup_card_complete,
2999
3000 /* PCIE specific */
3001 .cmdrsp_complete = mwifiex_pcie_cmdrsp_complete,
3002 .event_complete = mwifiex_pcie_event_complete,
3003 .update_mp_end_port = NULL,
3004 .cleanup_mpa_buf = NULL,
c6d1d87a 3005 .init_fw_port = mwifiex_pcie_init_fw_port,
fbd7e7ac 3006 .clean_pcie_ring = mwifiex_clean_pcie_ring_buf,
4646968b 3007 .reg_dump = mwifiex_pcie_reg_dump,
fc697159 3008 .device_dump = mwifiex_pcie_device_dump,
d930faee
AK		 3009};
3010
3011/*
3012 * This function initializes the PCIE driver module.
3013 *
3014 * This initiates the semaphore and registers the device with
3015 * PCIE bus.
3016 */
3017static int mwifiex_pcie_init_module(void)
3018{
3019 int ret;
3020
ca8f2112 3021 pr_debug("Marvell PCIe Driver\n");
d930faee
AK		 3022
3023 sema_init(&add_remove_card_sem, 1);
3024
3025 /* Clear the flag in case user removes the card. */
3026 user_rmmod = 0;
3027
3028 ret = pci_register_driver(&mwifiex_pcie);
3029 if (ret)
3030 pr_err("Driver register failed!\n");
3031 else
3032 pr_debug("info: Driver registered successfully!\n");
3033
3034 return ret;
3035}
3036
3037/*
3038 * This function cleans up the PCIE driver.
3039 *
3040 * The following major steps are followed for cleanup -
3041 * - Resume the device if its suspended
3042 * - Disconnect the device if connected
3043 * - Shutdown the firmware
3044 * - Unregister the device from PCIE bus.
3045 */
3046static void mwifiex_pcie_cleanup_module(void)
3047{
3048 if (!down_interruptible(&add_remove_card_sem))
3049 up(&add_remove_card_sem);
3050
3051 /* Set the flag as user is removing this module. */
3052 user_rmmod = 1;
3053
2f5872b6 3054 cancel_work_sync(&pcie_work);
d930faee
AK		 3055 pci_unregister_driver(&mwifiex_pcie);
3056}
3057
3058module_init(mwifiex_pcie_init_module);
3059module_exit(mwifiex_pcie_cleanup_module);
3060
3061MODULE_AUTHOR("Marvell International Ltd.");
3062MODULE_DESCRIPTION("Marvell WiFi-Ex PCI-Express Driver version " PCIE_VERSION);
3063MODULE_VERSION(PCIE_VERSION);
3064MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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