Commit | Line | Data |
---|---|---|
d930faee AK |
1 | /* |
2 | * Marvell Wireless LAN device driver: PCIE specific handling | |
3 | * | |
4 | * Copyright (C) 2011, Marvell International Ltd. | |
5 | * | |
6 | * This software file (the "File") is distributed by Marvell International | |
7 | * Ltd. under the terms of the GNU General Public License Version 2, June 1991 | |
8 | * (the "License"). You may use, redistribute and/or modify this File in | |
9 | * accordance with the terms and conditions of the License, a copy of which | |
10 | * is available by writing to the Free Software Foundation, Inc., | |
11 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the | |
12 | * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. | |
13 | * | |
14 | * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE | |
15 | * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE | |
16 | * ARE EXPRESSLY DISCLAIMED. The License provides additional details about | |
17 | * this warranty disclaimer. | |
18 | */ | |
19 | ||
20 | #include <linux/firmware.h> | |
21 | ||
22 | #include "decl.h" | |
23 | #include "ioctl.h" | |
24 | #include "util.h" | |
25 | #include "fw.h" | |
26 | #include "main.h" | |
27 | #include "wmm.h" | |
28 | #include "11n.h" | |
29 | #include "pcie.h" | |
30 | ||
31 | #define PCIE_VERSION "1.0" | |
32 | #define DRV_NAME "Marvell mwifiex PCIe" | |
33 | ||
34 | static u8 user_rmmod; | |
35 | ||
36 | static struct mwifiex_if_ops pcie_ops; | |
37 | ||
38 | static struct semaphore add_remove_card_sem; | |
d930faee | 39 | |
fc331460 AP |
40 | static int |
41 | mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb, | |
dbccc92b | 42 | size_t size, int flags) |
d930faee | 43 | { |
fc331460 | 44 | struct pcie_service_card *card = adapter->card; |
dbccc92b | 45 | struct mwifiex_dma_mapping mapping; |
d930faee | 46 | |
dbccc92b AD |
47 | mapping.addr = pci_map_single(card->dev, skb->data, size, flags); |
48 | if (pci_dma_mapping_error(card->dev, mapping.addr)) { | |
fc331460 AP |
49 | dev_err(adapter->dev, "failed to map pci memory!\n"); |
50 | return -1; | |
51 | } | |
dbccc92b AD |
52 | mapping.len = size; |
53 | memcpy(skb->cb, &mapping, sizeof(mapping)); | |
fc331460 | 54 | return 0; |
d930faee AK |
55 | } |
56 | ||
dbccc92b AD |
57 | static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter, |
58 | struct sk_buff *skb, int flags) | |
59 | { | |
60 | struct pcie_service_card *card = adapter->card; | |
61 | struct mwifiex_dma_mapping mapping; | |
62 | ||
63 | MWIFIEX_SKB_PACB(skb, &mapping); | |
64 | pci_unmap_single(card->dev, mapping.addr, mapping.len, flags); | |
65 | } | |
66 | ||
d930faee AK |
67 | /* |
68 | * This function reads sleep cookie and checks if FW is ready | |
69 | */ | |
70 | static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter) | |
71 | { | |
72 | u32 *cookie_addr; | |
73 | struct pcie_service_card *card = adapter->card; | |
52301a81 AP |
74 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
75 | ||
76 | if (!reg->sleep_cookie) | |
77 | return true; | |
d930faee | 78 | |
fc331460 AP |
79 | if (card->sleep_cookie_vbase) { |
80 | cookie_addr = (u32 *)card->sleep_cookie_vbase; | |
d930faee AK |
81 | dev_dbg(adapter->dev, "info: ACCESS_HW: sleep cookie=0x%x\n", |
82 | *cookie_addr); | |
83 | if (*cookie_addr == FW_AWAKE_COOKIE) | |
84 | return true; | |
85 | } | |
86 | ||
87 | return false; | |
88 | } | |
89 | ||
3266d732 | 90 | #ifdef CONFIG_PM_SLEEP |
fcca8d5a BZ |
91 | /* |
92 | * Kernel needs to suspend all functions separately. Therefore all | |
93 | * registered functions must have drivers with suspend and resume | |
94 | * methods. Failing that the kernel simply removes the whole card. | |
95 | * | |
96 | * If already not suspended, this function allocates and sends a host | |
97 | * sleep activate request to the firmware and turns off the traffic. | |
98 | */ | |
3266d732 | 99 | static int mwifiex_pcie_suspend(struct device *dev) |
fcca8d5a BZ |
100 | { |
101 | struct mwifiex_adapter *adapter; | |
102 | struct pcie_service_card *card; | |
103 | int hs_actived; | |
3266d732 | 104 | struct pci_dev *pdev = to_pci_dev(dev); |
fcca8d5a BZ |
105 | |
106 | if (pdev) { | |
b2a31204 | 107 | card = pci_get_drvdata(pdev); |
fcca8d5a BZ |
108 | if (!card || !card->adapter) { |
109 | pr_err("Card or adapter structure is not valid\n"); | |
110 | return 0; | |
111 | } | |
112 | } else { | |
113 | pr_err("PCIE device is not specified\n"); | |
114 | return 0; | |
115 | } | |
116 | ||
117 | adapter = card->adapter; | |
118 | ||
119 | hs_actived = mwifiex_enable_hs(adapter); | |
120 | ||
121 | /* Indicate device suspended */ | |
122 | adapter->is_suspended = true; | |
c0dbba66 | 123 | adapter->hs_enabling = false; |
fcca8d5a BZ |
124 | |
125 | return 0; | |
126 | } | |
127 | ||
128 | /* | |
129 | * Kernel needs to suspend all functions separately. Therefore all | |
130 | * registered functions must have drivers with suspend and resume | |
131 | * methods. Failing that the kernel simply removes the whole card. | |
132 | * | |
133 | * If already not resumed, this function turns on the traffic and | |
134 | * sends a host sleep cancel request to the firmware. | |
135 | */ | |
3266d732 | 136 | static int mwifiex_pcie_resume(struct device *dev) |
fcca8d5a BZ |
137 | { |
138 | struct mwifiex_adapter *adapter; | |
139 | struct pcie_service_card *card; | |
3266d732 | 140 | struct pci_dev *pdev = to_pci_dev(dev); |
fcca8d5a BZ |
141 | |
142 | if (pdev) { | |
b2a31204 | 143 | card = pci_get_drvdata(pdev); |
fcca8d5a BZ |
144 | if (!card || !card->adapter) { |
145 | pr_err("Card or adapter structure is not valid\n"); | |
146 | return 0; | |
147 | } | |
148 | } else { | |
149 | pr_err("PCIE device is not specified\n"); | |
150 | return 0; | |
151 | } | |
152 | ||
153 | adapter = card->adapter; | |
154 | ||
155 | if (!adapter->is_suspended) { | |
156 | dev_warn(adapter->dev, "Device already resumed\n"); | |
157 | return 0; | |
158 | } | |
159 | ||
160 | adapter->is_suspended = false; | |
161 | ||
162 | mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA), | |
163 | MWIFIEX_ASYNC_CMD); | |
164 | ||
165 | return 0; | |
166 | } | |
8509e820 | 167 | #endif |
fcca8d5a | 168 | |
d930faee AK |
169 | /* |
170 | * This function probes an mwifiex device and registers it. It allocates | |
171 | * the card structure, enables PCIE function number and initiates the | |
172 | * device registration and initialization procedure by adding a logical | |
173 | * interface. | |
174 | */ | |
175 | static int mwifiex_pcie_probe(struct pci_dev *pdev, | |
176 | const struct pci_device_id *ent) | |
177 | { | |
178 | struct pcie_service_card *card; | |
179 | ||
180 | pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n", | |
f57c1edc | 181 | pdev->vendor, pdev->device, pdev->revision); |
d930faee AK |
182 | |
183 | card = kzalloc(sizeof(struct pcie_service_card), GFP_KERNEL); | |
e404decb | 184 | if (!card) |
d930faee | 185 | return -ENOMEM; |
d930faee AK |
186 | |
187 | card->dev = pdev; | |
188 | ||
dd04e6ac AP |
189 | if (ent->driver_data) { |
190 | struct mwifiex_pcie_device *data = (void *)ent->driver_data; | |
191 | card->pcie.firmware = data->firmware; | |
192 | card->pcie.reg = data->reg; | |
193 | card->pcie.blksz_fw_dl = data->blksz_fw_dl; | |
828cf222 | 194 | card->pcie.tx_buf_size = data->tx_buf_size; |
dd04e6ac AP |
195 | } |
196 | ||
d930faee AK |
197 | if (mwifiex_add_card(card, &add_remove_card_sem, &pcie_ops, |
198 | MWIFIEX_PCIE)) { | |
199 | pr_err("%s failed\n", __func__); | |
200 | kfree(card); | |
201 | return -1; | |
202 | } | |
203 | ||
204 | return 0; | |
205 | } | |
206 | ||
207 | /* | |
208 | * This function removes the interface and frees up the card structure. | |
209 | */ | |
210 | static void mwifiex_pcie_remove(struct pci_dev *pdev) | |
211 | { | |
212 | struct pcie_service_card *card; | |
213 | struct mwifiex_adapter *adapter; | |
f57c1edc | 214 | struct mwifiex_private *priv; |
d930faee AK |
215 | |
216 | card = pci_get_drvdata(pdev); | |
217 | if (!card) | |
218 | return; | |
219 | ||
220 | adapter = card->adapter; | |
221 | if (!adapter || !adapter->priv_num) | |
222 | return; | |
223 | ||
59a4cc25 AK |
224 | /* In case driver is removed when asynchronous FW load is in progress */ |
225 | wait_for_completion(&adapter->fw_load); | |
226 | ||
d930faee | 227 | if (user_rmmod) { |
3266d732 | 228 | #ifdef CONFIG_PM_SLEEP |
d930faee | 229 | if (adapter->is_suspended) |
3266d732 | 230 | mwifiex_pcie_resume(&pdev->dev); |
d930faee AK |
231 | #endif |
232 | ||
848819f4 | 233 | mwifiex_deauthenticate_all(adapter); |
d930faee | 234 | |
f57c1edc | 235 | priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY); |
d930faee | 236 | |
f57c1edc YAP |
237 | mwifiex_disable_auto_ds(priv); |
238 | ||
239 | mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN); | |
d930faee AK |
240 | } |
241 | ||
242 | mwifiex_remove_card(card->adapter, &add_remove_card_sem); | |
d930faee AK |
243 | } |
244 | ||
43ba6b9f AK |
245 | static void mwifiex_pcie_shutdown(struct pci_dev *pdev) |
246 | { | |
247 | user_rmmod = 1; | |
248 | mwifiex_pcie_remove(pdev); | |
249 | ||
250 | return; | |
251 | } | |
252 | ||
d930faee AK |
253 | static DEFINE_PCI_DEVICE_TABLE(mwifiex_ids) = { |
254 | { | |
255 | PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8766P, | |
256 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
dd04e6ac | 257 | .driver_data = (unsigned long) &mwifiex_pcie8766, |
d930faee | 258 | }, |
ca8f2112 AP |
259 | { |
260 | PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8897, | |
261 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
262 | .driver_data = (unsigned long) &mwifiex_pcie8897, | |
263 | }, | |
d930faee AK |
264 | {}, |
265 | }; | |
266 | ||
267 | MODULE_DEVICE_TABLE(pci, mwifiex_ids); | |
268 | ||
3266d732 SK |
269 | #ifdef CONFIG_PM_SLEEP |
270 | /* Power Management Hooks */ | |
271 | static SIMPLE_DEV_PM_OPS(mwifiex_pcie_pm_ops, mwifiex_pcie_suspend, | |
272 | mwifiex_pcie_resume); | |
273 | #endif | |
274 | ||
d930faee AK |
275 | /* PCI Device Driver */ |
276 | static struct pci_driver __refdata mwifiex_pcie = { | |
277 | .name = "mwifiex_pcie", | |
278 | .id_table = mwifiex_ids, | |
279 | .probe = mwifiex_pcie_probe, | |
280 | .remove = mwifiex_pcie_remove, | |
3266d732 SK |
281 | #ifdef CONFIG_PM_SLEEP |
282 | .driver = { | |
283 | .pm = &mwifiex_pcie_pm_ops, | |
284 | }, | |
d930faee | 285 | #endif |
43ba6b9f | 286 | .shutdown = mwifiex_pcie_shutdown, |
d930faee AK |
287 | }; |
288 | ||
289 | /* | |
290 | * This function writes data into PCIE card register. | |
291 | */ | |
292 | static int mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data) | |
293 | { | |
294 | struct pcie_service_card *card = adapter->card; | |
295 | ||
296 | iowrite32(data, card->pci_mmap1 + reg); | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
301 | /* | |
302 | * This function reads data from PCIE card register. | |
303 | */ | |
304 | static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data) | |
305 | { | |
306 | struct pcie_service_card *card = adapter->card; | |
307 | ||
308 | *data = ioread32(card->pci_mmap1 + reg); | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
313 | /* | |
c0880a29 | 314 | * This function adds delay loop to ensure FW is awake before proceeding. |
d930faee | 315 | */ |
c0880a29 | 316 | static void mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter *adapter) |
d930faee AK |
317 | { |
318 | int i = 0; | |
319 | ||
c0880a29 | 320 | while (mwifiex_pcie_ok_to_access_hw(adapter)) { |
d930faee | 321 | i++; |
e7891ba2 | 322 | usleep_range(10, 20); |
d930faee | 323 | /* 50ms max wait */ |
3e7a4ff7 | 324 | if (i == 5000) |
d930faee AK |
325 | break; |
326 | } | |
327 | ||
c0880a29 AP |
328 | return; |
329 | } | |
330 | ||
c4bc980f AP |
331 | static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter, |
332 | u32 max_delay_loop_cnt) | |
333 | { | |
334 | struct pcie_service_card *card = adapter->card; | |
335 | u8 *buffer; | |
336 | u32 sleep_cookie, count; | |
337 | ||
338 | for (count = 0; count < max_delay_loop_cnt; count++) { | |
339 | buffer = card->cmdrsp_buf->data - INTF_HEADER_LEN; | |
340 | sleep_cookie = *(u32 *)buffer; | |
341 | ||
342 | if (sleep_cookie == MWIFIEX_DEF_SLEEP_COOKIE) { | |
343 | dev_dbg(adapter->dev, | |
344 | "sleep cookie found at count %d\n", count); | |
345 | break; | |
346 | } | |
347 | usleep_range(20, 30); | |
348 | } | |
349 | ||
350 | if (count >= max_delay_loop_cnt) | |
351 | dev_dbg(adapter->dev, | |
352 | "max count reached while accessing sleep cookie\n"); | |
353 | } | |
354 | ||
c0880a29 AP |
355 | /* This function wakes up the card by reading fw_status register. */ |
356 | static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter) | |
357 | { | |
358 | u32 fw_status; | |
359 | struct pcie_service_card *card = adapter->card; | |
360 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; | |
361 | ||
d930faee AK |
362 | dev_dbg(adapter->dev, "event: Wakeup device...\n"); |
363 | ||
c0880a29 AP |
364 | if (reg->sleep_cookie) |
365 | mwifiex_pcie_dev_wakeup_delay(adapter); | |
366 | ||
367 | /* Reading fw_status register will wakeup device */ | |
368 | if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status)) { | |
369 | dev_warn(adapter->dev, "Reading fw_status register failed\n"); | |
d930faee AK |
370 | return -1; |
371 | } | |
372 | ||
c0880a29 AP |
373 | if (reg->sleep_cookie) { |
374 | mwifiex_pcie_dev_wakeup_delay(adapter); | |
375 | dev_dbg(adapter->dev, "PCIE wakeup: Setting PS_STATE_AWAKE\n"); | |
376 | adapter->ps_state = PS_STATE_AWAKE; | |
377 | } | |
d930faee AK |
378 | |
379 | return 0; | |
380 | } | |
381 | ||
382 | /* | |
383 | * This function is called after the card has woken up. | |
384 | * | |
385 | * The card configuration register is reset. | |
386 | */ | |
387 | static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter) | |
388 | { | |
389 | dev_dbg(adapter->dev, "cmd: Wakeup device completed\n"); | |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
394 | /* | |
395 | * This function disables the host interrupt. | |
396 | * | |
397 | * The host interrupt mask is read, the disable bit is reset and | |
398 | * written back to the card host interrupt mask register. | |
399 | */ | |
400 | static int mwifiex_pcie_disable_host_int(struct mwifiex_adapter *adapter) | |
401 | { | |
402 | if (mwifiex_pcie_ok_to_access_hw(adapter)) { | |
403 | if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK, | |
404 | 0x00000000)) { | |
405 | dev_warn(adapter->dev, "Disable host interrupt failed\n"); | |
406 | return -1; | |
407 | } | |
408 | } | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
413 | /* | |
414 | * This function enables the host interrupt. | |
415 | * | |
416 | * The host interrupt enable mask is written to the card | |
417 | * host interrupt mask register. | |
418 | */ | |
419 | static int mwifiex_pcie_enable_host_int(struct mwifiex_adapter *adapter) | |
420 | { | |
421 | if (mwifiex_pcie_ok_to_access_hw(adapter)) { | |
422 | /* Simply write the mask to the register */ | |
423 | if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK, | |
424 | HOST_INTR_MASK)) { | |
425 | dev_warn(adapter->dev, "Enable host interrupt failed\n"); | |
426 | return -1; | |
427 | } | |
428 | } | |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
433 | /* | |
0732484b AP |
434 | * This function initializes TX buffer ring descriptors |
435 | */ | |
436 | static int mwifiex_init_txq_ring(struct mwifiex_adapter *adapter) | |
437 | { | |
438 | struct pcie_service_card *card = adapter->card; | |
ca8f2112 | 439 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
0732484b | 440 | struct mwifiex_pcie_buf_desc *desc; |
ca8f2112 | 441 | struct mwifiex_pfu_buf_desc *desc2; |
0732484b AP |
442 | int i; |
443 | ||
444 | for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { | |
445 | card->tx_buf_list[i] = NULL; | |
ca8f2112 AP |
446 | if (reg->pfu_enabled) { |
447 | card->txbd_ring[i] = (void *)card->txbd_ring_vbase + | |
448 | (sizeof(*desc2) * i); | |
449 | desc2 = card->txbd_ring[i]; | |
450 | memset(desc2, 0, sizeof(*desc2)); | |
451 | } else { | |
452 | card->txbd_ring[i] = (void *)card->txbd_ring_vbase + | |
453 | (sizeof(*desc) * i); | |
454 | desc = card->txbd_ring[i]; | |
455 | memset(desc, 0, sizeof(*desc)); | |
456 | } | |
0732484b AP |
457 | } |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
462 | /* This function initializes RX buffer ring descriptors. Each SKB is allocated | |
463 | * here and after mapping PCI memory, its physical address is assigned to | |
464 | * PCIE Rx buffer descriptor's physical address. | |
465 | */ | |
466 | static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter) | |
467 | { | |
468 | struct pcie_service_card *card = adapter->card; | |
ca8f2112 | 469 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
0732484b AP |
470 | struct sk_buff *skb; |
471 | struct mwifiex_pcie_buf_desc *desc; | |
ca8f2112 | 472 | struct mwifiex_pfu_buf_desc *desc2; |
0732484b AP |
473 | dma_addr_t buf_pa; |
474 | int i; | |
475 | ||
476 | for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { | |
477 | /* Allocate skb here so that firmware can DMA data from it */ | |
478 | skb = dev_alloc_skb(MWIFIEX_RX_DATA_BUF_SIZE); | |
479 | if (!skb) { | |
480 | dev_err(adapter->dev, | |
481 | "Unable to allocate skb for RX ring.\n"); | |
482 | kfree(card->rxbd_ring_vbase); | |
483 | return -ENOMEM; | |
484 | } | |
485 | ||
486 | if (mwifiex_map_pci_memory(adapter, skb, | |
487 | MWIFIEX_RX_DATA_BUF_SIZE, | |
488 | PCI_DMA_FROMDEVICE)) | |
489 | return -1; | |
490 | ||
dbccc92b | 491 | buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); |
0732484b AP |
492 | |
493 | dev_dbg(adapter->dev, | |
494 | "info: RX ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n", | |
495 | skb, skb->len, skb->data, (u32)buf_pa, | |
496 | (u32)((u64)buf_pa >> 32)); | |
497 | ||
498 | card->rx_buf_list[i] = skb; | |
ca8f2112 AP |
499 | if (reg->pfu_enabled) { |
500 | card->rxbd_ring[i] = (void *)card->rxbd_ring_vbase + | |
501 | (sizeof(*desc2) * i); | |
502 | desc2 = card->rxbd_ring[i]; | |
503 | desc2->paddr = buf_pa; | |
504 | desc2->len = (u16)skb->len; | |
505 | desc2->frag_len = (u16)skb->len; | |
506 | desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop; | |
507 | desc2->offset = 0; | |
508 | } else { | |
509 | card->rxbd_ring[i] = (void *)(card->rxbd_ring_vbase + | |
510 | (sizeof(*desc) * i)); | |
511 | desc = card->rxbd_ring[i]; | |
512 | desc->paddr = buf_pa; | |
513 | desc->len = (u16)skb->len; | |
514 | desc->flags = 0; | |
515 | } | |
0732484b AP |
516 | } |
517 | ||
518 | return 0; | |
519 | } | |
520 | ||
521 | /* This function initializes event buffer ring descriptors. Each SKB is | |
522 | * allocated here and after mapping PCI memory, its physical address is assigned | |
523 | * to PCIE Rx buffer descriptor's physical address | |
524 | */ | |
525 | static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter) | |
526 | { | |
527 | struct pcie_service_card *card = adapter->card; | |
e05dc3e9 | 528 | struct mwifiex_evt_buf_desc *desc; |
0732484b AP |
529 | struct sk_buff *skb; |
530 | dma_addr_t buf_pa; | |
531 | int i; | |
532 | ||
533 | for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { | |
534 | /* Allocate skb here so that firmware can DMA data from it */ | |
535 | skb = dev_alloc_skb(MAX_EVENT_SIZE); | |
536 | if (!skb) { | |
537 | dev_err(adapter->dev, | |
538 | "Unable to allocate skb for EVENT buf.\n"); | |
539 | kfree(card->evtbd_ring_vbase); | |
540 | return -ENOMEM; | |
541 | } | |
542 | skb_put(skb, MAX_EVENT_SIZE); | |
543 | ||
544 | if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE, | |
545 | PCI_DMA_FROMDEVICE)) | |
546 | return -1; | |
547 | ||
dbccc92b | 548 | buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); |
0732484b AP |
549 | |
550 | dev_dbg(adapter->dev, | |
551 | "info: EVT ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n", | |
552 | skb, skb->len, skb->data, (u32)buf_pa, | |
553 | (u32)((u64)buf_pa >> 32)); | |
554 | ||
555 | card->evt_buf_list[i] = skb; | |
556 | card->evtbd_ring[i] = (void *)(card->evtbd_ring_vbase + | |
557 | (sizeof(*desc) * i)); | |
0732484b AP |
558 | desc = card->evtbd_ring[i]; |
559 | desc->paddr = buf_pa; | |
560 | desc->len = (u16)skb->len; | |
561 | desc->flags = 0; | |
562 | } | |
563 | ||
564 | return 0; | |
565 | } | |
566 | ||
567 | /* This function cleans up TX buffer rings. If any of the buffer list has valid | |
568 | * SKB address, associated SKB is freed. | |
569 | */ | |
570 | static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter) | |
571 | { | |
572 | struct pcie_service_card *card = adapter->card; | |
ca8f2112 | 573 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
0732484b AP |
574 | struct sk_buff *skb; |
575 | struct mwifiex_pcie_buf_desc *desc; | |
ca8f2112 | 576 | struct mwifiex_pfu_buf_desc *desc2; |
0732484b AP |
577 | int i; |
578 | ||
579 | for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { | |
ca8f2112 AP |
580 | if (reg->pfu_enabled) { |
581 | desc2 = card->txbd_ring[i]; | |
582 | if (card->tx_buf_list[i]) { | |
583 | skb = card->tx_buf_list[i]; | |
dbccc92b AD |
584 | mwifiex_unmap_pci_memory(adapter, skb, |
585 | PCI_DMA_TODEVICE); | |
ca8f2112 AP |
586 | dev_kfree_skb_any(skb); |
587 | } | |
588 | memset(desc2, 0, sizeof(*desc2)); | |
589 | } else { | |
590 | desc = card->txbd_ring[i]; | |
591 | if (card->tx_buf_list[i]) { | |
592 | skb = card->tx_buf_list[i]; | |
dbccc92b AD |
593 | mwifiex_unmap_pci_memory(adapter, skb, |
594 | PCI_DMA_TODEVICE); | |
ca8f2112 AP |
595 | dev_kfree_skb_any(skb); |
596 | } | |
597 | memset(desc, 0, sizeof(*desc)); | |
0732484b AP |
598 | } |
599 | card->tx_buf_list[i] = NULL; | |
0732484b AP |
600 | } |
601 | ||
602 | return; | |
603 | } | |
604 | ||
605 | /* This function cleans up RX buffer rings. If any of the buffer list has valid | |
606 | * SKB address, associated SKB is freed. | |
607 | */ | |
608 | static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter) | |
609 | { | |
610 | struct pcie_service_card *card = adapter->card; | |
ca8f2112 | 611 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
0732484b | 612 | struct mwifiex_pcie_buf_desc *desc; |
ca8f2112 | 613 | struct mwifiex_pfu_buf_desc *desc2; |
0732484b AP |
614 | struct sk_buff *skb; |
615 | int i; | |
616 | ||
617 | for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { | |
ca8f2112 AP |
618 | if (reg->pfu_enabled) { |
619 | desc2 = card->rxbd_ring[i]; | |
620 | if (card->rx_buf_list[i]) { | |
621 | skb = card->rx_buf_list[i]; | |
dbccc92b AD |
622 | mwifiex_unmap_pci_memory(adapter, skb, |
623 | PCI_DMA_FROMDEVICE); | |
ca8f2112 AP |
624 | dev_kfree_skb_any(skb); |
625 | } | |
626 | memset(desc2, 0, sizeof(*desc2)); | |
627 | } else { | |
628 | desc = card->rxbd_ring[i]; | |
629 | if (card->rx_buf_list[i]) { | |
630 | skb = card->rx_buf_list[i]; | |
dbccc92b AD |
631 | mwifiex_unmap_pci_memory(adapter, skb, |
632 | PCI_DMA_FROMDEVICE); | |
ca8f2112 AP |
633 | dev_kfree_skb_any(skb); |
634 | } | |
635 | memset(desc, 0, sizeof(*desc)); | |
0732484b | 636 | } |
ca8f2112 | 637 | card->rx_buf_list[i] = NULL; |
0732484b AP |
638 | } |
639 | ||
640 | return; | |
641 | } | |
642 | ||
643 | /* This function cleans up event buffer rings. If any of the buffer list has | |
644 | * valid SKB address, associated SKB is freed. | |
645 | */ | |
646 | static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter) | |
647 | { | |
648 | struct pcie_service_card *card = adapter->card; | |
e05dc3e9 | 649 | struct mwifiex_evt_buf_desc *desc; |
0732484b AP |
650 | struct sk_buff *skb; |
651 | int i; | |
652 | ||
653 | for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { | |
654 | desc = card->evtbd_ring[i]; | |
655 | if (card->evt_buf_list[i]) { | |
656 | skb = card->evt_buf_list[i]; | |
dbccc92b AD |
657 | mwifiex_unmap_pci_memory(adapter, skb, |
658 | PCI_DMA_FROMDEVICE); | |
0732484b AP |
659 | dev_kfree_skb_any(skb); |
660 | } | |
661 | card->evt_buf_list[i] = NULL; | |
662 | memset(desc, 0, sizeof(*desc)); | |
663 | } | |
664 | ||
665 | return; | |
666 | } | |
667 | ||
668 | /* This function creates buffer descriptor ring for TX | |
d930faee AK |
669 | */ |
670 | static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter) | |
671 | { | |
672 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 673 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
674 | |
675 | /* | |
676 | * driver maintaines the write pointer and firmware maintaines the read | |
677 | * pointer. The write pointer starts at 0 (zero) while the read pointer | |
678 | * starts at zero with rollover bit set | |
679 | */ | |
680 | card->txbd_wrptr = 0; | |
ca8f2112 AP |
681 | |
682 | if (reg->pfu_enabled) | |
683 | card->txbd_rdptr = 0; | |
684 | else | |
685 | card->txbd_rdptr |= reg->tx_rollover_ind; | |
d930faee AK |
686 | |
687 | /* allocate shared memory for the BD ring and divide the same in to | |
688 | several descriptors */ | |
ca8f2112 AP |
689 | if (reg->pfu_enabled) |
690 | card->txbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) * | |
691 | MWIFIEX_MAX_TXRX_BD; | |
692 | else | |
693 | card->txbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) * | |
694 | MWIFIEX_MAX_TXRX_BD; | |
695 | ||
d930faee | 696 | dev_dbg(adapter->dev, "info: txbd_ring: Allocating %d bytes\n", |
f57c1edc | 697 | card->txbd_ring_size); |
fc331460 AP |
698 | card->txbd_ring_vbase = pci_alloc_consistent(card->dev, |
699 | card->txbd_ring_size, | |
700 | &card->txbd_ring_pbase); | |
d930faee | 701 | if (!card->txbd_ring_vbase) { |
fc331460 AP |
702 | dev_err(adapter->dev, |
703 | "allocate consistent memory (%d bytes) failed!\n", | |
704 | card->txbd_ring_size); | |
8c53e42d | 705 | return -ENOMEM; |
d930faee | 706 | } |
f57c1edc YAP |
707 | dev_dbg(adapter->dev, |
708 | "info: txbd_ring - base: %p, pbase: %#x:%x, len: %x\n", | |
fc331460 | 709 | card->txbd_ring_vbase, (unsigned int)card->txbd_ring_pbase, |
f57c1edc | 710 | (u32)((u64)card->txbd_ring_pbase >> 32), card->txbd_ring_size); |
d930faee | 711 | |
0732484b | 712 | return mwifiex_init_txq_ring(adapter); |
d930faee AK |
713 | } |
714 | ||
715 | static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter) | |
716 | { | |
717 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 718 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee | 719 | |
0732484b | 720 | mwifiex_cleanup_txq_ring(adapter); |
d930faee | 721 | |
fc331460 AP |
722 | if (card->txbd_ring_vbase) |
723 | pci_free_consistent(card->dev, card->txbd_ring_size, | |
724 | card->txbd_ring_vbase, | |
725 | card->txbd_ring_pbase); | |
d930faee AK |
726 | card->txbd_ring_size = 0; |
727 | card->txbd_wrptr = 0; | |
dd04e6ac | 728 | card->txbd_rdptr = 0 | reg->tx_rollover_ind; |
d930faee | 729 | card->txbd_ring_vbase = NULL; |
fc331460 | 730 | card->txbd_ring_pbase = 0; |
d930faee AK |
731 | |
732 | return 0; | |
733 | } | |
734 | ||
735 | /* | |
736 | * This function creates buffer descriptor ring for RX | |
737 | */ | |
738 | static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter) | |
739 | { | |
740 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 741 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
742 | |
743 | /* | |
744 | * driver maintaines the read pointer and firmware maintaines the write | |
745 | * pointer. The write pointer starts at 0 (zero) while the read pointer | |
746 | * starts at zero with rollover bit set | |
747 | */ | |
748 | card->rxbd_wrptr = 0; | |
dd04e6ac | 749 | card->rxbd_rdptr = reg->rx_rollover_ind; |
d930faee | 750 | |
ca8f2112 AP |
751 | if (reg->pfu_enabled) |
752 | card->rxbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) * | |
753 | MWIFIEX_MAX_TXRX_BD; | |
754 | else | |
755 | card->rxbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) * | |
756 | MWIFIEX_MAX_TXRX_BD; | |
757 | ||
d930faee | 758 | dev_dbg(adapter->dev, "info: rxbd_ring: Allocating %d bytes\n", |
f57c1edc | 759 | card->rxbd_ring_size); |
fc331460 AP |
760 | card->rxbd_ring_vbase = pci_alloc_consistent(card->dev, |
761 | card->rxbd_ring_size, | |
762 | &card->rxbd_ring_pbase); | |
d930faee | 763 | if (!card->rxbd_ring_vbase) { |
fc331460 AP |
764 | dev_err(adapter->dev, |
765 | "allocate consistent memory (%d bytes) failed!\n", | |
766 | card->rxbd_ring_size); | |
8c53e42d | 767 | return -ENOMEM; |
d930faee | 768 | } |
d930faee | 769 | |
f57c1edc YAP |
770 | dev_dbg(adapter->dev, |
771 | "info: rxbd_ring - base: %p, pbase: %#x:%x, len: %#x\n", | |
772 | card->rxbd_ring_vbase, (u32)card->rxbd_ring_pbase, | |
773 | (u32)((u64)card->rxbd_ring_pbase >> 32), | |
774 | card->rxbd_ring_size); | |
d930faee | 775 | |
0732484b | 776 | return mwifiex_init_rxq_ring(adapter); |
d930faee AK |
777 | } |
778 | ||
779 | /* | |
780 | * This function deletes Buffer descriptor ring for RX | |
781 | */ | |
782 | static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter) | |
783 | { | |
784 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 785 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee | 786 | |
0732484b | 787 | mwifiex_cleanup_rxq_ring(adapter); |
d930faee | 788 | |
fc331460 AP |
789 | if (card->rxbd_ring_vbase) |
790 | pci_free_consistent(card->dev, card->rxbd_ring_size, | |
791 | card->rxbd_ring_vbase, | |
792 | card->rxbd_ring_pbase); | |
d930faee AK |
793 | card->rxbd_ring_size = 0; |
794 | card->rxbd_wrptr = 0; | |
dd04e6ac | 795 | card->rxbd_rdptr = 0 | reg->rx_rollover_ind; |
d930faee | 796 | card->rxbd_ring_vbase = NULL; |
fc331460 | 797 | card->rxbd_ring_pbase = 0; |
d930faee AK |
798 | |
799 | return 0; | |
800 | } | |
801 | ||
802 | /* | |
803 | * This function creates buffer descriptor ring for Events | |
804 | */ | |
805 | static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter) | |
806 | { | |
807 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 808 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
809 | |
810 | /* | |
811 | * driver maintaines the read pointer and firmware maintaines the write | |
812 | * pointer. The write pointer starts at 0 (zero) while the read pointer | |
813 | * starts at zero with rollover bit set | |
814 | */ | |
815 | card->evtbd_wrptr = 0; | |
dd04e6ac | 816 | card->evtbd_rdptr = reg->evt_rollover_ind; |
d930faee | 817 | |
e05dc3e9 | 818 | card->evtbd_ring_size = sizeof(struct mwifiex_evt_buf_desc) * |
ca8f2112 AP |
819 | MWIFIEX_MAX_EVT_BD; |
820 | ||
d930faee | 821 | dev_dbg(adapter->dev, "info: evtbd_ring: Allocating %d bytes\n", |
f57c1edc | 822 | card->evtbd_ring_size); |
fc331460 AP |
823 | card->evtbd_ring_vbase = pci_alloc_consistent(card->dev, |
824 | card->evtbd_ring_size, | |
825 | &card->evtbd_ring_pbase); | |
d930faee | 826 | if (!card->evtbd_ring_vbase) { |
f57c1edc | 827 | dev_err(adapter->dev, |
fc331460 AP |
828 | "allocate consistent memory (%d bytes) failed!\n", |
829 | card->evtbd_ring_size); | |
8c53e42d | 830 | return -ENOMEM; |
d930faee | 831 | } |
d930faee | 832 | |
f57c1edc YAP |
833 | dev_dbg(adapter->dev, |
834 | "info: CMDRSP/EVT bd_ring - base: %p pbase: %#x:%x len: %#x\n", | |
835 | card->evtbd_ring_vbase, (u32)card->evtbd_ring_pbase, | |
836 | (u32)((u64)card->evtbd_ring_pbase >> 32), | |
837 | card->evtbd_ring_size); | |
d930faee | 838 | |
0732484b | 839 | return mwifiex_pcie_init_evt_ring(adapter); |
d930faee AK |
840 | } |
841 | ||
842 | /* | |
843 | * This function deletes Buffer descriptor ring for Events | |
844 | */ | |
845 | static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter) | |
846 | { | |
847 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 848 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee | 849 | |
0732484b | 850 | mwifiex_cleanup_evt_ring(adapter); |
d930faee | 851 | |
fc331460 AP |
852 | if (card->evtbd_ring_vbase) |
853 | pci_free_consistent(card->dev, card->evtbd_ring_size, | |
854 | card->evtbd_ring_vbase, | |
855 | card->evtbd_ring_pbase); | |
d930faee | 856 | card->evtbd_wrptr = 0; |
dd04e6ac | 857 | card->evtbd_rdptr = 0 | reg->evt_rollover_ind; |
d930faee AK |
858 | card->evtbd_ring_size = 0; |
859 | card->evtbd_ring_vbase = NULL; | |
fc331460 | 860 | card->evtbd_ring_pbase = 0; |
d930faee AK |
861 | |
862 | return 0; | |
863 | } | |
864 | ||
865 | /* | |
866 | * This function allocates a buffer for CMDRSP | |
867 | */ | |
868 | static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter) | |
869 | { | |
870 | struct pcie_service_card *card = adapter->card; | |
871 | struct sk_buff *skb; | |
872 | ||
873 | /* Allocate memory for receiving command response data */ | |
874 | skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE); | |
875 | if (!skb) { | |
f57c1edc YAP |
876 | dev_err(adapter->dev, |
877 | "Unable to allocate skb for command response data.\n"); | |
d930faee AK |
878 | return -ENOMEM; |
879 | } | |
d930faee | 880 | skb_put(skb, MWIFIEX_UPLD_SIZE); |
fc331460 AP |
881 | if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, |
882 | PCI_DMA_FROMDEVICE)) | |
883 | return -1; | |
d930faee | 884 | |
fc331460 | 885 | card->cmdrsp_buf = skb; |
d930faee AK |
886 | |
887 | return 0; | |
888 | } | |
889 | ||
890 | /* | |
891 | * This function deletes a buffer for CMDRSP | |
892 | */ | |
893 | static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter) | |
894 | { | |
895 | struct pcie_service_card *card; | |
896 | ||
897 | if (!adapter) | |
898 | return 0; | |
899 | ||
900 | card = adapter->card; | |
901 | ||
fc331460 | 902 | if (card && card->cmdrsp_buf) { |
dbccc92b AD |
903 | mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf, |
904 | PCI_DMA_FROMDEVICE); | |
d930faee | 905 | dev_kfree_skb_any(card->cmdrsp_buf); |
fc331460 | 906 | } |
d930faee | 907 | |
fc331460 | 908 | if (card && card->cmd_buf) { |
dbccc92b AD |
909 | mwifiex_unmap_pci_memory(adapter, card->cmd_buf, |
910 | PCI_DMA_TODEVICE); | |
fc331460 | 911 | } |
d930faee AK |
912 | return 0; |
913 | } | |
914 | ||
915 | /* | |
916 | * This function allocates a buffer for sleep cookie | |
917 | */ | |
918 | static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter) | |
919 | { | |
d930faee AK |
920 | struct pcie_service_card *card = adapter->card; |
921 | ||
fc331460 AP |
922 | card->sleep_cookie_vbase = pci_alloc_consistent(card->dev, sizeof(u32), |
923 | &card->sleep_cookie_pbase); | |
924 | if (!card->sleep_cookie_vbase) { | |
925 | dev_err(adapter->dev, "pci_alloc_consistent failed!\n"); | |
d930faee AK |
926 | return -ENOMEM; |
927 | } | |
d930faee | 928 | /* Init val of Sleep Cookie */ |
fc331460 | 929 | *(u32 *)card->sleep_cookie_vbase = FW_AWAKE_COOKIE; |
d930faee AK |
930 | |
931 | dev_dbg(adapter->dev, "alloc_scook: sleep cookie=0x%x\n", | |
fc331460 | 932 | *((u32 *)card->sleep_cookie_vbase)); |
d930faee AK |
933 | |
934 | return 0; | |
935 | } | |
936 | ||
937 | /* | |
938 | * This function deletes buffer for sleep cookie | |
939 | */ | |
940 | static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter) | |
941 | { | |
942 | struct pcie_service_card *card; | |
943 | ||
944 | if (!adapter) | |
945 | return 0; | |
946 | ||
947 | card = adapter->card; | |
948 | ||
fc331460 AP |
949 | if (card && card->sleep_cookie_vbase) { |
950 | pci_free_consistent(card->dev, sizeof(u32), | |
951 | card->sleep_cookie_vbase, | |
952 | card->sleep_cookie_pbase); | |
953 | card->sleep_cookie_vbase = NULL; | |
d930faee AK |
954 | } |
955 | ||
956 | return 0; | |
957 | } | |
958 | ||
fbd7e7ac AP |
959 | /* This function flushes the TX buffer descriptor ring |
960 | * This function defined as handler is also called while cleaning TXRX | |
961 | * during disconnect/ bss stop. | |
962 | */ | |
963 | static int mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter *adapter) | |
964 | { | |
965 | struct pcie_service_card *card = adapter->card; | |
fbd7e7ac | 966 | |
48f4d916 | 967 | if (!mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) { |
fbd7e7ac AP |
968 | card->txbd_flush = 1; |
969 | /* write pointer already set at last send | |
970 | * send dnld-rdy intr again, wait for completion. | |
971 | */ | |
972 | if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, | |
973 | CPU_INTR_DNLD_RDY)) { | |
974 | dev_err(adapter->dev, | |
975 | "failed to assert dnld-rdy interrupt.\n"); | |
976 | return -1; | |
977 | } | |
978 | } | |
979 | return 0; | |
980 | } | |
981 | ||
d930faee | 982 | /* |
e7f767a7 | 983 | * This function unmaps and frees downloaded data buffer |
d930faee | 984 | */ |
e7f767a7 | 985 | static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter) |
d930faee | 986 | { |
e7f767a7 | 987 | struct sk_buff *skb; |
ca8f2112 | 988 | u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0; |
e05dc3e9 | 989 | struct mwifiex_pcie_buf_desc *desc; |
ca8f2112 | 990 | struct mwifiex_pfu_buf_desc *desc2; |
d930faee | 991 | struct pcie_service_card *card = adapter->card; |
dd04e6ac | 992 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
993 | |
994 | if (!mwifiex_pcie_ok_to_access_hw(adapter)) | |
995 | mwifiex_pm_wakeup_card(adapter); | |
996 | ||
997 | /* Read the TX ring read pointer set by firmware */ | |
dd04e6ac | 998 | if (mwifiex_read_reg(adapter, reg->tx_rdptr, &rdptr)) { |
f57c1edc | 999 | dev_err(adapter->dev, |
dd04e6ac | 1000 | "SEND COMP: failed to read reg->tx_rdptr\n"); |
d930faee AK |
1001 | return -1; |
1002 | } | |
1003 | ||
e7f767a7 AP |
1004 | dev_dbg(adapter->dev, "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n", |
1005 | card->txbd_rdptr, rdptr); | |
d930faee | 1006 | |
ca8f2112 | 1007 | num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr; |
e7f767a7 | 1008 | /* free from previous txbd_rdptr to current txbd_rdptr */ |
dd04e6ac AP |
1009 | while (((card->txbd_rdptr & reg->tx_mask) != |
1010 | (rdptr & reg->tx_mask)) || | |
1011 | ((card->txbd_rdptr & reg->tx_rollover_ind) != | |
1012 | (rdptr & reg->tx_rollover_ind))) { | |
ca8f2112 AP |
1013 | wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >> |
1014 | reg->tx_start_ptr; | |
e7f767a7 AP |
1015 | |
1016 | skb = card->tx_buf_list[wrdoneidx]; | |
dbccc92b | 1017 | |
e7f767a7 AP |
1018 | if (skb) { |
1019 | dev_dbg(adapter->dev, | |
1020 | "SEND COMP: Detach skb %p at txbd_rdidx=%d\n", | |
1021 | skb, wrdoneidx); | |
dbccc92b AD |
1022 | mwifiex_unmap_pci_memory(adapter, skb, |
1023 | PCI_DMA_TODEVICE); | |
e7f767a7 AP |
1024 | |
1025 | unmap_count++; | |
1026 | ||
1027 | if (card->txbd_flush) | |
1028 | mwifiex_write_data_complete(adapter, skb, 0, | |
1029 | -1); | |
1030 | else | |
1031 | mwifiex_write_data_complete(adapter, skb, 0, 0); | |
1032 | } | |
1033 | ||
1034 | card->tx_buf_list[wrdoneidx] = NULL; | |
ca8f2112 AP |
1035 | |
1036 | if (reg->pfu_enabled) { | |
45d18c56 | 1037 | desc2 = card->txbd_ring[wrdoneidx]; |
ca8f2112 AP |
1038 | memset(desc2, 0, sizeof(*desc2)); |
1039 | } else { | |
1040 | desc = card->txbd_ring[wrdoneidx]; | |
1041 | memset(desc, 0, sizeof(*desc)); | |
1042 | } | |
1043 | switch (card->dev->device) { | |
1044 | case PCIE_DEVICE_ID_MARVELL_88W8766P: | |
1045 | card->txbd_rdptr++; | |
1046 | break; | |
1047 | case PCIE_DEVICE_ID_MARVELL_88W8897: | |
1048 | card->txbd_rdptr += reg->ring_tx_start_ptr; | |
1049 | break; | |
1050 | } | |
1051 | ||
e7f767a7 | 1052 | |
dd04e6ac | 1053 | if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs) |
e7f767a7 | 1054 | card->txbd_rdptr = ((card->txbd_rdptr & |
dd04e6ac AP |
1055 | reg->tx_rollover_ind) ^ |
1056 | reg->tx_rollover_ind); | |
e7f767a7 AP |
1057 | } |
1058 | ||
1059 | if (unmap_count) | |
1060 | adapter->data_sent = false; | |
1061 | ||
1062 | if (card->txbd_flush) { | |
3d482038 | 1063 | if (mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) |
e7f767a7 AP |
1064 | card->txbd_flush = 0; |
1065 | else | |
1066 | mwifiex_clean_pcie_ring_buf(adapter); | |
1067 | } | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
1072 | /* This function sends data buffer to device. First 4 bytes of payload | |
1073 | * are filled with payload length and payload type. Then this payload | |
1074 | * is mapped to PCI device memory. Tx ring pointers are advanced accordingly. | |
1075 | * Download ready interrupt to FW is deffered if Tx ring is not full and | |
1076 | * additional payload can be accomodated. | |
1077 | */ | |
1078 | static int | |
1079 | mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb, | |
1080 | struct mwifiex_tx_param *tx_param) | |
1081 | { | |
1082 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1083 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
ca8f2112 | 1084 | u32 wrindx, num_tx_buffs, rx_val; |
e7f767a7 AP |
1085 | int ret; |
1086 | dma_addr_t buf_pa; | |
9931078e BZ |
1087 | struct mwifiex_pcie_buf_desc *desc = NULL; |
1088 | struct mwifiex_pfu_buf_desc *desc2 = NULL; | |
e7f767a7 AP |
1089 | __le16 *tmp; |
1090 | ||
1091 | if (!(skb->data && skb->len)) { | |
1092 | dev_err(adapter->dev, "%s(): invalid parameter <%p, %#x>\n", | |
1093 | __func__, skb->data, skb->len); | |
1094 | return -1; | |
1095 | } | |
1096 | ||
1097 | if (!mwifiex_pcie_ok_to_access_hw(adapter)) | |
1098 | mwifiex_pm_wakeup_card(adapter); | |
1099 | ||
ca8f2112 | 1100 | num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr; |
e7f767a7 AP |
1101 | dev_dbg(adapter->dev, "info: SEND DATA: <Rd: %#x, Wr: %#x>\n", |
1102 | card->txbd_rdptr, card->txbd_wrptr); | |
1103 | if (mwifiex_pcie_txbd_not_full(card)) { | |
d930faee AK |
1104 | u8 *payload; |
1105 | ||
1106 | adapter->data_sent = true; | |
e7f767a7 | 1107 | payload = skb->data; |
d930faee AK |
1108 | tmp = (__le16 *)&payload[0]; |
1109 | *tmp = cpu_to_le16((u16)skb->len); | |
1110 | tmp = (__le16 *)&payload[2]; | |
1111 | *tmp = cpu_to_le16(MWIFIEX_TYPE_DATA); | |
e7f767a7 | 1112 | |
dbccc92b | 1113 | if (mwifiex_map_pci_memory(adapter, skb, skb->len, |
e7f767a7 AP |
1114 | PCI_DMA_TODEVICE)) |
1115 | return -1; | |
1116 | ||
ca8f2112 | 1117 | wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr; |
dbccc92b | 1118 | buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); |
e7f767a7 | 1119 | card->tx_buf_list[wrindx] = skb; |
d930faee | 1120 | |
ca8f2112 | 1121 | if (reg->pfu_enabled) { |
45d18c56 | 1122 | desc2 = card->txbd_ring[wrindx]; |
ca8f2112 AP |
1123 | desc2->paddr = buf_pa; |
1124 | desc2->len = (u16)skb->len; | |
1125 | desc2->frag_len = (u16)skb->len; | |
1126 | desc2->offset = 0; | |
1127 | desc2->flags = MWIFIEX_BD_FLAG_FIRST_DESC | | |
1128 | MWIFIEX_BD_FLAG_LAST_DESC; | |
1129 | } else { | |
1130 | desc = card->txbd_ring[wrindx]; | |
1131 | desc->paddr = buf_pa; | |
1132 | desc->len = (u16)skb->len; | |
1133 | desc->flags = MWIFIEX_BD_FLAG_FIRST_DESC | | |
1134 | MWIFIEX_BD_FLAG_LAST_DESC; | |
1135 | } | |
1136 | ||
1137 | switch (card->dev->device) { | |
1138 | case PCIE_DEVICE_ID_MARVELL_88W8766P: | |
1139 | card->txbd_wrptr++; | |
1140 | break; | |
1141 | case PCIE_DEVICE_ID_MARVELL_88W8897: | |
1142 | card->txbd_wrptr += reg->ring_tx_start_ptr; | |
1143 | break; | |
1144 | } | |
1145 | ||
1146 | if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs) | |
d930faee | 1147 | card->txbd_wrptr = ((card->txbd_wrptr & |
dd04e6ac AP |
1148 | reg->tx_rollover_ind) ^ |
1149 | reg->tx_rollover_ind); | |
d930faee | 1150 | |
ca8f2112 | 1151 | rx_val = card->rxbd_rdptr & reg->rx_wrap_mask; |
dd04e6ac AP |
1152 | /* Write the TX ring write pointer in to reg->tx_wrptr */ |
1153 | if (mwifiex_write_reg(adapter, reg->tx_wrptr, | |
ca8f2112 | 1154 | card->txbd_wrptr | rx_val)) { |
f57c1edc | 1155 | dev_err(adapter->dev, |
dd04e6ac | 1156 | "SEND DATA: failed to write reg->tx_wrptr\n"); |
e7f767a7 AP |
1157 | ret = -1; |
1158 | goto done_unmap; | |
d930faee | 1159 | } |
e7f767a7 AP |
1160 | if ((mwifiex_pcie_txbd_not_full(card)) && |
1161 | tx_param->next_pkt_len) { | |
1162 | /* have more packets and TxBD still can hold more */ | |
1163 | dev_dbg(adapter->dev, | |
1164 | "SEND DATA: delay dnld-rdy interrupt.\n"); | |
1165 | adapter->data_sent = false; | |
1166 | } else { | |
1167 | /* Send the TX ready interrupt */ | |
1168 | if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, | |
1169 | CPU_INTR_DNLD_RDY)) { | |
1170 | dev_err(adapter->dev, | |
1171 | "SEND DATA: failed to assert dnld-rdy interrupt.\n"); | |
1172 | ret = -1; | |
1173 | goto done_unmap; | |
1174 | } | |
d930faee AK |
1175 | } |
1176 | dev_dbg(adapter->dev, "info: SEND DATA: Updated <Rd: %#x, Wr: " | |
f57c1edc | 1177 | "%#x> and sent packet to firmware successfully\n", |
e7f767a7 | 1178 | card->txbd_rdptr, card->txbd_wrptr); |
d930faee | 1179 | } else { |
f57c1edc YAP |
1180 | dev_dbg(adapter->dev, |
1181 | "info: TX Ring full, can't send packets to fw\n"); | |
d930faee AK |
1182 | adapter->data_sent = true; |
1183 | /* Send the TX ready interrupt */ | |
1184 | if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, | |
1185 | CPU_INTR_DNLD_RDY)) | |
f57c1edc YAP |
1186 | dev_err(adapter->dev, |
1187 | "SEND DATA: failed to assert door-bell intr\n"); | |
d930faee AK |
1188 | return -EBUSY; |
1189 | } | |
1190 | ||
e7f767a7 AP |
1191 | return -EINPROGRESS; |
1192 | done_unmap: | |
dbccc92b | 1193 | mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); |
e7f767a7 | 1194 | card->tx_buf_list[wrindx] = NULL; |
ca8f2112 AP |
1195 | if (reg->pfu_enabled) |
1196 | memset(desc2, 0, sizeof(*desc2)); | |
1197 | else | |
1198 | memset(desc, 0, sizeof(*desc)); | |
1199 | ||
e7f767a7 | 1200 | return ret; |
d930faee AK |
1201 | } |
1202 | ||
1203 | /* | |
1204 | * This function handles received buffer ring and | |
1205 | * dispatches packets to upper | |
1206 | */ | |
1207 | static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter) | |
1208 | { | |
1209 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1210 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
ca8f2112 | 1211 | u32 wrptr, rd_index, tx_val; |
e7f767a7 | 1212 | dma_addr_t buf_pa; |
d930faee AK |
1213 | int ret = 0; |
1214 | struct sk_buff *skb_tmp = NULL; | |
e05dc3e9 | 1215 | struct mwifiex_pcie_buf_desc *desc; |
ca8f2112 | 1216 | struct mwifiex_pfu_buf_desc *desc2; |
d930faee | 1217 | |
e7f767a7 AP |
1218 | if (!mwifiex_pcie_ok_to_access_hw(adapter)) |
1219 | mwifiex_pm_wakeup_card(adapter); | |
1220 | ||
d930faee | 1221 | /* Read the RX ring Write pointer set by firmware */ |
dd04e6ac | 1222 | if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) { |
f57c1edc | 1223 | dev_err(adapter->dev, |
dd04e6ac | 1224 | "RECV DATA: failed to read reg->rx_wrptr\n"); |
d930faee AK |
1225 | ret = -1; |
1226 | goto done; | |
1227 | } | |
e7f767a7 | 1228 | card->rxbd_wrptr = wrptr; |
d930faee | 1229 | |
dd04e6ac AP |
1230 | while (((wrptr & reg->rx_mask) != |
1231 | (card->rxbd_rdptr & reg->rx_mask)) || | |
1232 | ((wrptr & reg->rx_rollover_ind) == | |
1233 | (card->rxbd_rdptr & reg->rx_rollover_ind))) { | |
d930faee AK |
1234 | struct sk_buff *skb_data; |
1235 | u16 rx_len; | |
e7f767a7 | 1236 | __le16 pkt_len; |
d930faee | 1237 | |
dd04e6ac | 1238 | rd_index = card->rxbd_rdptr & reg->rx_mask; |
d930faee AK |
1239 | skb_data = card->rx_buf_list[rd_index]; |
1240 | ||
bb8e6a1e AK |
1241 | /* If skb allocation was failed earlier for Rx packet, |
1242 | * rx_buf_list[rd_index] would have been left with a NULL. | |
1243 | */ | |
1244 | if (!skb_data) | |
1245 | return -ENOMEM; | |
1246 | ||
dbccc92b | 1247 | mwifiex_unmap_pci_memory(adapter, skb_data, PCI_DMA_FROMDEVICE); |
e7f767a7 AP |
1248 | card->rx_buf_list[rd_index] = NULL; |
1249 | ||
d930faee | 1250 | /* Get data length from interface header - |
e7f767a7 AP |
1251 | * first 2 bytes for len, next 2 bytes is for type |
1252 | */ | |
1253 | pkt_len = *((__le16 *)skb_data->data); | |
1254 | rx_len = le16_to_cpu(pkt_len); | |
1255 | skb_put(skb_data, rx_len); | |
f57c1edc YAP |
1256 | dev_dbg(adapter->dev, |
1257 | "info: RECV DATA: Rd=%#x, Wr=%#x, Len=%d\n", | |
1258 | card->rxbd_rdptr, wrptr, rx_len); | |
e7f767a7 AP |
1259 | skb_pull(skb_data, INTF_HEADER_LEN); |
1260 | mwifiex_handle_rx_packet(adapter, skb_data); | |
1261 | ||
1262 | skb_tmp = dev_alloc_skb(MWIFIEX_RX_DATA_BUF_SIZE); | |
d930faee | 1263 | if (!skb_tmp) { |
e7f767a7 AP |
1264 | dev_err(adapter->dev, |
1265 | "Unable to allocate skb.\n"); | |
1266 | return -ENOMEM; | |
d930faee AK |
1267 | } |
1268 | ||
e7f767a7 AP |
1269 | if (mwifiex_map_pci_memory(adapter, skb_tmp, |
1270 | MWIFIEX_RX_DATA_BUF_SIZE, | |
1271 | PCI_DMA_FROMDEVICE)) | |
1272 | return -1; | |
1273 | ||
dbccc92b | 1274 | buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp); |
e7f767a7 AP |
1275 | |
1276 | dev_dbg(adapter->dev, | |
1277 | "RECV DATA: Attach new sk_buff %p at rxbd_rdidx=%d\n", | |
1278 | skb_tmp, rd_index); | |
1279 | card->rx_buf_list[rd_index] = skb_tmp; | |
ca8f2112 AP |
1280 | |
1281 | if (reg->pfu_enabled) { | |
45d18c56 | 1282 | desc2 = card->rxbd_ring[rd_index]; |
ca8f2112 AP |
1283 | desc2->paddr = buf_pa; |
1284 | desc2->len = skb_tmp->len; | |
1285 | desc2->frag_len = skb_tmp->len; | |
1286 | desc2->offset = 0; | |
1287 | desc2->flags = reg->ring_flag_sop | reg->ring_flag_eop; | |
1288 | } else { | |
1289 | desc = card->rxbd_ring[rd_index]; | |
1290 | desc->paddr = buf_pa; | |
1291 | desc->len = skb_tmp->len; | |
1292 | desc->flags = 0; | |
1293 | } | |
d930faee | 1294 | |
dd04e6ac | 1295 | if ((++card->rxbd_rdptr & reg->rx_mask) == |
d930faee AK |
1296 | MWIFIEX_MAX_TXRX_BD) { |
1297 | card->rxbd_rdptr = ((card->rxbd_rdptr & | |
dd04e6ac AP |
1298 | reg->rx_rollover_ind) ^ |
1299 | reg->rx_rollover_ind); | |
d930faee AK |
1300 | } |
1301 | dev_dbg(adapter->dev, "info: RECV DATA: <Rd: %#x, Wr: %#x>\n", | |
f57c1edc | 1302 | card->rxbd_rdptr, wrptr); |
d930faee | 1303 | |
ca8f2112 | 1304 | tx_val = card->txbd_wrptr & reg->tx_wrap_mask; |
dd04e6ac AP |
1305 | /* Write the RX ring read pointer in to reg->rx_rdptr */ |
1306 | if (mwifiex_write_reg(adapter, reg->rx_rdptr, | |
ca8f2112 | 1307 | card->rxbd_rdptr | tx_val)) { |
f57c1edc | 1308 | dev_err(adapter->dev, |
dd04e6ac | 1309 | "RECV DATA: failed to write reg->rx_rdptr\n"); |
d930faee AK |
1310 | ret = -1; |
1311 | goto done; | |
1312 | } | |
1313 | ||
1314 | /* Read the RX ring Write pointer set by firmware */ | |
dd04e6ac | 1315 | if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) { |
f57c1edc | 1316 | dev_err(adapter->dev, |
dd04e6ac | 1317 | "RECV DATA: failed to read reg->rx_wrptr\n"); |
d930faee AK |
1318 | ret = -1; |
1319 | goto done; | |
1320 | } | |
f57c1edc YAP |
1321 | dev_dbg(adapter->dev, |
1322 | "info: RECV DATA: Rcvd packet from fw successfully\n"); | |
e7f767a7 | 1323 | card->rxbd_wrptr = wrptr; |
d930faee AK |
1324 | } |
1325 | ||
1326 | done: | |
d930faee AK |
1327 | return ret; |
1328 | } | |
1329 | ||
1330 | /* | |
1331 | * This function downloads the boot command to device | |
1332 | */ | |
1333 | static int | |
1334 | mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) | |
1335 | { | |
fc331460 AP |
1336 | dma_addr_t buf_pa; |
1337 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1338 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee | 1339 | |
fc331460 | 1340 | if (!(skb->data && skb->len)) { |
f57c1edc | 1341 | dev_err(adapter->dev, |
fc331460 AP |
1342 | "Invalid parameter in %s <%p. len %d>\n", |
1343 | __func__, skb->data, skb->len); | |
d930faee AK |
1344 | return -1; |
1345 | } | |
1346 | ||
fc331460 AP |
1347 | if (mwifiex_map_pci_memory(adapter, skb, skb->len , PCI_DMA_TODEVICE)) |
1348 | return -1; | |
1349 | ||
dbccc92b | 1350 | buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); |
fc331460 | 1351 | |
dd04e6ac AP |
1352 | /* Write the lower 32bits of the physical address to low command |
1353 | * address scratch register | |
1354 | */ | |
1355 | if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)buf_pa)) { | |
f57c1edc YAP |
1356 | dev_err(adapter->dev, |
1357 | "%s: failed to write download command to boot code.\n", | |
1358 | __func__); | |
dbccc92b | 1359 | mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); |
d930faee AK |
1360 | return -1; |
1361 | } | |
1362 | ||
dd04e6ac AP |
1363 | /* Write the upper 32bits of the physical address to high command |
1364 | * address scratch register | |
1365 | */ | |
1366 | if (mwifiex_write_reg(adapter, reg->cmd_addr_hi, | |
fc331460 | 1367 | (u32)((u64)buf_pa >> 32))) { |
f57c1edc YAP |
1368 | dev_err(adapter->dev, |
1369 | "%s: failed to write download command to boot code.\n", | |
1370 | __func__); | |
dbccc92b | 1371 | mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); |
d930faee AK |
1372 | return -1; |
1373 | } | |
1374 | ||
dd04e6ac AP |
1375 | /* Write the command length to cmd_size scratch register */ |
1376 | if (mwifiex_write_reg(adapter, reg->cmd_size, skb->len)) { | |
f57c1edc | 1377 | dev_err(adapter->dev, |
dd04e6ac | 1378 | "%s: failed to write command len to cmd_size scratch reg\n", |
f57c1edc | 1379 | __func__); |
dbccc92b | 1380 | mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); |
d930faee AK |
1381 | return -1; |
1382 | } | |
1383 | ||
1384 | /* Ring the door bell */ | |
1385 | if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, | |
1386 | CPU_INTR_DOOR_BELL)) { | |
f57c1edc YAP |
1387 | dev_err(adapter->dev, |
1388 | "%s: failed to assert door-bell intr\n", __func__); | |
dbccc92b | 1389 | mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); |
d930faee AK |
1390 | return -1; |
1391 | } | |
1392 | ||
1393 | return 0; | |
1394 | } | |
1395 | ||
c6d1d87a AP |
1396 | /* This function init rx port in firmware which in turn enables to receive data |
1397 | * from device before transmitting any packet. | |
1398 | */ | |
1399 | static int mwifiex_pcie_init_fw_port(struct mwifiex_adapter *adapter) | |
1400 | { | |
1401 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1402 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
ca8f2112 | 1403 | int tx_wrap = card->txbd_wrptr & reg->tx_wrap_mask; |
c6d1d87a | 1404 | |
dd04e6ac | 1405 | /* Write the RX ring read pointer in to reg->rx_rdptr */ |
ca8f2112 AP |
1406 | if (mwifiex_write_reg(adapter, reg->rx_rdptr, card->rxbd_rdptr | |
1407 | tx_wrap)) { | |
c6d1d87a | 1408 | dev_err(adapter->dev, |
dd04e6ac | 1409 | "RECV DATA: failed to write reg->rx_rdptr\n"); |
c6d1d87a AP |
1410 | return -1; |
1411 | } | |
1412 | return 0; | |
1413 | } | |
1414 | ||
1415 | /* This function downloads commands to the device | |
d930faee AK |
1416 | */ |
1417 | static int | |
1418 | mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) | |
1419 | { | |
1420 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1421 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee | 1422 | int ret = 0; |
fc331460 AP |
1423 | dma_addr_t cmd_buf_pa, cmdrsp_buf_pa; |
1424 | u8 *payload = (u8 *)skb->data; | |
d930faee AK |
1425 | |
1426 | if (!(skb->data && skb->len)) { | |
1427 | dev_err(adapter->dev, "Invalid parameter in %s <%p, %#x>\n", | |
f57c1edc | 1428 | __func__, skb->data, skb->len); |
d930faee AK |
1429 | return -1; |
1430 | } | |
1431 | ||
1432 | /* Make sure a command response buffer is available */ | |
1433 | if (!card->cmdrsp_buf) { | |
f57c1edc YAP |
1434 | dev_err(adapter->dev, |
1435 | "No response buffer available, send command failed\n"); | |
d930faee AK |
1436 | return -EBUSY; |
1437 | } | |
1438 | ||
fc331460 AP |
1439 | if (!mwifiex_pcie_ok_to_access_hw(adapter)) |
1440 | mwifiex_pm_wakeup_card(adapter); | |
d930faee AK |
1441 | |
1442 | adapter->cmd_sent = true; | |
fc331460 AP |
1443 | |
1444 | *(__le16 *)&payload[0] = cpu_to_le16((u16)skb->len); | |
1445 | *(__le16 *)&payload[2] = cpu_to_le16(MWIFIEX_TYPE_CMD); | |
1446 | ||
1447 | if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE)) | |
1448 | return -1; | |
1449 | ||
1450 | card->cmd_buf = skb; | |
d930faee AK |
1451 | |
1452 | /* To send a command, the driver will: | |
1453 | 1. Write the 64bit physical address of the data buffer to | |
dd04e6ac | 1454 | cmd response address low + cmd response address high |
d930faee AK |
1455 | 2. Ring the door bell (i.e. set the door bell interrupt) |
1456 | ||
1457 | In response to door bell interrupt, the firmware will perform | |
1458 | the DMA of the command packet (first header to obtain the total | |
1459 | length and then rest of the command). | |
1460 | */ | |
1461 | ||
1462 | if (card->cmdrsp_buf) { | |
dbccc92b | 1463 | cmdrsp_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmdrsp_buf); |
d930faee AK |
1464 | /* Write the lower 32bits of the cmdrsp buffer physical |
1465 | address */ | |
dd04e6ac | 1466 | if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, |
fc331460 | 1467 | (u32)cmdrsp_buf_pa)) { |
f57c1edc YAP |
1468 | dev_err(adapter->dev, |
1469 | "Failed to write download cmd to boot code.\n"); | |
d930faee AK |
1470 | ret = -1; |
1471 | goto done; | |
1472 | } | |
1473 | /* Write the upper 32bits of the cmdrsp buffer physical | |
1474 | address */ | |
dd04e6ac | 1475 | if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, |
fc331460 | 1476 | (u32)((u64)cmdrsp_buf_pa >> 32))) { |
f57c1edc YAP |
1477 | dev_err(adapter->dev, |
1478 | "Failed to write download cmd to boot code.\n"); | |
d930faee AK |
1479 | ret = -1; |
1480 | goto done; | |
1481 | } | |
1482 | } | |
1483 | ||
dbccc92b | 1484 | cmd_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmd_buf); |
dd04e6ac AP |
1485 | /* Write the lower 32bits of the physical address to reg->cmd_addr_lo */ |
1486 | if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, | |
1487 | (u32)cmd_buf_pa)) { | |
f57c1edc YAP |
1488 | dev_err(adapter->dev, |
1489 | "Failed to write download cmd to boot code.\n"); | |
d930faee AK |
1490 | ret = -1; |
1491 | goto done; | |
1492 | } | |
dd04e6ac AP |
1493 | /* Write the upper 32bits of the physical address to reg->cmd_addr_hi */ |
1494 | if (mwifiex_write_reg(adapter, reg->cmd_addr_hi, | |
fc331460 | 1495 | (u32)((u64)cmd_buf_pa >> 32))) { |
f57c1edc YAP |
1496 | dev_err(adapter->dev, |
1497 | "Failed to write download cmd to boot code.\n"); | |
d930faee AK |
1498 | ret = -1; |
1499 | goto done; | |
1500 | } | |
1501 | ||
dd04e6ac AP |
1502 | /* Write the command length to reg->cmd_size */ |
1503 | if (mwifiex_write_reg(adapter, reg->cmd_size, | |
1504 | card->cmd_buf->len)) { | |
f57c1edc | 1505 | dev_err(adapter->dev, |
dd04e6ac | 1506 | "Failed to write cmd len to reg->cmd_size\n"); |
d930faee AK |
1507 | ret = -1; |
1508 | goto done; | |
1509 | } | |
1510 | ||
1511 | /* Ring the door bell */ | |
1512 | if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, | |
1513 | CPU_INTR_DOOR_BELL)) { | |
f57c1edc YAP |
1514 | dev_err(adapter->dev, |
1515 | "Failed to assert door-bell intr\n"); | |
d930faee AK |
1516 | ret = -1; |
1517 | goto done; | |
1518 | } | |
1519 | ||
1520 | done: | |
1521 | if (ret) | |
1522 | adapter->cmd_sent = false; | |
1523 | ||
1524 | return 0; | |
1525 | } | |
1526 | ||
1527 | /* | |
1528 | * This function handles command complete interrupt | |
1529 | */ | |
1530 | static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) | |
1531 | { | |
1532 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1533 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
f57c1edc | 1534 | struct sk_buff *skb = card->cmdrsp_buf; |
d930faee | 1535 | int count = 0; |
fc331460 AP |
1536 | u16 rx_len; |
1537 | __le16 pkt_len; | |
d930faee AK |
1538 | |
1539 | dev_dbg(adapter->dev, "info: Rx CMD Response\n"); | |
1540 | ||
dbccc92b | 1541 | mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_FROMDEVICE); |
fc331460 | 1542 | |
189b3299 AD |
1543 | /* Unmap the command as a response has been received. */ |
1544 | if (card->cmd_buf) { | |
1545 | mwifiex_unmap_pci_memory(adapter, card->cmd_buf, | |
1546 | PCI_DMA_TODEVICE); | |
1547 | card->cmd_buf = NULL; | |
1548 | } | |
1549 | ||
fc331460 AP |
1550 | pkt_len = *((__le16 *)skb->data); |
1551 | rx_len = le16_to_cpu(pkt_len); | |
1552 | skb_trim(skb, rx_len); | |
1553 | skb_pull(skb, INTF_HEADER_LEN); | |
1554 | ||
d930faee | 1555 | if (!adapter->curr_cmd) { |
d930faee | 1556 | if (adapter->ps_state == PS_STATE_SLEEP_CFM) { |
f57c1edc YAP |
1557 | mwifiex_process_sleep_confirm_resp(adapter, skb->data, |
1558 | skb->len); | |
1c97560f AK |
1559 | mwifiex_pcie_enable_host_int(adapter); |
1560 | if (mwifiex_write_reg(adapter, | |
1561 | PCIE_CPU_INT_EVENT, | |
1562 | CPU_INTR_SLEEP_CFM_DONE)) { | |
1563 | dev_warn(adapter->dev, | |
1564 | "Write register failed\n"); | |
1565 | return -1; | |
1566 | } | |
c4bc980f AP |
1567 | mwifiex_delay_for_sleep_cookie(adapter, |
1568 | MWIFIEX_MAX_DELAY_COUNT); | |
52301a81 AP |
1569 | while (reg->sleep_cookie && (count++ < 10) && |
1570 | mwifiex_pcie_ok_to_access_hw(adapter)) | |
e7891ba2 | 1571 | usleep_range(50, 60); |
d930faee | 1572 | } else { |
f57c1edc YAP |
1573 | dev_err(adapter->dev, |
1574 | "There is no command but got cmdrsp\n"); | |
d930faee | 1575 | } |
f57c1edc YAP |
1576 | memcpy(adapter->upld_buf, skb->data, |
1577 | min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len)); | |
0f49d64c | 1578 | skb_push(skb, INTF_HEADER_LEN); |
fc331460 AP |
1579 | if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, |
1580 | PCI_DMA_FROMDEVICE)) | |
1581 | return -1; | |
d930faee | 1582 | } else if (mwifiex_pcie_ok_to_access_hw(adapter)) { |
f57c1edc | 1583 | adapter->curr_cmd->resp_skb = skb; |
d930faee AK |
1584 | adapter->cmd_resp_received = true; |
1585 | /* Take the pointer and set it to CMD node and will | |
1586 | return in the response complete callback */ | |
1587 | card->cmdrsp_buf = NULL; | |
1588 | ||
1589 | /* Clear the cmd-rsp buffer address in scratch registers. This | |
1590 | will prevent firmware from writing to the same response | |
1591 | buffer again. */ | |
dd04e6ac | 1592 | if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0)) { |
f57c1edc YAP |
1593 | dev_err(adapter->dev, |
1594 | "cmd_done: failed to clear cmd_rsp_addr_lo\n"); | |
d930faee AK |
1595 | return -1; |
1596 | } | |
1597 | /* Write the upper 32bits of the cmdrsp buffer physical | |
1598 | address */ | |
dd04e6ac | 1599 | if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0)) { |
f57c1edc YAP |
1600 | dev_err(adapter->dev, |
1601 | "cmd_done: failed to clear cmd_rsp_addr_hi\n"); | |
d930faee AK |
1602 | return -1; |
1603 | } | |
1604 | } | |
1605 | ||
1606 | return 0; | |
1607 | } | |
1608 | ||
1609 | /* | |
1610 | * Command Response processing complete handler | |
1611 | */ | |
1612 | static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter, | |
1613 | struct sk_buff *skb) | |
1614 | { | |
1615 | struct pcie_service_card *card = adapter->card; | |
1616 | ||
1617 | if (skb) { | |
1618 | card->cmdrsp_buf = skb; | |
1619 | skb_push(card->cmdrsp_buf, INTF_HEADER_LEN); | |
fc331460 AP |
1620 | if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, |
1621 | PCI_DMA_FROMDEVICE)) | |
1622 | return -1; | |
1623 | } | |
1624 | ||
d930faee AK |
1625 | return 0; |
1626 | } | |
1627 | ||
1628 | /* | |
1629 | * This function handles firmware event ready interrupt | |
1630 | */ | |
1631 | static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter) | |
1632 | { | |
1633 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1634 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
1635 | u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK; |
1636 | u32 wrptr, event; | |
e05dc3e9 | 1637 | struct mwifiex_evt_buf_desc *desc; |
fc331460 AP |
1638 | |
1639 | if (!mwifiex_pcie_ok_to_access_hw(adapter)) | |
1640 | mwifiex_pm_wakeup_card(adapter); | |
d930faee AK |
1641 | |
1642 | if (adapter->event_received) { | |
f57c1edc YAP |
1643 | dev_dbg(adapter->dev, "info: Event being processed, " |
1644 | "do not process this interrupt just yet\n"); | |
d930faee AK |
1645 | return 0; |
1646 | } | |
1647 | ||
1648 | if (rdptr >= MWIFIEX_MAX_EVT_BD) { | |
1649 | dev_dbg(adapter->dev, "info: Invalid read pointer...\n"); | |
1650 | return -1; | |
1651 | } | |
1652 | ||
1653 | /* Read the event ring write pointer set by firmware */ | |
dd04e6ac | 1654 | if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) { |
f57c1edc | 1655 | dev_err(adapter->dev, |
dd04e6ac | 1656 | "EventReady: failed to read reg->evt_wrptr\n"); |
d930faee AK |
1657 | return -1; |
1658 | } | |
1659 | ||
1660 | dev_dbg(adapter->dev, "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>", | |
f57c1edc YAP |
1661 | card->evtbd_rdptr, wrptr); |
1662 | if (((wrptr & MWIFIEX_EVTBD_MASK) != (card->evtbd_rdptr | |
1663 | & MWIFIEX_EVTBD_MASK)) || | |
dd04e6ac AP |
1664 | ((wrptr & reg->evt_rollover_ind) == |
1665 | (card->evtbd_rdptr & reg->evt_rollover_ind))) { | |
d930faee AK |
1666 | struct sk_buff *skb_cmd; |
1667 | __le16 data_len = 0; | |
1668 | u16 evt_len; | |
1669 | ||
1670 | dev_dbg(adapter->dev, "info: Read Index: %d\n", rdptr); | |
1671 | skb_cmd = card->evt_buf_list[rdptr]; | |
dbccc92b | 1672 | mwifiex_unmap_pci_memory(adapter, skb_cmd, PCI_DMA_FROMDEVICE); |
fc331460 | 1673 | |
d930faee AK |
1674 | /* Take the pointer and set it to event pointer in adapter |
1675 | and will return back after event handling callback */ | |
1676 | card->evt_buf_list[rdptr] = NULL; | |
e05dc3e9 AP |
1677 | desc = card->evtbd_ring[rdptr]; |
1678 | memset(desc, 0, sizeof(*desc)); | |
d930faee AK |
1679 | |
1680 | event = *(u32 *) &skb_cmd->data[INTF_HEADER_LEN]; | |
1681 | adapter->event_cause = event; | |
1682 | /* The first 4bytes will be the event transfer header | |
1683 | len is 2 bytes followed by type which is 2 bytes */ | |
1684 | memcpy(&data_len, skb_cmd->data, sizeof(__le16)); | |
1685 | evt_len = le16_to_cpu(data_len); | |
1686 | ||
1687 | skb_pull(skb_cmd, INTF_HEADER_LEN); | |
1688 | dev_dbg(adapter->dev, "info: Event length: %d\n", evt_len); | |
1689 | ||
1690 | if ((evt_len > 0) && (evt_len < MAX_EVENT_SIZE)) | |
1691 | memcpy(adapter->event_body, skb_cmd->data + | |
1692 | MWIFIEX_EVENT_HEADER_LEN, evt_len - | |
1693 | MWIFIEX_EVENT_HEADER_LEN); | |
1694 | ||
1695 | adapter->event_received = true; | |
1696 | adapter->event_skb = skb_cmd; | |
1697 | ||
1698 | /* Do not update the event read pointer here, wait till the | |
1699 | buffer is released. This is just to make things simpler, | |
1700 | we need to find a better method of managing these buffers. | |
1701 | */ | |
1702 | } | |
1703 | ||
1704 | return 0; | |
1705 | } | |
1706 | ||
1707 | /* | |
1708 | * Event processing complete handler | |
1709 | */ | |
1710 | static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter, | |
1711 | struct sk_buff *skb) | |
1712 | { | |
1713 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1714 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
1715 | int ret = 0; |
1716 | u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK; | |
1717 | u32 wrptr; | |
e05dc3e9 | 1718 | struct mwifiex_evt_buf_desc *desc; |
d930faee AK |
1719 | |
1720 | if (!skb) | |
1721 | return 0; | |
1722 | ||
1eb54c8a | 1723 | if (rdptr >= MWIFIEX_MAX_EVT_BD) { |
d930faee | 1724 | dev_err(adapter->dev, "event_complete: Invalid rdptr 0x%x\n", |
f57c1edc | 1725 | rdptr); |
8c53e42d | 1726 | return -EINVAL; |
1eb54c8a | 1727 | } |
d930faee AK |
1728 | |
1729 | /* Read the event ring write pointer set by firmware */ | |
dd04e6ac | 1730 | if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) { |
f57c1edc | 1731 | dev_err(adapter->dev, |
dd04e6ac | 1732 | "event_complete: failed to read reg->evt_wrptr\n"); |
8c53e42d | 1733 | return -1; |
d930faee AK |
1734 | } |
1735 | ||
1736 | if (!card->evt_buf_list[rdptr]) { | |
1737 | skb_push(skb, INTF_HEADER_LEN); | |
fc331460 AP |
1738 | if (mwifiex_map_pci_memory(adapter, skb, |
1739 | MAX_EVENT_SIZE, | |
1740 | PCI_DMA_FROMDEVICE)) | |
1741 | return -1; | |
d930faee | 1742 | card->evt_buf_list[rdptr] = skb; |
e05dc3e9 | 1743 | desc = card->evtbd_ring[rdptr]; |
dbccc92b | 1744 | desc->paddr = MWIFIEX_SKB_DMA_ADDR(skb); |
e05dc3e9 AP |
1745 | desc->len = (u16)skb->len; |
1746 | desc->flags = 0; | |
d930faee AK |
1747 | skb = NULL; |
1748 | } else { | |
f57c1edc YAP |
1749 | dev_dbg(adapter->dev, |
1750 | "info: ERROR: buf still valid at index %d, <%p, %p>\n", | |
1751 | rdptr, card->evt_buf_list[rdptr], skb); | |
d930faee AK |
1752 | } |
1753 | ||
1754 | if ((++card->evtbd_rdptr & MWIFIEX_EVTBD_MASK) == MWIFIEX_MAX_EVT_BD) { | |
1755 | card->evtbd_rdptr = ((card->evtbd_rdptr & | |
dd04e6ac AP |
1756 | reg->evt_rollover_ind) ^ |
1757 | reg->evt_rollover_ind); | |
d930faee AK |
1758 | } |
1759 | ||
1760 | dev_dbg(adapter->dev, "info: Updated <Rd: 0x%x, Wr: 0x%x>", | |
f57c1edc | 1761 | card->evtbd_rdptr, wrptr); |
d930faee | 1762 | |
dd04e6ac AP |
1763 | /* Write the event ring read pointer in to reg->evt_rdptr */ |
1764 | if (mwifiex_write_reg(adapter, reg->evt_rdptr, | |
1765 | card->evtbd_rdptr)) { | |
f57c1edc | 1766 | dev_err(adapter->dev, |
dd04e6ac | 1767 | "event_complete: failed to read reg->evt_rdptr\n"); |
8c53e42d | 1768 | return -1; |
d930faee AK |
1769 | } |
1770 | ||
d930faee AK |
1771 | dev_dbg(adapter->dev, "info: Check Events Again\n"); |
1772 | ret = mwifiex_pcie_process_event_ready(adapter); | |
1773 | ||
1774 | return ret; | |
1775 | } | |
1776 | ||
1777 | /* | |
1778 | * This function downloads the firmware to the card. | |
1779 | * | |
1780 | * Firmware is downloaded to the card in blocks. Every block download | |
1781 | * is tested for CRC errors, and retried a number of times before | |
1782 | * returning failure. | |
1783 | */ | |
1784 | static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter, | |
1785 | struct mwifiex_fw_image *fw) | |
1786 | { | |
1787 | int ret; | |
1788 | u8 *firmware = fw->fw_buf; | |
1789 | u32 firmware_len = fw->fw_len; | |
1790 | u32 offset = 0; | |
1791 | struct sk_buff *skb; | |
1792 | u32 txlen, tx_blocks = 0, tries, len; | |
1793 | u32 block_retry_cnt = 0; | |
fc331460 | 1794 | struct pcie_service_card *card = adapter->card; |
dd04e6ac | 1795 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
1796 | |
1797 | if (!firmware || !firmware_len) { | |
f57c1edc YAP |
1798 | dev_err(adapter->dev, |
1799 | "No firmware image found! Terminating download\n"); | |
d930faee AK |
1800 | return -1; |
1801 | } | |
1802 | ||
1803 | dev_dbg(adapter->dev, "info: Downloading FW image (%d bytes)\n", | |
f57c1edc | 1804 | firmware_len); |
d930faee AK |
1805 | |
1806 | if (mwifiex_pcie_disable_host_int(adapter)) { | |
f57c1edc YAP |
1807 | dev_err(adapter->dev, |
1808 | "%s: Disabling interrupts failed.\n", __func__); | |
d930faee AK |
1809 | return -1; |
1810 | } | |
1811 | ||
1812 | skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE); | |
1813 | if (!skb) { | |
1814 | ret = -ENOMEM; | |
1815 | goto done; | |
1816 | } | |
d930faee AK |
1817 | |
1818 | /* Perform firmware data transfer */ | |
1819 | do { | |
1820 | u32 ireg_intr = 0; | |
1821 | ||
1822 | /* More data? */ | |
1823 | if (offset >= firmware_len) | |
1824 | break; | |
1825 | ||
1826 | for (tries = 0; tries < MAX_POLL_TRIES; tries++) { | |
dd04e6ac | 1827 | ret = mwifiex_read_reg(adapter, reg->cmd_size, |
d930faee AK |
1828 | &len); |
1829 | if (ret) { | |
f57c1edc YAP |
1830 | dev_warn(adapter->dev, |
1831 | "Failed reading len from boot code\n"); | |
d930faee AK |
1832 | goto done; |
1833 | } | |
1834 | if (len) | |
1835 | break; | |
e7891ba2 | 1836 | usleep_range(10, 20); |
d930faee AK |
1837 | } |
1838 | ||
1839 | if (!len) { | |
1840 | break; | |
1841 | } else if (len > MWIFIEX_UPLD_SIZE) { | |
1842 | pr_err("FW download failure @ %d, invalid length %d\n", | |
f57c1edc | 1843 | offset, len); |
d930faee AK |
1844 | ret = -1; |
1845 | goto done; | |
1846 | } | |
1847 | ||
1848 | txlen = len; | |
1849 | ||
1850 | if (len & BIT(0)) { | |
1851 | block_retry_cnt++; | |
1852 | if (block_retry_cnt > MAX_WRITE_IOMEM_RETRY) { | |
1853 | pr_err("FW download failure @ %d, over max " | |
1854 | "retry count\n", offset); | |
1855 | ret = -1; | |
1856 | goto done; | |
1857 | } | |
1858 | dev_err(adapter->dev, "FW CRC error indicated by the " | |
f57c1edc YAP |
1859 | "helper: len = 0x%04X, txlen = %d\n", |
1860 | len, txlen); | |
d930faee AK |
1861 | len &= ~BIT(0); |
1862 | /* Setting this to 0 to resend from same offset */ | |
1863 | txlen = 0; | |
1864 | } else { | |
1865 | block_retry_cnt = 0; | |
1866 | /* Set blocksize to transfer - checking for | |
1867 | last block */ | |
1868 | if (firmware_len - offset < txlen) | |
1869 | txlen = firmware_len - offset; | |
1870 | ||
1871 | dev_dbg(adapter->dev, "."); | |
1872 | ||
dd04e6ac AP |
1873 | tx_blocks = (txlen + card->pcie.blksz_fw_dl - 1) / |
1874 | card->pcie.blksz_fw_dl; | |
d930faee AK |
1875 | |
1876 | /* Copy payload to buffer */ | |
1877 | memmove(skb->data, &firmware[offset], txlen); | |
1878 | } | |
1879 | ||
1880 | skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len); | |
dd04e6ac | 1881 | skb_trim(skb, tx_blocks * card->pcie.blksz_fw_dl); |
d930faee AK |
1882 | |
1883 | /* Send the boot command to device */ | |
1884 | if (mwifiex_pcie_send_boot_cmd(adapter, skb)) { | |
f57c1edc YAP |
1885 | dev_err(adapter->dev, |
1886 | "Failed to send firmware download command\n"); | |
d930faee AK |
1887 | ret = -1; |
1888 | goto done; | |
1889 | } | |
fc331460 | 1890 | |
d930faee AK |
1891 | /* Wait for the command done interrupt */ |
1892 | do { | |
1893 | if (mwifiex_read_reg(adapter, PCIE_CPU_INT_STATUS, | |
1894 | &ireg_intr)) { | |
1895 | dev_err(adapter->dev, "%s: Failed to read " | |
f57c1edc YAP |
1896 | "interrupt status during fw dnld.\n", |
1897 | __func__); | |
dbccc92b AD |
1898 | mwifiex_unmap_pci_memory(adapter, skb, |
1899 | PCI_DMA_TODEVICE); | |
d930faee AK |
1900 | ret = -1; |
1901 | goto done; | |
1902 | } | |
1903 | } while ((ireg_intr & CPU_INTR_DOOR_BELL) == | |
1904 | CPU_INTR_DOOR_BELL); | |
fc331460 | 1905 | |
dbccc92b | 1906 | mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); |
fc331460 | 1907 | |
d930faee AK |
1908 | offset += txlen; |
1909 | } while (true); | |
1910 | ||
1911 | dev_dbg(adapter->dev, "info:\nFW download over, size %d bytes\n", | |
f57c1edc | 1912 | offset); |
d930faee AK |
1913 | |
1914 | ret = 0; | |
1915 | ||
1916 | done: | |
1917 | dev_kfree_skb_any(skb); | |
1918 | return ret; | |
1919 | } | |
1920 | ||
1921 | /* | |
1922 | * This function checks the firmware status in card. | |
1923 | * | |
1924 | * The winner interface is also determined by this function. | |
1925 | */ | |
1926 | static int | |
1927 | mwifiex_check_fw_status(struct mwifiex_adapter *adapter, u32 poll_num) | |
1928 | { | |
1929 | int ret = 0; | |
1930 | u32 firmware_stat, winner_status; | |
dd04e6ac AP |
1931 | struct pcie_service_card *card = adapter->card; |
1932 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; | |
d930faee AK |
1933 | u32 tries; |
1934 | ||
1935 | /* Mask spurios interrupts */ | |
1936 | if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS_MASK, | |
f57c1edc | 1937 | HOST_INTR_MASK)) { |
d930faee AK |
1938 | dev_warn(adapter->dev, "Write register failed\n"); |
1939 | return -1; | |
1940 | } | |
1941 | ||
1942 | dev_dbg(adapter->dev, "Setting driver ready signature\n"); | |
dd04e6ac AP |
1943 | if (mwifiex_write_reg(adapter, reg->drv_rdy, |
1944 | FIRMWARE_READY_PCIE)) { | |
f57c1edc YAP |
1945 | dev_err(adapter->dev, |
1946 | "Failed to write driver ready signature\n"); | |
d930faee AK |
1947 | return -1; |
1948 | } | |
1949 | ||
1950 | /* Wait for firmware initialization event */ | |
1951 | for (tries = 0; tries < poll_num; tries++) { | |
dd04e6ac | 1952 | if (mwifiex_read_reg(adapter, reg->fw_status, |
d930faee AK |
1953 | &firmware_stat)) |
1954 | ret = -1; | |
1955 | else | |
1956 | ret = 0; | |
1957 | if (ret) | |
1958 | continue; | |
1959 | if (firmware_stat == FIRMWARE_READY_PCIE) { | |
1960 | ret = 0; | |
1961 | break; | |
1962 | } else { | |
a76b20e5 | 1963 | msleep(100); |
d930faee AK |
1964 | ret = -1; |
1965 | } | |
1966 | } | |
1967 | ||
1968 | if (ret) { | |
dd04e6ac | 1969 | if (mwifiex_read_reg(adapter, reg->fw_status, |
d930faee AK |
1970 | &winner_status)) |
1971 | ret = -1; | |
1972 | else if (!winner_status) { | |
1973 | dev_err(adapter->dev, "PCI-E is the winner\n"); | |
1974 | adapter->winner = 1; | |
d930faee | 1975 | } else { |
f57c1edc YAP |
1976 | dev_err(adapter->dev, |
1977 | "PCI-E is not the winner <%#x,%d>, exit dnld\n", | |
1978 | ret, adapter->winner); | |
d930faee AK |
1979 | } |
1980 | } | |
1981 | ||
1982 | return ret; | |
1983 | } | |
1984 | ||
1985 | /* | |
1986 | * This function reads the interrupt status from card. | |
1987 | */ | |
1988 | static void mwifiex_interrupt_status(struct mwifiex_adapter *adapter) | |
1989 | { | |
1990 | u32 pcie_ireg; | |
1991 | unsigned long flags; | |
1992 | ||
1993 | if (!mwifiex_pcie_ok_to_access_hw(adapter)) | |
1994 | return; | |
1995 | ||
1996 | if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS, &pcie_ireg)) { | |
1997 | dev_warn(adapter->dev, "Read register failed\n"); | |
1998 | return; | |
1999 | } | |
2000 | ||
2001 | if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) { | |
2002 | ||
2003 | mwifiex_pcie_disable_host_int(adapter); | |
2004 | ||
2005 | /* Clear the pending interrupts */ | |
2006 | if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS, | |
2007 | ~pcie_ireg)) { | |
2008 | dev_warn(adapter->dev, "Write register failed\n"); | |
2009 | return; | |
2010 | } | |
2011 | spin_lock_irqsave(&adapter->int_lock, flags); | |
2012 | adapter->int_status |= pcie_ireg; | |
2013 | spin_unlock_irqrestore(&adapter->int_lock, flags); | |
2014 | ||
1c97560f AK |
2015 | if (!adapter->pps_uapsd_mode && |
2016 | adapter->ps_state == PS_STATE_SLEEP && | |
2017 | mwifiex_pcie_ok_to_access_hw(adapter)) { | |
d930faee AK |
2018 | /* Potentially for PCIe we could get other |
2019 | * interrupts like shared. Don't change power | |
2020 | * state until cookie is set */ | |
c24d992a AP |
2021 | adapter->ps_state = PS_STATE_AWAKE; |
2022 | adapter->pm_wakeup_fw_try = false; | |
d930faee AK |
2023 | } |
2024 | } | |
2025 | } | |
2026 | ||
2027 | /* | |
2028 | * Interrupt handler for PCIe root port | |
2029 | * | |
2030 | * This function reads the interrupt status from firmware and assigns | |
2031 | * the main process in workqueue which will handle the interrupt. | |
2032 | */ | |
2033 | static irqreturn_t mwifiex_pcie_interrupt(int irq, void *context) | |
2034 | { | |
2035 | struct pci_dev *pdev = (struct pci_dev *)context; | |
2036 | struct pcie_service_card *card; | |
2037 | struct mwifiex_adapter *adapter; | |
2038 | ||
2039 | if (!pdev) { | |
2040 | pr_debug("info: %s: pdev is NULL\n", (u8 *)pdev); | |
2041 | goto exit; | |
2042 | } | |
2043 | ||
b2a31204 | 2044 | card = pci_get_drvdata(pdev); |
d930faee AK |
2045 | if (!card || !card->adapter) { |
2046 | pr_debug("info: %s: card=%p adapter=%p\n", __func__, card, | |
f57c1edc | 2047 | card ? card->adapter : NULL); |
d930faee AK |
2048 | goto exit; |
2049 | } | |
2050 | adapter = card->adapter; | |
2051 | ||
2052 | if (adapter->surprise_removed) | |
2053 | goto exit; | |
2054 | ||
2055 | mwifiex_interrupt_status(adapter); | |
2056 | queue_work(adapter->workqueue, &adapter->main_work); | |
2057 | ||
2058 | exit: | |
2059 | return IRQ_HANDLED; | |
2060 | } | |
2061 | ||
2062 | /* | |
2063 | * This function checks the current interrupt status. | |
2064 | * | |
2065 | * The following interrupts are checked and handled by this function - | |
2066 | * - Data sent | |
2067 | * - Command sent | |
2068 | * - Command received | |
2069 | * - Packets received | |
2070 | * - Events received | |
2071 | * | |
2072 | * In case of Rx packets received, the packets are uploaded from card to | |
2073 | * host and processed accordingly. | |
2074 | */ | |
2075 | static int mwifiex_process_int_status(struct mwifiex_adapter *adapter) | |
2076 | { | |
2077 | int ret; | |
659c4788 | 2078 | u32 pcie_ireg; |
d930faee AK |
2079 | unsigned long flags; |
2080 | ||
2081 | spin_lock_irqsave(&adapter->int_lock, flags); | |
2082 | /* Clear out unused interrupts */ | |
659c4788 AP |
2083 | pcie_ireg = adapter->int_status; |
2084 | adapter->int_status = 0; | |
d930faee AK |
2085 | spin_unlock_irqrestore(&adapter->int_lock, flags); |
2086 | ||
659c4788 AP |
2087 | while (pcie_ireg & HOST_INTR_MASK) { |
2088 | if (pcie_ireg & HOST_INTR_DNLD_DONE) { | |
2089 | pcie_ireg &= ~HOST_INTR_DNLD_DONE; | |
e7f767a7 AP |
2090 | dev_dbg(adapter->dev, "info: TX DNLD Done\n"); |
2091 | ret = mwifiex_pcie_send_data_complete(adapter); | |
2092 | if (ret) | |
2093 | return ret; | |
d930faee | 2094 | } |
659c4788 AP |
2095 | if (pcie_ireg & HOST_INTR_UPLD_RDY) { |
2096 | pcie_ireg &= ~HOST_INTR_UPLD_RDY; | |
d930faee AK |
2097 | dev_dbg(adapter->dev, "info: Rx DATA\n"); |
2098 | ret = mwifiex_pcie_process_recv_data(adapter); | |
2099 | if (ret) | |
2100 | return ret; | |
2101 | } | |
659c4788 AP |
2102 | if (pcie_ireg & HOST_INTR_EVENT_RDY) { |
2103 | pcie_ireg &= ~HOST_INTR_EVENT_RDY; | |
d930faee AK |
2104 | dev_dbg(adapter->dev, "info: Rx EVENT\n"); |
2105 | ret = mwifiex_pcie_process_event_ready(adapter); | |
2106 | if (ret) | |
2107 | return ret; | |
2108 | } | |
2109 | ||
659c4788 AP |
2110 | if (pcie_ireg & HOST_INTR_CMD_DONE) { |
2111 | pcie_ireg &= ~HOST_INTR_CMD_DONE; | |
d930faee | 2112 | if (adapter->cmd_sent) { |
f57c1edc YAP |
2113 | dev_dbg(adapter->dev, |
2114 | "info: CMD sent Interrupt\n"); | |
d930faee AK |
2115 | adapter->cmd_sent = false; |
2116 | } | |
2117 | /* Handle command response */ | |
2118 | ret = mwifiex_pcie_process_cmd_complete(adapter); | |
2119 | if (ret) | |
2120 | return ret; | |
2121 | } | |
2122 | ||
2123 | if (mwifiex_pcie_ok_to_access_hw(adapter)) { | |
2124 | if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS, | |
2125 | &pcie_ireg)) { | |
f57c1edc YAP |
2126 | dev_warn(adapter->dev, |
2127 | "Read register failed\n"); | |
d930faee AK |
2128 | return -1; |
2129 | } | |
2130 | ||
2131 | if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) { | |
2132 | if (mwifiex_write_reg(adapter, | |
f57c1edc YAP |
2133 | PCIE_HOST_INT_STATUS, |
2134 | ~pcie_ireg)) { | |
2135 | dev_warn(adapter->dev, | |
2136 | "Write register failed\n"); | |
d930faee AK |
2137 | return -1; |
2138 | } | |
d930faee AK |
2139 | } |
2140 | ||
2141 | } | |
2142 | } | |
2143 | dev_dbg(adapter->dev, "info: cmd_sent=%d data_sent=%d\n", | |
f57c1edc | 2144 | adapter->cmd_sent, adapter->data_sent); |
b2fda1f6 AP |
2145 | if (adapter->ps_state != PS_STATE_SLEEP) |
2146 | mwifiex_pcie_enable_host_int(adapter); | |
d930faee AK |
2147 | |
2148 | return 0; | |
2149 | } | |
2150 | ||
2151 | /* | |
2152 | * This function downloads data from driver to card. | |
2153 | * | |
2154 | * Both commands and data packets are transferred to the card by this | |
2155 | * function. | |
2156 | * | |
2157 | * This function adds the PCIE specific header to the front of the buffer | |
2158 | * before transferring. The header contains the length of the packet and | |
2159 | * the type. The firmware handles the packets based upon this set type. | |
2160 | */ | |
2161 | static int mwifiex_pcie_host_to_card(struct mwifiex_adapter *adapter, u8 type, | |
2162 | struct sk_buff *skb, | |
2163 | struct mwifiex_tx_param *tx_param) | |
2164 | { | |
fa161cb7 DC |
2165 | if (!skb) { |
2166 | dev_err(adapter->dev, "Passed NULL skb to %s\n", __func__); | |
d930faee AK |
2167 | return -1; |
2168 | } | |
2169 | ||
2170 | if (type == MWIFIEX_TYPE_DATA) | |
e7f767a7 | 2171 | return mwifiex_pcie_send_data(adapter, skb, tx_param); |
d930faee AK |
2172 | else if (type == MWIFIEX_TYPE_CMD) |
2173 | return mwifiex_pcie_send_cmd(adapter, skb); | |
2174 | ||
2175 | return 0; | |
2176 | } | |
2177 | ||
2178 | /* | |
2179 | * This function initializes the PCI-E host memory space, WCB rings, etc. | |
2180 | * | |
2181 | * The following initializations steps are followed - | |
2182 | * - Allocate TXBD ring buffers | |
2183 | * - Allocate RXBD ring buffers | |
2184 | * - Allocate event BD ring buffers | |
2185 | * - Allocate command response ring buffer | |
2186 | * - Allocate sleep cookie buffer | |
2187 | */ | |
2188 | static int mwifiex_pcie_init(struct mwifiex_adapter *adapter) | |
2189 | { | |
2190 | struct pcie_service_card *card = adapter->card; | |
2191 | int ret; | |
2192 | struct pci_dev *pdev = card->dev; | |
52301a81 | 2193 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
2194 | |
2195 | pci_set_drvdata(pdev, card); | |
2196 | ||
2197 | ret = pci_enable_device(pdev); | |
2198 | if (ret) | |
2199 | goto err_enable_dev; | |
2200 | ||
2201 | pci_set_master(pdev); | |
2202 | ||
2203 | dev_dbg(adapter->dev, "try set_consistent_dma_mask(32)\n"); | |
2204 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2205 | if (ret) { | |
2206 | dev_err(adapter->dev, "set_dma_mask(32) failed\n"); | |
2207 | goto err_set_dma_mask; | |
2208 | } | |
2209 | ||
2210 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2211 | if (ret) { | |
2212 | dev_err(adapter->dev, "set_consistent_dma_mask(64) failed\n"); | |
2213 | goto err_set_dma_mask; | |
2214 | } | |
2215 | ||
2216 | ret = pci_request_region(pdev, 0, DRV_NAME); | |
2217 | if (ret) { | |
2218 | dev_err(adapter->dev, "req_reg(0) error\n"); | |
2219 | goto err_req_region0; | |
2220 | } | |
2221 | card->pci_mmap = pci_iomap(pdev, 0, 0); | |
2222 | if (!card->pci_mmap) { | |
2223 | dev_err(adapter->dev, "iomap(0) error\n"); | |
3220712d | 2224 | ret = -EIO; |
d930faee AK |
2225 | goto err_iomap0; |
2226 | } | |
2227 | ret = pci_request_region(pdev, 2, DRV_NAME); | |
2228 | if (ret) { | |
2229 | dev_err(adapter->dev, "req_reg(2) error\n"); | |
2230 | goto err_req_region2; | |
2231 | } | |
2232 | card->pci_mmap1 = pci_iomap(pdev, 2, 0); | |
2233 | if (!card->pci_mmap1) { | |
2234 | dev_err(adapter->dev, "iomap(2) error\n"); | |
3220712d | 2235 | ret = -EIO; |
d930faee AK |
2236 | goto err_iomap2; |
2237 | } | |
2238 | ||
f57c1edc YAP |
2239 | dev_dbg(adapter->dev, |
2240 | "PCI memory map Virt0: %p PCI memory map Virt2: %p\n", | |
2241 | card->pci_mmap, card->pci_mmap1); | |
d930faee AK |
2242 | |
2243 | card->cmdrsp_buf = NULL; | |
2244 | ret = mwifiex_pcie_create_txbd_ring(adapter); | |
2245 | if (ret) | |
2246 | goto err_cre_txbd; | |
2247 | ret = mwifiex_pcie_create_rxbd_ring(adapter); | |
2248 | if (ret) | |
2249 | goto err_cre_rxbd; | |
2250 | ret = mwifiex_pcie_create_evtbd_ring(adapter); | |
2251 | if (ret) | |
2252 | goto err_cre_evtbd; | |
2253 | ret = mwifiex_pcie_alloc_cmdrsp_buf(adapter); | |
2254 | if (ret) | |
2255 | goto err_alloc_cmdbuf; | |
52301a81 AP |
2256 | if (reg->sleep_cookie) { |
2257 | ret = mwifiex_pcie_alloc_sleep_cookie_buf(adapter); | |
2258 | if (ret) | |
2259 | goto err_alloc_cookie; | |
2260 | } else { | |
2261 | card->sleep_cookie_vbase = NULL; | |
2262 | } | |
d930faee AK |
2263 | return ret; |
2264 | ||
2265 | err_alloc_cookie: | |
2266 | mwifiex_pcie_delete_cmdrsp_buf(adapter); | |
2267 | err_alloc_cmdbuf: | |
2268 | mwifiex_pcie_delete_evtbd_ring(adapter); | |
2269 | err_cre_evtbd: | |
2270 | mwifiex_pcie_delete_rxbd_ring(adapter); | |
2271 | err_cre_rxbd: | |
2272 | mwifiex_pcie_delete_txbd_ring(adapter); | |
2273 | err_cre_txbd: | |
2274 | pci_iounmap(pdev, card->pci_mmap1); | |
2275 | err_iomap2: | |
2276 | pci_release_region(pdev, 2); | |
2277 | err_req_region2: | |
2278 | pci_iounmap(pdev, card->pci_mmap); | |
2279 | err_iomap0: | |
2280 | pci_release_region(pdev, 0); | |
2281 | err_req_region0: | |
2282 | err_set_dma_mask: | |
2283 | pci_disable_device(pdev); | |
2284 | err_enable_dev: | |
2285 | pci_set_drvdata(pdev, NULL); | |
2286 | return ret; | |
2287 | } | |
2288 | ||
2289 | /* | |
2290 | * This function cleans up the allocated card buffers. | |
2291 | * | |
2292 | * The following are freed by this function - | |
2293 | * - TXBD ring buffers | |
2294 | * - RXBD ring buffers | |
2295 | * - Event BD ring buffers | |
2296 | * - Command response ring buffer | |
2297 | * - Sleep cookie buffer | |
2298 | */ | |
2299 | static void mwifiex_pcie_cleanup(struct mwifiex_adapter *adapter) | |
2300 | { | |
2301 | struct pcie_service_card *card = adapter->card; | |
2302 | struct pci_dev *pdev = card->dev; | |
dd04e6ac | 2303 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee | 2304 | |
d930faee | 2305 | if (user_rmmod) { |
fc331460 | 2306 | dev_dbg(adapter->dev, "Clearing driver ready signature\n"); |
dd04e6ac | 2307 | if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000)) |
f57c1edc YAP |
2308 | dev_err(adapter->dev, |
2309 | "Failed to write driver not-ready signature\n"); | |
d930faee AK |
2310 | } |
2311 | ||
2312 | if (pdev) { | |
2313 | pci_iounmap(pdev, card->pci_mmap); | |
2314 | pci_iounmap(pdev, card->pci_mmap1); | |
5b0d9b21 | 2315 | pci_disable_device(pdev); |
c380aafb YAP |
2316 | pci_release_region(pdev, 2); |
2317 | pci_release_region(pdev, 0); | |
d930faee AK |
2318 | pci_set_drvdata(pdev, NULL); |
2319 | } | |
3c59e328 | 2320 | kfree(card); |
d930faee AK |
2321 | } |
2322 | ||
2323 | /* | |
2324 | * This function registers the PCIE device. | |
2325 | * | |
2326 | * PCIE IRQ is claimed, block size is set and driver data is initialized. | |
2327 | */ | |
2328 | static int mwifiex_register_dev(struct mwifiex_adapter *adapter) | |
2329 | { | |
2330 | int ret; | |
2331 | struct pcie_service_card *card = adapter->card; | |
2332 | struct pci_dev *pdev = card->dev; | |
2333 | ||
2334 | /* save adapter pointer in card */ | |
2335 | card->adapter = adapter; | |
2336 | ||
2337 | ret = request_irq(pdev->irq, mwifiex_pcie_interrupt, IRQF_SHARED, | |
2338 | "MRVL_PCIE", pdev); | |
2339 | if (ret) { | |
2340 | pr_err("request_irq failed: ret=%d\n", ret); | |
2341 | adapter->card = NULL; | |
2342 | return -1; | |
2343 | } | |
2344 | ||
2345 | adapter->dev = &pdev->dev; | |
828cf222 | 2346 | adapter->tx_buf_size = card->pcie.tx_buf_size; |
dd04e6ac | 2347 | strcpy(adapter->fw_name, card->pcie.firmware); |
d930faee AK |
2348 | |
2349 | return 0; | |
2350 | } | |
2351 | ||
2352 | /* | |
2353 | * This function unregisters the PCIE device. | |
2354 | * | |
2355 | * The PCIE IRQ is released, the function is disabled and driver | |
2356 | * data is set to null. | |
2357 | */ | |
2358 | static void mwifiex_unregister_dev(struct mwifiex_adapter *adapter) | |
2359 | { | |
2360 | struct pcie_service_card *card = adapter->card; | |
52301a81 | 2361 | const struct mwifiex_pcie_card_reg *reg; |
d930faee AK |
2362 | |
2363 | if (card) { | |
2364 | dev_dbg(adapter->dev, "%s(): calling free_irq()\n", __func__); | |
2365 | free_irq(card->dev->irq, card->dev); | |
fc331460 | 2366 | |
52301a81 AP |
2367 | reg = card->pcie.reg; |
2368 | if (reg->sleep_cookie) | |
2369 | mwifiex_pcie_delete_sleep_cookie_buf(adapter); | |
2370 | ||
fc331460 AP |
2371 | mwifiex_pcie_delete_cmdrsp_buf(adapter); |
2372 | mwifiex_pcie_delete_evtbd_ring(adapter); | |
2373 | mwifiex_pcie_delete_rxbd_ring(adapter); | |
2374 | mwifiex_pcie_delete_txbd_ring(adapter); | |
2375 | card->cmdrsp_buf = NULL; | |
d930faee AK |
2376 | } |
2377 | } | |
2378 | ||
2379 | static struct mwifiex_if_ops pcie_ops = { | |
2380 | .init_if = mwifiex_pcie_init, | |
2381 | .cleanup_if = mwifiex_pcie_cleanup, | |
2382 | .check_fw_status = mwifiex_check_fw_status, | |
2383 | .prog_fw = mwifiex_prog_fw_w_helper, | |
2384 | .register_dev = mwifiex_register_dev, | |
2385 | .unregister_dev = mwifiex_unregister_dev, | |
2386 | .enable_int = mwifiex_pcie_enable_host_int, | |
2387 | .process_int_status = mwifiex_process_int_status, | |
2388 | .host_to_card = mwifiex_pcie_host_to_card, | |
2389 | .wakeup = mwifiex_pm_wakeup_card, | |
2390 | .wakeup_complete = mwifiex_pm_wakeup_card_complete, | |
2391 | ||
2392 | /* PCIE specific */ | |
2393 | .cmdrsp_complete = mwifiex_pcie_cmdrsp_complete, | |
2394 | .event_complete = mwifiex_pcie_event_complete, | |
2395 | .update_mp_end_port = NULL, | |
2396 | .cleanup_mpa_buf = NULL, | |
c6d1d87a | 2397 | .init_fw_port = mwifiex_pcie_init_fw_port, |
fbd7e7ac | 2398 | .clean_pcie_ring = mwifiex_clean_pcie_ring_buf, |
d930faee AK |
2399 | }; |
2400 | ||
2401 | /* | |
2402 | * This function initializes the PCIE driver module. | |
2403 | * | |
2404 | * This initiates the semaphore and registers the device with | |
2405 | * PCIE bus. | |
2406 | */ | |
2407 | static int mwifiex_pcie_init_module(void) | |
2408 | { | |
2409 | int ret; | |
2410 | ||
ca8f2112 | 2411 | pr_debug("Marvell PCIe Driver\n"); |
d930faee AK |
2412 | |
2413 | sema_init(&add_remove_card_sem, 1); | |
2414 | ||
2415 | /* Clear the flag in case user removes the card. */ | |
2416 | user_rmmod = 0; | |
2417 | ||
2418 | ret = pci_register_driver(&mwifiex_pcie); | |
2419 | if (ret) | |
2420 | pr_err("Driver register failed!\n"); | |
2421 | else | |
2422 | pr_debug("info: Driver registered successfully!\n"); | |
2423 | ||
2424 | return ret; | |
2425 | } | |
2426 | ||
2427 | /* | |
2428 | * This function cleans up the PCIE driver. | |
2429 | * | |
2430 | * The following major steps are followed for cleanup - | |
2431 | * - Resume the device if its suspended | |
2432 | * - Disconnect the device if connected | |
2433 | * - Shutdown the firmware | |
2434 | * - Unregister the device from PCIE bus. | |
2435 | */ | |
2436 | static void mwifiex_pcie_cleanup_module(void) | |
2437 | { | |
2438 | if (!down_interruptible(&add_remove_card_sem)) | |
2439 | up(&add_remove_card_sem); | |
2440 | ||
2441 | /* Set the flag as user is removing this module. */ | |
2442 | user_rmmod = 1; | |
2443 | ||
2444 | pci_unregister_driver(&mwifiex_pcie); | |
2445 | } | |
2446 | ||
2447 | module_init(mwifiex_pcie_init_module); | |
2448 | module_exit(mwifiex_pcie_cleanup_module); | |
2449 | ||
2450 | MODULE_AUTHOR("Marvell International Ltd."); | |
2451 | MODULE_DESCRIPTION("Marvell WiFi-Ex PCI-Express Driver version " PCIE_VERSION); | |
2452 | MODULE_VERSION(PCIE_VERSION); | |
2453 | MODULE_LICENSE("GPL v2"); | |
ca8f2112 AP |
2454 | MODULE_FIRMWARE(PCIE8766_DEFAULT_FW_NAME); |
2455 | MODULE_FIRMWARE(PCIE8897_DEFAULT_FW_NAME); |