[deliverable/linux.git] / drivers / net / wireless / mwifiex / sdio.h

/*
 * Marvell Wireless LAN device driver: SDIO specific definitions
 *
 * Copyright (C) 2011-2014, Marvell International Ltd.
 *
 * This software file (the "File") is distributed by Marvell International
 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
 * (the "License").  You may use, redistribute and/or modify this File in
 * accordance with the terms and conditions of the License, a copy of which
 * is available by writing to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
 * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
 * this warranty disclaimer.
 */

#ifndef	_MWIFIEX_SDIO_H
#define	_MWIFIEX_SDIO_H


#include <linux/mmc/sdio.h>
#include <linux/mmc/sdio_ids.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>

#include "main.h"

#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
#define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
#define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
#define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin"

#define BLOCK_MODE	1
#define BYTE_MODE	0

#define REG_PORT			0

#define MWIFIEX_SDIO_IO_PORT_MASK		0xfffff

#define MWIFIEX_SDIO_BYTE_MODE_MASK	0x80000000

#define MWIFIEX_MAX_FUNC2_REG_NUM	13
#define MWIFIEX_SDIO_SCRATCH_SIZE	10

#define SDIO_MPA_ADDR_BASE		0x1000
#define CTRL_PORT			0
#define CTRL_PORT_MASK			0x0001

#define CMD_PORT_UPLD_INT_MASK		(0x1U<<6)
#define CMD_PORT_DNLD_INT_MASK		(0x1U<<7)
#define HOST_TERM_CMD53			(0x1U << 2)
#define REG_PORT			0
#define MEM_PORT			0x10000

#define CMD53_NEW_MODE			(0x1U << 0)
#define CMD_PORT_RD_LEN_EN		(0x1U << 2)
#define CMD_PORT_AUTO_EN		(0x1U << 0)
#define CMD_PORT_SLCT			0x8000
#define UP_LD_CMD_PORT_HOST_INT_STATUS	(0x40U)
#define DN_LD_CMD_PORT_HOST_INT_STATUS	(0x80U)

#define MWIFIEX_MP_AGGR_BUF_SIZE_16K	(16384)
#define MWIFIEX_MP_AGGR_BUF_SIZE_32K	(32768)
/* we leave one block of 256 bytes for DMA alignment*/
#define MWIFIEX_MP_AGGR_BUF_SIZE_MAX    (65280)

/* Misc. Config Register : Auto Re-enable interrupts */
#define AUTO_RE_ENABLE_INT              BIT(4)

/* Host Control Registers : Configuration */
#define CONFIGURATION_REG		0x00
/* Host Control Registers : Host power up */
#define HOST_POWER_UP			(0x1U << 1)

/* Host Control Registers : Upload host interrupt mask */
#define UP_LD_HOST_INT_MASK		(0x1U)
/* Host Control Registers : Download host interrupt mask */
#define DN_LD_HOST_INT_MASK		(0x2U)

/* Host Control Registers : Upload host interrupt status */
#define UP_LD_HOST_INT_STATUS		(0x1U)
/* Host Control Registers : Download host interrupt status */
#define DN_LD_HOST_INT_STATUS		(0x2U)

/* Host Control Registers : Host interrupt status */
#define CARD_INT_STATUS_REG		0x28

/* Card Control Registers : Card I/O ready */
#define CARD_IO_READY                   (0x1U << 3)
/* Card Control Registers : Download card ready */
#define DN_LD_CARD_RDY                  (0x1U << 0)

/* Max retry number of CMD53 write */
#define MAX_WRITE_IOMEM_RETRY		2

/* SDIO Tx aggregation in progress ? */
#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)

/* SDIO Tx aggregation buffer room for next packet ? */
#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len)	\
						<= a->mpa_tx.buf_size)

/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do {		\
	memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len],			\
			payload, pkt_len);				\
	a->mpa_tx.buf_len += pkt_len;					\
	if (!a->mpa_tx.pkt_cnt)						\
		a->mpa_tx.start_port = port;				\
	if (a->mpa_tx.start_port <= port)				\
		a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt));		\
	else								\
		a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+		\
						(a->max_ports -	\
						a->mp_end_port)));	\
	a->mpa_tx.pkt_cnt++;						\
} while (0)

/* SDIO Tx aggregation limit ? */
#define MP_TX_AGGR_PKT_LIMIT_REACHED(a)					\
			(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)

/* Reset SDIO Tx aggregation buffer parameters */
#define MP_TX_AGGR_BUF_RESET(a) do {					\
	a->mpa_tx.pkt_cnt = 0;						\
	a->mpa_tx.buf_len = 0;						\
	a->mpa_tx.ports = 0;						\
	a->mpa_tx.start_port = 0;					\
} while (0)

/* SDIO Rx aggregation limit ? */
#define MP_RX_AGGR_PKT_LIMIT_REACHED(a)					\
			(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)

/* SDIO Rx aggregation in progress ? */
#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)

/* SDIO Rx aggregation buffer room for next packet ? */
#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len)				\
			((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)

/* Reset SDIO Rx aggregation buffer parameters */
#define MP_RX_AGGR_BUF_RESET(a) do {					\
	a->mpa_rx.pkt_cnt = 0;						\
	a->mpa_rx.buf_len = 0;						\
	a->mpa_rx.ports = 0;						\
	a->mpa_rx.start_port = 0;					\
} while (0)

/* data structure for SDIO MPA TX */
struct mwifiex_sdio_mpa_tx {
	/* multiport tx aggregation buffer pointer */
	u8 *buf;
	u32 buf_len;
	u32 pkt_cnt;
	u32 ports;
	u16 start_port;
	u8 enabled;
	u32 buf_size;
	u32 pkt_aggr_limit;
};

struct mwifiex_sdio_mpa_rx {
	u8 *buf;
	u32 buf_len;
	u32 pkt_cnt;
	u32 ports;
	u16 start_port;

	struct sk_buff **skb_arr;
	u32 *len_arr;

	u8 enabled;
	u32 buf_size;
	u32 pkt_aggr_limit;
};

int mwifiex_bus_register(void);
void mwifiex_bus_unregister(void);

struct mwifiex_sdio_card_reg {
	u8 start_rd_port;
	u8 start_wr_port;
	u8 base_0_reg;
	u8 base_1_reg;
	u8 poll_reg;
	u8 host_int_enable;
	u8 host_int_rsr_reg;
	u8 host_int_status_reg;
	u8 host_int_mask_reg;
	u8 status_reg_0;
	u8 status_reg_1;
	u8 sdio_int_mask;
	u32 data_port_mask;
	u8 io_port_0_reg;
	u8 io_port_1_reg;
	u8 io_port_2_reg;
	u8 max_mp_regs;
	u8 rd_bitmap_l;
	u8 rd_bitmap_u;
	u8 rd_bitmap_1l;
	u8 rd_bitmap_1u;
	u8 wr_bitmap_l;
	u8 wr_bitmap_u;
	u8 wr_bitmap_1l;
	u8 wr_bitmap_1u;
	u8 rd_len_p0_l;
	u8 rd_len_p0_u;
	u8 card_misc_cfg_reg;
	u8 card_cfg_2_1_reg;
	u8 cmd_rd_len_0;
	u8 cmd_rd_len_1;
	u8 cmd_rd_len_2;
	u8 cmd_rd_len_3;
	u8 cmd_cfg_0;
	u8 cmd_cfg_1;
	u8 cmd_cfg_2;
	u8 cmd_cfg_3;
	u8 fw_dump_ctrl;
	u8 fw_dump_start;
	u8 fw_dump_end;
	u8 func1_dump_reg_start;
	u8 func1_dump_reg_end;
	u8 func1_scratch_reg;
	u8 func1_spec_reg_num;
	u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM];
};

struct sdio_mmc_card {
	struct sdio_func *func;
	struct mwifiex_adapter *adapter;

	const char *firmware;
	const struct mwifiex_sdio_card_reg *reg;
	u8 max_ports;
	u8 mp_agg_pkt_limit;
	u16 tx_buf_size;
	u32 mp_tx_agg_buf_size;
	u32 mp_rx_agg_buf_size;

	u32 mp_rd_bitmap;
	u32 mp_wr_bitmap;

	u16 mp_end_port;
	u32 mp_data_port_mask;

	u8 curr_rd_port;
	u8 curr_wr_port;

	u8 *mp_regs;
	bool supports_sdio_new_mode;
	bool has_control_mask;
	bool can_dump_fw;
	bool can_auto_tdls;
	bool can_ext_scan;

	struct mwifiex_sdio_mpa_tx mpa_tx;
	struct mwifiex_sdio_mpa_rx mpa_rx;

	/* needed for card reset */
	const struct sdio_device_id *device_id;
};

struct mwifiex_sdio_device {
	const char *firmware;
	const struct mwifiex_sdio_card_reg *reg;
	u8 max_ports;
	u8 mp_agg_pkt_limit;
	u16 tx_buf_size;
	u32 mp_tx_agg_buf_size;
	u32 mp_rx_agg_buf_size;
	bool supports_sdio_new_mode;
	bool has_control_mask;
	bool can_dump_fw;
	bool can_auto_tdls;
	bool can_ext_scan;
};

static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
	.start_rd_port = 1,
	.start_wr_port = 1,
	.base_0_reg = 0x0040,
	.base_1_reg = 0x0041,
	.poll_reg = 0x30,
	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
	.host_int_rsr_reg = 0x1,
	.host_int_mask_reg = 0x02,
	.host_int_status_reg = 0x03,
	.status_reg_0 = 0x60,
	.status_reg_1 = 0x61,
	.sdio_int_mask = 0x3f,
	.data_port_mask = 0x0000fffe,
	.io_port_0_reg = 0x78,
	.io_port_1_reg = 0x79,
	.io_port_2_reg = 0x7A,
	.max_mp_regs = 64,
	.rd_bitmap_l = 0x04,
	.rd_bitmap_u = 0x05,
	.wr_bitmap_l = 0x06,
	.wr_bitmap_u = 0x07,
	.rd_len_p0_l = 0x08,
	.rd_len_p0_u = 0x09,
	.card_misc_cfg_reg = 0x6c,
	.func1_dump_reg_start = 0x0,
	.func1_dump_reg_end = 0x9,
	.func1_scratch_reg = 0x60,
	.func1_spec_reg_num = 5,
	.func1_spec_reg_table = {0x28, 0x30, 0x34, 0x38, 0x3c},
};

static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
	.start_rd_port = 0,
	.start_wr_port = 0,
	.base_0_reg = 0x60,
	.base_1_reg = 0x61,
	.poll_reg = 0x50,
	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
			CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
	.host_int_rsr_reg = 0x1,
	.host_int_status_reg = 0x03,
	.host_int_mask_reg = 0x02,
	.status_reg_0 = 0xc0,
	.status_reg_1 = 0xc1,
	.sdio_int_mask = 0xff,
	.data_port_mask = 0xffffffff,
	.io_port_0_reg = 0xD8,
	.io_port_1_reg = 0xD9,
	.io_port_2_reg = 0xDA,
	.max_mp_regs = 184,
	.rd_bitmap_l = 0x04,
	.rd_bitmap_u = 0x05,
	.rd_bitmap_1l = 0x06,
	.rd_bitmap_1u = 0x07,
	.wr_bitmap_l = 0x08,
	.wr_bitmap_u = 0x09,
	.wr_bitmap_1l = 0x0a,
	.wr_bitmap_1u = 0x0b,
	.rd_len_p0_l = 0x0c,
	.rd_len_p0_u = 0x0d,
	.card_misc_cfg_reg = 0xcc,
	.card_cfg_2_1_reg = 0xcd,
	.cmd_rd_len_0 = 0xb4,
	.cmd_rd_len_1 = 0xb5,
	.cmd_rd_len_2 = 0xb6,
	.cmd_rd_len_3 = 0xb7,
	.cmd_cfg_0 = 0xb8,
	.cmd_cfg_1 = 0xb9,
	.cmd_cfg_2 = 0xba,
	.cmd_cfg_3 = 0xbb,
	.fw_dump_ctrl = 0xe2,
	.fw_dump_start = 0xe3,
	.fw_dump_end = 0xea,
	.func1_dump_reg_start = 0x0,
	.func1_dump_reg_end = 0xb,
	.func1_scratch_reg = 0xc0,
	.func1_spec_reg_num = 8,
	.func1_spec_reg_table = {0x4C, 0x50, 0x54, 0x55, 0x58,
				 0x59, 0x5c, 0x5d},
};

static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887 = {
	.start_rd_port = 0,
	.start_wr_port = 0,
	.base_0_reg = 0x6C,
	.base_1_reg = 0x6D,
	.poll_reg = 0x5C,
	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
			CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
	.host_int_rsr_reg = 0x4,
	.host_int_status_reg = 0x0C,
	.host_int_mask_reg = 0x08,
	.status_reg_0 = 0x90,
	.status_reg_1 = 0x91,
	.sdio_int_mask = 0xff,
	.data_port_mask = 0xffffffff,
	.io_port_0_reg = 0xE4,
	.io_port_1_reg = 0xE5,
	.io_port_2_reg = 0xE6,
	.max_mp_regs = 196,
	.rd_bitmap_l = 0x10,
	.rd_bitmap_u = 0x11,
	.rd_bitmap_1l = 0x12,
	.rd_bitmap_1u = 0x13,
	.wr_bitmap_l = 0x14,
	.wr_bitmap_u = 0x15,
	.wr_bitmap_1l = 0x16,
	.wr_bitmap_1u = 0x17,
	.rd_len_p0_l = 0x18,
	.rd_len_p0_u = 0x19,
	.card_misc_cfg_reg = 0xd8,
	.card_cfg_2_1_reg = 0xd9,
	.cmd_rd_len_0 = 0xc0,
	.cmd_rd_len_1 = 0xc1,
	.cmd_rd_len_2 = 0xc2,
	.cmd_rd_len_3 = 0xc3,
	.cmd_cfg_0 = 0xc4,
	.cmd_cfg_1 = 0xc5,
	.cmd_cfg_2 = 0xc6,
	.cmd_cfg_3 = 0xc7,
	.func1_dump_reg_start = 0x10,
	.func1_dump_reg_end = 0x17,
	.func1_scratch_reg = 0x90,
	.func1_spec_reg_num = 13,
	.func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60,
				 0x61, 0x62, 0x64, 0x65, 0x66,
				 0x68, 0x69, 0x6a},
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
	.firmware = SD8786_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
	.supports_sdio_new_mode = false,
	.has_control_mask = true,
	.can_dump_fw = false,
	.can_auto_tdls = false,
	.can_ext_scan = false,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
	.firmware = SD8787_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
	.supports_sdio_new_mode = false,
	.has_control_mask = true,
	.can_dump_fw = false,
	.can_auto_tdls = false,
	.can_ext_scan = true,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
	.firmware = SD8797_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
	.supports_sdio_new_mode = false,
	.has_control_mask = true,
	.can_dump_fw = false,
	.can_auto_tdls = false,
	.can_ext_scan = true,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
	.firmware = SD8897_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd8897,
	.max_ports = 32,
	.mp_agg_pkt_limit = 16,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
	.supports_sdio_new_mode = true,
	.has_control_mask = false,
	.can_dump_fw = true,
	.can_auto_tdls = false,
	.can_ext_scan = true,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8887 = {
	.firmware = SD8887_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd8887,
	.max_ports = 32,
	.mp_agg_pkt_limit = 16,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
	.supports_sdio_new_mode = true,
	.has_control_mask = false,
	.can_dump_fw = false,
	.can_auto_tdls = true,
	.can_ext_scan = true,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8801 = {
	.firmware = SD8801_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
	.supports_sdio_new_mode = false,
	.has_control_mask = true,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
	.can_dump_fw = false,
	.can_auto_tdls = false,
	.can_ext_scan = true,
};

/*
 * .cmdrsp_complete handler
 */
static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
					       struct sk_buff *skb)
{
	dev_kfree_skb_any(skb);
	return 0;
}

/*
 * .event_complete handler
 */
static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
					      struct sk_buff *skb)
{
	dev_kfree_skb_any(skb);
	return 0;
}

static inline bool
mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
{
	u8 tmp;

	if (card->curr_rd_port < card->mpa_rx.start_port) {
		if (card->supports_sdio_new_mode)
			tmp = card->mp_end_port >> 1;
		else
			tmp = card->mp_agg_pkt_limit;

		if (((card->max_ports - card->mpa_rx.start_port) +
		    card->curr_rd_port) >= tmp)
			return true;
	}

	if (!card->supports_sdio_new_mode)
		return false;

	if ((card->curr_rd_port - card->mpa_rx.start_port) >=
	    (card->mp_end_port >> 1))
		return true;

	return false;
}

static inline bool
mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
{
	u16 tmp;

	if (card->curr_wr_port < card->mpa_tx.start_port) {
		if (card->supports_sdio_new_mode)
			tmp = card->mp_end_port >> 1;
		else
			tmp = card->mp_agg_pkt_limit;

		if (((card->max_ports - card->mpa_tx.start_port) +
		    card->curr_wr_port) >= tmp)
			return true;
	}

	if (!card->supports_sdio_new_mode)
		return false;

	if ((card->curr_wr_port - card->mpa_tx.start_port) >=
	    (card->mp_end_port >> 1))
		return true;

	return false;
}

/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
				    u16 rx_len, u8 port)
{
	card->mpa_rx.buf_len += rx_len;

	if (!card->mpa_rx.pkt_cnt)
		card->mpa_rx.start_port = port;

	if (card->supports_sdio_new_mode) {
		card->mpa_rx.ports |= (1 << port);
	} else {
		if (card->mpa_rx.start_port <= port)
			card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
		else
			card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
	}
	card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL;
	card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len;
	card->mpa_rx.pkt_cnt++;
}
#endif /* _MWIFIEX_SDIO_H */
Commit	Line	Data
5e6e3a92 BZ	1	/*
	2	* Marvell Wireless LAN device driver: SDIO specific definitions
	3	*
65da33f5	4	* Copyright (C) 2011-2014, Marvell International Ltd.
5e6e3a92 BZ	5	*
	6	* This software file (the "File") is distributed by Marvell International
	7	* Ltd. under the terms of the GNU General Public License Version 2, June 1991
	8	* (the "License"). You may use, redistribute and/or modify this File in
	9	* accordance with the terms and conditions of the License, a copy of which
	10	* is available by writing to the Free Software Foundation, Inc.,
	11	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
	12	* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
	13	*
	14	* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
	15	* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
	16	* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
	17	* this warranty disclaimer.
	18	*/
	19
	20	#ifndef _MWIFIEX_SDIO_H
	21	#define _MWIFIEX_SDIO_H
	22
	23
	24	#include <linux/mmc/sdio.h>
	25	#include <linux/mmc/sdio_ids.h>
	26	#include <linux/mmc/sdio_func.h>
	27	#include <linux/mmc/card.h>
d31ab357	28	#include <linux/mmc/host.h>
5e6e3a92 BZ	29
	30	#include "main.h"
	31
98e6b9df	32	#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
4a7f5db1	33	#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
e3bea1c8	34	#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
b60186f8	35	#define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
030bb75a	36	#define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
52bd3d20	37	#define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin"
4a7f5db1	38
5e6e3a92 BZ	39	#define BLOCK_MODE 1
	40	#define BYTE_MODE 0
	41
	42	#define REG_PORT 0
5e6e3a92 BZ	43
	44	#define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
	45
	46	#define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
	47
809c6ea8 XH	48	#define MWIFIEX_MAX_FUNC2_REG_NUM 13
	49	#define MWIFIEX_SDIO_SCRATCH_SIZE 10
	50
248eb4c6	51	#define SDIO_MPA_ADDR_BASE 0x1000
5e6e3a92 BZ	52	#define CTRL_PORT 0
5e6e3a92 BZ	53	#define CTRL_PORT_MASK 0x0001
5e6e3a92	54
b60186f8 YAP	55	#define CMD_PORT_UPLD_INT_MASK (0x1U<<6)
	56	#define CMD_PORT_DNLD_INT_MASK (0x1U<<7)
	57	#define HOST_TERM_CMD53 (0x1U << 2)
	58	#define REG_PORT 0
	59	#define MEM_PORT 0x10000
554a0113	60
b60186f8	61	#define CMD53_NEW_MODE (0x1U << 0)
b60186f8	62	#define CMD_PORT_RD_LEN_EN (0x1U << 2)
b60186f8 YAP	63	#define CMD_PORT_AUTO_EN (0x1U << 0)
	64	#define CMD_PORT_SLCT 0x8000
	65	#define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
	66	#define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
	67
e1aa93a4 AK	68	#define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384)
e1aa93a4 AK	69	#define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768)
ea44f4d0 AP	70	/* we leave one block of 256 bytes for DMA alignment*/
ea44f4d0 AP	71	#define MWIFIEX_MP_AGGR_BUF_SIZE_MAX (65280)
5e6e3a92 BZ	72
	73	/* Misc. Config Register : Auto Re-enable interrupts */
	74	#define AUTO_RE_ENABLE_INT BIT(4)
	75
5e6e3a92 BZ	76	/* Host Control Registers : Configuration */
5e6e3a92 BZ	77	#define CONFIGURATION_REG 0x00
5e6e3a92 BZ	78	/* Host Control Registers : Host power up */
5e6e3a92 BZ	79	#define HOST_POWER_UP (0x1U << 1)
5e6e3a92	80
5e6e3a92 BZ	81	/* Host Control Registers : Upload host interrupt mask */
	82	#define UP_LD_HOST_INT_MASK (0x1U)
	83	/* Host Control Registers : Download host interrupt mask */
	84	#define DN_LD_HOST_INT_MASK (0x2U)
b60186f8	85
5e6e3a92 BZ	86	/* Host Control Registers : Upload host interrupt status */
	87	#define UP_LD_HOST_INT_STATUS (0x1U)
	88	/* Host Control Registers : Download host interrupt status */
	89	#define DN_LD_HOST_INT_STATUS (0x2U)
	90
5e6e3a92	91	/* Host Control Registers : Host interrupt status */
554a0113	92	#define CARD_INT_STATUS_REG 0x28
5e6e3a92	93
5e6e3a92 BZ	94	/* Card Control Registers : Card I/O ready */
5e6e3a92 BZ	95	#define CARD_IO_READY (0x1U << 3)
5e6e3a92 BZ	96	/* Card Control Registers : Download card ready */
	97	#define DN_LD_CARD_RDY (0x1U << 0)
	98
5e6e3a92 BZ	99	/* Max retry number of CMD53 write */
	100	#define MAX_WRITE_IOMEM_RETRY 2
	101
	102	/* SDIO Tx aggregation in progress ? */
	103	#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
	104
	105	/* SDIO Tx aggregation buffer room for next packet ? */
	106	#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
	107	<= a->mpa_tx.buf_size)
	108
	109	/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
	110	#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
	111	memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
	112	payload, pkt_len); \
	113	a->mpa_tx.buf_len += pkt_len; \
	114	if (!a->mpa_tx.pkt_cnt) \
	115	a->mpa_tx.start_port = port; \
	116	if (a->mpa_tx.start_port <= port) \
	117	a->mpa_tx.ports \|= (1<<(a->mpa_tx.pkt_cnt)); \
	118	else \
05889f82 AK	119	a->mpa_tx.ports \|= (1<<(a->mpa_tx.pkt_cnt+1+ \
05889f82 AK	120	(a->max_ports - \
5e6e3a92 BZ	121	a->mp_end_port))); \
5e6e3a92 BZ	122	a->mpa_tx.pkt_cnt++; \
da951c24	123	} while (0)
5e6e3a92 BZ	124
	125	/* SDIO Tx aggregation limit ? */
	126	#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
	127	(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
	128
5e6e3a92 BZ	129	/* Reset SDIO Tx aggregation buffer parameters */
	130	#define MP_TX_AGGR_BUF_RESET(a) do { \
	131	a->mpa_tx.pkt_cnt = 0; \
	132	a->mpa_tx.buf_len = 0; \
	133	a->mpa_tx.ports = 0; \
	134	a->mpa_tx.start_port = 0; \
da951c24	135	} while (0)
5e6e3a92 BZ	136
	137	/* SDIO Rx aggregation limit ? */
	138	#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
	139	(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
	140
5e6e3a92 BZ	141	/* SDIO Rx aggregation in progress ? */
	142	#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
	143
	144	/* SDIO Rx aggregation buffer room for next packet ? */
	145	#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
	146	((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
	147
5e6e3a92 BZ	148	/* Reset SDIO Rx aggregation buffer parameters */
	149	#define MP_RX_AGGR_BUF_RESET(a) do { \
	150	a->mpa_rx.pkt_cnt = 0; \
	151	a->mpa_rx.buf_len = 0; \
	152	a->mpa_rx.ports = 0; \
	153	a->mpa_rx.start_port = 0; \
da951c24	154	} while (0)
5e6e3a92	155
5e6e3a92 BZ	156	/* data structure for SDIO MPA TX */
	157	struct mwifiex_sdio_mpa_tx {
	158	/* multiport tx aggregation buffer pointer */
	159	u8 *buf;
	160	u32 buf_len;
	161	u32 pkt_cnt;
5ac253d5	162	u32 ports;
5e6e3a92 BZ	163	u16 start_port;
	164	u8 enabled;
	165	u32 buf_size;
	166	u32 pkt_aggr_limit;
	167	};
	168
	169	struct mwifiex_sdio_mpa_rx {
	170	u8 *buf;
	171	u32 buf_len;
	172	u32 pkt_cnt;
5ac253d5	173	u32 ports;
5e6e3a92 BZ	174	u16 start_port;
5e6e3a92 BZ	175
c23b7c8f AK	176	struct sk_buff **skb_arr;
c23b7c8f AK	177	u32 *len_arr;
5e6e3a92 BZ	178
	179	u8 enabled;
	180	u32 buf_size;
	181	u32 pkt_aggr_limit;
	182	};
	183
	184	int mwifiex_bus_register(void);
	185	void mwifiex_bus_unregister(void);
	186
05889f82 AK	187	struct mwifiex_sdio_card_reg {
	188	u8 start_rd_port;
	189	u8 start_wr_port;
	190	u8 base_0_reg;
	191	u8 base_1_reg;
	192	u8 poll_reg;
	193	u8 host_int_enable;
554a0113 AP	194	u8 host_int_rsr_reg;
	195	u8 host_int_status_reg;
	196	u8 host_int_mask_reg;
05889f82 AK	197	u8 status_reg_0;
	198	u8 status_reg_1;
	199	u8 sdio_int_mask;
	200	u32 data_port_mask;
554a0113 AP	201	u8 io_port_0_reg;
	202	u8 io_port_1_reg;
	203	u8 io_port_2_reg;
05889f82 AK	204	u8 max_mp_regs;
	205	u8 rd_bitmap_l;
	206	u8 rd_bitmap_u;
b60186f8 YAP	207	u8 rd_bitmap_1l;
b60186f8 YAP	208	u8 rd_bitmap_1u;
05889f82 AK	209	u8 wr_bitmap_l;
05889f82 AK	210	u8 wr_bitmap_u;
b60186f8 YAP	211	u8 wr_bitmap_1l;
b60186f8 YAP	212	u8 wr_bitmap_1u;
05889f82 AK	213	u8 rd_len_p0_l;
	214	u8 rd_len_p0_u;
	215	u8 card_misc_cfg_reg;
554a0113 AP	216	u8 card_cfg_2_1_reg;
	217	u8 cmd_rd_len_0;
	218	u8 cmd_rd_len_1;
	219	u8 cmd_rd_len_2;
	220	u8 cmd_rd_len_3;
	221	u8 cmd_cfg_0;
	222	u8 cmd_cfg_1;
	223	u8 cmd_cfg_2;
	224	u8 cmd_cfg_3;
54881c6b AK	225	u8 fw_dump_ctrl;
	226	u8 fw_dump_start;
	227	u8 fw_dump_end;
809c6ea8 XH	228	u8 func1_dump_reg_start;
	229	u8 func1_dump_reg_end;
	230	u8 func1_scratch_reg;
	231	u8 func1_spec_reg_num;
	232	u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM];
05889f82 AK	233	};
05889f82 AK	234
5e6e3a92 BZ	235	struct sdio_mmc_card {
	236	struct sdio_func *func;
	237	struct mwifiex_adapter *adapter;
	238
05889f82 AK	239	const char *firmware;
	240	const struct mwifiex_sdio_card_reg *reg;
	241	u8 max_ports;
	242	u8 mp_agg_pkt_limit;
828cf222	243	u16 tx_buf_size;
e1aa93a4 AK	244	u32 mp_tx_agg_buf_size;
e1aa93a4 AK	245	u32 mp_rx_agg_buf_size;
05889f82	246
5ac253d5 AK	247	u32 mp_rd_bitmap;
5ac253d5 AK	248	u32 mp_wr_bitmap;
5e6e3a92 BZ	249
5e6e3a92 BZ	250	u16 mp_end_port;
5ac253d5	251	u32 mp_data_port_mask;
5e6e3a92 BZ	252
	253	u8 curr_rd_port;
	254	u8 curr_wr_port;
	255
	256	u8 *mp_regs;
b4e8aebb AP	257	bool supports_sdio_new_mode;
	258	bool has_control_mask;
	259	bool can_dump_fw;
	260	bool can_auto_tdls;
1fe192d8	261	bool can_ext_scan;
5e6e3a92 BZ	262
	263	struct mwifiex_sdio_mpa_tx mpa_tx;
	264	struct mwifiex_sdio_mpa_rx mpa_rx;
b4336a28 AF	265
	266	/* needed for card reset */
	267	const struct sdio_device_id *device_id;
5e6e3a92	268	};
d930faee	269
05889f82 AK	270	struct mwifiex_sdio_device {
	271	const char *firmware;
	272	const struct mwifiex_sdio_card_reg *reg;
	273	u8 max_ports;
	274	u8 mp_agg_pkt_limit;
828cf222	275	u16 tx_buf_size;
e1aa93a4 AK	276	u32 mp_tx_agg_buf_size;
e1aa93a4 AK	277	u32 mp_rx_agg_buf_size;
b4e8aebb AP	278	bool supports_sdio_new_mode;
	279	bool has_control_mask;
	280	bool can_dump_fw;
	281	bool can_auto_tdls;
1fe192d8	282	bool can_ext_scan;
05889f82 AK	283	};
	284
	285	static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
	286	.start_rd_port = 1,
	287	.start_wr_port = 1,
	288	.base_0_reg = 0x0040,
	289	.base_1_reg = 0x0041,
	290	.poll_reg = 0x30,
	291	.host_int_enable = UP_LD_HOST_INT_MASK \| DN_LD_HOST_INT_MASK,
554a0113 AP	292	.host_int_rsr_reg = 0x1,
	293	.host_int_mask_reg = 0x02,
	294	.host_int_status_reg = 0x03,
05889f82 AK	295	.status_reg_0 = 0x60,
	296	.status_reg_1 = 0x61,
	297	.sdio_int_mask = 0x3f,
	298	.data_port_mask = 0x0000fffe,
554a0113 AP	299	.io_port_0_reg = 0x78,
	300	.io_port_1_reg = 0x79,
	301	.io_port_2_reg = 0x7A,
05889f82 AK	302	.max_mp_regs = 64,
	303	.rd_bitmap_l = 0x04,
	304	.rd_bitmap_u = 0x05,
	305	.wr_bitmap_l = 0x06,
	306	.wr_bitmap_u = 0x07,
	307	.rd_len_p0_l = 0x08,
	308	.rd_len_p0_u = 0x09,
	309	.card_misc_cfg_reg = 0x6c,
809c6ea8 XH	310	.func1_dump_reg_start = 0x0,
	311	.func1_dump_reg_end = 0x9,
	312	.func1_scratch_reg = 0x60,
	313	.func1_spec_reg_num = 5,
	314	.func1_spec_reg_table = {0x28, 0x30, 0x34, 0x38, 0x3c},
05889f82 AK	315	};
05889f82 AK	316
b60186f8 YAP	317	static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
	318	.start_rd_port = 0,
	319	.start_wr_port = 0,
	320	.base_0_reg = 0x60,
	321	.base_1_reg = 0x61,
	322	.poll_reg = 0x50,
	323	.host_int_enable = UP_LD_HOST_INT_MASK \| DN_LD_HOST_INT_MASK \|
	324	CMD_PORT_UPLD_INT_MASK \| CMD_PORT_DNLD_INT_MASK,
554a0113 AP	325	.host_int_rsr_reg = 0x1,
	326	.host_int_status_reg = 0x03,
	327	.host_int_mask_reg = 0x02,
b60186f8 YAP	328	.status_reg_0 = 0xc0,
	329	.status_reg_1 = 0xc1,
	330	.sdio_int_mask = 0xff,
	331	.data_port_mask = 0xffffffff,
554a0113 AP	332	.io_port_0_reg = 0xD8,
	333	.io_port_1_reg = 0xD9,
	334	.io_port_2_reg = 0xDA,
b60186f8 YAP	335	.max_mp_regs = 184,
	336	.rd_bitmap_l = 0x04,
	337	.rd_bitmap_u = 0x05,
	338	.rd_bitmap_1l = 0x06,
	339	.rd_bitmap_1u = 0x07,
	340	.wr_bitmap_l = 0x08,
	341	.wr_bitmap_u = 0x09,
	342	.wr_bitmap_1l = 0x0a,
	343	.wr_bitmap_1u = 0x0b,
	344	.rd_len_p0_l = 0x0c,
	345	.rd_len_p0_u = 0x0d,
	346	.card_misc_cfg_reg = 0xcc,
554a0113 AP	347	.card_cfg_2_1_reg = 0xcd,
	348	.cmd_rd_len_0 = 0xb4,
	349	.cmd_rd_len_1 = 0xb5,
	350	.cmd_rd_len_2 = 0xb6,
	351	.cmd_rd_len_3 = 0xb7,
	352	.cmd_cfg_0 = 0xb8,
	353	.cmd_cfg_1 = 0xb9,
	354	.cmd_cfg_2 = 0xba,
	355	.cmd_cfg_3 = 0xbb,
54881c6b AK	356	.fw_dump_ctrl = 0xe2,
	357	.fw_dump_start = 0xe3,
	358	.fw_dump_end = 0xea,
809c6ea8 XH	359	.func1_dump_reg_start = 0x0,
	360	.func1_dump_reg_end = 0xb,
	361	.func1_scratch_reg = 0xc0,
	362	.func1_spec_reg_num = 8,
	363	.func1_spec_reg_table = {0x4C, 0x50, 0x54, 0x55, 0x58,
	364	0x59, 0x5c, 0x5d},
b60186f8 YAP	365	};
b60186f8 YAP	366
030bb75a AP	367	static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887 = {
	368	.start_rd_port = 0,
	369	.start_wr_port = 0,
	370	.base_0_reg = 0x6C,
	371	.base_1_reg = 0x6D,
	372	.poll_reg = 0x5C,
	373	.host_int_enable = UP_LD_HOST_INT_MASK \| DN_LD_HOST_INT_MASK \|
	374	CMD_PORT_UPLD_INT_MASK \| CMD_PORT_DNLD_INT_MASK,
	375	.host_int_rsr_reg = 0x4,
	376	.host_int_status_reg = 0x0C,
	377	.host_int_mask_reg = 0x08,
	378	.status_reg_0 = 0x90,
	379	.status_reg_1 = 0x91,
	380	.sdio_int_mask = 0xff,
	381	.data_port_mask = 0xffffffff,
	382	.io_port_0_reg = 0xE4,
	383	.io_port_1_reg = 0xE5,
	384	.io_port_2_reg = 0xE6,
	385	.max_mp_regs = 196,
	386	.rd_bitmap_l = 0x10,
	387	.rd_bitmap_u = 0x11,
	388	.rd_bitmap_1l = 0x12,
	389	.rd_bitmap_1u = 0x13,
	390	.wr_bitmap_l = 0x14,
	391	.wr_bitmap_u = 0x15,
	392	.wr_bitmap_1l = 0x16,
	393	.wr_bitmap_1u = 0x17,
	394	.rd_len_p0_l = 0x18,
	395	.rd_len_p0_u = 0x19,
	396	.card_misc_cfg_reg = 0xd8,
	397	.card_cfg_2_1_reg = 0xd9,
	398	.cmd_rd_len_0 = 0xc0,
	399	.cmd_rd_len_1 = 0xc1,
	400	.cmd_rd_len_2 = 0xc2,
	401	.cmd_rd_len_3 = 0xc3,
	402	.cmd_cfg_0 = 0xc4,
	403	.cmd_cfg_1 = 0xc5,
	404	.cmd_cfg_2 = 0xc6,
	405	.cmd_cfg_3 = 0xc7,
809c6ea8 XH	406	.func1_dump_reg_start = 0x10,
	407	.func1_dump_reg_end = 0x17,
	408	.func1_scratch_reg = 0x90,
	409	.func1_spec_reg_num = 13,
	410	.func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60,
	411	0x61, 0x62, 0x64, 0x65, 0x66,
	412	0x68, 0x69, 0x6a},
030bb75a AP	413	};
030bb75a AP	414
05889f82 AK	415	static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
	416	.firmware = SD8786_DEFAULT_FW_NAME,
	417	.reg = &mwifiex_reg_sd87xx,
	418	.max_ports = 16,
	419	.mp_agg_pkt_limit = 8,
828cf222	420	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
e1aa93a4 AK	421	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
e1aa93a4 AK	422	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
b4e8aebb AP	423	.supports_sdio_new_mode = false,
	424	.has_control_mask = true,
	425	.can_dump_fw = false,
	426	.can_auto_tdls = false,
1fe192d8	427	.can_ext_scan = false,
05889f82 AK	428	};
	429
	430	static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
	431	.firmware = SD8787_DEFAULT_FW_NAME,
	432	.reg = &mwifiex_reg_sd87xx,
	433	.max_ports = 16,
	434	.mp_agg_pkt_limit = 8,
828cf222	435	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
e1aa93a4 AK	436	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
e1aa93a4 AK	437	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
b4e8aebb AP	438	.supports_sdio_new_mode = false,
	439	.has_control_mask = true,
	440	.can_dump_fw = false,
	441	.can_auto_tdls = false,
1fe192d8	442	.can_ext_scan = true,
05889f82 AK	443	};
	444
	445	static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
	446	.firmware = SD8797_DEFAULT_FW_NAME,
	447	.reg = &mwifiex_reg_sd87xx,
	448	.max_ports = 16,
	449	.mp_agg_pkt_limit = 8,
828cf222	450	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
e1aa93a4 AK	451	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
e1aa93a4 AK	452	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
b4e8aebb AP	453	.supports_sdio_new_mode = false,
	454	.has_control_mask = true,
	455	.can_dump_fw = false,
	456	.can_auto_tdls = false,
1fe192d8	457	.can_ext_scan = true,
b60186f8 YAP	458	};
	459
	460	static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
	461	.firmware = SD8897_DEFAULT_FW_NAME,
	462	.reg = &mwifiex_reg_sd8897,
	463	.max_ports = 32,
	464	.mp_agg_pkt_limit = 16,
828cf222	465	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
ea44f4d0 AP	466	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
ea44f4d0 AP	467	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
b4e8aebb AP	468	.supports_sdio_new_mode = true,
	469	.has_control_mask = false,
	470	.can_dump_fw = true,
	471	.can_auto_tdls = false,
1fe192d8	472	.can_ext_scan = true,
05889f82 AK	473	};
05889f82 AK	474
030bb75a AP	475	static const struct mwifiex_sdio_device mwifiex_sdio_sd8887 = {
	476	.firmware = SD8887_DEFAULT_FW_NAME,
	477	.reg = &mwifiex_reg_sd8887,
	478	.max_ports = 32,
	479	.mp_agg_pkt_limit = 16,
1c4c24eb	480	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
030bb75a AP	481	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
030bb75a AP	482	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
b4e8aebb AP	483	.supports_sdio_new_mode = true,
	484	.has_control_mask = false,
	485	.can_dump_fw = false,
	486	.can_auto_tdls = true,
1fe192d8	487	.can_ext_scan = true,
030bb75a AP	488	};
030bb75a AP	489
52bd3d20 YAP	490	static const struct mwifiex_sdio_device mwifiex_sdio_sd8801 = {
	491	.firmware = SD8801_DEFAULT_FW_NAME,
	492	.reg = &mwifiex_reg_sd87xx,
	493	.max_ports = 16,
	494	.mp_agg_pkt_limit = 8,
	495	.supports_sdio_new_mode = false,
	496	.has_control_mask = true,
	497	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
	498	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
	499	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
b4e8aebb AP	500	.can_dump_fw = false,
b4e8aebb AP	501	.can_auto_tdls = false,
1fe192d8	502	.can_ext_scan = true,
52bd3d20 YAP	503	};
52bd3d20 YAP	504
d930faee AK	505	/*
	506	* .cmdrsp_complete handler
	507	*/
	508	static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
	509	struct sk_buff *skb)
	510	{
	511	dev_kfree_skb_any(skb);
	512	return 0;
	513	}
	514
	515	/*
	516	* .event_complete handler
	517	*/
	518	static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
	519	struct sk_buff *skb)
	520	{
	521	dev_kfree_skb_any(skb);
	522	return 0;
	523	}
	524
c23b7c8f AK	525	static inline bool
	526	mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
	527	{
	528	u8 tmp;
	529
	530	if (card->curr_rd_port < card->mpa_rx.start_port) {
b60186f8 YAP	531	if (card->supports_sdio_new_mode)
	532	tmp = card->mp_end_port >> 1;
	533	else
	534	tmp = card->mp_agg_pkt_limit;
c23b7c8f AK	535
	536	if (((card->max_ports - card->mpa_rx.start_port) +
	537	card->curr_rd_port) >= tmp)
	538	return true;
	539	}
	540
b60186f8 YAP	541	if (!card->supports_sdio_new_mode)
	542	return false;
	543
	544	if ((card->curr_rd_port - card->mpa_rx.start_port) >=
	545	(card->mp_end_port >> 1))
	546	return true;
	547
c23b7c8f AK	548	return false;
	549	}
	550
	551	static inline bool
	552	mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
	553	{
	554	u16 tmp;
	555
	556	if (card->curr_wr_port < card->mpa_tx.start_port) {
b60186f8 YAP	557	if (card->supports_sdio_new_mode)
	558	tmp = card->mp_end_port >> 1;
	559	else
	560	tmp = card->mp_agg_pkt_limit;
c23b7c8f AK	561
	562	if (((card->max_ports - card->mpa_tx.start_port) +
	563	card->curr_wr_port) >= tmp)
	564	return true;
	565	}
	566
b60186f8 YAP	567	if (!card->supports_sdio_new_mode)
	568	return false;
	569
	570	if ((card->curr_wr_port - card->mpa_tx.start_port) >=
	571	(card->mp_end_port >> 1))
	572	return true;
	573
c23b7c8f AK	574	return false;
	575	}
	576
	577	/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
	578	static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
960d6d08	579	u16 rx_len, u8 port)
c23b7c8f	580	{
960d6d08	581	card->mpa_rx.buf_len += rx_len;
c23b7c8f AK	582
	583	if (!card->mpa_rx.pkt_cnt)
	584	card->mpa_rx.start_port = port;
	585
b60186f8 YAP	586	if (card->supports_sdio_new_mode) {
	587	card->mpa_rx.ports \|= (1 << port);
	588	} else {
	589	if (card->mpa_rx.start_port <= port)
	590	card->mpa_rx.ports \|= 1 << (card->mpa_rx.pkt_cnt);
	591	else
	592	card->mpa_rx.ports \|= 1 << (card->mpa_rx.pkt_cnt + 1);
	593	}
960d6d08 ZL	594	card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL;
960d6d08 ZL	595	card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len;
c23b7c8f AK	596	card->mpa_rx.pkt_cnt++;
c23b7c8f AK	597	}
5e6e3a92	598	#endif /* _MWIFIEX_SDIO_H */