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brcmutil: add dequeue function with filtering
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a5fb297d 5 * Copyright (C) 2008, 2009, 2010 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
a6b7a407 13#include <linux/interrupt.h>
a66098da
LB		 14#include <linux/module.h>
15#include <linux/kernel.h>
3d76e82c 16#include <linux/sched.h>
a66098da
LB		 17#include <linux/spinlock.h>
18#include <linux/list.h>
19#include <linux/pci.h>
20#include <linux/delay.h>
21#include <linux/completion.h>
22#include <linux/etherdevice.h>
5a0e3ad6 23#include <linux/slab.h>
a66098da
LB		 24#include <net/mac80211.h>
25#include <linux/moduleparam.h>
26#include <linux/firmware.h>
27#include <linux/workqueue.h>
28
29#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
30#define MWL8K_NAME KBUILD_MODNAME
00e8e692 31#define MWL8K_VERSION "0.13"
a66098da 32
0863ade8 33/* Module parameters */
eb939922 34static bool ap_mode_default;
0863ade8
BC		 35module_param(ap_mode_default, bool, 0);
36MODULE_PARM_DESC(ap_mode_default,
37 "Set to 1 to make ap mode the default instead of sta mode");
38
a66098da
LB		 39/* Register definitions */
40#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 41#define MWL8K_MODE_STA 0x0000005a
42#define MWL8K_MODE_AP 0x000000a5
a66098da 43#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 44#define MWL8K_FWSTA_READY 0xf0f1f2f4
45#define MWL8K_FWAP_READY 0xf1f2f4a5
46#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 47#define MWL8K_HIU_SCRATCH 0x00000c40
48
49/* Host->device communications */
50#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
51#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
52#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
53#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
54#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 55#define MWL8K_H2A_INT_DUMMY (1 << 20)
56#define MWL8K_H2A_INT_RESET (1 << 15)
57#define MWL8K_H2A_INT_DOORBELL (1 << 1)
58#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 59
60/* Device->host communications */
61#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
62#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
63#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
64#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
65#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b 66#define MWL8K_A2H_INT_DUMMY (1 << 20)
3aefc37e 67#define MWL8K_A2H_INT_BA_WATCHDOG (1 << 14)
ce9e2e1b
LB		 68#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
69#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
70#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
71#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
72#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
73#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
74#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
75#define MWL8K_A2H_INT_RX_READY (1 << 1)
76#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da 77
566875db
PN		 78/* HW micro second timer register
79 * located at offset 0xA600. This
80 * will be used to timestamp tx
81 * packets.
82 */
83
84#define MWL8K_HW_TIMER_REGISTER 0x0000a600
85
a66098da
LB		 86#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
87 MWL8K_A2H_INT_CHNL_SWITCHED | \
88 MWL8K_A2H_INT_QUEUE_EMPTY | \
89 MWL8K_A2H_INT_RADAR_DETECT | \
90 MWL8K_A2H_INT_RADIO_ON | \
91 MWL8K_A2H_INT_RADIO_OFF | \
92 MWL8K_A2H_INT_MAC_EVENT | \
93 MWL8K_A2H_INT_OPC_DONE | \
94 MWL8K_A2H_INT_RX_READY | \
3aefc37e
NS		 95 MWL8K_A2H_INT_TX_DONE | \
96 MWL8K_A2H_INT_BA_WATCHDOG)
a66098da 97
a66098da 98#define MWL8K_RX_QUEUES 1
e600707b 99#define MWL8K_TX_WMM_QUEUES 4
8a7a578c 100#define MWL8K_MAX_AMPDU_QUEUES 8
e600707b
BC		 101#define MWL8K_MAX_TX_QUEUES (MWL8K_TX_WMM_QUEUES + MWL8K_MAX_AMPDU_QUEUES)
102#define mwl8k_tx_queues(priv) (MWL8K_TX_WMM_QUEUES + (priv)->num_ampdu_queues)
a66098da 103
7fb978b7
YAP		 104/* txpriorities are mapped with hw queues.
105 * Each hw queue has a txpriority.
106 */
107#define TOTAL_HW_TX_QUEUES 8
108
109/* Each HW queue can have one AMPDU stream.
110 * But, because one of the hw queue is reserved,
111 * maximum AMPDU queues that can be created are
112 * one short of total tx queues.
113 */
114#define MWL8K_NUM_AMPDU_STREAMS (TOTAL_HW_TX_QUEUES - 1)
115
54bc3a0d
LB		 116struct rxd_ops {
117 int rxd_size;
118 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
119 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d 120 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
0d462bbb 121 __le16 *qos, s8 *noise);
54bc3a0d
LB		 122};
123
45a390dd 124struct mwl8k_device_info {
a74b295e
LB		 125 char *part_name;
126 char *helper_image;
0863ade8
BC		 127 char *fw_image_sta;
128 char *fw_image_ap;
89a91f4f 129 struct rxd_ops *ap_rxd_ops;
952a0e96 130 u32 fw_api_ap;
45a390dd
LB		 131};
132
a66098da 133struct mwl8k_rx_queue {
45eb400d 134 int rxd_count;
a66098da
LB		 135
136 /* hw receives here */
45eb400d 137 int head;
a66098da
LB		 138
139 /* refill descs here */
45eb400d 140 int tail;
a66098da 141
54bc3a0d 142 void *rxd;
45eb400d 143 dma_addr_t rxd_dma;
788838eb
LB		 144 struct {
145 struct sk_buff *skb;
53b1b3e1 146 DEFINE_DMA_UNMAP_ADDR(dma);
788838eb 147 } *buf;
a66098da
LB		 148};
149
a66098da
LB		 150struct mwl8k_tx_queue {
151 /* hw transmits here */
45eb400d 152 int head;
a66098da
LB		 153
154 /* sw appends here */
45eb400d 155 int tail;
a66098da 156
8ccbc3b8 157 unsigned int len;
45eb400d
LB		 158 struct mwl8k_tx_desc *txd;
159 dma_addr_t txd_dma;
160 struct sk_buff **skb;
a66098da
LB		 161};
162
ac109fd0
BC		 163enum {
164 AMPDU_NO_STREAM,
165 AMPDU_STREAM_NEW,
166 AMPDU_STREAM_IN_PROGRESS,
167 AMPDU_STREAM_ACTIVE,
168};
169
5faa1aff
NS		 170struct mwl8k_ampdu_stream {
171 struct ieee80211_sta *sta;
172 u8 tid;
173 u8 state;
174 u8 idx;
5faa1aff
NS		 175};
176
a66098da 177struct mwl8k_priv {
a66098da 178 struct ieee80211_hw *hw;
a66098da 179 struct pci_dev *pdev;
bf3ca7f7 180 int irq;
a66098da 181
45a390dd
LB		 182 struct mwl8k_device_info *device_info;
183
be695fc4
LB		 184 void __iomem *sram;
185 void __iomem *regs;
186
187 /* firmware */
d1f9e41d
BC		 188 const struct firmware *fw_helper;
189 const struct firmware *fw_ucode;
a66098da 190
be695fc4
LB		 191 /* hardware/firmware parameters */
192 bool ap_fw;
193 struct rxd_ops *rxd_ops;
777ad375
LB		 194 struct ieee80211_supported_band band_24;
195 struct ieee80211_channel channels_24[14];
196 struct ieee80211_rate rates_24[14];
4eae9edd
LB		 197 struct ieee80211_supported_band band_50;
198 struct ieee80211_channel channels_50[4];
199 struct ieee80211_rate rates_50[9];
ee0ddf18
LB		 200 u32 ap_macids_supported;
201 u32 sta_macids_supported;
be695fc4 202
8a7a578c
BC		 203 /* Ampdu stream information */
204 u8 num_ampdu_queues;
ac109fd0
BC		 205 spinlock_t stream_lock;
206 struct mwl8k_ampdu_stream ampdu[MWL8K_MAX_AMPDU_QUEUES];
3aefc37e 207 struct work_struct watchdog_ba_handle;
8a7a578c 208
618952a7
LB		 209 /* firmware access */
210 struct mutex fw_mutex;
211 struct task_struct *fw_mutex_owner;
6b6accc3 212 struct task_struct *hw_restart_owner;
618952a7 213 int fw_mutex_depth;
618952a7
LB		 214 struct completion *hostcmd_wait;
215
c27a54d3
YAP		 216 atomic_t watchdog_event_pending;
217
a66098da
LB		 218 /* lock held over TX and TX reap */
219 spinlock_t tx_lock;
a66098da 220
88de754a
LB		 221 /* TX quiesce completion, protected by fw_mutex and tx_lock */
222 struct completion *tx_wait;
223
f5bb87cf 224 /* List of interfaces. */
ee0ddf18 225 u32 macids_used;
f5bb87cf 226 struct list_head vif_list;
a66098da 227
a66098da
LB		 228 /* power management status cookie from firmware */
229 u32 *cookie;
230 dma_addr_t cookie_dma;
231
232 u16 num_mcaddrs;
a66098da 233 u8 hw_rev;
2aa7b01f 234 u32 fw_rev;
a66098da
LB		 235
236 /*
237 * Running count of TX packets in flight, to avoid
238 * iterating over the transmit rings each time.
239 */
240 int pending_tx_pkts;
241
242 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
e600707b
BC		 243 struct mwl8k_tx_queue txq[MWL8K_MAX_TX_QUEUES];
244 u32 txq_offset[MWL8K_MAX_TX_QUEUES];
a66098da 245
c46563b7 246 bool radio_on;
68ce3884 247 bool radio_short_preamble;
a43c49a8 248 bool sniffer_enabled;
0439b1f5 249 bool wmm_enabled;
a66098da 250
a66098da
LB		 251 /* XXX need to convert this to handle multiple interfaces */
252 bool capture_beacon;
d89173f2 253 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 254 struct sk_buff *beacon_skb;
255
256 /*
257 * This FJ worker has to be global as it is scheduled from the
258 * RX handler. At this point we don't know which interface it
259 * belongs to until the list of bssids waiting to complete join
260 * is checked.
261 */
262 struct work_struct finalize_join_worker;
263
1e9f9de3
LB		 264 /* Tasklet to perform TX reclaim. */
265 struct tasklet_struct poll_tx_task;
67e2eb27
LB		 266
267 /* Tasklet to perform RX. */
268 struct tasklet_struct poll_rx_task;
0d462bbb
JL		 269
270 /* Most recently reported noise in dBm */
271 s8 noise;
0863ade8
BC		 272
273 /*
274 * preserve the queue configurations so they can be restored if/when
275 * the firmware image is swapped.
276 */
e600707b 277 struct ieee80211_tx_queue_params wmm_params[MWL8K_TX_WMM_QUEUES];
99020471 278
6b6accc3
YAP		 279 /* To perform the task of reloading the firmware */
280 struct work_struct fw_reload;
281 bool hw_restart_in_progress;
282
99020471
BC		 283 /* async firmware loading state */
284 unsigned fw_state;
285 char *fw_pref;
286 char *fw_alt;
98929824 287 bool is_8764;
99020471 288 struct completion firmware_loading_complete;
e882efc9
YAP		 289
290 /* bitmap of running BSSes */
291 u32 running_bsses;
a66098da
LB		 292};
293
e53d9b96
NS		 294#define MAX_WEP_KEY_LEN 13
295#define NUM_WEP_KEYS 4
296
a66098da
LB		 297/* Per interface specific private data */
298struct mwl8k_vif {
f5bb87cf
LB		 299 struct list_head list;
300 struct ieee80211_vif *vif;
301
f57ca9c1
LB		 302 /* Firmware macid for this vif. */
303 int macid;
304
c2c2b12a 305 /* Non AMPDU sequence number assigned by driver. */
a680400e 306 u16 seqno;
e53d9b96
NS		 307
308 /* Saved WEP keys */
309 struct {
310 u8 enabled;
311 u8 key[sizeof(struct ieee80211_key_conf) + MAX_WEP_KEY_LEN];
312 } wep_key_conf[NUM_WEP_KEYS];
d9a07d49
NS		 313
314 /* BSSID */
315 u8 bssid[ETH_ALEN];
316
317 /* A flag to indicate is HW crypto is enabled for this bssid */
318 bool is_hw_crypto_enabled;
a66098da 319};
a94cc97e 320#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
fcdc403c 321#define IEEE80211_KEY_CONF(_u8) ((struct ieee80211_key_conf *)(_u8))
a66098da 322
d0805c1c
BC		 323struct tx_traffic_info {
324 u32 start_time;
325 u32 pkts;
326};
327
328#define MWL8K_MAX_TID 8
a680400e
LB		 329struct mwl8k_sta {
330 /* Index into station database. Returned by UPDATE_STADB. */
331 u8 peer_id;
17033543 332 u8 is_ampdu_allowed;
d0805c1c 333 struct tx_traffic_info tx_stats[MWL8K_MAX_TID];
a680400e
LB		 334};
335#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
336
777ad375 337static const struct ieee80211_channel mwl8k_channels_24[] = {
d786f67e
JG		 338 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412, .hw_value = 1, },
339 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417, .hw_value = 2, },
340 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422, .hw_value = 3, },
341 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427, .hw_value = 4, },
342 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432, .hw_value = 5, },
343 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437, .hw_value = 6, },
344 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442, .hw_value = 7, },
345 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447, .hw_value = 8, },
346 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452, .hw_value = 9, },
347 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457, .hw_value = 10, },
348 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462, .hw_value = 11, },
349 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467, .hw_value = 12, },
350 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472, .hw_value = 13, },
351 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 352};
353
777ad375 354static const struct ieee80211_rate mwl8k_rates_24[] = {
a66098da
LB		 355 { .bitrate = 10, .hw_value = 2, },
356 { .bitrate = 20, .hw_value = 4, },
357 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 358 { .bitrate = 110, .hw_value = 22, },
359 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 360 { .bitrate = 60, .hw_value = 12, },
361 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 362 { .bitrate = 120, .hw_value = 24, },
363 { .bitrate = 180, .hw_value = 36, },
364 { .bitrate = 240, .hw_value = 48, },
365 { .bitrate = 360, .hw_value = 72, },
366 { .bitrate = 480, .hw_value = 96, },
367 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 368 { .bitrate = 720, .hw_value = 144, },
369};
370
4eae9edd 371static const struct ieee80211_channel mwl8k_channels_50[] = {
d786f67e
JG		 372 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5180, .hw_value = 36, },
373 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5200, .hw_value = 40, },
374 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5220, .hw_value = 44, },
375 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5240, .hw_value = 48, },
4eae9edd
LB		 376};
377
378static const struct ieee80211_rate mwl8k_rates_50[] = {
379 { .bitrate = 60, .hw_value = 12, },
380 { .bitrate = 90, .hw_value = 18, },
381 { .bitrate = 120, .hw_value = 24, },
382 { .bitrate = 180, .hw_value = 36, },
383 { .bitrate = 240, .hw_value = 48, },
384 { .bitrate = 360, .hw_value = 72, },
385 { .bitrate = 480, .hw_value = 96, },
386 { .bitrate = 540, .hw_value = 108, },
387 { .bitrate = 720, .hw_value = 144, },
388};
389
a66098da 390/* Set or get info from Firmware */
a66098da 391#define MWL8K_CMD_GET 0x0000
41fdf097
NS		 392#define MWL8K_CMD_SET 0x0001
393#define MWL8K_CMD_SET_LIST 0x0002
a66098da
LB		 394
395/* Firmware command codes */
396#define MWL8K_CMD_CODE_DNLD 0x0001
397#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 398#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 399#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
400#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 401#define MWL8K_CMD_RADIO_CONTROL 0x001c
402#define MWL8K_CMD_RF_TX_POWER 0x001e
41fdf097 403#define MWL8K_CMD_TX_POWER 0x001f
08b06347 404#define MWL8K_CMD_RF_ANTENNA 0x0020
aa21d0f6 405#define MWL8K_CMD_SET_BEACON 0x0100 /* per-vif */
a66098da
LB		 406#define MWL8K_CMD_SET_PRE_SCAN 0x0107
407#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 408#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
409#define MWL8K_CMD_SET_AID 0x010d
410#define MWL8K_CMD_SET_RATE 0x0110
411#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
412#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 413#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 414#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
415#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 416#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 417#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 418#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
aa21d0f6 419#define MWL8K_CMD_SET_MAC_ADDR 0x0202 /* per-vif */
a66098da 420#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
3aefc37e 421#define MWL8K_CMD_GET_WATCHDOG_BITMAP 0x0205
197a4e4e 422#define MWL8K_CMD_DEL_MAC_ADDR 0x0206 /* per-vif */
aa21d0f6
LB		 423#define MWL8K_CMD_BSS_START 0x1100 /* per-vif */
424#define MWL8K_CMD_SET_NEW_STN 0x1111 /* per-vif */
fcdc403c 425#define MWL8K_CMD_UPDATE_ENCRYPTION 0x1122 /* per-vif */
ff45fc60 426#define MWL8K_CMD_UPDATE_STADB 0x1123
5faa1aff 427#define MWL8K_CMD_BASTREAM 0x1125
a66098da 428
b603742f 429static const char *mwl8k_cmd_name(__le16 cmd, char *buf, int bufsize)
a66098da 430{
b603742f
JL		 431 u16 command = le16_to_cpu(cmd);
432
a66098da
LB		 433#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
434 snprintf(buf, bufsize, "%s", #x);\
435 return buf;\
436 } while (0)
b603742f 437 switch (command & ~0x8000) {
a66098da
LB		 438 MWL8K_CMDNAME(CODE_DNLD);
439 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 440 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 441 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
442 MWL8K_CMDNAME(GET_STAT);
443 MWL8K_CMDNAME(RADIO_CONTROL);
444 MWL8K_CMDNAME(RF_TX_POWER);
41fdf097 445 MWL8K_CMDNAME(TX_POWER);
08b06347 446 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 447 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB		 448 MWL8K_CMDNAME(SET_PRE_SCAN);
449 MWL8K_CMDNAME(SET_POST_SCAN);
450 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 451 MWL8K_CMDNAME(SET_AID);
452 MWL8K_CMDNAME(SET_RATE);
453 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
454 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 455 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 456 MWL8K_CMDNAME(SET_EDCA_PARAMS);
457 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 458 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 459 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 460 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 461 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 462 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 463 MWL8K_CMDNAME(BSS_START);
3f5610ff 464 MWL8K_CMDNAME(SET_NEW_STN);
fcdc403c 465 MWL8K_CMDNAME(UPDATE_ENCRYPTION);
ff45fc60 466 MWL8K_CMDNAME(UPDATE_STADB);
5faa1aff 467 MWL8K_CMDNAME(BASTREAM);
3aefc37e 468 MWL8K_CMDNAME(GET_WATCHDOG_BITMAP);
a66098da
LB		 469 default:
470 snprintf(buf, bufsize, "0x%x", cmd);
471 }
472#undef MWL8K_CMDNAME
473
474 return buf;
475}
476
477/* Hardware and firmware reset */
478static void mwl8k_hw_reset(struct mwl8k_priv *priv)
479{
480 iowrite32(MWL8K_H2A_INT_RESET,
481 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
482 iowrite32(MWL8K_H2A_INT_RESET,
483 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
484 msleep(20);
485}
486
487/* Release fw image */
d1f9e41d 488static void mwl8k_release_fw(const struct firmware **fw)
a66098da
LB		 489{
490 if (*fw == NULL)
491 return;
492 release_firmware(*fw);
493 *fw = NULL;
494}
495
496static void mwl8k_release_firmware(struct mwl8k_priv *priv)
497{
22be40d9
LB		 498 mwl8k_release_fw(&priv->fw_ucode);
499 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 500}
501
99020471
BC		 502/* states for asynchronous f/w loading */
503static void mwl8k_fw_state_machine(const struct firmware *fw, void *context);
504enum {
505 FW_STATE_INIT = 0,
506 FW_STATE_LOADING_PREF,
507 FW_STATE_LOADING_ALT,
508 FW_STATE_ERROR,
509};
510
a66098da
LB		 511/* Request fw image */
512static int mwl8k_request_fw(struct mwl8k_priv *priv,
d1f9e41d 513 const char *fname, const struct firmware **fw,
99020471 514 bool nowait)
a66098da
LB		 515{
516 /* release current image */
517 if (*fw != NULL)
518 mwl8k_release_fw(fw);
519
99020471
BC		 520 if (nowait)
521 return request_firmware_nowait(THIS_MODULE, 1, fname,
522 &priv->pdev->dev, GFP_KERNEL,
523 priv, mwl8k_fw_state_machine);
524 else
d1f9e41d 525 return request_firmware(fw, fname, &priv->pdev->dev);
a66098da
LB		 526}
527
99020471
BC		 528static int mwl8k_request_firmware(struct mwl8k_priv *priv, char *fw_image,
529 bool nowait)
a66098da 530{
a74b295e 531 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 532 int rc;
533
a74b295e 534 if (di->helper_image != NULL) {
99020471
BC		 535 if (nowait)
536 rc = mwl8k_request_fw(priv, di->helper_image,
537 &priv->fw_helper, true);
538 else
539 rc = mwl8k_request_fw(priv, di->helper_image,
540 &priv->fw_helper, false);
541 if (rc)
542 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
543 pci_name(priv->pdev), di->helper_image);
544
545 if (rc || nowait)
a74b295e 546 return rc;
a66098da
LB		 547 }
548
99020471
BC		 549 if (nowait) {
550 /*
551 * if we get here, no helper image is needed. Skip the
552 * FW_STATE_INIT state.
553 */
554 priv->fw_state = FW_STATE_LOADING_PREF;
555 rc = mwl8k_request_fw(priv, fw_image,
556 &priv->fw_ucode,
557 true);
558 } else
559 rc = mwl8k_request_fw(priv, fw_image,
560 &priv->fw_ucode, false);
a66098da 561 if (rc) {
c2c357ce 562 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
0863ade8 563 pci_name(priv->pdev), fw_image);
22be40d9 564 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 565 return rc;
566 }
567
568 return 0;
569}
570
571struct mwl8k_cmd_pkt {
572 __le16 code;
573 __le16 length;
f57ca9c1
LB		 574 __u8 seq_num;
575 __u8 macid;
a66098da
LB		 576 __le16 result;
577 char payload[0];
ba2d3587 578} __packed;
a66098da
LB		 579
580/*
581 * Firmware loading.
582 */
583static int
584mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
585{
586 void __iomem *regs = priv->regs;
587 dma_addr_t dma_addr;
a66098da
LB		 588 int loops;
589
590 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
591 if (pci_dma_mapping_error(priv->pdev, dma_addr))
592 return -ENOMEM;
593
594 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
595 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
596 iowrite32(MWL8K_H2A_INT_DOORBELL,
597 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
598 iowrite32(MWL8K_H2A_INT_DUMMY,
599 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
600
a66098da
LB		 601 loops = 1000;
602 do {
603 u32 int_code;
98929824
NS		 604 if (priv->is_8764) {
605 int_code = ioread32(regs +
606 MWL8K_HIU_H2A_INTERRUPT_STATUS);
607 if (int_code == 0)
608 break;
609 } else {
610 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
611 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
612 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
613 break;
614 }
a66098da 615 }
3d76e82c 616 cond_resched();
a66098da
LB		 617 udelay(1);
618 } while (--loops);
619
620 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
621
d4b70570 622 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 623}
624
625static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
626 const u8 *data, size_t length)
627{
628 struct mwl8k_cmd_pkt *cmd;
629 int done;
630 int rc = 0;
631
632 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
633 if (cmd == NULL)
634 return -ENOMEM;
635
636 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
637 cmd->seq_num = 0;
f57ca9c1 638 cmd->macid = 0;
a66098da
LB		 639 cmd->result = 0;
640
641 done = 0;
642 while (length) {
643 int block_size = length > 256 ? 256 : length;
644
645 memcpy(cmd->payload, data + done, block_size);
646 cmd->length = cpu_to_le16(block_size);
647
648 rc = mwl8k_send_fw_load_cmd(priv, cmd,
649 sizeof(*cmd) + block_size);
650 if (rc)
651 break;
652
653 done += block_size;
654 length -= block_size;
655 }
656
657 if (!rc) {
658 cmd->length = 0;
659 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
660 }
661
662 kfree(cmd);
663
664 return rc;
665}
666
667static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
668 const u8 *data, size_t length)
669{
670 unsigned char *buffer;
671 int may_continue, rc = 0;
672 u32 done, prev_block_size;
673
674 buffer = kmalloc(1024, GFP_KERNEL);
675 if (buffer == NULL)
676 return -ENOMEM;
677
678 done = 0;
679 prev_block_size = 0;
680 may_continue = 1000;
681 while (may_continue > 0) {
682 u32 block_size;
683
684 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
685 if (block_size & 1) {
686 block_size &= ~1;
687 may_continue--;
688 } else {
689 done += prev_block_size;
690 length -= prev_block_size;
691 }
692
693 if (block_size > 1024 || block_size > length) {
694 rc = -EOVERFLOW;
695 break;
696 }
697
698 if (length == 0) {
699 rc = 0;
700 break;
701 }
702
703 if (block_size == 0) {
704 rc = -EPROTO;
705 may_continue--;
706 udelay(1);
707 continue;
708 }
709
710 prev_block_size = block_size;
711 memcpy(buffer, data + done, block_size);
712
713 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
714 if (rc)
715 break;
716 }
717
718 if (!rc && length != 0)
719 rc = -EREMOTEIO;
720
721 kfree(buffer);
722
723 return rc;
724}
725
c2c357ce 726static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 727{
c2c357ce 728 struct mwl8k_priv *priv = hw->priv;
d1f9e41d 729 const struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 730 int rc;
731 int loops;
732
98929824 733 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4) && !priv->is_8764) {
d1f9e41d 734 const struct firmware *helper = priv->fw_helper;
a66098da 735
c2c357ce
LB		 736 if (helper == NULL) {
737 printk(KERN_ERR "%s: helper image needed but none "
738 "given\n", pci_name(priv->pdev));
739 return -EINVAL;
740 }
a66098da 741
c2c357ce 742 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 743 if (rc) {
744 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 745 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 746 return rc;
747 }
ba30c4a5 748 msleep(20);
a66098da 749
c2c357ce 750 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 751 } else {
98929824
NS		 752 if (priv->is_8764)
753 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
754 else
755 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 756 }
757
758 if (rc) {
c2c357ce
LB		 759 printk(KERN_ERR "%s: unable to load firmware image\n",
760 pci_name(priv->pdev));
a66098da
LB		 761 return rc;
762 }
763
89a91f4f 764 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 765
89b872e2 766 loops = 500000;
a66098da 767 do {
eae74e65
LB		 768 u32 ready_code;
769
770 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
771 if (ready_code == MWL8K_FWAP_READY) {
3db1cd5c 772 priv->ap_fw = true;
eae74e65
LB		 773 break;
774 } else if (ready_code == MWL8K_FWSTA_READY) {
3db1cd5c 775 priv->ap_fw = false;
a66098da 776 break;
eae74e65
LB		 777 }
778
779 cond_resched();
a66098da
LB		 780 udelay(1);
781 } while (--loops);
782
783 return loops ? 0 : -ETIMEDOUT;
784}
785
786
a66098da
LB		 787/* DMA header used by firmware and hardware. */
788struct mwl8k_dma_data {
789 __le16 fwlen;
790 struct ieee80211_hdr wh;
20f09c3d 791 char data[0];
ba2d3587 792} __packed;
a66098da
LB		 793
794/* Routines to add/remove DMA header from skb. */
20f09c3d 795static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 796{
20f09c3d
LB		 797 struct mwl8k_dma_data *tr;
798 int hdrlen;
799
800 tr = (struct mwl8k_dma_data *)skb->data;
801 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
802
803 if (hdrlen != sizeof(tr->wh)) {
804 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
805 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
806 *((__le16 *)(tr->data - 2)) = qos;
807 } else {
808 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
809 }
a66098da 810 }
20f09c3d
LB		 811
812 if (hdrlen != sizeof(*tr))
813 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 814}
815
ff776cec
YAP		 816#define REDUCED_TX_HEADROOM 8
817
252486a1 818static void
e4eefec7
YAP		 819mwl8k_add_dma_header(struct mwl8k_priv *priv, struct sk_buff *skb,
820 int head_pad, int tail_pad)
a66098da
LB		 821{
822 struct ieee80211_hdr *wh;
ca009301 823 int hdrlen;
252486a1 824 int reqd_hdrlen;
a66098da
LB		 825 struct mwl8k_dma_data *tr;
826
ca009301
LB		 827 /*
828 * Add a firmware DMA header; the firmware requires that we
829 * present a 2-byte payload length followed by a 4-address
830 * header (without QoS field), followed (optionally) by any
831 * WEP/ExtIV header (but only filled in for CCMP).
832 */
a66098da 833 wh = (struct ieee80211_hdr *)skb->data;
ca009301 834
a66098da 835 hdrlen = ieee80211_hdrlen(wh->frame_control);
ff776cec
YAP		 836
837 /*
838 * Check if skb_resize is required because of
839 * tx_headroom adjustment.
840 */
841 if (priv->ap_fw && (hdrlen < (sizeof(struct ieee80211_cts)
842 + REDUCED_TX_HEADROOM))) {
843 if (pskb_expand_head(skb, REDUCED_TX_HEADROOM, 0, GFP_ATOMIC)) {
844
845 wiphy_err(priv->hw->wiphy,
846 "Failed to reallocate TX buffer\n");
847 return;
848 }
849 skb->truesize += REDUCED_TX_HEADROOM;
850 }
851
e4eefec7 852 reqd_hdrlen = sizeof(*tr) + head_pad;
252486a1
NS		 853
854 if (hdrlen != reqd_hdrlen)
855 skb_push(skb, reqd_hdrlen - hdrlen);
a66098da 856
ca009301 857 if (ieee80211_is_data_qos(wh->frame_control))
252486a1 858 hdrlen -= IEEE80211_QOS_CTL_LEN;
a66098da
LB		 859
860 tr = (struct mwl8k_dma_data *)skb->data;
861 if (wh != &tr->wh)
862 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 863 if (hdrlen != sizeof(tr->wh))
864 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 865
866 /*
867 * Firmware length is the length of the fully formed "802.11
868 * payload". That is, everything except for the 802.11 header.
869 * This includes all crypto material including the MIC.
870 */
252486a1 871 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr) + tail_pad);
a66098da
LB		 872}
873
ff776cec
YAP		 874static void mwl8k_encapsulate_tx_frame(struct mwl8k_priv *priv,
875 struct sk_buff *skb)
e53d9b96
NS		 876{
877 struct ieee80211_hdr *wh;
878 struct ieee80211_tx_info *tx_info;
879 struct ieee80211_key_conf *key_conf;
880 int data_pad;
e4eefec7 881 int head_pad = 0;
e53d9b96
NS		 882
883 wh = (struct ieee80211_hdr *)skb->data;
884
885 tx_info = IEEE80211_SKB_CB(skb);
886
887 key_conf = NULL;
888 if (ieee80211_is_data(wh->frame_control))
889 key_conf = tx_info->control.hw_key;
890
891 /*
892 * Make sure the packet header is in the DMA header format (4-address
e4eefec7 893 * without QoS), and add head & tail padding when HW crypto is enabled.
e53d9b96
NS		 894 *
895 * We have the following trailer padding requirements:
896 * - WEP: 4 trailer bytes (ICV)
897 * - TKIP: 12 trailer bytes (8 MIC + 4 ICV)
898 * - CCMP: 8 trailer bytes (MIC)
899 */
900 data_pad = 0;
901 if (key_conf != NULL) {
e4eefec7 902 head_pad = key_conf->iv_len;
e53d9b96
NS		 903 switch (key_conf->cipher) {
904 case WLAN_CIPHER_SUITE_WEP40:
905 case WLAN_CIPHER_SUITE_WEP104:
906 data_pad = 4;
907 break;
908 case WLAN_CIPHER_SUITE_TKIP:
909 data_pad = 12;
910 break;
911 case WLAN_CIPHER_SUITE_CCMP:
912 data_pad = 8;
913 break;
914 }
915 }
e4eefec7 916 mwl8k_add_dma_header(priv, skb, head_pad, data_pad);
e53d9b96 917}
a66098da
LB		 918
919/*
d926dc7d 920 * Packet reception for 88w8366/88w8764 AP firmware.
6f6d1e9a 921 */
d926dc7d 922struct mwl8k_rxd_ap {
6f6d1e9a
LB		 923 __le16 pkt_len;
924 __u8 sq2;
925 __u8 rate;
926 __le32 pkt_phys_addr;
927 __le32 next_rxd_phys_addr;
928 __le16 qos_control;
929 __le16 htsig2;
930 __le32 hw_rssi_info;
931 __le32 hw_noise_floor_info;
932 __u8 noise_floor;
933 __u8 pad0[3];
934 __u8 rssi;
935 __u8 rx_status;
936 __u8 channel;
937 __u8 rx_ctrl;
ba2d3587 938} __packed;
6f6d1e9a 939
d926dc7d
NS		 940#define MWL8K_AP_RATE_INFO_MCS_FORMAT 0x80
941#define MWL8K_AP_RATE_INFO_40MHZ 0x40
942#define MWL8K_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 943
d926dc7d 944#define MWL8K_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 945
d926dc7d
NS		 946/* 8366/8764 AP rx_status bits */
947#define MWL8K_AP_RXSTAT_DECRYPT_ERR_MASK 0x80
948#define MWL8K_AP_RXSTAT_GENERAL_DECRYPT_ERR 0xFF
949#define MWL8K_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR 0x02
950#define MWL8K_AP_RXSTAT_WEP_DECRYPT_ICV_ERR 0x04
951#define MWL8K_AP_RXSTAT_TKIP_DECRYPT_ICV_ERR 0x08
d9a07d49 952
d926dc7d 953static void mwl8k_rxd_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 954{
d926dc7d 955 struct mwl8k_rxd_ap *rxd = _rxd;
6f6d1e9a
LB		 956
957 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
d926dc7d 958 rxd->rx_ctrl = MWL8K_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 959}
960
d926dc7d 961static void mwl8k_rxd_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 962{
d926dc7d 963 struct mwl8k_rxd_ap *rxd = _rxd;
6f6d1e9a
LB		 964
965 rxd->pkt_len = cpu_to_le16(len);
966 rxd->pkt_phys_addr = cpu_to_le32(addr);
967 wmb();
968 rxd->rx_ctrl = 0;
969}
970
971static int
d926dc7d
NS		 972mwl8k_rxd_ap_process(void *_rxd, struct ieee80211_rx_status *status,
973 __le16 *qos, s8 *noise)
6f6d1e9a 974{
d926dc7d 975 struct mwl8k_rxd_ap *rxd = _rxd;
6f6d1e9a 976
d926dc7d 977 if (!(rxd->rx_ctrl & MWL8K_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 978 return -1;
979 rmb();
980
981 memset(status, 0, sizeof(*status));
982
983 status->signal = -rxd->rssi;
0d462bbb 984 *noise = -rxd->noise_floor;
6f6d1e9a 985
d926dc7d 986 if (rxd->rate & MWL8K_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 987 status->flag |= RX_FLAG_HT;
d926dc7d 988 if (rxd->rate & MWL8K_AP_RATE_INFO_40MHZ)
8e9f33f0 989 status->flag |= RX_FLAG_40MHZ;
d926dc7d 990 status->rate_idx = MWL8K_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 991 } else {
992 int i;
993
777ad375
LB		 994 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
995 if (mwl8k_rates_24[i].hw_value == rxd->rate) {
6f6d1e9a
LB		 996 status->rate_idx = i;
997 break;
998 }
999 }
1000 }
1001
85478344
LB		 1002 if (rxd->channel > 14) {
1003 status->band = IEEE80211_BAND_5GHZ;
1004 if (!(status->flag & RX_FLAG_HT))
1005 status->rate_idx -= 5;
1006 } else {
1007 status->band = IEEE80211_BAND_2GHZ;
1008 }
59eb21a6
BR		 1009 status->freq = ieee80211_channel_to_frequency(rxd->channel,
1010 status->band);
6f6d1e9a 1011
20f09c3d
LB		 1012 *qos = rxd->qos_control;
1013
d926dc7d
NS		 1014 if ((rxd->rx_status != MWL8K_AP_RXSTAT_GENERAL_DECRYPT_ERR) &&
1015 (rxd->rx_status & MWL8K_AP_RXSTAT_DECRYPT_ERR_MASK) &&
1016 (rxd->rx_status & MWL8K_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR))
d9a07d49
NS		 1017 status->flag |= RX_FLAG_MMIC_ERROR;
1018
6f6d1e9a
LB		 1019 return le16_to_cpu(rxd->pkt_len);
1020}
1021
d926dc7d
NS		 1022static struct rxd_ops rxd_ap_ops = {
1023 .rxd_size = sizeof(struct mwl8k_rxd_ap),
1024 .rxd_init = mwl8k_rxd_ap_init,
1025 .rxd_refill = mwl8k_rxd_ap_refill,
1026 .rxd_process = mwl8k_rxd_ap_process,
6f6d1e9a
LB		 1027};
1028
1029/*
89a91f4f 1030 * Packet reception for STA firmware.
a66098da 1031 */
89a91f4f 1032struct mwl8k_rxd_sta {
a66098da
LB		 1033 __le16 pkt_len;
1034 __u8 link_quality;
1035 __u8 noise_level;
1036 __le32 pkt_phys_addr;
45eb400d 1037 __le32 next_rxd_phys_addr;
a66098da
LB		 1038 __le16 qos_control;
1039 __le16 rate_info;
1040 __le32 pad0[4];
1041 __u8 rssi;
1042 __u8 channel;
1043 __le16 pad1;
1044 __u8 rx_ctrl;
1045 __u8 rx_status;
1046 __u8 pad2[2];
ba2d3587 1047} __packed;
a66098da 1048
89a91f4f
LB		 1049#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
1050#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
1051#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
1052#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
1053#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
1054#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 1055
89a91f4f 1056#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
d9a07d49
NS		 1057#define MWL8K_STA_RX_CTRL_DECRYPT_ERROR 0x04
1058/* ICV=0 or MIC=1 */
1059#define MWL8K_STA_RX_CTRL_DEC_ERR_TYPE 0x08
1060/* Key is uploaded only in failure case */
1061#define MWL8K_STA_RX_CTRL_KEY_INDEX 0x30
54bc3a0d 1062
89a91f4f 1063static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 1064{
89a91f4f 1065 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1066
1067 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 1068 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 1069}
1070
89a91f4f 1071static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 1072{
89a91f4f 1073 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1074
1075 rxd->pkt_len = cpu_to_le16(len);
1076 rxd->pkt_phys_addr = cpu_to_le32(addr);
1077 wmb();
1078 rxd->rx_ctrl = 0;
1079}
1080
1081static int
89a91f4f 1082mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 1083 __le16 *qos, s8 *noise)
54bc3a0d 1084{
89a91f4f 1085 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1086 u16 rate_info;
1087
89a91f4f 1088 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 1089 return -1;
1090 rmb();
1091
1092 rate_info = le16_to_cpu(rxd->rate_info);
1093
1094 memset(status, 0, sizeof(*status));
1095
1096 status->signal = -rxd->rssi;
0d462bbb 1097 *noise = -rxd->noise_level;
89a91f4f
LB		 1098 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
1099 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 1100
89a91f4f 1101 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 1102 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 1103 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 1104 status->flag |= RX_FLAG_40MHZ;
89a91f4f 1105 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 1106 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 1107 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 1108 status->flag |= RX_FLAG_HT;
1109
85478344
LB		 1110 if (rxd->channel > 14) {
1111 status->band = IEEE80211_BAND_5GHZ;
1112 if (!(status->flag & RX_FLAG_HT))
1113 status->rate_idx -= 5;
1114 } else {
1115 status->band = IEEE80211_BAND_2GHZ;
1116 }
59eb21a6
BR		 1117 status->freq = ieee80211_channel_to_frequency(rxd->channel,
1118 status->band);
54bc3a0d 1119
20f09c3d 1120 *qos = rxd->qos_control;
d9a07d49
NS		 1121 if ((rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DECRYPT_ERROR) &&
1122 (rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DEC_ERR_TYPE))
1123 status->flag |= RX_FLAG_MMIC_ERROR;
20f09c3d 1124
54bc3a0d
LB		 1125 return le16_to_cpu(rxd->pkt_len);
1126}
1127
89a91f4f
LB		 1128static struct rxd_ops rxd_sta_ops = {
1129 .rxd_size = sizeof(struct mwl8k_rxd_sta),
1130 .rxd_init = mwl8k_rxd_sta_init,
1131 .rxd_refill = mwl8k_rxd_sta_refill,
1132 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 1133};
1134
1135
a66098da
LB		 1136#define MWL8K_RX_DESCS 256
1137#define MWL8K_RX_MAXSZ 3800
1138
1139static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
1140{
1141 struct mwl8k_priv *priv = hw->priv;
1142 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1143 int size;
1144 int i;
1145
45eb400d
LB		 1146 rxq->rxd_count = 0;
1147 rxq->head = 0;
1148 rxq->tail = 0;
a66098da 1149
54bc3a0d 1150 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 1151
45eb400d
LB		 1152 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
1153 if (rxq->rxd == NULL) {
5db55844 1154 wiphy_err(hw->wiphy, "failed to alloc RX descriptors\n");
a66098da
LB		 1155 return -ENOMEM;
1156 }
45eb400d 1157 memset(rxq->rxd, 0, size);
a66098da 1158
b9ede5f1 1159 rxq->buf = kcalloc(MWL8K_RX_DESCS, sizeof(*rxq->buf), GFP_KERNEL);
788838eb 1160 if (rxq->buf == NULL) {
45eb400d 1161 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 1162 return -ENOMEM;
1163 }
a66098da
LB		 1164
1165 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 1166 int desc_size;
1167 void *rxd;
a66098da 1168 int nexti;
54bc3a0d
LB		 1169 dma_addr_t next_dma_addr;
1170
1171 desc_size = priv->rxd_ops->rxd_size;
1172 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 1173
54bc3a0d
LB		 1174 nexti = i + 1;
1175 if (nexti == MWL8K_RX_DESCS)
1176 nexti = 0;
1177 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 1178
54bc3a0d 1179 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 1180 }
1181
1182 return 0;
1183}
1184
1185static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1186{
1187 struct mwl8k_priv *priv = hw->priv;
1188 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1189 int refilled;
1190
1191 refilled = 0;
45eb400d 1192 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 1193 struct sk_buff *skb;
788838eb 1194 dma_addr_t addr;
a66098da 1195 int rx;
54bc3a0d 1196 void *rxd;
a66098da
LB		 1197
1198 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1199 if (skb == NULL)
1200 break;
1201
788838eb
LB		 1202 addr = pci_map_single(priv->pdev, skb->data,
1203 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1204
54bc3a0d
LB		 1205 rxq->rxd_count++;
1206 rx = rxq->tail++;
1207 if (rxq->tail == MWL8K_RX_DESCS)
1208 rxq->tail = 0;
788838eb 1209 rxq->buf[rx].skb = skb;
53b1b3e1 1210 dma_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 1211
1212 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1213 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 1214
1215 refilled++;
1216 }
1217
1218 return refilled;
1219}
1220
1221/* Must be called only when the card's reception is completely halted */
1222static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1223{
1224 struct mwl8k_priv *priv = hw->priv;
1225 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1226 int i;
1227
73b46320
BC		 1228 if (rxq->rxd == NULL)
1229 return;
1230
a66098da 1231 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 1232 if (rxq->buf[i].skb != NULL) {
1233 pci_unmap_single(priv->pdev,
53b1b3e1 1234 dma_unmap_addr(&rxq->buf[i], dma),
788838eb 1235 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1236 dma_unmap_addr_set(&rxq->buf[i], dma, 0);
788838eb
LB		 1237
1238 kfree_skb(rxq->buf[i].skb);
1239 rxq->buf[i].skb = NULL;
a66098da
LB		 1240 }
1241 }
1242
788838eb
LB		 1243 kfree(rxq->buf);
1244 rxq->buf = NULL;
a66098da
LB		 1245
1246 pci_free_consistent(priv->pdev,
54bc3a0d 1247 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1248 rxq->rxd, rxq->rxd_dma);
1249 rxq->rxd = NULL;
a66098da
LB		 1250}
1251
1252
1253/*
1254 * Scan a list of BSSIDs to process for finalize join.
1255 * Allows for extension to process multiple BSSIDs.
1256 */
1257static inline int
1258mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1259{
1260 return priv->capture_beacon &&
1261 ieee80211_is_beacon(wh->frame_control) &&
2e42e474 1262 ether_addr_equal(wh->addr3, priv->capture_bssid);
a66098da
LB		 1263}
1264
3779752d
LB		 1265static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1266 struct sk_buff *skb)
a66098da 1267{
3779752d
LB		 1268 struct mwl8k_priv *priv = hw->priv;
1269
a66098da 1270 priv->capture_beacon = false;
d89173f2 1271 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1272
1273 /*
1274 * Use GFP_ATOMIC as rxq_process is called from
1275 * the primary interrupt handler, memory allocation call
1276 * must not sleep.
1277 */
1278 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1279 if (priv->beacon_skb != NULL)
3779752d 1280 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1281}
1282
d9a07d49
NS		 1283static inline struct mwl8k_vif *mwl8k_find_vif_bss(struct list_head *vif_list,
1284 u8 *bssid)
1285{
1286 struct mwl8k_vif *mwl8k_vif;
1287
1288 list_for_each_entry(mwl8k_vif,
1289 vif_list, list) {
1290 if (memcmp(bssid, mwl8k_vif->bssid,
1291 ETH_ALEN) == 0)
1292 return mwl8k_vif;
1293 }
1294
1295 return NULL;
1296}
1297
a66098da
LB		 1298static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1299{
1300 struct mwl8k_priv *priv = hw->priv;
d9a07d49 1301 struct mwl8k_vif *mwl8k_vif = NULL;
a66098da
LB		 1302 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1303 int processed;
1304
1305 processed = 0;
45eb400d 1306 while (rxq->rxd_count && limit--) {
a66098da 1307 struct sk_buff *skb;
54bc3a0d
LB		 1308 void *rxd;
1309 int pkt_len;
a66098da 1310 struct ieee80211_rx_status status;
d9a07d49 1311 struct ieee80211_hdr *wh;
20f09c3d 1312 __le16 qos;
a66098da 1313
788838eb 1314 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1315 if (skb == NULL)
1316 break;
54bc3a0d
LB		 1317
1318 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1319
0d462bbb
JL		 1320 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos,
1321 &priv->noise);
54bc3a0d
LB		 1322 if (pkt_len < 0)
1323 break;
1324
788838eb
LB		 1325 rxq->buf[rxq->head].skb = NULL;
1326
1327 pci_unmap_single(priv->pdev,
53b1b3e1 1328 dma_unmap_addr(&rxq->buf[rxq->head], dma),
788838eb 1329 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1330 dma_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1331
54bc3a0d
LB		 1332 rxq->head++;
1333 if (rxq->head == MWL8K_RX_DESCS)
1334 rxq->head = 0;
1335
45eb400d 1336 rxq->rxd_count--;
a66098da 1337
d9a07d49 1338 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da 1339
a66098da 1340 /*
c2c357ce
LB		 1341 * Check for a pending join operation. Save a
1342 * copy of the beacon and schedule a tasklet to
1343 * send a FINALIZE_JOIN command to the firmware.
a66098da 1344 */
54bc3a0d 1345 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1346 mwl8k_save_beacon(hw, skb);
a66098da 1347
d9a07d49
NS		 1348 if (ieee80211_has_protected(wh->frame_control)) {
1349
1350 /* Check if hw crypto has been enabled for
1351 * this bss. If yes, set the status flags
1352 * accordingly
1353 */
1354 mwl8k_vif = mwl8k_find_vif_bss(&priv->vif_list,
1355 wh->addr1);
1356
1357 if (mwl8k_vif != NULL &&
23677ce3 1358 mwl8k_vif->is_hw_crypto_enabled) {
d9a07d49
NS		 1359 /*
1360 * When MMIC ERROR is encountered
1361 * by the firmware, payload is
1362 * dropped and only 32 bytes of
1363 * mwl8k Firmware header is sent
1364 * to the host.
1365 *
1366 * We need to add four bytes of
1367 * key information. In it
1368 * MAC80211 expects keyidx set to
1369 * 0 for triggering Counter
1370 * Measure of MMIC failure.
1371 */
1372 if (status.flag & RX_FLAG_MMIC_ERROR) {
1373 struct mwl8k_dma_data *tr;
1374 tr = (struct mwl8k_dma_data *)skb->data;
1375 memset((void *)&(tr->data), 0, 4);
1376 pkt_len += 4;
1377 }
1378
1379 if (!ieee80211_is_auth(wh->frame_control))
1380 status.flag |= RX_FLAG_IV_STRIPPED |
1381 RX_FLAG_DECRYPTED |
1382 RX_FLAG_MMIC_STRIPPED;
1383 }
1384 }
1385
1386 skb_put(skb, pkt_len);
1387 mwl8k_remove_dma_header(skb, qos);
f1d58c25
JB		 1388 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1389 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1390
1391 processed++;
1392 }
1393
1394 return processed;
1395}
1396
1397
1398/*
1399 * Packet transmission.
1400 */
1401
a66098da
LB		 1402#define MWL8K_TXD_STATUS_OK 0x00000001
1403#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1404#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1405#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1406#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1407
e0493a8d
LB		 1408#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1409#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1410#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1411#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1412#define MWL8K_QOS_EOSP 0x0010
1413
a66098da
LB		 1414struct mwl8k_tx_desc {
1415 __le32 status;
1416 __u8 data_rate;
1417 __u8 tx_priority;
1418 __le16 qos_control;
1419 __le32 pkt_phys_addr;
1420 __le16 pkt_len;
d89173f2 1421 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1422 __le32 next_txd_phys_addr;
8a7a578c 1423 __le32 timestamp;
a66098da
LB		 1424 __le16 rate_info;
1425 __u8 peer_id;
a1fe24b0 1426 __u8 tx_frag_cnt;
ba2d3587 1427} __packed;
a66098da
LB		 1428
1429#define MWL8K_TX_DESCS 128
1430
1431static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1432{
1433 struct mwl8k_priv *priv = hw->priv;
1434 struct mwl8k_tx_queue *txq = priv->txq + index;
1435 int size;
1436 int i;
1437
8ccbc3b8 1438 txq->len = 0;
45eb400d
LB		 1439 txq->head = 0;
1440 txq->tail = 0;
a66098da
LB		 1441
1442 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1443
45eb400d
LB		 1444 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1445 if (txq->txd == NULL) {
5db55844 1446 wiphy_err(hw->wiphy, "failed to alloc TX descriptors\n");
a66098da
LB		 1447 return -ENOMEM;
1448 }
45eb400d 1449 memset(txq->txd, 0, size);
a66098da 1450
b9ede5f1 1451 txq->skb = kcalloc(MWL8K_TX_DESCS, sizeof(*txq->skb), GFP_KERNEL);
45eb400d 1452 if (txq->skb == NULL) {
45eb400d 1453 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1454 return -ENOMEM;
1455 }
a66098da
LB		 1456
1457 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1458 struct mwl8k_tx_desc *tx_desc;
1459 int nexti;
1460
45eb400d 1461 tx_desc = txq->txd + i;
a66098da
LB		 1462 nexti = (i + 1) % MWL8K_TX_DESCS;
1463
1464 tx_desc->status = 0;
45eb400d
LB		 1465 tx_desc->next_txd_phys_addr =
1466 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1467 }
1468
1469 return 0;
1470}
1471
1472static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1473{
1474 iowrite32(MWL8K_H2A_INT_PPA_READY,
1475 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1476 iowrite32(MWL8K_H2A_INT_DUMMY,
1477 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1478 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1479}
1480
7e1112d3 1481static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1482{
7e1112d3
LB		 1483 struct mwl8k_priv *priv = hw->priv;
1484 int i;
1485
e600707b 1486 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
7e1112d3
LB		 1487 struct mwl8k_tx_queue *txq = priv->txq + i;
1488 int fw_owned = 0;
1489 int drv_owned = 0;
1490 int unused = 0;
1491 int desc;
1492
a66098da 1493 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1494 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1495 u32 status;
a66098da 1496
7e1112d3 1497 status = le32_to_cpu(tx_desc->status);
a66098da 1498 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1499 fw_owned++;
a66098da 1500 else
7e1112d3 1501 drv_owned++;
a66098da
LB		 1502
1503 if (tx_desc->pkt_len == 0)
7e1112d3 1504 unused++;
a66098da 1505 }
a66098da 1506
c96c31e4
JP		 1507 wiphy_err(hw->wiphy,
1508 "txq[%d] len=%d head=%d tail=%d "
1509 "fw_owned=%d drv_owned=%d unused=%d\n",
1510 i,
1511 txq->len, txq->head, txq->tail,
1512 fw_owned, drv_owned, unused);
7e1112d3 1513 }
a66098da
LB		 1514}
1515
618952a7 1516/*
88de754a 1517 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1518 */
62abd3cf 1519#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1520
950d5b01 1521static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1522{
a66098da 1523 struct mwl8k_priv *priv = hw->priv;
88de754a 1524 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1525 int retry;
1526 int rc;
a66098da
LB		 1527
1528 might_sleep();
1529
6b6accc3
YAP		 1530 /* Since fw restart is in progress, allow only the firmware
1531 * commands from the restart code and block the other
1532 * commands since they are going to fail in any case since
1533 * the firmware has crashed
1534 */
1535 if (priv->hw_restart_in_progress) {
1536 if (priv->hw_restart_owner == current)
1537 return 0;
1538 else
1539 return -EBUSY;
1540 }
1541
c27a54d3
YAP		 1542 if (atomic_read(&priv->watchdog_event_pending))
1543 return 0;
1544
7e1112d3
LB		 1545 /*
1546 * The TX queues are stopped at this point, so this test
1547 * doesn't need to take ->tx_lock.
1548 */
1549 if (!priv->pending_tx_pkts)
1550 return 0;
1551
1552 retry = 0;
1553 rc = 0;
1554
a66098da 1555 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1556 priv->tx_wait = &tx_wait;
1557 while (!rc) {
1558 int oldcount;
1559 unsigned long timeout;
a66098da 1560
7e1112d3 1561 oldcount = priv->pending_tx_pkts;
a66098da 1562
7e1112d3 1563 spin_unlock_bh(&priv->tx_lock);
88de754a 1564 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1565 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
c27a54d3
YAP		 1566
1567 if (atomic_read(&priv->watchdog_event_pending)) {
1568 spin_lock_bh(&priv->tx_lock);
1569 priv->tx_wait = NULL;
1570 spin_unlock_bh(&priv->tx_lock);
1571 return 0;
1572 }
1573
a66098da 1574 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1575
1576 if (timeout) {
1577 WARN_ON(priv->pending_tx_pkts);
ba30c4a5 1578 if (retry)
c96c31e4 1579 wiphy_notice(hw->wiphy, "tx rings drained\n");
7e1112d3
LB		 1580 break;
1581 }
1582
1583 if (priv->pending_tx_pkts < oldcount) {
c96c31e4
JP		 1584 wiphy_notice(hw->wiphy,
1585 "waiting for tx rings to drain (%d -> %d pkts)\n",
1586 oldcount, priv->pending_tx_pkts);
7e1112d3
LB		 1587 retry = 1;
1588 continue;
1589 }
1590
a66098da 1591 priv->tx_wait = NULL;
a66098da 1592
c96c31e4
JP		 1593 wiphy_err(hw->wiphy, "tx rings stuck for %d ms\n",
1594 MWL8K_TX_WAIT_TIMEOUT_MS);
7e1112d3 1595 mwl8k_dump_tx_rings(hw);
6b6accc3
YAP		 1596 priv->hw_restart_in_progress = true;
1597 ieee80211_queue_work(hw, &priv->fw_reload);
7e1112d3
LB		 1598
1599 rc = -ETIMEDOUT;
a66098da 1600 }
9b0b11fb 1601 priv->tx_wait = NULL;
7e1112d3 1602 spin_unlock_bh(&priv->tx_lock);
a66098da 1603
7e1112d3 1604 return rc;
a66098da
LB		 1605}
1606
c23b5a69
LB		 1607#define MWL8K_TXD_SUCCESS(status) \
1608 ((status) & (MWL8K_TXD_STATUS_OK | \
1609 MWL8K_TXD_STATUS_OK_RETRY | \
1610 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1611
a0e7c6cf
NS		 1612static int mwl8k_tid_queue_mapping(u8 tid)
1613{
1614 BUG_ON(tid > 7);
1615
1616 switch (tid) {
1617 case 0:
1618 case 3:
1619 return IEEE80211_AC_BE;
1620 break;
1621 case 1:
1622 case 2:
1623 return IEEE80211_AC_BK;
1624 break;
1625 case 4:
1626 case 5:
1627 return IEEE80211_AC_VI;
1628 break;
1629 case 6:
1630 case 7:
1631 return IEEE80211_AC_VO;
1632 break;
1633 default:
1634 return -1;
1635 break;
1636 }
1637}
1638
17033543
NS		 1639/* The firmware will fill in the rate information
1640 * for each packet that gets queued in the hardware
49adc5ce 1641 * and these macros will interpret that info.
17033543
NS		 1642 */
1643
49adc5ce
JL		 1644#define RI_FORMAT(a) (a & 0x0001)
1645#define RI_RATE_ID_MCS(a) ((a & 0x01f8) >> 3)
17033543 1646
efb7c49a
LB		 1647static int
1648mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB		 1649{
1650 struct mwl8k_priv *priv = hw->priv;
1651 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1652 int processed;
a66098da 1653
efb7c49a 1654 processed = 0;
8ccbc3b8 1655 while (txq->len > 0 && limit--) {
a66098da 1656 int tx;
a66098da
LB		 1657 struct mwl8k_tx_desc *tx_desc;
1658 unsigned long addr;
ce9e2e1b 1659 int size;
a66098da
LB		 1660 struct sk_buff *skb;
1661 struct ieee80211_tx_info *info;
1662 u32 status;
17033543
NS		 1663 struct ieee80211_sta *sta;
1664 struct mwl8k_sta *sta_info = NULL;
1665 u16 rate_info;
17033543 1666 struct ieee80211_hdr *wh;
a66098da 1667
45eb400d
LB		 1668 tx = txq->head;
1669 tx_desc = txq->txd + tx;
a66098da
LB		 1670
1671 status = le32_to_cpu(tx_desc->status);
1672
1673 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1674 if (!force)
1675 break;
1676 tx_desc->status &=
1677 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1678 }
1679
45eb400d 1680 txq->head = (tx + 1) % MWL8K_TX_DESCS;
8ccbc3b8
KV		 1681 BUG_ON(txq->len == 0);
1682 txq->len--;
a66098da
LB		 1683 priv->pending_tx_pkts--;
1684
1685 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1686 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1687 skb = txq->skb[tx];
1688 txq->skb[tx] = NULL;
a66098da
LB		 1689
1690 BUG_ON(skb == NULL);
1691 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1692
20f09c3d 1693 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da 1694
17033543
NS		 1695 wh = (struct ieee80211_hdr *) skb->data;
1696
a66098da
LB		 1697 /* Mark descriptor as unused */
1698 tx_desc->pkt_phys_addr = 0;
1699 tx_desc->pkt_len = 0;
1700
a66098da 1701 info = IEEE80211_SKB_CB(skb);
17033543 1702 if (ieee80211_is_data(wh->frame_control)) {
89e11801
TH		 1703 rcu_read_lock();
1704 sta = ieee80211_find_sta_by_ifaddr(hw, wh->addr1,
1705 wh->addr2);
17033543
NS		 1706 if (sta) {
1707 sta_info = MWL8K_STA(sta);
1708 BUG_ON(sta_info == NULL);
1709 rate_info = le16_to_cpu(tx_desc->rate_info);
17033543
NS		 1710 /* If rate is < 6.5 Mpbs for an ht station
1711 * do not form an ampdu. If the station is a
1712 * legacy station (format = 0), do not form an
1713 * ampdu
1714 */
49adc5ce
JL		 1715 if (RI_RATE_ID_MCS(rate_info) < 1 ||
1716 RI_FORMAT(rate_info) == 0) {
17033543
NS		 1717 sta_info->is_ampdu_allowed = false;
1718 } else {
1719 sta_info->is_ampdu_allowed = true;
1720 }
1721 }
89e11801 1722 rcu_read_unlock();
17033543
NS		 1723 }
1724
a66098da 1725 ieee80211_tx_info_clear_status(info);
0bf22c37
NS		 1726
1727 /* Rate control is happening in the firmware.
1728 * Ensure no tx rate is being reported.
1729 */
ba30c4a5
YAP		 1730 info->status.rates[0].idx = -1;
1731 info->status.rates[0].count = 1;
0bf22c37 1732
ce9e2e1b 1733 if (MWL8K_TXD_SUCCESS(status))
a66098da 1734 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1735
1736 ieee80211_tx_status_irqsafe(hw, skb);
1737
efb7c49a 1738 processed++;
a66098da
LB		 1739 }
1740
efb7c49a 1741 return processed;
a66098da
LB		 1742}
1743
1744/* must be called only when the card's transmit is completely halted */
1745static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1746{
1747 struct mwl8k_priv *priv = hw->priv;
1748 struct mwl8k_tx_queue *txq = priv->txq + index;
1749
73b46320
BC		 1750 if (txq->txd == NULL)
1751 return;
1752
efb7c49a 1753 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1754
45eb400d
LB		 1755 kfree(txq->skb);
1756 txq->skb = NULL;
a66098da
LB		 1757
1758 pci_free_consistent(priv->pdev,
1759 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1760 txq->txd, txq->txd_dma);
1761 txq->txd = NULL;
a66098da
LB		 1762}
1763
ac109fd0 1764/* caller must hold priv->stream_lock when calling the stream functions */
ba30c4a5 1765static struct mwl8k_ampdu_stream *
ac109fd0
BC		 1766mwl8k_add_stream(struct ieee80211_hw *hw, struct ieee80211_sta *sta, u8 tid)
1767{
1768 struct mwl8k_ampdu_stream *stream;
1769 struct mwl8k_priv *priv = hw->priv;
1770 int i;
1771
7fb978b7 1772 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
ac109fd0
BC		 1773 stream = &priv->ampdu[i];
1774 if (stream->state == AMPDU_NO_STREAM) {
1775 stream->sta = sta;
1776 stream->state = AMPDU_STREAM_NEW;
1777 stream->tid = tid;
1778 stream->idx = i;
ac109fd0
BC		 1779 wiphy_debug(hw->wiphy, "Added a new stream for %pM %d",
1780 sta->addr, tid);
1781 return stream;
1782 }
1783 }
1784 return NULL;
1785}
1786
1787static int
1788mwl8k_start_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1789{
1790 int ret;
1791
1792 /* if the stream has already been started, don't start it again */
1793 if (stream->state != AMPDU_STREAM_NEW)
1794 return 0;
1795 ret = ieee80211_start_tx_ba_session(stream->sta, stream->tid, 0);
1796 if (ret)
1797 wiphy_debug(hw->wiphy, "Failed to start stream for %pM %d: "
1798 "%d\n", stream->sta->addr, stream->tid, ret);
1799 else
1800 wiphy_debug(hw->wiphy, "Started stream for %pM %d\n",
1801 stream->sta->addr, stream->tid);
1802 return ret;
1803}
1804
1805static void
1806mwl8k_remove_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1807{
1808 wiphy_debug(hw->wiphy, "Remove stream for %pM %d\n", stream->sta->addr,
1809 stream->tid);
1810 memset(stream, 0, sizeof(*stream));
1811}
1812
1813static struct mwl8k_ampdu_stream *
1814mwl8k_lookup_stream(struct ieee80211_hw *hw, u8 *addr, u8 tid)
1815{
1816 struct mwl8k_priv *priv = hw->priv;
1817 int i;
1818
7fb978b7 1819 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
ac109fd0
BC		 1820 struct mwl8k_ampdu_stream *stream;
1821 stream = &priv->ampdu[i];
1822 if (stream->state == AMPDU_NO_STREAM)
1823 continue;
1824 if (!memcmp(stream->sta->addr, addr, ETH_ALEN) &&
1825 stream->tid == tid)
1826 return stream;
1827 }
1828 return NULL;
1829}
1830
d0805c1c
BC		 1831#define MWL8K_AMPDU_PACKET_THRESHOLD 64
1832static inline bool mwl8k_ampdu_allowed(struct ieee80211_sta *sta, u8 tid)
1833{
1834 struct mwl8k_sta *sta_info = MWL8K_STA(sta);
1835 struct tx_traffic_info *tx_stats;
1836
1837 BUG_ON(tid >= MWL8K_MAX_TID);
1838 tx_stats = &sta_info->tx_stats[tid];
1839
1840 return sta_info->is_ampdu_allowed &&
1841 tx_stats->pkts > MWL8K_AMPDU_PACKET_THRESHOLD;
1842}
1843
1844static inline void mwl8k_tx_count_packet(struct ieee80211_sta *sta, u8 tid)
1845{
1846 struct mwl8k_sta *sta_info = MWL8K_STA(sta);
1847 struct tx_traffic_info *tx_stats;
1848
1849 BUG_ON(tid >= MWL8K_MAX_TID);
1850 tx_stats = &sta_info->tx_stats[tid];
1851
1852 if (tx_stats->start_time == 0)
1853 tx_stats->start_time = jiffies;
1854
1855 /* reset the packet count after each second elapses. If the number of
1856 * packets ever exceeds the ampdu_min_traffic threshold, we will allow
1857 * an ampdu stream to be started.
1858 */
1859 if (jiffies - tx_stats->start_time > HZ) {
1860 tx_stats->pkts = 0;
1861 tx_stats->start_time = 0;
1862 } else
1863 tx_stats->pkts++;
1864}
1865
7fb978b7
YAP		 1866/* The hardware ampdu queues start from 5.
1867 * txpriorities for ampdu queues are
1868 * 5 6 7 0 1 2 3 4 ie., queue 5 is highest
1869 * and queue 3 is lowest (queue 4 is reserved)
1870 */
1871#define BA_QUEUE 5
1872
7bb45683 1873static void
36323f81
TH		 1874mwl8k_txq_xmit(struct ieee80211_hw *hw,
1875 int index,
1876 struct ieee80211_sta *sta,
1877 struct sk_buff *skb)
a66098da
LB		 1878{
1879 struct mwl8k_priv *priv = hw->priv;
1880 struct ieee80211_tx_info *tx_info;
23b33906 1881 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1882 struct ieee80211_hdr *wh;
1883 struct mwl8k_tx_queue *txq;
1884 struct mwl8k_tx_desc *tx;
a66098da 1885 dma_addr_t dma;
23b33906
LB		 1886 u32 txstatus;
1887 u8 txdatarate;
1888 u16 qos;
65f3ddcd
NS		 1889 int txpriority;
1890 u8 tid = 0;
1891 struct mwl8k_ampdu_stream *stream = NULL;
1892 bool start_ba_session = false;
3a769888 1893 bool mgmtframe = false;
a0e7c6cf 1894 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
e1f4d69b 1895 bool eapol_frame = false;
a66098da 1896
23b33906
LB		 1897 wh = (struct ieee80211_hdr *)skb->data;
1898 if (ieee80211_is_data_qos(wh->frame_control))
1899 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1900 else
1901 qos = 0;
a66098da 1902
e1f4d69b
NS		 1903 if (skb->protocol == cpu_to_be16(ETH_P_PAE))
1904 eapol_frame = true;
1905
3a769888
NS		 1906 if (ieee80211_is_mgmt(wh->frame_control))
1907 mgmtframe = true;
1908
d9a07d49 1909 if (priv->ap_fw)
ff776cec 1910 mwl8k_encapsulate_tx_frame(priv, skb);
d9a07d49 1911 else
e4eefec7 1912 mwl8k_add_dma_header(priv, skb, 0, 0);
d9a07d49 1913
23b33906 1914 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1915
1916 tx_info = IEEE80211_SKB_CB(skb);
1917 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1918
1919 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
a66098da 1920 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
657232b6
LB		 1921 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1922 mwl8k_vif->seqno += 0x10;
a66098da
LB		 1923 }
1924
23b33906
LB		 1925 /* Setup firmware control bit fields for each frame type. */
1926 txstatus = 0;
1927 txdatarate = 0;
1928 if (ieee80211_is_mgmt(wh->frame_control) ||
1929 ieee80211_is_ctl(wh->frame_control)) {
1930 txdatarate = 0;
e0493a8d 1931 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1932 } else if (ieee80211_is_data(wh->frame_control)) {
1933 txdatarate = 1;
1934 if (is_multicast_ether_addr(wh->addr1))
1935 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1936
e0493a8d 1937 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1938 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1939 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1940 else
e0493a8d 1941 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1942 }
a66098da 1943
a0e7c6cf
NS		 1944 /* Queue ADDBA request in the respective data queue. While setting up
1945 * the ampdu stream, mac80211 queues further packets for that
1946 * particular ra/tid pair. However, packets piled up in the hardware
1947 * for that ra/tid pair will still go out. ADDBA request and the
1948 * related data packets going out from different queues asynchronously
1949 * will cause a shift in the receiver window which might result in
1950 * ampdu packets getting dropped at the receiver after the stream has
1951 * been setup.
1952 */
1953 if (unlikely(ieee80211_is_action(wh->frame_control) &&
1954 mgmt->u.action.category == WLAN_CATEGORY_BACK &&
1955 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ &&
1956 priv->ap_fw)) {
1957 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
1958 tid = (capab & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2;
1959 index = mwl8k_tid_queue_mapping(tid);
1960 }
1961
65f3ddcd
NS		 1962 txpriority = index;
1963
e1f4d69b
NS		 1964 if (priv->ap_fw && sta && sta->ht_cap.ht_supported && !eapol_frame &&
1965 ieee80211_is_data_qos(wh->frame_control)) {
65f3ddcd 1966 tid = qos & 0xf;
d0805c1c 1967 mwl8k_tx_count_packet(sta, tid);
65f3ddcd
NS		 1968 spin_lock(&priv->stream_lock);
1969 stream = mwl8k_lookup_stream(hw, sta->addr, tid);
1970 if (stream != NULL) {
1971 if (stream->state == AMPDU_STREAM_ACTIVE) {
5f2a1494 1972 WARN_ON(!(qos & MWL8K_QOS_ACK_POLICY_BLOCKACK));
7fb978b7
YAP		 1973 txpriority = (BA_QUEUE + stream->idx) %
1974 TOTAL_HW_TX_QUEUES;
1975 if (stream->idx <= 1)
1976 index = stream->idx +
1977 MWL8K_TX_WMM_QUEUES;
1978
65f3ddcd
NS		 1979 } else if (stream->state == AMPDU_STREAM_NEW) {
1980 /* We get here if the driver sends us packets
1981 * after we've initiated a stream, but before
1982 * our ampdu_action routine has been called
1983 * with IEEE80211_AMPDU_TX_START to get the SSN
1984 * for the ADDBA request. So this packet can
1985 * go out with no risk of sequence number
1986 * mismatch. No special handling is required.
1987 */
1988 } else {
1989 /* Drop packets that would go out after the
1990 * ADDBA request was sent but before the ADDBA
1991 * response is received. If we don't do this,
1992 * the recipient would probably receive it
1993 * after the ADDBA request with SSN 0. This
1994 * will cause the recipient's BA receive window
1995 * to shift, which would cause the subsequent
1996 * packets in the BA stream to be discarded.
1997 * mac80211 queues our packets for us in this
1998 * case, so this is really just a safety check.
1999 */
2000 wiphy_warn(hw->wiphy,
2001 "Cannot send packet while ADDBA "
2002 "dialog is underway.\n");
2003 spin_unlock(&priv->stream_lock);
2004 dev_kfree_skb(skb);
2005 return;
2006 }
2007 } else {
2008 /* Defer calling mwl8k_start_stream so that the current
2009 * skb can go out before the ADDBA request. This
2010 * prevents sequence number mismatch at the recepient
2011 * as described above.
2012 */
d0805c1c 2013 if (mwl8k_ampdu_allowed(sta, tid)) {
17033543
NS		 2014 stream = mwl8k_add_stream(hw, sta, tid);
2015 if (stream != NULL)
2016 start_ba_session = true;
2017 }
65f3ddcd
NS		 2018 }
2019 spin_unlock(&priv->stream_lock);
5f2a1494
YAP		 2020 } else {
2021 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
2022 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
65f3ddcd
NS		 2023 }
2024
a66098da
LB		 2025 dma = pci_map_single(priv->pdev, skb->data,
2026 skb->len, PCI_DMA_TODEVICE);
2027
2028 if (pci_dma_mapping_error(priv->pdev, dma)) {
c96c31e4
JP		 2029 wiphy_debug(hw->wiphy,
2030 "failed to dma map skb, dropping TX frame.\n");
65f3ddcd
NS		 2031 if (start_ba_session) {
2032 spin_lock(&priv->stream_lock);
2033 mwl8k_remove_stream(hw, stream);
2034 spin_unlock(&priv->stream_lock);
2035 }
23b33906 2036 dev_kfree_skb(skb);
7bb45683 2037 return;
a66098da
LB		 2038 }
2039
23b33906 2040 spin_lock_bh(&priv->tx_lock);
a66098da 2041
23b33906 2042 txq = priv->txq + index;
a66098da 2043
3a769888
NS		 2044 /* Mgmt frames that go out frequently are probe
2045 * responses. Other mgmt frames got out relatively
2046 * infrequently. Hence reserve 2 buffers so that
2047 * other mgmt frames do not get dropped due to an
2048 * already queued probe response in one of the
2049 * reserved buffers.
2050 */
2051
2052 if (txq->len >= MWL8K_TX_DESCS - 2) {
23677ce3 2053 if (!mgmtframe || txq->len == MWL8K_TX_DESCS) {
3a769888
NS		 2054 if (start_ba_session) {
2055 spin_lock(&priv->stream_lock);
2056 mwl8k_remove_stream(hw, stream);
2057 spin_unlock(&priv->stream_lock);
2058 }
2059 spin_unlock_bh(&priv->tx_lock);
ff7aa96f
NS		 2060 pci_unmap_single(priv->pdev, dma, skb->len,
2061 PCI_DMA_TODEVICE);
3a769888
NS		 2062 dev_kfree_skb(skb);
2063 return;
3a7dbc3b 2064 }
65f3ddcd
NS		 2065 }
2066
45eb400d
LB		 2067 BUG_ON(txq->skb[txq->tail] != NULL);
2068 txq->skb[txq->tail] = skb;
a66098da 2069
45eb400d 2070 tx = txq->txd + txq->tail;
23b33906 2071 tx->data_rate = txdatarate;
65f3ddcd 2072 tx->tx_priority = txpriority;
a66098da 2073 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 2074 tx->pkt_phys_addr = cpu_to_le32(dma);
2075 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 2076 tx->rate_info = 0;
36323f81
TH		 2077 if (!priv->ap_fw && sta != NULL)
2078 tx->peer_id = MWL8K_STA(sta)->peer_id;
a680400e
LB		 2079 else
2080 tx->peer_id = 0;
566875db 2081
e1f4d69b 2082 if (priv->ap_fw && ieee80211_is_data(wh->frame_control) && !eapol_frame)
566875db
PN		 2083 tx->timestamp = cpu_to_le32(ioread32(priv->regs +
2084 MWL8K_HW_TIMER_REGISTER));
b8d9e572
NS		 2085 else
2086 tx->timestamp = 0;
566875db 2087
a66098da 2088 wmb();
23b33906
LB		 2089 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
2090
8ccbc3b8 2091 txq->len++;
a66098da 2092 priv->pending_tx_pkts++;
a66098da 2093
45eb400d
LB		 2094 txq->tail++;
2095 if (txq->tail == MWL8K_TX_DESCS)
2096 txq->tail = 0;
23b33906 2097
23b33906 2098 mwl8k_tx_start(priv);
a66098da
LB		 2099
2100 spin_unlock_bh(&priv->tx_lock);
65f3ddcd
NS		 2101
2102 /* Initiate the ampdu session here */
2103 if (start_ba_session) {
2104 spin_lock(&priv->stream_lock);
2105 if (mwl8k_start_stream(hw, stream))
2106 mwl8k_remove_stream(hw, stream);
2107 spin_unlock(&priv->stream_lock);
2108 }
a66098da
LB		 2109}
2110
2111
618952a7
LB		 2112/*
2113 * Firmware access.
2114 *
2115 * We have the following requirements for issuing firmware commands:
2116 * - Some commands require that the packet transmit path is idle when
2117 * the command is issued. (For simplicity, we'll just quiesce the
2118 * transmit path for every command.)
2119 * - There are certain sequences of commands that need to be issued to
2120 * the hardware sequentially, with no other intervening commands.
2121 *
2122 * This leads to an implementation of a "firmware lock" as a mutex that
2123 * can be taken recursively, and which is taken by both the low-level
2124 * command submission function (mwl8k_post_cmd) as well as any users of
2125 * that function that require issuing of an atomic sequence of commands,
2126 * and quiesces the transmit path whenever it's taken.
2127 */
2128static int mwl8k_fw_lock(struct ieee80211_hw *hw)
2129{
2130 struct mwl8k_priv *priv = hw->priv;
2131
2132 if (priv->fw_mutex_owner != current) {
2133 int rc;
2134
2135 mutex_lock(&priv->fw_mutex);
2136 ieee80211_stop_queues(hw);
2137
2138 rc = mwl8k_tx_wait_empty(hw);
2139 if (rc) {
6b6accc3
YAP		 2140 if (!priv->hw_restart_in_progress)
2141 ieee80211_wake_queues(hw);
2142
618952a7
LB		 2143 mutex_unlock(&priv->fw_mutex);
2144
2145 return rc;
2146 }
2147
2148 priv->fw_mutex_owner = current;
2149 }
2150
2151 priv->fw_mutex_depth++;
2152
2153 return 0;
2154}
2155
2156static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
2157{
2158 struct mwl8k_priv *priv = hw->priv;
2159
2160 if (!--priv->fw_mutex_depth) {
6b6accc3
YAP		 2161 if (!priv->hw_restart_in_progress)
2162 ieee80211_wake_queues(hw);
2163
618952a7
LB		 2164 priv->fw_mutex_owner = NULL;
2165 mutex_unlock(&priv->fw_mutex);
2166 }
2167}
2168
e882efc9
YAP		 2169static void mwl8k_enable_bsses(struct ieee80211_hw *hw, bool enable,
2170 u32 bitmap);
618952a7 2171
a66098da
LB		 2172/*
2173 * Command processing.
2174 */
2175
0c9cc640
LB		 2176/* Timeout firmware commands after 10s */
2177#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 2178
2179static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
2180{
2181 DECLARE_COMPLETION_ONSTACK(cmd_wait);
2182 struct mwl8k_priv *priv = hw->priv;
2183 void __iomem *regs = priv->regs;
2184 dma_addr_t dma_addr;
2185 unsigned int dma_size;
2186 int rc;
a66098da
LB		 2187 unsigned long timeout = 0;
2188 u8 buf[32];
e882efc9
YAP		 2189 u32 bitmap = 0;
2190
2191 wiphy_dbg(hw->wiphy, "Posting %s [%d]\n",
2192 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), cmd->macid);
2193
2194 /* Before posting firmware commands that could change the hardware
2195 * characteristics, make sure that all BSSes are stopped temporary.
2196 * Enable these stopped BSSes after completion of the commands
2197 */
2198
2199 rc = mwl8k_fw_lock(hw);
2200 if (rc)
2201 return rc;
2202
2203 if (priv->ap_fw && priv->running_bsses) {
2204 switch (le16_to_cpu(cmd->code)) {
2205 case MWL8K_CMD_SET_RF_CHANNEL:
2206 case MWL8K_CMD_RADIO_CONTROL:
2207 case MWL8K_CMD_RF_TX_POWER:
2208 case MWL8K_CMD_TX_POWER:
2209 case MWL8K_CMD_RF_ANTENNA:
2210 case MWL8K_CMD_RTS_THRESHOLD:
2211 case MWL8K_CMD_MIMO_CONFIG:
2212 bitmap = priv->running_bsses;
2213 mwl8k_enable_bsses(hw, false, bitmap);
2214 break;
2215 }
2216 }
a66098da 2217
b603742f 2218 cmd->result = (__force __le16) 0xffff;
a66098da
LB		 2219 dma_size = le16_to_cpu(cmd->length);
2220 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
2221 PCI_DMA_BIDIRECTIONAL);
2222 if (pci_dma_mapping_error(priv->pdev, dma_addr))
2223 return -ENOMEM;
2224
a66098da
LB		 2225 priv->hostcmd_wait = &cmd_wait;
2226 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
2227 iowrite32(MWL8K_H2A_INT_DOORBELL,
2228 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
2229 iowrite32(MWL8K_H2A_INT_DUMMY,
2230 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 2231
2232 timeout = wait_for_completion_timeout(&cmd_wait,
2233 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
2234
618952a7
LB		 2235 priv->hostcmd_wait = NULL;
2236
618952a7 2237
37055bd4
LB		 2238 pci_unmap_single(priv->pdev, dma_addr, dma_size,
2239 PCI_DMA_BIDIRECTIONAL);
2240
a66098da 2241 if (!timeout) {
5db55844 2242 wiphy_err(hw->wiphy, "Command %s timeout after %u ms\n",
c96c31e4
JP		 2243 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2244 MWL8K_CMD_TIMEOUT_MS);
a66098da
LB		 2245 rc = -ETIMEDOUT;
2246 } else {
0c9cc640
LB		 2247 int ms;
2248
2249 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
2250
ce9e2e1b 2251 rc = cmd->result ? -EINVAL : 0;
a66098da 2252 if (rc)
5db55844 2253 wiphy_err(hw->wiphy, "Command %s error 0x%x\n",
c96c31e4
JP		 2254 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2255 le16_to_cpu(cmd->result));
0c9cc640 2256 else if (ms > 2000)
5db55844 2257 wiphy_notice(hw->wiphy, "Command %s took %d ms\n",
c96c31e4
JP		 2258 mwl8k_cmd_name(cmd->code,
2259 buf, sizeof(buf)),
2260 ms);
a66098da
LB		 2261 }
2262
e882efc9
YAP		 2263 if (bitmap)
2264 mwl8k_enable_bsses(hw, true, bitmap);
2265
2266 mwl8k_fw_unlock(hw);
2267
a66098da
LB		 2268 return rc;
2269}
2270
f57ca9c1
LB		 2271static int mwl8k_post_pervif_cmd(struct ieee80211_hw *hw,
2272 struct ieee80211_vif *vif,
2273 struct mwl8k_cmd_pkt *cmd)
2274{
2275 if (vif != NULL)
2276 cmd->macid = MWL8K_VIF(vif)->macid;
2277 return mwl8k_post_cmd(hw, cmd);
2278}
2279
1349ad2f
LB		 2280/*
2281 * Setup code shared between STA and AP firmware images.
2282 */
2283static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw)
2284{
2285 struct mwl8k_priv *priv = hw->priv;
2286
2287 BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24));
2288 memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
2289
2290 BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
2291 memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
2292
2293 priv->band_24.band = IEEE80211_BAND_2GHZ;
2294 priv->band_24.channels = priv->channels_24;
2295 priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
2296 priv->band_24.bitrates = priv->rates_24;
2297 priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
2298
2299 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24;
2300}
2301
4eae9edd
LB		 2302static void mwl8k_setup_5ghz_band(struct ieee80211_hw *hw)
2303{
2304 struct mwl8k_priv *priv = hw->priv;
2305
2306 BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl8k_channels_50));
2307 memcpy(priv->channels_50, mwl8k_channels_50, sizeof(mwl8k_channels_50));
2308
2309 BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl8k_rates_50));
2310 memcpy(priv->rates_50, mwl8k_rates_50, sizeof(mwl8k_rates_50));
2311
2312 priv->band_50.band = IEEE80211_BAND_5GHZ;
2313 priv->band_50.channels = priv->channels_50;
2314 priv->band_50.n_channels = ARRAY_SIZE(mwl8k_channels_50);
2315 priv->band_50.bitrates = priv->rates_50;
2316 priv->band_50.n_bitrates = ARRAY_SIZE(mwl8k_rates_50);
2317
2318 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->band_50;
2319}
2320
a66098da 2321/*
04b147b1 2322 * CMD_GET_HW_SPEC (STA version).
a66098da 2323 */
04b147b1 2324struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 2325 struct mwl8k_cmd_pkt header;
2326 __u8 hw_rev;
2327 __u8 host_interface;
2328 __le16 num_mcaddrs;
d89173f2 2329 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 2330 __le16 region_code;
2331 __le32 fw_rev;
2332 __le32 ps_cookie;
2333 __le32 caps;
2334 __u8 mcs_bitmap[16];
2335 __le32 rx_queue_ptr;
2336 __le32 num_tx_queues;
e600707b 2337 __le32 tx_queue_ptrs[MWL8K_TX_WMM_QUEUES];
a66098da
LB		 2338 __le32 caps2;
2339 __le32 num_tx_desc_per_queue;
45eb400d 2340 __le32 total_rxd;
ba2d3587 2341} __packed;
a66098da 2342
341c9791
LB		 2343#define MWL8K_CAP_MAX_AMSDU 0x20000000
2344#define MWL8K_CAP_GREENFIELD 0x08000000
2345#define MWL8K_CAP_AMPDU 0x04000000
2346#define MWL8K_CAP_RX_STBC 0x01000000
2347#define MWL8K_CAP_TX_STBC 0x00800000
2348#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
2349#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
2350#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
2351#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
2352#define MWL8K_CAP_DELAY_BA 0x00003000
2353#define MWL8K_CAP_MIMO 0x00000200
2354#define MWL8K_CAP_40MHZ 0x00000100
06953235
LB		 2355#define MWL8K_CAP_BAND_MASK 0x00000007
2356#define MWL8K_CAP_5GHZ 0x00000004
2357#define MWL8K_CAP_2GHZ4 0x00000001
341c9791 2358
06953235
LB		 2359static void
2360mwl8k_set_ht_caps(struct ieee80211_hw *hw,
2361 struct ieee80211_supported_band *band, u32 cap)
341c9791 2362{
341c9791
LB		 2363 int rx_streams;
2364 int tx_streams;
2365
777ad375 2366 band->ht_cap.ht_supported = 1;
341c9791
LB		 2367
2368 if (cap & MWL8K_CAP_MAX_AMSDU)
777ad375 2369 band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
341c9791 2370 if (cap & MWL8K_CAP_GREENFIELD)
777ad375 2371 band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
341c9791
LB		 2372 if (cap & MWL8K_CAP_AMPDU) {
2373 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
777ad375
LB		 2374 band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
2375 band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
341c9791
LB		 2376 }
2377 if (cap & MWL8K_CAP_RX_STBC)
777ad375 2378 band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
341c9791 2379 if (cap & MWL8K_CAP_TX_STBC)
777ad375 2380 band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
341c9791 2381 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
777ad375 2382 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
341c9791 2383 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
777ad375 2384 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
341c9791 2385 if (cap & MWL8K_CAP_DELAY_BA)
777ad375 2386 band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
341c9791 2387 if (cap & MWL8K_CAP_40MHZ)
777ad375 2388 band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
341c9791
LB		 2389
2390 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
2391 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
2392
777ad375 2393 band->ht_cap.mcs.rx_mask[0] = 0xff;
341c9791 2394 if (rx_streams >= 2)
777ad375 2395 band->ht_cap.mcs.rx_mask[1] = 0xff;
341c9791 2396 if (rx_streams >= 3)
777ad375
LB		 2397 band->ht_cap.mcs.rx_mask[2] = 0xff;
2398 band->ht_cap.mcs.rx_mask[4] = 0x01;
2399 band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
341c9791
LB		 2400
2401 if (rx_streams != tx_streams) {
777ad375
LB		 2402 band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
2403 band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
341c9791
LB		 2404 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2405 }
2406}
2407
06953235
LB		 2408static void
2409mwl8k_set_caps(struct ieee80211_hw *hw, u32 caps)
2410{
2411 struct mwl8k_priv *priv = hw->priv;
2412
2413 if ((caps & MWL8K_CAP_2GHZ4) || !(caps & MWL8K_CAP_BAND_MASK)) {
2414 mwl8k_setup_2ghz_band(hw);
2415 if (caps & MWL8K_CAP_MIMO)
2416 mwl8k_set_ht_caps(hw, &priv->band_24, caps);
2417 }
2418
2419 if (caps & MWL8K_CAP_5GHZ) {
2420 mwl8k_setup_5ghz_band(hw);
2421 if (caps & MWL8K_CAP_MIMO)
2422 mwl8k_set_ht_caps(hw, &priv->band_50, caps);
2423 }
2424}
2425
04b147b1 2426static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 2427{
2428 struct mwl8k_priv *priv = hw->priv;
04b147b1 2429 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 2430 int rc;
2431 int i;
2432
2433 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2434 if (cmd == NULL)
2435 return -ENOMEM;
2436
2437 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2438 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2439
2440 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2441 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 2442 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
e600707b
BC		 2443 cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
2444 for (i = 0; i < mwl8k_tx_queues(priv); i++)
45eb400d 2445 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 2446 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 2447 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 2448
2449 rc = mwl8k_post_cmd(hw, &cmd->header);
2450
2451 if (!rc) {
2452 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2453 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 2454 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 2455 priv->hw_rev = cmd->hw_rev;
06953235 2456 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18
LB		 2457 priv->ap_macids_supported = 0x00000000;
2458 priv->sta_macids_supported = 0x00000001;
a66098da
LB		 2459 }
2460
2461 kfree(cmd);
2462 return rc;
2463}
2464
42fba21d
LB		 2465/*
2466 * CMD_GET_HW_SPEC (AP version).
2467 */
2468struct mwl8k_cmd_get_hw_spec_ap {
2469 struct mwl8k_cmd_pkt header;
2470 __u8 hw_rev;
2471 __u8 host_interface;
2472 __le16 num_wcb;
2473 __le16 num_mcaddrs;
2474 __u8 perm_addr[ETH_ALEN];
2475 __le16 region_code;
2476 __le16 num_antenna;
2477 __le32 fw_rev;
2478 __le32 wcbbase0;
2479 __le32 rxwrptr;
2480 __le32 rxrdptr;
2481 __le32 ps_cookie;
2482 __le32 wcbbase1;
2483 __le32 wcbbase2;
2484 __le32 wcbbase3;
952a0e96 2485 __le32 fw_api_version;
8a7a578c
BC		 2486 __le32 caps;
2487 __le32 num_of_ampdu_queues;
2488 __le32 wcbbase_ampdu[MWL8K_MAX_AMPDU_QUEUES];
ba2d3587 2489} __packed;
42fba21d
LB		 2490
2491static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
2492{
2493 struct mwl8k_priv *priv = hw->priv;
2494 struct mwl8k_cmd_get_hw_spec_ap *cmd;
8a7a578c 2495 int rc, i;
952a0e96 2496 u32 api_version;
42fba21d
LB		 2497
2498 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2499 if (cmd == NULL)
2500 return -ENOMEM;
2501
2502 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2503 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2504
2505 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2506 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2507
2508 rc = mwl8k_post_cmd(hw, &cmd->header);
2509
2510 if (!rc) {
2511 int off;
2512
952a0e96
BC		 2513 api_version = le32_to_cpu(cmd->fw_api_version);
2514 if (priv->device_info->fw_api_ap != api_version) {
2515 printk(KERN_ERR "%s: Unsupported fw API version for %s."
2516 " Expected %d got %d.\n", MWL8K_NAME,
2517 priv->device_info->part_name,
2518 priv->device_info->fw_api_ap,
2519 api_version);
2520 rc = -EINVAL;
2521 goto done;
2522 }
42fba21d
LB		 2523 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2524 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
2525 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
2526 priv->hw_rev = cmd->hw_rev;
8a7a578c 2527 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18 2528 priv->ap_macids_supported = 0x000000ff;
d59c1cfd 2529 priv->sta_macids_supported = 0x00000100;
8a7a578c
BC		 2530 priv->num_ampdu_queues = le32_to_cpu(cmd->num_of_ampdu_queues);
2531 if (priv->num_ampdu_queues > MWL8K_MAX_AMPDU_QUEUES) {
2532 wiphy_warn(hw->wiphy, "fw reported %d ampdu queues"
2533 " but we only support %d.\n",
2534 priv->num_ampdu_queues,
2535 MWL8K_MAX_AMPDU_QUEUES);
2536 priv->num_ampdu_queues = MWL8K_MAX_AMPDU_QUEUES;
2537 }
42fba21d 2538 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
b603742f 2539 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d
LB		 2540
2541 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
b603742f 2542 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d 2543
73b46320
BC		 2544 priv->txq_offset[0] = le32_to_cpu(cmd->wcbbase0) & 0xffff;
2545 priv->txq_offset[1] = le32_to_cpu(cmd->wcbbase1) & 0xffff;
2546 priv->txq_offset[2] = le32_to_cpu(cmd->wcbbase2) & 0xffff;
2547 priv->txq_offset[3] = le32_to_cpu(cmd->wcbbase3) & 0xffff;
8a7a578c
BC		 2548
2549 for (i = 0; i < priv->num_ampdu_queues; i++)
e600707b 2550 priv->txq_offset[i + MWL8K_TX_WMM_QUEUES] =
8a7a578c 2551 le32_to_cpu(cmd->wcbbase_ampdu[i]) & 0xffff;
42fba21d
LB		 2552 }
2553
952a0e96 2554done:
42fba21d
LB		 2555 kfree(cmd);
2556 return rc;
2557}
2558
2559/*
2560 * CMD_SET_HW_SPEC.
2561 */
2562struct mwl8k_cmd_set_hw_spec {
2563 struct mwl8k_cmd_pkt header;
2564 __u8 hw_rev;
2565 __u8 host_interface;
2566 __le16 num_mcaddrs;
2567 __u8 perm_addr[ETH_ALEN];
2568 __le16 region_code;
2569 __le32 fw_rev;
2570 __le32 ps_cookie;
2571 __le32 caps;
2572 __le32 rx_queue_ptr;
2573 __le32 num_tx_queues;
e600707b 2574 __le32 tx_queue_ptrs[MWL8K_MAX_TX_QUEUES];
42fba21d
LB		 2575 __le32 flags;
2576 __le32 num_tx_desc_per_queue;
2577 __le32 total_rxd;
ba2d3587 2578} __packed;
42fba21d 2579
8a7a578c
BC		 2580/* If enabled, MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY will cause
2581 * packets to expire 500 ms after the timestamp in the tx descriptor. That is,
2582 * the packets that are queued for more than 500ms, will be dropped in the
2583 * hardware. This helps minimizing the issues caused due to head-of-line
2584 * blocking where a slow client can hog the bandwidth and affect traffic to a
2585 * faster client.
2586 */
2587#define MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY 0x00000400
3373b28e 2588#define MWL8K_SET_HW_SPEC_FLAG_GENERATE_CCMP_HDR 0x00000200
b64fe619
LB		 2589#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
2590#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
2591#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB		 2592
2593static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
2594{
2595 struct mwl8k_priv *priv = hw->priv;
2596 struct mwl8k_cmd_set_hw_spec *cmd;
2597 int rc;
2598 int i;
2599
2600 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2601 if (cmd == NULL)
2602 return -ENOMEM;
2603
2604 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
2605 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2606
2607 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2608 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
e600707b 2609 cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
85c9205c
NS		 2610
2611 /*
2612 * Mac80211 stack has Q0 as highest priority and Q3 as lowest in
2613 * that order. Firmware has Q3 as highest priority and Q0 as lowest
2614 * in that order. Map Q3 of mac80211 to Q0 of firmware so that the
2615 * priority is interpreted the right way in firmware.
2616 */
e600707b
BC		 2617 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
2618 int j = mwl8k_tx_queues(priv) - 1 - i;
85c9205c
NS		 2619 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[j].txd_dma);
2620 }
2621
b64fe619
LB		 2622 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
2623 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
31d291a7 2624 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON |
3373b28e
NS		 2625 MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY |
2626 MWL8K_SET_HW_SPEC_FLAG_GENERATE_CCMP_HDR);
42fba21d
LB		 2627 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
2628 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
2629
2630 rc = mwl8k_post_cmd(hw, &cmd->header);
2631 kfree(cmd);
2632
2633 return rc;
2634}
2635
a66098da
LB		 2636/*
2637 * CMD_MAC_MULTICAST_ADR.
2638 */
2639struct mwl8k_cmd_mac_multicast_adr {
2640 struct mwl8k_cmd_pkt header;
2641 __le16 action;
2642 __le16 numaddr;
ce9e2e1b 2643 __u8 addr[0][ETH_ALEN];
a66098da
LB		 2644};
2645
d5e30845
LB		 2646#define MWL8K_ENABLE_RX_DIRECTED 0x0001
2647#define MWL8K_ENABLE_RX_MULTICAST 0x0002
2648#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
2649#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 2650
e81cd2d6 2651static struct mwl8k_cmd_pkt *
447ced07 2652__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
22bedad3 2653 struct netdev_hw_addr_list *mc_list)
a66098da 2654{
e81cd2d6 2655 struct mwl8k_priv *priv = hw->priv;
a66098da 2656 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 2657 int size;
22bedad3
JP		 2658 int mc_count = 0;
2659
2660 if (mc_list)
2661 mc_count = netdev_hw_addr_list_count(mc_list);
e81cd2d6 2662
447ced07 2663 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 2664 allmulti = 1;
2665 mc_count = 0;
2666 }
e81cd2d6
LB		 2667
2668 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 2669
e81cd2d6 2670 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 2671 if (cmd == NULL)
e81cd2d6 2672 return NULL;
a66098da
LB		 2673
2674 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
2675 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 2676 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
2677 MWL8K_ENABLE_RX_BROADCAST);
2678
2679 if (allmulti) {
2680 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
2681 } else if (mc_count) {
22bedad3
JP		 2682 struct netdev_hw_addr *ha;
2683 int i = 0;
d5e30845
LB		 2684
2685 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
2686 cmd->numaddr = cpu_to_le16(mc_count);
22bedad3
JP		 2687 netdev_hw_addr_list_for_each(ha, mc_list) {
2688 memcpy(cmd->addr[i], ha->addr, ETH_ALEN);
a66098da 2689 }
a66098da
LB		 2690 }
2691
e81cd2d6 2692 return &cmd->header;
a66098da
LB		 2693}
2694
2695/*
55489b6e 2696 * CMD_GET_STAT.
a66098da 2697 */
55489b6e 2698struct mwl8k_cmd_get_stat {
a66098da 2699 struct mwl8k_cmd_pkt header;
a66098da 2700 __le32 stats[64];
ba2d3587 2701} __packed;
a66098da
LB		 2702
2703#define MWL8K_STAT_ACK_FAILURE 9
2704#define MWL8K_STAT_RTS_FAILURE 12
2705#define MWL8K_STAT_FCS_ERROR 24
2706#define MWL8K_STAT_RTS_SUCCESS 11
2707
55489b6e
LB		 2708static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
2709 struct ieee80211_low_level_stats *stats)
a66098da 2710{
55489b6e 2711 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 2712 int rc;
2713
2714 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2715 if (cmd == NULL)
2716 return -ENOMEM;
2717
2718 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
2719 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2720
2721 rc = mwl8k_post_cmd(hw, &cmd->header);
2722 if (!rc) {
2723 stats->dot11ACKFailureCount =
2724 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
2725 stats->dot11RTSFailureCount =
2726 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
2727 stats->dot11FCSErrorCount =
2728 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
2729 stats->dot11RTSSuccessCount =
2730 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
2731 }
2732 kfree(cmd);
2733
2734 return rc;
2735}
2736
2737/*
55489b6e 2738 * CMD_RADIO_CONTROL.
a66098da 2739 */
55489b6e 2740struct mwl8k_cmd_radio_control {
a66098da
LB		 2741 struct mwl8k_cmd_pkt header;
2742 __le16 action;
2743 __le16 control;
2744 __le16 radio_on;
ba2d3587 2745} __packed;
a66098da 2746
c46563b7 2747static int
55489b6e 2748mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 2749{
2750 struct mwl8k_priv *priv = hw->priv;
55489b6e 2751 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 2752 int rc;
2753
c46563b7 2754 if (enable == priv->radio_on && !force)
a66098da
LB		 2755 return 0;
2756
a66098da
LB		 2757 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2758 if (cmd == NULL)
2759 return -ENOMEM;
2760
2761 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
2762 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2763 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 2764 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 2765 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
2766
2767 rc = mwl8k_post_cmd(hw, &cmd->header);
2768 kfree(cmd);
2769
2770 if (!rc)
c46563b7 2771 priv->radio_on = enable;
a66098da
LB		 2772
2773 return rc;
2774}
2775
55489b6e 2776static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 2777{
55489b6e 2778 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 2779}
2780
55489b6e 2781static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 2782{
55489b6e 2783 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 2784}
2785
a66098da
LB		 2786static int
2787mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
2788{
99200a99 2789 struct mwl8k_priv *priv = hw->priv;
a66098da 2790
68ce3884 2791 priv->radio_short_preamble = short_preamble;
a66098da 2792
55489b6e 2793 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 2794}
2795
2796/*
55489b6e 2797 * CMD_RF_TX_POWER.
a66098da 2798 */
41fdf097 2799#define MWL8K_RF_TX_POWER_LEVEL_TOTAL 8
a66098da 2800
55489b6e 2801struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 2802 struct mwl8k_cmd_pkt header;
2803 __le16 action;
2804 __le16 support_level;
2805 __le16 current_level;
2806 __le16 reserved;
41fdf097 2807 __le16 power_level_list[MWL8K_RF_TX_POWER_LEVEL_TOTAL];
ba2d3587 2808} __packed;
a66098da 2809
55489b6e 2810static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 2811{
55489b6e 2812 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 2813 int rc;
2814
2815 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2816 if (cmd == NULL)
2817 return -ENOMEM;
2818
2819 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2820 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2821 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2822 cmd->support_level = cpu_to_le16(dBm);
2823
2824 rc = mwl8k_post_cmd(hw, &cmd->header);
2825 kfree(cmd);
2826
2827 return rc;
2828}
2829
41fdf097
NS		 2830/*
2831 * CMD_TX_POWER.
2832 */
2833#define MWL8K_TX_POWER_LEVEL_TOTAL 12
2834
2835struct mwl8k_cmd_tx_power {
2836 struct mwl8k_cmd_pkt header;
2837 __le16 action;
2838 __le16 band;
2839 __le16 channel;
2840 __le16 bw;
2841 __le16 sub_ch;
2842 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
ba30c4a5 2843} __packed;
41fdf097
NS		 2844
2845static int mwl8k_cmd_tx_power(struct ieee80211_hw *hw,
2846 struct ieee80211_conf *conf,
2847 unsigned short pwr)
2848{
2849 struct ieee80211_channel *channel = conf->channel;
2850 struct mwl8k_cmd_tx_power *cmd;
2851 int rc;
2852 int i;
2853
2854 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2855 if (cmd == NULL)
2856 return -ENOMEM;
2857
2858 cmd->header.code = cpu_to_le16(MWL8K_CMD_TX_POWER);
2859 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2860 cmd->action = cpu_to_le16(MWL8K_CMD_SET_LIST);
2861
2862 if (channel->band == IEEE80211_BAND_2GHZ)
2863 cmd->band = cpu_to_le16(0x1);
2864 else if (channel->band == IEEE80211_BAND_5GHZ)
2865 cmd->band = cpu_to_le16(0x4);
2866
604c4ef1 2867 cmd->channel = cpu_to_le16(channel->hw_value);
41fdf097
NS		 2868
2869 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2870 conf->channel_type == NL80211_CHAN_HT20) {
2871 cmd->bw = cpu_to_le16(0x2);
2872 } else {
2873 cmd->bw = cpu_to_le16(0x4);
2874 if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2875 cmd->sub_ch = cpu_to_le16(0x3);
2876 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2877 cmd->sub_ch = cpu_to_le16(0x1);
2878 }
2879
2880 for (i = 0; i < MWL8K_TX_POWER_LEVEL_TOTAL; i++)
2881 cmd->power_level_list[i] = cpu_to_le16(pwr);
2882
2883 rc = mwl8k_post_cmd(hw, &cmd->header);
2884 kfree(cmd);
2885
2886 return rc;
2887}
2888
08b06347
LB		 2889/*
2890 * CMD_RF_ANTENNA.
2891 */
2892struct mwl8k_cmd_rf_antenna {
2893 struct mwl8k_cmd_pkt header;
2894 __le16 antenna;
2895 __le16 mode;
ba2d3587 2896} __packed;
08b06347
LB		 2897
2898#define MWL8K_RF_ANTENNA_RX 1
2899#define MWL8K_RF_ANTENNA_TX 2
2900
2901static int
2902mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2903{
2904 struct mwl8k_cmd_rf_antenna *cmd;
2905 int rc;
2906
2907 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2908 if (cmd == NULL)
2909 return -ENOMEM;
2910
2911 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2912 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2913 cmd->antenna = cpu_to_le16(antenna);
2914 cmd->mode = cpu_to_le16(mask);
2915
2916 rc = mwl8k_post_cmd(hw, &cmd->header);
2917 kfree(cmd);
2918
2919 return rc;
2920}
2921
b64fe619
LB		 2922/*
2923 * CMD_SET_BEACON.
2924 */
2925struct mwl8k_cmd_set_beacon {
2926 struct mwl8k_cmd_pkt header;
2927 __le16 beacon_len;
2928 __u8 beacon[0];
2929};
2930
aa21d0f6
LB		 2931static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw,
2932 struct ieee80211_vif *vif, u8 *beacon, int len)
b64fe619
LB		 2933{
2934 struct mwl8k_cmd_set_beacon *cmd;
2935 int rc;
2936
2937 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2938 if (cmd == NULL)
2939 return -ENOMEM;
2940
2941 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2942 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2943 cmd->beacon_len = cpu_to_le16(len);
2944 memcpy(cmd->beacon, beacon, len);
2945
aa21d0f6 2946 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 2947 kfree(cmd);
2948
2949 return rc;
2950}
2951
a66098da
LB		 2952/*
2953 * CMD_SET_PRE_SCAN.
2954 */
2955struct mwl8k_cmd_set_pre_scan {
2956 struct mwl8k_cmd_pkt header;
ba2d3587 2957} __packed;
a66098da
LB		 2958
2959static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2960{
2961 struct mwl8k_cmd_set_pre_scan *cmd;
2962 int rc;
2963
2964 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2965 if (cmd == NULL)
2966 return -ENOMEM;
2967
2968 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2969 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2970
2971 rc = mwl8k_post_cmd(hw, &cmd->header);
2972 kfree(cmd);
2973
2974 return rc;
2975}
2976
2977/*
2978 * CMD_SET_POST_SCAN.
2979 */
2980struct mwl8k_cmd_set_post_scan {
2981 struct mwl8k_cmd_pkt header;
2982 __le32 isibss;
d89173f2 2983 __u8 bssid[ETH_ALEN];
ba2d3587 2984} __packed;
a66098da
LB		 2985
2986static int
0a11dfc3 2987mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 2988{
2989 struct mwl8k_cmd_set_post_scan *cmd;
2990 int rc;
2991
2992 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2993 if (cmd == NULL)
2994 return -ENOMEM;
2995
2996 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2997 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2998 cmd->isibss = 0;
d89173f2 2999 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 3000
3001 rc = mwl8k_post_cmd(hw, &cmd->header);
3002 kfree(cmd);
3003
3004 return rc;
3005}
3006
3007/*
3008 * CMD_SET_RF_CHANNEL.
3009 */
3010struct mwl8k_cmd_set_rf_channel {
3011 struct mwl8k_cmd_pkt header;
3012 __le16 action;
3013 __u8 current_channel;
3014 __le32 channel_flags;
ba2d3587 3015} __packed;
a66098da
LB		 3016
3017static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 3018 struct ieee80211_conf *conf)
a66098da 3019{
610677d2 3020 struct ieee80211_channel *channel = conf->channel;
a66098da
LB		 3021 struct mwl8k_cmd_set_rf_channel *cmd;
3022 int rc;
3023
3024 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3025 if (cmd == NULL)
3026 return -ENOMEM;
3027
3028 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
3029 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3030 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3031 cmd->current_channel = channel->hw_value;
610677d2 3032
a66098da 3033 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2 3034 cmd->channel_flags |= cpu_to_le32(0x00000001);
42574ea2
LB		 3035 else if (channel->band == IEEE80211_BAND_5GHZ)
3036 cmd->channel_flags |= cpu_to_le32(0x00000004);
610677d2
LB		 3037
3038 if (conf->channel_type == NL80211_CHAN_NO_HT ||
3039 conf->channel_type == NL80211_CHAN_HT20)
3040 cmd->channel_flags |= cpu_to_le32(0x00000080);
3041 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
3042 cmd->channel_flags |= cpu_to_le32(0x000001900);
3043 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
3044 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB		 3045
3046 rc = mwl8k_post_cmd(hw, &cmd->header);
3047 kfree(cmd);
3048
3049 return rc;
3050}
3051
3052/*
55489b6e 3053 * CMD_SET_AID.
a66098da 3054 */
55489b6e
LB		 3055#define MWL8K_FRAME_PROT_DISABLED 0x00
3056#define MWL8K_FRAME_PROT_11G 0x07
3057#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
3058#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 3059
55489b6e
LB		 3060struct mwl8k_cmd_update_set_aid {
3061 struct mwl8k_cmd_pkt header;
3062 __le16 aid;
a66098da 3063
55489b6e
LB		 3064 /* AP's MAC address (BSSID) */
3065 __u8 bssid[ETH_ALEN];
3066 __le16 protection_mode;
3067 __u8 supp_rates[14];
ba2d3587 3068} __packed;
a66098da 3069
c6e96010
LB		 3070static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
3071{
3072 int i;
3073 int j;
3074
3075 /*
3076 * Clear nonstandard rates 4 and 13.
3077 */
3078 mask &= 0x1fef;
3079
3080 for (i = 0, j = 0; i < 14; i++) {
3081 if (mask & (1 << i))
777ad375 3082 rates[j++] = mwl8k_rates_24[i].hw_value;
c6e96010
LB		 3083 }
3084}
3085
55489b6e 3086static int
c6e96010
LB		 3087mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
3088 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 3089{
55489b6e
LB		 3090 struct mwl8k_cmd_update_set_aid *cmd;
3091 u16 prot_mode;
a66098da
LB		 3092 int rc;
3093
3094 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3095 if (cmd == NULL)
3096 return -ENOMEM;
3097
55489b6e 3098 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 3099 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 3100 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 3101 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 3102
7dc6a7a7 3103 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 3104 prot_mode = MWL8K_FRAME_PROT_11G;
3105 } else {
7dc6a7a7 3106 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 3107 IEEE80211_HT_OP_MODE_PROTECTION) {
3108 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
3109 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
3110 break;
3111 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
3112 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
3113 break;
3114 default:
3115 prot_mode = MWL8K_FRAME_PROT_DISABLED;
3116 break;
3117 }
3118 }
3119 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 3120
c6e96010 3121 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 3122
3123 rc = mwl8k_post_cmd(hw, &cmd->header);
3124 kfree(cmd);
3125
3126 return rc;
3127}
3128
32060e1b 3129/*
55489b6e 3130 * CMD_SET_RATE.
32060e1b 3131 */
55489b6e
LB		 3132struct mwl8k_cmd_set_rate {
3133 struct mwl8k_cmd_pkt header;
3134 __u8 legacy_rates[14];
3135
3136 /* Bitmap for supported MCS codes. */
3137 __u8 mcs_set[16];
3138 __u8 reserved[16];
ba2d3587 3139} __packed;
32060e1b 3140
55489b6e 3141static int
c6e96010 3142mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 3143 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 3144{
55489b6e 3145 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 3146 int rc;
3147
3148 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3149 if (cmd == NULL)
3150 return -ENOMEM;
3151
55489b6e 3152 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 3153 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 3154 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 3155 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB		 3156
3157 rc = mwl8k_post_cmd(hw, &cmd->header);
3158 kfree(cmd);
3159
3160 return rc;
3161}
3162
a66098da 3163/*
55489b6e 3164 * CMD_FINALIZE_JOIN.
a66098da 3165 */
55489b6e
LB		 3166#define MWL8K_FJ_BEACON_MAXLEN 128
3167
3168struct mwl8k_cmd_finalize_join {
a66098da 3169 struct mwl8k_cmd_pkt header;
55489b6e
LB		 3170 __le32 sleep_interval; /* Number of beacon periods to sleep */
3171 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
ba2d3587 3172} __packed;
a66098da 3173
55489b6e
LB		 3174static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
3175 int framelen, int dtim)
a66098da 3176{
55489b6e
LB		 3177 struct mwl8k_cmd_finalize_join *cmd;
3178 struct ieee80211_mgmt *payload = frame;
3179 int payload_len;
a66098da
LB		 3180 int rc;
3181
3182 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3183 if (cmd == NULL)
3184 return -ENOMEM;
3185
55489b6e 3186 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 3187 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3188 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
3189
3190 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
3191 if (payload_len < 0)
3192 payload_len = 0;
3193 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
3194 payload_len = MWL8K_FJ_BEACON_MAXLEN;
3195
3196 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 3197
3198 rc = mwl8k_post_cmd(hw, &cmd->header);
3199 kfree(cmd);
3200
3201 return rc;
3202}
3203
3204/*
55489b6e 3205 * CMD_SET_RTS_THRESHOLD.
a66098da 3206 */
55489b6e 3207struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 3208 struct mwl8k_cmd_pkt header;
3209 __le16 action;
55489b6e 3210 __le16 threshold;
ba2d3587 3211} __packed;
a66098da 3212
c2c2b12a
LB		 3213static int
3214mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 3215{
55489b6e 3216 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 3217 int rc;
3218
3219 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3220 if (cmd == NULL)
3221 return -ENOMEM;
3222
55489b6e 3223 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 3224 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB		 3225 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3226 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB		 3227
3228 rc = mwl8k_post_cmd(hw, &cmd->header);
3229 kfree(cmd);
3230
a66098da
LB		 3231 return rc;
3232}
3233
3234/*
55489b6e 3235 * CMD_SET_SLOT.
a66098da 3236 */
55489b6e 3237struct mwl8k_cmd_set_slot {
a66098da
LB		 3238 struct mwl8k_cmd_pkt header;
3239 __le16 action;
55489b6e 3240 __u8 short_slot;
ba2d3587 3241} __packed;
a66098da 3242
55489b6e 3243static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 3244{
55489b6e 3245 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 3246 int rc;
3247
3248 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3249 if (cmd == NULL)
3250 return -ENOMEM;
3251
55489b6e 3252 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 3253 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3254 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3255 cmd->short_slot = short_slot_time;
a66098da
LB		 3256
3257 rc = mwl8k_post_cmd(hw, &cmd->header);
3258 kfree(cmd);
3259
3260 return rc;
3261}
3262
3263/*
3264 * CMD_SET_EDCA_PARAMS.
3265 */
3266struct mwl8k_cmd_set_edca_params {
3267 struct mwl8k_cmd_pkt header;
3268
3269 /* See MWL8K_SET_EDCA_XXX below */
3270 __le16 action;
3271
3272 /* TX opportunity in units of 32 us */
3273 __le16 txop;
3274
2e484c89
LB		 3275 union {
3276 struct {
3277 /* Log exponent of max contention period: 0...15 */
3278 __le32 log_cw_max;
3279
3280 /* Log exponent of min contention period: 0...15 */
3281 __le32 log_cw_min;
3282
3283 /* Adaptive interframe spacing in units of 32us */
3284 __u8 aifs;
3285
3286 /* TX queue to configure */
3287 __u8 txq;
3288 } ap;
3289 struct {
3290 /* Log exponent of max contention period: 0...15 */
3291 __u8 log_cw_max;
a66098da 3292
2e484c89
LB		 3293 /* Log exponent of min contention period: 0...15 */
3294 __u8 log_cw_min;
a66098da 3295
2e484c89
LB		 3296 /* Adaptive interframe spacing in units of 32us */
3297 __u8 aifs;
a66098da 3298
2e484c89
LB		 3299 /* TX queue to configure */
3300 __u8 txq;
3301 } sta;
3302 };
ba2d3587 3303} __packed;
a66098da 3304
a66098da
LB		 3305#define MWL8K_SET_EDCA_CW 0x01
3306#define MWL8K_SET_EDCA_TXOP 0x02
3307#define MWL8K_SET_EDCA_AIFS 0x04
3308
3309#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
3310 MWL8K_SET_EDCA_TXOP | \
3311 MWL8K_SET_EDCA_AIFS)
3312
3313static int
55489b6e
LB		 3314mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
3315 __u16 cw_min, __u16 cw_max,
3316 __u8 aifs, __u16 txop)
a66098da 3317{
2e484c89 3318 struct mwl8k_priv *priv = hw->priv;
a66098da 3319 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 3320 int rc;
3321
3322 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3323 if (cmd == NULL)
3324 return -ENOMEM;
3325
a66098da
LB		 3326 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
3327 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 3328 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
3329 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 3330 if (priv->ap_fw) {
3331 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
3332 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
3333 cmd->ap.aifs = aifs;
3334 cmd->ap.txq = qnum;
3335 } else {
3336 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
3337 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
3338 cmd->sta.aifs = aifs;
3339 cmd->sta.txq = qnum;
3340 }
a66098da
LB		 3341
3342 rc = mwl8k_post_cmd(hw, &cmd->header);
3343 kfree(cmd);
3344
3345 return rc;
3346}
3347
3348/*
55489b6e 3349 * CMD_SET_WMM_MODE.
a66098da 3350 */
55489b6e 3351struct mwl8k_cmd_set_wmm_mode {
a66098da 3352 struct mwl8k_cmd_pkt header;
55489b6e 3353 __le16 action;
ba2d3587 3354} __packed;
a66098da 3355
55489b6e 3356static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 3357{
55489b6e
LB		 3358 struct mwl8k_priv *priv = hw->priv;
3359 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 3360 int rc;
3361
a66098da
LB		 3362 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3363 if (cmd == NULL)
3364 return -ENOMEM;
3365
55489b6e 3366 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 3367 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 3368 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 3369
3370 rc = mwl8k_post_cmd(hw, &cmd->header);
3371 kfree(cmd);
16cec43d 3372
55489b6e
LB		 3373 if (!rc)
3374 priv->wmm_enabled = enable;
a66098da
LB		 3375
3376 return rc;
3377}
3378
3379/*
55489b6e 3380 * CMD_MIMO_CONFIG.
a66098da 3381 */
55489b6e
LB		 3382struct mwl8k_cmd_mimo_config {
3383 struct mwl8k_cmd_pkt header;
3384 __le32 action;
3385 __u8 rx_antenna_map;
3386 __u8 tx_antenna_map;
ba2d3587 3387} __packed;
a66098da 3388
55489b6e 3389static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 3390{
55489b6e 3391 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 3392 int rc;
3393
3394 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3395 if (cmd == NULL)
3396 return -ENOMEM;
3397
55489b6e 3398 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 3399 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3400 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
3401 cmd->rx_antenna_map = rx;
3402 cmd->tx_antenna_map = tx;
a66098da
LB		 3403
3404 rc = mwl8k_post_cmd(hw, &cmd->header);
3405 kfree(cmd);
3406
3407 return rc;
3408}
3409
3410/*
b71ed2c6 3411 * CMD_USE_FIXED_RATE (STA version).
a66098da 3412 */
b71ed2c6
LB		 3413struct mwl8k_cmd_use_fixed_rate_sta {
3414 struct mwl8k_cmd_pkt header;
3415 __le32 action;
3416 __le32 allow_rate_drop;
3417 __le32 num_rates;
3418 struct {
3419 __le32 is_ht_rate;
3420 __le32 enable_retry;
3421 __le32 rate;
3422 __le32 retry_count;
3423 } rate_entry[8];
3424 __le32 rate_type;
3425 __le32 reserved1;
3426 __le32 reserved2;
ba2d3587 3427} __packed;
a66098da 3428
b71ed2c6
LB		 3429#define MWL8K_USE_AUTO_RATE 0x0002
3430#define MWL8K_UCAST_RATE 0
a66098da 3431
b71ed2c6 3432static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 3433{
b71ed2c6 3434 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB		 3435 int rc;
3436
3437 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3438 if (cmd == NULL)
3439 return -ENOMEM;
3440
3441 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3442 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB		 3443 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3444 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB		 3445
3446 rc = mwl8k_post_cmd(hw, &cmd->header);
3447 kfree(cmd);
3448
3449 return rc;
3450}
3451
088aab8b
LB		 3452/*
3453 * CMD_USE_FIXED_RATE (AP version).
3454 */
3455struct mwl8k_cmd_use_fixed_rate_ap {
3456 struct mwl8k_cmd_pkt header;
3457 __le32 action;
3458 __le32 allow_rate_drop;
3459 __le32 num_rates;
3460 struct mwl8k_rate_entry_ap {
3461 __le32 is_ht_rate;
3462 __le32 enable_retry;
3463 __le32 rate;
3464 __le32 retry_count;
3465 } rate_entry[4];
3466 u8 multicast_rate;
3467 u8 multicast_rate_type;
3468 u8 management_rate;
ba2d3587 3469} __packed;
088aab8b
LB		 3470
3471static int
3472mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
3473{
3474 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
3475 int rc;
3476
3477 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3478 if (cmd == NULL)
3479 return -ENOMEM;
3480
3481 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3482 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3483 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3484 cmd->multicast_rate = mcast;
3485 cmd->management_rate = mgmt;
3486
3487 rc = mwl8k_post_cmd(hw, &cmd->header);
3488 kfree(cmd);
3489
3490 return rc;
3491}
3492
55489b6e
LB		 3493/*
3494 * CMD_ENABLE_SNIFFER.
3495 */
3496struct mwl8k_cmd_enable_sniffer {
3497 struct mwl8k_cmd_pkt header;
3498 __le32 action;
ba2d3587 3499} __packed;
55489b6e
LB		 3500
3501static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
3502{
3503 struct mwl8k_cmd_enable_sniffer *cmd;
3504 int rc;
3505
3506 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3507 if (cmd == NULL)
3508 return -ENOMEM;
3509
3510 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
3511 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3512 cmd->action = cpu_to_le32(!!enable);
3513
3514 rc = mwl8k_post_cmd(hw, &cmd->header);
3515 kfree(cmd);
3516
3517 return rc;
3518}
3519
197a4e4e 3520struct mwl8k_cmd_update_mac_addr {
55489b6e
LB		 3521 struct mwl8k_cmd_pkt header;
3522 union {
3523 struct {
3524 __le16 mac_type;
3525 __u8 mac_addr[ETH_ALEN];
3526 } mbss;
3527 __u8 mac_addr[ETH_ALEN];
3528 };
ba2d3587 3529} __packed;
55489b6e 3530
ee0ddf18
LB		 3531#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
3532#define MWL8K_MAC_TYPE_SECONDARY_CLIENT 1
3533#define MWL8K_MAC_TYPE_PRIMARY_AP 2
3534#define MWL8K_MAC_TYPE_SECONDARY_AP 3
a9e00b15 3535
197a4e4e
YAP		 3536static int mwl8k_cmd_update_mac_addr(struct ieee80211_hw *hw,
3537 struct ieee80211_vif *vif, u8 *mac, bool set)
55489b6e
LB		 3538{
3539 struct mwl8k_priv *priv = hw->priv;
ee0ddf18 3540 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
197a4e4e 3541 struct mwl8k_cmd_update_mac_addr *cmd;
ee0ddf18 3542 int mac_type;
55489b6e
LB		 3543 int rc;
3544
ee0ddf18
LB		 3545 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3546 if (vif != NULL && vif->type == NL80211_IFTYPE_STATION) {
3547 if (mwl8k_vif->macid + 1 == ffs(priv->sta_macids_supported))
af458831
YAP		 3548 if (priv->ap_fw)
3549 mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3550 else
3551 mac_type = MWL8K_MAC_TYPE_PRIMARY_CLIENT;
ee0ddf18
LB		 3552 else
3553 mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3554 } else if (vif != NULL && vif->type == NL80211_IFTYPE_AP) {
3555 if (mwl8k_vif->macid + 1 == ffs(priv->ap_macids_supported))
3556 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3557 else
3558 mac_type = MWL8K_MAC_TYPE_SECONDARY_AP;
3559 }
3560
55489b6e
LB		 3561 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3562 if (cmd == NULL)
3563 return -ENOMEM;
3564
197a4e4e
YAP		 3565 if (set)
3566 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
3567 else
3568 cmd->header.code = cpu_to_le16(MWL8K_CMD_DEL_MAC_ADDR);
3569
55489b6e
LB		 3570 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3571 if (priv->ap_fw) {
ee0ddf18 3572 cmd->mbss.mac_type = cpu_to_le16(mac_type);
55489b6e
LB		 3573 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
3574 } else {
3575 memcpy(cmd->mac_addr, mac, ETH_ALEN);
3576 }
3577
aa21d0f6 3578 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
55489b6e
LB		 3579 kfree(cmd);
3580
3581 return rc;
3582}
3583
197a4e4e
YAP		 3584/*
3585 * MWL8K_CMD_SET_MAC_ADDR.
3586 */
3587static inline int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw,
3588 struct ieee80211_vif *vif, u8 *mac)
3589{
3590 return mwl8k_cmd_update_mac_addr(hw, vif, mac, true);
3591}
3592
3593/*
3594 * MWL8K_CMD_DEL_MAC_ADDR.
3595 */
3596static inline int mwl8k_cmd_del_mac_addr(struct ieee80211_hw *hw,
3597 struct ieee80211_vif *vif, u8 *mac)
3598{
3599 return mwl8k_cmd_update_mac_addr(hw, vif, mac, false);
3600}
3601
55489b6e
LB		 3602/*
3603 * CMD_SET_RATEADAPT_MODE.
3604 */
3605struct mwl8k_cmd_set_rate_adapt_mode {
3606 struct mwl8k_cmd_pkt header;
3607 __le16 action;
3608 __le16 mode;
ba2d3587 3609} __packed;
55489b6e
LB		 3610
3611static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
3612{
3613 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
3614 int rc;
3615
3616 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3617 if (cmd == NULL)
3618 return -ENOMEM;
3619
3620 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
3621 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3622 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3623 cmd->mode = cpu_to_le16(mode);
3624
3625 rc = mwl8k_post_cmd(hw, &cmd->header);
3626 kfree(cmd);
3627
3628 return rc;
3629}
3630
3aefc37e
NS		 3631/*
3632 * CMD_GET_WATCHDOG_BITMAP.
3633 */
3634struct mwl8k_cmd_get_watchdog_bitmap {
3635 struct mwl8k_cmd_pkt header;
3636 u8 bitmap;
3637} __packed;
3638
3639static int mwl8k_cmd_get_watchdog_bitmap(struct ieee80211_hw *hw, u8 *bitmap)
3640{
3641 struct mwl8k_cmd_get_watchdog_bitmap *cmd;
3642 int rc;
3643
3644 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3645 if (cmd == NULL)
3646 return -ENOMEM;
3647
3648 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_WATCHDOG_BITMAP);
3649 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3650
3651 rc = mwl8k_post_cmd(hw, &cmd->header);
3652 if (!rc)
3653 *bitmap = cmd->bitmap;
3654
3655 kfree(cmd);
3656
3657 return rc;
3658}
3659
cfacba12
YAP		 3660#define MWL8K_WMM_QUEUE_NUMBER 3
3661
3662static void mwl8k_destroy_ba(struct ieee80211_hw *hw,
3663 u8 idx);
3664
3aefc37e
NS		 3665static void mwl8k_watchdog_ba_events(struct work_struct *work)
3666{
3667 int rc;
3668 u8 bitmap = 0, stream_index;
3669 struct mwl8k_ampdu_stream *streams;
3670 struct mwl8k_priv *priv =
3671 container_of(work, struct mwl8k_priv, watchdog_ba_handle);
cfacba12
YAP		 3672 struct ieee80211_hw *hw = priv->hw;
3673 int i;
3674 u32 status = 0;
3675
3676 mwl8k_fw_lock(hw);
3aefc37e
NS		 3677
3678 rc = mwl8k_cmd_get_watchdog_bitmap(priv->hw, &bitmap);
3679 if (rc)
cfacba12 3680 goto done;
3aefc37e 3681
cfacba12 3682 spin_lock(&priv->stream_lock);
3aefc37e
NS		 3683
3684 /* the bitmap is the hw queue number. Map it to the ampdu queue. */
cfacba12
YAP		 3685 for (i = 0; i < TOTAL_HW_TX_QUEUES; i++) {
3686 if (bitmap & (1 << i)) {
3687 stream_index = (i + MWL8K_WMM_QUEUE_NUMBER) %
3688 TOTAL_HW_TX_QUEUES;
3689 streams = &priv->ampdu[stream_index];
3690 if (streams->state == AMPDU_STREAM_ACTIVE) {
3691 ieee80211_stop_tx_ba_session(streams->sta,
3692 streams->tid);
3693 spin_unlock(&priv->stream_lock);
3694 mwl8k_destroy_ba(hw, stream_index);
3695 spin_lock(&priv->stream_lock);
3696 }
3697 }
3698 }
3aefc37e 3699
cfacba12
YAP		 3700 spin_unlock(&priv->stream_lock);
3701done:
c27a54d3 3702 atomic_dec(&priv->watchdog_event_pending);
cfacba12
YAP		 3703 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3704 iowrite32((status | MWL8K_A2H_INT_BA_WATCHDOG),
3705 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3706 mwl8k_fw_unlock(hw);
3aefc37e
NS		 3707 return;
3708}
3709
3710
b64fe619
LB		 3711/*
3712 * CMD_BSS_START.
3713 */
3714struct mwl8k_cmd_bss_start {
3715 struct mwl8k_cmd_pkt header;
3716 __le32 enable;
ba2d3587 3717} __packed;
b64fe619 3718
aa21d0f6
LB		 3719static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw,
3720 struct ieee80211_vif *vif, int enable)
b64fe619
LB		 3721{
3722 struct mwl8k_cmd_bss_start *cmd;
e882efc9
YAP		 3723 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3724 struct mwl8k_priv *priv = hw->priv;
b64fe619
LB		 3725 int rc;
3726
e882efc9
YAP		 3727 if (enable && (priv->running_bsses & (1 << mwl8k_vif->macid)))
3728 return 0;
3729
3730 if (!enable && !(priv->running_bsses & (1 << mwl8k_vif->macid)))
3731 return 0;
3732
b64fe619
LB		 3733 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3734 if (cmd == NULL)
3735 return -ENOMEM;
3736
3737 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
3738 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3739 cmd->enable = cpu_to_le32(enable);
3740
aa21d0f6 3741 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 3742 kfree(cmd);
3743
e882efc9
YAP		 3744 if (!rc) {
3745 if (enable)
3746 priv->running_bsses |= (1 << mwl8k_vif->macid);
3747 else
3748 priv->running_bsses &= ~(1 << mwl8k_vif->macid);
3749 }
b64fe619
LB		 3750 return rc;
3751}
3752
e882efc9
YAP		 3753static void mwl8k_enable_bsses(struct ieee80211_hw *hw, bool enable, u32 bitmap)
3754{
3755 struct mwl8k_priv *priv = hw->priv;
3756 struct mwl8k_vif *mwl8k_vif, *tmp_vif;
3757 struct ieee80211_vif *vif;
3758
3759 list_for_each_entry_safe(mwl8k_vif, tmp_vif, &priv->vif_list, list) {
3760 vif = mwl8k_vif->vif;
3761
3762 if (!(bitmap & (1 << mwl8k_vif->macid)))
3763 continue;
3764
3765 if (vif->type == NL80211_IFTYPE_AP)
3766 mwl8k_cmd_bss_start(hw, vif, enable);
3767 }
3768}
5faa1aff
NS		 3769/*
3770 * CMD_BASTREAM.
3771 */
3772
3773/*
3774 * UPSTREAM is tx direction
3775 */
3776#define BASTREAM_FLAG_DIRECTION_UPSTREAM 0x00
3777#define BASTREAM_FLAG_IMMEDIATE_TYPE 0x01
3778
ba30c4a5 3779enum ba_stream_action_type {
5faa1aff
NS		 3780 MWL8K_BA_CREATE,
3781 MWL8K_BA_UPDATE,
3782 MWL8K_BA_DESTROY,
3783 MWL8K_BA_FLUSH,
3784 MWL8K_BA_CHECK,
ba30c4a5 3785};
5faa1aff
NS		 3786
3787
3788struct mwl8k_create_ba_stream {
3789 __le32 flags;
3790 __le32 idle_thrs;
3791 __le32 bar_thrs;
3792 __le32 window_size;
3793 u8 peer_mac_addr[6];
3794 u8 dialog_token;
3795 u8 tid;
3796 u8 queue_id;
3797 u8 param_info;
3798 __le32 ba_context;
3799 u8 reset_seq_no_flag;
3800 __le16 curr_seq_no;
3801 u8 sta_src_mac_addr[6];
3802} __packed;
3803
3804struct mwl8k_destroy_ba_stream {
3805 __le32 flags;
3806 __le32 ba_context;
3807} __packed;
3808
3809struct mwl8k_cmd_bastream {
3810 struct mwl8k_cmd_pkt header;
3811 __le32 action;
3812 union {
3813 struct mwl8k_create_ba_stream create_params;
3814 struct mwl8k_destroy_ba_stream destroy_params;
3815 };
3816} __packed;
3817
3818static int
f95275c4
YAP		 3819mwl8k_check_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream,
3820 struct ieee80211_vif *vif)
5faa1aff
NS		 3821{
3822 struct mwl8k_cmd_bastream *cmd;
3823 int rc;
3824
3825 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3826 if (cmd == NULL)
3827 return -ENOMEM;
3828
3829 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3830 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3831
3832 cmd->action = cpu_to_le32(MWL8K_BA_CHECK);
3833
3834 cmd->create_params.queue_id = stream->idx;
3835 memcpy(&cmd->create_params.peer_mac_addr[0], stream->sta->addr,
3836 ETH_ALEN);
3837 cmd->create_params.tid = stream->tid;
3838
3839 cmd->create_params.flags =
3840 cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE) |
3841 cpu_to_le32(BASTREAM_FLAG_DIRECTION_UPSTREAM);
3842
f95275c4 3843 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
5faa1aff
NS		 3844
3845 kfree(cmd);
3846
3847 return rc;
3848}
3849
3850static int
3851mwl8k_create_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream,
f95275c4 3852 u8 buf_size, struct ieee80211_vif *vif)
5faa1aff
NS		 3853{
3854 struct mwl8k_cmd_bastream *cmd;
3855 int rc;
3856
3857 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3858 if (cmd == NULL)
3859 return -ENOMEM;
3860
3861
3862 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3863 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3864
3865 cmd->action = cpu_to_le32(MWL8K_BA_CREATE);
3866
3867 cmd->create_params.bar_thrs = cpu_to_le32((u32)buf_size);
3868 cmd->create_params.window_size = cpu_to_le32((u32)buf_size);
3869 cmd->create_params.queue_id = stream->idx;
3870
3871 memcpy(cmd->create_params.peer_mac_addr, stream->sta->addr, ETH_ALEN);
3872 cmd->create_params.tid = stream->tid;
3873 cmd->create_params.curr_seq_no = cpu_to_le16(0);
3874 cmd->create_params.reset_seq_no_flag = 1;
3875
3876 cmd->create_params.param_info =
3877 (stream->sta->ht_cap.ampdu_factor &
3878 IEEE80211_HT_AMPDU_PARM_FACTOR) |
3879 ((stream->sta->ht_cap.ampdu_density << 2) &
3880 IEEE80211_HT_AMPDU_PARM_DENSITY);
3881
3882 cmd->create_params.flags =
3883 cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE |
3884 BASTREAM_FLAG_DIRECTION_UPSTREAM);
3885
f95275c4 3886 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
5faa1aff
NS		 3887
3888 wiphy_debug(hw->wiphy, "Created a BA stream for %pM : tid %d\n",
3889 stream->sta->addr, stream->tid);
3890 kfree(cmd);
3891
3892 return rc;
3893}
3894
3895static void mwl8k_destroy_ba(struct ieee80211_hw *hw,
07f6dda1 3896 u8 idx)
5faa1aff
NS		 3897{
3898 struct mwl8k_cmd_bastream *cmd;
3899
3900 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3901 if (cmd == NULL)
3902 return;
3903
3904 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3905 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3906 cmd->action = cpu_to_le32(MWL8K_BA_DESTROY);
3907
07f6dda1 3908 cmd->destroy_params.ba_context = cpu_to_le32(idx);
5faa1aff
NS		 3909 mwl8k_post_cmd(hw, &cmd->header);
3910
07f6dda1 3911 wiphy_debug(hw->wiphy, "Deleted BA stream index %d\n", idx);
5faa1aff
NS		 3912
3913 kfree(cmd);
3914}
3915
3f5610ff
LB		 3916/*
3917 * CMD_SET_NEW_STN.
3918 */
3919struct mwl8k_cmd_set_new_stn {
3920 struct mwl8k_cmd_pkt header;
3921 __le16 aid;
3922 __u8 mac_addr[6];
3923 __le16 stn_id;
3924 __le16 action;
3925 __le16 rsvd;
3926 __le32 legacy_rates;
3927 __u8 ht_rates[4];
3928 __le16 cap_info;
3929 __le16 ht_capabilities_info;
3930 __u8 mac_ht_param_info;
3931 __u8 rev;
3932 __u8 control_channel;
3933 __u8 add_channel;
3934 __le16 op_mode;
3935 __le16 stbc;
3936 __u8 add_qos_info;
3937 __u8 is_qos_sta;
3938 __le32 fw_sta_ptr;
ba2d3587 3939} __packed;
3f5610ff
LB		 3940
3941#define MWL8K_STA_ACTION_ADD 0
3942#define MWL8K_STA_ACTION_REMOVE 2
3943
3944static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
3945 struct ieee80211_vif *vif,
3946 struct ieee80211_sta *sta)
3947{
3948 struct mwl8k_cmd_set_new_stn *cmd;
8707d026 3949 u32 rates;
3f5610ff
LB		 3950 int rc;
3951
3952 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3953 if (cmd == NULL)
3954 return -ENOMEM;
3955
3956 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3957 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3958 cmd->aid = cpu_to_le16(sta->aid);
3959 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
3960 cmd->stn_id = cpu_to_le16(sta->aid);
3961 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
8707d026
LB		 3962 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3963 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
3964 else
3965 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3966 cmd->legacy_rates = cpu_to_le32(rates);
3f5610ff
LB		 3967 if (sta->ht_cap.ht_supported) {
3968 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
3969 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
3970 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
3971 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
3972 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
3973 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
3974 ((sta->ht_cap.ampdu_density & 7) << 2);
3975 cmd->is_qos_sta = 1;
3976 }
3977
aa21d0f6 3978 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 3979 kfree(cmd);
3980
3981 return rc;
3982}
3983
b64fe619
LB		 3984static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
3985 struct ieee80211_vif *vif)
3986{
3987 struct mwl8k_cmd_set_new_stn *cmd;
3988 int rc;
3989
3990 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3991 if (cmd == NULL)
3992 return -ENOMEM;
3993
3994 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3995 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3996 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
3997
aa21d0f6 3998 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 3999 kfree(cmd);
4000
4001 return rc;
4002}
4003
3f5610ff
LB		 4004static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
4005 struct ieee80211_vif *vif, u8 *addr)
4006{
4007 struct mwl8k_cmd_set_new_stn *cmd;
0dd13a48
YAP		 4008 struct mwl8k_priv *priv = hw->priv;
4009 int rc, i;
4010 u8 idx;
4011
4012 spin_lock(&priv->stream_lock);
4013 /* Destroy any active ampdu streams for this sta */
4014 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
4015 struct mwl8k_ampdu_stream *s;
4016 s = &priv->ampdu[i];
4017 if (s->state != AMPDU_NO_STREAM) {
4018 if (memcmp(s->sta->addr, addr, ETH_ALEN) == 0) {
4019 if (s->state == AMPDU_STREAM_ACTIVE) {
4020 idx = s->idx;
4021 spin_unlock(&priv->stream_lock);
4022 mwl8k_destroy_ba(hw, idx);
4023 spin_lock(&priv->stream_lock);
4024 } else if (s->state == AMPDU_STREAM_NEW) {
4025 mwl8k_remove_stream(hw, s);
4026 }
4027 }
4028 }
4029 }
4030
4031 spin_unlock(&priv->stream_lock);
3f5610ff
LB		 4032
4033 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4034 if (cmd == NULL)
4035 return -ENOMEM;
4036
4037 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
4038 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4039 memcpy(cmd->mac_addr, addr, ETH_ALEN);
4040 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
4041
aa21d0f6 4042 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 4043 kfree(cmd);
4044
4045 return rc;
4046}
4047
fcdc403c
NS		 4048/*
4049 * CMD_UPDATE_ENCRYPTION.
4050 */
4051
4052#define MAX_ENCR_KEY_LENGTH 16
4053#define MIC_KEY_LENGTH 8
4054
4055struct mwl8k_cmd_update_encryption {
4056 struct mwl8k_cmd_pkt header;
4057
4058 __le32 action;
4059 __le32 reserved;
4060 __u8 mac_addr[6];
4061 __u8 encr_type;
4062
ba30c4a5 4063} __packed;
fcdc403c
NS		 4064
4065struct mwl8k_cmd_set_key {
4066 struct mwl8k_cmd_pkt header;
4067
4068 __le32 action;
4069 __le32 reserved;
4070 __le16 length;
4071 __le16 key_type_id;
4072 __le32 key_info;
4073 __le32 key_id;
4074 __le16 key_len;
4075 __u8 key_material[MAX_ENCR_KEY_LENGTH];
4076 __u8 tkip_tx_mic_key[MIC_KEY_LENGTH];
4077 __u8 tkip_rx_mic_key[MIC_KEY_LENGTH];
4078 __le16 tkip_rsc_low;
4079 __le32 tkip_rsc_high;
4080 __le16 tkip_tsc_low;
4081 __le32 tkip_tsc_high;
4082 __u8 mac_addr[6];
ba30c4a5 4083} __packed;
fcdc403c
NS		 4084
4085enum {
4086 MWL8K_ENCR_ENABLE,
4087 MWL8K_ENCR_SET_KEY,
4088 MWL8K_ENCR_REMOVE_KEY,
4089 MWL8K_ENCR_SET_GROUP_KEY,
4090};
4091
4092#define MWL8K_UPDATE_ENCRYPTION_TYPE_WEP 0
4093#define MWL8K_UPDATE_ENCRYPTION_TYPE_DISABLE 1
4094#define MWL8K_UPDATE_ENCRYPTION_TYPE_TKIP 4
4095#define MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED 7
4096#define MWL8K_UPDATE_ENCRYPTION_TYPE_AES 8
4097
4098enum {
4099 MWL8K_ALG_WEP,
4100 MWL8K_ALG_TKIP,
4101 MWL8K_ALG_CCMP,
4102};
4103
4104#define MWL8K_KEY_FLAG_TXGROUPKEY 0x00000004
4105#define MWL8K_KEY_FLAG_PAIRWISE 0x00000008
4106#define MWL8K_KEY_FLAG_TSC_VALID 0x00000040
4107#define MWL8K_KEY_FLAG_WEP_TXKEY 0x01000000
4108#define MWL8K_KEY_FLAG_MICKEY_VALID 0x02000000
4109
4110static int mwl8k_cmd_update_encryption_enable(struct ieee80211_hw *hw,
4111 struct ieee80211_vif *vif,
4112 u8 *addr,
4113 u8 encr_type)
4114{
4115 struct mwl8k_cmd_update_encryption *cmd;
4116 int rc;
4117
4118 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4119 if (cmd == NULL)
4120 return -ENOMEM;
4121
4122 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
4123 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4124 cmd->action = cpu_to_le32(MWL8K_ENCR_ENABLE);
4125 memcpy(cmd->mac_addr, addr, ETH_ALEN);
4126 cmd->encr_type = encr_type;
4127
4128 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4129 kfree(cmd);
4130
4131 return rc;
4132}
4133
4134static int mwl8k_encryption_set_cmd_info(struct mwl8k_cmd_set_key *cmd,
4135 u8 *addr,
4136 struct ieee80211_key_conf *key)
4137{
4138 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
4139 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4140 cmd->length = cpu_to_le16(sizeof(*cmd) -
4141 offsetof(struct mwl8k_cmd_set_key, length));
4142 cmd->key_id = cpu_to_le32(key->keyidx);
4143 cmd->key_len = cpu_to_le16(key->keylen);
4144 memcpy(cmd->mac_addr, addr, ETH_ALEN);
4145
4146 switch (key->cipher) {
4147 case WLAN_CIPHER_SUITE_WEP40:
4148 case WLAN_CIPHER_SUITE_WEP104:
4149 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_WEP);
4150 if (key->keyidx == 0)
4151 cmd->key_info = cpu_to_le32(MWL8K_KEY_FLAG_WEP_TXKEY);
4152
4153 break;
4154 case WLAN_CIPHER_SUITE_TKIP:
4155 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_TKIP);
4156 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4157 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
4158 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
4159 cmd->key_info |= cpu_to_le32(MWL8K_KEY_FLAG_MICKEY_VALID
4160 | MWL8K_KEY_FLAG_TSC_VALID);
4161 break;
4162 case WLAN_CIPHER_SUITE_CCMP:
4163 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_CCMP);
4164 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4165 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
4166 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
4167 break;
4168 default:
4169 return -ENOTSUPP;
4170 }
4171
4172 return 0;
4173}
4174
4175static int mwl8k_cmd_encryption_set_key(struct ieee80211_hw *hw,
4176 struct ieee80211_vif *vif,
4177 u8 *addr,
4178 struct ieee80211_key_conf *key)
4179{
4180 struct mwl8k_cmd_set_key *cmd;
4181 int rc;
4182 int keymlen;
4183 u32 action;
4184 u8 idx;
4185 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4186
4187 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4188 if (cmd == NULL)
4189 return -ENOMEM;
4190
4191 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
4192 if (rc < 0)
4193 goto done;
4194
4195 idx = key->keyidx;
4196
4197 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4198 action = MWL8K_ENCR_SET_KEY;
4199 else
4200 action = MWL8K_ENCR_SET_GROUP_KEY;
4201
4202 switch (key->cipher) {
4203 case WLAN_CIPHER_SUITE_WEP40:
4204 case WLAN_CIPHER_SUITE_WEP104:
4205 if (!mwl8k_vif->wep_key_conf[idx].enabled) {
4206 memcpy(mwl8k_vif->wep_key_conf[idx].key, key,
4207 sizeof(*key) + key->keylen);
4208 mwl8k_vif->wep_key_conf[idx].enabled = 1;
4209 }
4210
9b571e24 4211 keymlen = key->keylen;
fcdc403c
NS		 4212 action = MWL8K_ENCR_SET_KEY;
4213 break;
4214 case WLAN_CIPHER_SUITE_TKIP:
4215 keymlen = MAX_ENCR_KEY_LENGTH + 2 * MIC_KEY_LENGTH;
4216 break;
4217 case WLAN_CIPHER_SUITE_CCMP:
4218 keymlen = key->keylen;
4219 break;
4220 default:
4221 rc = -ENOTSUPP;
4222 goto done;
4223 }
4224
4225 memcpy(cmd->key_material, key->key, keymlen);
4226 cmd->action = cpu_to_le32(action);
4227
4228 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4229done:
4230 kfree(cmd);
4231
4232 return rc;
4233}
4234
4235static int mwl8k_cmd_encryption_remove_key(struct ieee80211_hw *hw,
4236 struct ieee80211_vif *vif,
4237 u8 *addr,
4238 struct ieee80211_key_conf *key)
4239{
4240 struct mwl8k_cmd_set_key *cmd;
4241 int rc;
4242 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4243
4244 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4245 if (cmd == NULL)
4246 return -ENOMEM;
4247
4248 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
4249 if (rc < 0)
4250 goto done;
4251
4252 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
d981e059 4253 key->cipher == WLAN_CIPHER_SUITE_WEP104)
fcdc403c
NS		 4254 mwl8k_vif->wep_key_conf[key->keyidx].enabled = 0;
4255
4256 cmd->action = cpu_to_le32(MWL8K_ENCR_REMOVE_KEY);
4257
4258 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4259done:
4260 kfree(cmd);
4261
4262 return rc;
4263}
4264
4265static int mwl8k_set_key(struct ieee80211_hw *hw,
4266 enum set_key_cmd cmd_param,
4267 struct ieee80211_vif *vif,
4268 struct ieee80211_sta *sta,
4269 struct ieee80211_key_conf *key)
4270{
4271 int rc = 0;
4272 u8 encr_type;
4273 u8 *addr;
4274 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
751930cb 4275 struct mwl8k_priv *priv = hw->priv;
fcdc403c 4276
751930cb 4277 if (vif->type == NL80211_IFTYPE_STATION && !priv->ap_fw)
fcdc403c
NS		 4278 return -EOPNOTSUPP;
4279
4280 if (sta == NULL)
ff7e9f99 4281 addr = vif->addr;
fcdc403c
NS		 4282 else
4283 addr = sta->addr;
4284
4285 if (cmd_param == SET_KEY) {
fcdc403c
NS		 4286 rc = mwl8k_cmd_encryption_set_key(hw, vif, addr, key);
4287 if (rc)
4288 goto out;
4289
4290 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40)
4291 || (key->cipher == WLAN_CIPHER_SUITE_WEP104))
4292 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_WEP;
4293 else
4294 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED;
4295
4296 rc = mwl8k_cmd_update_encryption_enable(hw, vif, addr,
4297 encr_type);
4298 if (rc)
4299 goto out;
4300
4301 mwl8k_vif->is_hw_crypto_enabled = true;
4302
4303 } else {
4304 rc = mwl8k_cmd_encryption_remove_key(hw, vif, addr, key);
4305
4306 if (rc)
4307 goto out;
fcdc403c
NS		 4308 }
4309out:
4310 return rc;
4311}
4312
55489b6e
LB		 4313/*
4314 * CMD_UPDATE_STADB.
4315 */
25d81b1e
LB		 4316struct ewc_ht_info {
4317 __le16 control1;
4318 __le16 control2;
4319 __le16 control3;
ba2d3587 4320} __packed;
25d81b1e
LB		 4321
4322struct peer_capability_info {
4323 /* Peer type - AP vs. STA. */
4324 __u8 peer_type;
4325
4326 /* Basic 802.11 capabilities from assoc resp. */
4327 __le16 basic_caps;
4328
4329 /* Set if peer supports 802.11n high throughput (HT). */
4330 __u8 ht_support;
4331
4332 /* Valid if HT is supported. */
4333 __le16 ht_caps;
4334 __u8 extended_ht_caps;
4335 struct ewc_ht_info ewc_info;
4336
4337 /* Legacy rate table. Intersection of our rates and peer rates. */
4338 __u8 legacy_rates[12];
4339
4340 /* HT rate table. Intersection of our rates and peer rates. */
4341 __u8 ht_rates[16];
4342 __u8 pad[16];
4343
4344 /* If set, interoperability mode, no proprietary extensions. */
4345 __u8 interop;
4346 __u8 pad2;
4347 __u8 station_id;
4348 __le16 amsdu_enabled;
ba2d3587 4349} __packed;
25d81b1e 4350
55489b6e
LB		 4351struct mwl8k_cmd_update_stadb {
4352 struct mwl8k_cmd_pkt header;
4353
4354 /* See STADB_ACTION_TYPE */
4355 __le32 action;
4356
4357 /* Peer MAC address */
4358 __u8 peer_addr[ETH_ALEN];
4359
4360 __le32 reserved;
4361
4362 /* Peer info - valid during add/update. */
4363 struct peer_capability_info peer_info;
ba2d3587 4364} __packed;
55489b6e 4365
a680400e
LB		 4366#define MWL8K_STA_DB_MODIFY_ENTRY 1
4367#define MWL8K_STA_DB_DEL_ENTRY 2
4368
4369/* Peer Entry flags - used to define the type of the peer node */
4370#define MWL8K_PEER_TYPE_ACCESSPOINT 2
4371
4372static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 4373 struct ieee80211_vif *vif,
13935e2c 4374 struct ieee80211_sta *sta)
55489b6e 4375{
55489b6e 4376 struct mwl8k_cmd_update_stadb *cmd;
a680400e 4377 struct peer_capability_info *p;
8707d026 4378 u32 rates;
55489b6e
LB		 4379 int rc;
4380
4381 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4382 if (cmd == NULL)
4383 return -ENOMEM;
4384
4385 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4386 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 4387 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 4388 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 4389
a680400e
LB		 4390 p = &cmd->peer_info;
4391 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
4392 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c 4393 p->ht_support = sta->ht_cap.ht_supported;
b603742f 4394 p->ht_caps = cpu_to_le16(sta->ht_cap.cap);
13935e2c
LB		 4395 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
4396 ((sta->ht_cap.ampdu_density & 7) << 2);
8707d026
LB		 4397 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
4398 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
4399 else
4400 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
4401 legacy_rate_mask_to_array(p->legacy_rates, rates);
13935e2c 4402 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB		 4403 p->interop = 1;
4404 p->amsdu_enabled = 0;
4405
4406 rc = mwl8k_post_cmd(hw, &cmd->header);
c4f74d35
NZ		 4407 if (!rc)
4408 rc = p->station_id;
a680400e
LB		 4409 kfree(cmd);
4410
c4f74d35 4411 return rc;
a680400e
LB		 4412}
4413
4414static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
4415 struct ieee80211_vif *vif, u8 *addr)
4416{
4417 struct mwl8k_cmd_update_stadb *cmd;
4418 int rc;
4419
4420 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4421 if (cmd == NULL)
4422 return -ENOMEM;
4423
4424 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4425 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4426 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 4427 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 4428
a680400e 4429 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 4430 kfree(cmd);
4431
4432 return rc;
4433}
4434
a66098da
LB		 4435
4436/*
4437 * Interrupt handling.
4438 */
4439static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
4440{
4441 struct ieee80211_hw *hw = dev_id;
4442 struct mwl8k_priv *priv = hw->priv;
4443 u32 status;
4444
4445 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB		 4446 if (!status)
4447 return IRQ_NONE;
4448
1e9f9de3
LB		 4449 if (status & MWL8K_A2H_INT_TX_DONE) {
4450 status &= ~MWL8K_A2H_INT_TX_DONE;
4451 tasklet_schedule(&priv->poll_tx_task);
4452 }
4453
a66098da 4454 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB		 4455 status &= ~MWL8K_A2H_INT_RX_READY;
4456 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB		 4457 }
4458
3aefc37e 4459 if (status & MWL8K_A2H_INT_BA_WATCHDOG) {
c27a54d3
YAP		 4460 iowrite32(~MWL8K_A2H_INT_BA_WATCHDOG,
4461 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
4462
4463 atomic_inc(&priv->watchdog_event_pending);
3aefc37e
NS		 4464 status &= ~MWL8K_A2H_INT_BA_WATCHDOG;
4465 ieee80211_queue_work(hw, &priv->watchdog_ba_handle);
4466 }
4467
67e2eb27
LB		 4468 if (status)
4469 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4470
a66098da 4471 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 4472 if (priv->hostcmd_wait != NULL)
a66098da 4473 complete(priv->hostcmd_wait);
a66098da
LB		 4474 }
4475
4476 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 4477 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 4478 priv->radio_on && priv->pending_tx_pkts)
618952a7 4479 mwl8k_tx_start(priv);
a66098da
LB		 4480 }
4481
4482 return IRQ_HANDLED;
4483}
4484
1e9f9de3
LB		 4485static void mwl8k_tx_poll(unsigned long data)
4486{
4487 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
4488 struct mwl8k_priv *priv = hw->priv;
4489 int limit;
4490 int i;
4491
4492 limit = 32;
4493
4494 spin_lock_bh(&priv->tx_lock);
4495
e600707b 4496 for (i = 0; i < mwl8k_tx_queues(priv); i++)
1e9f9de3
LB		 4497 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
4498
4499 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
4500 complete(priv->tx_wait);
4501 priv->tx_wait = NULL;
4502 }
4503
4504 spin_unlock_bh(&priv->tx_lock);
4505
4506 if (limit) {
4507 writel(~MWL8K_A2H_INT_TX_DONE,
4508 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4509 } else {
4510 tasklet_schedule(&priv->poll_tx_task);
4511 }
4512}
4513
67e2eb27
LB		 4514static void mwl8k_rx_poll(unsigned long data)
4515{
4516 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
4517 struct mwl8k_priv *priv = hw->priv;
4518 int limit;
4519
4520 limit = 32;
4521 limit -= rxq_process(hw, 0, limit);
4522 limit -= rxq_refill(hw, 0, limit);
4523
4524 if (limit) {
4525 writel(~MWL8K_A2H_INT_RX_READY,
4526 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4527 } else {
4528 tasklet_schedule(&priv->poll_rx_task);
4529 }
4530}
4531
a66098da
LB		 4532
4533/*
4534 * Core driver operations.
4535 */
36323f81
TH		 4536static void mwl8k_tx(struct ieee80211_hw *hw,
4537 struct ieee80211_tx_control *control,
4538 struct sk_buff *skb)
a66098da
LB		 4539{
4540 struct mwl8k_priv *priv = hw->priv;
4541 int index = skb_get_queue_mapping(skb);
a66098da 4542
9189c100 4543 if (!priv->radio_on) {
c96c31e4
JP		 4544 wiphy_debug(hw->wiphy,
4545 "dropped TX frame since radio disabled\n");
a66098da 4546 dev_kfree_skb(skb);
7bb45683 4547 return;
a66098da
LB		 4548 }
4549
36323f81 4550 mwl8k_txq_xmit(hw, index, control->sta, skb);
a66098da
LB		 4551}
4552
a66098da
LB		 4553static int mwl8k_start(struct ieee80211_hw *hw)
4554{
a66098da
LB		 4555 struct mwl8k_priv *priv = hw->priv;
4556 int rc;
4557
a0607fd3 4558 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 4559 IRQF_SHARED, MWL8K_NAME, hw);
4560 if (rc) {
bf3ca7f7 4561 priv->irq = -1;
5db55844 4562 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
2ec610cb 4563 return -EIO;
a66098da 4564 }
bf3ca7f7 4565 priv->irq = priv->pdev->irq;
a66098da 4566
67e2eb27 4567 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 4568 tasklet_enable(&priv->poll_tx_task);
67e2eb27 4569 tasklet_enable(&priv->poll_rx_task);
2ec610cb 4570
a66098da 4571 /* Enable interrupts */
c23b5a69 4572 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
12488e01
NS		 4573 iowrite32(MWL8K_A2H_EVENTS,
4574 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
a66098da 4575
2ec610cb
LB		 4576 rc = mwl8k_fw_lock(hw);
4577 if (!rc) {
55489b6e 4578 rc = mwl8k_cmd_radio_enable(hw);
a66098da 4579
5e4cf166
LB		 4580 if (!priv->ap_fw) {
4581 if (!rc)
55489b6e 4582 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 4583
5e4cf166
LB		 4584 if (!rc)
4585 rc = mwl8k_cmd_set_pre_scan(hw);
4586
4587 if (!rc)
4588 rc = mwl8k_cmd_set_post_scan(hw,
4589 "\x00\x00\x00\x00\x00\x00");
4590 }
2ec610cb
LB		 4591
4592 if (!rc)
55489b6e 4593 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 4594
2ec610cb 4595 if (!rc)
55489b6e 4596 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 4597
2ec610cb
LB		 4598 mwl8k_fw_unlock(hw);
4599 }
4600
4601 if (rc) {
4602 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
4603 free_irq(priv->pdev->irq, hw);
bf3ca7f7 4604 priv->irq = -1;
1e9f9de3 4605 tasklet_disable(&priv->poll_tx_task);
67e2eb27 4606 tasklet_disable(&priv->poll_rx_task);
4850b6d3
NS		 4607 } else {
4608 ieee80211_wake_queues(hw);
2ec610cb 4609 }
a66098da
LB		 4610
4611 return rc;
4612}
4613
a66098da
LB		 4614static void mwl8k_stop(struct ieee80211_hw *hw)
4615{
a66098da
LB		 4616 struct mwl8k_priv *priv = hw->priv;
4617 int i;
4618
6b6accc3
YAP		 4619 if (!priv->hw_restart_in_progress)
4620 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 4621
4622 ieee80211_stop_queues(hw);
4623
a66098da 4624 /* Disable interrupts */
a66098da 4625 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
bf3ca7f7
BC		 4626 if (priv->irq != -1) {
4627 free_irq(priv->pdev->irq, hw);
4628 priv->irq = -1;
4629 }
a66098da
LB		 4630
4631 /* Stop finalize join worker */
4632 cancel_work_sync(&priv->finalize_join_worker);
3aefc37e 4633 cancel_work_sync(&priv->watchdog_ba_handle);
a66098da
LB		 4634 if (priv->beacon_skb != NULL)
4635 dev_kfree_skb(priv->beacon_skb);
4636
67e2eb27 4637 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 4638 tasklet_disable(&priv->poll_tx_task);
67e2eb27 4639 tasklet_disable(&priv->poll_rx_task);
a66098da 4640
a66098da 4641 /* Return all skbs to mac80211 */
e600707b 4642 for (i = 0; i < mwl8k_tx_queues(priv); i++)
efb7c49a 4643 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB		 4644}
4645
0863ade8
BC		 4646static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image);
4647
a66098da 4648static int mwl8k_add_interface(struct ieee80211_hw *hw,
f5bb87cf 4649 struct ieee80211_vif *vif)
a66098da
LB		 4650{
4651 struct mwl8k_priv *priv = hw->priv;
4652 struct mwl8k_vif *mwl8k_vif;
ee0ddf18 4653 u32 macids_supported;
0863ade8
BC		 4654 int macid, rc;
4655 struct mwl8k_device_info *di;
a66098da 4656
a43c49a8
LB		 4657 /*
4658 * Reject interface creation if sniffer mode is active, as
4659 * STA operation is mutually exclusive with hardware sniffer
b64fe619 4660 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB		 4661 */
4662 if (priv->sniffer_enabled) {
c96c31e4
JP		 4663 wiphy_info(hw->wiphy,
4664 "unable to create STA interface because sniffer mode is enabled\n");
a43c49a8
LB		 4665 return -EINVAL;
4666 }
4667
0863ade8 4668 di = priv->device_info;
ee0ddf18
LB		 4669 switch (vif->type) {
4670 case NL80211_IFTYPE_AP:
0863ade8
BC		 4671 if (!priv->ap_fw && di->fw_image_ap) {
4672 /* we must load the ap fw to meet this request */
4673 if (!list_empty(&priv->vif_list))
4674 return -EBUSY;
4675 rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
4676 if (rc)
4677 return rc;
4678 }
ee0ddf18
LB		 4679 macids_supported = priv->ap_macids_supported;
4680 break;
4681 case NL80211_IFTYPE_STATION:
0863ade8 4682 if (priv->ap_fw && di->fw_image_sta) {
d59c1cfd
YAP		 4683 if (!list_empty(&priv->vif_list)) {
4684 wiphy_warn(hw->wiphy, "AP interface is running.\n"
4685 "Adding STA interface for WDS");
4686 } else {
4687 /* we must load the sta fw to
4688 * meet this request.
4689 */
4690 rc = mwl8k_reload_firmware(hw,
4691 di->fw_image_sta);
4692 if (rc)
4693 return rc;
4694 }
0863ade8 4695 }
ee0ddf18
LB		 4696 macids_supported = priv->sta_macids_supported;
4697 break;
4698 default:
4699 return -EINVAL;
4700 }
4701
4702 macid = ffs(macids_supported & ~priv->macids_used);
4703 if (!macid--)
4704 return -EBUSY;
4705
f5bb87cf 4706 /* Setup driver private area. */
1ed32e4f 4707 mwl8k_vif = MWL8K_VIF(vif);
a66098da 4708 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
f5bb87cf 4709 mwl8k_vif->vif = vif;
ee0ddf18 4710 mwl8k_vif->macid = macid;
a66098da 4711 mwl8k_vif->seqno = 0;
d9a07d49
NS		 4712 memcpy(mwl8k_vif->bssid, vif->addr, ETH_ALEN);
4713 mwl8k_vif->is_hw_crypto_enabled = false;
a66098da 4714
aa21d0f6
LB		 4715 /* Set the mac address. */
4716 mwl8k_cmd_set_mac_addr(hw, vif, vif->addr);
4717
d994a1c8 4718 if (vif->type == NL80211_IFTYPE_AP)
aa21d0f6
LB		 4719 mwl8k_cmd_set_new_stn_add_self(hw, vif);
4720
ee0ddf18 4721 priv->macids_used |= 1 << mwl8k_vif->macid;
f5bb87cf 4722 list_add_tail(&mwl8k_vif->list, &priv->vif_list);
a66098da
LB		 4723
4724 return 0;
4725}
4726
6b6accc3
YAP		 4727static void mwl8k_remove_vif(struct mwl8k_priv *priv, struct mwl8k_vif *vif)
4728{
4729 /* Has ieee80211_restart_hw re-added the removed interfaces? */
4730 if (!priv->macids_used)
4731 return;
4732
4733 priv->macids_used &= ~(1 << vif->macid);
4734 list_del(&vif->list);
4735}
4736
a66098da 4737static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4738 struct ieee80211_vif *vif)
a66098da
LB		 4739{
4740 struct mwl8k_priv *priv = hw->priv;
f5bb87cf 4741 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
a66098da 4742
d994a1c8 4743 if (vif->type == NL80211_IFTYPE_AP)
b64fe619
LB		 4744 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
4745
197a4e4e 4746 mwl8k_cmd_del_mac_addr(hw, vif, vif->addr);
32060e1b 4747
6b6accc3
YAP		 4748 mwl8k_remove_vif(priv, mwl8k_vif);
4749}
4750
4751static void mwl8k_hw_restart_work(struct work_struct *work)
4752{
4753 struct mwl8k_priv *priv =
4754 container_of(work, struct mwl8k_priv, fw_reload);
4755 struct ieee80211_hw *hw = priv->hw;
4756 struct mwl8k_device_info *di;
4757 int rc;
4758
4759 /* If some command is waiting for a response, clear it */
4760 if (priv->hostcmd_wait != NULL) {
4761 complete(priv->hostcmd_wait);
4762 priv->hostcmd_wait = NULL;
4763 }
4764
4765 priv->hw_restart_owner = current;
4766 di = priv->device_info;
4767 mwl8k_fw_lock(hw);
4768
4769 if (priv->ap_fw)
4770 rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
4771 else
4772 rc = mwl8k_reload_firmware(hw, di->fw_image_sta);
4773
4774 if (rc)
4775 goto fail;
4776
4777 priv->hw_restart_owner = NULL;
4778 priv->hw_restart_in_progress = false;
4779
4780 /*
4781 * This unlock will wake up the queues and
4782 * also opens the command path for other
4783 * commands
4784 */
4785 mwl8k_fw_unlock(hw);
4786
4787 ieee80211_restart_hw(hw);
4788
4789 wiphy_err(hw->wiphy, "Firmware restarted successfully\n");
4790
4791 return;
4792fail:
4793 mwl8k_fw_unlock(hw);
4794
4795 wiphy_err(hw->wiphy, "Firmware restart failed\n");
a66098da
LB		 4796}
4797
ee03a932 4798static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 4799{
a66098da
LB		 4800 struct ieee80211_conf *conf = &hw->conf;
4801 struct mwl8k_priv *priv = hw->priv;
ee03a932 4802 int rc;
a66098da 4803
7595d67a 4804 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 4805 mwl8k_cmd_radio_disable(hw);
ee03a932 4806 return 0;
7595d67a
LB		 4807 }
4808
ee03a932
LB		 4809 rc = mwl8k_fw_lock(hw);
4810 if (rc)
4811 return rc;
a66098da 4812
55489b6e 4813 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 4814 if (rc)
4815 goto out;
a66098da 4816
0f4316b9
YAP		 4817 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
4818 rc = mwl8k_cmd_set_rf_channel(hw, conf);
4819 if (rc)
4820 goto out;
4821 }
ee03a932 4822
a66098da
LB		 4823 if (conf->power_level > 18)
4824 conf->power_level = 18;
a66098da 4825
08b06347 4826 if (priv->ap_fw) {
03217087
NS		 4827
4828 if (conf->flags & IEEE80211_CONF_CHANGE_POWER) {
4829 rc = mwl8k_cmd_tx_power(hw, conf, conf->power_level);
4830 if (rc)
4831 goto out;
4832 }
41fdf097 4833
da62b761 4834
08b06347 4835 } else {
41fdf097
NS		 4836 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
4837 if (rc)
4838 goto out;
08b06347
LB		 4839 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
4840 }
a66098da 4841
ee03a932
LB		 4842out:
4843 mwl8k_fw_unlock(hw);
a66098da 4844
ee03a932 4845 return rc;
a66098da
LB		 4846}
4847
b64fe619
LB		 4848static void
4849mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4850 struct ieee80211_bss_conf *info, u32 changed)
a66098da 4851{
a66098da 4852 struct mwl8k_priv *priv = hw->priv;
ba30c4a5 4853 u32 ap_legacy_rates = 0;
13935e2c 4854 u8 ap_mcs_rates[16];
3a980d0a
LB		 4855 int rc;
4856
c3cbbe8a 4857 if (mwl8k_fw_lock(hw))
3a980d0a 4858 return;
a66098da 4859
c3cbbe8a
LB		 4860 /*
4861 * No need to capture a beacon if we're no longer associated.
4862 */
4863 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
4864 priv->capture_beacon = false;
3a980d0a 4865
c3cbbe8a 4866 /*
13935e2c 4867 * Get the AP's legacy and MCS rates.
c3cbbe8a 4868 */
7dc6a7a7 4869 if (vif->bss_conf.assoc) {
c6e96010 4870 struct ieee80211_sta *ap;
c97470dd 4871
c6e96010 4872 rcu_read_lock();
c6e96010 4873
c3cbbe8a
LB		 4874 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
4875 if (ap == NULL) {
4876 rcu_read_unlock();
c6e96010 4877 goto out;
c3cbbe8a
LB		 4878 }
4879
8707d026
LB		 4880 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
4881 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
4882 } else {
4883 ap_legacy_rates =
4884 ap->supp_rates[IEEE80211_BAND_5GHZ] << 5;
4885 }
13935e2c 4886 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB		 4887
4888 rcu_read_unlock();
4889 }
c6e96010 4890
dcee7438
YAP		 4891 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc &&
4892 !priv->ap_fw) {
13935e2c 4893 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB		 4894 if (rc)
4895 goto out;
a66098da 4896
b71ed2c6 4897 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB		 4898 if (rc)
4899 goto out;
dcee7438
YAP		 4900 } else {
4901 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc &&
4902 priv->ap_fw) {
4903 int idx;
4904 int rate;
4905
4906 /* Use AP firmware specific rate command.
4907 */
4908 idx = ffs(vif->bss_conf.basic_rates);
4909 if (idx)
4910 idx--;
4911
4912 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
4913 rate = mwl8k_rates_24[idx].hw_value;
4914 else
4915 rate = mwl8k_rates_50[idx].hw_value;
4916
4917 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
4918 }
c3cbbe8a 4919 }
a66098da 4920
c3cbbe8a 4921 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB		 4922 rc = mwl8k_set_radio_preamble(hw,
4923 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 4924 if (rc)
4925 goto out;
c3cbbe8a 4926 }
a66098da 4927
dcee7438 4928 if ((changed & BSS_CHANGED_ERP_SLOT) && !priv->ap_fw) {
7dc6a7a7 4929 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 4930 if (rc)
4931 goto out;
c3cbbe8a 4932 }
a66098da 4933
dcee7438 4934 if (vif->bss_conf.assoc && !priv->ap_fw &&
c97470dd
LB		 4935 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
4936 BSS_CHANGED_HT))) {
c3cbbe8a 4937 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB		 4938 if (rc)
4939 goto out;
c3cbbe8a 4940 }
a66098da 4941
c3cbbe8a
LB		 4942 if (vif->bss_conf.assoc &&
4943 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB		 4944 /*
4945 * Finalize the join. Tell rx handler to process
4946 * next beacon from our BSSID.
4947 */
0a11dfc3 4948 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 4949 priv->capture_beacon = true;
a66098da
LB		 4950 }
4951
3a980d0a
LB		 4952out:
4953 mwl8k_fw_unlock(hw);
a66098da
LB		 4954}
4955
b64fe619
LB		 4956static void
4957mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4958 struct ieee80211_bss_conf *info, u32 changed)
4959{
4960 int rc;
4961
4962 if (mwl8k_fw_lock(hw))
4963 return;
4964
4965 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4966 rc = mwl8k_set_radio_preamble(hw,
4967 vif->bss_conf.use_short_preamble);
4968 if (rc)
4969 goto out;
4970 }
4971
4972 if (changed & BSS_CHANGED_BASIC_RATES) {
4973 int idx;
4974 int rate;
4975
4976 /*
4977 * Use lowest supported basic rate for multicasts
4978 * and management frames (such as probe responses --
4979 * beacons will always go out at 1 Mb/s).
4980 */
4981 idx = ffs(vif->bss_conf.basic_rates);
8707d026
LB		 4982 if (idx)
4983 idx--;
4984
4985 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
4986 rate = mwl8k_rates_24[idx].hw_value;
4987 else
4988 rate = mwl8k_rates_50[idx].hw_value;
b64fe619
LB		 4989
4990 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
4991 }
4992
4993 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
4994 struct sk_buff *skb;
4995
4996 skb = ieee80211_beacon_get(hw, vif);
4997 if (skb != NULL) {
aa21d0f6 4998 mwl8k_cmd_set_beacon(hw, vif, skb->data, skb->len);
b64fe619
LB		 4999 kfree_skb(skb);
5000 }
5001 }
5002
5003 if (changed & BSS_CHANGED_BEACON_ENABLED)
aa21d0f6 5004 mwl8k_cmd_bss_start(hw, vif, info->enable_beacon);
b64fe619
LB		 5005
5006out:
5007 mwl8k_fw_unlock(hw);
5008}
5009
5010static void
5011mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5012 struct ieee80211_bss_conf *info, u32 changed)
5013{
41bf9119 5014 if (vif->type == NL80211_IFTYPE_STATION)
b64fe619 5015 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
41bf9119 5016 if (vif->type == NL80211_IFTYPE_AP)
b64fe619
LB		 5017 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
5018}
5019
e81cd2d6 5020static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 5021 struct netdev_hw_addr_list *mc_list)
e81cd2d6
LB		 5022{
5023 struct mwl8k_cmd_pkt *cmd;
5024
447ced07
LB		 5025 /*
5026 * Synthesize and return a command packet that programs the
5027 * hardware multicast address filter. At this point we don't
5028 * know whether FIF_ALLMULTI is being requested, but if it is,
5029 * we'll end up throwing this packet away and creating a new
5030 * one in mwl8k_configure_filter().
5031 */
22bedad3 5032 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_list);
e81cd2d6
LB		 5033
5034 return (unsigned long)cmd;
5035}
5036
a43c49a8
LB		 5037static int
5038mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
5039 unsigned int changed_flags,
5040 unsigned int *total_flags)
5041{
5042 struct mwl8k_priv *priv = hw->priv;
5043
5044 /*
5045 * Hardware sniffer mode is mutually exclusive with STA
5046 * operation, so refuse to enable sniffer mode if a STA
5047 * interface is active.
5048 */
f5bb87cf 5049 if (!list_empty(&priv->vif_list)) {
a43c49a8 5050 if (net_ratelimit())
c96c31e4
JP		 5051 wiphy_info(hw->wiphy,
5052 "not enabling sniffer mode because STA interface is active\n");
a43c49a8
LB		 5053 return 0;
5054 }
5055
5056 if (!priv->sniffer_enabled) {
55489b6e 5057 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 5058 return 0;
5059 priv->sniffer_enabled = true;
5060 }
5061
5062 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
5063 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
5064 FIF_OTHER_BSS;
5065
5066 return 1;
5067}
5068
f5bb87cf
LB		 5069static struct mwl8k_vif *mwl8k_first_vif(struct mwl8k_priv *priv)
5070{
5071 if (!list_empty(&priv->vif_list))
5072 return list_entry(priv->vif_list.next, struct mwl8k_vif, list);
5073
5074 return NULL;
5075}
5076
e6935ea1
LB		 5077static void mwl8k_configure_filter(struct ieee80211_hw *hw,
5078 unsigned int changed_flags,
5079 unsigned int *total_flags,
5080 u64 multicast)
5081{
5082 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 5083 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
5084
c0adae2c
LB		 5085 /*
5086 * AP firmware doesn't allow fine-grained control over
5087 * the receive filter.
5088 */
5089 if (priv->ap_fw) {
5090 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
5091 kfree(cmd);
5092 return;
5093 }
5094
a43c49a8
LB		 5095 /*
5096 * Enable hardware sniffer mode if FIF_CONTROL or
5097 * FIF_OTHER_BSS is requested.
5098 */
5099 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
5100 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
5101 kfree(cmd);
5102 return;
5103 }
a66098da 5104
e6935ea1 5105 /* Clear unsupported feature flags */
447ced07 5106 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 5107
90852f7a
LB		 5108 if (mwl8k_fw_lock(hw)) {
5109 kfree(cmd);
e6935ea1 5110 return;
90852f7a 5111 }
a66098da 5112
a43c49a8 5113 if (priv->sniffer_enabled) {
55489b6e 5114 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 5115 priv->sniffer_enabled = false;
5116 }
5117
e6935ea1 5118 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 5119 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
5120 /*
5121 * Disable the BSS filter.
5122 */
e6935ea1 5123 mwl8k_cmd_set_pre_scan(hw);
77165d88 5124 } else {
f5bb87cf 5125 struct mwl8k_vif *mwl8k_vif;
0a11dfc3 5126 const u8 *bssid;
a94cc97e 5127
77165d88
LB		 5128 /*
5129 * Enable the BSS filter.
5130 *
5131 * If there is an active STA interface, use that
5132 * interface's BSSID, otherwise use a dummy one
5133 * (where the OUI part needs to be nonzero for
5134 * the BSSID to be accepted by POST_SCAN).
5135 */
f5bb87cf
LB		 5136 mwl8k_vif = mwl8k_first_vif(priv);
5137 if (mwl8k_vif != NULL)
5138 bssid = mwl8k_vif->vif->bss_conf.bssid;
5139 else
5140 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 5141
e6935ea1 5142 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 5143 }
5144 }
5145
447ced07
LB		 5146 /*
5147 * If FIF_ALLMULTI is being requested, throw away the command
5148 * packet that ->prepare_multicast() built and replace it with
5149 * a command packet that enables reception of all multicast
5150 * packets.
5151 */
5152 if (*total_flags & FIF_ALLMULTI) {
5153 kfree(cmd);
22bedad3 5154 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, NULL);
447ced07
LB		 5155 }
5156
5157 if (cmd != NULL) {
5158 mwl8k_post_cmd(hw, cmd);
5159 kfree(cmd);
e6935ea1 5160 }
a66098da 5161
e6935ea1 5162 mwl8k_fw_unlock(hw);
a66098da
LB		 5163}
5164
a66098da
LB		 5165static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
5166{
c2c2b12a 5167 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB		 5168}
5169
4a6967b8
JB		 5170static int mwl8k_sta_remove(struct ieee80211_hw *hw,
5171 struct ieee80211_vif *vif,
5172 struct ieee80211_sta *sta)
3f5610ff
LB		 5173{
5174 struct mwl8k_priv *priv = hw->priv;
5175
4a6967b8
JB		 5176 if (priv->ap_fw)
5177 return mwl8k_cmd_set_new_stn_del(hw, vif, sta->addr);
5178 else
5179 return mwl8k_cmd_update_stadb_del(hw, vif, sta->addr);
bbfd9128
LB		 5180}
5181
4a6967b8
JB		 5182static int mwl8k_sta_add(struct ieee80211_hw *hw,
5183 struct ieee80211_vif *vif,
5184 struct ieee80211_sta *sta)
bbfd9128
LB		 5185{
5186 struct mwl8k_priv *priv = hw->priv;
4a6967b8 5187 int ret;
fcdc403c
NS		 5188 int i;
5189 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
5190 struct ieee80211_key_conf *key;
bbfd9128 5191
4a6967b8
JB		 5192 if (!priv->ap_fw) {
5193 ret = mwl8k_cmd_update_stadb_add(hw, vif, sta);
5194 if (ret >= 0) {
5195 MWL8K_STA(sta)->peer_id = ret;
17033543
NS		 5196 if (sta->ht_cap.ht_supported)
5197 MWL8K_STA(sta)->is_ampdu_allowed = true;
fcdc403c 5198 ret = 0;
4a6967b8 5199 }
bbfd9128 5200
d9a07d49
NS		 5201 } else {
5202 ret = mwl8k_cmd_set_new_stn_add(hw, vif, sta);
bbfd9128 5203 }
4a6967b8 5204
d9a07d49
NS		 5205 for (i = 0; i < NUM_WEP_KEYS; i++) {
5206 key = IEEE80211_KEY_CONF(mwl8k_vif->wep_key_conf[i].key);
5207 if (mwl8k_vif->wep_key_conf[i].enabled)
5208 mwl8k_set_key(hw, SET_KEY, vif, sta, key);
5209 }
fcdc403c 5210 return ret;
bbfd9128
LB		 5211}
5212
8a3a3c85
EP		 5213static int mwl8k_conf_tx(struct ieee80211_hw *hw,
5214 struct ieee80211_vif *vif, u16 queue,
a66098da
LB		 5215 const struct ieee80211_tx_queue_params *params)
5216{
3e4f542c 5217 struct mwl8k_priv *priv = hw->priv;
a66098da 5218 int rc;
a66098da 5219
3e4f542c
LB		 5220 rc = mwl8k_fw_lock(hw);
5221 if (!rc) {
e600707b 5222 BUG_ON(queue > MWL8K_TX_WMM_QUEUES - 1);
0863ade8
BC		 5223 memcpy(&priv->wmm_params[queue], params, sizeof(*params));
5224
3e4f542c 5225 if (!priv->wmm_enabled)
55489b6e 5226 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 5227
85c9205c 5228 if (!rc) {
e600707b 5229 int q = MWL8K_TX_WMM_QUEUES - 1 - queue;
85c9205c 5230 rc = mwl8k_cmd_set_edca_params(hw, q,
55489b6e
LB		 5231 params->cw_min,
5232 params->cw_max,
5233 params->aifs,
5234 params->txop);
85c9205c 5235 }
3e4f542c
LB		 5236
5237 mwl8k_fw_unlock(hw);
a66098da 5238 }
3e4f542c 5239
a66098da
LB		 5240 return rc;
5241}
5242
a66098da
LB		 5243static int mwl8k_get_stats(struct ieee80211_hw *hw,
5244 struct ieee80211_low_level_stats *stats)
5245{
55489b6e 5246 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 5247}
5248
0d462bbb
JL		 5249static int mwl8k_get_survey(struct ieee80211_hw *hw, int idx,
5250 struct survey_info *survey)
5251{
5252 struct mwl8k_priv *priv = hw->priv;
5253 struct ieee80211_conf *conf = &hw->conf;
5254
5255 if (idx != 0)
5256 return -ENOENT;
5257
5258 survey->channel = conf->channel;
5259 survey->filled = SURVEY_INFO_NOISE_DBM;
5260 survey->noise = priv->noise;
5261
5262 return 0;
5263}
5264
65f3ddcd
NS		 5265#define MAX_AMPDU_ATTEMPTS 5
5266
a2292d83
LB		 5267static int
5268mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5269 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 5270 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
5271 u8 buf_size)
a2292d83 5272{
65f3ddcd
NS		 5273
5274 int i, rc = 0;
5275 struct mwl8k_priv *priv = hw->priv;
5276 struct mwl8k_ampdu_stream *stream;
07f6dda1 5277 u8 *addr = sta->addr, idx;
fd712f5f 5278 struct mwl8k_sta *sta_info = MWL8K_STA(sta);
65f3ddcd
NS		 5279
5280 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
5281 return -ENOTSUPP;
5282
5283 spin_lock(&priv->stream_lock);
5284 stream = mwl8k_lookup_stream(hw, addr, tid);
5285
a2292d83
LB		 5286 switch (action) {
5287 case IEEE80211_AMPDU_RX_START:
5288 case IEEE80211_AMPDU_RX_STOP:
65f3ddcd
NS		 5289 break;
5290 case IEEE80211_AMPDU_TX_START:
5291 /* By the time we get here the hw queues may contain outgoing
5292 * packets for this RA/TID that are not part of this BA
5293 * session. The hw will assign sequence numbers to these
5294 * packets as they go out. So if we query the hw for its next
5295 * sequence number and use that for the SSN here, it may end up
5296 * being wrong, which will lead to sequence number mismatch at
5297 * the recipient. To avoid this, we reset the sequence number
5298 * to O for the first MPDU in this BA stream.
5299 */
5300 *ssn = 0;
5301 if (stream == NULL) {
5302 /* This means that somebody outside this driver called
5303 * ieee80211_start_tx_ba_session. This is unexpected
5304 * because we do our own rate control. Just warn and
5305 * move on.
5306 */
5307 wiphy_warn(hw->wiphy, "Unexpected call to %s. "
5308 "Proceeding anyway.\n", __func__);
5309 stream = mwl8k_add_stream(hw, sta, tid);
5310 }
5311 if (stream == NULL) {
5312 wiphy_debug(hw->wiphy, "no free AMPDU streams\n");
5313 rc = -EBUSY;
5314 break;
5315 }
5316 stream->state = AMPDU_STREAM_IN_PROGRESS;
5317
5318 /* Release the lock before we do the time consuming stuff */
5319 spin_unlock(&priv->stream_lock);
5320 for (i = 0; i < MAX_AMPDU_ATTEMPTS; i++) {
fd712f5f
YAP		 5321
5322 /* Check if link is still valid */
5323 if (!sta_info->is_ampdu_allowed) {
5324 spin_lock(&priv->stream_lock);
5325 mwl8k_remove_stream(hw, stream);
5326 spin_unlock(&priv->stream_lock);
5327 return -EBUSY;
5328 }
5329
f95275c4 5330 rc = mwl8k_check_ba(hw, stream, vif);
65f3ddcd 5331
6b6accc3
YAP		 5332 /* If HW restart is in progress mwl8k_post_cmd will
5333 * return -EBUSY. Avoid retrying mwl8k_check_ba in
5334 * such cases
5335 */
5336 if (!rc || rc == -EBUSY)
65f3ddcd
NS		 5337 break;
5338 /*
5339 * HW queues take time to be flushed, give them
5340 * sufficient time
5341 */
5342
5343 msleep(1000);
5344 }
5345 spin_lock(&priv->stream_lock);
5346 if (rc) {
5347 wiphy_err(hw->wiphy, "Stream for tid %d busy after %d"
5348 " attempts\n", tid, MAX_AMPDU_ATTEMPTS);
5349 mwl8k_remove_stream(hw, stream);
5350 rc = -EBUSY;
5351 break;
5352 }
5353 ieee80211_start_tx_ba_cb_irqsafe(vif, addr, tid);
5354 break;
18b559d5
JB		 5355 case IEEE80211_AMPDU_TX_STOP_CONT:
5356 case IEEE80211_AMPDU_TX_STOP_FLUSH:
5357 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
eca107ff
YAP		 5358 if (stream) {
5359 if (stream->state == AMPDU_STREAM_ACTIVE) {
07f6dda1 5360 idx = stream->idx;
eca107ff 5361 spin_unlock(&priv->stream_lock);
07f6dda1 5362 mwl8k_destroy_ba(hw, idx);
eca107ff
YAP		 5363 spin_lock(&priv->stream_lock);
5364 }
5365 mwl8k_remove_stream(hw, stream);
65f3ddcd 5366 }
65f3ddcd
NS		 5367 ieee80211_stop_tx_ba_cb_irqsafe(vif, addr, tid);
5368 break;
5369 case IEEE80211_AMPDU_TX_OPERATIONAL:
5370 BUG_ON(stream == NULL);
5371 BUG_ON(stream->state != AMPDU_STREAM_IN_PROGRESS);
5372 spin_unlock(&priv->stream_lock);
f95275c4 5373 rc = mwl8k_create_ba(hw, stream, buf_size, vif);
65f3ddcd
NS		 5374 spin_lock(&priv->stream_lock);
5375 if (!rc)
5376 stream->state = AMPDU_STREAM_ACTIVE;
5377 else {
07f6dda1 5378 idx = stream->idx;
65f3ddcd 5379 spin_unlock(&priv->stream_lock);
07f6dda1 5380 mwl8k_destroy_ba(hw, idx);
65f3ddcd
NS		 5381 spin_lock(&priv->stream_lock);
5382 wiphy_debug(hw->wiphy,
5383 "Failed adding stream for sta %pM tid %d\n",
5384 addr, tid);
5385 mwl8k_remove_stream(hw, stream);
5386 }
5387 break;
5388
a2292d83 5389 default:
65f3ddcd 5390 rc = -ENOTSUPP;
a2292d83 5391 }
65f3ddcd
NS		 5392
5393 spin_unlock(&priv->stream_lock);
5394 return rc;
a2292d83
LB		 5395}
5396
a66098da
LB		 5397static const struct ieee80211_ops mwl8k_ops = {
5398 .tx = mwl8k_tx,
5399 .start = mwl8k_start,
5400 .stop = mwl8k_stop,
5401 .add_interface = mwl8k_add_interface,
5402 .remove_interface = mwl8k_remove_interface,
5403 .config = mwl8k_config,
a66098da 5404 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 5405 .prepare_multicast = mwl8k_prepare_multicast,
a66098da 5406 .configure_filter = mwl8k_configure_filter,
fcdc403c 5407 .set_key = mwl8k_set_key,
a66098da 5408 .set_rts_threshold = mwl8k_set_rts_threshold,
4a6967b8
JB		 5409 .sta_add = mwl8k_sta_add,
5410 .sta_remove = mwl8k_sta_remove,
a66098da 5411 .conf_tx = mwl8k_conf_tx,
a66098da 5412 .get_stats = mwl8k_get_stats,
0d462bbb 5413 .get_survey = mwl8k_get_survey,
a2292d83 5414 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB		 5415};
5416
a66098da
LB		 5417static void mwl8k_finalize_join_worker(struct work_struct *work)
5418{
5419 struct mwl8k_priv *priv =
5420 container_of(work, struct mwl8k_priv, finalize_join_worker);
5421 struct sk_buff *skb = priv->beacon_skb;
56007a02
JB		 5422 struct ieee80211_mgmt *mgmt = (void *)skb->data;
5423 int len = skb->len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
5424 const u8 *tim = cfg80211_find_ie(WLAN_EID_TIM,
5425 mgmt->u.beacon.variable, len);
5426 int dtim_period = 1;
5427
5428 if (tim && tim[1] >= 2)
5429 dtim_period = tim[3];
a66098da 5430
56007a02 5431 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, dtim_period);
a66098da 5432
f5bb87cf 5433 dev_kfree_skb(skb);
a66098da
LB		 5434 priv->beacon_skb = NULL;
5435}
5436
bcb628d5 5437enum {
9e1b17ea
LB		 5438 MWL8363 = 0,
5439 MWL8687,
bcb628d5 5440 MWL8366,
d926dc7d 5441 MWL8764,
6f6d1e9a
LB		 5442};
5443
c2f2e202 5444#define MWL8K_8366_AP_FW_API 3
952a0e96
BC		 5445#define _MWL8K_8366_AP_FW(api) "mwl8k/fmimage_8366_ap-" #api ".fw"
5446#define MWL8K_8366_AP_FW(api) _MWL8K_8366_AP_FW(api)
5447
d926dc7d
NS		 5448#define MWL8K_8764_AP_FW_API 1
5449#define _MWL8K_8764_AP_FW(api) "mwl8k/fmimage_8764_ap-" #api ".fw"
5450#define MWL8K_8764_AP_FW(api) _MWL8K_8764_AP_FW(api)
5451
8dee5eef 5452static struct mwl8k_device_info mwl8k_info_tbl[] = {
9e1b17ea
LB		 5453 [MWL8363] = {
5454 .part_name = "88w8363",
5455 .helper_image = "mwl8k/helper_8363.fw",
0863ade8 5456 .fw_image_sta = "mwl8k/fmimage_8363.fw",
9e1b17ea 5457 },
49eb691c 5458 [MWL8687] = {
bcb628d5
JL		 5459 .part_name = "88w8687",
5460 .helper_image = "mwl8k/helper_8687.fw",
0863ade8 5461 .fw_image_sta = "mwl8k/fmimage_8687.fw",
bcb628d5 5462 },
49eb691c 5463 [MWL8366] = {
bcb628d5
JL		 5464 .part_name = "88w8366",
5465 .helper_image = "mwl8k/helper_8366.fw",
0863ade8 5466 .fw_image_sta = "mwl8k/fmimage_8366.fw",
952a0e96
BC		 5467 .fw_image_ap = MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API),
5468 .fw_api_ap = MWL8K_8366_AP_FW_API,
d926dc7d
NS		 5469 .ap_rxd_ops = &rxd_ap_ops,
5470 },
5471 [MWL8764] = {
5472 .part_name = "88w8764",
5473 .fw_image_ap = MWL8K_8764_AP_FW(MWL8K_8764_AP_FW_API),
5474 .fw_api_ap = MWL8K_8764_AP_FW_API,
5475 .ap_rxd_ops = &rxd_ap_ops,
bcb628d5 5476 },
45a390dd
LB		 5477};
5478
c92d4ede
LB		 5479MODULE_FIRMWARE("mwl8k/helper_8363.fw");
5480MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
5481MODULE_FIRMWARE("mwl8k/helper_8687.fw");
5482MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
5483MODULE_FIRMWARE("mwl8k/helper_8366.fw");
5484MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
952a0e96 5485MODULE_FIRMWARE(MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API));
c92d4ede 5486
45a390dd 5487static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
e5868ba1 5488 { PCI_VDEVICE(MARVELL, 0x2a0a), .driver_data = MWL8363, },
9e1b17ea
LB		 5489 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
5490 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL		 5491 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
5492 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
5493 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
fc5bc165
JG		 5494 { PCI_VDEVICE(MARVELL, 0x2a41), .driver_data = MWL8366, },
5495 { PCI_VDEVICE(MARVELL, 0x2a42), .driver_data = MWL8366, },
ca66527c 5496 { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
d926dc7d 5497 { PCI_VDEVICE(MARVELL, 0x2b36), .driver_data = MWL8764, },
bcb628d5 5498 { },
45a390dd
LB		 5499};
5500MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
5501
99020471
BC		 5502static int mwl8k_request_alt_fw(struct mwl8k_priv *priv)
5503{
5504 int rc;
5505 printk(KERN_ERR "%s: Error requesting preferred fw %s.\n"
5506 "Trying alternative firmware %s\n", pci_name(priv->pdev),
5507 priv->fw_pref, priv->fw_alt);
5508 rc = mwl8k_request_fw(priv, priv->fw_alt, &priv->fw_ucode, true);
5509 if (rc) {
5510 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5511 pci_name(priv->pdev), priv->fw_alt);
5512 return rc;
5513 }
5514 return 0;
5515}
5516
5517static int mwl8k_firmware_load_success(struct mwl8k_priv *priv);
5518static void mwl8k_fw_state_machine(const struct firmware *fw, void *context)
5519{
5520 struct mwl8k_priv *priv = context;
5521 struct mwl8k_device_info *di = priv->device_info;
5522 int rc;
5523
5524 switch (priv->fw_state) {
5525 case FW_STATE_INIT:
5526 if (!fw) {
5527 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
5528 pci_name(priv->pdev), di->helper_image);
5529 goto fail;
5530 }
5531 priv->fw_helper = fw;
5532 rc = mwl8k_request_fw(priv, priv->fw_pref, &priv->fw_ucode,
5533 true);
5534 if (rc && priv->fw_alt) {
5535 rc = mwl8k_request_alt_fw(priv);
5536 if (rc)
5537 goto fail;
5538 priv->fw_state = FW_STATE_LOADING_ALT;
5539 } else if (rc)
5540 goto fail;
5541 else
5542 priv->fw_state = FW_STATE_LOADING_PREF;
5543 break;
5544
5545 case FW_STATE_LOADING_PREF:
5546 if (!fw) {
5547 if (priv->fw_alt) {
5548 rc = mwl8k_request_alt_fw(priv);
5549 if (rc)
5550 goto fail;
5551 priv->fw_state = FW_STATE_LOADING_ALT;
5552 } else
5553 goto fail;
5554 } else {
5555 priv->fw_ucode = fw;
5556 rc = mwl8k_firmware_load_success(priv);
5557 if (rc)
5558 goto fail;
5559 else
5560 complete(&priv->firmware_loading_complete);
5561 }
5562 break;
5563
5564 case FW_STATE_LOADING_ALT:
5565 if (!fw) {
5566 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5567 pci_name(priv->pdev), di->helper_image);
5568 goto fail;
5569 }
5570 priv->fw_ucode = fw;
5571 rc = mwl8k_firmware_load_success(priv);
5572 if (rc)
5573 goto fail;
5574 else
5575 complete(&priv->firmware_loading_complete);
5576 break;
5577
5578 default:
5579 printk(KERN_ERR "%s: Unexpected firmware loading state: %d\n",
5580 MWL8K_NAME, priv->fw_state);
5581 BUG_ON(1);
5582 }
5583
5584 return;
5585
5586fail:
5587 priv->fw_state = FW_STATE_ERROR;
5588 complete(&priv->firmware_loading_complete);
5589 device_release_driver(&priv->pdev->dev);
5590 mwl8k_release_firmware(priv);
5591}
5592
6b6accc3 5593#define MAX_RESTART_ATTEMPTS 1
99020471
BC		 5594static int mwl8k_init_firmware(struct ieee80211_hw *hw, char *fw_image,
5595 bool nowait)
a66098da 5596{
3cc7772c 5597 struct mwl8k_priv *priv = hw->priv;
a66098da 5598 int rc;
6b6accc3 5599 int count = MAX_RESTART_ATTEMPTS;
be695fc4 5600
6b6accc3 5601retry:
be695fc4
LB		 5602 /* Reset firmware and hardware */
5603 mwl8k_hw_reset(priv);
5604
5605 /* Ask userland hotplug daemon for the device firmware */
99020471 5606 rc = mwl8k_request_firmware(priv, fw_image, nowait);
be695fc4 5607 if (rc) {
5db55844 5608 wiphy_err(hw->wiphy, "Firmware files not found\n");
3cc7772c 5609 return rc;
be695fc4
LB		 5610 }
5611
99020471
BC		 5612 if (nowait)
5613 return rc;
5614
be695fc4
LB		 5615 /* Load firmware into hardware */
5616 rc = mwl8k_load_firmware(hw);
3cc7772c 5617 if (rc)
5db55844 5618 wiphy_err(hw->wiphy, "Cannot start firmware\n");
be695fc4
LB		 5619
5620 /* Reclaim memory once firmware is successfully loaded */
5621 mwl8k_release_firmware(priv);
5622
6b6accc3
YAP		 5623 if (rc && count) {
5624 /* FW did not start successfully;
5625 * lets try one more time
5626 */
5627 count--;
5628 wiphy_err(hw->wiphy, "Trying to reload the firmware again\n");
5629 msleep(20);
5630 goto retry;
5631 }
5632
3cc7772c
BC		 5633 return rc;
5634}
5635
73b46320
BC		 5636static int mwl8k_init_txqs(struct ieee80211_hw *hw)
5637{
5638 struct mwl8k_priv *priv = hw->priv;
5639 int rc = 0;
5640 int i;
5641
e600707b 5642 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
73b46320
BC		 5643 rc = mwl8k_txq_init(hw, i);
5644 if (rc)
5645 break;
5646 if (priv->ap_fw)
5647 iowrite32(priv->txq[i].txd_dma,
5648 priv->sram + priv->txq_offset[i]);
5649 }
5650 return rc;
5651}
5652
3cc7772c
BC		 5653/* initialize hw after successfully loading a firmware image */
5654static int mwl8k_probe_hw(struct ieee80211_hw *hw)
5655{
5656 struct mwl8k_priv *priv = hw->priv;
5657 int rc = 0;
5658 int i;
be695fc4 5659
91942230 5660 if (priv->ap_fw) {
89a91f4f 5661 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230 5662 if (priv->rxd_ops == NULL) {
c96c31e4
JP		 5663 wiphy_err(hw->wiphy,
5664 "Driver does not have AP firmware image support for this hardware\n");
a2ca8ecb 5665 rc = -ENOENT;
91942230
LB		 5666 goto err_stop_firmware;
5667 }
5668 } else {
89a91f4f 5669 priv->rxd_ops = &rxd_sta_ops;
91942230 5670 }
be695fc4
LB		 5671
5672 priv->sniffer_enabled = false;
5673 priv->wmm_enabled = false;
5674 priv->pending_tx_pkts = 0;
c27a54d3 5675 atomic_set(&priv->watchdog_event_pending, 0);
be695fc4 5676
a66098da
LB		 5677 rc = mwl8k_rxq_init(hw, 0);
5678 if (rc)
3cc7772c 5679 goto err_stop_firmware;
a66098da
LB		 5680 rxq_refill(hw, 0, INT_MAX);
5681
73b46320
BC		 5682 /* For the sta firmware, we need to know the dma addresses of tx queues
5683 * before sending MWL8K_CMD_GET_HW_SPEC. So we must initialize them
5684 * prior to issuing this command. But for the AP case, we learn the
5685 * total number of queues from the result CMD_GET_HW_SPEC, so for this
5686 * case we must initialize the tx queues after.
5687 */
8a7a578c 5688 priv->num_ampdu_queues = 0;
73b46320
BC		 5689 if (!priv->ap_fw) {
5690 rc = mwl8k_init_txqs(hw);
a66098da
LB		 5691 if (rc)
5692 goto err_free_queues;
5693 }
5694
5695 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 5696 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3aefc37e
NS		 5697 iowrite32(MWL8K_A2H_INT_TX_DONE|MWL8K_A2H_INT_RX_READY|
5698 MWL8K_A2H_INT_BA_WATCHDOG,
1e9f9de3 5699 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
12488e01
NS		 5700 iowrite32(MWL8K_A2H_INT_OPC_DONE,
5701 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
a66098da 5702
a0607fd3 5703 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 5704 IRQF_SHARED, MWL8K_NAME, hw);
5705 if (rc) {
5db55844 5706 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
a66098da
LB		 5707 goto err_free_queues;
5708 }
5709
6b6accc3
YAP		 5710 /*
5711 * When hw restart is requested,
5712 * mac80211 will take care of clearing
5713 * the ampdu streams, so do not clear
5714 * the ampdu state here
5715 */
5716 if (!priv->hw_restart_in_progress)
5717 memset(priv->ampdu, 0, sizeof(priv->ampdu));
ac109fd0 5718
a66098da
LB		 5719 /*
5720 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 5721 * commands use interrupts and avoid polling. Disable
a66098da
LB		 5722 * interrupts when done.
5723 */
c23b5a69 5724 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5725
5726 /* Get config data, mac addrs etc */
42fba21d
LB		 5727 if (priv->ap_fw) {
5728 rc = mwl8k_cmd_get_hw_spec_ap(hw);
73b46320
BC		 5729 if (!rc)
5730 rc = mwl8k_init_txqs(hw);
42fba21d
LB		 5731 if (!rc)
5732 rc = mwl8k_cmd_set_hw_spec(hw);
5733 } else {
5734 rc = mwl8k_cmd_get_hw_spec_sta(hw);
5735 }
a66098da 5736 if (rc) {
5db55844 5737 wiphy_err(hw->wiphy, "Cannot initialise firmware\n");
be695fc4 5738 goto err_free_irq;
a66098da
LB		 5739 }
5740
5741 /* Turn radio off */
55489b6e 5742 rc = mwl8k_cmd_radio_disable(hw);
a66098da 5743 if (rc) {
5db55844 5744 wiphy_err(hw->wiphy, "Cannot disable\n");
be695fc4 5745 goto err_free_irq;
a66098da
LB		 5746 }
5747
32060e1b 5748 /* Clear MAC address */
aa21d0f6 5749 rc = mwl8k_cmd_set_mac_addr(hw, NULL, "\x00\x00\x00\x00\x00\x00");
32060e1b 5750 if (rc) {
5db55844 5751 wiphy_err(hw->wiphy, "Cannot clear MAC address\n");
be695fc4 5752 goto err_free_irq;
32060e1b
LB		 5753 }
5754
a246ac38
YAP		 5755 /* Configure Antennas */
5756 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x3);
5757 if (rc)
5758 wiphy_warn(hw->wiphy, "failed to set # of RX antennas");
5759 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
5760 if (rc)
5761 wiphy_warn(hw->wiphy, "failed to set # of TX antennas");
5762
5763
a66098da 5764 /* Disable interrupts */
a66098da 5765 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5766 free_irq(priv->pdev->irq, hw);
5767
c96c31e4
JP		 5768 wiphy_info(hw->wiphy, "%s v%d, %pm, %s firmware %u.%u.%u.%u\n",
5769 priv->device_info->part_name,
5770 priv->hw_rev, hw->wiphy->perm_addr,
5771 priv->ap_fw ? "AP" : "STA",
5772 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
5773 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 5774
5775 return 0;
5776
a66098da 5777err_free_irq:
a66098da 5778 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5779 free_irq(priv->pdev->irq, hw);
5780
5781err_free_queues:
e600707b 5782 for (i = 0; i < mwl8k_tx_queues(priv); i++)
a66098da
LB		 5783 mwl8k_txq_deinit(hw, i);
5784 mwl8k_rxq_deinit(hw, 0);
5785
3cc7772c
BC		 5786err_stop_firmware:
5787 mwl8k_hw_reset(priv);
5788
5789 return rc;
5790}
5791
5792/*
5793 * invoke mwl8k_reload_firmware to change the firmware image after the device
5794 * has already been registered
5795 */
5796static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image)
5797{
5798 int i, rc = 0;
5799 struct mwl8k_priv *priv = hw->priv;
6b6accc3 5800 struct mwl8k_vif *vif, *tmp_vif;
3cc7772c
BC		 5801
5802 mwl8k_stop(hw);
5803 mwl8k_rxq_deinit(hw, 0);
5804
6b6accc3
YAP		 5805 /*
5806 * All the existing interfaces are re-added by the ieee80211_reconfig;
5807 * which means driver should remove existing interfaces before calling
5808 * ieee80211_restart_hw
5809 */
5810 if (priv->hw_restart_in_progress)
5811 list_for_each_entry_safe(vif, tmp_vif, &priv->vif_list, list)
5812 mwl8k_remove_vif(priv, vif);
5813
e600707b 5814 for (i = 0; i < mwl8k_tx_queues(priv); i++)
3cc7772c
BC		 5815 mwl8k_txq_deinit(hw, i);
5816
99020471 5817 rc = mwl8k_init_firmware(hw, fw_image, false);
3cc7772c
BC		 5818 if (rc)
5819 goto fail;
5820
5821 rc = mwl8k_probe_hw(hw);
5822 if (rc)
5823 goto fail;
5824
6b6accc3
YAP		 5825 if (priv->hw_restart_in_progress)
5826 return rc;
5827
3cc7772c
BC		 5828 rc = mwl8k_start(hw);
5829 if (rc)
5830 goto fail;
5831
5832 rc = mwl8k_config(hw, ~0);
5833 if (rc)
5834 goto fail;
5835
e600707b 5836 for (i = 0; i < MWL8K_TX_WMM_QUEUES; i++) {
8a3a3c85 5837 rc = mwl8k_conf_tx(hw, NULL, i, &priv->wmm_params[i]);
3cc7772c
BC		 5838 if (rc)
5839 goto fail;
5840 }
5841
5842 return rc;
5843
5844fail:
5845 printk(KERN_WARNING "mwl8k: Failed to reload firmware image.\n");
5846 return rc;
5847}
5848
5d377fca
YAP		 5849static const struct ieee80211_iface_limit ap_if_limits[] = {
5850 { .max = 8, .types = BIT(NL80211_IFTYPE_AP) },
2acdaa7a 5851 { .max = 1, .types = BIT(NL80211_IFTYPE_STATION) },
5d377fca
YAP		 5852};
5853
5854static const struct ieee80211_iface_combination ap_if_comb = {
5855 .limits = ap_if_limits,
5856 .n_limits = ARRAY_SIZE(ap_if_limits),
5857 .max_interfaces = 8,
5858 .num_different_channels = 1,
5859};
5860
5861
3cc7772c
BC		 5862static int mwl8k_firmware_load_success(struct mwl8k_priv *priv)
5863{
5864 struct ieee80211_hw *hw = priv->hw;
5865 int i, rc;
5866
99020471
BC		 5867 rc = mwl8k_load_firmware(hw);
5868 mwl8k_release_firmware(priv);
5869 if (rc) {
5870 wiphy_err(hw->wiphy, "Cannot start firmware\n");
5871 return rc;
5872 }
5873
3cc7772c
BC		 5874 /*
5875 * Extra headroom is the size of the required DMA header
5876 * minus the size of the smallest 802.11 frame (CTS frame).
5877 */
5878 hw->extra_tx_headroom =
5879 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
5880
ff776cec
YAP		 5881 hw->extra_tx_headroom -= priv->ap_fw ? REDUCED_TX_HEADROOM : 0;
5882
3cc7772c
BC		 5883 hw->channel_change_time = 10;
5884
e600707b 5885 hw->queues = MWL8K_TX_WMM_QUEUES;
3cc7772c
BC		 5886
5887 /* Set rssi values to dBm */
0bf22c37 5888 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_HAS_RATE_CONTROL;
2a36a0ec
YAP		 5889
5890 /*
5891 * Ask mac80211 to not to trigger PS mode
5892 * based on PM bit of incoming frames.
5893 */
5894 if (priv->ap_fw)
5895 hw->flags |= IEEE80211_HW_AP_LINK_PS;
5896
3cc7772c
BC		 5897 hw->vif_data_size = sizeof(struct mwl8k_vif);
5898 hw->sta_data_size = sizeof(struct mwl8k_sta);
5899
5900 priv->macids_used = 0;
5901 INIT_LIST_HEAD(&priv->vif_list);
5902
5903 /* Set default radio state and preamble */
3db1cd5c
RR		 5904 priv->radio_on = false;
5905 priv->radio_short_preamble = false;
3cc7772c
BC		 5906
5907 /* Finalize join worker */
5908 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3aefc37e
NS		 5909 /* Handle watchdog ba events */
5910 INIT_WORK(&priv->watchdog_ba_handle, mwl8k_watchdog_ba_events);
6b6accc3
YAP		 5911 /* To reload the firmware if it crashes */
5912 INIT_WORK(&priv->fw_reload, mwl8k_hw_restart_work);
3cc7772c
BC		 5913
5914 /* TX reclaim and RX tasklets. */
5915 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
5916 tasklet_disable(&priv->poll_tx_task);
5917 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
5918 tasklet_disable(&priv->poll_rx_task);
5919
5920 /* Power management cookie */
5921 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
5922 if (priv->cookie == NULL)
5923 return -ENOMEM;
5924
5925 mutex_init(&priv->fw_mutex);
5926 priv->fw_mutex_owner = NULL;
5927 priv->fw_mutex_depth = 0;
5928 priv->hostcmd_wait = NULL;
5929
5930 spin_lock_init(&priv->tx_lock);
5931
ac109fd0
BC		 5932 spin_lock_init(&priv->stream_lock);
5933
3cc7772c
BC		 5934 priv->tx_wait = NULL;
5935
5936 rc = mwl8k_probe_hw(hw);
5937 if (rc)
5938 goto err_free_cookie;
5939
5940 hw->wiphy->interface_modes = 0;
5d377fca
YAP		 5941
5942 if (priv->ap_macids_supported || priv->device_info->fw_image_ap) {
3cc7772c 5943 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
2acdaa7a 5944 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
5d377fca
YAP		 5945 hw->wiphy->iface_combinations = &ap_if_comb;
5946 hw->wiphy->n_iface_combinations = 1;
5947 }
5948
3cc7772c
BC		 5949 if (priv->sta_macids_supported || priv->device_info->fw_image_sta)
5950 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
5951
5952 rc = ieee80211_register_hw(hw);
5953 if (rc) {
5954 wiphy_err(hw->wiphy, "Cannot register device\n");
5955 goto err_unprobe_hw;
5956 }
5957
5958 return 0;
5959
5960err_unprobe_hw:
e600707b 5961 for (i = 0; i < mwl8k_tx_queues(priv); i++)
3cc7772c
BC		 5962 mwl8k_txq_deinit(hw, i);
5963 mwl8k_rxq_deinit(hw, 0);
5964
be695fc4 5965err_free_cookie:
a66098da
LB		 5966 if (priv->cookie != NULL)
5967 pci_free_consistent(priv->pdev, 4,
5968 priv->cookie, priv->cookie_dma);
5969
3cc7772c
BC		 5970 return rc;
5971}
8dee5eef 5972static int mwl8k_probe(struct pci_dev *pdev,
3cc7772c
BC		 5973 const struct pci_device_id *id)
5974{
5975 static int printed_version;
5976 struct ieee80211_hw *hw;
5977 struct mwl8k_priv *priv;
0863ade8 5978 struct mwl8k_device_info *di;
3cc7772c
BC		 5979 int rc;
5980
5981 if (!printed_version) {
5982 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
5983 printed_version = 1;
5984 }
5985
5986
5987 rc = pci_enable_device(pdev);
5988 if (rc) {
5989 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
5990 MWL8K_NAME);
5991 return rc;
5992 }
5993
5994 rc = pci_request_regions(pdev, MWL8K_NAME);
5995 if (rc) {
5996 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
5997 MWL8K_NAME);
5998 goto err_disable_device;
5999 }
6000
6001 pci_set_master(pdev);
6002
6003
6004 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
6005 if (hw == NULL) {
6006 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
6007 rc = -ENOMEM;
6008 goto err_free_reg;
6009 }
6010
6011 SET_IEEE80211_DEV(hw, &pdev->dev);
6012 pci_set_drvdata(pdev, hw);
6013
6014 priv = hw->priv;
6015 priv->hw = hw;
6016 priv->pdev = pdev;
6017 priv->device_info = &mwl8k_info_tbl[id->driver_data];
6018
98929824
NS		 6019 if (id->driver_data == MWL8764)
6020 priv->is_8764 = true;
3cc7772c
BC		 6021
6022 priv->sram = pci_iomap(pdev, 0, 0x10000);
6023 if (priv->sram == NULL) {
6024 wiphy_err(hw->wiphy, "Cannot map device SRAM\n");
a2ca8ecb 6025 rc = -EIO;
3cc7772c
BC		 6026 goto err_iounmap;
6027 }
6028
6029 /*
6030 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
6031 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
6032 */
6033 priv->regs = pci_iomap(pdev, 1, 0x10000);
6034 if (priv->regs == NULL) {
6035 priv->regs = pci_iomap(pdev, 2, 0x10000);
6036 if (priv->regs == NULL) {
6037 wiphy_err(hw->wiphy, "Cannot map device registers\n");
a2ca8ecb 6038 rc = -EIO;
3cc7772c
BC		 6039 goto err_iounmap;
6040 }
6041 }
6042
0863ade8 6043 /*
99020471
BC		 6044 * Choose the initial fw image depending on user input. If a second
6045 * image is available, make it the alternative image that will be
6046 * loaded if the first one fails.
0863ade8 6047 */
99020471 6048 init_completion(&priv->firmware_loading_complete);
0863ade8 6049 di = priv->device_info;
99020471
BC		 6050 if (ap_mode_default && di->fw_image_ap) {
6051 priv->fw_pref = di->fw_image_ap;
6052 priv->fw_alt = di->fw_image_sta;
6053 } else if (!ap_mode_default && di->fw_image_sta) {
6054 priv->fw_pref = di->fw_image_sta;
6055 priv->fw_alt = di->fw_image_ap;
6056 } else if (ap_mode_default && !di->fw_image_ap && di->fw_image_sta) {
0863ade8 6057 printk(KERN_WARNING "AP fw is unavailable. Using STA fw.");
99020471 6058 priv->fw_pref = di->fw_image_sta;
0863ade8
BC		 6059 } else if (!ap_mode_default && !di->fw_image_sta && di->fw_image_ap) {
6060 printk(KERN_WARNING "STA fw is unavailable. Using AP fw.");
99020471
BC		 6061 priv->fw_pref = di->fw_image_ap;
6062 }
6063 rc = mwl8k_init_firmware(hw, priv->fw_pref, true);
3cc7772c
BC		 6064 if (rc)
6065 goto err_stop_firmware;
6b6accc3
YAP		 6066
6067 priv->hw_restart_in_progress = false;
6068
e882efc9
YAP		 6069 priv->running_bsses = 0;
6070
99020471 6071 return rc;
3cc7772c 6072
be695fc4
LB		 6073err_stop_firmware:
6074 mwl8k_hw_reset(priv);
be695fc4
LB		 6075
6076err_iounmap:
a66098da
LB		 6077 if (priv->regs != NULL)
6078 pci_iounmap(pdev, priv->regs);
6079
5b9482dd
LB		 6080 if (priv->sram != NULL)
6081 pci_iounmap(pdev, priv->sram);
6082
a66098da
LB		 6083 pci_set_drvdata(pdev, NULL);
6084 ieee80211_free_hw(hw);
6085
6086err_free_reg:
6087 pci_release_regions(pdev);
3db95e50
LB		 6088
6089err_disable_device:
a66098da
LB		 6090 pci_disable_device(pdev);
6091
6092 return rc;
6093}
6094
8dee5eef 6095static void mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 6096{
6097 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
6098 struct mwl8k_priv *priv;
6099 int i;
6100
6101 if (hw == NULL)
6102 return;
6103 priv = hw->priv;
6104
99020471
BC		 6105 wait_for_completion(&priv->firmware_loading_complete);
6106
6107 if (priv->fw_state == FW_STATE_ERROR) {
6108 mwl8k_hw_reset(priv);
6109 goto unmap;
6110 }
6111
a66098da
LB		 6112 ieee80211_stop_queues(hw);
6113
60aa569f
LB		 6114 ieee80211_unregister_hw(hw);
6115
67e2eb27 6116 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 6117 tasklet_kill(&priv->poll_tx_task);
67e2eb27 6118 tasklet_kill(&priv->poll_rx_task);
a66098da 6119
a66098da
LB		 6120 /* Stop hardware */
6121 mwl8k_hw_reset(priv);
6122
6123 /* Return all skbs to mac80211 */
e600707b 6124 for (i = 0; i < mwl8k_tx_queues(priv); i++)
efb7c49a 6125 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 6126
e600707b 6127 for (i = 0; i < mwl8k_tx_queues(priv); i++)
a66098da
LB		 6128 mwl8k_txq_deinit(hw, i);
6129
6130 mwl8k_rxq_deinit(hw, 0);
6131
c2c357ce 6132 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da 6133
99020471 6134unmap:
a66098da 6135 pci_iounmap(pdev, priv->regs);
5b9482dd 6136 pci_iounmap(pdev, priv->sram);
a66098da
LB		 6137 pci_set_drvdata(pdev, NULL);
6138 ieee80211_free_hw(hw);
6139 pci_release_regions(pdev);
6140 pci_disable_device(pdev);
6141}
6142
6143static struct pci_driver mwl8k_driver = {
6144 .name = MWL8K_NAME,
45a390dd 6145 .id_table = mwl8k_pci_id_table,
a66098da 6146 .probe = mwl8k_probe,
8dee5eef 6147 .remove = mwl8k_remove,
a66098da
LB		 6148};
6149
5b0a3b7e 6150module_pci_driver(mwl8k_driver);
c2c357ce
LB		 6151
6152MODULE_DESCRIPTION(MWL8K_DESC);
6153MODULE_VERSION(MWL8K_VERSION);
6154MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
6155MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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