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mac80211: track receiver's aggregation reorder buffer size
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a5fb297d 5 * Copyright (C) 2008, 2009, 2010 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
5a0e3ad6 22#include <linux/slab.h>
a66098da
LB		 23#include <net/mac80211.h>
24#include <linux/moduleparam.h>
25#include <linux/firmware.h>
26#include <linux/workqueue.h>
27
28#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
29#define MWL8K_NAME KBUILD_MODNAME
a5fb297d 30#define MWL8K_VERSION "0.12"
a66098da 31
0863ade8
BC		 32/* Module parameters */
33static unsigned ap_mode_default;
34module_param(ap_mode_default, bool, 0);
35MODULE_PARM_DESC(ap_mode_default,
36 "Set to 1 to make ap mode the default instead of sta mode");
37
a66098da
LB		 38/* Register definitions */
39#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 40#define MWL8K_MODE_STA 0x0000005a
41#define MWL8K_MODE_AP 0x000000a5
a66098da 42#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 43#define MWL8K_FWSTA_READY 0xf0f1f2f4
44#define MWL8K_FWAP_READY 0xf1f2f4a5
45#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 46#define MWL8K_HIU_SCRATCH 0x00000c40
47
48/* Host->device communications */
49#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
50#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
51#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
52#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
53#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 54#define MWL8K_H2A_INT_DUMMY (1 << 20)
55#define MWL8K_H2A_INT_RESET (1 << 15)
56#define MWL8K_H2A_INT_DOORBELL (1 << 1)
57#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 58
59/* Device->host communications */
60#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
61#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
62#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
63#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
64#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 65#define MWL8K_A2H_INT_DUMMY (1 << 20)
66#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
67#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
68#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
69#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
70#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
71#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
72#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
73#define MWL8K_A2H_INT_RX_READY (1 << 1)
74#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 75
76#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
77 MWL8K_A2H_INT_CHNL_SWITCHED | \
78 MWL8K_A2H_INT_QUEUE_EMPTY | \
79 MWL8K_A2H_INT_RADAR_DETECT | \
80 MWL8K_A2H_INT_RADIO_ON | \
81 MWL8K_A2H_INT_RADIO_OFF | \
82 MWL8K_A2H_INT_MAC_EVENT | \
83 MWL8K_A2H_INT_OPC_DONE | \
84 MWL8K_A2H_INT_RX_READY | \
85 MWL8K_A2H_INT_TX_DONE)
86
a66098da
LB		 87#define MWL8K_RX_QUEUES 1
88#define MWL8K_TX_QUEUES 4
89
54bc3a0d
LB		 90struct rxd_ops {
91 int rxd_size;
92 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
93 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d 94 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
0d462bbb 95 __le16 *qos, s8 *noise);
54bc3a0d
LB		 96};
97
45a390dd 98struct mwl8k_device_info {
a74b295e
LB		 99 char *part_name;
100 char *helper_image;
0863ade8
BC		 101 char *fw_image_sta;
102 char *fw_image_ap;
89a91f4f 103 struct rxd_ops *ap_rxd_ops;
952a0e96 104 u32 fw_api_ap;
45a390dd
LB		 105};
106
a66098da 107struct mwl8k_rx_queue {
45eb400d 108 int rxd_count;
a66098da
LB		 109
110 /* hw receives here */
45eb400d 111 int head;
a66098da
LB		 112
113 /* refill descs here */
45eb400d 114 int tail;
a66098da 115
54bc3a0d 116 void *rxd;
45eb400d 117 dma_addr_t rxd_dma;
788838eb
LB		 118 struct {
119 struct sk_buff *skb;
53b1b3e1 120 DEFINE_DMA_UNMAP_ADDR(dma);
788838eb 121 } *buf;
a66098da
LB		 122};
123
a66098da
LB		 124struct mwl8k_tx_queue {
125 /* hw transmits here */
45eb400d 126 int head;
a66098da
LB		 127
128 /* sw appends here */
45eb400d 129 int tail;
a66098da 130
8ccbc3b8 131 unsigned int len;
45eb400d
LB		 132 struct mwl8k_tx_desc *txd;
133 dma_addr_t txd_dma;
134 struct sk_buff **skb;
a66098da
LB		 135};
136
a66098da 137struct mwl8k_priv {
a66098da 138 struct ieee80211_hw *hw;
a66098da 139 struct pci_dev *pdev;
a66098da 140
45a390dd
LB		 141 struct mwl8k_device_info *device_info;
142
be695fc4
LB		 143 void __iomem *sram;
144 void __iomem *regs;
145
146 /* firmware */
d1f9e41d
BC		 147 const struct firmware *fw_helper;
148 const struct firmware *fw_ucode;
a66098da 149
be695fc4
LB		 150 /* hardware/firmware parameters */
151 bool ap_fw;
152 struct rxd_ops *rxd_ops;
777ad375
LB		 153 struct ieee80211_supported_band band_24;
154 struct ieee80211_channel channels_24[14];
155 struct ieee80211_rate rates_24[14];
4eae9edd
LB		 156 struct ieee80211_supported_band band_50;
157 struct ieee80211_channel channels_50[4];
158 struct ieee80211_rate rates_50[9];
ee0ddf18
LB		 159 u32 ap_macids_supported;
160 u32 sta_macids_supported;
be695fc4 161
618952a7
LB		 162 /* firmware access */
163 struct mutex fw_mutex;
164 struct task_struct *fw_mutex_owner;
165 int fw_mutex_depth;
618952a7
LB		 166 struct completion *hostcmd_wait;
167
a66098da
LB		 168 /* lock held over TX and TX reap */
169 spinlock_t tx_lock;
a66098da 170
88de754a
LB		 171 /* TX quiesce completion, protected by fw_mutex and tx_lock */
172 struct completion *tx_wait;
173
f5bb87cf 174 /* List of interfaces. */
ee0ddf18 175 u32 macids_used;
f5bb87cf 176 struct list_head vif_list;
a66098da 177
a66098da
LB		 178 /* power management status cookie from firmware */
179 u32 *cookie;
180 dma_addr_t cookie_dma;
181
182 u16 num_mcaddrs;
a66098da 183 u8 hw_rev;
2aa7b01f 184 u32 fw_rev;
a66098da
LB		 185
186 /*
187 * Running count of TX packets in flight, to avoid
188 * iterating over the transmit rings each time.
189 */
190 int pending_tx_pkts;
191
192 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
193 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
194
c46563b7 195 bool radio_on;
68ce3884 196 bool radio_short_preamble;
a43c49a8 197 bool sniffer_enabled;
0439b1f5 198 bool wmm_enabled;
a66098da 199
a66098da
LB		 200 /* XXX need to convert this to handle multiple interfaces */
201 bool capture_beacon;
d89173f2 202 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 203 struct sk_buff *beacon_skb;
204
205 /*
206 * This FJ worker has to be global as it is scheduled from the
207 * RX handler. At this point we don't know which interface it
208 * belongs to until the list of bssids waiting to complete join
209 * is checked.
210 */
211 struct work_struct finalize_join_worker;
212
1e9f9de3
LB		 213 /* Tasklet to perform TX reclaim. */
214 struct tasklet_struct poll_tx_task;
67e2eb27
LB		 215
216 /* Tasklet to perform RX. */
217 struct tasklet_struct poll_rx_task;
0d462bbb
JL		 218
219 /* Most recently reported noise in dBm */
220 s8 noise;
0863ade8
BC		 221
222 /*
223 * preserve the queue configurations so they can be restored if/when
224 * the firmware image is swapped.
225 */
226 struct ieee80211_tx_queue_params wmm_params[MWL8K_TX_QUEUES];
99020471
BC		 227
228 /* async firmware loading state */
229 unsigned fw_state;
230 char *fw_pref;
231 char *fw_alt;
232 struct completion firmware_loading_complete;
a66098da
LB		 233};
234
e53d9b96
NS		 235#define MAX_WEP_KEY_LEN 13
236#define NUM_WEP_KEYS 4
237
a66098da
LB		 238/* Per interface specific private data */
239struct mwl8k_vif {
f5bb87cf
LB		 240 struct list_head list;
241 struct ieee80211_vif *vif;
242
f57ca9c1
LB		 243 /* Firmware macid for this vif. */
244 int macid;
245
c2c2b12a 246 /* Non AMPDU sequence number assigned by driver. */
a680400e 247 u16 seqno;
e53d9b96
NS		 248
249 /* Saved WEP keys */
250 struct {
251 u8 enabled;
252 u8 key[sizeof(struct ieee80211_key_conf) + MAX_WEP_KEY_LEN];
253 } wep_key_conf[NUM_WEP_KEYS];
d9a07d49
NS		 254
255 /* BSSID */
256 u8 bssid[ETH_ALEN];
257
258 /* A flag to indicate is HW crypto is enabled for this bssid */
259 bool is_hw_crypto_enabled;
a66098da 260};
a94cc97e 261#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
fcdc403c 262#define IEEE80211_KEY_CONF(_u8) ((struct ieee80211_key_conf *)(_u8))
a66098da 263
a680400e
LB		 264struct mwl8k_sta {
265 /* Index into station database. Returned by UPDATE_STADB. */
266 u8 peer_id;
267};
268#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
269
777ad375 270static const struct ieee80211_channel mwl8k_channels_24[] = {
a66098da
LB		 271 { .center_freq = 2412, .hw_value = 1, },
272 { .center_freq = 2417, .hw_value = 2, },
273 { .center_freq = 2422, .hw_value = 3, },
274 { .center_freq = 2427, .hw_value = 4, },
275 { .center_freq = 2432, .hw_value = 5, },
276 { .center_freq = 2437, .hw_value = 6, },
277 { .center_freq = 2442, .hw_value = 7, },
278 { .center_freq = 2447, .hw_value = 8, },
279 { .center_freq = 2452, .hw_value = 9, },
280 { .center_freq = 2457, .hw_value = 10, },
281 { .center_freq = 2462, .hw_value = 11, },
647ca6b0
LB		 282 { .center_freq = 2467, .hw_value = 12, },
283 { .center_freq = 2472, .hw_value = 13, },
284 { .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 285};
286
777ad375 287static const struct ieee80211_rate mwl8k_rates_24[] = {
a66098da
LB		 288 { .bitrate = 10, .hw_value = 2, },
289 { .bitrate = 20, .hw_value = 4, },
290 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 291 { .bitrate = 110, .hw_value = 22, },
292 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 293 { .bitrate = 60, .hw_value = 12, },
294 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 295 { .bitrate = 120, .hw_value = 24, },
296 { .bitrate = 180, .hw_value = 36, },
297 { .bitrate = 240, .hw_value = 48, },
298 { .bitrate = 360, .hw_value = 72, },
299 { .bitrate = 480, .hw_value = 96, },
300 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 301 { .bitrate = 720, .hw_value = 144, },
302};
303
4eae9edd
LB		 304static const struct ieee80211_channel mwl8k_channels_50[] = {
305 { .center_freq = 5180, .hw_value = 36, },
306 { .center_freq = 5200, .hw_value = 40, },
307 { .center_freq = 5220, .hw_value = 44, },
308 { .center_freq = 5240, .hw_value = 48, },
309};
310
311static const struct ieee80211_rate mwl8k_rates_50[] = {
312 { .bitrate = 60, .hw_value = 12, },
313 { .bitrate = 90, .hw_value = 18, },
314 { .bitrate = 120, .hw_value = 24, },
315 { .bitrate = 180, .hw_value = 36, },
316 { .bitrate = 240, .hw_value = 48, },
317 { .bitrate = 360, .hw_value = 72, },
318 { .bitrate = 480, .hw_value = 96, },
319 { .bitrate = 540, .hw_value = 108, },
320 { .bitrate = 720, .hw_value = 144, },
321};
322
a66098da 323/* Set or get info from Firmware */
a66098da 324#define MWL8K_CMD_GET 0x0000
41fdf097
NS		 325#define MWL8K_CMD_SET 0x0001
326#define MWL8K_CMD_SET_LIST 0x0002
a66098da
LB		 327
328/* Firmware command codes */
329#define MWL8K_CMD_CODE_DNLD 0x0001
330#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 331#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 332#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
333#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 334#define MWL8K_CMD_RADIO_CONTROL 0x001c
335#define MWL8K_CMD_RF_TX_POWER 0x001e
41fdf097 336#define MWL8K_CMD_TX_POWER 0x001f
08b06347 337#define MWL8K_CMD_RF_ANTENNA 0x0020
aa21d0f6 338#define MWL8K_CMD_SET_BEACON 0x0100 /* per-vif */
a66098da
LB		 339#define MWL8K_CMD_SET_PRE_SCAN 0x0107
340#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 341#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
342#define MWL8K_CMD_SET_AID 0x010d
343#define MWL8K_CMD_SET_RATE 0x0110
344#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
345#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 346#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 347#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
348#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 349#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 350#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 351#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
aa21d0f6 352#define MWL8K_CMD_SET_MAC_ADDR 0x0202 /* per-vif */
a66098da 353#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
aa21d0f6
LB		 354#define MWL8K_CMD_BSS_START 0x1100 /* per-vif */
355#define MWL8K_CMD_SET_NEW_STN 0x1111 /* per-vif */
fcdc403c 356#define MWL8K_CMD_UPDATE_ENCRYPTION 0x1122 /* per-vif */
ff45fc60 357#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da 358
b603742f 359static const char *mwl8k_cmd_name(__le16 cmd, char *buf, int bufsize)
a66098da 360{
b603742f
JL		 361 u16 command = le16_to_cpu(cmd);
362
a66098da
LB		 363#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
364 snprintf(buf, bufsize, "%s", #x);\
365 return buf;\
366 } while (0)
b603742f 367 switch (command & ~0x8000) {
a66098da
LB		 368 MWL8K_CMDNAME(CODE_DNLD);
369 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 370 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 371 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
372 MWL8K_CMDNAME(GET_STAT);
373 MWL8K_CMDNAME(RADIO_CONTROL);
374 MWL8K_CMDNAME(RF_TX_POWER);
41fdf097 375 MWL8K_CMDNAME(TX_POWER);
08b06347 376 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 377 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB		 378 MWL8K_CMDNAME(SET_PRE_SCAN);
379 MWL8K_CMDNAME(SET_POST_SCAN);
380 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 381 MWL8K_CMDNAME(SET_AID);
382 MWL8K_CMDNAME(SET_RATE);
383 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
384 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 385 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 386 MWL8K_CMDNAME(SET_EDCA_PARAMS);
387 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 388 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 389 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 390 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 391 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 392 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 393 MWL8K_CMDNAME(BSS_START);
3f5610ff 394 MWL8K_CMDNAME(SET_NEW_STN);
fcdc403c 395 MWL8K_CMDNAME(UPDATE_ENCRYPTION);
ff45fc60 396 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 397 default:
398 snprintf(buf, bufsize, "0x%x", cmd);
399 }
400#undef MWL8K_CMDNAME
401
402 return buf;
403}
404
405/* Hardware and firmware reset */
406static void mwl8k_hw_reset(struct mwl8k_priv *priv)
407{
408 iowrite32(MWL8K_H2A_INT_RESET,
409 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
410 iowrite32(MWL8K_H2A_INT_RESET,
411 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
412 msleep(20);
413}
414
415/* Release fw image */
d1f9e41d 416static void mwl8k_release_fw(const struct firmware **fw)
a66098da
LB		 417{
418 if (*fw == NULL)
419 return;
420 release_firmware(*fw);
421 *fw = NULL;
422}
423
424static void mwl8k_release_firmware(struct mwl8k_priv *priv)
425{
22be40d9
LB		 426 mwl8k_release_fw(&priv->fw_ucode);
427 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 428}
429
99020471
BC		 430/* states for asynchronous f/w loading */
431static void mwl8k_fw_state_machine(const struct firmware *fw, void *context);
432enum {
433 FW_STATE_INIT = 0,
434 FW_STATE_LOADING_PREF,
435 FW_STATE_LOADING_ALT,
436 FW_STATE_ERROR,
437};
438
a66098da
LB		 439/* Request fw image */
440static int mwl8k_request_fw(struct mwl8k_priv *priv,
d1f9e41d 441 const char *fname, const struct firmware **fw,
99020471 442 bool nowait)
a66098da
LB		 443{
444 /* release current image */
445 if (*fw != NULL)
446 mwl8k_release_fw(fw);
447
99020471
BC		 448 if (nowait)
449 return request_firmware_nowait(THIS_MODULE, 1, fname,
450 &priv->pdev->dev, GFP_KERNEL,
451 priv, mwl8k_fw_state_machine);
452 else
d1f9e41d 453 return request_firmware(fw, fname, &priv->pdev->dev);
a66098da
LB		 454}
455
99020471
BC		 456static int mwl8k_request_firmware(struct mwl8k_priv *priv, char *fw_image,
457 bool nowait)
a66098da 458{
a74b295e 459 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 460 int rc;
461
a74b295e 462 if (di->helper_image != NULL) {
99020471
BC		 463 if (nowait)
464 rc = mwl8k_request_fw(priv, di->helper_image,
465 &priv->fw_helper, true);
466 else
467 rc = mwl8k_request_fw(priv, di->helper_image,
468 &priv->fw_helper, false);
469 if (rc)
470 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
471 pci_name(priv->pdev), di->helper_image);
472
473 if (rc || nowait)
a74b295e 474 return rc;
a66098da
LB		 475 }
476
99020471
BC		 477 if (nowait) {
478 /*
479 * if we get here, no helper image is needed. Skip the
480 * FW_STATE_INIT state.
481 */
482 priv->fw_state = FW_STATE_LOADING_PREF;
483 rc = mwl8k_request_fw(priv, fw_image,
484 &priv->fw_ucode,
485 true);
486 } else
487 rc = mwl8k_request_fw(priv, fw_image,
488 &priv->fw_ucode, false);
a66098da 489 if (rc) {
c2c357ce 490 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
0863ade8 491 pci_name(priv->pdev), fw_image);
22be40d9 492 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 493 return rc;
494 }
495
496 return 0;
497}
498
499struct mwl8k_cmd_pkt {
500 __le16 code;
501 __le16 length;
f57ca9c1
LB		 502 __u8 seq_num;
503 __u8 macid;
a66098da
LB		 504 __le16 result;
505 char payload[0];
ba2d3587 506} __packed;
a66098da
LB		 507
508/*
509 * Firmware loading.
510 */
511static int
512mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
513{
514 void __iomem *regs = priv->regs;
515 dma_addr_t dma_addr;
a66098da
LB		 516 int loops;
517
518 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
519 if (pci_dma_mapping_error(priv->pdev, dma_addr))
520 return -ENOMEM;
521
522 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
523 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
524 iowrite32(MWL8K_H2A_INT_DOORBELL,
525 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
526 iowrite32(MWL8K_H2A_INT_DUMMY,
527 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
528
a66098da
LB		 529 loops = 1000;
530 do {
531 u32 int_code;
532
533 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
534 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
535 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 536 break;
537 }
538
3d76e82c 539 cond_resched();
a66098da
LB		 540 udelay(1);
541 } while (--loops);
542
543 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
544
d4b70570 545 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 546}
547
548static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
549 const u8 *data, size_t length)
550{
551 struct mwl8k_cmd_pkt *cmd;
552 int done;
553 int rc = 0;
554
555 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
556 if (cmd == NULL)
557 return -ENOMEM;
558
559 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
560 cmd->seq_num = 0;
f57ca9c1 561 cmd->macid = 0;
a66098da
LB		 562 cmd->result = 0;
563
564 done = 0;
565 while (length) {
566 int block_size = length > 256 ? 256 : length;
567
568 memcpy(cmd->payload, data + done, block_size);
569 cmd->length = cpu_to_le16(block_size);
570
571 rc = mwl8k_send_fw_load_cmd(priv, cmd,
572 sizeof(*cmd) + block_size);
573 if (rc)
574 break;
575
576 done += block_size;
577 length -= block_size;
578 }
579
580 if (!rc) {
581 cmd->length = 0;
582 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
583 }
584
585 kfree(cmd);
586
587 return rc;
588}
589
590static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
591 const u8 *data, size_t length)
592{
593 unsigned char *buffer;
594 int may_continue, rc = 0;
595 u32 done, prev_block_size;
596
597 buffer = kmalloc(1024, GFP_KERNEL);
598 if (buffer == NULL)
599 return -ENOMEM;
600
601 done = 0;
602 prev_block_size = 0;
603 may_continue = 1000;
604 while (may_continue > 0) {
605 u32 block_size;
606
607 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
608 if (block_size & 1) {
609 block_size &= ~1;
610 may_continue--;
611 } else {
612 done += prev_block_size;
613 length -= prev_block_size;
614 }
615
616 if (block_size > 1024 || block_size > length) {
617 rc = -EOVERFLOW;
618 break;
619 }
620
621 if (length == 0) {
622 rc = 0;
623 break;
624 }
625
626 if (block_size == 0) {
627 rc = -EPROTO;
628 may_continue--;
629 udelay(1);
630 continue;
631 }
632
633 prev_block_size = block_size;
634 memcpy(buffer, data + done, block_size);
635
636 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
637 if (rc)
638 break;
639 }
640
641 if (!rc && length != 0)
642 rc = -EREMOTEIO;
643
644 kfree(buffer);
645
646 return rc;
647}
648
c2c357ce 649static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 650{
c2c357ce 651 struct mwl8k_priv *priv = hw->priv;
d1f9e41d 652 const struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 653 int rc;
654 int loops;
655
656 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
d1f9e41d 657 const struct firmware *helper = priv->fw_helper;
a66098da 658
c2c357ce
LB		 659 if (helper == NULL) {
660 printk(KERN_ERR "%s: helper image needed but none "
661 "given\n", pci_name(priv->pdev));
662 return -EINVAL;
663 }
a66098da 664
c2c357ce 665 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 666 if (rc) {
667 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 668 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 669 return rc;
670 }
89b872e2 671 msleep(5);
a66098da 672
c2c357ce 673 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 674 } else {
c2c357ce 675 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 676 }
677
678 if (rc) {
c2c357ce
LB		 679 printk(KERN_ERR "%s: unable to load firmware image\n",
680 pci_name(priv->pdev));
a66098da
LB		 681 return rc;
682 }
683
89a91f4f 684 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 685
89b872e2 686 loops = 500000;
a66098da 687 do {
eae74e65
LB		 688 u32 ready_code;
689
690 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
691 if (ready_code == MWL8K_FWAP_READY) {
692 priv->ap_fw = 1;
693 break;
694 } else if (ready_code == MWL8K_FWSTA_READY) {
695 priv->ap_fw = 0;
a66098da 696 break;
eae74e65
LB		 697 }
698
699 cond_resched();
a66098da
LB		 700 udelay(1);
701 } while (--loops);
702
703 return loops ? 0 : -ETIMEDOUT;
704}
705
706
a66098da
LB		 707/* DMA header used by firmware and hardware. */
708struct mwl8k_dma_data {
709 __le16 fwlen;
710 struct ieee80211_hdr wh;
20f09c3d 711 char data[0];
ba2d3587 712} __packed;
a66098da
LB		 713
714/* Routines to add/remove DMA header from skb. */
20f09c3d 715static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 716{
20f09c3d
LB		 717 struct mwl8k_dma_data *tr;
718 int hdrlen;
719
720 tr = (struct mwl8k_dma_data *)skb->data;
721 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
722
723 if (hdrlen != sizeof(tr->wh)) {
724 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
725 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
726 *((__le16 *)(tr->data - 2)) = qos;
727 } else {
728 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
729 }
a66098da 730 }
20f09c3d
LB		 731
732 if (hdrlen != sizeof(*tr))
733 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 734}
735
252486a1
NS		 736static void
737mwl8k_add_dma_header(struct sk_buff *skb, int tail_pad)
a66098da
LB		 738{
739 struct ieee80211_hdr *wh;
ca009301 740 int hdrlen;
252486a1 741 int reqd_hdrlen;
a66098da
LB		 742 struct mwl8k_dma_data *tr;
743
ca009301
LB		 744 /*
745 * Add a firmware DMA header; the firmware requires that we
746 * present a 2-byte payload length followed by a 4-address
747 * header (without QoS field), followed (optionally) by any
748 * WEP/ExtIV header (but only filled in for CCMP).
749 */
a66098da 750 wh = (struct ieee80211_hdr *)skb->data;
ca009301 751
a66098da 752 hdrlen = ieee80211_hdrlen(wh->frame_control);
252486a1
NS		 753 reqd_hdrlen = sizeof(*tr);
754
755 if (hdrlen != reqd_hdrlen)
756 skb_push(skb, reqd_hdrlen - hdrlen);
a66098da 757
ca009301 758 if (ieee80211_is_data_qos(wh->frame_control))
252486a1 759 hdrlen -= IEEE80211_QOS_CTL_LEN;
a66098da
LB		 760
761 tr = (struct mwl8k_dma_data *)skb->data;
762 if (wh != &tr->wh)
763 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 764 if (hdrlen != sizeof(tr->wh))
765 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 766
767 /*
768 * Firmware length is the length of the fully formed "802.11
769 * payload". That is, everything except for the 802.11 header.
770 * This includes all crypto material including the MIC.
771 */
252486a1 772 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr) + tail_pad);
a66098da
LB		 773}
774
e53d9b96
NS		 775static void mwl8k_encapsulate_tx_frame(struct sk_buff *skb)
776{
777 struct ieee80211_hdr *wh;
778 struct ieee80211_tx_info *tx_info;
779 struct ieee80211_key_conf *key_conf;
780 int data_pad;
781
782 wh = (struct ieee80211_hdr *)skb->data;
783
784 tx_info = IEEE80211_SKB_CB(skb);
785
786 key_conf = NULL;
787 if (ieee80211_is_data(wh->frame_control))
788 key_conf = tx_info->control.hw_key;
789
790 /*
791 * Make sure the packet header is in the DMA header format (4-address
792 * without QoS), the necessary crypto padding between the header and the
793 * payload has already been provided by mac80211, but it doesn't add tail
794 * padding when HW crypto is enabled.
795 *
796 * We have the following trailer padding requirements:
797 * - WEP: 4 trailer bytes (ICV)
798 * - TKIP: 12 trailer bytes (8 MIC + 4 ICV)
799 * - CCMP: 8 trailer bytes (MIC)
800 */
801 data_pad = 0;
802 if (key_conf != NULL) {
803 switch (key_conf->cipher) {
804 case WLAN_CIPHER_SUITE_WEP40:
805 case WLAN_CIPHER_SUITE_WEP104:
806 data_pad = 4;
807 break;
808 case WLAN_CIPHER_SUITE_TKIP:
809 data_pad = 12;
810 break;
811 case WLAN_CIPHER_SUITE_CCMP:
812 data_pad = 8;
813 break;
814 }
815 }
816 mwl8k_add_dma_header(skb, data_pad);
817}
a66098da
LB		 818
819/*
89a91f4f 820 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 821 */
89a91f4f 822struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB		 823 __le16 pkt_len;
824 __u8 sq2;
825 __u8 rate;
826 __le32 pkt_phys_addr;
827 __le32 next_rxd_phys_addr;
828 __le16 qos_control;
829 __le16 htsig2;
830 __le32 hw_rssi_info;
831 __le32 hw_noise_floor_info;
832 __u8 noise_floor;
833 __u8 pad0[3];
834 __u8 rssi;
835 __u8 rx_status;
836 __u8 channel;
837 __u8 rx_ctrl;
ba2d3587 838} __packed;
6f6d1e9a 839
89a91f4f
LB		 840#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
841#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
842#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 843
89a91f4f 844#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 845
d9a07d49
NS		 846/* 8366 AP rx_status bits */
847#define MWL8K_8366_AP_RXSTAT_DECRYPT_ERR_MASK 0x80
848#define MWL8K_8366_AP_RXSTAT_GENERAL_DECRYPT_ERR 0xFF
849#define MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR 0x02
850#define MWL8K_8366_AP_RXSTAT_WEP_DECRYPT_ICV_ERR 0x04
851#define MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_ICV_ERR 0x08
852
89a91f4f 853static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 854{
89a91f4f 855 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 856
857 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 858 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 859}
860
89a91f4f 861static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 862{
89a91f4f 863 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 864
865 rxd->pkt_len = cpu_to_le16(len);
866 rxd->pkt_phys_addr = cpu_to_le32(addr);
867 wmb();
868 rxd->rx_ctrl = 0;
869}
870
871static int
89a91f4f 872mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 873 __le16 *qos, s8 *noise)
6f6d1e9a 874{
89a91f4f 875 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 876
89a91f4f 877 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 878 return -1;
879 rmb();
880
881 memset(status, 0, sizeof(*status));
882
883 status->signal = -rxd->rssi;
0d462bbb 884 *noise = -rxd->noise_floor;
6f6d1e9a 885
89a91f4f 886 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 887 status->flag |= RX_FLAG_HT;
89a91f4f 888 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 889 status->flag |= RX_FLAG_40MHZ;
89a91f4f 890 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 891 } else {
892 int i;
893
777ad375
LB		 894 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
895 if (mwl8k_rates_24[i].hw_value == rxd->rate) {
6f6d1e9a
LB		 896 status->rate_idx = i;
897 break;
898 }
899 }
900 }
901
85478344
LB		 902 if (rxd->channel > 14) {
903 status->band = IEEE80211_BAND_5GHZ;
904 if (!(status->flag & RX_FLAG_HT))
905 status->rate_idx -= 5;
906 } else {
907 status->band = IEEE80211_BAND_2GHZ;
908 }
6f6d1e9a
LB		 909 status->freq = ieee80211_channel_to_frequency(rxd->channel);
910
20f09c3d
LB		 911 *qos = rxd->qos_control;
912
d9a07d49
NS		 913 if ((rxd->rx_status != MWL8K_8366_AP_RXSTAT_GENERAL_DECRYPT_ERR) &&
914 (rxd->rx_status & MWL8K_8366_AP_RXSTAT_DECRYPT_ERR_MASK) &&
915 (rxd->rx_status & MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR))
916 status->flag |= RX_FLAG_MMIC_ERROR;
917
6f6d1e9a
LB		 918 return le16_to_cpu(rxd->pkt_len);
919}
920
89a91f4f
LB		 921static struct rxd_ops rxd_8366_ap_ops = {
922 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
923 .rxd_init = mwl8k_rxd_8366_ap_init,
924 .rxd_refill = mwl8k_rxd_8366_ap_refill,
925 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB		 926};
927
928/*
89a91f4f 929 * Packet reception for STA firmware.
a66098da 930 */
89a91f4f 931struct mwl8k_rxd_sta {
a66098da
LB		 932 __le16 pkt_len;
933 __u8 link_quality;
934 __u8 noise_level;
935 __le32 pkt_phys_addr;
45eb400d 936 __le32 next_rxd_phys_addr;
a66098da
LB		 937 __le16 qos_control;
938 __le16 rate_info;
939 __le32 pad0[4];
940 __u8 rssi;
941 __u8 channel;
942 __le16 pad1;
943 __u8 rx_ctrl;
944 __u8 rx_status;
945 __u8 pad2[2];
ba2d3587 946} __packed;
a66098da 947
89a91f4f
LB		 948#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
949#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
950#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
951#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
952#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
953#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 954
89a91f4f 955#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
d9a07d49
NS		 956#define MWL8K_STA_RX_CTRL_DECRYPT_ERROR 0x04
957/* ICV=0 or MIC=1 */
958#define MWL8K_STA_RX_CTRL_DEC_ERR_TYPE 0x08
959/* Key is uploaded only in failure case */
960#define MWL8K_STA_RX_CTRL_KEY_INDEX 0x30
54bc3a0d 961
89a91f4f 962static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 963{
89a91f4f 964 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 965
966 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 967 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 968}
969
89a91f4f 970static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 971{
89a91f4f 972 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 973
974 rxd->pkt_len = cpu_to_le16(len);
975 rxd->pkt_phys_addr = cpu_to_le32(addr);
976 wmb();
977 rxd->rx_ctrl = 0;
978}
979
980static int
89a91f4f 981mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 982 __le16 *qos, s8 *noise)
54bc3a0d 983{
89a91f4f 984 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 985 u16 rate_info;
986
89a91f4f 987 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 988 return -1;
989 rmb();
990
991 rate_info = le16_to_cpu(rxd->rate_info);
992
993 memset(status, 0, sizeof(*status));
994
995 status->signal = -rxd->rssi;
0d462bbb 996 *noise = -rxd->noise_level;
89a91f4f
LB		 997 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
998 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 999
89a91f4f 1000 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 1001 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 1002 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 1003 status->flag |= RX_FLAG_40MHZ;
89a91f4f 1004 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 1005 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 1006 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 1007 status->flag |= RX_FLAG_HT;
1008
85478344
LB		 1009 if (rxd->channel > 14) {
1010 status->band = IEEE80211_BAND_5GHZ;
1011 if (!(status->flag & RX_FLAG_HT))
1012 status->rate_idx -= 5;
1013 } else {
1014 status->band = IEEE80211_BAND_2GHZ;
1015 }
54bc3a0d
LB		 1016 status->freq = ieee80211_channel_to_frequency(rxd->channel);
1017
20f09c3d 1018 *qos = rxd->qos_control;
d9a07d49
NS		 1019 if ((rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DECRYPT_ERROR) &&
1020 (rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DEC_ERR_TYPE))
1021 status->flag |= RX_FLAG_MMIC_ERROR;
20f09c3d 1022
54bc3a0d
LB		 1023 return le16_to_cpu(rxd->pkt_len);
1024}
1025
89a91f4f
LB		 1026static struct rxd_ops rxd_sta_ops = {
1027 .rxd_size = sizeof(struct mwl8k_rxd_sta),
1028 .rxd_init = mwl8k_rxd_sta_init,
1029 .rxd_refill = mwl8k_rxd_sta_refill,
1030 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 1031};
1032
1033
a66098da
LB		 1034#define MWL8K_RX_DESCS 256
1035#define MWL8K_RX_MAXSZ 3800
1036
1037static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
1038{
1039 struct mwl8k_priv *priv = hw->priv;
1040 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1041 int size;
1042 int i;
1043
45eb400d
LB		 1044 rxq->rxd_count = 0;
1045 rxq->head = 0;
1046 rxq->tail = 0;
a66098da 1047
54bc3a0d 1048 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 1049
45eb400d
LB		 1050 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
1051 if (rxq->rxd == NULL) {
5db55844 1052 wiphy_err(hw->wiphy, "failed to alloc RX descriptors\n");
a66098da
LB		 1053 return -ENOMEM;
1054 }
45eb400d 1055 memset(rxq->rxd, 0, size);
a66098da 1056
788838eb
LB		 1057 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
1058 if (rxq->buf == NULL) {
5db55844 1059 wiphy_err(hw->wiphy, "failed to alloc RX skbuff list\n");
45eb400d 1060 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 1061 return -ENOMEM;
1062 }
788838eb 1063 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 1064
1065 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 1066 int desc_size;
1067 void *rxd;
a66098da 1068 int nexti;
54bc3a0d
LB		 1069 dma_addr_t next_dma_addr;
1070
1071 desc_size = priv->rxd_ops->rxd_size;
1072 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 1073
54bc3a0d
LB		 1074 nexti = i + 1;
1075 if (nexti == MWL8K_RX_DESCS)
1076 nexti = 0;
1077 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 1078
54bc3a0d 1079 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 1080 }
1081
1082 return 0;
1083}
1084
1085static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1086{
1087 struct mwl8k_priv *priv = hw->priv;
1088 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1089 int refilled;
1090
1091 refilled = 0;
45eb400d 1092 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 1093 struct sk_buff *skb;
788838eb 1094 dma_addr_t addr;
a66098da 1095 int rx;
54bc3a0d 1096 void *rxd;
a66098da
LB		 1097
1098 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1099 if (skb == NULL)
1100 break;
1101
788838eb
LB		 1102 addr = pci_map_single(priv->pdev, skb->data,
1103 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1104
54bc3a0d
LB		 1105 rxq->rxd_count++;
1106 rx = rxq->tail++;
1107 if (rxq->tail == MWL8K_RX_DESCS)
1108 rxq->tail = 0;
788838eb 1109 rxq->buf[rx].skb = skb;
53b1b3e1 1110 dma_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 1111
1112 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1113 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 1114
1115 refilled++;
1116 }
1117
1118 return refilled;
1119}
1120
1121/* Must be called only when the card's reception is completely halted */
1122static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1123{
1124 struct mwl8k_priv *priv = hw->priv;
1125 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1126 int i;
1127
1128 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 1129 if (rxq->buf[i].skb != NULL) {
1130 pci_unmap_single(priv->pdev,
53b1b3e1 1131 dma_unmap_addr(&rxq->buf[i], dma),
788838eb 1132 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1133 dma_unmap_addr_set(&rxq->buf[i], dma, 0);
788838eb
LB		 1134
1135 kfree_skb(rxq->buf[i].skb);
1136 rxq->buf[i].skb = NULL;
a66098da
LB		 1137 }
1138 }
1139
788838eb
LB		 1140 kfree(rxq->buf);
1141 rxq->buf = NULL;
a66098da
LB		 1142
1143 pci_free_consistent(priv->pdev,
54bc3a0d 1144 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1145 rxq->rxd, rxq->rxd_dma);
1146 rxq->rxd = NULL;
a66098da
LB		 1147}
1148
1149
1150/*
1151 * Scan a list of BSSIDs to process for finalize join.
1152 * Allows for extension to process multiple BSSIDs.
1153 */
1154static inline int
1155mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1156{
1157 return priv->capture_beacon &&
1158 ieee80211_is_beacon(wh->frame_control) &&
1159 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1160}
1161
3779752d
LB		 1162static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1163 struct sk_buff *skb)
a66098da 1164{
3779752d
LB		 1165 struct mwl8k_priv *priv = hw->priv;
1166
a66098da 1167 priv->capture_beacon = false;
d89173f2 1168 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1169
1170 /*
1171 * Use GFP_ATOMIC as rxq_process is called from
1172 * the primary interrupt handler, memory allocation call
1173 * must not sleep.
1174 */
1175 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1176 if (priv->beacon_skb != NULL)
3779752d 1177 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1178}
1179
d9a07d49
NS		 1180static inline struct mwl8k_vif *mwl8k_find_vif_bss(struct list_head *vif_list,
1181 u8 *bssid)
1182{
1183 struct mwl8k_vif *mwl8k_vif;
1184
1185 list_for_each_entry(mwl8k_vif,
1186 vif_list, list) {
1187 if (memcmp(bssid, mwl8k_vif->bssid,
1188 ETH_ALEN) == 0)
1189 return mwl8k_vif;
1190 }
1191
1192 return NULL;
1193}
1194
a66098da
LB		 1195static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1196{
1197 struct mwl8k_priv *priv = hw->priv;
d9a07d49 1198 struct mwl8k_vif *mwl8k_vif = NULL;
a66098da
LB		 1199 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1200 int processed;
1201
1202 processed = 0;
45eb400d 1203 while (rxq->rxd_count && limit--) {
a66098da 1204 struct sk_buff *skb;
54bc3a0d
LB		 1205 void *rxd;
1206 int pkt_len;
a66098da 1207 struct ieee80211_rx_status status;
d9a07d49 1208 struct ieee80211_hdr *wh;
20f09c3d 1209 __le16 qos;
a66098da 1210
788838eb 1211 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1212 if (skb == NULL)
1213 break;
54bc3a0d
LB		 1214
1215 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1216
0d462bbb
JL		 1217 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos,
1218 &priv->noise);
54bc3a0d
LB		 1219 if (pkt_len < 0)
1220 break;
1221
788838eb
LB		 1222 rxq->buf[rxq->head].skb = NULL;
1223
1224 pci_unmap_single(priv->pdev,
53b1b3e1 1225 dma_unmap_addr(&rxq->buf[rxq->head], dma),
788838eb 1226 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1227 dma_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1228
54bc3a0d
LB		 1229 rxq->head++;
1230 if (rxq->head == MWL8K_RX_DESCS)
1231 rxq->head = 0;
1232
45eb400d 1233 rxq->rxd_count--;
a66098da 1234
d9a07d49 1235 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da 1236
a66098da 1237 /*
c2c357ce
LB		 1238 * Check for a pending join operation. Save a
1239 * copy of the beacon and schedule a tasklet to
1240 * send a FINALIZE_JOIN command to the firmware.
a66098da 1241 */
54bc3a0d 1242 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1243 mwl8k_save_beacon(hw, skb);
a66098da 1244
d9a07d49
NS		 1245 if (ieee80211_has_protected(wh->frame_control)) {
1246
1247 /* Check if hw crypto has been enabled for
1248 * this bss. If yes, set the status flags
1249 * accordingly
1250 */
1251 mwl8k_vif = mwl8k_find_vif_bss(&priv->vif_list,
1252 wh->addr1);
1253
1254 if (mwl8k_vif != NULL &&
1255 mwl8k_vif->is_hw_crypto_enabled == true) {
1256 /*
1257 * When MMIC ERROR is encountered
1258 * by the firmware, payload is
1259 * dropped and only 32 bytes of
1260 * mwl8k Firmware header is sent
1261 * to the host.
1262 *
1263 * We need to add four bytes of
1264 * key information. In it
1265 * MAC80211 expects keyidx set to
1266 * 0 for triggering Counter
1267 * Measure of MMIC failure.
1268 */
1269 if (status.flag & RX_FLAG_MMIC_ERROR) {
1270 struct mwl8k_dma_data *tr;
1271 tr = (struct mwl8k_dma_data *)skb->data;
1272 memset((void *)&(tr->data), 0, 4);
1273 pkt_len += 4;
1274 }
1275
1276 if (!ieee80211_is_auth(wh->frame_control))
1277 status.flag |= RX_FLAG_IV_STRIPPED |
1278 RX_FLAG_DECRYPTED |
1279 RX_FLAG_MMIC_STRIPPED;
1280 }
1281 }
1282
1283 skb_put(skb, pkt_len);
1284 mwl8k_remove_dma_header(skb, qos);
f1d58c25
JB		 1285 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1286 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1287
1288 processed++;
1289 }
1290
1291 return processed;
1292}
1293
1294
1295/*
1296 * Packet transmission.
1297 */
1298
a66098da
LB		 1299#define MWL8K_TXD_STATUS_OK 0x00000001
1300#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1301#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1302#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1303#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1304
e0493a8d
LB		 1305#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1306#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1307#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1308#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1309#define MWL8K_QOS_EOSP 0x0010
1310
a66098da
LB		 1311struct mwl8k_tx_desc {
1312 __le32 status;
1313 __u8 data_rate;
1314 __u8 tx_priority;
1315 __le16 qos_control;
1316 __le32 pkt_phys_addr;
1317 __le16 pkt_len;
d89173f2 1318 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1319 __le32 next_txd_phys_addr;
a66098da
LB		 1320 __le32 reserved;
1321 __le16 rate_info;
1322 __u8 peer_id;
a1fe24b0 1323 __u8 tx_frag_cnt;
ba2d3587 1324} __packed;
a66098da
LB		 1325
1326#define MWL8K_TX_DESCS 128
1327
1328static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1329{
1330 struct mwl8k_priv *priv = hw->priv;
1331 struct mwl8k_tx_queue *txq = priv->txq + index;
1332 int size;
1333 int i;
1334
8ccbc3b8 1335 txq->len = 0;
45eb400d
LB		 1336 txq->head = 0;
1337 txq->tail = 0;
a66098da
LB		 1338
1339 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1340
45eb400d
LB		 1341 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1342 if (txq->txd == NULL) {
5db55844 1343 wiphy_err(hw->wiphy, "failed to alloc TX descriptors\n");
a66098da
LB		 1344 return -ENOMEM;
1345 }
45eb400d 1346 memset(txq->txd, 0, size);
a66098da 1347
45eb400d
LB		 1348 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1349 if (txq->skb == NULL) {
5db55844 1350 wiphy_err(hw->wiphy, "failed to alloc TX skbuff list\n");
45eb400d 1351 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1352 return -ENOMEM;
1353 }
45eb400d 1354 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1355
1356 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1357 struct mwl8k_tx_desc *tx_desc;
1358 int nexti;
1359
45eb400d 1360 tx_desc = txq->txd + i;
a66098da
LB		 1361 nexti = (i + 1) % MWL8K_TX_DESCS;
1362
1363 tx_desc->status = 0;
45eb400d
LB		 1364 tx_desc->next_txd_phys_addr =
1365 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1366 }
1367
1368 return 0;
1369}
1370
1371static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1372{
1373 iowrite32(MWL8K_H2A_INT_PPA_READY,
1374 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1375 iowrite32(MWL8K_H2A_INT_DUMMY,
1376 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1377 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1378}
1379
7e1112d3 1380static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1381{
7e1112d3
LB		 1382 struct mwl8k_priv *priv = hw->priv;
1383 int i;
1384
1385 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1386 struct mwl8k_tx_queue *txq = priv->txq + i;
1387 int fw_owned = 0;
1388 int drv_owned = 0;
1389 int unused = 0;
1390 int desc;
1391
a66098da 1392 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1393 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1394 u32 status;
a66098da 1395
7e1112d3 1396 status = le32_to_cpu(tx_desc->status);
a66098da 1397 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1398 fw_owned++;
a66098da 1399 else
7e1112d3 1400 drv_owned++;
a66098da
LB		 1401
1402 if (tx_desc->pkt_len == 0)
7e1112d3 1403 unused++;
a66098da 1404 }
a66098da 1405
c96c31e4
JP		 1406 wiphy_err(hw->wiphy,
1407 "txq[%d] len=%d head=%d tail=%d "
1408 "fw_owned=%d drv_owned=%d unused=%d\n",
1409 i,
1410 txq->len, txq->head, txq->tail,
1411 fw_owned, drv_owned, unused);
7e1112d3 1412 }
a66098da
LB		 1413}
1414
618952a7 1415/*
88de754a 1416 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1417 */
62abd3cf 1418#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1419
950d5b01 1420static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1421{
a66098da 1422 struct mwl8k_priv *priv = hw->priv;
88de754a 1423 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1424 int retry;
1425 int rc;
a66098da
LB		 1426
1427 might_sleep();
1428
7e1112d3
LB		 1429 /*
1430 * The TX queues are stopped at this point, so this test
1431 * doesn't need to take ->tx_lock.
1432 */
1433 if (!priv->pending_tx_pkts)
1434 return 0;
1435
1436 retry = 0;
1437 rc = 0;
1438
a66098da 1439 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1440 priv->tx_wait = &tx_wait;
1441 while (!rc) {
1442 int oldcount;
1443 unsigned long timeout;
a66098da 1444
7e1112d3 1445 oldcount = priv->pending_tx_pkts;
a66098da 1446
7e1112d3 1447 spin_unlock_bh(&priv->tx_lock);
88de754a 1448 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1449 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1450 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1451
1452 if (timeout) {
1453 WARN_ON(priv->pending_tx_pkts);
1454 if (retry) {
c96c31e4 1455 wiphy_notice(hw->wiphy, "tx rings drained\n");
7e1112d3
LB		 1456 }
1457 break;
1458 }
1459
1460 if (priv->pending_tx_pkts < oldcount) {
c96c31e4
JP		 1461 wiphy_notice(hw->wiphy,
1462 "waiting for tx rings to drain (%d -> %d pkts)\n",
1463 oldcount, priv->pending_tx_pkts);
7e1112d3
LB		 1464 retry = 1;
1465 continue;
1466 }
1467
a66098da 1468 priv->tx_wait = NULL;
a66098da 1469
c96c31e4
JP		 1470 wiphy_err(hw->wiphy, "tx rings stuck for %d ms\n",
1471 MWL8K_TX_WAIT_TIMEOUT_MS);
7e1112d3
LB		 1472 mwl8k_dump_tx_rings(hw);
1473
1474 rc = -ETIMEDOUT;
a66098da 1475 }
7e1112d3 1476 spin_unlock_bh(&priv->tx_lock);
a66098da 1477
7e1112d3 1478 return rc;
a66098da
LB		 1479}
1480
c23b5a69
LB		 1481#define MWL8K_TXD_SUCCESS(status) \
1482 ((status) & (MWL8K_TXD_STATUS_OK | \
1483 MWL8K_TXD_STATUS_OK_RETRY | \
1484 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1485
efb7c49a
LB		 1486static int
1487mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB		 1488{
1489 struct mwl8k_priv *priv = hw->priv;
1490 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1491 int processed;
a66098da 1492
efb7c49a 1493 processed = 0;
8ccbc3b8 1494 while (txq->len > 0 && limit--) {
a66098da 1495 int tx;
a66098da
LB		 1496 struct mwl8k_tx_desc *tx_desc;
1497 unsigned long addr;
ce9e2e1b 1498 int size;
a66098da
LB		 1499 struct sk_buff *skb;
1500 struct ieee80211_tx_info *info;
1501 u32 status;
1502
45eb400d
LB		 1503 tx = txq->head;
1504 tx_desc = txq->txd + tx;
a66098da
LB		 1505
1506 status = le32_to_cpu(tx_desc->status);
1507
1508 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1509 if (!force)
1510 break;
1511 tx_desc->status &=
1512 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1513 }
1514
45eb400d 1515 txq->head = (tx + 1) % MWL8K_TX_DESCS;
8ccbc3b8
KV		 1516 BUG_ON(txq->len == 0);
1517 txq->len--;
a66098da
LB		 1518 priv->pending_tx_pkts--;
1519
1520 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1521 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1522 skb = txq->skb[tx];
1523 txq->skb[tx] = NULL;
a66098da
LB		 1524
1525 BUG_ON(skb == NULL);
1526 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1527
20f09c3d 1528 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1529
1530 /* Mark descriptor as unused */
1531 tx_desc->pkt_phys_addr = 0;
1532 tx_desc->pkt_len = 0;
1533
a66098da
LB		 1534 info = IEEE80211_SKB_CB(skb);
1535 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1536 if (MWL8K_TXD_SUCCESS(status))
a66098da 1537 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1538
1539 ieee80211_tx_status_irqsafe(hw, skb);
1540
efb7c49a 1541 processed++;
a66098da
LB		 1542 }
1543
efb7c49a 1544 if (processed && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da 1545 ieee80211_wake_queue(hw, index);
efb7c49a
LB		 1546
1547 return processed;
a66098da
LB		 1548}
1549
1550/* must be called only when the card's transmit is completely halted */
1551static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1552{
1553 struct mwl8k_priv *priv = hw->priv;
1554 struct mwl8k_tx_queue *txq = priv->txq + index;
1555
efb7c49a 1556 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1557
45eb400d
LB		 1558 kfree(txq->skb);
1559 txq->skb = NULL;
a66098da
LB		 1560
1561 pci_free_consistent(priv->pdev,
1562 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1563 txq->txd, txq->txd_dma);
1564 txq->txd = NULL;
a66098da
LB		 1565}
1566
1567static int
1568mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1569{
1570 struct mwl8k_priv *priv = hw->priv;
1571 struct ieee80211_tx_info *tx_info;
23b33906 1572 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1573 struct ieee80211_hdr *wh;
1574 struct mwl8k_tx_queue *txq;
1575 struct mwl8k_tx_desc *tx;
a66098da 1576 dma_addr_t dma;
23b33906
LB		 1577 u32 txstatus;
1578 u8 txdatarate;
1579 u16 qos;
a66098da 1580
23b33906
LB		 1581 wh = (struct ieee80211_hdr *)skb->data;
1582 if (ieee80211_is_data_qos(wh->frame_control))
1583 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1584 else
1585 qos = 0;
a66098da 1586
d9a07d49
NS		 1587 if (priv->ap_fw)
1588 mwl8k_encapsulate_tx_frame(skb);
1589 else
1590 mwl8k_add_dma_header(skb, 0);
1591
23b33906 1592 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1593
1594 tx_info = IEEE80211_SKB_CB(skb);
1595 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1596
1597 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
a66098da 1598 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
657232b6
LB		 1599 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1600 mwl8k_vif->seqno += 0x10;
a66098da
LB		 1601 }
1602
23b33906
LB		 1603 /* Setup firmware control bit fields for each frame type. */
1604 txstatus = 0;
1605 txdatarate = 0;
1606 if (ieee80211_is_mgmt(wh->frame_control) ||
1607 ieee80211_is_ctl(wh->frame_control)) {
1608 txdatarate = 0;
e0493a8d 1609 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1610 } else if (ieee80211_is_data(wh->frame_control)) {
1611 txdatarate = 1;
1612 if (is_multicast_ether_addr(wh->addr1))
1613 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1614
e0493a8d 1615 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1616 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1617 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1618 else
e0493a8d 1619 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1620 }
a66098da
LB		 1621
1622 dma = pci_map_single(priv->pdev, skb->data,
1623 skb->len, PCI_DMA_TODEVICE);
1624
1625 if (pci_dma_mapping_error(priv->pdev, dma)) {
c96c31e4
JP		 1626 wiphy_debug(hw->wiphy,
1627 "failed to dma map skb, dropping TX frame.\n");
23b33906 1628 dev_kfree_skb(skb);
a66098da
LB		 1629 return NETDEV_TX_OK;
1630 }
1631
23b33906 1632 spin_lock_bh(&priv->tx_lock);
a66098da 1633
23b33906 1634 txq = priv->txq + index;
a66098da 1635
45eb400d
LB		 1636 BUG_ON(txq->skb[txq->tail] != NULL);
1637 txq->skb[txq->tail] = skb;
a66098da 1638
45eb400d 1639 tx = txq->txd + txq->tail;
23b33906
LB		 1640 tx->data_rate = txdatarate;
1641 tx->tx_priority = index;
a66098da 1642 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1643 tx->pkt_phys_addr = cpu_to_le32(dma);
1644 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1645 tx->rate_info = 0;
a680400e
LB		 1646 if (!priv->ap_fw && tx_info->control.sta != NULL)
1647 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1648 else
1649 tx->peer_id = 0;
a66098da 1650 wmb();
23b33906
LB		 1651 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1652
8ccbc3b8 1653 txq->len++;
a66098da 1654 priv->pending_tx_pkts++;
a66098da 1655
45eb400d
LB		 1656 txq->tail++;
1657 if (txq->tail == MWL8K_TX_DESCS)
1658 txq->tail = 0;
23b33906 1659
45eb400d 1660 if (txq->head == txq->tail)
a66098da
LB		 1661 ieee80211_stop_queue(hw, index);
1662
23b33906 1663 mwl8k_tx_start(priv);
a66098da
LB		 1664
1665 spin_unlock_bh(&priv->tx_lock);
1666
1667 return NETDEV_TX_OK;
1668}
1669
1670
618952a7
LB		 1671/*
1672 * Firmware access.
1673 *
1674 * We have the following requirements for issuing firmware commands:
1675 * - Some commands require that the packet transmit path is idle when
1676 * the command is issued. (For simplicity, we'll just quiesce the
1677 * transmit path for every command.)
1678 * - There are certain sequences of commands that need to be issued to
1679 * the hardware sequentially, with no other intervening commands.
1680 *
1681 * This leads to an implementation of a "firmware lock" as a mutex that
1682 * can be taken recursively, and which is taken by both the low-level
1683 * command submission function (mwl8k_post_cmd) as well as any users of
1684 * that function that require issuing of an atomic sequence of commands,
1685 * and quiesces the transmit path whenever it's taken.
1686 */
1687static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1688{
1689 struct mwl8k_priv *priv = hw->priv;
1690
1691 if (priv->fw_mutex_owner != current) {
1692 int rc;
1693
1694 mutex_lock(&priv->fw_mutex);
1695 ieee80211_stop_queues(hw);
1696
1697 rc = mwl8k_tx_wait_empty(hw);
1698 if (rc) {
1699 ieee80211_wake_queues(hw);
1700 mutex_unlock(&priv->fw_mutex);
1701
1702 return rc;
1703 }
1704
1705 priv->fw_mutex_owner = current;
1706 }
1707
1708 priv->fw_mutex_depth++;
1709
1710 return 0;
1711}
1712
1713static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1714{
1715 struct mwl8k_priv *priv = hw->priv;
1716
1717 if (!--priv->fw_mutex_depth) {
1718 ieee80211_wake_queues(hw);
1719 priv->fw_mutex_owner = NULL;
1720 mutex_unlock(&priv->fw_mutex);
1721 }
1722}
1723
1724
a66098da
LB		 1725/*
1726 * Command processing.
1727 */
1728
0c9cc640
LB		 1729/* Timeout firmware commands after 10s */
1730#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 1731
1732static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1733{
1734 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1735 struct mwl8k_priv *priv = hw->priv;
1736 void __iomem *regs = priv->regs;
1737 dma_addr_t dma_addr;
1738 unsigned int dma_size;
1739 int rc;
a66098da
LB		 1740 unsigned long timeout = 0;
1741 u8 buf[32];
1742
b603742f 1743 cmd->result = (__force __le16) 0xffff;
a66098da
LB		 1744 dma_size = le16_to_cpu(cmd->length);
1745 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1746 PCI_DMA_BIDIRECTIONAL);
1747 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1748 return -ENOMEM;
1749
618952a7 1750 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1751 if (rc) {
1752 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1753 PCI_DMA_BIDIRECTIONAL);
618952a7 1754 return rc;
39a1e42e 1755 }
a66098da 1756
a66098da
LB		 1757 priv->hostcmd_wait = &cmd_wait;
1758 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1759 iowrite32(MWL8K_H2A_INT_DOORBELL,
1760 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1761 iowrite32(MWL8K_H2A_INT_DUMMY,
1762 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1763
1764 timeout = wait_for_completion_timeout(&cmd_wait,
1765 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1766
618952a7
LB		 1767 priv->hostcmd_wait = NULL;
1768
1769 mwl8k_fw_unlock(hw);
1770
37055bd4
LB		 1771 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1772 PCI_DMA_BIDIRECTIONAL);
1773
a66098da 1774 if (!timeout) {
5db55844 1775 wiphy_err(hw->wiphy, "Command %s timeout after %u ms\n",
c96c31e4
JP		 1776 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1777 MWL8K_CMD_TIMEOUT_MS);
a66098da
LB		 1778 rc = -ETIMEDOUT;
1779 } else {
0c9cc640
LB		 1780 int ms;
1781
1782 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1783
ce9e2e1b 1784 rc = cmd->result ? -EINVAL : 0;
a66098da 1785 if (rc)
5db55844 1786 wiphy_err(hw->wiphy, "Command %s error 0x%x\n",
c96c31e4
JP		 1787 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1788 le16_to_cpu(cmd->result));
0c9cc640 1789 else if (ms > 2000)
5db55844 1790 wiphy_notice(hw->wiphy, "Command %s took %d ms\n",
c96c31e4
JP		 1791 mwl8k_cmd_name(cmd->code,
1792 buf, sizeof(buf)),
1793 ms);
a66098da
LB		 1794 }
1795
a66098da
LB		 1796 return rc;
1797}
1798
f57ca9c1
LB		 1799static int mwl8k_post_pervif_cmd(struct ieee80211_hw *hw,
1800 struct ieee80211_vif *vif,
1801 struct mwl8k_cmd_pkt *cmd)
1802{
1803 if (vif != NULL)
1804 cmd->macid = MWL8K_VIF(vif)->macid;
1805 return mwl8k_post_cmd(hw, cmd);
1806}
1807
1349ad2f
LB		 1808/*
1809 * Setup code shared between STA and AP firmware images.
1810 */
1811static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw)
1812{
1813 struct mwl8k_priv *priv = hw->priv;
1814
1815 BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24));
1816 memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
1817
1818 BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
1819 memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
1820
1821 priv->band_24.band = IEEE80211_BAND_2GHZ;
1822 priv->band_24.channels = priv->channels_24;
1823 priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
1824 priv->band_24.bitrates = priv->rates_24;
1825 priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
1826
1827 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24;
1828}
1829
4eae9edd
LB		 1830static void mwl8k_setup_5ghz_band(struct ieee80211_hw *hw)
1831{
1832 struct mwl8k_priv *priv = hw->priv;
1833
1834 BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl8k_channels_50));
1835 memcpy(priv->channels_50, mwl8k_channels_50, sizeof(mwl8k_channels_50));
1836
1837 BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl8k_rates_50));
1838 memcpy(priv->rates_50, mwl8k_rates_50, sizeof(mwl8k_rates_50));
1839
1840 priv->band_50.band = IEEE80211_BAND_5GHZ;
1841 priv->band_50.channels = priv->channels_50;
1842 priv->band_50.n_channels = ARRAY_SIZE(mwl8k_channels_50);
1843 priv->band_50.bitrates = priv->rates_50;
1844 priv->band_50.n_bitrates = ARRAY_SIZE(mwl8k_rates_50);
1845
1846 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->band_50;
1847}
1848
a66098da 1849/*
04b147b1 1850 * CMD_GET_HW_SPEC (STA version).
a66098da 1851 */
04b147b1 1852struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1853 struct mwl8k_cmd_pkt header;
1854 __u8 hw_rev;
1855 __u8 host_interface;
1856 __le16 num_mcaddrs;
d89173f2 1857 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1858 __le16 region_code;
1859 __le32 fw_rev;
1860 __le32 ps_cookie;
1861 __le32 caps;
1862 __u8 mcs_bitmap[16];
1863 __le32 rx_queue_ptr;
1864 __le32 num_tx_queues;
1865 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1866 __le32 caps2;
1867 __le32 num_tx_desc_per_queue;
45eb400d 1868 __le32 total_rxd;
ba2d3587 1869} __packed;
a66098da 1870
341c9791
LB		 1871#define MWL8K_CAP_MAX_AMSDU 0x20000000
1872#define MWL8K_CAP_GREENFIELD 0x08000000
1873#define MWL8K_CAP_AMPDU 0x04000000
1874#define MWL8K_CAP_RX_STBC 0x01000000
1875#define MWL8K_CAP_TX_STBC 0x00800000
1876#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
1877#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
1878#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
1879#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
1880#define MWL8K_CAP_DELAY_BA 0x00003000
1881#define MWL8K_CAP_MIMO 0x00000200
1882#define MWL8K_CAP_40MHZ 0x00000100
06953235
LB		 1883#define MWL8K_CAP_BAND_MASK 0x00000007
1884#define MWL8K_CAP_5GHZ 0x00000004
1885#define MWL8K_CAP_2GHZ4 0x00000001
341c9791 1886
06953235
LB		 1887static void
1888mwl8k_set_ht_caps(struct ieee80211_hw *hw,
1889 struct ieee80211_supported_band *band, u32 cap)
341c9791 1890{
341c9791
LB		 1891 int rx_streams;
1892 int tx_streams;
1893
777ad375 1894 band->ht_cap.ht_supported = 1;
341c9791
LB		 1895
1896 if (cap & MWL8K_CAP_MAX_AMSDU)
777ad375 1897 band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
341c9791 1898 if (cap & MWL8K_CAP_GREENFIELD)
777ad375 1899 band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
341c9791
LB		 1900 if (cap & MWL8K_CAP_AMPDU) {
1901 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
777ad375
LB		 1902 band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1903 band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
341c9791
LB		 1904 }
1905 if (cap & MWL8K_CAP_RX_STBC)
777ad375 1906 band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
341c9791 1907 if (cap & MWL8K_CAP_TX_STBC)
777ad375 1908 band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
341c9791 1909 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
777ad375 1910 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
341c9791 1911 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
777ad375 1912 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
341c9791 1913 if (cap & MWL8K_CAP_DELAY_BA)
777ad375 1914 band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
341c9791 1915 if (cap & MWL8K_CAP_40MHZ)
777ad375 1916 band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
341c9791
LB		 1917
1918 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
1919 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
1920
777ad375 1921 band->ht_cap.mcs.rx_mask[0] = 0xff;
341c9791 1922 if (rx_streams >= 2)
777ad375 1923 band->ht_cap.mcs.rx_mask[1] = 0xff;
341c9791 1924 if (rx_streams >= 3)
777ad375
LB		 1925 band->ht_cap.mcs.rx_mask[2] = 0xff;
1926 band->ht_cap.mcs.rx_mask[4] = 0x01;
1927 band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
341c9791
LB		 1928
1929 if (rx_streams != tx_streams) {
777ad375
LB		 1930 band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
1931 band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
341c9791
LB		 1932 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
1933 }
1934}
1935
06953235
LB		 1936static void
1937mwl8k_set_caps(struct ieee80211_hw *hw, u32 caps)
1938{
1939 struct mwl8k_priv *priv = hw->priv;
1940
1941 if ((caps & MWL8K_CAP_2GHZ4) || !(caps & MWL8K_CAP_BAND_MASK)) {
1942 mwl8k_setup_2ghz_band(hw);
1943 if (caps & MWL8K_CAP_MIMO)
1944 mwl8k_set_ht_caps(hw, &priv->band_24, caps);
1945 }
1946
1947 if (caps & MWL8K_CAP_5GHZ) {
1948 mwl8k_setup_5ghz_band(hw);
1949 if (caps & MWL8K_CAP_MIMO)
1950 mwl8k_set_ht_caps(hw, &priv->band_50, caps);
1951 }
1952}
1953
04b147b1 1954static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1955{
1956 struct mwl8k_priv *priv = hw->priv;
04b147b1 1957 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1958 int rc;
1959 int i;
1960
1961 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1962 if (cmd == NULL)
1963 return -ENOMEM;
1964
1965 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1966 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1967
1968 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1969 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1970 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1971 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1972 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1973 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1974 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1975 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1976
1977 rc = mwl8k_post_cmd(hw, &cmd->header);
1978
1979 if (!rc) {
1980 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1981 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1982 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1983 priv->hw_rev = cmd->hw_rev;
06953235 1984 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18
LB		 1985 priv->ap_macids_supported = 0x00000000;
1986 priv->sta_macids_supported = 0x00000001;
a66098da
LB		 1987 }
1988
1989 kfree(cmd);
1990 return rc;
1991}
1992
42fba21d
LB		 1993/*
1994 * CMD_GET_HW_SPEC (AP version).
1995 */
1996struct mwl8k_cmd_get_hw_spec_ap {
1997 struct mwl8k_cmd_pkt header;
1998 __u8 hw_rev;
1999 __u8 host_interface;
2000 __le16 num_wcb;
2001 __le16 num_mcaddrs;
2002 __u8 perm_addr[ETH_ALEN];
2003 __le16 region_code;
2004 __le16 num_antenna;
2005 __le32 fw_rev;
2006 __le32 wcbbase0;
2007 __le32 rxwrptr;
2008 __le32 rxrdptr;
2009 __le32 ps_cookie;
2010 __le32 wcbbase1;
2011 __le32 wcbbase2;
2012 __le32 wcbbase3;
952a0e96 2013 __le32 fw_api_version;
ba2d3587 2014} __packed;
42fba21d
LB		 2015
2016static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
2017{
2018 struct mwl8k_priv *priv = hw->priv;
2019 struct mwl8k_cmd_get_hw_spec_ap *cmd;
2020 int rc;
952a0e96 2021 u32 api_version;
42fba21d
LB		 2022
2023 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2024 if (cmd == NULL)
2025 return -ENOMEM;
2026
2027 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2028 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2029
2030 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2031 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2032
2033 rc = mwl8k_post_cmd(hw, &cmd->header);
2034
2035 if (!rc) {
2036 int off;
2037
952a0e96
BC		 2038 api_version = le32_to_cpu(cmd->fw_api_version);
2039 if (priv->device_info->fw_api_ap != api_version) {
2040 printk(KERN_ERR "%s: Unsupported fw API version for %s."
2041 " Expected %d got %d.\n", MWL8K_NAME,
2042 priv->device_info->part_name,
2043 priv->device_info->fw_api_ap,
2044 api_version);
2045 rc = -EINVAL;
2046 goto done;
2047 }
42fba21d
LB		 2048 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2049 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
2050 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
2051 priv->hw_rev = cmd->hw_rev;
1349ad2f 2052 mwl8k_setup_2ghz_band(hw);
ee0ddf18
LB		 2053 priv->ap_macids_supported = 0x000000ff;
2054 priv->sta_macids_supported = 0x00000000;
42fba21d
LB		 2055
2056 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
b603742f 2057 iowrite32(priv->txq[0].txd_dma, priv->sram + off);
42fba21d
LB		 2058
2059 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
b603742f 2060 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d
LB		 2061
2062 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
b603742f 2063 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d
LB		 2064
2065 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
b603742f 2066 iowrite32(priv->txq[1].txd_dma, priv->sram + off);
42fba21d
LB		 2067
2068 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
b603742f 2069 iowrite32(priv->txq[2].txd_dma, priv->sram + off);
42fba21d
LB		 2070
2071 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
b603742f 2072 iowrite32(priv->txq[3].txd_dma, priv->sram + off);
42fba21d
LB		 2073 }
2074
952a0e96 2075done:
42fba21d
LB		 2076 kfree(cmd);
2077 return rc;
2078}
2079
2080/*
2081 * CMD_SET_HW_SPEC.
2082 */
2083struct mwl8k_cmd_set_hw_spec {
2084 struct mwl8k_cmd_pkt header;
2085 __u8 hw_rev;
2086 __u8 host_interface;
2087 __le16 num_mcaddrs;
2088 __u8 perm_addr[ETH_ALEN];
2089 __le16 region_code;
2090 __le32 fw_rev;
2091 __le32 ps_cookie;
2092 __le32 caps;
2093 __le32 rx_queue_ptr;
2094 __le32 num_tx_queues;
2095 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
2096 __le32 flags;
2097 __le32 num_tx_desc_per_queue;
2098 __le32 total_rxd;
ba2d3587 2099} __packed;
42fba21d 2100
b64fe619
LB		 2101#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
2102#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
2103#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB		 2104
2105static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
2106{
2107 struct mwl8k_priv *priv = hw->priv;
2108 struct mwl8k_cmd_set_hw_spec *cmd;
2109 int rc;
2110 int i;
2111
2112 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2113 if (cmd == NULL)
2114 return -ENOMEM;
2115
2116 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
2117 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2118
2119 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2120 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
2121 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
2122 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2123 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
b64fe619
LB		 2124 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
2125 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
2126 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
42fba21d
LB		 2127 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
2128 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
2129
2130 rc = mwl8k_post_cmd(hw, &cmd->header);
2131 kfree(cmd);
2132
2133 return rc;
2134}
2135
a66098da
LB		 2136/*
2137 * CMD_MAC_MULTICAST_ADR.
2138 */
2139struct mwl8k_cmd_mac_multicast_adr {
2140 struct mwl8k_cmd_pkt header;
2141 __le16 action;
2142 __le16 numaddr;
ce9e2e1b 2143 __u8 addr[0][ETH_ALEN];
a66098da
LB		 2144};
2145
d5e30845
LB		 2146#define MWL8K_ENABLE_RX_DIRECTED 0x0001
2147#define MWL8K_ENABLE_RX_MULTICAST 0x0002
2148#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
2149#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 2150
e81cd2d6 2151static struct mwl8k_cmd_pkt *
447ced07 2152__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
22bedad3 2153 struct netdev_hw_addr_list *mc_list)
a66098da 2154{
e81cd2d6 2155 struct mwl8k_priv *priv = hw->priv;
a66098da 2156 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 2157 int size;
22bedad3
JP		 2158 int mc_count = 0;
2159
2160 if (mc_list)
2161 mc_count = netdev_hw_addr_list_count(mc_list);
e81cd2d6 2162
447ced07 2163 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 2164 allmulti = 1;
2165 mc_count = 0;
2166 }
e81cd2d6
LB		 2167
2168 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 2169
e81cd2d6 2170 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 2171 if (cmd == NULL)
e81cd2d6 2172 return NULL;
a66098da
LB		 2173
2174 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
2175 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 2176 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
2177 MWL8K_ENABLE_RX_BROADCAST);
2178
2179 if (allmulti) {
2180 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
2181 } else if (mc_count) {
22bedad3
JP		 2182 struct netdev_hw_addr *ha;
2183 int i = 0;
d5e30845
LB		 2184
2185 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
2186 cmd->numaddr = cpu_to_le16(mc_count);
22bedad3
JP		 2187 netdev_hw_addr_list_for_each(ha, mc_list) {
2188 memcpy(cmd->addr[i], ha->addr, ETH_ALEN);
a66098da 2189 }
a66098da
LB		 2190 }
2191
e81cd2d6 2192 return &cmd->header;
a66098da
LB		 2193}
2194
2195/*
55489b6e 2196 * CMD_GET_STAT.
a66098da 2197 */
55489b6e 2198struct mwl8k_cmd_get_stat {
a66098da 2199 struct mwl8k_cmd_pkt header;
a66098da 2200 __le32 stats[64];
ba2d3587 2201} __packed;
a66098da
LB		 2202
2203#define MWL8K_STAT_ACK_FAILURE 9
2204#define MWL8K_STAT_RTS_FAILURE 12
2205#define MWL8K_STAT_FCS_ERROR 24
2206#define MWL8K_STAT_RTS_SUCCESS 11
2207
55489b6e
LB		 2208static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
2209 struct ieee80211_low_level_stats *stats)
a66098da 2210{
55489b6e 2211 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 2212 int rc;
2213
2214 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2215 if (cmd == NULL)
2216 return -ENOMEM;
2217
2218 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
2219 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2220
2221 rc = mwl8k_post_cmd(hw, &cmd->header);
2222 if (!rc) {
2223 stats->dot11ACKFailureCount =
2224 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
2225 stats->dot11RTSFailureCount =
2226 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
2227 stats->dot11FCSErrorCount =
2228 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
2229 stats->dot11RTSSuccessCount =
2230 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
2231 }
2232 kfree(cmd);
2233
2234 return rc;
2235}
2236
2237/*
55489b6e 2238 * CMD_RADIO_CONTROL.
a66098da 2239 */
55489b6e 2240struct mwl8k_cmd_radio_control {
a66098da
LB		 2241 struct mwl8k_cmd_pkt header;
2242 __le16 action;
2243 __le16 control;
2244 __le16 radio_on;
ba2d3587 2245} __packed;
a66098da 2246
c46563b7 2247static int
55489b6e 2248mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 2249{
2250 struct mwl8k_priv *priv = hw->priv;
55489b6e 2251 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 2252 int rc;
2253
c46563b7 2254 if (enable == priv->radio_on && !force)
a66098da
LB		 2255 return 0;
2256
a66098da
LB		 2257 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2258 if (cmd == NULL)
2259 return -ENOMEM;
2260
2261 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
2262 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2263 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 2264 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 2265 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
2266
2267 rc = mwl8k_post_cmd(hw, &cmd->header);
2268 kfree(cmd);
2269
2270 if (!rc)
c46563b7 2271 priv->radio_on = enable;
a66098da
LB		 2272
2273 return rc;
2274}
2275
55489b6e 2276static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 2277{
55489b6e 2278 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 2279}
2280
55489b6e 2281static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 2282{
55489b6e 2283 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 2284}
2285
a66098da
LB		 2286static int
2287mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
2288{
99200a99 2289 struct mwl8k_priv *priv = hw->priv;
a66098da 2290
68ce3884 2291 priv->radio_short_preamble = short_preamble;
a66098da 2292
55489b6e 2293 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 2294}
2295
2296/*
55489b6e 2297 * CMD_RF_TX_POWER.
a66098da 2298 */
41fdf097 2299#define MWL8K_RF_TX_POWER_LEVEL_TOTAL 8
a66098da 2300
55489b6e 2301struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 2302 struct mwl8k_cmd_pkt header;
2303 __le16 action;
2304 __le16 support_level;
2305 __le16 current_level;
2306 __le16 reserved;
41fdf097 2307 __le16 power_level_list[MWL8K_RF_TX_POWER_LEVEL_TOTAL];
ba2d3587 2308} __packed;
a66098da 2309
55489b6e 2310static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 2311{
55489b6e 2312 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 2313 int rc;
2314
2315 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2316 if (cmd == NULL)
2317 return -ENOMEM;
2318
2319 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2320 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2321 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2322 cmd->support_level = cpu_to_le16(dBm);
2323
2324 rc = mwl8k_post_cmd(hw, &cmd->header);
2325 kfree(cmd);
2326
2327 return rc;
2328}
2329
41fdf097
NS		 2330/*
2331 * CMD_TX_POWER.
2332 */
2333#define MWL8K_TX_POWER_LEVEL_TOTAL 12
2334
2335struct mwl8k_cmd_tx_power {
2336 struct mwl8k_cmd_pkt header;
2337 __le16 action;
2338 __le16 band;
2339 __le16 channel;
2340 __le16 bw;
2341 __le16 sub_ch;
2342 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
2343} __attribute__((packed));
2344
2345static int mwl8k_cmd_tx_power(struct ieee80211_hw *hw,
2346 struct ieee80211_conf *conf,
2347 unsigned short pwr)
2348{
2349 struct ieee80211_channel *channel = conf->channel;
2350 struct mwl8k_cmd_tx_power *cmd;
2351 int rc;
2352 int i;
2353
2354 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2355 if (cmd == NULL)
2356 return -ENOMEM;
2357
2358 cmd->header.code = cpu_to_le16(MWL8K_CMD_TX_POWER);
2359 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2360 cmd->action = cpu_to_le16(MWL8K_CMD_SET_LIST);
2361
2362 if (channel->band == IEEE80211_BAND_2GHZ)
2363 cmd->band = cpu_to_le16(0x1);
2364 else if (channel->band == IEEE80211_BAND_5GHZ)
2365 cmd->band = cpu_to_le16(0x4);
2366
2367 cmd->channel = channel->hw_value;
2368
2369 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2370 conf->channel_type == NL80211_CHAN_HT20) {
2371 cmd->bw = cpu_to_le16(0x2);
2372 } else {
2373 cmd->bw = cpu_to_le16(0x4);
2374 if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2375 cmd->sub_ch = cpu_to_le16(0x3);
2376 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2377 cmd->sub_ch = cpu_to_le16(0x1);
2378 }
2379
2380 for (i = 0; i < MWL8K_TX_POWER_LEVEL_TOTAL; i++)
2381 cmd->power_level_list[i] = cpu_to_le16(pwr);
2382
2383 rc = mwl8k_post_cmd(hw, &cmd->header);
2384 kfree(cmd);
2385
2386 return rc;
2387}
2388
08b06347
LB		 2389/*
2390 * CMD_RF_ANTENNA.
2391 */
2392struct mwl8k_cmd_rf_antenna {
2393 struct mwl8k_cmd_pkt header;
2394 __le16 antenna;
2395 __le16 mode;
ba2d3587 2396} __packed;
08b06347
LB		 2397
2398#define MWL8K_RF_ANTENNA_RX 1
2399#define MWL8K_RF_ANTENNA_TX 2
2400
2401static int
2402mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2403{
2404 struct mwl8k_cmd_rf_antenna *cmd;
2405 int rc;
2406
2407 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2408 if (cmd == NULL)
2409 return -ENOMEM;
2410
2411 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2412 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2413 cmd->antenna = cpu_to_le16(antenna);
2414 cmd->mode = cpu_to_le16(mask);
2415
2416 rc = mwl8k_post_cmd(hw, &cmd->header);
2417 kfree(cmd);
2418
2419 return rc;
2420}
2421
b64fe619
LB		 2422/*
2423 * CMD_SET_BEACON.
2424 */
2425struct mwl8k_cmd_set_beacon {
2426 struct mwl8k_cmd_pkt header;
2427 __le16 beacon_len;
2428 __u8 beacon[0];
2429};
2430
aa21d0f6
LB		 2431static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw,
2432 struct ieee80211_vif *vif, u8 *beacon, int len)
b64fe619
LB		 2433{
2434 struct mwl8k_cmd_set_beacon *cmd;
2435 int rc;
2436
2437 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2438 if (cmd == NULL)
2439 return -ENOMEM;
2440
2441 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2442 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2443 cmd->beacon_len = cpu_to_le16(len);
2444 memcpy(cmd->beacon, beacon, len);
2445
aa21d0f6 2446 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 2447 kfree(cmd);
2448
2449 return rc;
2450}
2451
a66098da
LB		 2452/*
2453 * CMD_SET_PRE_SCAN.
2454 */
2455struct mwl8k_cmd_set_pre_scan {
2456 struct mwl8k_cmd_pkt header;
ba2d3587 2457} __packed;
a66098da
LB		 2458
2459static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2460{
2461 struct mwl8k_cmd_set_pre_scan *cmd;
2462 int rc;
2463
2464 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2465 if (cmd == NULL)
2466 return -ENOMEM;
2467
2468 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2469 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2470
2471 rc = mwl8k_post_cmd(hw, &cmd->header);
2472 kfree(cmd);
2473
2474 return rc;
2475}
2476
2477/*
2478 * CMD_SET_POST_SCAN.
2479 */
2480struct mwl8k_cmd_set_post_scan {
2481 struct mwl8k_cmd_pkt header;
2482 __le32 isibss;
d89173f2 2483 __u8 bssid[ETH_ALEN];
ba2d3587 2484} __packed;
a66098da
LB		 2485
2486static int
0a11dfc3 2487mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 2488{
2489 struct mwl8k_cmd_set_post_scan *cmd;
2490 int rc;
2491
2492 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2493 if (cmd == NULL)
2494 return -ENOMEM;
2495
2496 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2497 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2498 cmd->isibss = 0;
d89173f2 2499 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2500
2501 rc = mwl8k_post_cmd(hw, &cmd->header);
2502 kfree(cmd);
2503
2504 return rc;
2505}
2506
2507/*
2508 * CMD_SET_RF_CHANNEL.
2509 */
2510struct mwl8k_cmd_set_rf_channel {
2511 struct mwl8k_cmd_pkt header;
2512 __le16 action;
2513 __u8 current_channel;
2514 __le32 channel_flags;
ba2d3587 2515} __packed;
a66098da
LB		 2516
2517static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 2518 struct ieee80211_conf *conf)
a66098da 2519{
610677d2 2520 struct ieee80211_channel *channel = conf->channel;
a66098da
LB		 2521 struct mwl8k_cmd_set_rf_channel *cmd;
2522 int rc;
2523
2524 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2525 if (cmd == NULL)
2526 return -ENOMEM;
2527
2528 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2529 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2530 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2531 cmd->current_channel = channel->hw_value;
610677d2 2532
a66098da 2533 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2 2534 cmd->channel_flags |= cpu_to_le32(0x00000001);
42574ea2
LB		 2535 else if (channel->band == IEEE80211_BAND_5GHZ)
2536 cmd->channel_flags |= cpu_to_le32(0x00000004);
610677d2
LB		 2537
2538 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2539 conf->channel_type == NL80211_CHAN_HT20)
2540 cmd->channel_flags |= cpu_to_le32(0x00000080);
2541 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2542 cmd->channel_flags |= cpu_to_le32(0x000001900);
2543 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2544 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB		 2545
2546 rc = mwl8k_post_cmd(hw, &cmd->header);
2547 kfree(cmd);
2548
2549 return rc;
2550}
2551
2552/*
55489b6e 2553 * CMD_SET_AID.
a66098da 2554 */
55489b6e
LB		 2555#define MWL8K_FRAME_PROT_DISABLED 0x00
2556#define MWL8K_FRAME_PROT_11G 0x07
2557#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2558#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2559
55489b6e
LB		 2560struct mwl8k_cmd_update_set_aid {
2561 struct mwl8k_cmd_pkt header;
2562 __le16 aid;
a66098da 2563
55489b6e
LB		 2564 /* AP's MAC address (BSSID) */
2565 __u8 bssid[ETH_ALEN];
2566 __le16 protection_mode;
2567 __u8 supp_rates[14];
ba2d3587 2568} __packed;
a66098da 2569
c6e96010
LB		 2570static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
2571{
2572 int i;
2573 int j;
2574
2575 /*
2576 * Clear nonstandard rates 4 and 13.
2577 */
2578 mask &= 0x1fef;
2579
2580 for (i = 0, j = 0; i < 14; i++) {
2581 if (mask & (1 << i))
777ad375 2582 rates[j++] = mwl8k_rates_24[i].hw_value;
c6e96010
LB		 2583 }
2584}
2585
55489b6e 2586static int
c6e96010
LB		 2587mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2588 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 2589{
55489b6e
LB		 2590 struct mwl8k_cmd_update_set_aid *cmd;
2591 u16 prot_mode;
a66098da
LB		 2592 int rc;
2593
2594 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2595 if (cmd == NULL)
2596 return -ENOMEM;
2597
55489b6e 2598 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2599 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2600 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 2601 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2602
7dc6a7a7 2603 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 2604 prot_mode = MWL8K_FRAME_PROT_11G;
2605 } else {
7dc6a7a7 2606 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 2607 IEEE80211_HT_OP_MODE_PROTECTION) {
2608 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2609 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2610 break;
2611 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2612 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2613 break;
2614 default:
2615 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2616 break;
2617 }
2618 }
2619 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2620
c6e96010 2621 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 2622
2623 rc = mwl8k_post_cmd(hw, &cmd->header);
2624 kfree(cmd);
2625
2626 return rc;
2627}
2628
32060e1b 2629/*
55489b6e 2630 * CMD_SET_RATE.
32060e1b 2631 */
55489b6e
LB		 2632struct mwl8k_cmd_set_rate {
2633 struct mwl8k_cmd_pkt header;
2634 __u8 legacy_rates[14];
2635
2636 /* Bitmap for supported MCS codes. */
2637 __u8 mcs_set[16];
2638 __u8 reserved[16];
ba2d3587 2639} __packed;
32060e1b 2640
55489b6e 2641static int
c6e96010 2642mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 2643 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 2644{
55489b6e 2645 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 2646 int rc;
2647
2648 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2649 if (cmd == NULL)
2650 return -ENOMEM;
2651
55489b6e 2652 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 2653 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 2654 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 2655 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB		 2656
2657 rc = mwl8k_post_cmd(hw, &cmd->header);
2658 kfree(cmd);
2659
2660 return rc;
2661}
2662
a66098da 2663/*
55489b6e 2664 * CMD_FINALIZE_JOIN.
a66098da 2665 */
55489b6e
LB		 2666#define MWL8K_FJ_BEACON_MAXLEN 128
2667
2668struct mwl8k_cmd_finalize_join {
a66098da 2669 struct mwl8k_cmd_pkt header;
55489b6e
LB		 2670 __le32 sleep_interval; /* Number of beacon periods to sleep */
2671 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
ba2d3587 2672} __packed;
a66098da 2673
55489b6e
LB		 2674static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2675 int framelen, int dtim)
a66098da 2676{
55489b6e
LB		 2677 struct mwl8k_cmd_finalize_join *cmd;
2678 struct ieee80211_mgmt *payload = frame;
2679 int payload_len;
a66098da
LB		 2680 int rc;
2681
2682 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2683 if (cmd == NULL)
2684 return -ENOMEM;
2685
55489b6e 2686 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 2687 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2688 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2689
2690 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2691 if (payload_len < 0)
2692 payload_len = 0;
2693 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2694 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2695
2696 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 2697
2698 rc = mwl8k_post_cmd(hw, &cmd->header);
2699 kfree(cmd);
2700
2701 return rc;
2702}
2703
2704/*
55489b6e 2705 * CMD_SET_RTS_THRESHOLD.
a66098da 2706 */
55489b6e 2707struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 2708 struct mwl8k_cmd_pkt header;
2709 __le16 action;
55489b6e 2710 __le16 threshold;
ba2d3587 2711} __packed;
a66098da 2712
c2c2b12a
LB		 2713static int
2714mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 2715{
55489b6e 2716 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 2717 int rc;
2718
2719 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2720 if (cmd == NULL)
2721 return -ENOMEM;
2722
55489b6e 2723 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 2724 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB		 2725 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2726 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB		 2727
2728 rc = mwl8k_post_cmd(hw, &cmd->header);
2729 kfree(cmd);
2730
a66098da
LB		 2731 return rc;
2732}
2733
2734/*
55489b6e 2735 * CMD_SET_SLOT.
a66098da 2736 */
55489b6e 2737struct mwl8k_cmd_set_slot {
a66098da
LB		 2738 struct mwl8k_cmd_pkt header;
2739 __le16 action;
55489b6e 2740 __u8 short_slot;
ba2d3587 2741} __packed;
a66098da 2742
55489b6e 2743static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 2744{
55489b6e 2745 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 2746 int rc;
2747
2748 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2749 if (cmd == NULL)
2750 return -ENOMEM;
2751
55489b6e 2752 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 2753 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2754 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2755 cmd->short_slot = short_slot_time;
a66098da
LB		 2756
2757 rc = mwl8k_post_cmd(hw, &cmd->header);
2758 kfree(cmd);
2759
2760 return rc;
2761}
2762
2763/*
2764 * CMD_SET_EDCA_PARAMS.
2765 */
2766struct mwl8k_cmd_set_edca_params {
2767 struct mwl8k_cmd_pkt header;
2768
2769 /* See MWL8K_SET_EDCA_XXX below */
2770 __le16 action;
2771
2772 /* TX opportunity in units of 32 us */
2773 __le16 txop;
2774
2e484c89
LB		 2775 union {
2776 struct {
2777 /* Log exponent of max contention period: 0...15 */
2778 __le32 log_cw_max;
2779
2780 /* Log exponent of min contention period: 0...15 */
2781 __le32 log_cw_min;
2782
2783 /* Adaptive interframe spacing in units of 32us */
2784 __u8 aifs;
2785
2786 /* TX queue to configure */
2787 __u8 txq;
2788 } ap;
2789 struct {
2790 /* Log exponent of max contention period: 0...15 */
2791 __u8 log_cw_max;
a66098da 2792
2e484c89
LB		 2793 /* Log exponent of min contention period: 0...15 */
2794 __u8 log_cw_min;
a66098da 2795
2e484c89
LB		 2796 /* Adaptive interframe spacing in units of 32us */
2797 __u8 aifs;
a66098da 2798
2e484c89
LB		 2799 /* TX queue to configure */
2800 __u8 txq;
2801 } sta;
2802 };
ba2d3587 2803} __packed;
a66098da 2804
a66098da
LB		 2805#define MWL8K_SET_EDCA_CW 0x01
2806#define MWL8K_SET_EDCA_TXOP 0x02
2807#define MWL8K_SET_EDCA_AIFS 0x04
2808
2809#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2810 MWL8K_SET_EDCA_TXOP | \
2811 MWL8K_SET_EDCA_AIFS)
2812
2813static int
55489b6e
LB		 2814mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2815 __u16 cw_min, __u16 cw_max,
2816 __u8 aifs, __u16 txop)
a66098da 2817{
2e484c89 2818 struct mwl8k_priv *priv = hw->priv;
a66098da 2819 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2820 int rc;
2821
2822 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2823 if (cmd == NULL)
2824 return -ENOMEM;
2825
a66098da
LB		 2826 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2827 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2828 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2829 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2830 if (priv->ap_fw) {
2831 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2832 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2833 cmd->ap.aifs = aifs;
2834 cmd->ap.txq = qnum;
2835 } else {
2836 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2837 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2838 cmd->sta.aifs = aifs;
2839 cmd->sta.txq = qnum;
2840 }
a66098da
LB		 2841
2842 rc = mwl8k_post_cmd(hw, &cmd->header);
2843 kfree(cmd);
2844
2845 return rc;
2846}
2847
2848/*
55489b6e 2849 * CMD_SET_WMM_MODE.
a66098da 2850 */
55489b6e 2851struct mwl8k_cmd_set_wmm_mode {
a66098da 2852 struct mwl8k_cmd_pkt header;
55489b6e 2853 __le16 action;
ba2d3587 2854} __packed;
a66098da 2855
55489b6e 2856static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 2857{
55489b6e
LB		 2858 struct mwl8k_priv *priv = hw->priv;
2859 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 2860 int rc;
2861
a66098da
LB		 2862 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2863 if (cmd == NULL)
2864 return -ENOMEM;
2865
55489b6e 2866 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 2867 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 2868 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2869
2870 rc = mwl8k_post_cmd(hw, &cmd->header);
2871 kfree(cmd);
16cec43d 2872
55489b6e
LB		 2873 if (!rc)
2874 priv->wmm_enabled = enable;
a66098da
LB		 2875
2876 return rc;
2877}
2878
2879/*
55489b6e 2880 * CMD_MIMO_CONFIG.
a66098da 2881 */
55489b6e
LB		 2882struct mwl8k_cmd_mimo_config {
2883 struct mwl8k_cmd_pkt header;
2884 __le32 action;
2885 __u8 rx_antenna_map;
2886 __u8 tx_antenna_map;
ba2d3587 2887} __packed;
a66098da 2888
55489b6e 2889static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 2890{
55489b6e 2891 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 2892 int rc;
2893
2894 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2895 if (cmd == NULL)
2896 return -ENOMEM;
2897
55489b6e 2898 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 2899 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2900 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2901 cmd->rx_antenna_map = rx;
2902 cmd->tx_antenna_map = tx;
a66098da
LB		 2903
2904 rc = mwl8k_post_cmd(hw, &cmd->header);
2905 kfree(cmd);
2906
2907 return rc;
2908}
2909
2910/*
b71ed2c6 2911 * CMD_USE_FIXED_RATE (STA version).
a66098da 2912 */
b71ed2c6
LB		 2913struct mwl8k_cmd_use_fixed_rate_sta {
2914 struct mwl8k_cmd_pkt header;
2915 __le32 action;
2916 __le32 allow_rate_drop;
2917 __le32 num_rates;
2918 struct {
2919 __le32 is_ht_rate;
2920 __le32 enable_retry;
2921 __le32 rate;
2922 __le32 retry_count;
2923 } rate_entry[8];
2924 __le32 rate_type;
2925 __le32 reserved1;
2926 __le32 reserved2;
ba2d3587 2927} __packed;
a66098da 2928
b71ed2c6
LB		 2929#define MWL8K_USE_AUTO_RATE 0x0002
2930#define MWL8K_UCAST_RATE 0
a66098da 2931
b71ed2c6 2932static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 2933{
b71ed2c6 2934 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB		 2935 int rc;
2936
2937 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2938 if (cmd == NULL)
2939 return -ENOMEM;
2940
2941 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2942 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB		 2943 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2944 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB		 2945
2946 rc = mwl8k_post_cmd(hw, &cmd->header);
2947 kfree(cmd);
2948
2949 return rc;
2950}
2951
088aab8b
LB		 2952/*
2953 * CMD_USE_FIXED_RATE (AP version).
2954 */
2955struct mwl8k_cmd_use_fixed_rate_ap {
2956 struct mwl8k_cmd_pkt header;
2957 __le32 action;
2958 __le32 allow_rate_drop;
2959 __le32 num_rates;
2960 struct mwl8k_rate_entry_ap {
2961 __le32 is_ht_rate;
2962 __le32 enable_retry;
2963 __le32 rate;
2964 __le32 retry_count;
2965 } rate_entry[4];
2966 u8 multicast_rate;
2967 u8 multicast_rate_type;
2968 u8 management_rate;
ba2d3587 2969} __packed;
088aab8b
LB		 2970
2971static int
2972mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
2973{
2974 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
2975 int rc;
2976
2977 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2978 if (cmd == NULL)
2979 return -ENOMEM;
2980
2981 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2982 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2983 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2984 cmd->multicast_rate = mcast;
2985 cmd->management_rate = mgmt;
2986
2987 rc = mwl8k_post_cmd(hw, &cmd->header);
2988 kfree(cmd);
2989
2990 return rc;
2991}
2992
55489b6e
LB		 2993/*
2994 * CMD_ENABLE_SNIFFER.
2995 */
2996struct mwl8k_cmd_enable_sniffer {
2997 struct mwl8k_cmd_pkt header;
2998 __le32 action;
ba2d3587 2999} __packed;
55489b6e
LB		 3000
3001static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
3002{
3003 struct mwl8k_cmd_enable_sniffer *cmd;
3004 int rc;
3005
3006 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3007 if (cmd == NULL)
3008 return -ENOMEM;
3009
3010 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
3011 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3012 cmd->action = cpu_to_le32(!!enable);
3013
3014 rc = mwl8k_post_cmd(hw, &cmd->header);
3015 kfree(cmd);
3016
3017 return rc;
3018}
3019
3020/*
3021 * CMD_SET_MAC_ADDR.
3022 */
3023struct mwl8k_cmd_set_mac_addr {
3024 struct mwl8k_cmd_pkt header;
3025 union {
3026 struct {
3027 __le16 mac_type;
3028 __u8 mac_addr[ETH_ALEN];
3029 } mbss;
3030 __u8 mac_addr[ETH_ALEN];
3031 };
ba2d3587 3032} __packed;
55489b6e 3033
ee0ddf18
LB		 3034#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
3035#define MWL8K_MAC_TYPE_SECONDARY_CLIENT 1
3036#define MWL8K_MAC_TYPE_PRIMARY_AP 2
3037#define MWL8K_MAC_TYPE_SECONDARY_AP 3
a9e00b15 3038
aa21d0f6
LB		 3039static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw,
3040 struct ieee80211_vif *vif, u8 *mac)
55489b6e
LB		 3041{
3042 struct mwl8k_priv *priv = hw->priv;
ee0ddf18 3043 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
55489b6e 3044 struct mwl8k_cmd_set_mac_addr *cmd;
ee0ddf18 3045 int mac_type;
55489b6e
LB		 3046 int rc;
3047
ee0ddf18
LB		 3048 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3049 if (vif != NULL && vif->type == NL80211_IFTYPE_STATION) {
3050 if (mwl8k_vif->macid + 1 == ffs(priv->sta_macids_supported))
3051 mac_type = MWL8K_MAC_TYPE_PRIMARY_CLIENT;
3052 else
3053 mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3054 } else if (vif != NULL && vif->type == NL80211_IFTYPE_AP) {
3055 if (mwl8k_vif->macid + 1 == ffs(priv->ap_macids_supported))
3056 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3057 else
3058 mac_type = MWL8K_MAC_TYPE_SECONDARY_AP;
3059 }
3060
55489b6e
LB		 3061 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3062 if (cmd == NULL)
3063 return -ENOMEM;
3064
3065 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
3066 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3067 if (priv->ap_fw) {
ee0ddf18 3068 cmd->mbss.mac_type = cpu_to_le16(mac_type);
55489b6e
LB		 3069 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
3070 } else {
3071 memcpy(cmd->mac_addr, mac, ETH_ALEN);
3072 }
3073
aa21d0f6 3074 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
55489b6e
LB		 3075 kfree(cmd);
3076
3077 return rc;
3078}
3079
3080/*
3081 * CMD_SET_RATEADAPT_MODE.
3082 */
3083struct mwl8k_cmd_set_rate_adapt_mode {
3084 struct mwl8k_cmd_pkt header;
3085 __le16 action;
3086 __le16 mode;
ba2d3587 3087} __packed;
55489b6e
LB		 3088
3089static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
3090{
3091 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
3092 int rc;
3093
3094 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3095 if (cmd == NULL)
3096 return -ENOMEM;
3097
3098 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
3099 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3100 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3101 cmd->mode = cpu_to_le16(mode);
3102
3103 rc = mwl8k_post_cmd(hw, &cmd->header);
3104 kfree(cmd);
3105
3106 return rc;
3107}
3108
b64fe619
LB		 3109/*
3110 * CMD_BSS_START.
3111 */
3112struct mwl8k_cmd_bss_start {
3113 struct mwl8k_cmd_pkt header;
3114 __le32 enable;
ba2d3587 3115} __packed;
b64fe619 3116
aa21d0f6
LB		 3117static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw,
3118 struct ieee80211_vif *vif, int enable)
b64fe619
LB		 3119{
3120 struct mwl8k_cmd_bss_start *cmd;
3121 int rc;
3122
3123 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3124 if (cmd == NULL)
3125 return -ENOMEM;
3126
3127 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
3128 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3129 cmd->enable = cpu_to_le32(enable);
3130
aa21d0f6 3131 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 3132 kfree(cmd);
3133
3134 return rc;
3135}
3136
3f5610ff
LB		 3137/*
3138 * CMD_SET_NEW_STN.
3139 */
3140struct mwl8k_cmd_set_new_stn {
3141 struct mwl8k_cmd_pkt header;
3142 __le16 aid;
3143 __u8 mac_addr[6];
3144 __le16 stn_id;
3145 __le16 action;
3146 __le16 rsvd;
3147 __le32 legacy_rates;
3148 __u8 ht_rates[4];
3149 __le16 cap_info;
3150 __le16 ht_capabilities_info;
3151 __u8 mac_ht_param_info;
3152 __u8 rev;
3153 __u8 control_channel;
3154 __u8 add_channel;
3155 __le16 op_mode;
3156 __le16 stbc;
3157 __u8 add_qos_info;
3158 __u8 is_qos_sta;
3159 __le32 fw_sta_ptr;
ba2d3587 3160} __packed;
3f5610ff
LB		 3161
3162#define MWL8K_STA_ACTION_ADD 0
3163#define MWL8K_STA_ACTION_REMOVE 2
3164
3165static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
3166 struct ieee80211_vif *vif,
3167 struct ieee80211_sta *sta)
3168{
3169 struct mwl8k_cmd_set_new_stn *cmd;
8707d026 3170 u32 rates;
3f5610ff
LB		 3171 int rc;
3172
3173 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3174 if (cmd == NULL)
3175 return -ENOMEM;
3176
3177 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3178 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3179 cmd->aid = cpu_to_le16(sta->aid);
3180 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
3181 cmd->stn_id = cpu_to_le16(sta->aid);
3182 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
8707d026
LB		 3183 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3184 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
3185 else
3186 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3187 cmd->legacy_rates = cpu_to_le32(rates);
3f5610ff
LB		 3188 if (sta->ht_cap.ht_supported) {
3189 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
3190 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
3191 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
3192 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
3193 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
3194 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
3195 ((sta->ht_cap.ampdu_density & 7) << 2);
3196 cmd->is_qos_sta = 1;
3197 }
3198
aa21d0f6 3199 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 3200 kfree(cmd);
3201
3202 return rc;
3203}
3204
b64fe619
LB		 3205static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
3206 struct ieee80211_vif *vif)
3207{
3208 struct mwl8k_cmd_set_new_stn *cmd;
3209 int rc;
3210
3211 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3212 if (cmd == NULL)
3213 return -ENOMEM;
3214
3215 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3216 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3217 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
3218
aa21d0f6 3219 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 3220 kfree(cmd);
3221
3222 return rc;
3223}
3224
3f5610ff
LB		 3225static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
3226 struct ieee80211_vif *vif, u8 *addr)
3227{
3228 struct mwl8k_cmd_set_new_stn *cmd;
3229 int rc;
3230
3231 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3232 if (cmd == NULL)
3233 return -ENOMEM;
3234
3235 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3236 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3237 memcpy(cmd->mac_addr, addr, ETH_ALEN);
3238 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
3239
aa21d0f6 3240 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 3241 kfree(cmd);
3242
3243 return rc;
3244}
3245
fcdc403c
NS		 3246/*
3247 * CMD_UPDATE_ENCRYPTION.
3248 */
3249
3250#define MAX_ENCR_KEY_LENGTH 16
3251#define MIC_KEY_LENGTH 8
3252
3253struct mwl8k_cmd_update_encryption {
3254 struct mwl8k_cmd_pkt header;
3255
3256 __le32 action;
3257 __le32 reserved;
3258 __u8 mac_addr[6];
3259 __u8 encr_type;
3260
3261} __attribute__((packed));
3262
3263struct mwl8k_cmd_set_key {
3264 struct mwl8k_cmd_pkt header;
3265
3266 __le32 action;
3267 __le32 reserved;
3268 __le16 length;
3269 __le16 key_type_id;
3270 __le32 key_info;
3271 __le32 key_id;
3272 __le16 key_len;
3273 __u8 key_material[MAX_ENCR_KEY_LENGTH];
3274 __u8 tkip_tx_mic_key[MIC_KEY_LENGTH];
3275 __u8 tkip_rx_mic_key[MIC_KEY_LENGTH];
3276 __le16 tkip_rsc_low;
3277 __le32 tkip_rsc_high;
3278 __le16 tkip_tsc_low;
3279 __le32 tkip_tsc_high;
3280 __u8 mac_addr[6];
3281} __attribute__((packed));
3282
3283enum {
3284 MWL8K_ENCR_ENABLE,
3285 MWL8K_ENCR_SET_KEY,
3286 MWL8K_ENCR_REMOVE_KEY,
3287 MWL8K_ENCR_SET_GROUP_KEY,
3288};
3289
3290#define MWL8K_UPDATE_ENCRYPTION_TYPE_WEP 0
3291#define MWL8K_UPDATE_ENCRYPTION_TYPE_DISABLE 1
3292#define MWL8K_UPDATE_ENCRYPTION_TYPE_TKIP 4
3293#define MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED 7
3294#define MWL8K_UPDATE_ENCRYPTION_TYPE_AES 8
3295
3296enum {
3297 MWL8K_ALG_WEP,
3298 MWL8K_ALG_TKIP,
3299 MWL8K_ALG_CCMP,
3300};
3301
3302#define MWL8K_KEY_FLAG_TXGROUPKEY 0x00000004
3303#define MWL8K_KEY_FLAG_PAIRWISE 0x00000008
3304#define MWL8K_KEY_FLAG_TSC_VALID 0x00000040
3305#define MWL8K_KEY_FLAG_WEP_TXKEY 0x01000000
3306#define MWL8K_KEY_FLAG_MICKEY_VALID 0x02000000
3307
3308static int mwl8k_cmd_update_encryption_enable(struct ieee80211_hw *hw,
3309 struct ieee80211_vif *vif,
3310 u8 *addr,
3311 u8 encr_type)
3312{
3313 struct mwl8k_cmd_update_encryption *cmd;
3314 int rc;
3315
3316 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3317 if (cmd == NULL)
3318 return -ENOMEM;
3319
3320 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
3321 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3322 cmd->action = cpu_to_le32(MWL8K_ENCR_ENABLE);
3323 memcpy(cmd->mac_addr, addr, ETH_ALEN);
3324 cmd->encr_type = encr_type;
3325
3326 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3327 kfree(cmd);
3328
3329 return rc;
3330}
3331
3332static int mwl8k_encryption_set_cmd_info(struct mwl8k_cmd_set_key *cmd,
3333 u8 *addr,
3334 struct ieee80211_key_conf *key)
3335{
3336 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
3337 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3338 cmd->length = cpu_to_le16(sizeof(*cmd) -
3339 offsetof(struct mwl8k_cmd_set_key, length));
3340 cmd->key_id = cpu_to_le32(key->keyidx);
3341 cmd->key_len = cpu_to_le16(key->keylen);
3342 memcpy(cmd->mac_addr, addr, ETH_ALEN);
3343
3344 switch (key->cipher) {
3345 case WLAN_CIPHER_SUITE_WEP40:
3346 case WLAN_CIPHER_SUITE_WEP104:
3347 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_WEP);
3348 if (key->keyidx == 0)
3349 cmd->key_info = cpu_to_le32(MWL8K_KEY_FLAG_WEP_TXKEY);
3350
3351 break;
3352 case WLAN_CIPHER_SUITE_TKIP:
3353 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_TKIP);
3354 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
3355 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
3356 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
3357 cmd->key_info |= cpu_to_le32(MWL8K_KEY_FLAG_MICKEY_VALID
3358 | MWL8K_KEY_FLAG_TSC_VALID);
3359 break;
3360 case WLAN_CIPHER_SUITE_CCMP:
3361 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_CCMP);
3362 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
3363 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
3364 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
3365 break;
3366 default:
3367 return -ENOTSUPP;
3368 }
3369
3370 return 0;
3371}
3372
3373static int mwl8k_cmd_encryption_set_key(struct ieee80211_hw *hw,
3374 struct ieee80211_vif *vif,
3375 u8 *addr,
3376 struct ieee80211_key_conf *key)
3377{
3378 struct mwl8k_cmd_set_key *cmd;
3379 int rc;
3380 int keymlen;
3381 u32 action;
3382 u8 idx;
3383 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3384
3385 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3386 if (cmd == NULL)
3387 return -ENOMEM;
3388
3389 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
3390 if (rc < 0)
3391 goto done;
3392
3393 idx = key->keyidx;
3394
3395 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
3396 action = MWL8K_ENCR_SET_KEY;
3397 else
3398 action = MWL8K_ENCR_SET_GROUP_KEY;
3399
3400 switch (key->cipher) {
3401 case WLAN_CIPHER_SUITE_WEP40:
3402 case WLAN_CIPHER_SUITE_WEP104:
3403 if (!mwl8k_vif->wep_key_conf[idx].enabled) {
3404 memcpy(mwl8k_vif->wep_key_conf[idx].key, key,
3405 sizeof(*key) + key->keylen);
3406 mwl8k_vif->wep_key_conf[idx].enabled = 1;
3407 }
3408
3409 keymlen = 0;
3410 action = MWL8K_ENCR_SET_KEY;
3411 break;
3412 case WLAN_CIPHER_SUITE_TKIP:
3413 keymlen = MAX_ENCR_KEY_LENGTH + 2 * MIC_KEY_LENGTH;
3414 break;
3415 case WLAN_CIPHER_SUITE_CCMP:
3416 keymlen = key->keylen;
3417 break;
3418 default:
3419 rc = -ENOTSUPP;
3420 goto done;
3421 }
3422
3423 memcpy(cmd->key_material, key->key, keymlen);
3424 cmd->action = cpu_to_le32(action);
3425
3426 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3427done:
3428 kfree(cmd);
3429
3430 return rc;
3431}
3432
3433static int mwl8k_cmd_encryption_remove_key(struct ieee80211_hw *hw,
3434 struct ieee80211_vif *vif,
3435 u8 *addr,
3436 struct ieee80211_key_conf *key)
3437{
3438 struct mwl8k_cmd_set_key *cmd;
3439 int rc;
3440 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3441
3442 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3443 if (cmd == NULL)
3444 return -ENOMEM;
3445
3446 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
3447 if (rc < 0)
3448 goto done;
3449
3450 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3451 WLAN_CIPHER_SUITE_WEP104)
3452 mwl8k_vif->wep_key_conf[key->keyidx].enabled = 0;
3453
3454 cmd->action = cpu_to_le32(MWL8K_ENCR_REMOVE_KEY);
3455
3456 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3457done:
3458 kfree(cmd);
3459
3460 return rc;
3461}
3462
3463static int mwl8k_set_key(struct ieee80211_hw *hw,
3464 enum set_key_cmd cmd_param,
3465 struct ieee80211_vif *vif,
3466 struct ieee80211_sta *sta,
3467 struct ieee80211_key_conf *key)
3468{
3469 int rc = 0;
3470 u8 encr_type;
3471 u8 *addr;
3472 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3473
3474 if (vif->type == NL80211_IFTYPE_STATION)
3475 return -EOPNOTSUPP;
3476
3477 if (sta == NULL)
3478 addr = hw->wiphy->perm_addr;
3479 else
3480 addr = sta->addr;
3481
3482 if (cmd_param == SET_KEY) {
3483 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3484 rc = mwl8k_cmd_encryption_set_key(hw, vif, addr, key);
3485 if (rc)
3486 goto out;
3487
3488 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40)
3489 || (key->cipher == WLAN_CIPHER_SUITE_WEP104))
3490 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_WEP;
3491 else
3492 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED;
3493
3494 rc = mwl8k_cmd_update_encryption_enable(hw, vif, addr,
3495 encr_type);
3496 if (rc)
3497 goto out;
3498
3499 mwl8k_vif->is_hw_crypto_enabled = true;
3500
3501 } else {
3502 rc = mwl8k_cmd_encryption_remove_key(hw, vif, addr, key);
3503
3504 if (rc)
3505 goto out;
3506
3507 mwl8k_vif->is_hw_crypto_enabled = false;
3508
3509 }
3510out:
3511 return rc;
3512}
3513
55489b6e
LB		 3514/*
3515 * CMD_UPDATE_STADB.
3516 */
25d81b1e
LB		 3517struct ewc_ht_info {
3518 __le16 control1;
3519 __le16 control2;
3520 __le16 control3;
ba2d3587 3521} __packed;
25d81b1e
LB		 3522
3523struct peer_capability_info {
3524 /* Peer type - AP vs. STA. */
3525 __u8 peer_type;
3526
3527 /* Basic 802.11 capabilities from assoc resp. */
3528 __le16 basic_caps;
3529
3530 /* Set if peer supports 802.11n high throughput (HT). */
3531 __u8 ht_support;
3532
3533 /* Valid if HT is supported. */
3534 __le16 ht_caps;
3535 __u8 extended_ht_caps;
3536 struct ewc_ht_info ewc_info;
3537
3538 /* Legacy rate table. Intersection of our rates and peer rates. */
3539 __u8 legacy_rates[12];
3540
3541 /* HT rate table. Intersection of our rates and peer rates. */
3542 __u8 ht_rates[16];
3543 __u8 pad[16];
3544
3545 /* If set, interoperability mode, no proprietary extensions. */
3546 __u8 interop;
3547 __u8 pad2;
3548 __u8 station_id;
3549 __le16 amsdu_enabled;
ba2d3587 3550} __packed;
25d81b1e 3551
55489b6e
LB		 3552struct mwl8k_cmd_update_stadb {
3553 struct mwl8k_cmd_pkt header;
3554
3555 /* See STADB_ACTION_TYPE */
3556 __le32 action;
3557
3558 /* Peer MAC address */
3559 __u8 peer_addr[ETH_ALEN];
3560
3561 __le32 reserved;
3562
3563 /* Peer info - valid during add/update. */
3564 struct peer_capability_info peer_info;
ba2d3587 3565} __packed;
55489b6e 3566
a680400e
LB		 3567#define MWL8K_STA_DB_MODIFY_ENTRY 1
3568#define MWL8K_STA_DB_DEL_ENTRY 2
3569
3570/* Peer Entry flags - used to define the type of the peer node */
3571#define MWL8K_PEER_TYPE_ACCESSPOINT 2
3572
3573static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 3574 struct ieee80211_vif *vif,
13935e2c 3575 struct ieee80211_sta *sta)
55489b6e 3576{
55489b6e 3577 struct mwl8k_cmd_update_stadb *cmd;
a680400e 3578 struct peer_capability_info *p;
8707d026 3579 u32 rates;
55489b6e
LB		 3580 int rc;
3581
3582 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3583 if (cmd == NULL)
3584 return -ENOMEM;
3585
3586 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
3587 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 3588 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 3589 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 3590
a680400e
LB		 3591 p = &cmd->peer_info;
3592 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
3593 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c 3594 p->ht_support = sta->ht_cap.ht_supported;
b603742f 3595 p->ht_caps = cpu_to_le16(sta->ht_cap.cap);
13935e2c
LB		 3596 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
3597 ((sta->ht_cap.ampdu_density & 7) << 2);
8707d026
LB		 3598 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3599 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
3600 else
3601 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3602 legacy_rate_mask_to_array(p->legacy_rates, rates);
13935e2c 3603 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB		 3604 p->interop = 1;
3605 p->amsdu_enabled = 0;
3606
3607 rc = mwl8k_post_cmd(hw, &cmd->header);
3608 kfree(cmd);
3609
3610 return rc ? rc : p->station_id;
3611}
3612
3613static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
3614 struct ieee80211_vif *vif, u8 *addr)
3615{
3616 struct mwl8k_cmd_update_stadb *cmd;
3617 int rc;
3618
3619 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3620 if (cmd == NULL)
3621 return -ENOMEM;
3622
3623 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
3624 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3625 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 3626 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 3627
a680400e 3628 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 3629 kfree(cmd);
3630
3631 return rc;
3632}
3633
a66098da
LB		 3634
3635/*
3636 * Interrupt handling.
3637 */
3638static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
3639{
3640 struct ieee80211_hw *hw = dev_id;
3641 struct mwl8k_priv *priv = hw->priv;
3642 u32 status;
3643
3644 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB		 3645 if (!status)
3646 return IRQ_NONE;
3647
1e9f9de3
LB		 3648 if (status & MWL8K_A2H_INT_TX_DONE) {
3649 status &= ~MWL8K_A2H_INT_TX_DONE;
3650 tasklet_schedule(&priv->poll_tx_task);
3651 }
3652
a66098da 3653 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB		 3654 status &= ~MWL8K_A2H_INT_RX_READY;
3655 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB		 3656 }
3657
67e2eb27
LB		 3658 if (status)
3659 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3660
a66098da 3661 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 3662 if (priv->hostcmd_wait != NULL)
a66098da 3663 complete(priv->hostcmd_wait);
a66098da
LB		 3664 }
3665
3666 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 3667 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 3668 priv->radio_on && priv->pending_tx_pkts)
618952a7 3669 mwl8k_tx_start(priv);
a66098da
LB		 3670 }
3671
3672 return IRQ_HANDLED;
3673}
3674
1e9f9de3
LB		 3675static void mwl8k_tx_poll(unsigned long data)
3676{
3677 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3678 struct mwl8k_priv *priv = hw->priv;
3679 int limit;
3680 int i;
3681
3682 limit = 32;
3683
3684 spin_lock_bh(&priv->tx_lock);
3685
3686 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3687 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
3688
3689 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
3690 complete(priv->tx_wait);
3691 priv->tx_wait = NULL;
3692 }
3693
3694 spin_unlock_bh(&priv->tx_lock);
3695
3696 if (limit) {
3697 writel(~MWL8K_A2H_INT_TX_DONE,
3698 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3699 } else {
3700 tasklet_schedule(&priv->poll_tx_task);
3701 }
3702}
3703
67e2eb27
LB		 3704static void mwl8k_rx_poll(unsigned long data)
3705{
3706 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3707 struct mwl8k_priv *priv = hw->priv;
3708 int limit;
3709
3710 limit = 32;
3711 limit -= rxq_process(hw, 0, limit);
3712 limit -= rxq_refill(hw, 0, limit);
3713
3714 if (limit) {
3715 writel(~MWL8K_A2H_INT_RX_READY,
3716 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3717 } else {
3718 tasklet_schedule(&priv->poll_rx_task);
3719 }
3720}
3721
a66098da
LB		 3722
3723/*
3724 * Core driver operations.
3725 */
3726static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3727{
3728 struct mwl8k_priv *priv = hw->priv;
3729 int index = skb_get_queue_mapping(skb);
3730 int rc;
3731
9189c100 3732 if (!priv->radio_on) {
c96c31e4
JP		 3733 wiphy_debug(hw->wiphy,
3734 "dropped TX frame since radio disabled\n");
a66098da
LB		 3735 dev_kfree_skb(skb);
3736 return NETDEV_TX_OK;
3737 }
3738
3739 rc = mwl8k_txq_xmit(hw, index, skb);
3740
3741 return rc;
3742}
3743
a66098da
LB		 3744static int mwl8k_start(struct ieee80211_hw *hw)
3745{
a66098da
LB		 3746 struct mwl8k_priv *priv = hw->priv;
3747 int rc;
3748
a0607fd3 3749 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3750 IRQF_SHARED, MWL8K_NAME, hw);
3751 if (rc) {
5db55844 3752 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
2ec610cb 3753 return -EIO;
a66098da
LB		 3754 }
3755
67e2eb27 3756 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 3757 tasklet_enable(&priv->poll_tx_task);
67e2eb27 3758 tasklet_enable(&priv->poll_rx_task);
2ec610cb 3759
a66098da 3760 /* Enable interrupts */
c23b5a69 3761 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 3762
2ec610cb
LB		 3763 rc = mwl8k_fw_lock(hw);
3764 if (!rc) {
55489b6e 3765 rc = mwl8k_cmd_radio_enable(hw);
a66098da 3766
5e4cf166
LB		 3767 if (!priv->ap_fw) {
3768 if (!rc)
55489b6e 3769 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 3770
5e4cf166
LB		 3771 if (!rc)
3772 rc = mwl8k_cmd_set_pre_scan(hw);
3773
3774 if (!rc)
3775 rc = mwl8k_cmd_set_post_scan(hw,
3776 "\x00\x00\x00\x00\x00\x00");
3777 }
2ec610cb
LB		 3778
3779 if (!rc)
55489b6e 3780 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 3781
2ec610cb 3782 if (!rc)
55489b6e 3783 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 3784
2ec610cb
LB		 3785 mwl8k_fw_unlock(hw);
3786 }
3787
3788 if (rc) {
3789 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3790 free_irq(priv->pdev->irq, hw);
1e9f9de3 3791 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3792 tasklet_disable(&priv->poll_rx_task);
2ec610cb 3793 }
a66098da
LB		 3794
3795 return rc;
3796}
3797
a66098da
LB		 3798static void mwl8k_stop(struct ieee80211_hw *hw)
3799{
a66098da
LB		 3800 struct mwl8k_priv *priv = hw->priv;
3801 int i;
3802
55489b6e 3803 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 3804
3805 ieee80211_stop_queues(hw);
3806
a66098da 3807 /* Disable interrupts */
a66098da 3808 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3809 free_irq(priv->pdev->irq, hw);
3810
3811 /* Stop finalize join worker */
3812 cancel_work_sync(&priv->finalize_join_worker);
3813 if (priv->beacon_skb != NULL)
3814 dev_kfree_skb(priv->beacon_skb);
3815
67e2eb27 3816 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 3817 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3818 tasklet_disable(&priv->poll_rx_task);
a66098da 3819
a66098da
LB		 3820 /* Return all skbs to mac80211 */
3821 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 3822 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB		 3823}
3824
0863ade8
BC		 3825static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image);
3826
a66098da 3827static int mwl8k_add_interface(struct ieee80211_hw *hw,
f5bb87cf 3828 struct ieee80211_vif *vif)
a66098da
LB		 3829{
3830 struct mwl8k_priv *priv = hw->priv;
3831 struct mwl8k_vif *mwl8k_vif;
ee0ddf18 3832 u32 macids_supported;
0863ade8
BC		 3833 int macid, rc;
3834 struct mwl8k_device_info *di;
a66098da 3835
a43c49a8
LB		 3836 /*
3837 * Reject interface creation if sniffer mode is active, as
3838 * STA operation is mutually exclusive with hardware sniffer
b64fe619 3839 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB		 3840 */
3841 if (priv->sniffer_enabled) {
c96c31e4
JP		 3842 wiphy_info(hw->wiphy,
3843 "unable to create STA interface because sniffer mode is enabled\n");
a43c49a8
LB		 3844 return -EINVAL;
3845 }
3846
0863ade8 3847 di = priv->device_info;
ee0ddf18
LB		 3848 switch (vif->type) {
3849 case NL80211_IFTYPE_AP:
0863ade8
BC		 3850 if (!priv->ap_fw && di->fw_image_ap) {
3851 /* we must load the ap fw to meet this request */
3852 if (!list_empty(&priv->vif_list))
3853 return -EBUSY;
3854 rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
3855 if (rc)
3856 return rc;
3857 }
ee0ddf18
LB		 3858 macids_supported = priv->ap_macids_supported;
3859 break;
3860 case NL80211_IFTYPE_STATION:
0863ade8
BC		 3861 if (priv->ap_fw && di->fw_image_sta) {
3862 /* we must load the sta fw to meet this request */
3863 if (!list_empty(&priv->vif_list))
3864 return -EBUSY;
3865 rc = mwl8k_reload_firmware(hw, di->fw_image_sta);
3866 if (rc)
3867 return rc;
3868 }
ee0ddf18
LB		 3869 macids_supported = priv->sta_macids_supported;
3870 break;
3871 default:
3872 return -EINVAL;
3873 }
3874
3875 macid = ffs(macids_supported & ~priv->macids_used);
3876 if (!macid--)
3877 return -EBUSY;
3878
f5bb87cf 3879 /* Setup driver private area. */
1ed32e4f 3880 mwl8k_vif = MWL8K_VIF(vif);
a66098da 3881 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
f5bb87cf 3882 mwl8k_vif->vif = vif;
ee0ddf18 3883 mwl8k_vif->macid = macid;
a66098da 3884 mwl8k_vif->seqno = 0;
d9a07d49
NS		 3885 memcpy(mwl8k_vif->bssid, vif->addr, ETH_ALEN);
3886 mwl8k_vif->is_hw_crypto_enabled = false;
a66098da 3887
aa21d0f6
LB		 3888 /* Set the mac address. */
3889 mwl8k_cmd_set_mac_addr(hw, vif, vif->addr);
3890
3891 if (priv->ap_fw)
3892 mwl8k_cmd_set_new_stn_add_self(hw, vif);
3893
ee0ddf18 3894 priv->macids_used |= 1 << mwl8k_vif->macid;
f5bb87cf 3895 list_add_tail(&mwl8k_vif->list, &priv->vif_list);
a66098da
LB		 3896
3897 return 0;
3898}
3899
3900static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3901 struct ieee80211_vif *vif)
a66098da
LB		 3902{
3903 struct mwl8k_priv *priv = hw->priv;
f5bb87cf 3904 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
a66098da 3905
b64fe619
LB		 3906 if (priv->ap_fw)
3907 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
3908
aa21d0f6 3909 mwl8k_cmd_set_mac_addr(hw, vif, "\x00\x00\x00\x00\x00\x00");
32060e1b 3910
ee0ddf18 3911 priv->macids_used &= ~(1 << mwl8k_vif->macid);
f5bb87cf 3912 list_del(&mwl8k_vif->list);
a66098da
LB		 3913}
3914
ee03a932 3915static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 3916{
a66098da
LB		 3917 struct ieee80211_conf *conf = &hw->conf;
3918 struct mwl8k_priv *priv = hw->priv;
ee03a932 3919 int rc;
a66098da 3920
7595d67a 3921 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 3922 mwl8k_cmd_radio_disable(hw);
ee03a932 3923 return 0;
7595d67a
LB		 3924 }
3925
ee03a932
LB		 3926 rc = mwl8k_fw_lock(hw);
3927 if (rc)
3928 return rc;
a66098da 3929
55489b6e 3930 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 3931 if (rc)
3932 goto out;
a66098da 3933
610677d2 3934 rc = mwl8k_cmd_set_rf_channel(hw, conf);
ee03a932
LB		 3935 if (rc)
3936 goto out;
3937
a66098da
LB		 3938 if (conf->power_level > 18)
3939 conf->power_level = 18;
a66098da 3940
08b06347 3941 if (priv->ap_fw) {
41fdf097
NS		 3942 rc = mwl8k_cmd_tx_power(hw, conf, conf->power_level);
3943 if (rc)
3944 goto out;
3945
08b06347
LB		 3946 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
3947 if (!rc)
3948 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
3949 } else {
41fdf097
NS		 3950 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
3951 if (rc)
3952 goto out;
08b06347
LB		 3953 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
3954 }
a66098da 3955
ee03a932
LB		 3956out:
3957 mwl8k_fw_unlock(hw);
a66098da 3958
ee03a932 3959 return rc;
a66098da
LB		 3960}
3961
b64fe619
LB		 3962static void
3963mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3964 struct ieee80211_bss_conf *info, u32 changed)
a66098da 3965{
a66098da 3966 struct mwl8k_priv *priv = hw->priv;
c3cbbe8a 3967 u32 ap_legacy_rates;
13935e2c 3968 u8 ap_mcs_rates[16];
3a980d0a
LB		 3969 int rc;
3970
c3cbbe8a 3971 if (mwl8k_fw_lock(hw))
3a980d0a 3972 return;
a66098da 3973
c3cbbe8a
LB		 3974 /*
3975 * No need to capture a beacon if we're no longer associated.
3976 */
3977 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
3978 priv->capture_beacon = false;
3a980d0a 3979
c3cbbe8a 3980 /*
13935e2c 3981 * Get the AP's legacy and MCS rates.
c3cbbe8a 3982 */
7dc6a7a7 3983 if (vif->bss_conf.assoc) {
c6e96010 3984 struct ieee80211_sta *ap;
c97470dd 3985
c6e96010 3986 rcu_read_lock();
c6e96010 3987
c3cbbe8a
LB		 3988 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
3989 if (ap == NULL) {
3990 rcu_read_unlock();
c6e96010 3991 goto out;
c3cbbe8a
LB		 3992 }
3993
8707d026
LB		 3994 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
3995 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
3996 } else {
3997 ap_legacy_rates =
3998 ap->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3999 }
13935e2c 4000 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB		 4001
4002 rcu_read_unlock();
4003 }
c6e96010 4004
c3cbbe8a 4005 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
13935e2c 4006 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB		 4007 if (rc)
4008 goto out;
a66098da 4009
b71ed2c6 4010 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB		 4011 if (rc)
4012 goto out;
c3cbbe8a 4013 }
a66098da 4014
c3cbbe8a 4015 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB		 4016 rc = mwl8k_set_radio_preamble(hw,
4017 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 4018 if (rc)
4019 goto out;
c3cbbe8a 4020 }
a66098da 4021
c3cbbe8a 4022 if (changed & BSS_CHANGED_ERP_SLOT) {
7dc6a7a7 4023 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 4024 if (rc)
4025 goto out;
c3cbbe8a 4026 }
a66098da 4027
c97470dd
LB		 4028 if (vif->bss_conf.assoc &&
4029 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
4030 BSS_CHANGED_HT))) {
c3cbbe8a 4031 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB		 4032 if (rc)
4033 goto out;
c3cbbe8a 4034 }
a66098da 4035
c3cbbe8a
LB		 4036 if (vif->bss_conf.assoc &&
4037 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB		 4038 /*
4039 * Finalize the join. Tell rx handler to process
4040 * next beacon from our BSSID.
4041 */
0a11dfc3 4042 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 4043 priv->capture_beacon = true;
a66098da
LB		 4044 }
4045
3a980d0a
LB		 4046out:
4047 mwl8k_fw_unlock(hw);
a66098da
LB		 4048}
4049
b64fe619
LB		 4050static void
4051mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4052 struct ieee80211_bss_conf *info, u32 changed)
4053{
4054 int rc;
4055
4056 if (mwl8k_fw_lock(hw))
4057 return;
4058
4059 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4060 rc = mwl8k_set_radio_preamble(hw,
4061 vif->bss_conf.use_short_preamble);
4062 if (rc)
4063 goto out;
4064 }
4065
4066 if (changed & BSS_CHANGED_BASIC_RATES) {
4067 int idx;
4068 int rate;
4069
4070 /*
4071 * Use lowest supported basic rate for multicasts
4072 * and management frames (such as probe responses --
4073 * beacons will always go out at 1 Mb/s).
4074 */
4075 idx = ffs(vif->bss_conf.basic_rates);
8707d026
LB		 4076 if (idx)
4077 idx--;
4078
4079 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
4080 rate = mwl8k_rates_24[idx].hw_value;
4081 else
4082 rate = mwl8k_rates_50[idx].hw_value;
b64fe619
LB		 4083
4084 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
4085 }
4086
4087 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
4088 struct sk_buff *skb;
4089
4090 skb = ieee80211_beacon_get(hw, vif);
4091 if (skb != NULL) {
aa21d0f6 4092 mwl8k_cmd_set_beacon(hw, vif, skb->data, skb->len);
b64fe619
LB		 4093 kfree_skb(skb);
4094 }
4095 }
4096
4097 if (changed & BSS_CHANGED_BEACON_ENABLED)
aa21d0f6 4098 mwl8k_cmd_bss_start(hw, vif, info->enable_beacon);
b64fe619
LB		 4099
4100out:
4101 mwl8k_fw_unlock(hw);
4102}
4103
4104static void
4105mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4106 struct ieee80211_bss_conf *info, u32 changed)
4107{
4108 struct mwl8k_priv *priv = hw->priv;
4109
4110 if (!priv->ap_fw)
4111 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
4112 else
4113 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
4114}
4115
e81cd2d6 4116static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 4117 struct netdev_hw_addr_list *mc_list)
e81cd2d6
LB		 4118{
4119 struct mwl8k_cmd_pkt *cmd;
4120
447ced07
LB		 4121 /*
4122 * Synthesize and return a command packet that programs the
4123 * hardware multicast address filter. At this point we don't
4124 * know whether FIF_ALLMULTI is being requested, but if it is,
4125 * we'll end up throwing this packet away and creating a new
4126 * one in mwl8k_configure_filter().
4127 */
22bedad3 4128 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_list);
e81cd2d6
LB		 4129
4130 return (unsigned long)cmd;
4131}
4132
a43c49a8
LB		 4133static int
4134mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
4135 unsigned int changed_flags,
4136 unsigned int *total_flags)
4137{
4138 struct mwl8k_priv *priv = hw->priv;
4139
4140 /*
4141 * Hardware sniffer mode is mutually exclusive with STA
4142 * operation, so refuse to enable sniffer mode if a STA
4143 * interface is active.
4144 */
f5bb87cf 4145 if (!list_empty(&priv->vif_list)) {
a43c49a8 4146 if (net_ratelimit())
c96c31e4
JP		 4147 wiphy_info(hw->wiphy,
4148 "not enabling sniffer mode because STA interface is active\n");
a43c49a8
LB		 4149 return 0;
4150 }
4151
4152 if (!priv->sniffer_enabled) {
55489b6e 4153 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 4154 return 0;
4155 priv->sniffer_enabled = true;
4156 }
4157
4158 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
4159 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
4160 FIF_OTHER_BSS;
4161
4162 return 1;
4163}
4164
f5bb87cf
LB		 4165static struct mwl8k_vif *mwl8k_first_vif(struct mwl8k_priv *priv)
4166{
4167 if (!list_empty(&priv->vif_list))
4168 return list_entry(priv->vif_list.next, struct mwl8k_vif, list);
4169
4170 return NULL;
4171}
4172
e6935ea1
LB		 4173static void mwl8k_configure_filter(struct ieee80211_hw *hw,
4174 unsigned int changed_flags,
4175 unsigned int *total_flags,
4176 u64 multicast)
4177{
4178 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 4179 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
4180
c0adae2c
LB		 4181 /*
4182 * AP firmware doesn't allow fine-grained control over
4183 * the receive filter.
4184 */
4185 if (priv->ap_fw) {
4186 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
4187 kfree(cmd);
4188 return;
4189 }
4190
a43c49a8
LB		 4191 /*
4192 * Enable hardware sniffer mode if FIF_CONTROL or
4193 * FIF_OTHER_BSS is requested.
4194 */
4195 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
4196 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
4197 kfree(cmd);
4198 return;
4199 }
a66098da 4200
e6935ea1 4201 /* Clear unsupported feature flags */
447ced07 4202 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 4203
90852f7a
LB		 4204 if (mwl8k_fw_lock(hw)) {
4205 kfree(cmd);
e6935ea1 4206 return;
90852f7a 4207 }
a66098da 4208
a43c49a8 4209 if (priv->sniffer_enabled) {
55489b6e 4210 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 4211 priv->sniffer_enabled = false;
4212 }
4213
e6935ea1 4214 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 4215 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
4216 /*
4217 * Disable the BSS filter.
4218 */
e6935ea1 4219 mwl8k_cmd_set_pre_scan(hw);
77165d88 4220 } else {
f5bb87cf 4221 struct mwl8k_vif *mwl8k_vif;
0a11dfc3 4222 const u8 *bssid;
a94cc97e 4223
77165d88
LB		 4224 /*
4225 * Enable the BSS filter.
4226 *
4227 * If there is an active STA interface, use that
4228 * interface's BSSID, otherwise use a dummy one
4229 * (where the OUI part needs to be nonzero for
4230 * the BSSID to be accepted by POST_SCAN).
4231 */
f5bb87cf
LB		 4232 mwl8k_vif = mwl8k_first_vif(priv);
4233 if (mwl8k_vif != NULL)
4234 bssid = mwl8k_vif->vif->bss_conf.bssid;
4235 else
4236 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 4237
e6935ea1 4238 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 4239 }
4240 }
4241
447ced07
LB		 4242 /*
4243 * If FIF_ALLMULTI is being requested, throw away the command
4244 * packet that ->prepare_multicast() built and replace it with
4245 * a command packet that enables reception of all multicast
4246 * packets.
4247 */
4248 if (*total_flags & FIF_ALLMULTI) {
4249 kfree(cmd);
22bedad3 4250 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, NULL);
447ced07
LB		 4251 }
4252
4253 if (cmd != NULL) {
4254 mwl8k_post_cmd(hw, cmd);
4255 kfree(cmd);
e6935ea1 4256 }
a66098da 4257
e6935ea1 4258 mwl8k_fw_unlock(hw);
a66098da
LB		 4259}
4260
a66098da
LB		 4261static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4262{
c2c2b12a 4263 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB		 4264}
4265
4a6967b8
JB		 4266static int mwl8k_sta_remove(struct ieee80211_hw *hw,
4267 struct ieee80211_vif *vif,
4268 struct ieee80211_sta *sta)
3f5610ff
LB		 4269{
4270 struct mwl8k_priv *priv = hw->priv;
4271
4a6967b8
JB		 4272 if (priv->ap_fw)
4273 return mwl8k_cmd_set_new_stn_del(hw, vif, sta->addr);
4274 else
4275 return mwl8k_cmd_update_stadb_del(hw, vif, sta->addr);
bbfd9128
LB		 4276}
4277
4a6967b8
JB		 4278static int mwl8k_sta_add(struct ieee80211_hw *hw,
4279 struct ieee80211_vif *vif,
4280 struct ieee80211_sta *sta)
bbfd9128
LB		 4281{
4282 struct mwl8k_priv *priv = hw->priv;
4a6967b8 4283 int ret;
fcdc403c
NS		 4284 int i;
4285 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4286 struct ieee80211_key_conf *key;
bbfd9128 4287
4a6967b8
JB		 4288 if (!priv->ap_fw) {
4289 ret = mwl8k_cmd_update_stadb_add(hw, vif, sta);
4290 if (ret >= 0) {
4291 MWL8K_STA(sta)->peer_id = ret;
fcdc403c 4292 ret = 0;
4a6967b8 4293 }
bbfd9128 4294
d9a07d49
NS		 4295 } else {
4296 ret = mwl8k_cmd_set_new_stn_add(hw, vif, sta);
bbfd9128 4297 }
4a6967b8 4298
d9a07d49
NS		 4299 for (i = 0; i < NUM_WEP_KEYS; i++) {
4300 key = IEEE80211_KEY_CONF(mwl8k_vif->wep_key_conf[i].key);
4301 if (mwl8k_vif->wep_key_conf[i].enabled)
4302 mwl8k_set_key(hw, SET_KEY, vif, sta, key);
4303 }
fcdc403c 4304 return ret;
bbfd9128
LB		 4305}
4306
a66098da
LB		 4307static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
4308 const struct ieee80211_tx_queue_params *params)
4309{
3e4f542c 4310 struct mwl8k_priv *priv = hw->priv;
a66098da 4311 int rc;
a66098da 4312
3e4f542c
LB		 4313 rc = mwl8k_fw_lock(hw);
4314 if (!rc) {
0863ade8
BC		 4315 BUG_ON(queue > MWL8K_TX_QUEUES - 1);
4316 memcpy(&priv->wmm_params[queue], params, sizeof(*params));
4317
3e4f542c 4318 if (!priv->wmm_enabled)
55489b6e 4319 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 4320
3e4f542c 4321 if (!rc)
55489b6e
LB		 4322 rc = mwl8k_cmd_set_edca_params(hw, queue,
4323 params->cw_min,
4324 params->cw_max,
4325 params->aifs,
4326 params->txop);
3e4f542c
LB		 4327
4328 mwl8k_fw_unlock(hw);
a66098da 4329 }
3e4f542c 4330
a66098da
LB		 4331 return rc;
4332}
4333
a66098da
LB		 4334static int mwl8k_get_stats(struct ieee80211_hw *hw,
4335 struct ieee80211_low_level_stats *stats)
4336{
55489b6e 4337 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 4338}
4339
0d462bbb
JL		 4340static int mwl8k_get_survey(struct ieee80211_hw *hw, int idx,
4341 struct survey_info *survey)
4342{
4343 struct mwl8k_priv *priv = hw->priv;
4344 struct ieee80211_conf *conf = &hw->conf;
4345
4346 if (idx != 0)
4347 return -ENOENT;
4348
4349 survey->channel = conf->channel;
4350 survey->filled = SURVEY_INFO_NOISE_DBM;
4351 survey->noise = priv->noise;
4352
4353 return 0;
4354}
4355
a2292d83
LB		 4356static int
4357mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4358 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 4359 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4360 u8 buf_size)
a2292d83
LB		 4361{
4362 switch (action) {
4363 case IEEE80211_AMPDU_RX_START:
4364 case IEEE80211_AMPDU_RX_STOP:
4365 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
4366 return -ENOTSUPP;
4367 return 0;
4368 default:
4369 return -ENOTSUPP;
4370 }
4371}
4372
a66098da
LB		 4373static const struct ieee80211_ops mwl8k_ops = {
4374 .tx = mwl8k_tx,
4375 .start = mwl8k_start,
4376 .stop = mwl8k_stop,
4377 .add_interface = mwl8k_add_interface,
4378 .remove_interface = mwl8k_remove_interface,
4379 .config = mwl8k_config,
a66098da 4380 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 4381 .prepare_multicast = mwl8k_prepare_multicast,
a66098da 4382 .configure_filter = mwl8k_configure_filter,
fcdc403c 4383 .set_key = mwl8k_set_key,
a66098da 4384 .set_rts_threshold = mwl8k_set_rts_threshold,
4a6967b8
JB		 4385 .sta_add = mwl8k_sta_add,
4386 .sta_remove = mwl8k_sta_remove,
a66098da 4387 .conf_tx = mwl8k_conf_tx,
a66098da 4388 .get_stats = mwl8k_get_stats,
0d462bbb 4389 .get_survey = mwl8k_get_survey,
a2292d83 4390 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB		 4391};
4392
a66098da
LB		 4393static void mwl8k_finalize_join_worker(struct work_struct *work)
4394{
4395 struct mwl8k_priv *priv =
4396 container_of(work, struct mwl8k_priv, finalize_join_worker);
4397 struct sk_buff *skb = priv->beacon_skb;
56007a02
JB		 4398 struct ieee80211_mgmt *mgmt = (void *)skb->data;
4399 int len = skb->len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
4400 const u8 *tim = cfg80211_find_ie(WLAN_EID_TIM,
4401 mgmt->u.beacon.variable, len);
4402 int dtim_period = 1;
4403
4404 if (tim && tim[1] >= 2)
4405 dtim_period = tim[3];
a66098da 4406
56007a02 4407 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, dtim_period);
a66098da 4408
f5bb87cf 4409 dev_kfree_skb(skb);
a66098da
LB		 4410 priv->beacon_skb = NULL;
4411}
4412
bcb628d5 4413enum {
9e1b17ea
LB		 4414 MWL8363 = 0,
4415 MWL8687,
bcb628d5 4416 MWL8366,
6f6d1e9a
LB		 4417};
4418
952a0e96
BC		 4419#define MWL8K_8366_AP_FW_API 1
4420#define _MWL8K_8366_AP_FW(api) "mwl8k/fmimage_8366_ap-" #api ".fw"
4421#define MWL8K_8366_AP_FW(api) _MWL8K_8366_AP_FW(api)
4422
bcb628d5 4423static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
9e1b17ea
LB		 4424 [MWL8363] = {
4425 .part_name = "88w8363",
4426 .helper_image = "mwl8k/helper_8363.fw",
0863ade8 4427 .fw_image_sta = "mwl8k/fmimage_8363.fw",
9e1b17ea 4428 },
49eb691c 4429 [MWL8687] = {
bcb628d5
JL		 4430 .part_name = "88w8687",
4431 .helper_image = "mwl8k/helper_8687.fw",
0863ade8 4432 .fw_image_sta = "mwl8k/fmimage_8687.fw",
bcb628d5 4433 },
49eb691c 4434 [MWL8366] = {
bcb628d5
JL		 4435 .part_name = "88w8366",
4436 .helper_image = "mwl8k/helper_8366.fw",
0863ade8 4437 .fw_image_sta = "mwl8k/fmimage_8366.fw",
952a0e96
BC		 4438 .fw_image_ap = MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API),
4439 .fw_api_ap = MWL8K_8366_AP_FW_API,
89a91f4f 4440 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 4441 },
45a390dd
LB		 4442};
4443
c92d4ede
LB		 4444MODULE_FIRMWARE("mwl8k/helper_8363.fw");
4445MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
4446MODULE_FIRMWARE("mwl8k/helper_8687.fw");
4447MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
4448MODULE_FIRMWARE("mwl8k/helper_8366.fw");
4449MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
952a0e96 4450MODULE_FIRMWARE(MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API));
c92d4ede 4451
45a390dd 4452static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
e5868ba1 4453 { PCI_VDEVICE(MARVELL, 0x2a0a), .driver_data = MWL8363, },
9e1b17ea
LB		 4454 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
4455 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL		 4456 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
4457 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
4458 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
ca66527c 4459 { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
bcb628d5 4460 { },
45a390dd
LB		 4461};
4462MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
4463
99020471
BC		 4464static int mwl8k_request_alt_fw(struct mwl8k_priv *priv)
4465{
4466 int rc;
4467 printk(KERN_ERR "%s: Error requesting preferred fw %s.\n"
4468 "Trying alternative firmware %s\n", pci_name(priv->pdev),
4469 priv->fw_pref, priv->fw_alt);
4470 rc = mwl8k_request_fw(priv, priv->fw_alt, &priv->fw_ucode, true);
4471 if (rc) {
4472 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
4473 pci_name(priv->pdev), priv->fw_alt);
4474 return rc;
4475 }
4476 return 0;
4477}
4478
4479static int mwl8k_firmware_load_success(struct mwl8k_priv *priv);
4480static void mwl8k_fw_state_machine(const struct firmware *fw, void *context)
4481{
4482 struct mwl8k_priv *priv = context;
4483 struct mwl8k_device_info *di = priv->device_info;
4484 int rc;
4485
4486 switch (priv->fw_state) {
4487 case FW_STATE_INIT:
4488 if (!fw) {
4489 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
4490 pci_name(priv->pdev), di->helper_image);
4491 goto fail;
4492 }
4493 priv->fw_helper = fw;
4494 rc = mwl8k_request_fw(priv, priv->fw_pref, &priv->fw_ucode,
4495 true);
4496 if (rc && priv->fw_alt) {
4497 rc = mwl8k_request_alt_fw(priv);
4498 if (rc)
4499 goto fail;
4500 priv->fw_state = FW_STATE_LOADING_ALT;
4501 } else if (rc)
4502 goto fail;
4503 else
4504 priv->fw_state = FW_STATE_LOADING_PREF;
4505 break;
4506
4507 case FW_STATE_LOADING_PREF:
4508 if (!fw) {
4509 if (priv->fw_alt) {
4510 rc = mwl8k_request_alt_fw(priv);
4511 if (rc)
4512 goto fail;
4513 priv->fw_state = FW_STATE_LOADING_ALT;
4514 } else
4515 goto fail;
4516 } else {
4517 priv->fw_ucode = fw;
4518 rc = mwl8k_firmware_load_success(priv);
4519 if (rc)
4520 goto fail;
4521 else
4522 complete(&priv->firmware_loading_complete);
4523 }
4524 break;
4525
4526 case FW_STATE_LOADING_ALT:
4527 if (!fw) {
4528 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
4529 pci_name(priv->pdev), di->helper_image);
4530 goto fail;
4531 }
4532 priv->fw_ucode = fw;
4533 rc = mwl8k_firmware_load_success(priv);
4534 if (rc)
4535 goto fail;
4536 else
4537 complete(&priv->firmware_loading_complete);
4538 break;
4539
4540 default:
4541 printk(KERN_ERR "%s: Unexpected firmware loading state: %d\n",
4542 MWL8K_NAME, priv->fw_state);
4543 BUG_ON(1);
4544 }
4545
4546 return;
4547
4548fail:
4549 priv->fw_state = FW_STATE_ERROR;
4550 complete(&priv->firmware_loading_complete);
4551 device_release_driver(&priv->pdev->dev);
4552 mwl8k_release_firmware(priv);
4553}
4554
4555static int mwl8k_init_firmware(struct ieee80211_hw *hw, char *fw_image,
4556 bool nowait)
a66098da 4557{
3cc7772c 4558 struct mwl8k_priv *priv = hw->priv;
a66098da 4559 int rc;
be695fc4
LB		 4560
4561 /* Reset firmware and hardware */
4562 mwl8k_hw_reset(priv);
4563
4564 /* Ask userland hotplug daemon for the device firmware */
99020471 4565 rc = mwl8k_request_firmware(priv, fw_image, nowait);
be695fc4 4566 if (rc) {
5db55844 4567 wiphy_err(hw->wiphy, "Firmware files not found\n");
3cc7772c 4568 return rc;
be695fc4
LB		 4569 }
4570
99020471
BC		 4571 if (nowait)
4572 return rc;
4573
be695fc4
LB		 4574 /* Load firmware into hardware */
4575 rc = mwl8k_load_firmware(hw);
3cc7772c 4576 if (rc)
5db55844 4577 wiphy_err(hw->wiphy, "Cannot start firmware\n");
be695fc4
LB		 4578
4579 /* Reclaim memory once firmware is successfully loaded */
4580 mwl8k_release_firmware(priv);
4581
3cc7772c
BC		 4582 return rc;
4583}
4584
4585/* initialize hw after successfully loading a firmware image */
4586static int mwl8k_probe_hw(struct ieee80211_hw *hw)
4587{
4588 struct mwl8k_priv *priv = hw->priv;
4589 int rc = 0;
4590 int i;
be695fc4 4591
91942230 4592 if (priv->ap_fw) {
89a91f4f 4593 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230 4594 if (priv->rxd_ops == NULL) {
c96c31e4
JP		 4595 wiphy_err(hw->wiphy,
4596 "Driver does not have AP firmware image support for this hardware\n");
91942230
LB		 4597 goto err_stop_firmware;
4598 }
4599 } else {
89a91f4f 4600 priv->rxd_ops = &rxd_sta_ops;
91942230 4601 }
be695fc4
LB		 4602
4603 priv->sniffer_enabled = false;
4604 priv->wmm_enabled = false;
4605 priv->pending_tx_pkts = 0;
4606
a66098da
LB		 4607 rc = mwl8k_rxq_init(hw, 0);
4608 if (rc)
3cc7772c 4609 goto err_stop_firmware;
a66098da
LB		 4610 rxq_refill(hw, 0, INT_MAX);
4611
a66098da
LB		 4612 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
4613 rc = mwl8k_txq_init(hw, i);
4614 if (rc)
4615 goto err_free_queues;
4616 }
4617
4618 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 4619 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
67e2eb27 4620 iowrite32(MWL8K_A2H_INT_TX_DONE | MWL8K_A2H_INT_RX_READY,
1e9f9de3 4621 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
a66098da
LB		 4622 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
4623
a0607fd3 4624 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 4625 IRQF_SHARED, MWL8K_NAME, hw);
4626 if (rc) {
5db55844 4627 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
a66098da
LB		 4628 goto err_free_queues;
4629 }
4630
a66098da
LB		 4631 /*
4632 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 4633 * commands use interrupts and avoid polling. Disable
a66098da
LB		 4634 * interrupts when done.
4635 */
c23b5a69 4636 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4637
4638 /* Get config data, mac addrs etc */
42fba21d
LB		 4639 if (priv->ap_fw) {
4640 rc = mwl8k_cmd_get_hw_spec_ap(hw);
4641 if (!rc)
4642 rc = mwl8k_cmd_set_hw_spec(hw);
4643 } else {
4644 rc = mwl8k_cmd_get_hw_spec_sta(hw);
4645 }
a66098da 4646 if (rc) {
5db55844 4647 wiphy_err(hw->wiphy, "Cannot initialise firmware\n");
be695fc4 4648 goto err_free_irq;
a66098da
LB		 4649 }
4650
4651 /* Turn radio off */
55489b6e 4652 rc = mwl8k_cmd_radio_disable(hw);
a66098da 4653 if (rc) {
5db55844 4654 wiphy_err(hw->wiphy, "Cannot disable\n");
be695fc4 4655 goto err_free_irq;
a66098da
LB		 4656 }
4657
32060e1b 4658 /* Clear MAC address */
aa21d0f6 4659 rc = mwl8k_cmd_set_mac_addr(hw, NULL, "\x00\x00\x00\x00\x00\x00");
32060e1b 4660 if (rc) {
5db55844 4661 wiphy_err(hw->wiphy, "Cannot clear MAC address\n");
be695fc4 4662 goto err_free_irq;
32060e1b
LB		 4663 }
4664
a66098da 4665 /* Disable interrupts */
a66098da 4666 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4667 free_irq(priv->pdev->irq, hw);
4668
c96c31e4
JP		 4669 wiphy_info(hw->wiphy, "%s v%d, %pm, %s firmware %u.%u.%u.%u\n",
4670 priv->device_info->part_name,
4671 priv->hw_rev, hw->wiphy->perm_addr,
4672 priv->ap_fw ? "AP" : "STA",
4673 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
4674 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 4675
4676 return 0;
4677
a66098da 4678err_free_irq:
a66098da 4679 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4680 free_irq(priv->pdev->irq, hw);
4681
4682err_free_queues:
4683 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4684 mwl8k_txq_deinit(hw, i);
4685 mwl8k_rxq_deinit(hw, 0);
4686
3cc7772c
BC		 4687err_stop_firmware:
4688 mwl8k_hw_reset(priv);
4689
4690 return rc;
4691}
4692
4693/*
4694 * invoke mwl8k_reload_firmware to change the firmware image after the device
4695 * has already been registered
4696 */
4697static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image)
4698{
4699 int i, rc = 0;
4700 struct mwl8k_priv *priv = hw->priv;
4701
4702 mwl8k_stop(hw);
4703 mwl8k_rxq_deinit(hw, 0);
4704
4705 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4706 mwl8k_txq_deinit(hw, i);
4707
99020471 4708 rc = mwl8k_init_firmware(hw, fw_image, false);
3cc7772c
BC		 4709 if (rc)
4710 goto fail;
4711
4712 rc = mwl8k_probe_hw(hw);
4713 if (rc)
4714 goto fail;
4715
4716 rc = mwl8k_start(hw);
4717 if (rc)
4718 goto fail;
4719
4720 rc = mwl8k_config(hw, ~0);
4721 if (rc)
4722 goto fail;
4723
4724 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
4725 rc = mwl8k_conf_tx(hw, i, &priv->wmm_params[i]);
4726 if (rc)
4727 goto fail;
4728 }
4729
4730 return rc;
4731
4732fail:
4733 printk(KERN_WARNING "mwl8k: Failed to reload firmware image.\n");
4734 return rc;
4735}
4736
4737static int mwl8k_firmware_load_success(struct mwl8k_priv *priv)
4738{
4739 struct ieee80211_hw *hw = priv->hw;
4740 int i, rc;
4741
99020471
BC		 4742 rc = mwl8k_load_firmware(hw);
4743 mwl8k_release_firmware(priv);
4744 if (rc) {
4745 wiphy_err(hw->wiphy, "Cannot start firmware\n");
4746 return rc;
4747 }
4748
3cc7772c
BC		 4749 /*
4750 * Extra headroom is the size of the required DMA header
4751 * minus the size of the smallest 802.11 frame (CTS frame).
4752 */
4753 hw->extra_tx_headroom =
4754 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
4755
4756 hw->channel_change_time = 10;
4757
4758 hw->queues = MWL8K_TX_QUEUES;
4759
4760 /* Set rssi values to dBm */
4761 hw->flags |= IEEE80211_HW_SIGNAL_DBM;
4762 hw->vif_data_size = sizeof(struct mwl8k_vif);
4763 hw->sta_data_size = sizeof(struct mwl8k_sta);
4764
4765 priv->macids_used = 0;
4766 INIT_LIST_HEAD(&priv->vif_list);
4767
4768 /* Set default radio state and preamble */
4769 priv->radio_on = 0;
4770 priv->radio_short_preamble = 0;
4771
4772 /* Finalize join worker */
4773 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
4774
4775 /* TX reclaim and RX tasklets. */
4776 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
4777 tasklet_disable(&priv->poll_tx_task);
4778 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
4779 tasklet_disable(&priv->poll_rx_task);
4780
4781 /* Power management cookie */
4782 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
4783 if (priv->cookie == NULL)
4784 return -ENOMEM;
4785
4786 mutex_init(&priv->fw_mutex);
4787 priv->fw_mutex_owner = NULL;
4788 priv->fw_mutex_depth = 0;
4789 priv->hostcmd_wait = NULL;
4790
4791 spin_lock_init(&priv->tx_lock);
4792
4793 priv->tx_wait = NULL;
4794
4795 rc = mwl8k_probe_hw(hw);
4796 if (rc)
4797 goto err_free_cookie;
4798
4799 hw->wiphy->interface_modes = 0;
4800 if (priv->ap_macids_supported || priv->device_info->fw_image_ap)
4801 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
4802 if (priv->sta_macids_supported || priv->device_info->fw_image_sta)
4803 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
4804
4805 rc = ieee80211_register_hw(hw);
4806 if (rc) {
4807 wiphy_err(hw->wiphy, "Cannot register device\n");
4808 goto err_unprobe_hw;
4809 }
4810
4811 return 0;
4812
4813err_unprobe_hw:
4814 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4815 mwl8k_txq_deinit(hw, i);
4816 mwl8k_rxq_deinit(hw, 0);
4817
be695fc4 4818err_free_cookie:
a66098da
LB		 4819 if (priv->cookie != NULL)
4820 pci_free_consistent(priv->pdev, 4,
4821 priv->cookie, priv->cookie_dma);
4822
3cc7772c
BC		 4823 return rc;
4824}
4825static int __devinit mwl8k_probe(struct pci_dev *pdev,
4826 const struct pci_device_id *id)
4827{
4828 static int printed_version;
4829 struct ieee80211_hw *hw;
4830 struct mwl8k_priv *priv;
0863ade8 4831 struct mwl8k_device_info *di;
3cc7772c
BC		 4832 int rc;
4833
4834 if (!printed_version) {
4835 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
4836 printed_version = 1;
4837 }
4838
4839
4840 rc = pci_enable_device(pdev);
4841 if (rc) {
4842 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
4843 MWL8K_NAME);
4844 return rc;
4845 }
4846
4847 rc = pci_request_regions(pdev, MWL8K_NAME);
4848 if (rc) {
4849 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
4850 MWL8K_NAME);
4851 goto err_disable_device;
4852 }
4853
4854 pci_set_master(pdev);
4855
4856
4857 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
4858 if (hw == NULL) {
4859 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
4860 rc = -ENOMEM;
4861 goto err_free_reg;
4862 }
4863
4864 SET_IEEE80211_DEV(hw, &pdev->dev);
4865 pci_set_drvdata(pdev, hw);
4866
4867 priv = hw->priv;
4868 priv->hw = hw;
4869 priv->pdev = pdev;
4870 priv->device_info = &mwl8k_info_tbl[id->driver_data];
4871
4872
4873 priv->sram = pci_iomap(pdev, 0, 0x10000);
4874 if (priv->sram == NULL) {
4875 wiphy_err(hw->wiphy, "Cannot map device SRAM\n");
4876 goto err_iounmap;
4877 }
4878
4879 /*
4880 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
4881 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
4882 */
4883 priv->regs = pci_iomap(pdev, 1, 0x10000);
4884 if (priv->regs == NULL) {
4885 priv->regs = pci_iomap(pdev, 2, 0x10000);
4886 if (priv->regs == NULL) {
4887 wiphy_err(hw->wiphy, "Cannot map device registers\n");
4888 goto err_iounmap;
4889 }
4890 }
4891
0863ade8 4892 /*
99020471
BC		 4893 * Choose the initial fw image depending on user input. If a second
4894 * image is available, make it the alternative image that will be
4895 * loaded if the first one fails.
0863ade8 4896 */
99020471 4897 init_completion(&priv->firmware_loading_complete);
0863ade8 4898 di = priv->device_info;
99020471
BC		 4899 if (ap_mode_default && di->fw_image_ap) {
4900 priv->fw_pref = di->fw_image_ap;
4901 priv->fw_alt = di->fw_image_sta;
4902 } else if (!ap_mode_default && di->fw_image_sta) {
4903 priv->fw_pref = di->fw_image_sta;
4904 priv->fw_alt = di->fw_image_ap;
4905 } else if (ap_mode_default && !di->fw_image_ap && di->fw_image_sta) {
0863ade8 4906 printk(KERN_WARNING "AP fw is unavailable. Using STA fw.");
99020471 4907 priv->fw_pref = di->fw_image_sta;
0863ade8
BC		 4908 } else if (!ap_mode_default && !di->fw_image_sta && di->fw_image_ap) {
4909 printk(KERN_WARNING "STA fw is unavailable. Using AP fw.");
99020471
BC		 4910 priv->fw_pref = di->fw_image_ap;
4911 }
4912 rc = mwl8k_init_firmware(hw, priv->fw_pref, true);
3cc7772c
BC		 4913 if (rc)
4914 goto err_stop_firmware;
99020471 4915 return rc;
3cc7772c 4916
be695fc4
LB		 4917err_stop_firmware:
4918 mwl8k_hw_reset(priv);
be695fc4
LB		 4919
4920err_iounmap:
a66098da
LB		 4921 if (priv->regs != NULL)
4922 pci_iounmap(pdev, priv->regs);
4923
5b9482dd
LB		 4924 if (priv->sram != NULL)
4925 pci_iounmap(pdev, priv->sram);
4926
a66098da
LB		 4927 pci_set_drvdata(pdev, NULL);
4928 ieee80211_free_hw(hw);
4929
4930err_free_reg:
4931 pci_release_regions(pdev);
3db95e50
LB		 4932
4933err_disable_device:
a66098da
LB		 4934 pci_disable_device(pdev);
4935
4936 return rc;
4937}
4938
230f7af0 4939static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 4940{
4941 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
4942}
4943
230f7af0 4944static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 4945{
4946 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
4947 struct mwl8k_priv *priv;
4948 int i;
4949
4950 if (hw == NULL)
4951 return;
4952 priv = hw->priv;
4953
99020471
BC		 4954 wait_for_completion(&priv->firmware_loading_complete);
4955
4956 if (priv->fw_state == FW_STATE_ERROR) {
4957 mwl8k_hw_reset(priv);
4958 goto unmap;
4959 }
4960
a66098da
LB		 4961 ieee80211_stop_queues(hw);
4962
60aa569f
LB		 4963 ieee80211_unregister_hw(hw);
4964
67e2eb27 4965 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 4966 tasklet_kill(&priv->poll_tx_task);
67e2eb27 4967 tasklet_kill(&priv->poll_rx_task);
a66098da 4968
a66098da
LB		 4969 /* Stop hardware */
4970 mwl8k_hw_reset(priv);
4971
4972 /* Return all skbs to mac80211 */
4973 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 4974 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 4975
a66098da
LB		 4976 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4977 mwl8k_txq_deinit(hw, i);
4978
4979 mwl8k_rxq_deinit(hw, 0);
4980
c2c357ce 4981 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da 4982
99020471 4983unmap:
a66098da 4984 pci_iounmap(pdev, priv->regs);
5b9482dd 4985 pci_iounmap(pdev, priv->sram);
a66098da
LB		 4986 pci_set_drvdata(pdev, NULL);
4987 ieee80211_free_hw(hw);
4988 pci_release_regions(pdev);
4989 pci_disable_device(pdev);
4990}
4991
4992static struct pci_driver mwl8k_driver = {
4993 .name = MWL8K_NAME,
45a390dd 4994 .id_table = mwl8k_pci_id_table,
a66098da
LB		 4995 .probe = mwl8k_probe,
4996 .remove = __devexit_p(mwl8k_remove),
4997 .shutdown = __devexit_p(mwl8k_shutdown),
4998};
4999
5000static int __init mwl8k_init(void)
5001{
5002 return pci_register_driver(&mwl8k_driver);
5003}
5004
5005static void __exit mwl8k_exit(void)
5006{
5007 pci_unregister_driver(&mwl8k_driver);
5008}
5009
5010module_init(mwl8k_init);
5011module_exit(mwl8k_exit);
c2c357ce
LB		 5012
5013MODULE_DESCRIPTION(MWL8K_DESC);
5014MODULE_VERSION(MWL8K_VERSION);
5015MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
5016MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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