projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mwl8k: Remove unnecessary alloc/OOM messages
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a5fb297d 5 * Copyright (C) 2008, 2009, 2010 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
a6b7a407 13#include <linux/interrupt.h>
a66098da
LB		 14#include <linux/module.h>
15#include <linux/kernel.h>
3d76e82c 16#include <linux/sched.h>
a66098da
LB		 17#include <linux/spinlock.h>
18#include <linux/list.h>
19#include <linux/pci.h>
20#include <linux/delay.h>
21#include <linux/completion.h>
22#include <linux/etherdevice.h>
5a0e3ad6 23#include <linux/slab.h>
a66098da
LB		 24#include <net/mac80211.h>
25#include <linux/moduleparam.h>
26#include <linux/firmware.h>
27#include <linux/workqueue.h>
28
29#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
30#define MWL8K_NAME KBUILD_MODNAME
00e8e692 31#define MWL8K_VERSION "0.13"
a66098da 32
0863ade8 33/* Module parameters */
eb939922 34static bool ap_mode_default;
0863ade8
BC		 35module_param(ap_mode_default, bool, 0);
36MODULE_PARM_DESC(ap_mode_default,
37 "Set to 1 to make ap mode the default instead of sta mode");
38
a66098da
LB		 39/* Register definitions */
40#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 41#define MWL8K_MODE_STA 0x0000005a
42#define MWL8K_MODE_AP 0x000000a5
a66098da 43#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 44#define MWL8K_FWSTA_READY 0xf0f1f2f4
45#define MWL8K_FWAP_READY 0xf1f2f4a5
46#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 47#define MWL8K_HIU_SCRATCH 0x00000c40
48
49/* Host->device communications */
50#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
51#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
52#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
53#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
54#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 55#define MWL8K_H2A_INT_DUMMY (1 << 20)
56#define MWL8K_H2A_INT_RESET (1 << 15)
57#define MWL8K_H2A_INT_DOORBELL (1 << 1)
58#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 59
60/* Device->host communications */
61#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
62#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
63#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
64#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
65#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b 66#define MWL8K_A2H_INT_DUMMY (1 << 20)
3aefc37e 67#define MWL8K_A2H_INT_BA_WATCHDOG (1 << 14)
ce9e2e1b
LB		 68#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
69#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
70#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
71#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
72#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
73#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
74#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
75#define MWL8K_A2H_INT_RX_READY (1 << 1)
76#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da 77
566875db
PN		 78/* HW micro second timer register
79 * located at offset 0xA600. This
80 * will be used to timestamp tx
81 * packets.
82 */
83
84#define MWL8K_HW_TIMER_REGISTER 0x0000a600
85
a66098da
LB		 86#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
87 MWL8K_A2H_INT_CHNL_SWITCHED | \
88 MWL8K_A2H_INT_QUEUE_EMPTY | \
89 MWL8K_A2H_INT_RADAR_DETECT | \
90 MWL8K_A2H_INT_RADIO_ON | \
91 MWL8K_A2H_INT_RADIO_OFF | \
92 MWL8K_A2H_INT_MAC_EVENT | \
93 MWL8K_A2H_INT_OPC_DONE | \
94 MWL8K_A2H_INT_RX_READY | \
3aefc37e
NS		 95 MWL8K_A2H_INT_TX_DONE | \
96 MWL8K_A2H_INT_BA_WATCHDOG)
a66098da 97
a66098da 98#define MWL8K_RX_QUEUES 1
e600707b 99#define MWL8K_TX_WMM_QUEUES 4
8a7a578c 100#define MWL8K_MAX_AMPDU_QUEUES 8
e600707b
BC		 101#define MWL8K_MAX_TX_QUEUES (MWL8K_TX_WMM_QUEUES + MWL8K_MAX_AMPDU_QUEUES)
102#define mwl8k_tx_queues(priv) (MWL8K_TX_WMM_QUEUES + (priv)->num_ampdu_queues)
a66098da 103
7fb978b7
YAP		 104/* txpriorities are mapped with hw queues.
105 * Each hw queue has a txpriority.
106 */
107#define TOTAL_HW_TX_QUEUES 8
108
109/* Each HW queue can have one AMPDU stream.
110 * But, because one of the hw queue is reserved,
111 * maximum AMPDU queues that can be created are
112 * one short of total tx queues.
113 */
114#define MWL8K_NUM_AMPDU_STREAMS (TOTAL_HW_TX_QUEUES - 1)
115
54bc3a0d
LB		 116struct rxd_ops {
117 int rxd_size;
118 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
119 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d 120 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
0d462bbb 121 __le16 *qos, s8 *noise);
54bc3a0d
LB		 122};
123
45a390dd 124struct mwl8k_device_info {
a74b295e
LB		 125 char *part_name;
126 char *helper_image;
0863ade8
BC		 127 char *fw_image_sta;
128 char *fw_image_ap;
89a91f4f 129 struct rxd_ops *ap_rxd_ops;
952a0e96 130 u32 fw_api_ap;
45a390dd
LB		 131};
132
a66098da 133struct mwl8k_rx_queue {
45eb400d 134 int rxd_count;
a66098da
LB		 135
136 /* hw receives here */
45eb400d 137 int head;
a66098da
LB		 138
139 /* refill descs here */
45eb400d 140 int tail;
a66098da 141
54bc3a0d 142 void *rxd;
45eb400d 143 dma_addr_t rxd_dma;
788838eb
LB		 144 struct {
145 struct sk_buff *skb;
53b1b3e1 146 DEFINE_DMA_UNMAP_ADDR(dma);
788838eb 147 } *buf;
a66098da
LB		 148};
149
a66098da
LB		 150struct mwl8k_tx_queue {
151 /* hw transmits here */
45eb400d 152 int head;
a66098da
LB		 153
154 /* sw appends here */
45eb400d 155 int tail;
a66098da 156
8ccbc3b8 157 unsigned int len;
45eb400d
LB		 158 struct mwl8k_tx_desc *txd;
159 dma_addr_t txd_dma;
160 struct sk_buff **skb;
a66098da
LB		 161};
162
ac109fd0
BC		 163enum {
164 AMPDU_NO_STREAM,
165 AMPDU_STREAM_NEW,
166 AMPDU_STREAM_IN_PROGRESS,
167 AMPDU_STREAM_ACTIVE,
168};
169
5faa1aff
NS		 170struct mwl8k_ampdu_stream {
171 struct ieee80211_sta *sta;
172 u8 tid;
173 u8 state;
174 u8 idx;
5faa1aff
NS		 175};
176
a66098da 177struct mwl8k_priv {
a66098da 178 struct ieee80211_hw *hw;
a66098da 179 struct pci_dev *pdev;
bf3ca7f7 180 int irq;
a66098da 181
45a390dd
LB		 182 struct mwl8k_device_info *device_info;
183
be695fc4
LB		 184 void __iomem *sram;
185 void __iomem *regs;
186
187 /* firmware */
d1f9e41d
BC		 188 const struct firmware *fw_helper;
189 const struct firmware *fw_ucode;
a66098da 190
be695fc4
LB		 191 /* hardware/firmware parameters */
192 bool ap_fw;
193 struct rxd_ops *rxd_ops;
777ad375
LB		 194 struct ieee80211_supported_band band_24;
195 struct ieee80211_channel channels_24[14];
196 struct ieee80211_rate rates_24[14];
4eae9edd
LB		 197 struct ieee80211_supported_band band_50;
198 struct ieee80211_channel channels_50[4];
199 struct ieee80211_rate rates_50[9];
ee0ddf18
LB		 200 u32 ap_macids_supported;
201 u32 sta_macids_supported;
be695fc4 202
8a7a578c
BC		 203 /* Ampdu stream information */
204 u8 num_ampdu_queues;
ac109fd0
BC		 205 spinlock_t stream_lock;
206 struct mwl8k_ampdu_stream ampdu[MWL8K_MAX_AMPDU_QUEUES];
3aefc37e 207 struct work_struct watchdog_ba_handle;
8a7a578c 208
618952a7
LB		 209 /* firmware access */
210 struct mutex fw_mutex;
211 struct task_struct *fw_mutex_owner;
6b6accc3 212 struct task_struct *hw_restart_owner;
618952a7 213 int fw_mutex_depth;
618952a7
LB		 214 struct completion *hostcmd_wait;
215
c27a54d3
YAP		 216 atomic_t watchdog_event_pending;
217
a66098da
LB		 218 /* lock held over TX and TX reap */
219 spinlock_t tx_lock;
a66098da 220
88de754a
LB		 221 /* TX quiesce completion, protected by fw_mutex and tx_lock */
222 struct completion *tx_wait;
223
f5bb87cf 224 /* List of interfaces. */
ee0ddf18 225 u32 macids_used;
f5bb87cf 226 struct list_head vif_list;
a66098da 227
a66098da
LB		 228 /* power management status cookie from firmware */
229 u32 *cookie;
230 dma_addr_t cookie_dma;
231
232 u16 num_mcaddrs;
a66098da 233 u8 hw_rev;
2aa7b01f 234 u32 fw_rev;
a66098da
LB		 235
236 /*
237 * Running count of TX packets in flight, to avoid
238 * iterating over the transmit rings each time.
239 */
240 int pending_tx_pkts;
241
242 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
e600707b
BC		 243 struct mwl8k_tx_queue txq[MWL8K_MAX_TX_QUEUES];
244 u32 txq_offset[MWL8K_MAX_TX_QUEUES];
a66098da 245
c46563b7 246 bool radio_on;
68ce3884 247 bool radio_short_preamble;
a43c49a8 248 bool sniffer_enabled;
0439b1f5 249 bool wmm_enabled;
a66098da 250
a66098da
LB		 251 /* XXX need to convert this to handle multiple interfaces */
252 bool capture_beacon;
d89173f2 253 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 254 struct sk_buff *beacon_skb;
255
256 /*
257 * This FJ worker has to be global as it is scheduled from the
258 * RX handler. At this point we don't know which interface it
259 * belongs to until the list of bssids waiting to complete join
260 * is checked.
261 */
262 struct work_struct finalize_join_worker;
263
1e9f9de3
LB		 264 /* Tasklet to perform TX reclaim. */
265 struct tasklet_struct poll_tx_task;
67e2eb27
LB		 266
267 /* Tasklet to perform RX. */
268 struct tasklet_struct poll_rx_task;
0d462bbb
JL		 269
270 /* Most recently reported noise in dBm */
271 s8 noise;
0863ade8
BC		 272
273 /*
274 * preserve the queue configurations so they can be restored if/when
275 * the firmware image is swapped.
276 */
e600707b 277 struct ieee80211_tx_queue_params wmm_params[MWL8K_TX_WMM_QUEUES];
99020471 278
6b6accc3
YAP		 279 /* To perform the task of reloading the firmware */
280 struct work_struct fw_reload;
281 bool hw_restart_in_progress;
282
99020471
BC		 283 /* async firmware loading state */
284 unsigned fw_state;
285 char *fw_pref;
286 char *fw_alt;
287 struct completion firmware_loading_complete;
e882efc9
YAP		 288
289 /* bitmap of running BSSes */
290 u32 running_bsses;
a66098da
LB		 291};
292
e53d9b96
NS		 293#define MAX_WEP_KEY_LEN 13
294#define NUM_WEP_KEYS 4
295
a66098da
LB		 296/* Per interface specific private data */
297struct mwl8k_vif {
f5bb87cf
LB		 298 struct list_head list;
299 struct ieee80211_vif *vif;
300
f57ca9c1
LB		 301 /* Firmware macid for this vif. */
302 int macid;
303
c2c2b12a 304 /* Non AMPDU sequence number assigned by driver. */
a680400e 305 u16 seqno;
e53d9b96
NS		 306
307 /* Saved WEP keys */
308 struct {
309 u8 enabled;
310 u8 key[sizeof(struct ieee80211_key_conf) + MAX_WEP_KEY_LEN];
311 } wep_key_conf[NUM_WEP_KEYS];
d9a07d49
NS		 312
313 /* BSSID */
314 u8 bssid[ETH_ALEN];
315
316 /* A flag to indicate is HW crypto is enabled for this bssid */
317 bool is_hw_crypto_enabled;
a66098da 318};
a94cc97e 319#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
fcdc403c 320#define IEEE80211_KEY_CONF(_u8) ((struct ieee80211_key_conf *)(_u8))
a66098da 321
d0805c1c
BC		 322struct tx_traffic_info {
323 u32 start_time;
324 u32 pkts;
325};
326
327#define MWL8K_MAX_TID 8
a680400e
LB		 328struct mwl8k_sta {
329 /* Index into station database. Returned by UPDATE_STADB. */
330 u8 peer_id;
17033543 331 u8 is_ampdu_allowed;
d0805c1c 332 struct tx_traffic_info tx_stats[MWL8K_MAX_TID];
a680400e
LB		 333};
334#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
335
777ad375 336static const struct ieee80211_channel mwl8k_channels_24[] = {
a66098da
LB		 337 { .center_freq = 2412, .hw_value = 1, },
338 { .center_freq = 2417, .hw_value = 2, },
339 { .center_freq = 2422, .hw_value = 3, },
340 { .center_freq = 2427, .hw_value = 4, },
341 { .center_freq = 2432, .hw_value = 5, },
342 { .center_freq = 2437, .hw_value = 6, },
343 { .center_freq = 2442, .hw_value = 7, },
344 { .center_freq = 2447, .hw_value = 8, },
345 { .center_freq = 2452, .hw_value = 9, },
346 { .center_freq = 2457, .hw_value = 10, },
347 { .center_freq = 2462, .hw_value = 11, },
647ca6b0
LB		 348 { .center_freq = 2467, .hw_value = 12, },
349 { .center_freq = 2472, .hw_value = 13, },
350 { .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 351};
352
777ad375 353static const struct ieee80211_rate mwl8k_rates_24[] = {
a66098da
LB		 354 { .bitrate = 10, .hw_value = 2, },
355 { .bitrate = 20, .hw_value = 4, },
356 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 357 { .bitrate = 110, .hw_value = 22, },
358 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 359 { .bitrate = 60, .hw_value = 12, },
360 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 361 { .bitrate = 120, .hw_value = 24, },
362 { .bitrate = 180, .hw_value = 36, },
363 { .bitrate = 240, .hw_value = 48, },
364 { .bitrate = 360, .hw_value = 72, },
365 { .bitrate = 480, .hw_value = 96, },
366 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 367 { .bitrate = 720, .hw_value = 144, },
368};
369
4eae9edd
LB		 370static const struct ieee80211_channel mwl8k_channels_50[] = {
371 { .center_freq = 5180, .hw_value = 36, },
372 { .center_freq = 5200, .hw_value = 40, },
373 { .center_freq = 5220, .hw_value = 44, },
374 { .center_freq = 5240, .hw_value = 48, },
375};
376
377static const struct ieee80211_rate mwl8k_rates_50[] = {
378 { .bitrate = 60, .hw_value = 12, },
379 { .bitrate = 90, .hw_value = 18, },
380 { .bitrate = 120, .hw_value = 24, },
381 { .bitrate = 180, .hw_value = 36, },
382 { .bitrate = 240, .hw_value = 48, },
383 { .bitrate = 360, .hw_value = 72, },
384 { .bitrate = 480, .hw_value = 96, },
385 { .bitrate = 540, .hw_value = 108, },
386 { .bitrate = 720, .hw_value = 144, },
387};
388
a66098da 389/* Set or get info from Firmware */
a66098da 390#define MWL8K_CMD_GET 0x0000
41fdf097
NS		 391#define MWL8K_CMD_SET 0x0001
392#define MWL8K_CMD_SET_LIST 0x0002
a66098da
LB		 393
394/* Firmware command codes */
395#define MWL8K_CMD_CODE_DNLD 0x0001
396#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 397#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 398#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
399#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 400#define MWL8K_CMD_RADIO_CONTROL 0x001c
401#define MWL8K_CMD_RF_TX_POWER 0x001e
41fdf097 402#define MWL8K_CMD_TX_POWER 0x001f
08b06347 403#define MWL8K_CMD_RF_ANTENNA 0x0020
aa21d0f6 404#define MWL8K_CMD_SET_BEACON 0x0100 /* per-vif */
a66098da
LB		 405#define MWL8K_CMD_SET_PRE_SCAN 0x0107
406#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 407#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
408#define MWL8K_CMD_SET_AID 0x010d
409#define MWL8K_CMD_SET_RATE 0x0110
410#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
411#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 412#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 413#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
414#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 415#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 416#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 417#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
aa21d0f6 418#define MWL8K_CMD_SET_MAC_ADDR 0x0202 /* per-vif */
a66098da 419#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
3aefc37e 420#define MWL8K_CMD_GET_WATCHDOG_BITMAP 0x0205
197a4e4e 421#define MWL8K_CMD_DEL_MAC_ADDR 0x0206 /* per-vif */
aa21d0f6
LB		 422#define MWL8K_CMD_BSS_START 0x1100 /* per-vif */
423#define MWL8K_CMD_SET_NEW_STN 0x1111 /* per-vif */
fcdc403c 424#define MWL8K_CMD_UPDATE_ENCRYPTION 0x1122 /* per-vif */
ff45fc60 425#define MWL8K_CMD_UPDATE_STADB 0x1123
5faa1aff 426#define MWL8K_CMD_BASTREAM 0x1125
a66098da 427
b603742f 428static const char *mwl8k_cmd_name(__le16 cmd, char *buf, int bufsize)
a66098da 429{
b603742f
JL		 430 u16 command = le16_to_cpu(cmd);
431
a66098da
LB		 432#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
433 snprintf(buf, bufsize, "%s", #x);\
434 return buf;\
435 } while (0)
b603742f 436 switch (command & ~0x8000) {
a66098da
LB		 437 MWL8K_CMDNAME(CODE_DNLD);
438 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 439 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 440 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
441 MWL8K_CMDNAME(GET_STAT);
442 MWL8K_CMDNAME(RADIO_CONTROL);
443 MWL8K_CMDNAME(RF_TX_POWER);
41fdf097 444 MWL8K_CMDNAME(TX_POWER);
08b06347 445 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 446 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB		 447 MWL8K_CMDNAME(SET_PRE_SCAN);
448 MWL8K_CMDNAME(SET_POST_SCAN);
449 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 450 MWL8K_CMDNAME(SET_AID);
451 MWL8K_CMDNAME(SET_RATE);
452 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
453 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 454 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 455 MWL8K_CMDNAME(SET_EDCA_PARAMS);
456 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 457 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 458 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 459 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 460 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 461 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 462 MWL8K_CMDNAME(BSS_START);
3f5610ff 463 MWL8K_CMDNAME(SET_NEW_STN);
fcdc403c 464 MWL8K_CMDNAME(UPDATE_ENCRYPTION);
ff45fc60 465 MWL8K_CMDNAME(UPDATE_STADB);
5faa1aff 466 MWL8K_CMDNAME(BASTREAM);
3aefc37e 467 MWL8K_CMDNAME(GET_WATCHDOG_BITMAP);
a66098da
LB		 468 default:
469 snprintf(buf, bufsize, "0x%x", cmd);
470 }
471#undef MWL8K_CMDNAME
472
473 return buf;
474}
475
476/* Hardware and firmware reset */
477static void mwl8k_hw_reset(struct mwl8k_priv *priv)
478{
479 iowrite32(MWL8K_H2A_INT_RESET,
480 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
481 iowrite32(MWL8K_H2A_INT_RESET,
482 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
483 msleep(20);
484}
485
486/* Release fw image */
d1f9e41d 487static void mwl8k_release_fw(const struct firmware **fw)
a66098da
LB		 488{
489 if (*fw == NULL)
490 return;
491 release_firmware(*fw);
492 *fw = NULL;
493}
494
495static void mwl8k_release_firmware(struct mwl8k_priv *priv)
496{
22be40d9
LB		 497 mwl8k_release_fw(&priv->fw_ucode);
498 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 499}
500
99020471
BC		 501/* states for asynchronous f/w loading */
502static void mwl8k_fw_state_machine(const struct firmware *fw, void *context);
503enum {
504 FW_STATE_INIT = 0,
505 FW_STATE_LOADING_PREF,
506 FW_STATE_LOADING_ALT,
507 FW_STATE_ERROR,
508};
509
a66098da
LB		 510/* Request fw image */
511static int mwl8k_request_fw(struct mwl8k_priv *priv,
d1f9e41d 512 const char *fname, const struct firmware **fw,
99020471 513 bool nowait)
a66098da
LB		 514{
515 /* release current image */
516 if (*fw != NULL)
517 mwl8k_release_fw(fw);
518
99020471
BC		 519 if (nowait)
520 return request_firmware_nowait(THIS_MODULE, 1, fname,
521 &priv->pdev->dev, GFP_KERNEL,
522 priv, mwl8k_fw_state_machine);
523 else
d1f9e41d 524 return request_firmware(fw, fname, &priv->pdev->dev);
a66098da
LB		 525}
526
99020471
BC		 527static int mwl8k_request_firmware(struct mwl8k_priv *priv, char *fw_image,
528 bool nowait)
a66098da 529{
a74b295e 530 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 531 int rc;
532
a74b295e 533 if (di->helper_image != NULL) {
99020471
BC		 534 if (nowait)
535 rc = mwl8k_request_fw(priv, di->helper_image,
536 &priv->fw_helper, true);
537 else
538 rc = mwl8k_request_fw(priv, di->helper_image,
539 &priv->fw_helper, false);
540 if (rc)
541 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
542 pci_name(priv->pdev), di->helper_image);
543
544 if (rc || nowait)
a74b295e 545 return rc;
a66098da
LB		 546 }
547
99020471
BC		 548 if (nowait) {
549 /*
550 * if we get here, no helper image is needed. Skip the
551 * FW_STATE_INIT state.
552 */
553 priv->fw_state = FW_STATE_LOADING_PREF;
554 rc = mwl8k_request_fw(priv, fw_image,
555 &priv->fw_ucode,
556 true);
557 } else
558 rc = mwl8k_request_fw(priv, fw_image,
559 &priv->fw_ucode, false);
a66098da 560 if (rc) {
c2c357ce 561 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
0863ade8 562 pci_name(priv->pdev), fw_image);
22be40d9 563 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 564 return rc;
565 }
566
567 return 0;
568}
569
570struct mwl8k_cmd_pkt {
571 __le16 code;
572 __le16 length;
f57ca9c1
LB		 573 __u8 seq_num;
574 __u8 macid;
a66098da
LB		 575 __le16 result;
576 char payload[0];
ba2d3587 577} __packed;
a66098da
LB		 578
579/*
580 * Firmware loading.
581 */
582static int
583mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
584{
585 void __iomem *regs = priv->regs;
586 dma_addr_t dma_addr;
a66098da
LB		 587 int loops;
588
589 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
590 if (pci_dma_mapping_error(priv->pdev, dma_addr))
591 return -ENOMEM;
592
593 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
594 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
595 iowrite32(MWL8K_H2A_INT_DOORBELL,
596 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
597 iowrite32(MWL8K_H2A_INT_DUMMY,
598 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
599
a66098da
LB		 600 loops = 1000;
601 do {
602 u32 int_code;
603
604 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
605 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
606 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 607 break;
608 }
609
3d76e82c 610 cond_resched();
a66098da
LB		 611 udelay(1);
612 } while (--loops);
613
614 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
615
d4b70570 616 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 617}
618
619static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
620 const u8 *data, size_t length)
621{
622 struct mwl8k_cmd_pkt *cmd;
623 int done;
624 int rc = 0;
625
626 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
627 if (cmd == NULL)
628 return -ENOMEM;
629
630 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
631 cmd->seq_num = 0;
f57ca9c1 632 cmd->macid = 0;
a66098da
LB		 633 cmd->result = 0;
634
635 done = 0;
636 while (length) {
637 int block_size = length > 256 ? 256 : length;
638
639 memcpy(cmd->payload, data + done, block_size);
640 cmd->length = cpu_to_le16(block_size);
641
642 rc = mwl8k_send_fw_load_cmd(priv, cmd,
643 sizeof(*cmd) + block_size);
644 if (rc)
645 break;
646
647 done += block_size;
648 length -= block_size;
649 }
650
651 if (!rc) {
652 cmd->length = 0;
653 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
654 }
655
656 kfree(cmd);
657
658 return rc;
659}
660
661static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
662 const u8 *data, size_t length)
663{
664 unsigned char *buffer;
665 int may_continue, rc = 0;
666 u32 done, prev_block_size;
667
668 buffer = kmalloc(1024, GFP_KERNEL);
669 if (buffer == NULL)
670 return -ENOMEM;
671
672 done = 0;
673 prev_block_size = 0;
674 may_continue = 1000;
675 while (may_continue > 0) {
676 u32 block_size;
677
678 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
679 if (block_size & 1) {
680 block_size &= ~1;
681 may_continue--;
682 } else {
683 done += prev_block_size;
684 length -= prev_block_size;
685 }
686
687 if (block_size > 1024 || block_size > length) {
688 rc = -EOVERFLOW;
689 break;
690 }
691
692 if (length == 0) {
693 rc = 0;
694 break;
695 }
696
697 if (block_size == 0) {
698 rc = -EPROTO;
699 may_continue--;
700 udelay(1);
701 continue;
702 }
703
704 prev_block_size = block_size;
705 memcpy(buffer, data + done, block_size);
706
707 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
708 if (rc)
709 break;
710 }
711
712 if (!rc && length != 0)
713 rc = -EREMOTEIO;
714
715 kfree(buffer);
716
717 return rc;
718}
719
c2c357ce 720static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 721{
c2c357ce 722 struct mwl8k_priv *priv = hw->priv;
d1f9e41d 723 const struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 724 int rc;
725 int loops;
726
727 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
d1f9e41d 728 const struct firmware *helper = priv->fw_helper;
a66098da 729
c2c357ce
LB		 730 if (helper == NULL) {
731 printk(KERN_ERR "%s: helper image needed but none "
732 "given\n", pci_name(priv->pdev));
733 return -EINVAL;
734 }
a66098da 735
c2c357ce 736 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 737 if (rc) {
738 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 739 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 740 return rc;
741 }
ba30c4a5 742 msleep(20);
a66098da 743
c2c357ce 744 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 745 } else {
c2c357ce 746 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 747 }
748
749 if (rc) {
c2c357ce
LB		 750 printk(KERN_ERR "%s: unable to load firmware image\n",
751 pci_name(priv->pdev));
a66098da
LB		 752 return rc;
753 }
754
89a91f4f 755 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 756
89b872e2 757 loops = 500000;
a66098da 758 do {
eae74e65
LB		 759 u32 ready_code;
760
761 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
762 if (ready_code == MWL8K_FWAP_READY) {
3db1cd5c 763 priv->ap_fw = true;
eae74e65
LB		 764 break;
765 } else if (ready_code == MWL8K_FWSTA_READY) {
3db1cd5c 766 priv->ap_fw = false;
a66098da 767 break;
eae74e65
LB		 768 }
769
770 cond_resched();
a66098da
LB		 771 udelay(1);
772 } while (--loops);
773
774 return loops ? 0 : -ETIMEDOUT;
775}
776
777
a66098da
LB		 778/* DMA header used by firmware and hardware. */
779struct mwl8k_dma_data {
780 __le16 fwlen;
781 struct ieee80211_hdr wh;
20f09c3d 782 char data[0];
ba2d3587 783} __packed;
a66098da
LB		 784
785/* Routines to add/remove DMA header from skb. */
20f09c3d 786static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 787{
20f09c3d
LB		 788 struct mwl8k_dma_data *tr;
789 int hdrlen;
790
791 tr = (struct mwl8k_dma_data *)skb->data;
792 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
793
794 if (hdrlen != sizeof(tr->wh)) {
795 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
796 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
797 *((__le16 *)(tr->data - 2)) = qos;
798 } else {
799 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
800 }
a66098da 801 }
20f09c3d
LB		 802
803 if (hdrlen != sizeof(*tr))
804 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 805}
806
ff776cec
YAP		 807#define REDUCED_TX_HEADROOM 8
808
252486a1 809static void
e4eefec7
YAP		 810mwl8k_add_dma_header(struct mwl8k_priv *priv, struct sk_buff *skb,
811 int head_pad, int tail_pad)
a66098da
LB		 812{
813 struct ieee80211_hdr *wh;
ca009301 814 int hdrlen;
252486a1 815 int reqd_hdrlen;
a66098da
LB		 816 struct mwl8k_dma_data *tr;
817
ca009301
LB		 818 /*
819 * Add a firmware DMA header; the firmware requires that we
820 * present a 2-byte payload length followed by a 4-address
821 * header (without QoS field), followed (optionally) by any
822 * WEP/ExtIV header (but only filled in for CCMP).
823 */
a66098da 824 wh = (struct ieee80211_hdr *)skb->data;
ca009301 825
a66098da 826 hdrlen = ieee80211_hdrlen(wh->frame_control);
ff776cec
YAP		 827
828 /*
829 * Check if skb_resize is required because of
830 * tx_headroom adjustment.
831 */
832 if (priv->ap_fw && (hdrlen < (sizeof(struct ieee80211_cts)
833 + REDUCED_TX_HEADROOM))) {
834 if (pskb_expand_head(skb, REDUCED_TX_HEADROOM, 0, GFP_ATOMIC)) {
835
836 wiphy_err(priv->hw->wiphy,
837 "Failed to reallocate TX buffer\n");
838 return;
839 }
840 skb->truesize += REDUCED_TX_HEADROOM;
841 }
842
e4eefec7 843 reqd_hdrlen = sizeof(*tr) + head_pad;
252486a1
NS		 844
845 if (hdrlen != reqd_hdrlen)
846 skb_push(skb, reqd_hdrlen - hdrlen);
a66098da 847
ca009301 848 if (ieee80211_is_data_qos(wh->frame_control))
252486a1 849 hdrlen -= IEEE80211_QOS_CTL_LEN;
a66098da
LB		 850
851 tr = (struct mwl8k_dma_data *)skb->data;
852 if (wh != &tr->wh)
853 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 854 if (hdrlen != sizeof(tr->wh))
855 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 856
857 /*
858 * Firmware length is the length of the fully formed "802.11
859 * payload". That is, everything except for the 802.11 header.
860 * This includes all crypto material including the MIC.
861 */
252486a1 862 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr) + tail_pad);
a66098da
LB		 863}
864
ff776cec
YAP		 865static void mwl8k_encapsulate_tx_frame(struct mwl8k_priv *priv,
866 struct sk_buff *skb)
e53d9b96
NS		 867{
868 struct ieee80211_hdr *wh;
869 struct ieee80211_tx_info *tx_info;
870 struct ieee80211_key_conf *key_conf;
871 int data_pad;
e4eefec7 872 int head_pad = 0;
e53d9b96
NS		 873
874 wh = (struct ieee80211_hdr *)skb->data;
875
876 tx_info = IEEE80211_SKB_CB(skb);
877
878 key_conf = NULL;
879 if (ieee80211_is_data(wh->frame_control))
880 key_conf = tx_info->control.hw_key;
881
882 /*
883 * Make sure the packet header is in the DMA header format (4-address
e4eefec7 884 * without QoS), and add head & tail padding when HW crypto is enabled.
e53d9b96
NS		 885 *
886 * We have the following trailer padding requirements:
887 * - WEP: 4 trailer bytes (ICV)
888 * - TKIP: 12 trailer bytes (8 MIC + 4 ICV)
889 * - CCMP: 8 trailer bytes (MIC)
890 */
891 data_pad = 0;
892 if (key_conf != NULL) {
e4eefec7 893 head_pad = key_conf->iv_len;
e53d9b96
NS		 894 switch (key_conf->cipher) {
895 case WLAN_CIPHER_SUITE_WEP40:
896 case WLAN_CIPHER_SUITE_WEP104:
897 data_pad = 4;
898 break;
899 case WLAN_CIPHER_SUITE_TKIP:
900 data_pad = 12;
901 break;
902 case WLAN_CIPHER_SUITE_CCMP:
903 data_pad = 8;
904 break;
905 }
906 }
e4eefec7 907 mwl8k_add_dma_header(priv, skb, head_pad, data_pad);
e53d9b96 908}
a66098da
LB		 909
910/*
89a91f4f 911 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 912 */
89a91f4f 913struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB		 914 __le16 pkt_len;
915 __u8 sq2;
916 __u8 rate;
917 __le32 pkt_phys_addr;
918 __le32 next_rxd_phys_addr;
919 __le16 qos_control;
920 __le16 htsig2;
921 __le32 hw_rssi_info;
922 __le32 hw_noise_floor_info;
923 __u8 noise_floor;
924 __u8 pad0[3];
925 __u8 rssi;
926 __u8 rx_status;
927 __u8 channel;
928 __u8 rx_ctrl;
ba2d3587 929} __packed;
6f6d1e9a 930
89a91f4f
LB		 931#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
932#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
933#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 934
89a91f4f 935#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 936
d9a07d49
NS		 937/* 8366 AP rx_status bits */
938#define MWL8K_8366_AP_RXSTAT_DECRYPT_ERR_MASK 0x80
939#define MWL8K_8366_AP_RXSTAT_GENERAL_DECRYPT_ERR 0xFF
940#define MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR 0x02
941#define MWL8K_8366_AP_RXSTAT_WEP_DECRYPT_ICV_ERR 0x04
942#define MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_ICV_ERR 0x08
943
89a91f4f 944static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 945{
89a91f4f 946 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 947
948 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 949 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 950}
951
89a91f4f 952static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 953{
89a91f4f 954 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 955
956 rxd->pkt_len = cpu_to_le16(len);
957 rxd->pkt_phys_addr = cpu_to_le32(addr);
958 wmb();
959 rxd->rx_ctrl = 0;
960}
961
962static int
89a91f4f 963mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 964 __le16 *qos, s8 *noise)
6f6d1e9a 965{
89a91f4f 966 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 967
89a91f4f 968 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 969 return -1;
970 rmb();
971
972 memset(status, 0, sizeof(*status));
973
974 status->signal = -rxd->rssi;
0d462bbb 975 *noise = -rxd->noise_floor;
6f6d1e9a 976
89a91f4f 977 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 978 status->flag |= RX_FLAG_HT;
89a91f4f 979 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 980 status->flag |= RX_FLAG_40MHZ;
89a91f4f 981 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 982 } else {
983 int i;
984
777ad375
LB		 985 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
986 if (mwl8k_rates_24[i].hw_value == rxd->rate) {
6f6d1e9a
LB		 987 status->rate_idx = i;
988 break;
989 }
990 }
991 }
992
85478344
LB		 993 if (rxd->channel > 14) {
994 status->band = IEEE80211_BAND_5GHZ;
995 if (!(status->flag & RX_FLAG_HT))
996 status->rate_idx -= 5;
997 } else {
998 status->band = IEEE80211_BAND_2GHZ;
999 }
59eb21a6
BR		 1000 status->freq = ieee80211_channel_to_frequency(rxd->channel,
1001 status->band);
6f6d1e9a 1002
20f09c3d
LB		 1003 *qos = rxd->qos_control;
1004
d9a07d49
NS		 1005 if ((rxd->rx_status != MWL8K_8366_AP_RXSTAT_GENERAL_DECRYPT_ERR) &&
1006 (rxd->rx_status & MWL8K_8366_AP_RXSTAT_DECRYPT_ERR_MASK) &&
1007 (rxd->rx_status & MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR))
1008 status->flag |= RX_FLAG_MMIC_ERROR;
1009
6f6d1e9a
LB		 1010 return le16_to_cpu(rxd->pkt_len);
1011}
1012
89a91f4f
LB		 1013static struct rxd_ops rxd_8366_ap_ops = {
1014 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
1015 .rxd_init = mwl8k_rxd_8366_ap_init,
1016 .rxd_refill = mwl8k_rxd_8366_ap_refill,
1017 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB		 1018};
1019
1020/*
89a91f4f 1021 * Packet reception for STA firmware.
a66098da 1022 */
89a91f4f 1023struct mwl8k_rxd_sta {
a66098da
LB		 1024 __le16 pkt_len;
1025 __u8 link_quality;
1026 __u8 noise_level;
1027 __le32 pkt_phys_addr;
45eb400d 1028 __le32 next_rxd_phys_addr;
a66098da
LB		 1029 __le16 qos_control;
1030 __le16 rate_info;
1031 __le32 pad0[4];
1032 __u8 rssi;
1033 __u8 channel;
1034 __le16 pad1;
1035 __u8 rx_ctrl;
1036 __u8 rx_status;
1037 __u8 pad2[2];
ba2d3587 1038} __packed;
a66098da 1039
89a91f4f
LB		 1040#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
1041#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
1042#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
1043#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
1044#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
1045#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 1046
89a91f4f 1047#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
d9a07d49
NS		 1048#define MWL8K_STA_RX_CTRL_DECRYPT_ERROR 0x04
1049/* ICV=0 or MIC=1 */
1050#define MWL8K_STA_RX_CTRL_DEC_ERR_TYPE 0x08
1051/* Key is uploaded only in failure case */
1052#define MWL8K_STA_RX_CTRL_KEY_INDEX 0x30
54bc3a0d 1053
89a91f4f 1054static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 1055{
89a91f4f 1056 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1057
1058 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 1059 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 1060}
1061
89a91f4f 1062static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 1063{
89a91f4f 1064 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1065
1066 rxd->pkt_len = cpu_to_le16(len);
1067 rxd->pkt_phys_addr = cpu_to_le32(addr);
1068 wmb();
1069 rxd->rx_ctrl = 0;
1070}
1071
1072static int
89a91f4f 1073mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 1074 __le16 *qos, s8 *noise)
54bc3a0d 1075{
89a91f4f 1076 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1077 u16 rate_info;
1078
89a91f4f 1079 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 1080 return -1;
1081 rmb();
1082
1083 rate_info = le16_to_cpu(rxd->rate_info);
1084
1085 memset(status, 0, sizeof(*status));
1086
1087 status->signal = -rxd->rssi;
0d462bbb 1088 *noise = -rxd->noise_level;
89a91f4f
LB		 1089 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
1090 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 1091
89a91f4f 1092 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 1093 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 1094 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 1095 status->flag |= RX_FLAG_40MHZ;
89a91f4f 1096 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 1097 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 1098 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 1099 status->flag |= RX_FLAG_HT;
1100
85478344
LB		 1101 if (rxd->channel > 14) {
1102 status->band = IEEE80211_BAND_5GHZ;
1103 if (!(status->flag & RX_FLAG_HT))
1104 status->rate_idx -= 5;
1105 } else {
1106 status->band = IEEE80211_BAND_2GHZ;
1107 }
59eb21a6
BR		 1108 status->freq = ieee80211_channel_to_frequency(rxd->channel,
1109 status->band);
54bc3a0d 1110
20f09c3d 1111 *qos = rxd->qos_control;
d9a07d49
NS		 1112 if ((rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DECRYPT_ERROR) &&
1113 (rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DEC_ERR_TYPE))
1114 status->flag |= RX_FLAG_MMIC_ERROR;
20f09c3d 1115
54bc3a0d
LB		 1116 return le16_to_cpu(rxd->pkt_len);
1117}
1118
89a91f4f
LB		 1119static struct rxd_ops rxd_sta_ops = {
1120 .rxd_size = sizeof(struct mwl8k_rxd_sta),
1121 .rxd_init = mwl8k_rxd_sta_init,
1122 .rxd_refill = mwl8k_rxd_sta_refill,
1123 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 1124};
1125
1126
a66098da
LB		 1127#define MWL8K_RX_DESCS 256
1128#define MWL8K_RX_MAXSZ 3800
1129
1130static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
1131{
1132 struct mwl8k_priv *priv = hw->priv;
1133 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1134 int size;
1135 int i;
1136
45eb400d
LB		 1137 rxq->rxd_count = 0;
1138 rxq->head = 0;
1139 rxq->tail = 0;
a66098da 1140
54bc3a0d 1141 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 1142
45eb400d
LB		 1143 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
1144 if (rxq->rxd == NULL) {
5db55844 1145 wiphy_err(hw->wiphy, "failed to alloc RX descriptors\n");
a66098da
LB		 1146 return -ENOMEM;
1147 }
45eb400d 1148 memset(rxq->rxd, 0, size);
a66098da 1149
b9ede5f1 1150 rxq->buf = kcalloc(MWL8K_RX_DESCS, sizeof(*rxq->buf), GFP_KERNEL);
788838eb 1151 if (rxq->buf == NULL) {
45eb400d 1152 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 1153 return -ENOMEM;
1154 }
a66098da
LB		 1155
1156 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 1157 int desc_size;
1158 void *rxd;
a66098da 1159 int nexti;
54bc3a0d
LB		 1160 dma_addr_t next_dma_addr;
1161
1162 desc_size = priv->rxd_ops->rxd_size;
1163 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 1164
54bc3a0d
LB		 1165 nexti = i + 1;
1166 if (nexti == MWL8K_RX_DESCS)
1167 nexti = 0;
1168 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 1169
54bc3a0d 1170 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 1171 }
1172
1173 return 0;
1174}
1175
1176static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1177{
1178 struct mwl8k_priv *priv = hw->priv;
1179 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1180 int refilled;
1181
1182 refilled = 0;
45eb400d 1183 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 1184 struct sk_buff *skb;
788838eb 1185 dma_addr_t addr;
a66098da 1186 int rx;
54bc3a0d 1187 void *rxd;
a66098da
LB		 1188
1189 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1190 if (skb == NULL)
1191 break;
1192
788838eb
LB		 1193 addr = pci_map_single(priv->pdev, skb->data,
1194 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1195
54bc3a0d
LB		 1196 rxq->rxd_count++;
1197 rx = rxq->tail++;
1198 if (rxq->tail == MWL8K_RX_DESCS)
1199 rxq->tail = 0;
788838eb 1200 rxq->buf[rx].skb = skb;
53b1b3e1 1201 dma_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 1202
1203 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1204 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 1205
1206 refilled++;
1207 }
1208
1209 return refilled;
1210}
1211
1212/* Must be called only when the card's reception is completely halted */
1213static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1214{
1215 struct mwl8k_priv *priv = hw->priv;
1216 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1217 int i;
1218
73b46320
BC		 1219 if (rxq->rxd == NULL)
1220 return;
1221
a66098da 1222 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 1223 if (rxq->buf[i].skb != NULL) {
1224 pci_unmap_single(priv->pdev,
53b1b3e1 1225 dma_unmap_addr(&rxq->buf[i], dma),
788838eb 1226 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1227 dma_unmap_addr_set(&rxq->buf[i], dma, 0);
788838eb
LB		 1228
1229 kfree_skb(rxq->buf[i].skb);
1230 rxq->buf[i].skb = NULL;
a66098da
LB		 1231 }
1232 }
1233
788838eb
LB		 1234 kfree(rxq->buf);
1235 rxq->buf = NULL;
a66098da
LB		 1236
1237 pci_free_consistent(priv->pdev,
54bc3a0d 1238 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1239 rxq->rxd, rxq->rxd_dma);
1240 rxq->rxd = NULL;
a66098da
LB		 1241}
1242
1243
1244/*
1245 * Scan a list of BSSIDs to process for finalize join.
1246 * Allows for extension to process multiple BSSIDs.
1247 */
1248static inline int
1249mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1250{
1251 return priv->capture_beacon &&
1252 ieee80211_is_beacon(wh->frame_control) &&
2e42e474 1253 ether_addr_equal(wh->addr3, priv->capture_bssid);
a66098da
LB		 1254}
1255
3779752d
LB		 1256static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1257 struct sk_buff *skb)
a66098da 1258{
3779752d
LB		 1259 struct mwl8k_priv *priv = hw->priv;
1260
a66098da 1261 priv->capture_beacon = false;
d89173f2 1262 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1263
1264 /*
1265 * Use GFP_ATOMIC as rxq_process is called from
1266 * the primary interrupt handler, memory allocation call
1267 * must not sleep.
1268 */
1269 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1270 if (priv->beacon_skb != NULL)
3779752d 1271 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1272}
1273
d9a07d49
NS		 1274static inline struct mwl8k_vif *mwl8k_find_vif_bss(struct list_head *vif_list,
1275 u8 *bssid)
1276{
1277 struct mwl8k_vif *mwl8k_vif;
1278
1279 list_for_each_entry(mwl8k_vif,
1280 vif_list, list) {
1281 if (memcmp(bssid, mwl8k_vif->bssid,
1282 ETH_ALEN) == 0)
1283 return mwl8k_vif;
1284 }
1285
1286 return NULL;
1287}
1288
a66098da
LB		 1289static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1290{
1291 struct mwl8k_priv *priv = hw->priv;
d9a07d49 1292 struct mwl8k_vif *mwl8k_vif = NULL;
a66098da
LB		 1293 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1294 int processed;
1295
1296 processed = 0;
45eb400d 1297 while (rxq->rxd_count && limit--) {
a66098da 1298 struct sk_buff *skb;
54bc3a0d
LB		 1299 void *rxd;
1300 int pkt_len;
a66098da 1301 struct ieee80211_rx_status status;
d9a07d49 1302 struct ieee80211_hdr *wh;
20f09c3d 1303 __le16 qos;
a66098da 1304
788838eb 1305 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1306 if (skb == NULL)
1307 break;
54bc3a0d
LB		 1308
1309 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1310
0d462bbb
JL		 1311 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos,
1312 &priv->noise);
54bc3a0d
LB		 1313 if (pkt_len < 0)
1314 break;
1315
788838eb
LB		 1316 rxq->buf[rxq->head].skb = NULL;
1317
1318 pci_unmap_single(priv->pdev,
53b1b3e1 1319 dma_unmap_addr(&rxq->buf[rxq->head], dma),
788838eb 1320 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1321 dma_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1322
54bc3a0d
LB		 1323 rxq->head++;
1324 if (rxq->head == MWL8K_RX_DESCS)
1325 rxq->head = 0;
1326
45eb400d 1327 rxq->rxd_count--;
a66098da 1328
d9a07d49 1329 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da 1330
a66098da 1331 /*
c2c357ce
LB		 1332 * Check for a pending join operation. Save a
1333 * copy of the beacon and schedule a tasklet to
1334 * send a FINALIZE_JOIN command to the firmware.
a66098da 1335 */
54bc3a0d 1336 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1337 mwl8k_save_beacon(hw, skb);
a66098da 1338
d9a07d49
NS		 1339 if (ieee80211_has_protected(wh->frame_control)) {
1340
1341 /* Check if hw crypto has been enabled for
1342 * this bss. If yes, set the status flags
1343 * accordingly
1344 */
1345 mwl8k_vif = mwl8k_find_vif_bss(&priv->vif_list,
1346 wh->addr1);
1347
1348 if (mwl8k_vif != NULL &&
23677ce3 1349 mwl8k_vif->is_hw_crypto_enabled) {
d9a07d49
NS		 1350 /*
1351 * When MMIC ERROR is encountered
1352 * by the firmware, payload is
1353 * dropped and only 32 bytes of
1354 * mwl8k Firmware header is sent
1355 * to the host.
1356 *
1357 * We need to add four bytes of
1358 * key information. In it
1359 * MAC80211 expects keyidx set to
1360 * 0 for triggering Counter
1361 * Measure of MMIC failure.
1362 */
1363 if (status.flag & RX_FLAG_MMIC_ERROR) {
1364 struct mwl8k_dma_data *tr;
1365 tr = (struct mwl8k_dma_data *)skb->data;
1366 memset((void *)&(tr->data), 0, 4);
1367 pkt_len += 4;
1368 }
1369
1370 if (!ieee80211_is_auth(wh->frame_control))
1371 status.flag |= RX_FLAG_IV_STRIPPED |
1372 RX_FLAG_DECRYPTED |
1373 RX_FLAG_MMIC_STRIPPED;
1374 }
1375 }
1376
1377 skb_put(skb, pkt_len);
1378 mwl8k_remove_dma_header(skb, qos);
f1d58c25
JB		 1379 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1380 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1381
1382 processed++;
1383 }
1384
1385 return processed;
1386}
1387
1388
1389/*
1390 * Packet transmission.
1391 */
1392
a66098da
LB		 1393#define MWL8K_TXD_STATUS_OK 0x00000001
1394#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1395#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1396#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1397#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1398
e0493a8d
LB		 1399#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1400#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1401#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1402#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1403#define MWL8K_QOS_EOSP 0x0010
1404
a66098da
LB		 1405struct mwl8k_tx_desc {
1406 __le32 status;
1407 __u8 data_rate;
1408 __u8 tx_priority;
1409 __le16 qos_control;
1410 __le32 pkt_phys_addr;
1411 __le16 pkt_len;
d89173f2 1412 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1413 __le32 next_txd_phys_addr;
8a7a578c 1414 __le32 timestamp;
a66098da
LB		 1415 __le16 rate_info;
1416 __u8 peer_id;
a1fe24b0 1417 __u8 tx_frag_cnt;
ba2d3587 1418} __packed;
a66098da
LB		 1419
1420#define MWL8K_TX_DESCS 128
1421
1422static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1423{
1424 struct mwl8k_priv *priv = hw->priv;
1425 struct mwl8k_tx_queue *txq = priv->txq + index;
1426 int size;
1427 int i;
1428
8ccbc3b8 1429 txq->len = 0;
45eb400d
LB		 1430 txq->head = 0;
1431 txq->tail = 0;
a66098da
LB		 1432
1433 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1434
45eb400d
LB		 1435 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1436 if (txq->txd == NULL) {
5db55844 1437 wiphy_err(hw->wiphy, "failed to alloc TX descriptors\n");
a66098da
LB		 1438 return -ENOMEM;
1439 }
45eb400d 1440 memset(txq->txd, 0, size);
a66098da 1441
b9ede5f1 1442 txq->skb = kcalloc(MWL8K_TX_DESCS, sizeof(*txq->skb), GFP_KERNEL);
45eb400d 1443 if (txq->skb == NULL) {
45eb400d 1444 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1445 return -ENOMEM;
1446 }
a66098da
LB		 1447
1448 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1449 struct mwl8k_tx_desc *tx_desc;
1450 int nexti;
1451
45eb400d 1452 tx_desc = txq->txd + i;
a66098da
LB		 1453 nexti = (i + 1) % MWL8K_TX_DESCS;
1454
1455 tx_desc->status = 0;
45eb400d
LB		 1456 tx_desc->next_txd_phys_addr =
1457 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1458 }
1459
1460 return 0;
1461}
1462
1463static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1464{
1465 iowrite32(MWL8K_H2A_INT_PPA_READY,
1466 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1467 iowrite32(MWL8K_H2A_INT_DUMMY,
1468 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1469 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1470}
1471
7e1112d3 1472static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1473{
7e1112d3
LB		 1474 struct mwl8k_priv *priv = hw->priv;
1475 int i;
1476
e600707b 1477 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
7e1112d3
LB		 1478 struct mwl8k_tx_queue *txq = priv->txq + i;
1479 int fw_owned = 0;
1480 int drv_owned = 0;
1481 int unused = 0;
1482 int desc;
1483
a66098da 1484 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1485 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1486 u32 status;
a66098da 1487
7e1112d3 1488 status = le32_to_cpu(tx_desc->status);
a66098da 1489 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1490 fw_owned++;
a66098da 1491 else
7e1112d3 1492 drv_owned++;
a66098da
LB		 1493
1494 if (tx_desc->pkt_len == 0)
7e1112d3 1495 unused++;
a66098da 1496 }
a66098da 1497
c96c31e4
JP		 1498 wiphy_err(hw->wiphy,
1499 "txq[%d] len=%d head=%d tail=%d "
1500 "fw_owned=%d drv_owned=%d unused=%d\n",
1501 i,
1502 txq->len, txq->head, txq->tail,
1503 fw_owned, drv_owned, unused);
7e1112d3 1504 }
a66098da
LB		 1505}
1506
618952a7 1507/*
88de754a 1508 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1509 */
62abd3cf 1510#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1511
950d5b01 1512static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1513{
a66098da 1514 struct mwl8k_priv *priv = hw->priv;
88de754a 1515 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1516 int retry;
1517 int rc;
a66098da
LB		 1518
1519 might_sleep();
1520
6b6accc3
YAP		 1521 /* Since fw restart is in progress, allow only the firmware
1522 * commands from the restart code and block the other
1523 * commands since they are going to fail in any case since
1524 * the firmware has crashed
1525 */
1526 if (priv->hw_restart_in_progress) {
1527 if (priv->hw_restart_owner == current)
1528 return 0;
1529 else
1530 return -EBUSY;
1531 }
1532
c27a54d3
YAP		 1533 if (atomic_read(&priv->watchdog_event_pending))
1534 return 0;
1535
7e1112d3
LB		 1536 /*
1537 * The TX queues are stopped at this point, so this test
1538 * doesn't need to take ->tx_lock.
1539 */
1540 if (!priv->pending_tx_pkts)
1541 return 0;
1542
1543 retry = 0;
1544 rc = 0;
1545
a66098da 1546 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1547 priv->tx_wait = &tx_wait;
1548 while (!rc) {
1549 int oldcount;
1550 unsigned long timeout;
a66098da 1551
7e1112d3 1552 oldcount = priv->pending_tx_pkts;
a66098da 1553
7e1112d3 1554 spin_unlock_bh(&priv->tx_lock);
88de754a 1555 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1556 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
c27a54d3
YAP		 1557
1558 if (atomic_read(&priv->watchdog_event_pending)) {
1559 spin_lock_bh(&priv->tx_lock);
1560 priv->tx_wait = NULL;
1561 spin_unlock_bh(&priv->tx_lock);
1562 return 0;
1563 }
1564
a66098da 1565 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1566
1567 if (timeout) {
1568 WARN_ON(priv->pending_tx_pkts);
ba30c4a5 1569 if (retry)
c96c31e4 1570 wiphy_notice(hw->wiphy, "tx rings drained\n");
7e1112d3
LB		 1571 break;
1572 }
1573
1574 if (priv->pending_tx_pkts < oldcount) {
c96c31e4
JP		 1575 wiphy_notice(hw->wiphy,
1576 "waiting for tx rings to drain (%d -> %d pkts)\n",
1577 oldcount, priv->pending_tx_pkts);
7e1112d3
LB		 1578 retry = 1;
1579 continue;
1580 }
1581
a66098da 1582 priv->tx_wait = NULL;
a66098da 1583
c96c31e4
JP		 1584 wiphy_err(hw->wiphy, "tx rings stuck for %d ms\n",
1585 MWL8K_TX_WAIT_TIMEOUT_MS);
7e1112d3 1586 mwl8k_dump_tx_rings(hw);
6b6accc3
YAP		 1587 priv->hw_restart_in_progress = true;
1588 ieee80211_queue_work(hw, &priv->fw_reload);
7e1112d3
LB		 1589
1590 rc = -ETIMEDOUT;
a66098da 1591 }
9b0b11fb 1592 priv->tx_wait = NULL;
7e1112d3 1593 spin_unlock_bh(&priv->tx_lock);
a66098da 1594
7e1112d3 1595 return rc;
a66098da
LB		 1596}
1597
c23b5a69
LB		 1598#define MWL8K_TXD_SUCCESS(status) \
1599 ((status) & (MWL8K_TXD_STATUS_OK | \
1600 MWL8K_TXD_STATUS_OK_RETRY | \
1601 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1602
a0e7c6cf
NS		 1603static int mwl8k_tid_queue_mapping(u8 tid)
1604{
1605 BUG_ON(tid > 7);
1606
1607 switch (tid) {
1608 case 0:
1609 case 3:
1610 return IEEE80211_AC_BE;
1611 break;
1612 case 1:
1613 case 2:
1614 return IEEE80211_AC_BK;
1615 break;
1616 case 4:
1617 case 5:
1618 return IEEE80211_AC_VI;
1619 break;
1620 case 6:
1621 case 7:
1622 return IEEE80211_AC_VO;
1623 break;
1624 default:
1625 return -1;
1626 break;
1627 }
1628}
1629
17033543
NS		 1630/* The firmware will fill in the rate information
1631 * for each packet that gets queued in the hardware
49adc5ce 1632 * and these macros will interpret that info.
17033543
NS		 1633 */
1634
49adc5ce
JL		 1635#define RI_FORMAT(a) (a & 0x0001)
1636#define RI_RATE_ID_MCS(a) ((a & 0x01f8) >> 3)
17033543 1637
efb7c49a
LB		 1638static int
1639mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB		 1640{
1641 struct mwl8k_priv *priv = hw->priv;
1642 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1643 int processed;
a66098da 1644
efb7c49a 1645 processed = 0;
8ccbc3b8 1646 while (txq->len > 0 && limit--) {
a66098da 1647 int tx;
a66098da
LB		 1648 struct mwl8k_tx_desc *tx_desc;
1649 unsigned long addr;
ce9e2e1b 1650 int size;
a66098da
LB		 1651 struct sk_buff *skb;
1652 struct ieee80211_tx_info *info;
1653 u32 status;
17033543
NS		 1654 struct ieee80211_sta *sta;
1655 struct mwl8k_sta *sta_info = NULL;
1656 u16 rate_info;
17033543 1657 struct ieee80211_hdr *wh;
a66098da 1658
45eb400d
LB		 1659 tx = txq->head;
1660 tx_desc = txq->txd + tx;
a66098da
LB		 1661
1662 status = le32_to_cpu(tx_desc->status);
1663
1664 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1665 if (!force)
1666 break;
1667 tx_desc->status &=
1668 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1669 }
1670
45eb400d 1671 txq->head = (tx + 1) % MWL8K_TX_DESCS;
8ccbc3b8
KV		 1672 BUG_ON(txq->len == 0);
1673 txq->len--;
a66098da
LB		 1674 priv->pending_tx_pkts--;
1675
1676 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1677 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1678 skb = txq->skb[tx];
1679 txq->skb[tx] = NULL;
a66098da
LB		 1680
1681 BUG_ON(skb == NULL);
1682 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1683
20f09c3d 1684 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da 1685
17033543
NS		 1686 wh = (struct ieee80211_hdr *) skb->data;
1687
a66098da
LB		 1688 /* Mark descriptor as unused */
1689 tx_desc->pkt_phys_addr = 0;
1690 tx_desc->pkt_len = 0;
1691
a66098da 1692 info = IEEE80211_SKB_CB(skb);
17033543 1693 if (ieee80211_is_data(wh->frame_control)) {
89e11801
TH		 1694 rcu_read_lock();
1695 sta = ieee80211_find_sta_by_ifaddr(hw, wh->addr1,
1696 wh->addr2);
17033543
NS		 1697 if (sta) {
1698 sta_info = MWL8K_STA(sta);
1699 BUG_ON(sta_info == NULL);
1700 rate_info = le16_to_cpu(tx_desc->rate_info);
17033543
NS		 1701 /* If rate is < 6.5 Mpbs for an ht station
1702 * do not form an ampdu. If the station is a
1703 * legacy station (format = 0), do not form an
1704 * ampdu
1705 */
49adc5ce
JL		 1706 if (RI_RATE_ID_MCS(rate_info) < 1 ||
1707 RI_FORMAT(rate_info) == 0) {
17033543
NS		 1708 sta_info->is_ampdu_allowed = false;
1709 } else {
1710 sta_info->is_ampdu_allowed = true;
1711 }
1712 }
89e11801 1713 rcu_read_unlock();
17033543
NS		 1714 }
1715
a66098da 1716 ieee80211_tx_info_clear_status(info);
0bf22c37
NS		 1717
1718 /* Rate control is happening in the firmware.
1719 * Ensure no tx rate is being reported.
1720 */
ba30c4a5
YAP		 1721 info->status.rates[0].idx = -1;
1722 info->status.rates[0].count = 1;
0bf22c37 1723
ce9e2e1b 1724 if (MWL8K_TXD_SUCCESS(status))
a66098da 1725 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1726
1727 ieee80211_tx_status_irqsafe(hw, skb);
1728
efb7c49a 1729 processed++;
a66098da
LB		 1730 }
1731
efb7c49a 1732 return processed;
a66098da
LB		 1733}
1734
1735/* must be called only when the card's transmit is completely halted */
1736static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1737{
1738 struct mwl8k_priv *priv = hw->priv;
1739 struct mwl8k_tx_queue *txq = priv->txq + index;
1740
73b46320
BC		 1741 if (txq->txd == NULL)
1742 return;
1743
efb7c49a 1744 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1745
45eb400d
LB		 1746 kfree(txq->skb);
1747 txq->skb = NULL;
a66098da
LB		 1748
1749 pci_free_consistent(priv->pdev,
1750 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1751 txq->txd, txq->txd_dma);
1752 txq->txd = NULL;
a66098da
LB		 1753}
1754
ac109fd0 1755/* caller must hold priv->stream_lock when calling the stream functions */
ba30c4a5 1756static struct mwl8k_ampdu_stream *
ac109fd0
BC		 1757mwl8k_add_stream(struct ieee80211_hw *hw, struct ieee80211_sta *sta, u8 tid)
1758{
1759 struct mwl8k_ampdu_stream *stream;
1760 struct mwl8k_priv *priv = hw->priv;
1761 int i;
1762
7fb978b7 1763 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
ac109fd0
BC		 1764 stream = &priv->ampdu[i];
1765 if (stream->state == AMPDU_NO_STREAM) {
1766 stream->sta = sta;
1767 stream->state = AMPDU_STREAM_NEW;
1768 stream->tid = tid;
1769 stream->idx = i;
ac109fd0
BC		 1770 wiphy_debug(hw->wiphy, "Added a new stream for %pM %d",
1771 sta->addr, tid);
1772 return stream;
1773 }
1774 }
1775 return NULL;
1776}
1777
1778static int
1779mwl8k_start_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1780{
1781 int ret;
1782
1783 /* if the stream has already been started, don't start it again */
1784 if (stream->state != AMPDU_STREAM_NEW)
1785 return 0;
1786 ret = ieee80211_start_tx_ba_session(stream->sta, stream->tid, 0);
1787 if (ret)
1788 wiphy_debug(hw->wiphy, "Failed to start stream for %pM %d: "
1789 "%d\n", stream->sta->addr, stream->tid, ret);
1790 else
1791 wiphy_debug(hw->wiphy, "Started stream for %pM %d\n",
1792 stream->sta->addr, stream->tid);
1793 return ret;
1794}
1795
1796static void
1797mwl8k_remove_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1798{
1799 wiphy_debug(hw->wiphy, "Remove stream for %pM %d\n", stream->sta->addr,
1800 stream->tid);
1801 memset(stream, 0, sizeof(*stream));
1802}
1803
1804static struct mwl8k_ampdu_stream *
1805mwl8k_lookup_stream(struct ieee80211_hw *hw, u8 *addr, u8 tid)
1806{
1807 struct mwl8k_priv *priv = hw->priv;
1808 int i;
1809
7fb978b7 1810 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
ac109fd0
BC		 1811 struct mwl8k_ampdu_stream *stream;
1812 stream = &priv->ampdu[i];
1813 if (stream->state == AMPDU_NO_STREAM)
1814 continue;
1815 if (!memcmp(stream->sta->addr, addr, ETH_ALEN) &&
1816 stream->tid == tid)
1817 return stream;
1818 }
1819 return NULL;
1820}
1821
d0805c1c
BC		 1822#define MWL8K_AMPDU_PACKET_THRESHOLD 64
1823static inline bool mwl8k_ampdu_allowed(struct ieee80211_sta *sta, u8 tid)
1824{
1825 struct mwl8k_sta *sta_info = MWL8K_STA(sta);
1826 struct tx_traffic_info *tx_stats;
1827
1828 BUG_ON(tid >= MWL8K_MAX_TID);
1829 tx_stats = &sta_info->tx_stats[tid];
1830
1831 return sta_info->is_ampdu_allowed &&
1832 tx_stats->pkts > MWL8K_AMPDU_PACKET_THRESHOLD;
1833}
1834
1835static inline void mwl8k_tx_count_packet(struct ieee80211_sta *sta, u8 tid)
1836{
1837 struct mwl8k_sta *sta_info = MWL8K_STA(sta);
1838 struct tx_traffic_info *tx_stats;
1839
1840 BUG_ON(tid >= MWL8K_MAX_TID);
1841 tx_stats = &sta_info->tx_stats[tid];
1842
1843 if (tx_stats->start_time == 0)
1844 tx_stats->start_time = jiffies;
1845
1846 /* reset the packet count after each second elapses. If the number of
1847 * packets ever exceeds the ampdu_min_traffic threshold, we will allow
1848 * an ampdu stream to be started.
1849 */
1850 if (jiffies - tx_stats->start_time > HZ) {
1851 tx_stats->pkts = 0;
1852 tx_stats->start_time = 0;
1853 } else
1854 tx_stats->pkts++;
1855}
1856
7fb978b7
YAP		 1857/* The hardware ampdu queues start from 5.
1858 * txpriorities for ampdu queues are
1859 * 5 6 7 0 1 2 3 4 ie., queue 5 is highest
1860 * and queue 3 is lowest (queue 4 is reserved)
1861 */
1862#define BA_QUEUE 5
1863
7bb45683 1864static void
36323f81
TH		 1865mwl8k_txq_xmit(struct ieee80211_hw *hw,
1866 int index,
1867 struct ieee80211_sta *sta,
1868 struct sk_buff *skb)
a66098da
LB		 1869{
1870 struct mwl8k_priv *priv = hw->priv;
1871 struct ieee80211_tx_info *tx_info;
23b33906 1872 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1873 struct ieee80211_hdr *wh;
1874 struct mwl8k_tx_queue *txq;
1875 struct mwl8k_tx_desc *tx;
a66098da 1876 dma_addr_t dma;
23b33906
LB		 1877 u32 txstatus;
1878 u8 txdatarate;
1879 u16 qos;
65f3ddcd
NS		 1880 int txpriority;
1881 u8 tid = 0;
1882 struct mwl8k_ampdu_stream *stream = NULL;
1883 bool start_ba_session = false;
3a769888 1884 bool mgmtframe = false;
a0e7c6cf 1885 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
e1f4d69b 1886 bool eapol_frame = false;
a66098da 1887
23b33906
LB		 1888 wh = (struct ieee80211_hdr *)skb->data;
1889 if (ieee80211_is_data_qos(wh->frame_control))
1890 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1891 else
1892 qos = 0;
a66098da 1893
e1f4d69b
NS		 1894 if (skb->protocol == cpu_to_be16(ETH_P_PAE))
1895 eapol_frame = true;
1896
3a769888
NS		 1897 if (ieee80211_is_mgmt(wh->frame_control))
1898 mgmtframe = true;
1899
d9a07d49 1900 if (priv->ap_fw)
ff776cec 1901 mwl8k_encapsulate_tx_frame(priv, skb);
d9a07d49 1902 else
e4eefec7 1903 mwl8k_add_dma_header(priv, skb, 0, 0);
d9a07d49 1904
23b33906 1905 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1906
1907 tx_info = IEEE80211_SKB_CB(skb);
1908 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1909
1910 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
a66098da 1911 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
657232b6
LB		 1912 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1913 mwl8k_vif->seqno += 0x10;
a66098da
LB		 1914 }
1915
23b33906
LB		 1916 /* Setup firmware control bit fields for each frame type. */
1917 txstatus = 0;
1918 txdatarate = 0;
1919 if (ieee80211_is_mgmt(wh->frame_control) ||
1920 ieee80211_is_ctl(wh->frame_control)) {
1921 txdatarate = 0;
e0493a8d 1922 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1923 } else if (ieee80211_is_data(wh->frame_control)) {
1924 txdatarate = 1;
1925 if (is_multicast_ether_addr(wh->addr1))
1926 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1927
e0493a8d 1928 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1929 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1930 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1931 else
e0493a8d 1932 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1933 }
a66098da 1934
a0e7c6cf
NS		 1935 /* Queue ADDBA request in the respective data queue. While setting up
1936 * the ampdu stream, mac80211 queues further packets for that
1937 * particular ra/tid pair. However, packets piled up in the hardware
1938 * for that ra/tid pair will still go out. ADDBA request and the
1939 * related data packets going out from different queues asynchronously
1940 * will cause a shift in the receiver window which might result in
1941 * ampdu packets getting dropped at the receiver after the stream has
1942 * been setup.
1943 */
1944 if (unlikely(ieee80211_is_action(wh->frame_control) &&
1945 mgmt->u.action.category == WLAN_CATEGORY_BACK &&
1946 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ &&
1947 priv->ap_fw)) {
1948 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
1949 tid = (capab & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2;
1950 index = mwl8k_tid_queue_mapping(tid);
1951 }
1952
65f3ddcd
NS		 1953 txpriority = index;
1954
e1f4d69b
NS		 1955 if (priv->ap_fw && sta && sta->ht_cap.ht_supported && !eapol_frame &&
1956 ieee80211_is_data_qos(wh->frame_control)) {
65f3ddcd 1957 tid = qos & 0xf;
d0805c1c 1958 mwl8k_tx_count_packet(sta, tid);
65f3ddcd
NS		 1959 spin_lock(&priv->stream_lock);
1960 stream = mwl8k_lookup_stream(hw, sta->addr, tid);
1961 if (stream != NULL) {
1962 if (stream->state == AMPDU_STREAM_ACTIVE) {
5f2a1494 1963 WARN_ON(!(qos & MWL8K_QOS_ACK_POLICY_BLOCKACK));
7fb978b7
YAP		 1964 txpriority = (BA_QUEUE + stream->idx) %
1965 TOTAL_HW_TX_QUEUES;
1966 if (stream->idx <= 1)
1967 index = stream->idx +
1968 MWL8K_TX_WMM_QUEUES;
1969
65f3ddcd
NS		 1970 } else if (stream->state == AMPDU_STREAM_NEW) {
1971 /* We get here if the driver sends us packets
1972 * after we've initiated a stream, but before
1973 * our ampdu_action routine has been called
1974 * with IEEE80211_AMPDU_TX_START to get the SSN
1975 * for the ADDBA request. So this packet can
1976 * go out with no risk of sequence number
1977 * mismatch. No special handling is required.
1978 */
1979 } else {
1980 /* Drop packets that would go out after the
1981 * ADDBA request was sent but before the ADDBA
1982 * response is received. If we don't do this,
1983 * the recipient would probably receive it
1984 * after the ADDBA request with SSN 0. This
1985 * will cause the recipient's BA receive window
1986 * to shift, which would cause the subsequent
1987 * packets in the BA stream to be discarded.
1988 * mac80211 queues our packets for us in this
1989 * case, so this is really just a safety check.
1990 */
1991 wiphy_warn(hw->wiphy,
1992 "Cannot send packet while ADDBA "
1993 "dialog is underway.\n");
1994 spin_unlock(&priv->stream_lock);
1995 dev_kfree_skb(skb);
1996 return;
1997 }
1998 } else {
1999 /* Defer calling mwl8k_start_stream so that the current
2000 * skb can go out before the ADDBA request. This
2001 * prevents sequence number mismatch at the recepient
2002 * as described above.
2003 */
d0805c1c 2004 if (mwl8k_ampdu_allowed(sta, tid)) {
17033543
NS		 2005 stream = mwl8k_add_stream(hw, sta, tid);
2006 if (stream != NULL)
2007 start_ba_session = true;
2008 }
65f3ddcd
NS		 2009 }
2010 spin_unlock(&priv->stream_lock);
5f2a1494
YAP		 2011 } else {
2012 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
2013 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
65f3ddcd
NS		 2014 }
2015
a66098da
LB		 2016 dma = pci_map_single(priv->pdev, skb->data,
2017 skb->len, PCI_DMA_TODEVICE);
2018
2019 if (pci_dma_mapping_error(priv->pdev, dma)) {
c96c31e4
JP		 2020 wiphy_debug(hw->wiphy,
2021 "failed to dma map skb, dropping TX frame.\n");
65f3ddcd
NS		 2022 if (start_ba_session) {
2023 spin_lock(&priv->stream_lock);
2024 mwl8k_remove_stream(hw, stream);
2025 spin_unlock(&priv->stream_lock);
2026 }
23b33906 2027 dev_kfree_skb(skb);
7bb45683 2028 return;
a66098da
LB		 2029 }
2030
23b33906 2031 spin_lock_bh(&priv->tx_lock);
a66098da 2032
23b33906 2033 txq = priv->txq + index;
a66098da 2034
3a769888
NS		 2035 /* Mgmt frames that go out frequently are probe
2036 * responses. Other mgmt frames got out relatively
2037 * infrequently. Hence reserve 2 buffers so that
2038 * other mgmt frames do not get dropped due to an
2039 * already queued probe response in one of the
2040 * reserved buffers.
2041 */
2042
2043 if (txq->len >= MWL8K_TX_DESCS - 2) {
23677ce3 2044 if (!mgmtframe || txq->len == MWL8K_TX_DESCS) {
3a769888
NS		 2045 if (start_ba_session) {
2046 spin_lock(&priv->stream_lock);
2047 mwl8k_remove_stream(hw, stream);
2048 spin_unlock(&priv->stream_lock);
2049 }
2050 spin_unlock_bh(&priv->tx_lock);
ff7aa96f
NS		 2051 pci_unmap_single(priv->pdev, dma, skb->len,
2052 PCI_DMA_TODEVICE);
3a769888
NS		 2053 dev_kfree_skb(skb);
2054 return;
3a7dbc3b 2055 }
65f3ddcd
NS		 2056 }
2057
45eb400d
LB		 2058 BUG_ON(txq->skb[txq->tail] != NULL);
2059 txq->skb[txq->tail] = skb;
a66098da 2060
45eb400d 2061 tx = txq->txd + txq->tail;
23b33906 2062 tx->data_rate = txdatarate;
65f3ddcd 2063 tx->tx_priority = txpriority;
a66098da 2064 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 2065 tx->pkt_phys_addr = cpu_to_le32(dma);
2066 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 2067 tx->rate_info = 0;
36323f81
TH		 2068 if (!priv->ap_fw && sta != NULL)
2069 tx->peer_id = MWL8K_STA(sta)->peer_id;
a680400e
LB		 2070 else
2071 tx->peer_id = 0;
566875db 2072
e1f4d69b 2073 if (priv->ap_fw && ieee80211_is_data(wh->frame_control) && !eapol_frame)
566875db
PN		 2074 tx->timestamp = cpu_to_le32(ioread32(priv->regs +
2075 MWL8K_HW_TIMER_REGISTER));
b8d9e572
NS		 2076 else
2077 tx->timestamp = 0;
566875db 2078
a66098da 2079 wmb();
23b33906
LB		 2080 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
2081
8ccbc3b8 2082 txq->len++;
a66098da 2083 priv->pending_tx_pkts++;
a66098da 2084
45eb400d
LB		 2085 txq->tail++;
2086 if (txq->tail == MWL8K_TX_DESCS)
2087 txq->tail = 0;
23b33906 2088
23b33906 2089 mwl8k_tx_start(priv);
a66098da
LB		 2090
2091 spin_unlock_bh(&priv->tx_lock);
65f3ddcd
NS		 2092
2093 /* Initiate the ampdu session here */
2094 if (start_ba_session) {
2095 spin_lock(&priv->stream_lock);
2096 if (mwl8k_start_stream(hw, stream))
2097 mwl8k_remove_stream(hw, stream);
2098 spin_unlock(&priv->stream_lock);
2099 }
a66098da
LB		 2100}
2101
2102
618952a7
LB		 2103/*
2104 * Firmware access.
2105 *
2106 * We have the following requirements for issuing firmware commands:
2107 * - Some commands require that the packet transmit path is idle when
2108 * the command is issued. (For simplicity, we'll just quiesce the
2109 * transmit path for every command.)
2110 * - There are certain sequences of commands that need to be issued to
2111 * the hardware sequentially, with no other intervening commands.
2112 *
2113 * This leads to an implementation of a "firmware lock" as a mutex that
2114 * can be taken recursively, and which is taken by both the low-level
2115 * command submission function (mwl8k_post_cmd) as well as any users of
2116 * that function that require issuing of an atomic sequence of commands,
2117 * and quiesces the transmit path whenever it's taken.
2118 */
2119static int mwl8k_fw_lock(struct ieee80211_hw *hw)
2120{
2121 struct mwl8k_priv *priv = hw->priv;
2122
2123 if (priv->fw_mutex_owner != current) {
2124 int rc;
2125
2126 mutex_lock(&priv->fw_mutex);
2127 ieee80211_stop_queues(hw);
2128
2129 rc = mwl8k_tx_wait_empty(hw);
2130 if (rc) {
6b6accc3
YAP		 2131 if (!priv->hw_restart_in_progress)
2132 ieee80211_wake_queues(hw);
2133
618952a7
LB		 2134 mutex_unlock(&priv->fw_mutex);
2135
2136 return rc;
2137 }
2138
2139 priv->fw_mutex_owner = current;
2140 }
2141
2142 priv->fw_mutex_depth++;
2143
2144 return 0;
2145}
2146
2147static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
2148{
2149 struct mwl8k_priv *priv = hw->priv;
2150
2151 if (!--priv->fw_mutex_depth) {
6b6accc3
YAP		 2152 if (!priv->hw_restart_in_progress)
2153 ieee80211_wake_queues(hw);
2154
618952a7
LB		 2155 priv->fw_mutex_owner = NULL;
2156 mutex_unlock(&priv->fw_mutex);
2157 }
2158}
2159
e882efc9
YAP		 2160static void mwl8k_enable_bsses(struct ieee80211_hw *hw, bool enable,
2161 u32 bitmap);
618952a7 2162
a66098da
LB		 2163/*
2164 * Command processing.
2165 */
2166
0c9cc640
LB		 2167/* Timeout firmware commands after 10s */
2168#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 2169
2170static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
2171{
2172 DECLARE_COMPLETION_ONSTACK(cmd_wait);
2173 struct mwl8k_priv *priv = hw->priv;
2174 void __iomem *regs = priv->regs;
2175 dma_addr_t dma_addr;
2176 unsigned int dma_size;
2177 int rc;
a66098da
LB		 2178 unsigned long timeout = 0;
2179 u8 buf[32];
e882efc9
YAP		 2180 u32 bitmap = 0;
2181
2182 wiphy_dbg(hw->wiphy, "Posting %s [%d]\n",
2183 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), cmd->macid);
2184
2185 /* Before posting firmware commands that could change the hardware
2186 * characteristics, make sure that all BSSes are stopped temporary.
2187 * Enable these stopped BSSes after completion of the commands
2188 */
2189
2190 rc = mwl8k_fw_lock(hw);
2191 if (rc)
2192 return rc;
2193
2194 if (priv->ap_fw && priv->running_bsses) {
2195 switch (le16_to_cpu(cmd->code)) {
2196 case MWL8K_CMD_SET_RF_CHANNEL:
2197 case MWL8K_CMD_RADIO_CONTROL:
2198 case MWL8K_CMD_RF_TX_POWER:
2199 case MWL8K_CMD_TX_POWER:
2200 case MWL8K_CMD_RF_ANTENNA:
2201 case MWL8K_CMD_RTS_THRESHOLD:
2202 case MWL8K_CMD_MIMO_CONFIG:
2203 bitmap = priv->running_bsses;
2204 mwl8k_enable_bsses(hw, false, bitmap);
2205 break;
2206 }
2207 }
a66098da 2208
b603742f 2209 cmd->result = (__force __le16) 0xffff;
a66098da
LB		 2210 dma_size = le16_to_cpu(cmd->length);
2211 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
2212 PCI_DMA_BIDIRECTIONAL);
2213 if (pci_dma_mapping_error(priv->pdev, dma_addr))
2214 return -ENOMEM;
2215
a66098da
LB		 2216 priv->hostcmd_wait = &cmd_wait;
2217 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
2218 iowrite32(MWL8K_H2A_INT_DOORBELL,
2219 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
2220 iowrite32(MWL8K_H2A_INT_DUMMY,
2221 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 2222
2223 timeout = wait_for_completion_timeout(&cmd_wait,
2224 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
2225
618952a7
LB		 2226 priv->hostcmd_wait = NULL;
2227
618952a7 2228
37055bd4
LB		 2229 pci_unmap_single(priv->pdev, dma_addr, dma_size,
2230 PCI_DMA_BIDIRECTIONAL);
2231
a66098da 2232 if (!timeout) {
5db55844 2233 wiphy_err(hw->wiphy, "Command %s timeout after %u ms\n",
c96c31e4
JP		 2234 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2235 MWL8K_CMD_TIMEOUT_MS);
a66098da
LB		 2236 rc = -ETIMEDOUT;
2237 } else {
0c9cc640
LB		 2238 int ms;
2239
2240 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
2241
ce9e2e1b 2242 rc = cmd->result ? -EINVAL : 0;
a66098da 2243 if (rc)
5db55844 2244 wiphy_err(hw->wiphy, "Command %s error 0x%x\n",
c96c31e4
JP		 2245 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2246 le16_to_cpu(cmd->result));
0c9cc640 2247 else if (ms > 2000)
5db55844 2248 wiphy_notice(hw->wiphy, "Command %s took %d ms\n",
c96c31e4
JP		 2249 mwl8k_cmd_name(cmd->code,
2250 buf, sizeof(buf)),
2251 ms);
a66098da
LB		 2252 }
2253
e882efc9
YAP		 2254 if (bitmap)
2255 mwl8k_enable_bsses(hw, true, bitmap);
2256
2257 mwl8k_fw_unlock(hw);
2258
a66098da
LB		 2259 return rc;
2260}
2261
f57ca9c1
LB		 2262static int mwl8k_post_pervif_cmd(struct ieee80211_hw *hw,
2263 struct ieee80211_vif *vif,
2264 struct mwl8k_cmd_pkt *cmd)
2265{
2266 if (vif != NULL)
2267 cmd->macid = MWL8K_VIF(vif)->macid;
2268 return mwl8k_post_cmd(hw, cmd);
2269}
2270
1349ad2f
LB		 2271/*
2272 * Setup code shared between STA and AP firmware images.
2273 */
2274static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw)
2275{
2276 struct mwl8k_priv *priv = hw->priv;
2277
2278 BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24));
2279 memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
2280
2281 BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
2282 memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
2283
2284 priv->band_24.band = IEEE80211_BAND_2GHZ;
2285 priv->band_24.channels = priv->channels_24;
2286 priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
2287 priv->band_24.bitrates = priv->rates_24;
2288 priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
2289
2290 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24;
2291}
2292
4eae9edd
LB		 2293static void mwl8k_setup_5ghz_band(struct ieee80211_hw *hw)
2294{
2295 struct mwl8k_priv *priv = hw->priv;
2296
2297 BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl8k_channels_50));
2298 memcpy(priv->channels_50, mwl8k_channels_50, sizeof(mwl8k_channels_50));
2299
2300 BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl8k_rates_50));
2301 memcpy(priv->rates_50, mwl8k_rates_50, sizeof(mwl8k_rates_50));
2302
2303 priv->band_50.band = IEEE80211_BAND_5GHZ;
2304 priv->band_50.channels = priv->channels_50;
2305 priv->band_50.n_channels = ARRAY_SIZE(mwl8k_channels_50);
2306 priv->band_50.bitrates = priv->rates_50;
2307 priv->band_50.n_bitrates = ARRAY_SIZE(mwl8k_rates_50);
2308
2309 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->band_50;
2310}
2311
a66098da 2312/*
04b147b1 2313 * CMD_GET_HW_SPEC (STA version).
a66098da 2314 */
04b147b1 2315struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 2316 struct mwl8k_cmd_pkt header;
2317 __u8 hw_rev;
2318 __u8 host_interface;
2319 __le16 num_mcaddrs;
d89173f2 2320 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 2321 __le16 region_code;
2322 __le32 fw_rev;
2323 __le32 ps_cookie;
2324 __le32 caps;
2325 __u8 mcs_bitmap[16];
2326 __le32 rx_queue_ptr;
2327 __le32 num_tx_queues;
e600707b 2328 __le32 tx_queue_ptrs[MWL8K_TX_WMM_QUEUES];
a66098da
LB		 2329 __le32 caps2;
2330 __le32 num_tx_desc_per_queue;
45eb400d 2331 __le32 total_rxd;
ba2d3587 2332} __packed;
a66098da 2333
341c9791
LB		 2334#define MWL8K_CAP_MAX_AMSDU 0x20000000
2335#define MWL8K_CAP_GREENFIELD 0x08000000
2336#define MWL8K_CAP_AMPDU 0x04000000
2337#define MWL8K_CAP_RX_STBC 0x01000000
2338#define MWL8K_CAP_TX_STBC 0x00800000
2339#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
2340#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
2341#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
2342#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
2343#define MWL8K_CAP_DELAY_BA 0x00003000
2344#define MWL8K_CAP_MIMO 0x00000200
2345#define MWL8K_CAP_40MHZ 0x00000100
06953235
LB		 2346#define MWL8K_CAP_BAND_MASK 0x00000007
2347#define MWL8K_CAP_5GHZ 0x00000004
2348#define MWL8K_CAP_2GHZ4 0x00000001
341c9791 2349
06953235
LB		 2350static void
2351mwl8k_set_ht_caps(struct ieee80211_hw *hw,
2352 struct ieee80211_supported_band *band, u32 cap)
341c9791 2353{
341c9791
LB		 2354 int rx_streams;
2355 int tx_streams;
2356
777ad375 2357 band->ht_cap.ht_supported = 1;
341c9791
LB		 2358
2359 if (cap & MWL8K_CAP_MAX_AMSDU)
777ad375 2360 band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
341c9791 2361 if (cap & MWL8K_CAP_GREENFIELD)
777ad375 2362 band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
341c9791
LB		 2363 if (cap & MWL8K_CAP_AMPDU) {
2364 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
777ad375
LB		 2365 band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
2366 band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
341c9791
LB		 2367 }
2368 if (cap & MWL8K_CAP_RX_STBC)
777ad375 2369 band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
341c9791 2370 if (cap & MWL8K_CAP_TX_STBC)
777ad375 2371 band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
341c9791 2372 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
777ad375 2373 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
341c9791 2374 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
777ad375 2375 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
341c9791 2376 if (cap & MWL8K_CAP_DELAY_BA)
777ad375 2377 band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
341c9791 2378 if (cap & MWL8K_CAP_40MHZ)
777ad375 2379 band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
341c9791
LB		 2380
2381 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
2382 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
2383
777ad375 2384 band->ht_cap.mcs.rx_mask[0] = 0xff;
341c9791 2385 if (rx_streams >= 2)
777ad375 2386 band->ht_cap.mcs.rx_mask[1] = 0xff;
341c9791 2387 if (rx_streams >= 3)
777ad375
LB		 2388 band->ht_cap.mcs.rx_mask[2] = 0xff;
2389 band->ht_cap.mcs.rx_mask[4] = 0x01;
2390 band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
341c9791
LB		 2391
2392 if (rx_streams != tx_streams) {
777ad375
LB		 2393 band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
2394 band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
341c9791
LB		 2395 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2396 }
2397}
2398
06953235
LB		 2399static void
2400mwl8k_set_caps(struct ieee80211_hw *hw, u32 caps)
2401{
2402 struct mwl8k_priv *priv = hw->priv;
2403
2404 if ((caps & MWL8K_CAP_2GHZ4) || !(caps & MWL8K_CAP_BAND_MASK)) {
2405 mwl8k_setup_2ghz_band(hw);
2406 if (caps & MWL8K_CAP_MIMO)
2407 mwl8k_set_ht_caps(hw, &priv->band_24, caps);
2408 }
2409
2410 if (caps & MWL8K_CAP_5GHZ) {
2411 mwl8k_setup_5ghz_band(hw);
2412 if (caps & MWL8K_CAP_MIMO)
2413 mwl8k_set_ht_caps(hw, &priv->band_50, caps);
2414 }
2415}
2416
04b147b1 2417static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 2418{
2419 struct mwl8k_priv *priv = hw->priv;
04b147b1 2420 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 2421 int rc;
2422 int i;
2423
2424 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2425 if (cmd == NULL)
2426 return -ENOMEM;
2427
2428 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2429 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2430
2431 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2432 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 2433 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
e600707b
BC		 2434 cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
2435 for (i = 0; i < mwl8k_tx_queues(priv); i++)
45eb400d 2436 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 2437 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 2438 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 2439
2440 rc = mwl8k_post_cmd(hw, &cmd->header);
2441
2442 if (!rc) {
2443 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2444 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 2445 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 2446 priv->hw_rev = cmd->hw_rev;
06953235 2447 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18
LB		 2448 priv->ap_macids_supported = 0x00000000;
2449 priv->sta_macids_supported = 0x00000001;
a66098da
LB		 2450 }
2451
2452 kfree(cmd);
2453 return rc;
2454}
2455
42fba21d
LB		 2456/*
2457 * CMD_GET_HW_SPEC (AP version).
2458 */
2459struct mwl8k_cmd_get_hw_spec_ap {
2460 struct mwl8k_cmd_pkt header;
2461 __u8 hw_rev;
2462 __u8 host_interface;
2463 __le16 num_wcb;
2464 __le16 num_mcaddrs;
2465 __u8 perm_addr[ETH_ALEN];
2466 __le16 region_code;
2467 __le16 num_antenna;
2468 __le32 fw_rev;
2469 __le32 wcbbase0;
2470 __le32 rxwrptr;
2471 __le32 rxrdptr;
2472 __le32 ps_cookie;
2473 __le32 wcbbase1;
2474 __le32 wcbbase2;
2475 __le32 wcbbase3;
952a0e96 2476 __le32 fw_api_version;
8a7a578c
BC		 2477 __le32 caps;
2478 __le32 num_of_ampdu_queues;
2479 __le32 wcbbase_ampdu[MWL8K_MAX_AMPDU_QUEUES];
ba2d3587 2480} __packed;
42fba21d
LB		 2481
2482static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
2483{
2484 struct mwl8k_priv *priv = hw->priv;
2485 struct mwl8k_cmd_get_hw_spec_ap *cmd;
8a7a578c 2486 int rc, i;
952a0e96 2487 u32 api_version;
42fba21d
LB		 2488
2489 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2490 if (cmd == NULL)
2491 return -ENOMEM;
2492
2493 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2494 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2495
2496 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2497 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2498
2499 rc = mwl8k_post_cmd(hw, &cmd->header);
2500
2501 if (!rc) {
2502 int off;
2503
952a0e96
BC		 2504 api_version = le32_to_cpu(cmd->fw_api_version);
2505 if (priv->device_info->fw_api_ap != api_version) {
2506 printk(KERN_ERR "%s: Unsupported fw API version for %s."
2507 " Expected %d got %d.\n", MWL8K_NAME,
2508 priv->device_info->part_name,
2509 priv->device_info->fw_api_ap,
2510 api_version);
2511 rc = -EINVAL;
2512 goto done;
2513 }
42fba21d
LB		 2514 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2515 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
2516 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
2517 priv->hw_rev = cmd->hw_rev;
8a7a578c 2518 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18 2519 priv->ap_macids_supported = 0x000000ff;
d59c1cfd 2520 priv->sta_macids_supported = 0x00000100;
8a7a578c
BC		 2521 priv->num_ampdu_queues = le32_to_cpu(cmd->num_of_ampdu_queues);
2522 if (priv->num_ampdu_queues > MWL8K_MAX_AMPDU_QUEUES) {
2523 wiphy_warn(hw->wiphy, "fw reported %d ampdu queues"
2524 " but we only support %d.\n",
2525 priv->num_ampdu_queues,
2526 MWL8K_MAX_AMPDU_QUEUES);
2527 priv->num_ampdu_queues = MWL8K_MAX_AMPDU_QUEUES;
2528 }
42fba21d 2529 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
b603742f 2530 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d
LB		 2531
2532 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
b603742f 2533 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d 2534
73b46320
BC		 2535 priv->txq_offset[0] = le32_to_cpu(cmd->wcbbase0) & 0xffff;
2536 priv->txq_offset[1] = le32_to_cpu(cmd->wcbbase1) & 0xffff;
2537 priv->txq_offset[2] = le32_to_cpu(cmd->wcbbase2) & 0xffff;
2538 priv->txq_offset[3] = le32_to_cpu(cmd->wcbbase3) & 0xffff;
8a7a578c
BC		 2539
2540 for (i = 0; i < priv->num_ampdu_queues; i++)
e600707b 2541 priv->txq_offset[i + MWL8K_TX_WMM_QUEUES] =
8a7a578c 2542 le32_to_cpu(cmd->wcbbase_ampdu[i]) & 0xffff;
42fba21d
LB		 2543 }
2544
952a0e96 2545done:
42fba21d
LB		 2546 kfree(cmd);
2547 return rc;
2548}
2549
2550/*
2551 * CMD_SET_HW_SPEC.
2552 */
2553struct mwl8k_cmd_set_hw_spec {
2554 struct mwl8k_cmd_pkt header;
2555 __u8 hw_rev;
2556 __u8 host_interface;
2557 __le16 num_mcaddrs;
2558 __u8 perm_addr[ETH_ALEN];
2559 __le16 region_code;
2560 __le32 fw_rev;
2561 __le32 ps_cookie;
2562 __le32 caps;
2563 __le32 rx_queue_ptr;
2564 __le32 num_tx_queues;
e600707b 2565 __le32 tx_queue_ptrs[MWL8K_MAX_TX_QUEUES];
42fba21d
LB		 2566 __le32 flags;
2567 __le32 num_tx_desc_per_queue;
2568 __le32 total_rxd;
ba2d3587 2569} __packed;
42fba21d 2570
8a7a578c
BC		 2571/* If enabled, MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY will cause
2572 * packets to expire 500 ms after the timestamp in the tx descriptor. That is,
2573 * the packets that are queued for more than 500ms, will be dropped in the
2574 * hardware. This helps minimizing the issues caused due to head-of-line
2575 * blocking where a slow client can hog the bandwidth and affect traffic to a
2576 * faster client.
2577 */
2578#define MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY 0x00000400
3373b28e 2579#define MWL8K_SET_HW_SPEC_FLAG_GENERATE_CCMP_HDR 0x00000200
b64fe619
LB		 2580#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
2581#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
2582#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB		 2583
2584static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
2585{
2586 struct mwl8k_priv *priv = hw->priv;
2587 struct mwl8k_cmd_set_hw_spec *cmd;
2588 int rc;
2589 int i;
2590
2591 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2592 if (cmd == NULL)
2593 return -ENOMEM;
2594
2595 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
2596 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2597
2598 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2599 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
e600707b 2600 cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
85c9205c
NS		 2601
2602 /*
2603 * Mac80211 stack has Q0 as highest priority and Q3 as lowest in
2604 * that order. Firmware has Q3 as highest priority and Q0 as lowest
2605 * in that order. Map Q3 of mac80211 to Q0 of firmware so that the
2606 * priority is interpreted the right way in firmware.
2607 */
e600707b
BC		 2608 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
2609 int j = mwl8k_tx_queues(priv) - 1 - i;
85c9205c
NS		 2610 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[j].txd_dma);
2611 }
2612
b64fe619
LB		 2613 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
2614 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
31d291a7 2615 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON |
3373b28e
NS		 2616 MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY |
2617 MWL8K_SET_HW_SPEC_FLAG_GENERATE_CCMP_HDR);
42fba21d
LB		 2618 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
2619 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
2620
2621 rc = mwl8k_post_cmd(hw, &cmd->header);
2622 kfree(cmd);
2623
2624 return rc;
2625}
2626
a66098da
LB		 2627/*
2628 * CMD_MAC_MULTICAST_ADR.
2629 */
2630struct mwl8k_cmd_mac_multicast_adr {
2631 struct mwl8k_cmd_pkt header;
2632 __le16 action;
2633 __le16 numaddr;
ce9e2e1b 2634 __u8 addr[0][ETH_ALEN];
a66098da
LB		 2635};
2636
d5e30845
LB		 2637#define MWL8K_ENABLE_RX_DIRECTED 0x0001
2638#define MWL8K_ENABLE_RX_MULTICAST 0x0002
2639#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
2640#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 2641
e81cd2d6 2642static struct mwl8k_cmd_pkt *
447ced07 2643__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
22bedad3 2644 struct netdev_hw_addr_list *mc_list)
a66098da 2645{
e81cd2d6 2646 struct mwl8k_priv *priv = hw->priv;
a66098da 2647 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 2648 int size;
22bedad3
JP		 2649 int mc_count = 0;
2650
2651 if (mc_list)
2652 mc_count = netdev_hw_addr_list_count(mc_list);
e81cd2d6 2653
447ced07 2654 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 2655 allmulti = 1;
2656 mc_count = 0;
2657 }
e81cd2d6
LB		 2658
2659 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 2660
e81cd2d6 2661 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 2662 if (cmd == NULL)
e81cd2d6 2663 return NULL;
a66098da
LB		 2664
2665 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
2666 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 2667 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
2668 MWL8K_ENABLE_RX_BROADCAST);
2669
2670 if (allmulti) {
2671 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
2672 } else if (mc_count) {
22bedad3
JP		 2673 struct netdev_hw_addr *ha;
2674 int i = 0;
d5e30845
LB		 2675
2676 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
2677 cmd->numaddr = cpu_to_le16(mc_count);
22bedad3
JP		 2678 netdev_hw_addr_list_for_each(ha, mc_list) {
2679 memcpy(cmd->addr[i], ha->addr, ETH_ALEN);
a66098da 2680 }
a66098da
LB		 2681 }
2682
e81cd2d6 2683 return &cmd->header;
a66098da
LB		 2684}
2685
2686/*
55489b6e 2687 * CMD_GET_STAT.
a66098da 2688 */
55489b6e 2689struct mwl8k_cmd_get_stat {
a66098da 2690 struct mwl8k_cmd_pkt header;
a66098da 2691 __le32 stats[64];
ba2d3587 2692} __packed;
a66098da
LB		 2693
2694#define MWL8K_STAT_ACK_FAILURE 9
2695#define MWL8K_STAT_RTS_FAILURE 12
2696#define MWL8K_STAT_FCS_ERROR 24
2697#define MWL8K_STAT_RTS_SUCCESS 11
2698
55489b6e
LB		 2699static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
2700 struct ieee80211_low_level_stats *stats)
a66098da 2701{
55489b6e 2702 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 2703 int rc;
2704
2705 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2706 if (cmd == NULL)
2707 return -ENOMEM;
2708
2709 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
2710 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2711
2712 rc = mwl8k_post_cmd(hw, &cmd->header);
2713 if (!rc) {
2714 stats->dot11ACKFailureCount =
2715 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
2716 stats->dot11RTSFailureCount =
2717 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
2718 stats->dot11FCSErrorCount =
2719 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
2720 stats->dot11RTSSuccessCount =
2721 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
2722 }
2723 kfree(cmd);
2724
2725 return rc;
2726}
2727
2728/*
55489b6e 2729 * CMD_RADIO_CONTROL.
a66098da 2730 */
55489b6e 2731struct mwl8k_cmd_radio_control {
a66098da
LB		 2732 struct mwl8k_cmd_pkt header;
2733 __le16 action;
2734 __le16 control;
2735 __le16 radio_on;
ba2d3587 2736} __packed;
a66098da 2737
c46563b7 2738static int
55489b6e 2739mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 2740{
2741 struct mwl8k_priv *priv = hw->priv;
55489b6e 2742 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 2743 int rc;
2744
c46563b7 2745 if (enable == priv->radio_on && !force)
a66098da
LB		 2746 return 0;
2747
a66098da
LB		 2748 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2749 if (cmd == NULL)
2750 return -ENOMEM;
2751
2752 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
2753 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2754 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 2755 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 2756 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
2757
2758 rc = mwl8k_post_cmd(hw, &cmd->header);
2759 kfree(cmd);
2760
2761 if (!rc)
c46563b7 2762 priv->radio_on = enable;
a66098da
LB		 2763
2764 return rc;
2765}
2766
55489b6e 2767static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 2768{
55489b6e 2769 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 2770}
2771
55489b6e 2772static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 2773{
55489b6e 2774 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 2775}
2776
a66098da
LB		 2777static int
2778mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
2779{
99200a99 2780 struct mwl8k_priv *priv = hw->priv;
a66098da 2781
68ce3884 2782 priv->radio_short_preamble = short_preamble;
a66098da 2783
55489b6e 2784 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 2785}
2786
2787/*
55489b6e 2788 * CMD_RF_TX_POWER.
a66098da 2789 */
41fdf097 2790#define MWL8K_RF_TX_POWER_LEVEL_TOTAL 8
a66098da 2791
55489b6e 2792struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 2793 struct mwl8k_cmd_pkt header;
2794 __le16 action;
2795 __le16 support_level;
2796 __le16 current_level;
2797 __le16 reserved;
41fdf097 2798 __le16 power_level_list[MWL8K_RF_TX_POWER_LEVEL_TOTAL];
ba2d3587 2799} __packed;
a66098da 2800
55489b6e 2801static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 2802{
55489b6e 2803 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 2804 int rc;
2805
2806 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2807 if (cmd == NULL)
2808 return -ENOMEM;
2809
2810 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2811 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2812 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2813 cmd->support_level = cpu_to_le16(dBm);
2814
2815 rc = mwl8k_post_cmd(hw, &cmd->header);
2816 kfree(cmd);
2817
2818 return rc;
2819}
2820
41fdf097
NS		 2821/*
2822 * CMD_TX_POWER.
2823 */
2824#define MWL8K_TX_POWER_LEVEL_TOTAL 12
2825
2826struct mwl8k_cmd_tx_power {
2827 struct mwl8k_cmd_pkt header;
2828 __le16 action;
2829 __le16 band;
2830 __le16 channel;
2831 __le16 bw;
2832 __le16 sub_ch;
2833 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
ba30c4a5 2834} __packed;
41fdf097
NS		 2835
2836static int mwl8k_cmd_tx_power(struct ieee80211_hw *hw,
2837 struct ieee80211_conf *conf,
2838 unsigned short pwr)
2839{
2840 struct ieee80211_channel *channel = conf->channel;
2841 struct mwl8k_cmd_tx_power *cmd;
2842 int rc;
2843 int i;
2844
2845 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2846 if (cmd == NULL)
2847 return -ENOMEM;
2848
2849 cmd->header.code = cpu_to_le16(MWL8K_CMD_TX_POWER);
2850 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2851 cmd->action = cpu_to_le16(MWL8K_CMD_SET_LIST);
2852
2853 if (channel->band == IEEE80211_BAND_2GHZ)
2854 cmd->band = cpu_to_le16(0x1);
2855 else if (channel->band == IEEE80211_BAND_5GHZ)
2856 cmd->band = cpu_to_le16(0x4);
2857
604c4ef1 2858 cmd->channel = cpu_to_le16(channel->hw_value);
41fdf097
NS		 2859
2860 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2861 conf->channel_type == NL80211_CHAN_HT20) {
2862 cmd->bw = cpu_to_le16(0x2);
2863 } else {
2864 cmd->bw = cpu_to_le16(0x4);
2865 if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2866 cmd->sub_ch = cpu_to_le16(0x3);
2867 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2868 cmd->sub_ch = cpu_to_le16(0x1);
2869 }
2870
2871 for (i = 0; i < MWL8K_TX_POWER_LEVEL_TOTAL; i++)
2872 cmd->power_level_list[i] = cpu_to_le16(pwr);
2873
2874 rc = mwl8k_post_cmd(hw, &cmd->header);
2875 kfree(cmd);
2876
2877 return rc;
2878}
2879
08b06347
LB		 2880/*
2881 * CMD_RF_ANTENNA.
2882 */
2883struct mwl8k_cmd_rf_antenna {
2884 struct mwl8k_cmd_pkt header;
2885 __le16 antenna;
2886 __le16 mode;
ba2d3587 2887} __packed;
08b06347
LB		 2888
2889#define MWL8K_RF_ANTENNA_RX 1
2890#define MWL8K_RF_ANTENNA_TX 2
2891
2892static int
2893mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2894{
2895 struct mwl8k_cmd_rf_antenna *cmd;
2896 int rc;
2897
2898 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2899 if (cmd == NULL)
2900 return -ENOMEM;
2901
2902 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2903 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2904 cmd->antenna = cpu_to_le16(antenna);
2905 cmd->mode = cpu_to_le16(mask);
2906
2907 rc = mwl8k_post_cmd(hw, &cmd->header);
2908 kfree(cmd);
2909
2910 return rc;
2911}
2912
b64fe619
LB		 2913/*
2914 * CMD_SET_BEACON.
2915 */
2916struct mwl8k_cmd_set_beacon {
2917 struct mwl8k_cmd_pkt header;
2918 __le16 beacon_len;
2919 __u8 beacon[0];
2920};
2921
aa21d0f6
LB		 2922static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw,
2923 struct ieee80211_vif *vif, u8 *beacon, int len)
b64fe619
LB		 2924{
2925 struct mwl8k_cmd_set_beacon *cmd;
2926 int rc;
2927
2928 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2929 if (cmd == NULL)
2930 return -ENOMEM;
2931
2932 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2933 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2934 cmd->beacon_len = cpu_to_le16(len);
2935 memcpy(cmd->beacon, beacon, len);
2936
aa21d0f6 2937 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 2938 kfree(cmd);
2939
2940 return rc;
2941}
2942
a66098da
LB		 2943/*
2944 * CMD_SET_PRE_SCAN.
2945 */
2946struct mwl8k_cmd_set_pre_scan {
2947 struct mwl8k_cmd_pkt header;
ba2d3587 2948} __packed;
a66098da
LB		 2949
2950static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2951{
2952 struct mwl8k_cmd_set_pre_scan *cmd;
2953 int rc;
2954
2955 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2956 if (cmd == NULL)
2957 return -ENOMEM;
2958
2959 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2960 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2961
2962 rc = mwl8k_post_cmd(hw, &cmd->header);
2963 kfree(cmd);
2964
2965 return rc;
2966}
2967
2968/*
2969 * CMD_SET_POST_SCAN.
2970 */
2971struct mwl8k_cmd_set_post_scan {
2972 struct mwl8k_cmd_pkt header;
2973 __le32 isibss;
d89173f2 2974 __u8 bssid[ETH_ALEN];
ba2d3587 2975} __packed;
a66098da
LB		 2976
2977static int
0a11dfc3 2978mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 2979{
2980 struct mwl8k_cmd_set_post_scan *cmd;
2981 int rc;
2982
2983 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2984 if (cmd == NULL)
2985 return -ENOMEM;
2986
2987 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2988 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2989 cmd->isibss = 0;
d89173f2 2990 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2991
2992 rc = mwl8k_post_cmd(hw, &cmd->header);
2993 kfree(cmd);
2994
2995 return rc;
2996}
2997
2998/*
2999 * CMD_SET_RF_CHANNEL.
3000 */
3001struct mwl8k_cmd_set_rf_channel {
3002 struct mwl8k_cmd_pkt header;
3003 __le16 action;
3004 __u8 current_channel;
3005 __le32 channel_flags;
ba2d3587 3006} __packed;
a66098da
LB		 3007
3008static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 3009 struct ieee80211_conf *conf)
a66098da 3010{
610677d2 3011 struct ieee80211_channel *channel = conf->channel;
a66098da
LB		 3012 struct mwl8k_cmd_set_rf_channel *cmd;
3013 int rc;
3014
3015 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3016 if (cmd == NULL)
3017 return -ENOMEM;
3018
3019 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
3020 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3021 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3022 cmd->current_channel = channel->hw_value;
610677d2 3023
a66098da 3024 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2 3025 cmd->channel_flags |= cpu_to_le32(0x00000001);
42574ea2
LB		 3026 else if (channel->band == IEEE80211_BAND_5GHZ)
3027 cmd->channel_flags |= cpu_to_le32(0x00000004);
610677d2
LB		 3028
3029 if (conf->channel_type == NL80211_CHAN_NO_HT ||
3030 conf->channel_type == NL80211_CHAN_HT20)
3031 cmd->channel_flags |= cpu_to_le32(0x00000080);
3032 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
3033 cmd->channel_flags |= cpu_to_le32(0x000001900);
3034 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
3035 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB		 3036
3037 rc = mwl8k_post_cmd(hw, &cmd->header);
3038 kfree(cmd);
3039
3040 return rc;
3041}
3042
3043/*
55489b6e 3044 * CMD_SET_AID.
a66098da 3045 */
55489b6e
LB		 3046#define MWL8K_FRAME_PROT_DISABLED 0x00
3047#define MWL8K_FRAME_PROT_11G 0x07
3048#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
3049#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 3050
55489b6e
LB		 3051struct mwl8k_cmd_update_set_aid {
3052 struct mwl8k_cmd_pkt header;
3053 __le16 aid;
a66098da 3054
55489b6e
LB		 3055 /* AP's MAC address (BSSID) */
3056 __u8 bssid[ETH_ALEN];
3057 __le16 protection_mode;
3058 __u8 supp_rates[14];
ba2d3587 3059} __packed;
a66098da 3060
c6e96010
LB		 3061static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
3062{
3063 int i;
3064 int j;
3065
3066 /*
3067 * Clear nonstandard rates 4 and 13.
3068 */
3069 mask &= 0x1fef;
3070
3071 for (i = 0, j = 0; i < 14; i++) {
3072 if (mask & (1 << i))
777ad375 3073 rates[j++] = mwl8k_rates_24[i].hw_value;
c6e96010
LB		 3074 }
3075}
3076
55489b6e 3077static int
c6e96010
LB		 3078mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
3079 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 3080{
55489b6e
LB		 3081 struct mwl8k_cmd_update_set_aid *cmd;
3082 u16 prot_mode;
a66098da
LB		 3083 int rc;
3084
3085 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3086 if (cmd == NULL)
3087 return -ENOMEM;
3088
55489b6e 3089 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 3090 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 3091 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 3092 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 3093
7dc6a7a7 3094 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 3095 prot_mode = MWL8K_FRAME_PROT_11G;
3096 } else {
7dc6a7a7 3097 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 3098 IEEE80211_HT_OP_MODE_PROTECTION) {
3099 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
3100 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
3101 break;
3102 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
3103 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
3104 break;
3105 default:
3106 prot_mode = MWL8K_FRAME_PROT_DISABLED;
3107 break;
3108 }
3109 }
3110 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 3111
c6e96010 3112 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 3113
3114 rc = mwl8k_post_cmd(hw, &cmd->header);
3115 kfree(cmd);
3116
3117 return rc;
3118}
3119
32060e1b 3120/*
55489b6e 3121 * CMD_SET_RATE.
32060e1b 3122 */
55489b6e
LB		 3123struct mwl8k_cmd_set_rate {
3124 struct mwl8k_cmd_pkt header;
3125 __u8 legacy_rates[14];
3126
3127 /* Bitmap for supported MCS codes. */
3128 __u8 mcs_set[16];
3129 __u8 reserved[16];
ba2d3587 3130} __packed;
32060e1b 3131
55489b6e 3132static int
c6e96010 3133mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 3134 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 3135{
55489b6e 3136 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 3137 int rc;
3138
3139 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3140 if (cmd == NULL)
3141 return -ENOMEM;
3142
55489b6e 3143 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 3144 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 3145 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 3146 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB		 3147
3148 rc = mwl8k_post_cmd(hw, &cmd->header);
3149 kfree(cmd);
3150
3151 return rc;
3152}
3153
a66098da 3154/*
55489b6e 3155 * CMD_FINALIZE_JOIN.
a66098da 3156 */
55489b6e
LB		 3157#define MWL8K_FJ_BEACON_MAXLEN 128
3158
3159struct mwl8k_cmd_finalize_join {
a66098da 3160 struct mwl8k_cmd_pkt header;
55489b6e
LB		 3161 __le32 sleep_interval; /* Number of beacon periods to sleep */
3162 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
ba2d3587 3163} __packed;
a66098da 3164
55489b6e
LB		 3165static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
3166 int framelen, int dtim)
a66098da 3167{
55489b6e
LB		 3168 struct mwl8k_cmd_finalize_join *cmd;
3169 struct ieee80211_mgmt *payload = frame;
3170 int payload_len;
a66098da
LB		 3171 int rc;
3172
3173 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3174 if (cmd == NULL)
3175 return -ENOMEM;
3176
55489b6e 3177 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 3178 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3179 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
3180
3181 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
3182 if (payload_len < 0)
3183 payload_len = 0;
3184 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
3185 payload_len = MWL8K_FJ_BEACON_MAXLEN;
3186
3187 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 3188
3189 rc = mwl8k_post_cmd(hw, &cmd->header);
3190 kfree(cmd);
3191
3192 return rc;
3193}
3194
3195/*
55489b6e 3196 * CMD_SET_RTS_THRESHOLD.
a66098da 3197 */
55489b6e 3198struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 3199 struct mwl8k_cmd_pkt header;
3200 __le16 action;
55489b6e 3201 __le16 threshold;
ba2d3587 3202} __packed;
a66098da 3203
c2c2b12a
LB		 3204static int
3205mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 3206{
55489b6e 3207 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 3208 int rc;
3209
3210 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3211 if (cmd == NULL)
3212 return -ENOMEM;
3213
55489b6e 3214 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 3215 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB		 3216 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3217 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB		 3218
3219 rc = mwl8k_post_cmd(hw, &cmd->header);
3220 kfree(cmd);
3221
a66098da
LB		 3222 return rc;
3223}
3224
3225/*
55489b6e 3226 * CMD_SET_SLOT.
a66098da 3227 */
55489b6e 3228struct mwl8k_cmd_set_slot {
a66098da
LB		 3229 struct mwl8k_cmd_pkt header;
3230 __le16 action;
55489b6e 3231 __u8 short_slot;
ba2d3587 3232} __packed;
a66098da 3233
55489b6e 3234static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 3235{
55489b6e 3236 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 3237 int rc;
3238
3239 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3240 if (cmd == NULL)
3241 return -ENOMEM;
3242
55489b6e 3243 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 3244 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3245 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3246 cmd->short_slot = short_slot_time;
a66098da
LB		 3247
3248 rc = mwl8k_post_cmd(hw, &cmd->header);
3249 kfree(cmd);
3250
3251 return rc;
3252}
3253
3254/*
3255 * CMD_SET_EDCA_PARAMS.
3256 */
3257struct mwl8k_cmd_set_edca_params {
3258 struct mwl8k_cmd_pkt header;
3259
3260 /* See MWL8K_SET_EDCA_XXX below */
3261 __le16 action;
3262
3263 /* TX opportunity in units of 32 us */
3264 __le16 txop;
3265
2e484c89
LB		 3266 union {
3267 struct {
3268 /* Log exponent of max contention period: 0...15 */
3269 __le32 log_cw_max;
3270
3271 /* Log exponent of min contention period: 0...15 */
3272 __le32 log_cw_min;
3273
3274 /* Adaptive interframe spacing in units of 32us */
3275 __u8 aifs;
3276
3277 /* TX queue to configure */
3278 __u8 txq;
3279 } ap;
3280 struct {
3281 /* Log exponent of max contention period: 0...15 */
3282 __u8 log_cw_max;
a66098da 3283
2e484c89
LB		 3284 /* Log exponent of min contention period: 0...15 */
3285 __u8 log_cw_min;
a66098da 3286
2e484c89
LB		 3287 /* Adaptive interframe spacing in units of 32us */
3288 __u8 aifs;
a66098da 3289
2e484c89
LB		 3290 /* TX queue to configure */
3291 __u8 txq;
3292 } sta;
3293 };
ba2d3587 3294} __packed;
a66098da 3295
a66098da
LB		 3296#define MWL8K_SET_EDCA_CW 0x01
3297#define MWL8K_SET_EDCA_TXOP 0x02
3298#define MWL8K_SET_EDCA_AIFS 0x04
3299
3300#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
3301 MWL8K_SET_EDCA_TXOP | \
3302 MWL8K_SET_EDCA_AIFS)
3303
3304static int
55489b6e
LB		 3305mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
3306 __u16 cw_min, __u16 cw_max,
3307 __u8 aifs, __u16 txop)
a66098da 3308{
2e484c89 3309 struct mwl8k_priv *priv = hw->priv;
a66098da 3310 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 3311 int rc;
3312
3313 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3314 if (cmd == NULL)
3315 return -ENOMEM;
3316
a66098da
LB		 3317 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
3318 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 3319 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
3320 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 3321 if (priv->ap_fw) {
3322 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
3323 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
3324 cmd->ap.aifs = aifs;
3325 cmd->ap.txq = qnum;
3326 } else {
3327 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
3328 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
3329 cmd->sta.aifs = aifs;
3330 cmd->sta.txq = qnum;
3331 }
a66098da
LB		 3332
3333 rc = mwl8k_post_cmd(hw, &cmd->header);
3334 kfree(cmd);
3335
3336 return rc;
3337}
3338
3339/*
55489b6e 3340 * CMD_SET_WMM_MODE.
a66098da 3341 */
55489b6e 3342struct mwl8k_cmd_set_wmm_mode {
a66098da 3343 struct mwl8k_cmd_pkt header;
55489b6e 3344 __le16 action;
ba2d3587 3345} __packed;
a66098da 3346
55489b6e 3347static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 3348{
55489b6e
LB		 3349 struct mwl8k_priv *priv = hw->priv;
3350 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 3351 int rc;
3352
a66098da
LB		 3353 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3354 if (cmd == NULL)
3355 return -ENOMEM;
3356
55489b6e 3357 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 3358 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 3359 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 3360
3361 rc = mwl8k_post_cmd(hw, &cmd->header);
3362 kfree(cmd);
16cec43d 3363
55489b6e
LB		 3364 if (!rc)
3365 priv->wmm_enabled = enable;
a66098da
LB		 3366
3367 return rc;
3368}
3369
3370/*
55489b6e 3371 * CMD_MIMO_CONFIG.
a66098da 3372 */
55489b6e
LB		 3373struct mwl8k_cmd_mimo_config {
3374 struct mwl8k_cmd_pkt header;
3375 __le32 action;
3376 __u8 rx_antenna_map;
3377 __u8 tx_antenna_map;
ba2d3587 3378} __packed;
a66098da 3379
55489b6e 3380static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 3381{
55489b6e 3382 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 3383 int rc;
3384
3385 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3386 if (cmd == NULL)
3387 return -ENOMEM;
3388
55489b6e 3389 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 3390 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3391 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
3392 cmd->rx_antenna_map = rx;
3393 cmd->tx_antenna_map = tx;
a66098da
LB		 3394
3395 rc = mwl8k_post_cmd(hw, &cmd->header);
3396 kfree(cmd);
3397
3398 return rc;
3399}
3400
3401/*
b71ed2c6 3402 * CMD_USE_FIXED_RATE (STA version).
a66098da 3403 */
b71ed2c6
LB		 3404struct mwl8k_cmd_use_fixed_rate_sta {
3405 struct mwl8k_cmd_pkt header;
3406 __le32 action;
3407 __le32 allow_rate_drop;
3408 __le32 num_rates;
3409 struct {
3410 __le32 is_ht_rate;
3411 __le32 enable_retry;
3412 __le32 rate;
3413 __le32 retry_count;
3414 } rate_entry[8];
3415 __le32 rate_type;
3416 __le32 reserved1;
3417 __le32 reserved2;
ba2d3587 3418} __packed;
a66098da 3419
b71ed2c6
LB		 3420#define MWL8K_USE_AUTO_RATE 0x0002
3421#define MWL8K_UCAST_RATE 0
a66098da 3422
b71ed2c6 3423static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 3424{
b71ed2c6 3425 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB		 3426 int rc;
3427
3428 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3429 if (cmd == NULL)
3430 return -ENOMEM;
3431
3432 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3433 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB		 3434 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3435 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB		 3436
3437 rc = mwl8k_post_cmd(hw, &cmd->header);
3438 kfree(cmd);
3439
3440 return rc;
3441}
3442
088aab8b
LB		 3443/*
3444 * CMD_USE_FIXED_RATE (AP version).
3445 */
3446struct mwl8k_cmd_use_fixed_rate_ap {
3447 struct mwl8k_cmd_pkt header;
3448 __le32 action;
3449 __le32 allow_rate_drop;
3450 __le32 num_rates;
3451 struct mwl8k_rate_entry_ap {
3452 __le32 is_ht_rate;
3453 __le32 enable_retry;
3454 __le32 rate;
3455 __le32 retry_count;
3456 } rate_entry[4];
3457 u8 multicast_rate;
3458 u8 multicast_rate_type;
3459 u8 management_rate;
ba2d3587 3460} __packed;
088aab8b
LB		 3461
3462static int
3463mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
3464{
3465 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
3466 int rc;
3467
3468 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3469 if (cmd == NULL)
3470 return -ENOMEM;
3471
3472 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3473 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3474 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3475 cmd->multicast_rate = mcast;
3476 cmd->management_rate = mgmt;
3477
3478 rc = mwl8k_post_cmd(hw, &cmd->header);
3479 kfree(cmd);
3480
3481 return rc;
3482}
3483
55489b6e
LB		 3484/*
3485 * CMD_ENABLE_SNIFFER.
3486 */
3487struct mwl8k_cmd_enable_sniffer {
3488 struct mwl8k_cmd_pkt header;
3489 __le32 action;
ba2d3587 3490} __packed;
55489b6e
LB		 3491
3492static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
3493{
3494 struct mwl8k_cmd_enable_sniffer *cmd;
3495 int rc;
3496
3497 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3498 if (cmd == NULL)
3499 return -ENOMEM;
3500
3501 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
3502 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3503 cmd->action = cpu_to_le32(!!enable);
3504
3505 rc = mwl8k_post_cmd(hw, &cmd->header);
3506 kfree(cmd);
3507
3508 return rc;
3509}
3510
197a4e4e 3511struct mwl8k_cmd_update_mac_addr {
55489b6e
LB		 3512 struct mwl8k_cmd_pkt header;
3513 union {
3514 struct {
3515 __le16 mac_type;
3516 __u8 mac_addr[ETH_ALEN];
3517 } mbss;
3518 __u8 mac_addr[ETH_ALEN];
3519 };
ba2d3587 3520} __packed;
55489b6e 3521
ee0ddf18
LB		 3522#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
3523#define MWL8K_MAC_TYPE_SECONDARY_CLIENT 1
3524#define MWL8K_MAC_TYPE_PRIMARY_AP 2
3525#define MWL8K_MAC_TYPE_SECONDARY_AP 3
a9e00b15 3526
197a4e4e
YAP		 3527static int mwl8k_cmd_update_mac_addr(struct ieee80211_hw *hw,
3528 struct ieee80211_vif *vif, u8 *mac, bool set)
55489b6e
LB		 3529{
3530 struct mwl8k_priv *priv = hw->priv;
ee0ddf18 3531 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
197a4e4e 3532 struct mwl8k_cmd_update_mac_addr *cmd;
ee0ddf18 3533 int mac_type;
55489b6e
LB		 3534 int rc;
3535
ee0ddf18
LB		 3536 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3537 if (vif != NULL && vif->type == NL80211_IFTYPE_STATION) {
3538 if (mwl8k_vif->macid + 1 == ffs(priv->sta_macids_supported))
af458831
YAP		 3539 if (priv->ap_fw)
3540 mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3541 else
3542 mac_type = MWL8K_MAC_TYPE_PRIMARY_CLIENT;
ee0ddf18
LB		 3543 else
3544 mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3545 } else if (vif != NULL && vif->type == NL80211_IFTYPE_AP) {
3546 if (mwl8k_vif->macid + 1 == ffs(priv->ap_macids_supported))
3547 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3548 else
3549 mac_type = MWL8K_MAC_TYPE_SECONDARY_AP;
3550 }
3551
55489b6e
LB		 3552 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3553 if (cmd == NULL)
3554 return -ENOMEM;
3555
197a4e4e
YAP		 3556 if (set)
3557 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
3558 else
3559 cmd->header.code = cpu_to_le16(MWL8K_CMD_DEL_MAC_ADDR);
3560
55489b6e
LB		 3561 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3562 if (priv->ap_fw) {
ee0ddf18 3563 cmd->mbss.mac_type = cpu_to_le16(mac_type);
55489b6e
LB		 3564 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
3565 } else {
3566 memcpy(cmd->mac_addr, mac, ETH_ALEN);
3567 }
3568
aa21d0f6 3569 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
55489b6e
LB		 3570 kfree(cmd);
3571
3572 return rc;
3573}
3574
197a4e4e
YAP		 3575/*
3576 * MWL8K_CMD_SET_MAC_ADDR.
3577 */
3578static inline int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw,
3579 struct ieee80211_vif *vif, u8 *mac)
3580{
3581 return mwl8k_cmd_update_mac_addr(hw, vif, mac, true);
3582}
3583
3584/*
3585 * MWL8K_CMD_DEL_MAC_ADDR.
3586 */
3587static inline int mwl8k_cmd_del_mac_addr(struct ieee80211_hw *hw,
3588 struct ieee80211_vif *vif, u8 *mac)
3589{
3590 return mwl8k_cmd_update_mac_addr(hw, vif, mac, false);
3591}
3592
55489b6e
LB		 3593/*
3594 * CMD_SET_RATEADAPT_MODE.
3595 */
3596struct mwl8k_cmd_set_rate_adapt_mode {
3597 struct mwl8k_cmd_pkt header;
3598 __le16 action;
3599 __le16 mode;
ba2d3587 3600} __packed;
55489b6e
LB		 3601
3602static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
3603{
3604 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
3605 int rc;
3606
3607 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3608 if (cmd == NULL)
3609 return -ENOMEM;
3610
3611 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
3612 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3613 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3614 cmd->mode = cpu_to_le16(mode);
3615
3616 rc = mwl8k_post_cmd(hw, &cmd->header);
3617 kfree(cmd);
3618
3619 return rc;
3620}
3621
3aefc37e
NS		 3622/*
3623 * CMD_GET_WATCHDOG_BITMAP.
3624 */
3625struct mwl8k_cmd_get_watchdog_bitmap {
3626 struct mwl8k_cmd_pkt header;
3627 u8 bitmap;
3628} __packed;
3629
3630static int mwl8k_cmd_get_watchdog_bitmap(struct ieee80211_hw *hw, u8 *bitmap)
3631{
3632 struct mwl8k_cmd_get_watchdog_bitmap *cmd;
3633 int rc;
3634
3635 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3636 if (cmd == NULL)
3637 return -ENOMEM;
3638
3639 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_WATCHDOG_BITMAP);
3640 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3641
3642 rc = mwl8k_post_cmd(hw, &cmd->header);
3643 if (!rc)
3644 *bitmap = cmd->bitmap;
3645
3646 kfree(cmd);
3647
3648 return rc;
3649}
3650
cfacba12
YAP		 3651#define MWL8K_WMM_QUEUE_NUMBER 3
3652
3653static void mwl8k_destroy_ba(struct ieee80211_hw *hw,
3654 u8 idx);
3655
3aefc37e
NS		 3656static void mwl8k_watchdog_ba_events(struct work_struct *work)
3657{
3658 int rc;
3659 u8 bitmap = 0, stream_index;
3660 struct mwl8k_ampdu_stream *streams;
3661 struct mwl8k_priv *priv =
3662 container_of(work, struct mwl8k_priv, watchdog_ba_handle);
cfacba12
YAP		 3663 struct ieee80211_hw *hw = priv->hw;
3664 int i;
3665 u32 status = 0;
3666
3667 mwl8k_fw_lock(hw);
3aefc37e
NS		 3668
3669 rc = mwl8k_cmd_get_watchdog_bitmap(priv->hw, &bitmap);
3670 if (rc)
cfacba12 3671 goto done;
3aefc37e 3672
cfacba12 3673 spin_lock(&priv->stream_lock);
3aefc37e
NS		 3674
3675 /* the bitmap is the hw queue number. Map it to the ampdu queue. */
cfacba12
YAP		 3676 for (i = 0; i < TOTAL_HW_TX_QUEUES; i++) {
3677 if (bitmap & (1 << i)) {
3678 stream_index = (i + MWL8K_WMM_QUEUE_NUMBER) %
3679 TOTAL_HW_TX_QUEUES;
3680 streams = &priv->ampdu[stream_index];
3681 if (streams->state == AMPDU_STREAM_ACTIVE) {
3682 ieee80211_stop_tx_ba_session(streams->sta,
3683 streams->tid);
3684 spin_unlock(&priv->stream_lock);
3685 mwl8k_destroy_ba(hw, stream_index);
3686 spin_lock(&priv->stream_lock);
3687 }
3688 }
3689 }
3aefc37e 3690
cfacba12
YAP		 3691 spin_unlock(&priv->stream_lock);
3692done:
c27a54d3 3693 atomic_dec(&priv->watchdog_event_pending);
cfacba12
YAP		 3694 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3695 iowrite32((status | MWL8K_A2H_INT_BA_WATCHDOG),
3696 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3697 mwl8k_fw_unlock(hw);
3aefc37e
NS		 3698 return;
3699}
3700
3701
b64fe619
LB		 3702/*
3703 * CMD_BSS_START.
3704 */
3705struct mwl8k_cmd_bss_start {
3706 struct mwl8k_cmd_pkt header;
3707 __le32 enable;
ba2d3587 3708} __packed;
b64fe619 3709
aa21d0f6
LB		 3710static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw,
3711 struct ieee80211_vif *vif, int enable)
b64fe619
LB		 3712{
3713 struct mwl8k_cmd_bss_start *cmd;
e882efc9
YAP		 3714 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3715 struct mwl8k_priv *priv = hw->priv;
b64fe619
LB		 3716 int rc;
3717
e882efc9
YAP		 3718 if (enable && (priv->running_bsses & (1 << mwl8k_vif->macid)))
3719 return 0;
3720
3721 if (!enable && !(priv->running_bsses & (1 << mwl8k_vif->macid)))
3722 return 0;
3723
b64fe619
LB		 3724 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3725 if (cmd == NULL)
3726 return -ENOMEM;
3727
3728 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
3729 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3730 cmd->enable = cpu_to_le32(enable);
3731
aa21d0f6 3732 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 3733 kfree(cmd);
3734
e882efc9
YAP		 3735 if (!rc) {
3736 if (enable)
3737 priv->running_bsses |= (1 << mwl8k_vif->macid);
3738 else
3739 priv->running_bsses &= ~(1 << mwl8k_vif->macid);
3740 }
b64fe619
LB		 3741 return rc;
3742}
3743
e882efc9
YAP		 3744static void mwl8k_enable_bsses(struct ieee80211_hw *hw, bool enable, u32 bitmap)
3745{
3746 struct mwl8k_priv *priv = hw->priv;
3747 struct mwl8k_vif *mwl8k_vif, *tmp_vif;
3748 struct ieee80211_vif *vif;
3749
3750 list_for_each_entry_safe(mwl8k_vif, tmp_vif, &priv->vif_list, list) {
3751 vif = mwl8k_vif->vif;
3752
3753 if (!(bitmap & (1 << mwl8k_vif->macid)))
3754 continue;
3755
3756 if (vif->type == NL80211_IFTYPE_AP)
3757 mwl8k_cmd_bss_start(hw, vif, enable);
3758 }
3759}
5faa1aff
NS		 3760/*
3761 * CMD_BASTREAM.
3762 */
3763
3764/*
3765 * UPSTREAM is tx direction
3766 */
3767#define BASTREAM_FLAG_DIRECTION_UPSTREAM 0x00
3768#define BASTREAM_FLAG_IMMEDIATE_TYPE 0x01
3769
ba30c4a5 3770enum ba_stream_action_type {
5faa1aff
NS		 3771 MWL8K_BA_CREATE,
3772 MWL8K_BA_UPDATE,
3773 MWL8K_BA_DESTROY,
3774 MWL8K_BA_FLUSH,
3775 MWL8K_BA_CHECK,
ba30c4a5 3776};
5faa1aff
NS		 3777
3778
3779struct mwl8k_create_ba_stream {
3780 __le32 flags;
3781 __le32 idle_thrs;
3782 __le32 bar_thrs;
3783 __le32 window_size;
3784 u8 peer_mac_addr[6];
3785 u8 dialog_token;
3786 u8 tid;
3787 u8 queue_id;
3788 u8 param_info;
3789 __le32 ba_context;
3790 u8 reset_seq_no_flag;
3791 __le16 curr_seq_no;
3792 u8 sta_src_mac_addr[6];
3793} __packed;
3794
3795struct mwl8k_destroy_ba_stream {
3796 __le32 flags;
3797 __le32 ba_context;
3798} __packed;
3799
3800struct mwl8k_cmd_bastream {
3801 struct mwl8k_cmd_pkt header;
3802 __le32 action;
3803 union {
3804 struct mwl8k_create_ba_stream create_params;
3805 struct mwl8k_destroy_ba_stream destroy_params;
3806 };
3807} __packed;
3808
3809static int
f95275c4
YAP		 3810mwl8k_check_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream,
3811 struct ieee80211_vif *vif)
5faa1aff
NS		 3812{
3813 struct mwl8k_cmd_bastream *cmd;
3814 int rc;
3815
3816 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3817 if (cmd == NULL)
3818 return -ENOMEM;
3819
3820 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3821 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3822
3823 cmd->action = cpu_to_le32(MWL8K_BA_CHECK);
3824
3825 cmd->create_params.queue_id = stream->idx;
3826 memcpy(&cmd->create_params.peer_mac_addr[0], stream->sta->addr,
3827 ETH_ALEN);
3828 cmd->create_params.tid = stream->tid;
3829
3830 cmd->create_params.flags =
3831 cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE) |
3832 cpu_to_le32(BASTREAM_FLAG_DIRECTION_UPSTREAM);
3833
f95275c4 3834 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
5faa1aff
NS		 3835
3836 kfree(cmd);
3837
3838 return rc;
3839}
3840
3841static int
3842mwl8k_create_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream,
f95275c4 3843 u8 buf_size, struct ieee80211_vif *vif)
5faa1aff
NS		 3844{
3845 struct mwl8k_cmd_bastream *cmd;
3846 int rc;
3847
3848 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3849 if (cmd == NULL)
3850 return -ENOMEM;
3851
3852
3853 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3854 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3855
3856 cmd->action = cpu_to_le32(MWL8K_BA_CREATE);
3857
3858 cmd->create_params.bar_thrs = cpu_to_le32((u32)buf_size);
3859 cmd->create_params.window_size = cpu_to_le32((u32)buf_size);
3860 cmd->create_params.queue_id = stream->idx;
3861
3862 memcpy(cmd->create_params.peer_mac_addr, stream->sta->addr, ETH_ALEN);
3863 cmd->create_params.tid = stream->tid;
3864 cmd->create_params.curr_seq_no = cpu_to_le16(0);
3865 cmd->create_params.reset_seq_no_flag = 1;
3866
3867 cmd->create_params.param_info =
3868 (stream->sta->ht_cap.ampdu_factor &
3869 IEEE80211_HT_AMPDU_PARM_FACTOR) |
3870 ((stream->sta->ht_cap.ampdu_density << 2) &
3871 IEEE80211_HT_AMPDU_PARM_DENSITY);
3872
3873 cmd->create_params.flags =
3874 cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE |
3875 BASTREAM_FLAG_DIRECTION_UPSTREAM);
3876
f95275c4 3877 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
5faa1aff
NS		 3878
3879 wiphy_debug(hw->wiphy, "Created a BA stream for %pM : tid %d\n",
3880 stream->sta->addr, stream->tid);
3881 kfree(cmd);
3882
3883 return rc;
3884}
3885
3886static void mwl8k_destroy_ba(struct ieee80211_hw *hw,
07f6dda1 3887 u8 idx)
5faa1aff
NS		 3888{
3889 struct mwl8k_cmd_bastream *cmd;
3890
3891 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3892 if (cmd == NULL)
3893 return;
3894
3895 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3896 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3897 cmd->action = cpu_to_le32(MWL8K_BA_DESTROY);
3898
07f6dda1 3899 cmd->destroy_params.ba_context = cpu_to_le32(idx);
5faa1aff
NS		 3900 mwl8k_post_cmd(hw, &cmd->header);
3901
07f6dda1 3902 wiphy_debug(hw->wiphy, "Deleted BA stream index %d\n", idx);
5faa1aff
NS		 3903
3904 kfree(cmd);
3905}
3906
3f5610ff
LB		 3907/*
3908 * CMD_SET_NEW_STN.
3909 */
3910struct mwl8k_cmd_set_new_stn {
3911 struct mwl8k_cmd_pkt header;
3912 __le16 aid;
3913 __u8 mac_addr[6];
3914 __le16 stn_id;
3915 __le16 action;
3916 __le16 rsvd;
3917 __le32 legacy_rates;
3918 __u8 ht_rates[4];
3919 __le16 cap_info;
3920 __le16 ht_capabilities_info;
3921 __u8 mac_ht_param_info;
3922 __u8 rev;
3923 __u8 control_channel;
3924 __u8 add_channel;
3925 __le16 op_mode;
3926 __le16 stbc;
3927 __u8 add_qos_info;
3928 __u8 is_qos_sta;
3929 __le32 fw_sta_ptr;
ba2d3587 3930} __packed;
3f5610ff
LB		 3931
3932#define MWL8K_STA_ACTION_ADD 0
3933#define MWL8K_STA_ACTION_REMOVE 2
3934
3935static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
3936 struct ieee80211_vif *vif,
3937 struct ieee80211_sta *sta)
3938{
3939 struct mwl8k_cmd_set_new_stn *cmd;
8707d026 3940 u32 rates;
3f5610ff
LB		 3941 int rc;
3942
3943 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3944 if (cmd == NULL)
3945 return -ENOMEM;
3946
3947 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3948 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3949 cmd->aid = cpu_to_le16(sta->aid);
3950 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
3951 cmd->stn_id = cpu_to_le16(sta->aid);
3952 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
8707d026
LB		 3953 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3954 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
3955 else
3956 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3957 cmd->legacy_rates = cpu_to_le32(rates);
3f5610ff
LB		 3958 if (sta->ht_cap.ht_supported) {
3959 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
3960 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
3961 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
3962 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
3963 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
3964 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
3965 ((sta->ht_cap.ampdu_density & 7) << 2);
3966 cmd->is_qos_sta = 1;
3967 }
3968
aa21d0f6 3969 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 3970 kfree(cmd);
3971
3972 return rc;
3973}
3974
b64fe619
LB		 3975static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
3976 struct ieee80211_vif *vif)
3977{
3978 struct mwl8k_cmd_set_new_stn *cmd;
3979 int rc;
3980
3981 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3982 if (cmd == NULL)
3983 return -ENOMEM;
3984
3985 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3986 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3987 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
3988
aa21d0f6 3989 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 3990 kfree(cmd);
3991
3992 return rc;
3993}
3994
3f5610ff
LB		 3995static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
3996 struct ieee80211_vif *vif, u8 *addr)
3997{
3998 struct mwl8k_cmd_set_new_stn *cmd;
0dd13a48
YAP		 3999 struct mwl8k_priv *priv = hw->priv;
4000 int rc, i;
4001 u8 idx;
4002
4003 spin_lock(&priv->stream_lock);
4004 /* Destroy any active ampdu streams for this sta */
4005 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
4006 struct mwl8k_ampdu_stream *s;
4007 s = &priv->ampdu[i];
4008 if (s->state != AMPDU_NO_STREAM) {
4009 if (memcmp(s->sta->addr, addr, ETH_ALEN) == 0) {
4010 if (s->state == AMPDU_STREAM_ACTIVE) {
4011 idx = s->idx;
4012 spin_unlock(&priv->stream_lock);
4013 mwl8k_destroy_ba(hw, idx);
4014 spin_lock(&priv->stream_lock);
4015 } else if (s->state == AMPDU_STREAM_NEW) {
4016 mwl8k_remove_stream(hw, s);
4017 }
4018 }
4019 }
4020 }
4021
4022 spin_unlock(&priv->stream_lock);
3f5610ff
LB		 4023
4024 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4025 if (cmd == NULL)
4026 return -ENOMEM;
4027
4028 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
4029 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4030 memcpy(cmd->mac_addr, addr, ETH_ALEN);
4031 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
4032
aa21d0f6 4033 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 4034 kfree(cmd);
4035
4036 return rc;
4037}
4038
fcdc403c
NS		 4039/*
4040 * CMD_UPDATE_ENCRYPTION.
4041 */
4042
4043#define MAX_ENCR_KEY_LENGTH 16
4044#define MIC_KEY_LENGTH 8
4045
4046struct mwl8k_cmd_update_encryption {
4047 struct mwl8k_cmd_pkt header;
4048
4049 __le32 action;
4050 __le32 reserved;
4051 __u8 mac_addr[6];
4052 __u8 encr_type;
4053
ba30c4a5 4054} __packed;
fcdc403c
NS		 4055
4056struct mwl8k_cmd_set_key {
4057 struct mwl8k_cmd_pkt header;
4058
4059 __le32 action;
4060 __le32 reserved;
4061 __le16 length;
4062 __le16 key_type_id;
4063 __le32 key_info;
4064 __le32 key_id;
4065 __le16 key_len;
4066 __u8 key_material[MAX_ENCR_KEY_LENGTH];
4067 __u8 tkip_tx_mic_key[MIC_KEY_LENGTH];
4068 __u8 tkip_rx_mic_key[MIC_KEY_LENGTH];
4069 __le16 tkip_rsc_low;
4070 __le32 tkip_rsc_high;
4071 __le16 tkip_tsc_low;
4072 __le32 tkip_tsc_high;
4073 __u8 mac_addr[6];
ba30c4a5 4074} __packed;
fcdc403c
NS		 4075
4076enum {
4077 MWL8K_ENCR_ENABLE,
4078 MWL8K_ENCR_SET_KEY,
4079 MWL8K_ENCR_REMOVE_KEY,
4080 MWL8K_ENCR_SET_GROUP_KEY,
4081};
4082
4083#define MWL8K_UPDATE_ENCRYPTION_TYPE_WEP 0
4084#define MWL8K_UPDATE_ENCRYPTION_TYPE_DISABLE 1
4085#define MWL8K_UPDATE_ENCRYPTION_TYPE_TKIP 4
4086#define MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED 7
4087#define MWL8K_UPDATE_ENCRYPTION_TYPE_AES 8
4088
4089enum {
4090 MWL8K_ALG_WEP,
4091 MWL8K_ALG_TKIP,
4092 MWL8K_ALG_CCMP,
4093};
4094
4095#define MWL8K_KEY_FLAG_TXGROUPKEY 0x00000004
4096#define MWL8K_KEY_FLAG_PAIRWISE 0x00000008
4097#define MWL8K_KEY_FLAG_TSC_VALID 0x00000040
4098#define MWL8K_KEY_FLAG_WEP_TXKEY 0x01000000
4099#define MWL8K_KEY_FLAG_MICKEY_VALID 0x02000000
4100
4101static int mwl8k_cmd_update_encryption_enable(struct ieee80211_hw *hw,
4102 struct ieee80211_vif *vif,
4103 u8 *addr,
4104 u8 encr_type)
4105{
4106 struct mwl8k_cmd_update_encryption *cmd;
4107 int rc;
4108
4109 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4110 if (cmd == NULL)
4111 return -ENOMEM;
4112
4113 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
4114 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4115 cmd->action = cpu_to_le32(MWL8K_ENCR_ENABLE);
4116 memcpy(cmd->mac_addr, addr, ETH_ALEN);
4117 cmd->encr_type = encr_type;
4118
4119 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4120 kfree(cmd);
4121
4122 return rc;
4123}
4124
4125static int mwl8k_encryption_set_cmd_info(struct mwl8k_cmd_set_key *cmd,
4126 u8 *addr,
4127 struct ieee80211_key_conf *key)
4128{
4129 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
4130 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4131 cmd->length = cpu_to_le16(sizeof(*cmd) -
4132 offsetof(struct mwl8k_cmd_set_key, length));
4133 cmd->key_id = cpu_to_le32(key->keyidx);
4134 cmd->key_len = cpu_to_le16(key->keylen);
4135 memcpy(cmd->mac_addr, addr, ETH_ALEN);
4136
4137 switch (key->cipher) {
4138 case WLAN_CIPHER_SUITE_WEP40:
4139 case WLAN_CIPHER_SUITE_WEP104:
4140 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_WEP);
4141 if (key->keyidx == 0)
4142 cmd->key_info = cpu_to_le32(MWL8K_KEY_FLAG_WEP_TXKEY);
4143
4144 break;
4145 case WLAN_CIPHER_SUITE_TKIP:
4146 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_TKIP);
4147 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4148 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
4149 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
4150 cmd->key_info |= cpu_to_le32(MWL8K_KEY_FLAG_MICKEY_VALID
4151 | MWL8K_KEY_FLAG_TSC_VALID);
4152 break;
4153 case WLAN_CIPHER_SUITE_CCMP:
4154 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_CCMP);
4155 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4156 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
4157 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
4158 break;
4159 default:
4160 return -ENOTSUPP;
4161 }
4162
4163 return 0;
4164}
4165
4166static int mwl8k_cmd_encryption_set_key(struct ieee80211_hw *hw,
4167 struct ieee80211_vif *vif,
4168 u8 *addr,
4169 struct ieee80211_key_conf *key)
4170{
4171 struct mwl8k_cmd_set_key *cmd;
4172 int rc;
4173 int keymlen;
4174 u32 action;
4175 u8 idx;
4176 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4177
4178 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4179 if (cmd == NULL)
4180 return -ENOMEM;
4181
4182 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
4183 if (rc < 0)
4184 goto done;
4185
4186 idx = key->keyidx;
4187
4188 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4189 action = MWL8K_ENCR_SET_KEY;
4190 else
4191 action = MWL8K_ENCR_SET_GROUP_KEY;
4192
4193 switch (key->cipher) {
4194 case WLAN_CIPHER_SUITE_WEP40:
4195 case WLAN_CIPHER_SUITE_WEP104:
4196 if (!mwl8k_vif->wep_key_conf[idx].enabled) {
4197 memcpy(mwl8k_vif->wep_key_conf[idx].key, key,
4198 sizeof(*key) + key->keylen);
4199 mwl8k_vif->wep_key_conf[idx].enabled = 1;
4200 }
4201
9b571e24 4202 keymlen = key->keylen;
fcdc403c
NS		 4203 action = MWL8K_ENCR_SET_KEY;
4204 break;
4205 case WLAN_CIPHER_SUITE_TKIP:
4206 keymlen = MAX_ENCR_KEY_LENGTH + 2 * MIC_KEY_LENGTH;
4207 break;
4208 case WLAN_CIPHER_SUITE_CCMP:
4209 keymlen = key->keylen;
4210 break;
4211 default:
4212 rc = -ENOTSUPP;
4213 goto done;
4214 }
4215
4216 memcpy(cmd->key_material, key->key, keymlen);
4217 cmd->action = cpu_to_le32(action);
4218
4219 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4220done:
4221 kfree(cmd);
4222
4223 return rc;
4224}
4225
4226static int mwl8k_cmd_encryption_remove_key(struct ieee80211_hw *hw,
4227 struct ieee80211_vif *vif,
4228 u8 *addr,
4229 struct ieee80211_key_conf *key)
4230{
4231 struct mwl8k_cmd_set_key *cmd;
4232 int rc;
4233 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4234
4235 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4236 if (cmd == NULL)
4237 return -ENOMEM;
4238
4239 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
4240 if (rc < 0)
4241 goto done;
4242
4243 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
d981e059 4244 key->cipher == WLAN_CIPHER_SUITE_WEP104)
fcdc403c
NS		 4245 mwl8k_vif->wep_key_conf[key->keyidx].enabled = 0;
4246
4247 cmd->action = cpu_to_le32(MWL8K_ENCR_REMOVE_KEY);
4248
4249 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4250done:
4251 kfree(cmd);
4252
4253 return rc;
4254}
4255
4256static int mwl8k_set_key(struct ieee80211_hw *hw,
4257 enum set_key_cmd cmd_param,
4258 struct ieee80211_vif *vif,
4259 struct ieee80211_sta *sta,
4260 struct ieee80211_key_conf *key)
4261{
4262 int rc = 0;
4263 u8 encr_type;
4264 u8 *addr;
4265 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
751930cb 4266 struct mwl8k_priv *priv = hw->priv;
fcdc403c 4267
751930cb 4268 if (vif->type == NL80211_IFTYPE_STATION && !priv->ap_fw)
fcdc403c
NS		 4269 return -EOPNOTSUPP;
4270
4271 if (sta == NULL)
ff7e9f99 4272 addr = vif->addr;
fcdc403c
NS		 4273 else
4274 addr = sta->addr;
4275
4276 if (cmd_param == SET_KEY) {
fcdc403c
NS		 4277 rc = mwl8k_cmd_encryption_set_key(hw, vif, addr, key);
4278 if (rc)
4279 goto out;
4280
4281 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40)
4282 || (key->cipher == WLAN_CIPHER_SUITE_WEP104))
4283 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_WEP;
4284 else
4285 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED;
4286
4287 rc = mwl8k_cmd_update_encryption_enable(hw, vif, addr,
4288 encr_type);
4289 if (rc)
4290 goto out;
4291
4292 mwl8k_vif->is_hw_crypto_enabled = true;
4293
4294 } else {
4295 rc = mwl8k_cmd_encryption_remove_key(hw, vif, addr, key);
4296
4297 if (rc)
4298 goto out;
fcdc403c
NS		 4299 }
4300out:
4301 return rc;
4302}
4303
55489b6e
LB		 4304/*
4305 * CMD_UPDATE_STADB.
4306 */
25d81b1e
LB		 4307struct ewc_ht_info {
4308 __le16 control1;
4309 __le16 control2;
4310 __le16 control3;
ba2d3587 4311} __packed;
25d81b1e
LB		 4312
4313struct peer_capability_info {
4314 /* Peer type - AP vs. STA. */
4315 __u8 peer_type;
4316
4317 /* Basic 802.11 capabilities from assoc resp. */
4318 __le16 basic_caps;
4319
4320 /* Set if peer supports 802.11n high throughput (HT). */
4321 __u8 ht_support;
4322
4323 /* Valid if HT is supported. */
4324 __le16 ht_caps;
4325 __u8 extended_ht_caps;
4326 struct ewc_ht_info ewc_info;
4327
4328 /* Legacy rate table. Intersection of our rates and peer rates. */
4329 __u8 legacy_rates[12];
4330
4331 /* HT rate table. Intersection of our rates and peer rates. */
4332 __u8 ht_rates[16];
4333 __u8 pad[16];
4334
4335 /* If set, interoperability mode, no proprietary extensions. */
4336 __u8 interop;
4337 __u8 pad2;
4338 __u8 station_id;
4339 __le16 amsdu_enabled;
ba2d3587 4340} __packed;
25d81b1e 4341
55489b6e
LB		 4342struct mwl8k_cmd_update_stadb {
4343 struct mwl8k_cmd_pkt header;
4344
4345 /* See STADB_ACTION_TYPE */
4346 __le32 action;
4347
4348 /* Peer MAC address */
4349 __u8 peer_addr[ETH_ALEN];
4350
4351 __le32 reserved;
4352
4353 /* Peer info - valid during add/update. */
4354 struct peer_capability_info peer_info;
ba2d3587 4355} __packed;
55489b6e 4356
a680400e
LB		 4357#define MWL8K_STA_DB_MODIFY_ENTRY 1
4358#define MWL8K_STA_DB_DEL_ENTRY 2
4359
4360/* Peer Entry flags - used to define the type of the peer node */
4361#define MWL8K_PEER_TYPE_ACCESSPOINT 2
4362
4363static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 4364 struct ieee80211_vif *vif,
13935e2c 4365 struct ieee80211_sta *sta)
55489b6e 4366{
55489b6e 4367 struct mwl8k_cmd_update_stadb *cmd;
a680400e 4368 struct peer_capability_info *p;
8707d026 4369 u32 rates;
55489b6e
LB		 4370 int rc;
4371
4372 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4373 if (cmd == NULL)
4374 return -ENOMEM;
4375
4376 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4377 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 4378 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 4379 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 4380
a680400e
LB		 4381 p = &cmd->peer_info;
4382 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
4383 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c 4384 p->ht_support = sta->ht_cap.ht_supported;
b603742f 4385 p->ht_caps = cpu_to_le16(sta->ht_cap.cap);
13935e2c
LB		 4386 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
4387 ((sta->ht_cap.ampdu_density & 7) << 2);
8707d026
LB		 4388 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
4389 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
4390 else
4391 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
4392 legacy_rate_mask_to_array(p->legacy_rates, rates);
13935e2c 4393 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB		 4394 p->interop = 1;
4395 p->amsdu_enabled = 0;
4396
4397 rc = mwl8k_post_cmd(hw, &cmd->header);
c4f74d35
NZ		 4398 if (!rc)
4399 rc = p->station_id;
a680400e
LB		 4400 kfree(cmd);
4401
c4f74d35 4402 return rc;
a680400e
LB		 4403}
4404
4405static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
4406 struct ieee80211_vif *vif, u8 *addr)
4407{
4408 struct mwl8k_cmd_update_stadb *cmd;
4409 int rc;
4410
4411 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4412 if (cmd == NULL)
4413 return -ENOMEM;
4414
4415 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4416 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4417 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 4418 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 4419
a680400e 4420 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 4421 kfree(cmd);
4422
4423 return rc;
4424}
4425
a66098da
LB		 4426
4427/*
4428 * Interrupt handling.
4429 */
4430static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
4431{
4432 struct ieee80211_hw *hw = dev_id;
4433 struct mwl8k_priv *priv = hw->priv;
4434 u32 status;
4435
4436 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB		 4437 if (!status)
4438 return IRQ_NONE;
4439
1e9f9de3
LB		 4440 if (status & MWL8K_A2H_INT_TX_DONE) {
4441 status &= ~MWL8K_A2H_INT_TX_DONE;
4442 tasklet_schedule(&priv->poll_tx_task);
4443 }
4444
a66098da 4445 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB		 4446 status &= ~MWL8K_A2H_INT_RX_READY;
4447 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB		 4448 }
4449
3aefc37e 4450 if (status & MWL8K_A2H_INT_BA_WATCHDOG) {
c27a54d3
YAP		 4451 iowrite32(~MWL8K_A2H_INT_BA_WATCHDOG,
4452 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
4453
4454 atomic_inc(&priv->watchdog_event_pending);
3aefc37e
NS		 4455 status &= ~MWL8K_A2H_INT_BA_WATCHDOG;
4456 ieee80211_queue_work(hw, &priv->watchdog_ba_handle);
4457 }
4458
67e2eb27
LB		 4459 if (status)
4460 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4461
a66098da 4462 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 4463 if (priv->hostcmd_wait != NULL)
a66098da 4464 complete(priv->hostcmd_wait);
a66098da
LB		 4465 }
4466
4467 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 4468 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 4469 priv->radio_on && priv->pending_tx_pkts)
618952a7 4470 mwl8k_tx_start(priv);
a66098da
LB		 4471 }
4472
4473 return IRQ_HANDLED;
4474}
4475
1e9f9de3
LB		 4476static void mwl8k_tx_poll(unsigned long data)
4477{
4478 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
4479 struct mwl8k_priv *priv = hw->priv;
4480 int limit;
4481 int i;
4482
4483 limit = 32;
4484
4485 spin_lock_bh(&priv->tx_lock);
4486
e600707b 4487 for (i = 0; i < mwl8k_tx_queues(priv); i++)
1e9f9de3
LB		 4488 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
4489
4490 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
4491 complete(priv->tx_wait);
4492 priv->tx_wait = NULL;
4493 }
4494
4495 spin_unlock_bh(&priv->tx_lock);
4496
4497 if (limit) {
4498 writel(~MWL8K_A2H_INT_TX_DONE,
4499 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4500 } else {
4501 tasklet_schedule(&priv->poll_tx_task);
4502 }
4503}
4504
67e2eb27
LB		 4505static void mwl8k_rx_poll(unsigned long data)
4506{
4507 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
4508 struct mwl8k_priv *priv = hw->priv;
4509 int limit;
4510
4511 limit = 32;
4512 limit -= rxq_process(hw, 0, limit);
4513 limit -= rxq_refill(hw, 0, limit);
4514
4515 if (limit) {
4516 writel(~MWL8K_A2H_INT_RX_READY,
4517 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4518 } else {
4519 tasklet_schedule(&priv->poll_rx_task);
4520 }
4521}
4522
a66098da
LB		 4523
4524/*
4525 * Core driver operations.
4526 */
36323f81
TH		 4527static void mwl8k_tx(struct ieee80211_hw *hw,
4528 struct ieee80211_tx_control *control,
4529 struct sk_buff *skb)
a66098da
LB		 4530{
4531 struct mwl8k_priv *priv = hw->priv;
4532 int index = skb_get_queue_mapping(skb);
a66098da 4533
9189c100 4534 if (!priv->radio_on) {
c96c31e4
JP		 4535 wiphy_debug(hw->wiphy,
4536 "dropped TX frame since radio disabled\n");
a66098da 4537 dev_kfree_skb(skb);
7bb45683 4538 return;
a66098da
LB		 4539 }
4540
36323f81 4541 mwl8k_txq_xmit(hw, index, control->sta, skb);
a66098da
LB		 4542}
4543
a66098da
LB		 4544static int mwl8k_start(struct ieee80211_hw *hw)
4545{
a66098da
LB		 4546 struct mwl8k_priv *priv = hw->priv;
4547 int rc;
4548
a0607fd3 4549 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 4550 IRQF_SHARED, MWL8K_NAME, hw);
4551 if (rc) {
bf3ca7f7 4552 priv->irq = -1;
5db55844 4553 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
2ec610cb 4554 return -EIO;
a66098da 4555 }
bf3ca7f7 4556 priv->irq = priv->pdev->irq;
a66098da 4557
67e2eb27 4558 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 4559 tasklet_enable(&priv->poll_tx_task);
67e2eb27 4560 tasklet_enable(&priv->poll_rx_task);
2ec610cb 4561
a66098da 4562 /* Enable interrupts */
c23b5a69 4563 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
12488e01
NS		 4564 iowrite32(MWL8K_A2H_EVENTS,
4565 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
a66098da 4566
2ec610cb
LB		 4567 rc = mwl8k_fw_lock(hw);
4568 if (!rc) {
55489b6e 4569 rc = mwl8k_cmd_radio_enable(hw);
a66098da 4570
5e4cf166
LB		 4571 if (!priv->ap_fw) {
4572 if (!rc)
55489b6e 4573 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 4574
5e4cf166
LB		 4575 if (!rc)
4576 rc = mwl8k_cmd_set_pre_scan(hw);
4577
4578 if (!rc)
4579 rc = mwl8k_cmd_set_post_scan(hw,
4580 "\x00\x00\x00\x00\x00\x00");
4581 }
2ec610cb
LB		 4582
4583 if (!rc)
55489b6e 4584 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 4585
2ec610cb 4586 if (!rc)
55489b6e 4587 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 4588
2ec610cb
LB		 4589 mwl8k_fw_unlock(hw);
4590 }
4591
4592 if (rc) {
4593 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
4594 free_irq(priv->pdev->irq, hw);
bf3ca7f7 4595 priv->irq = -1;
1e9f9de3 4596 tasklet_disable(&priv->poll_tx_task);
67e2eb27 4597 tasklet_disable(&priv->poll_rx_task);
4850b6d3
NS		 4598 } else {
4599 ieee80211_wake_queues(hw);
2ec610cb 4600 }
a66098da
LB		 4601
4602 return rc;
4603}
4604
a66098da
LB		 4605static void mwl8k_stop(struct ieee80211_hw *hw)
4606{
a66098da
LB		 4607 struct mwl8k_priv *priv = hw->priv;
4608 int i;
4609
6b6accc3
YAP		 4610 if (!priv->hw_restart_in_progress)
4611 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 4612
4613 ieee80211_stop_queues(hw);
4614
a66098da 4615 /* Disable interrupts */
a66098da 4616 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
bf3ca7f7
BC		 4617 if (priv->irq != -1) {
4618 free_irq(priv->pdev->irq, hw);
4619 priv->irq = -1;
4620 }
a66098da
LB		 4621
4622 /* Stop finalize join worker */
4623 cancel_work_sync(&priv->finalize_join_worker);
3aefc37e 4624 cancel_work_sync(&priv->watchdog_ba_handle);
a66098da
LB		 4625 if (priv->beacon_skb != NULL)
4626 dev_kfree_skb(priv->beacon_skb);
4627
67e2eb27 4628 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 4629 tasklet_disable(&priv->poll_tx_task);
67e2eb27 4630 tasklet_disable(&priv->poll_rx_task);
a66098da 4631
a66098da 4632 /* Return all skbs to mac80211 */
e600707b 4633 for (i = 0; i < mwl8k_tx_queues(priv); i++)
efb7c49a 4634 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB		 4635}
4636
0863ade8
BC		 4637static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image);
4638
a66098da 4639static int mwl8k_add_interface(struct ieee80211_hw *hw,
f5bb87cf 4640 struct ieee80211_vif *vif)
a66098da
LB		 4641{
4642 struct mwl8k_priv *priv = hw->priv;
4643 struct mwl8k_vif *mwl8k_vif;
ee0ddf18 4644 u32 macids_supported;
0863ade8
BC		 4645 int macid, rc;
4646 struct mwl8k_device_info *di;
a66098da 4647
a43c49a8
LB		 4648 /*
4649 * Reject interface creation if sniffer mode is active, as
4650 * STA operation is mutually exclusive with hardware sniffer
b64fe619 4651 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB		 4652 */
4653 if (priv->sniffer_enabled) {
c96c31e4
JP		 4654 wiphy_info(hw->wiphy,
4655 "unable to create STA interface because sniffer mode is enabled\n");
a43c49a8
LB		 4656 return -EINVAL;
4657 }
4658
0863ade8 4659 di = priv->device_info;
ee0ddf18
LB		 4660 switch (vif->type) {
4661 case NL80211_IFTYPE_AP:
0863ade8
BC		 4662 if (!priv->ap_fw && di->fw_image_ap) {
4663 /* we must load the ap fw to meet this request */
4664 if (!list_empty(&priv->vif_list))
4665 return -EBUSY;
4666 rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
4667 if (rc)
4668 return rc;
4669 }
ee0ddf18
LB		 4670 macids_supported = priv->ap_macids_supported;
4671 break;
4672 case NL80211_IFTYPE_STATION:
0863ade8 4673 if (priv->ap_fw && di->fw_image_sta) {
d59c1cfd
YAP		 4674 if (!list_empty(&priv->vif_list)) {
4675 wiphy_warn(hw->wiphy, "AP interface is running.\n"
4676 "Adding STA interface for WDS");
4677 } else {
4678 /* we must load the sta fw to
4679 * meet this request.
4680 */
4681 rc = mwl8k_reload_firmware(hw,
4682 di->fw_image_sta);
4683 if (rc)
4684 return rc;
4685 }
0863ade8 4686 }
ee0ddf18
LB		 4687 macids_supported = priv->sta_macids_supported;
4688 break;
4689 default:
4690 return -EINVAL;
4691 }
4692
4693 macid = ffs(macids_supported & ~priv->macids_used);
4694 if (!macid--)
4695 return -EBUSY;
4696
f5bb87cf 4697 /* Setup driver private area. */
1ed32e4f 4698 mwl8k_vif = MWL8K_VIF(vif);
a66098da 4699 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
f5bb87cf 4700 mwl8k_vif->vif = vif;
ee0ddf18 4701 mwl8k_vif->macid = macid;
a66098da 4702 mwl8k_vif->seqno = 0;
d9a07d49
NS		 4703 memcpy(mwl8k_vif->bssid, vif->addr, ETH_ALEN);
4704 mwl8k_vif->is_hw_crypto_enabled = false;
a66098da 4705
aa21d0f6
LB		 4706 /* Set the mac address. */
4707 mwl8k_cmd_set_mac_addr(hw, vif, vif->addr);
4708
d994a1c8 4709 if (vif->type == NL80211_IFTYPE_AP)
aa21d0f6
LB		 4710 mwl8k_cmd_set_new_stn_add_self(hw, vif);
4711
ee0ddf18 4712 priv->macids_used |= 1 << mwl8k_vif->macid;
f5bb87cf 4713 list_add_tail(&mwl8k_vif->list, &priv->vif_list);
a66098da
LB		 4714
4715 return 0;
4716}
4717
6b6accc3
YAP		 4718static void mwl8k_remove_vif(struct mwl8k_priv *priv, struct mwl8k_vif *vif)
4719{
4720 /* Has ieee80211_restart_hw re-added the removed interfaces? */
4721 if (!priv->macids_used)
4722 return;
4723
4724 priv->macids_used &= ~(1 << vif->macid);
4725 list_del(&vif->list);
4726}
4727
a66098da 4728static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4729 struct ieee80211_vif *vif)
a66098da
LB		 4730{
4731 struct mwl8k_priv *priv = hw->priv;
f5bb87cf 4732 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
a66098da 4733
d994a1c8 4734 if (vif->type == NL80211_IFTYPE_AP)
b64fe619
LB		 4735 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
4736
197a4e4e 4737 mwl8k_cmd_del_mac_addr(hw, vif, vif->addr);
32060e1b 4738
6b6accc3
YAP		 4739 mwl8k_remove_vif(priv, mwl8k_vif);
4740}
4741
4742static void mwl8k_hw_restart_work(struct work_struct *work)
4743{
4744 struct mwl8k_priv *priv =
4745 container_of(work, struct mwl8k_priv, fw_reload);
4746 struct ieee80211_hw *hw = priv->hw;
4747 struct mwl8k_device_info *di;
4748 int rc;
4749
4750 /* If some command is waiting for a response, clear it */
4751 if (priv->hostcmd_wait != NULL) {
4752 complete(priv->hostcmd_wait);
4753 priv->hostcmd_wait = NULL;
4754 }
4755
4756 priv->hw_restart_owner = current;
4757 di = priv->device_info;
4758 mwl8k_fw_lock(hw);
4759
4760 if (priv->ap_fw)
4761 rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
4762 else
4763 rc = mwl8k_reload_firmware(hw, di->fw_image_sta);
4764
4765 if (rc)
4766 goto fail;
4767
4768 priv->hw_restart_owner = NULL;
4769 priv->hw_restart_in_progress = false;
4770
4771 /*
4772 * This unlock will wake up the queues and
4773 * also opens the command path for other
4774 * commands
4775 */
4776 mwl8k_fw_unlock(hw);
4777
4778 ieee80211_restart_hw(hw);
4779
4780 wiphy_err(hw->wiphy, "Firmware restarted successfully\n");
4781
4782 return;
4783fail:
4784 mwl8k_fw_unlock(hw);
4785
4786 wiphy_err(hw->wiphy, "Firmware restart failed\n");
a66098da
LB		 4787}
4788
ee03a932 4789static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 4790{
a66098da
LB		 4791 struct ieee80211_conf *conf = &hw->conf;
4792 struct mwl8k_priv *priv = hw->priv;
ee03a932 4793 int rc;
a66098da 4794
7595d67a 4795 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 4796 mwl8k_cmd_radio_disable(hw);
ee03a932 4797 return 0;
7595d67a
LB		 4798 }
4799
ee03a932
LB		 4800 rc = mwl8k_fw_lock(hw);
4801 if (rc)
4802 return rc;
a66098da 4803
55489b6e 4804 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 4805 if (rc)
4806 goto out;
a66098da 4807
0f4316b9
YAP		 4808 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
4809 rc = mwl8k_cmd_set_rf_channel(hw, conf);
4810 if (rc)
4811 goto out;
4812 }
ee03a932 4813
a66098da
LB		 4814 if (conf->power_level > 18)
4815 conf->power_level = 18;
a66098da 4816
08b06347 4817 if (priv->ap_fw) {
03217087
NS		 4818
4819 if (conf->flags & IEEE80211_CONF_CHANGE_POWER) {
4820 rc = mwl8k_cmd_tx_power(hw, conf, conf->power_level);
4821 if (rc)
4822 goto out;
4823 }
41fdf097 4824
da62b761 4825
08b06347 4826 } else {
41fdf097
NS		 4827 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
4828 if (rc)
4829 goto out;
08b06347
LB		 4830 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
4831 }
a66098da 4832
ee03a932
LB		 4833out:
4834 mwl8k_fw_unlock(hw);
a66098da 4835
ee03a932 4836 return rc;
a66098da
LB		 4837}
4838
b64fe619
LB		 4839static void
4840mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4841 struct ieee80211_bss_conf *info, u32 changed)
a66098da 4842{
a66098da 4843 struct mwl8k_priv *priv = hw->priv;
ba30c4a5 4844 u32 ap_legacy_rates = 0;
13935e2c 4845 u8 ap_mcs_rates[16];
3a980d0a
LB		 4846 int rc;
4847
c3cbbe8a 4848 if (mwl8k_fw_lock(hw))
3a980d0a 4849 return;
a66098da 4850
c3cbbe8a
LB		 4851 /*
4852 * No need to capture a beacon if we're no longer associated.
4853 */
4854 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
4855 priv->capture_beacon = false;
3a980d0a 4856
c3cbbe8a 4857 /*
13935e2c 4858 * Get the AP's legacy and MCS rates.
c3cbbe8a 4859 */
7dc6a7a7 4860 if (vif->bss_conf.assoc) {
c6e96010 4861 struct ieee80211_sta *ap;
c97470dd 4862
c6e96010 4863 rcu_read_lock();
c6e96010 4864
c3cbbe8a
LB		 4865 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
4866 if (ap == NULL) {
4867 rcu_read_unlock();
c6e96010 4868 goto out;
c3cbbe8a
LB		 4869 }
4870
8707d026
LB		 4871 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
4872 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
4873 } else {
4874 ap_legacy_rates =
4875 ap->supp_rates[IEEE80211_BAND_5GHZ] << 5;
4876 }
13935e2c 4877 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB		 4878
4879 rcu_read_unlock();
4880 }
c6e96010 4881
dcee7438
YAP		 4882 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc &&
4883 !priv->ap_fw) {
13935e2c 4884 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB		 4885 if (rc)
4886 goto out;
a66098da 4887
b71ed2c6 4888 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB		 4889 if (rc)
4890 goto out;
dcee7438
YAP		 4891 } else {
4892 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc &&
4893 priv->ap_fw) {
4894 int idx;
4895 int rate;
4896
4897 /* Use AP firmware specific rate command.
4898 */
4899 idx = ffs(vif->bss_conf.basic_rates);
4900 if (idx)
4901 idx--;
4902
4903 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
4904 rate = mwl8k_rates_24[idx].hw_value;
4905 else
4906 rate = mwl8k_rates_50[idx].hw_value;
4907
4908 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
4909 }
c3cbbe8a 4910 }
a66098da 4911
c3cbbe8a 4912 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB		 4913 rc = mwl8k_set_radio_preamble(hw,
4914 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 4915 if (rc)
4916 goto out;
c3cbbe8a 4917 }
a66098da 4918
dcee7438 4919 if ((changed & BSS_CHANGED_ERP_SLOT) && !priv->ap_fw) {
7dc6a7a7 4920 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 4921 if (rc)
4922 goto out;
c3cbbe8a 4923 }
a66098da 4924
dcee7438 4925 if (vif->bss_conf.assoc && !priv->ap_fw &&
c97470dd
LB		 4926 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
4927 BSS_CHANGED_HT))) {
c3cbbe8a 4928 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB		 4929 if (rc)
4930 goto out;
c3cbbe8a 4931 }
a66098da 4932
c3cbbe8a
LB		 4933 if (vif->bss_conf.assoc &&
4934 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB		 4935 /*
4936 * Finalize the join. Tell rx handler to process
4937 * next beacon from our BSSID.
4938 */
0a11dfc3 4939 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 4940 priv->capture_beacon = true;
a66098da
LB		 4941 }
4942
3a980d0a
LB		 4943out:
4944 mwl8k_fw_unlock(hw);
a66098da
LB		 4945}
4946
b64fe619
LB		 4947static void
4948mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4949 struct ieee80211_bss_conf *info, u32 changed)
4950{
4951 int rc;
4952
4953 if (mwl8k_fw_lock(hw))
4954 return;
4955
4956 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4957 rc = mwl8k_set_radio_preamble(hw,
4958 vif->bss_conf.use_short_preamble);
4959 if (rc)
4960 goto out;
4961 }
4962
4963 if (changed & BSS_CHANGED_BASIC_RATES) {
4964 int idx;
4965 int rate;
4966
4967 /*
4968 * Use lowest supported basic rate for multicasts
4969 * and management frames (such as probe responses --
4970 * beacons will always go out at 1 Mb/s).
4971 */
4972 idx = ffs(vif->bss_conf.basic_rates);
8707d026
LB		 4973 if (idx)
4974 idx--;
4975
4976 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
4977 rate = mwl8k_rates_24[idx].hw_value;
4978 else
4979 rate = mwl8k_rates_50[idx].hw_value;
b64fe619
LB		 4980
4981 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
4982 }
4983
4984 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
4985 struct sk_buff *skb;
4986
4987 skb = ieee80211_beacon_get(hw, vif);
4988 if (skb != NULL) {
aa21d0f6 4989 mwl8k_cmd_set_beacon(hw, vif, skb->data, skb->len);
b64fe619
LB		 4990 kfree_skb(skb);
4991 }
4992 }
4993
4994 if (changed & BSS_CHANGED_BEACON_ENABLED)
aa21d0f6 4995 mwl8k_cmd_bss_start(hw, vif, info->enable_beacon);
b64fe619
LB		 4996
4997out:
4998 mwl8k_fw_unlock(hw);
4999}
5000
5001static void
5002mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5003 struct ieee80211_bss_conf *info, u32 changed)
5004{
41bf9119 5005 if (vif->type == NL80211_IFTYPE_STATION)
b64fe619 5006 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
41bf9119 5007 if (vif->type == NL80211_IFTYPE_AP)
b64fe619
LB		 5008 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
5009}
5010
e81cd2d6 5011static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 5012 struct netdev_hw_addr_list *mc_list)
e81cd2d6
LB		 5013{
5014 struct mwl8k_cmd_pkt *cmd;
5015
447ced07
LB		 5016 /*
5017 * Synthesize and return a command packet that programs the
5018 * hardware multicast address filter. At this point we don't
5019 * know whether FIF_ALLMULTI is being requested, but if it is,
5020 * we'll end up throwing this packet away and creating a new
5021 * one in mwl8k_configure_filter().
5022 */
22bedad3 5023 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_list);
e81cd2d6
LB		 5024
5025 return (unsigned long)cmd;
5026}
5027
a43c49a8
LB		 5028static int
5029mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
5030 unsigned int changed_flags,
5031 unsigned int *total_flags)
5032{
5033 struct mwl8k_priv *priv = hw->priv;
5034
5035 /*
5036 * Hardware sniffer mode is mutually exclusive with STA
5037 * operation, so refuse to enable sniffer mode if a STA
5038 * interface is active.
5039 */
f5bb87cf 5040 if (!list_empty(&priv->vif_list)) {
a43c49a8 5041 if (net_ratelimit())
c96c31e4
JP		 5042 wiphy_info(hw->wiphy,
5043 "not enabling sniffer mode because STA interface is active\n");
a43c49a8
LB		 5044 return 0;
5045 }
5046
5047 if (!priv->sniffer_enabled) {
55489b6e 5048 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 5049 return 0;
5050 priv->sniffer_enabled = true;
5051 }
5052
5053 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
5054 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
5055 FIF_OTHER_BSS;
5056
5057 return 1;
5058}
5059
f5bb87cf
LB		 5060static struct mwl8k_vif *mwl8k_first_vif(struct mwl8k_priv *priv)
5061{
5062 if (!list_empty(&priv->vif_list))
5063 return list_entry(priv->vif_list.next, struct mwl8k_vif, list);
5064
5065 return NULL;
5066}
5067
e6935ea1
LB		 5068static void mwl8k_configure_filter(struct ieee80211_hw *hw,
5069 unsigned int changed_flags,
5070 unsigned int *total_flags,
5071 u64 multicast)
5072{
5073 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 5074 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
5075
c0adae2c
LB		 5076 /*
5077 * AP firmware doesn't allow fine-grained control over
5078 * the receive filter.
5079 */
5080 if (priv->ap_fw) {
5081 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
5082 kfree(cmd);
5083 return;
5084 }
5085
a43c49a8
LB		 5086 /*
5087 * Enable hardware sniffer mode if FIF_CONTROL or
5088 * FIF_OTHER_BSS is requested.
5089 */
5090 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
5091 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
5092 kfree(cmd);
5093 return;
5094 }
a66098da 5095
e6935ea1 5096 /* Clear unsupported feature flags */
447ced07 5097 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 5098
90852f7a
LB		 5099 if (mwl8k_fw_lock(hw)) {
5100 kfree(cmd);
e6935ea1 5101 return;
90852f7a 5102 }
a66098da 5103
a43c49a8 5104 if (priv->sniffer_enabled) {
55489b6e 5105 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 5106 priv->sniffer_enabled = false;
5107 }
5108
e6935ea1 5109 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 5110 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
5111 /*
5112 * Disable the BSS filter.
5113 */
e6935ea1 5114 mwl8k_cmd_set_pre_scan(hw);
77165d88 5115 } else {
f5bb87cf 5116 struct mwl8k_vif *mwl8k_vif;
0a11dfc3 5117 const u8 *bssid;
a94cc97e 5118
77165d88
LB		 5119 /*
5120 * Enable the BSS filter.
5121 *
5122 * If there is an active STA interface, use that
5123 * interface's BSSID, otherwise use a dummy one
5124 * (where the OUI part needs to be nonzero for
5125 * the BSSID to be accepted by POST_SCAN).
5126 */
f5bb87cf
LB		 5127 mwl8k_vif = mwl8k_first_vif(priv);
5128 if (mwl8k_vif != NULL)
5129 bssid = mwl8k_vif->vif->bss_conf.bssid;
5130 else
5131 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 5132
e6935ea1 5133 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 5134 }
5135 }
5136
447ced07
LB		 5137 /*
5138 * If FIF_ALLMULTI is being requested, throw away the command
5139 * packet that ->prepare_multicast() built and replace it with
5140 * a command packet that enables reception of all multicast
5141 * packets.
5142 */
5143 if (*total_flags & FIF_ALLMULTI) {
5144 kfree(cmd);
22bedad3 5145 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, NULL);
447ced07
LB		 5146 }
5147
5148 if (cmd != NULL) {
5149 mwl8k_post_cmd(hw, cmd);
5150 kfree(cmd);
e6935ea1 5151 }
a66098da 5152
e6935ea1 5153 mwl8k_fw_unlock(hw);
a66098da
LB		 5154}
5155
a66098da
LB		 5156static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
5157{
c2c2b12a 5158 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB		 5159}
5160
4a6967b8
JB		 5161static int mwl8k_sta_remove(struct ieee80211_hw *hw,
5162 struct ieee80211_vif *vif,
5163 struct ieee80211_sta *sta)
3f5610ff
LB		 5164{
5165 struct mwl8k_priv *priv = hw->priv;
5166
4a6967b8
JB		 5167 if (priv->ap_fw)
5168 return mwl8k_cmd_set_new_stn_del(hw, vif, sta->addr);
5169 else
5170 return mwl8k_cmd_update_stadb_del(hw, vif, sta->addr);
bbfd9128
LB		 5171}
5172
4a6967b8
JB		 5173static int mwl8k_sta_add(struct ieee80211_hw *hw,
5174 struct ieee80211_vif *vif,
5175 struct ieee80211_sta *sta)
bbfd9128
LB		 5176{
5177 struct mwl8k_priv *priv = hw->priv;
4a6967b8 5178 int ret;
fcdc403c
NS		 5179 int i;
5180 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
5181 struct ieee80211_key_conf *key;
bbfd9128 5182
4a6967b8
JB		 5183 if (!priv->ap_fw) {
5184 ret = mwl8k_cmd_update_stadb_add(hw, vif, sta);
5185 if (ret >= 0) {
5186 MWL8K_STA(sta)->peer_id = ret;
17033543
NS		 5187 if (sta->ht_cap.ht_supported)
5188 MWL8K_STA(sta)->is_ampdu_allowed = true;
fcdc403c 5189 ret = 0;
4a6967b8 5190 }
bbfd9128 5191
d9a07d49
NS		 5192 } else {
5193 ret = mwl8k_cmd_set_new_stn_add(hw, vif, sta);
bbfd9128 5194 }
4a6967b8 5195
d9a07d49
NS		 5196 for (i = 0; i < NUM_WEP_KEYS; i++) {
5197 key = IEEE80211_KEY_CONF(mwl8k_vif->wep_key_conf[i].key);
5198 if (mwl8k_vif->wep_key_conf[i].enabled)
5199 mwl8k_set_key(hw, SET_KEY, vif, sta, key);
5200 }
fcdc403c 5201 return ret;
bbfd9128
LB		 5202}
5203
8a3a3c85
EP		 5204static int mwl8k_conf_tx(struct ieee80211_hw *hw,
5205 struct ieee80211_vif *vif, u16 queue,
a66098da
LB		 5206 const struct ieee80211_tx_queue_params *params)
5207{
3e4f542c 5208 struct mwl8k_priv *priv = hw->priv;
a66098da 5209 int rc;
a66098da 5210
3e4f542c
LB		 5211 rc = mwl8k_fw_lock(hw);
5212 if (!rc) {
e600707b 5213 BUG_ON(queue > MWL8K_TX_WMM_QUEUES - 1);
0863ade8
BC		 5214 memcpy(&priv->wmm_params[queue], params, sizeof(*params));
5215
3e4f542c 5216 if (!priv->wmm_enabled)
55489b6e 5217 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 5218
85c9205c 5219 if (!rc) {
e600707b 5220 int q = MWL8K_TX_WMM_QUEUES - 1 - queue;
85c9205c 5221 rc = mwl8k_cmd_set_edca_params(hw, q,
55489b6e
LB		 5222 params->cw_min,
5223 params->cw_max,
5224 params->aifs,
5225 params->txop);
85c9205c 5226 }
3e4f542c
LB		 5227
5228 mwl8k_fw_unlock(hw);
a66098da 5229 }
3e4f542c 5230
a66098da
LB		 5231 return rc;
5232}
5233
a66098da
LB		 5234static int mwl8k_get_stats(struct ieee80211_hw *hw,
5235 struct ieee80211_low_level_stats *stats)
5236{
55489b6e 5237 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 5238}
5239
0d462bbb
JL		 5240static int mwl8k_get_survey(struct ieee80211_hw *hw, int idx,
5241 struct survey_info *survey)
5242{
5243 struct mwl8k_priv *priv = hw->priv;
5244 struct ieee80211_conf *conf = &hw->conf;
5245
5246 if (idx != 0)
5247 return -ENOENT;
5248
5249 survey->channel = conf->channel;
5250 survey->filled = SURVEY_INFO_NOISE_DBM;
5251 survey->noise = priv->noise;
5252
5253 return 0;
5254}
5255
65f3ddcd
NS		 5256#define MAX_AMPDU_ATTEMPTS 5
5257
a2292d83
LB		 5258static int
5259mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5260 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 5261 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
5262 u8 buf_size)
a2292d83 5263{
65f3ddcd
NS		 5264
5265 int i, rc = 0;
5266 struct mwl8k_priv *priv = hw->priv;
5267 struct mwl8k_ampdu_stream *stream;
07f6dda1 5268 u8 *addr = sta->addr, idx;
fd712f5f 5269 struct mwl8k_sta *sta_info = MWL8K_STA(sta);
65f3ddcd
NS		 5270
5271 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
5272 return -ENOTSUPP;
5273
5274 spin_lock(&priv->stream_lock);
5275 stream = mwl8k_lookup_stream(hw, addr, tid);
5276
a2292d83
LB		 5277 switch (action) {
5278 case IEEE80211_AMPDU_RX_START:
5279 case IEEE80211_AMPDU_RX_STOP:
65f3ddcd
NS		 5280 break;
5281 case IEEE80211_AMPDU_TX_START:
5282 /* By the time we get here the hw queues may contain outgoing
5283 * packets for this RA/TID that are not part of this BA
5284 * session. The hw will assign sequence numbers to these
5285 * packets as they go out. So if we query the hw for its next
5286 * sequence number and use that for the SSN here, it may end up
5287 * being wrong, which will lead to sequence number mismatch at
5288 * the recipient. To avoid this, we reset the sequence number
5289 * to O for the first MPDU in this BA stream.
5290 */
5291 *ssn = 0;
5292 if (stream == NULL) {
5293 /* This means that somebody outside this driver called
5294 * ieee80211_start_tx_ba_session. This is unexpected
5295 * because we do our own rate control. Just warn and
5296 * move on.
5297 */
5298 wiphy_warn(hw->wiphy, "Unexpected call to %s. "
5299 "Proceeding anyway.\n", __func__);
5300 stream = mwl8k_add_stream(hw, sta, tid);
5301 }
5302 if (stream == NULL) {
5303 wiphy_debug(hw->wiphy, "no free AMPDU streams\n");
5304 rc = -EBUSY;
5305 break;
5306 }
5307 stream->state = AMPDU_STREAM_IN_PROGRESS;
5308
5309 /* Release the lock before we do the time consuming stuff */
5310 spin_unlock(&priv->stream_lock);
5311 for (i = 0; i < MAX_AMPDU_ATTEMPTS; i++) {
fd712f5f
YAP		 5312
5313 /* Check if link is still valid */
5314 if (!sta_info->is_ampdu_allowed) {
5315 spin_lock(&priv->stream_lock);
5316 mwl8k_remove_stream(hw, stream);
5317 spin_unlock(&priv->stream_lock);
5318 return -EBUSY;
5319 }
5320
f95275c4 5321 rc = mwl8k_check_ba(hw, stream, vif);
65f3ddcd 5322
6b6accc3
YAP		 5323 /* If HW restart is in progress mwl8k_post_cmd will
5324 * return -EBUSY. Avoid retrying mwl8k_check_ba in
5325 * such cases
5326 */
5327 if (!rc || rc == -EBUSY)
65f3ddcd
NS		 5328 break;
5329 /*
5330 * HW queues take time to be flushed, give them
5331 * sufficient time
5332 */
5333
5334 msleep(1000);
5335 }
5336 spin_lock(&priv->stream_lock);
5337 if (rc) {
5338 wiphy_err(hw->wiphy, "Stream for tid %d busy after %d"
5339 " attempts\n", tid, MAX_AMPDU_ATTEMPTS);
5340 mwl8k_remove_stream(hw, stream);
5341 rc = -EBUSY;
5342 break;
5343 }
5344 ieee80211_start_tx_ba_cb_irqsafe(vif, addr, tid);
5345 break;
18b559d5
JB		 5346 case IEEE80211_AMPDU_TX_STOP_CONT:
5347 case IEEE80211_AMPDU_TX_STOP_FLUSH:
5348 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
eca107ff
YAP		 5349 if (stream) {
5350 if (stream->state == AMPDU_STREAM_ACTIVE) {
07f6dda1 5351 idx = stream->idx;
eca107ff 5352 spin_unlock(&priv->stream_lock);
07f6dda1 5353 mwl8k_destroy_ba(hw, idx);
eca107ff
YAP		 5354 spin_lock(&priv->stream_lock);
5355 }
5356 mwl8k_remove_stream(hw, stream);
65f3ddcd 5357 }
65f3ddcd
NS		 5358 ieee80211_stop_tx_ba_cb_irqsafe(vif, addr, tid);
5359 break;
5360 case IEEE80211_AMPDU_TX_OPERATIONAL:
5361 BUG_ON(stream == NULL);
5362 BUG_ON(stream->state != AMPDU_STREAM_IN_PROGRESS);
5363 spin_unlock(&priv->stream_lock);
f95275c4 5364 rc = mwl8k_create_ba(hw, stream, buf_size, vif);
65f3ddcd
NS		 5365 spin_lock(&priv->stream_lock);
5366 if (!rc)
5367 stream->state = AMPDU_STREAM_ACTIVE;
5368 else {
07f6dda1 5369 idx = stream->idx;
65f3ddcd 5370 spin_unlock(&priv->stream_lock);
07f6dda1 5371 mwl8k_destroy_ba(hw, idx);
65f3ddcd
NS		 5372 spin_lock(&priv->stream_lock);
5373 wiphy_debug(hw->wiphy,
5374 "Failed adding stream for sta %pM tid %d\n",
5375 addr, tid);
5376 mwl8k_remove_stream(hw, stream);
5377 }
5378 break;
5379
a2292d83 5380 default:
65f3ddcd 5381 rc = -ENOTSUPP;
a2292d83 5382 }
65f3ddcd
NS		 5383
5384 spin_unlock(&priv->stream_lock);
5385 return rc;
a2292d83
LB		 5386}
5387
a66098da
LB		 5388static const struct ieee80211_ops mwl8k_ops = {
5389 .tx = mwl8k_tx,
5390 .start = mwl8k_start,
5391 .stop = mwl8k_stop,
5392 .add_interface = mwl8k_add_interface,
5393 .remove_interface = mwl8k_remove_interface,
5394 .config = mwl8k_config,
a66098da 5395 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 5396 .prepare_multicast = mwl8k_prepare_multicast,
a66098da 5397 .configure_filter = mwl8k_configure_filter,
fcdc403c 5398 .set_key = mwl8k_set_key,
a66098da 5399 .set_rts_threshold = mwl8k_set_rts_threshold,
4a6967b8
JB		 5400 .sta_add = mwl8k_sta_add,
5401 .sta_remove = mwl8k_sta_remove,
a66098da 5402 .conf_tx = mwl8k_conf_tx,
a66098da 5403 .get_stats = mwl8k_get_stats,
0d462bbb 5404 .get_survey = mwl8k_get_survey,
a2292d83 5405 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB		 5406};
5407
a66098da
LB		 5408static void mwl8k_finalize_join_worker(struct work_struct *work)
5409{
5410 struct mwl8k_priv *priv =
5411 container_of(work, struct mwl8k_priv, finalize_join_worker);
5412 struct sk_buff *skb = priv->beacon_skb;
56007a02
JB		 5413 struct ieee80211_mgmt *mgmt = (void *)skb->data;
5414 int len = skb->len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
5415 const u8 *tim = cfg80211_find_ie(WLAN_EID_TIM,
5416 mgmt->u.beacon.variable, len);
5417 int dtim_period = 1;
5418
5419 if (tim && tim[1] >= 2)
5420 dtim_period = tim[3];
a66098da 5421
56007a02 5422 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, dtim_period);
a66098da 5423
f5bb87cf 5424 dev_kfree_skb(skb);
a66098da
LB		 5425 priv->beacon_skb = NULL;
5426}
5427
bcb628d5 5428enum {
9e1b17ea
LB		 5429 MWL8363 = 0,
5430 MWL8687,
bcb628d5 5431 MWL8366,
6f6d1e9a
LB		 5432};
5433
c2f2e202 5434#define MWL8K_8366_AP_FW_API 3
952a0e96
BC		 5435#define _MWL8K_8366_AP_FW(api) "mwl8k/fmimage_8366_ap-" #api ".fw"
5436#define MWL8K_8366_AP_FW(api) _MWL8K_8366_AP_FW(api)
5437
8dee5eef 5438static struct mwl8k_device_info mwl8k_info_tbl[] = {
9e1b17ea
LB		 5439 [MWL8363] = {
5440 .part_name = "88w8363",
5441 .helper_image = "mwl8k/helper_8363.fw",
0863ade8 5442 .fw_image_sta = "mwl8k/fmimage_8363.fw",
9e1b17ea 5443 },
49eb691c 5444 [MWL8687] = {
bcb628d5
JL		 5445 .part_name = "88w8687",
5446 .helper_image = "mwl8k/helper_8687.fw",
0863ade8 5447 .fw_image_sta = "mwl8k/fmimage_8687.fw",
bcb628d5 5448 },
49eb691c 5449 [MWL8366] = {
bcb628d5
JL		 5450 .part_name = "88w8366",
5451 .helper_image = "mwl8k/helper_8366.fw",
0863ade8 5452 .fw_image_sta = "mwl8k/fmimage_8366.fw",
952a0e96
BC		 5453 .fw_image_ap = MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API),
5454 .fw_api_ap = MWL8K_8366_AP_FW_API,
89a91f4f 5455 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 5456 },
45a390dd
LB		 5457};
5458
c92d4ede
LB		 5459MODULE_FIRMWARE("mwl8k/helper_8363.fw");
5460MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
5461MODULE_FIRMWARE("mwl8k/helper_8687.fw");
5462MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
5463MODULE_FIRMWARE("mwl8k/helper_8366.fw");
5464MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
952a0e96 5465MODULE_FIRMWARE(MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API));
c92d4ede 5466
45a390dd 5467static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
e5868ba1 5468 { PCI_VDEVICE(MARVELL, 0x2a0a), .driver_data = MWL8363, },
9e1b17ea
LB		 5469 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
5470 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL		 5471 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
5472 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
5473 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
fc5bc165
JG		 5474 { PCI_VDEVICE(MARVELL, 0x2a41), .driver_data = MWL8366, },
5475 { PCI_VDEVICE(MARVELL, 0x2a42), .driver_data = MWL8366, },
ca66527c 5476 { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
bcb628d5 5477 { },
45a390dd
LB		 5478};
5479MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
5480
99020471
BC		 5481static int mwl8k_request_alt_fw(struct mwl8k_priv *priv)
5482{
5483 int rc;
5484 printk(KERN_ERR "%s: Error requesting preferred fw %s.\n"
5485 "Trying alternative firmware %s\n", pci_name(priv->pdev),
5486 priv->fw_pref, priv->fw_alt);
5487 rc = mwl8k_request_fw(priv, priv->fw_alt, &priv->fw_ucode, true);
5488 if (rc) {
5489 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5490 pci_name(priv->pdev), priv->fw_alt);
5491 return rc;
5492 }
5493 return 0;
5494}
5495
5496static int mwl8k_firmware_load_success(struct mwl8k_priv *priv);
5497static void mwl8k_fw_state_machine(const struct firmware *fw, void *context)
5498{
5499 struct mwl8k_priv *priv = context;
5500 struct mwl8k_device_info *di = priv->device_info;
5501 int rc;
5502
5503 switch (priv->fw_state) {
5504 case FW_STATE_INIT:
5505 if (!fw) {
5506 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
5507 pci_name(priv->pdev), di->helper_image);
5508 goto fail;
5509 }
5510 priv->fw_helper = fw;
5511 rc = mwl8k_request_fw(priv, priv->fw_pref, &priv->fw_ucode,
5512 true);
5513 if (rc && priv->fw_alt) {
5514 rc = mwl8k_request_alt_fw(priv);
5515 if (rc)
5516 goto fail;
5517 priv->fw_state = FW_STATE_LOADING_ALT;
5518 } else if (rc)
5519 goto fail;
5520 else
5521 priv->fw_state = FW_STATE_LOADING_PREF;
5522 break;
5523
5524 case FW_STATE_LOADING_PREF:
5525 if (!fw) {
5526 if (priv->fw_alt) {
5527 rc = mwl8k_request_alt_fw(priv);
5528 if (rc)
5529 goto fail;
5530 priv->fw_state = FW_STATE_LOADING_ALT;
5531 } else
5532 goto fail;
5533 } else {
5534 priv->fw_ucode = fw;
5535 rc = mwl8k_firmware_load_success(priv);
5536 if (rc)
5537 goto fail;
5538 else
5539 complete(&priv->firmware_loading_complete);
5540 }
5541 break;
5542
5543 case FW_STATE_LOADING_ALT:
5544 if (!fw) {
5545 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5546 pci_name(priv->pdev), di->helper_image);
5547 goto fail;
5548 }
5549 priv->fw_ucode = fw;
5550 rc = mwl8k_firmware_load_success(priv);
5551 if (rc)
5552 goto fail;
5553 else
5554 complete(&priv->firmware_loading_complete);
5555 break;
5556
5557 default:
5558 printk(KERN_ERR "%s: Unexpected firmware loading state: %d\n",
5559 MWL8K_NAME, priv->fw_state);
5560 BUG_ON(1);
5561 }
5562
5563 return;
5564
5565fail:
5566 priv->fw_state = FW_STATE_ERROR;
5567 complete(&priv->firmware_loading_complete);
5568 device_release_driver(&priv->pdev->dev);
5569 mwl8k_release_firmware(priv);
5570}
5571
6b6accc3 5572#define MAX_RESTART_ATTEMPTS 1
99020471
BC		 5573static int mwl8k_init_firmware(struct ieee80211_hw *hw, char *fw_image,
5574 bool nowait)
a66098da 5575{
3cc7772c 5576 struct mwl8k_priv *priv = hw->priv;
a66098da 5577 int rc;
6b6accc3 5578 int count = MAX_RESTART_ATTEMPTS;
be695fc4 5579
6b6accc3 5580retry:
be695fc4
LB		 5581 /* Reset firmware and hardware */
5582 mwl8k_hw_reset(priv);
5583
5584 /* Ask userland hotplug daemon for the device firmware */
99020471 5585 rc = mwl8k_request_firmware(priv, fw_image, nowait);
be695fc4 5586 if (rc) {
5db55844 5587 wiphy_err(hw->wiphy, "Firmware files not found\n");
3cc7772c 5588 return rc;
be695fc4
LB		 5589 }
5590
99020471
BC		 5591 if (nowait)
5592 return rc;
5593
be695fc4
LB		 5594 /* Load firmware into hardware */
5595 rc = mwl8k_load_firmware(hw);
3cc7772c 5596 if (rc)
5db55844 5597 wiphy_err(hw->wiphy, "Cannot start firmware\n");
be695fc4
LB		 5598
5599 /* Reclaim memory once firmware is successfully loaded */
5600 mwl8k_release_firmware(priv);
5601
6b6accc3
YAP		 5602 if (rc && count) {
5603 /* FW did not start successfully;
5604 * lets try one more time
5605 */
5606 count--;
5607 wiphy_err(hw->wiphy, "Trying to reload the firmware again\n");
5608 msleep(20);
5609 goto retry;
5610 }
5611
3cc7772c
BC		 5612 return rc;
5613}
5614
73b46320
BC		 5615static int mwl8k_init_txqs(struct ieee80211_hw *hw)
5616{
5617 struct mwl8k_priv *priv = hw->priv;
5618 int rc = 0;
5619 int i;
5620
e600707b 5621 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
73b46320
BC		 5622 rc = mwl8k_txq_init(hw, i);
5623 if (rc)
5624 break;
5625 if (priv->ap_fw)
5626 iowrite32(priv->txq[i].txd_dma,
5627 priv->sram + priv->txq_offset[i]);
5628 }
5629 return rc;
5630}
5631
3cc7772c
BC		 5632/* initialize hw after successfully loading a firmware image */
5633static int mwl8k_probe_hw(struct ieee80211_hw *hw)
5634{
5635 struct mwl8k_priv *priv = hw->priv;
5636 int rc = 0;
5637 int i;
be695fc4 5638
91942230 5639 if (priv->ap_fw) {
89a91f4f 5640 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230 5641 if (priv->rxd_ops == NULL) {
c96c31e4
JP		 5642 wiphy_err(hw->wiphy,
5643 "Driver does not have AP firmware image support for this hardware\n");
a2ca8ecb 5644 rc = -ENOENT;
91942230
LB		 5645 goto err_stop_firmware;
5646 }
5647 } else {
89a91f4f 5648 priv->rxd_ops = &rxd_sta_ops;
91942230 5649 }
be695fc4
LB		 5650
5651 priv->sniffer_enabled = false;
5652 priv->wmm_enabled = false;
5653 priv->pending_tx_pkts = 0;
c27a54d3 5654 atomic_set(&priv->watchdog_event_pending, 0);
be695fc4 5655
a66098da
LB		 5656 rc = mwl8k_rxq_init(hw, 0);
5657 if (rc)
3cc7772c 5658 goto err_stop_firmware;
a66098da
LB		 5659 rxq_refill(hw, 0, INT_MAX);
5660
73b46320
BC		 5661 /* For the sta firmware, we need to know the dma addresses of tx queues
5662 * before sending MWL8K_CMD_GET_HW_SPEC. So we must initialize them
5663 * prior to issuing this command. But for the AP case, we learn the
5664 * total number of queues from the result CMD_GET_HW_SPEC, so for this
5665 * case we must initialize the tx queues after.
5666 */
8a7a578c 5667 priv->num_ampdu_queues = 0;
73b46320
BC		 5668 if (!priv->ap_fw) {
5669 rc = mwl8k_init_txqs(hw);
a66098da
LB		 5670 if (rc)
5671 goto err_free_queues;
5672 }
5673
5674 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 5675 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3aefc37e
NS		 5676 iowrite32(MWL8K_A2H_INT_TX_DONE|MWL8K_A2H_INT_RX_READY|
5677 MWL8K_A2H_INT_BA_WATCHDOG,
1e9f9de3 5678 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
12488e01
NS		 5679 iowrite32(MWL8K_A2H_INT_OPC_DONE,
5680 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
a66098da 5681
a0607fd3 5682 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 5683 IRQF_SHARED, MWL8K_NAME, hw);
5684 if (rc) {
5db55844 5685 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
a66098da
LB		 5686 goto err_free_queues;
5687 }
5688
6b6accc3
YAP		 5689 /*
5690 * When hw restart is requested,
5691 * mac80211 will take care of clearing
5692 * the ampdu streams, so do not clear
5693 * the ampdu state here
5694 */
5695 if (!priv->hw_restart_in_progress)
5696 memset(priv->ampdu, 0, sizeof(priv->ampdu));
ac109fd0 5697
a66098da
LB		 5698 /*
5699 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 5700 * commands use interrupts and avoid polling. Disable
a66098da
LB		 5701 * interrupts when done.
5702 */
c23b5a69 5703 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5704
5705 /* Get config data, mac addrs etc */
42fba21d
LB		 5706 if (priv->ap_fw) {
5707 rc = mwl8k_cmd_get_hw_spec_ap(hw);
73b46320
BC		 5708 if (!rc)
5709 rc = mwl8k_init_txqs(hw);
42fba21d
LB		 5710 if (!rc)
5711 rc = mwl8k_cmd_set_hw_spec(hw);
5712 } else {
5713 rc = mwl8k_cmd_get_hw_spec_sta(hw);
5714 }
a66098da 5715 if (rc) {
5db55844 5716 wiphy_err(hw->wiphy, "Cannot initialise firmware\n");
be695fc4 5717 goto err_free_irq;
a66098da
LB		 5718 }
5719
5720 /* Turn radio off */
55489b6e 5721 rc = mwl8k_cmd_radio_disable(hw);
a66098da 5722 if (rc) {
5db55844 5723 wiphy_err(hw->wiphy, "Cannot disable\n");
be695fc4 5724 goto err_free_irq;
a66098da
LB		 5725 }
5726
32060e1b 5727 /* Clear MAC address */
aa21d0f6 5728 rc = mwl8k_cmd_set_mac_addr(hw, NULL, "\x00\x00\x00\x00\x00\x00");
32060e1b 5729 if (rc) {
5db55844 5730 wiphy_err(hw->wiphy, "Cannot clear MAC address\n");
be695fc4 5731 goto err_free_irq;
32060e1b
LB		 5732 }
5733
a246ac38
YAP		 5734 /* Configure Antennas */
5735 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x3);
5736 if (rc)
5737 wiphy_warn(hw->wiphy, "failed to set # of RX antennas");
5738 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
5739 if (rc)
5740 wiphy_warn(hw->wiphy, "failed to set # of TX antennas");
5741
5742
a66098da 5743 /* Disable interrupts */
a66098da 5744 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5745 free_irq(priv->pdev->irq, hw);
5746
c96c31e4
JP		 5747 wiphy_info(hw->wiphy, "%s v%d, %pm, %s firmware %u.%u.%u.%u\n",
5748 priv->device_info->part_name,
5749 priv->hw_rev, hw->wiphy->perm_addr,
5750 priv->ap_fw ? "AP" : "STA",
5751 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
5752 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 5753
5754 return 0;
5755
a66098da 5756err_free_irq:
a66098da 5757 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5758 free_irq(priv->pdev->irq, hw);
5759
5760err_free_queues:
e600707b 5761 for (i = 0; i < mwl8k_tx_queues(priv); i++)
a66098da
LB		 5762 mwl8k_txq_deinit(hw, i);
5763 mwl8k_rxq_deinit(hw, 0);
5764
3cc7772c
BC		 5765err_stop_firmware:
5766 mwl8k_hw_reset(priv);
5767
5768 return rc;
5769}
5770
5771/*
5772 * invoke mwl8k_reload_firmware to change the firmware image after the device
5773 * has already been registered
5774 */
5775static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image)
5776{
5777 int i, rc = 0;
5778 struct mwl8k_priv *priv = hw->priv;
6b6accc3 5779 struct mwl8k_vif *vif, *tmp_vif;
3cc7772c
BC		 5780
5781 mwl8k_stop(hw);
5782 mwl8k_rxq_deinit(hw, 0);
5783
6b6accc3
YAP		 5784 /*
5785 * All the existing interfaces are re-added by the ieee80211_reconfig;
5786 * which means driver should remove existing interfaces before calling
5787 * ieee80211_restart_hw
5788 */
5789 if (priv->hw_restart_in_progress)
5790 list_for_each_entry_safe(vif, tmp_vif, &priv->vif_list, list)
5791 mwl8k_remove_vif(priv, vif);
5792
e600707b 5793 for (i = 0; i < mwl8k_tx_queues(priv); i++)
3cc7772c
BC		 5794 mwl8k_txq_deinit(hw, i);
5795
99020471 5796 rc = mwl8k_init_firmware(hw, fw_image, false);
3cc7772c
BC		 5797 if (rc)
5798 goto fail;
5799
5800 rc = mwl8k_probe_hw(hw);
5801 if (rc)
5802 goto fail;
5803
6b6accc3
YAP		 5804 if (priv->hw_restart_in_progress)
5805 return rc;
5806
3cc7772c
BC		 5807 rc = mwl8k_start(hw);
5808 if (rc)
5809 goto fail;
5810
5811 rc = mwl8k_config(hw, ~0);
5812 if (rc)
5813 goto fail;
5814
e600707b 5815 for (i = 0; i < MWL8K_TX_WMM_QUEUES; i++) {
8a3a3c85 5816 rc = mwl8k_conf_tx(hw, NULL, i, &priv->wmm_params[i]);
3cc7772c
BC		 5817 if (rc)
5818 goto fail;
5819 }
5820
5821 return rc;
5822
5823fail:
5824 printk(KERN_WARNING "mwl8k: Failed to reload firmware image.\n");
5825 return rc;
5826}
5827
5d377fca
YAP		 5828static const struct ieee80211_iface_limit ap_if_limits[] = {
5829 { .max = 8, .types = BIT(NL80211_IFTYPE_AP) },
2acdaa7a 5830 { .max = 1, .types = BIT(NL80211_IFTYPE_STATION) },
5d377fca
YAP		 5831};
5832
5833static const struct ieee80211_iface_combination ap_if_comb = {
5834 .limits = ap_if_limits,
5835 .n_limits = ARRAY_SIZE(ap_if_limits),
5836 .max_interfaces = 8,
5837 .num_different_channels = 1,
5838};
5839
5840
3cc7772c
BC		 5841static int mwl8k_firmware_load_success(struct mwl8k_priv *priv)
5842{
5843 struct ieee80211_hw *hw = priv->hw;
5844 int i, rc;
5845
99020471
BC		 5846 rc = mwl8k_load_firmware(hw);
5847 mwl8k_release_firmware(priv);
5848 if (rc) {
5849 wiphy_err(hw->wiphy, "Cannot start firmware\n");
5850 return rc;
5851 }
5852
3cc7772c
BC		 5853 /*
5854 * Extra headroom is the size of the required DMA header
5855 * minus the size of the smallest 802.11 frame (CTS frame).
5856 */
5857 hw->extra_tx_headroom =
5858 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
5859
ff776cec
YAP		 5860 hw->extra_tx_headroom -= priv->ap_fw ? REDUCED_TX_HEADROOM : 0;
5861
3cc7772c
BC		 5862 hw->channel_change_time = 10;
5863
e600707b 5864 hw->queues = MWL8K_TX_WMM_QUEUES;
3cc7772c
BC		 5865
5866 /* Set rssi values to dBm */
0bf22c37 5867 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_HAS_RATE_CONTROL;
2a36a0ec
YAP		 5868
5869 /*
5870 * Ask mac80211 to not to trigger PS mode
5871 * based on PM bit of incoming frames.
5872 */
5873 if (priv->ap_fw)
5874 hw->flags |= IEEE80211_HW_AP_LINK_PS;
5875
3cc7772c
BC		 5876 hw->vif_data_size = sizeof(struct mwl8k_vif);
5877 hw->sta_data_size = sizeof(struct mwl8k_sta);
5878
5879 priv->macids_used = 0;
5880 INIT_LIST_HEAD(&priv->vif_list);
5881
5882 /* Set default radio state and preamble */
3db1cd5c
RR		 5883 priv->radio_on = false;
5884 priv->radio_short_preamble = false;
3cc7772c
BC		 5885
5886 /* Finalize join worker */
5887 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3aefc37e
NS		 5888 /* Handle watchdog ba events */
5889 INIT_WORK(&priv->watchdog_ba_handle, mwl8k_watchdog_ba_events);
6b6accc3
YAP		 5890 /* To reload the firmware if it crashes */
5891 INIT_WORK(&priv->fw_reload, mwl8k_hw_restart_work);
3cc7772c
BC		 5892
5893 /* TX reclaim and RX tasklets. */
5894 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
5895 tasklet_disable(&priv->poll_tx_task);
5896 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
5897 tasklet_disable(&priv->poll_rx_task);
5898
5899 /* Power management cookie */
5900 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
5901 if (priv->cookie == NULL)
5902 return -ENOMEM;
5903
5904 mutex_init(&priv->fw_mutex);
5905 priv->fw_mutex_owner = NULL;
5906 priv->fw_mutex_depth = 0;
5907 priv->hostcmd_wait = NULL;
5908
5909 spin_lock_init(&priv->tx_lock);
5910
ac109fd0
BC		 5911 spin_lock_init(&priv->stream_lock);
5912
3cc7772c
BC		 5913 priv->tx_wait = NULL;
5914
5915 rc = mwl8k_probe_hw(hw);
5916 if (rc)
5917 goto err_free_cookie;
5918
5919 hw->wiphy->interface_modes = 0;
5d377fca
YAP		 5920
5921 if (priv->ap_macids_supported || priv->device_info->fw_image_ap) {
3cc7772c 5922 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
2acdaa7a 5923 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
5d377fca
YAP		 5924 hw->wiphy->iface_combinations = &ap_if_comb;
5925 hw->wiphy->n_iface_combinations = 1;
5926 }
5927
3cc7772c
BC		 5928 if (priv->sta_macids_supported || priv->device_info->fw_image_sta)
5929 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
5930
5931 rc = ieee80211_register_hw(hw);
5932 if (rc) {
5933 wiphy_err(hw->wiphy, "Cannot register device\n");
5934 goto err_unprobe_hw;
5935 }
5936
5937 return 0;
5938
5939err_unprobe_hw:
e600707b 5940 for (i = 0; i < mwl8k_tx_queues(priv); i++)
3cc7772c
BC		 5941 mwl8k_txq_deinit(hw, i);
5942 mwl8k_rxq_deinit(hw, 0);
5943
be695fc4 5944err_free_cookie:
a66098da
LB		 5945 if (priv->cookie != NULL)
5946 pci_free_consistent(priv->pdev, 4,
5947 priv->cookie, priv->cookie_dma);
5948
3cc7772c
BC		 5949 return rc;
5950}
8dee5eef 5951static int mwl8k_probe(struct pci_dev *pdev,
3cc7772c
BC		 5952 const struct pci_device_id *id)
5953{
5954 static int printed_version;
5955 struct ieee80211_hw *hw;
5956 struct mwl8k_priv *priv;
0863ade8 5957 struct mwl8k_device_info *di;
3cc7772c
BC		 5958 int rc;
5959
5960 if (!printed_version) {
5961 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
5962 printed_version = 1;
5963 }
5964
5965
5966 rc = pci_enable_device(pdev);
5967 if (rc) {
5968 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
5969 MWL8K_NAME);
5970 return rc;
5971 }
5972
5973 rc = pci_request_regions(pdev, MWL8K_NAME);
5974 if (rc) {
5975 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
5976 MWL8K_NAME);
5977 goto err_disable_device;
5978 }
5979
5980 pci_set_master(pdev);
5981
5982
5983 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
5984 if (hw == NULL) {
5985 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
5986 rc = -ENOMEM;
5987 goto err_free_reg;
5988 }
5989
5990 SET_IEEE80211_DEV(hw, &pdev->dev);
5991 pci_set_drvdata(pdev, hw);
5992
5993 priv = hw->priv;
5994 priv->hw = hw;
5995 priv->pdev = pdev;
5996 priv->device_info = &mwl8k_info_tbl[id->driver_data];
5997
5998
5999 priv->sram = pci_iomap(pdev, 0, 0x10000);
6000 if (priv->sram == NULL) {
6001 wiphy_err(hw->wiphy, "Cannot map device SRAM\n");
a2ca8ecb 6002 rc = -EIO;
3cc7772c
BC		 6003 goto err_iounmap;
6004 }
6005
6006 /*
6007 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
6008 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
6009 */
6010 priv->regs = pci_iomap(pdev, 1, 0x10000);
6011 if (priv->regs == NULL) {
6012 priv->regs = pci_iomap(pdev, 2, 0x10000);
6013 if (priv->regs == NULL) {
6014 wiphy_err(hw->wiphy, "Cannot map device registers\n");
a2ca8ecb 6015 rc = -EIO;
3cc7772c
BC		 6016 goto err_iounmap;
6017 }
6018 }
6019
0863ade8 6020 /*
99020471
BC		 6021 * Choose the initial fw image depending on user input. If a second
6022 * image is available, make it the alternative image that will be
6023 * loaded if the first one fails.
0863ade8 6024 */
99020471 6025 init_completion(&priv->firmware_loading_complete);
0863ade8 6026 di = priv->device_info;
99020471
BC		 6027 if (ap_mode_default && di->fw_image_ap) {
6028 priv->fw_pref = di->fw_image_ap;
6029 priv->fw_alt = di->fw_image_sta;
6030 } else if (!ap_mode_default && di->fw_image_sta) {
6031 priv->fw_pref = di->fw_image_sta;
6032 priv->fw_alt = di->fw_image_ap;
6033 } else if (ap_mode_default && !di->fw_image_ap && di->fw_image_sta) {
0863ade8 6034 printk(KERN_WARNING "AP fw is unavailable. Using STA fw.");
99020471 6035 priv->fw_pref = di->fw_image_sta;
0863ade8
BC		 6036 } else if (!ap_mode_default && !di->fw_image_sta && di->fw_image_ap) {
6037 printk(KERN_WARNING "STA fw is unavailable. Using AP fw.");
99020471
BC		 6038 priv->fw_pref = di->fw_image_ap;
6039 }
6040 rc = mwl8k_init_firmware(hw, priv->fw_pref, true);
3cc7772c
BC		 6041 if (rc)
6042 goto err_stop_firmware;
6b6accc3
YAP		 6043
6044 priv->hw_restart_in_progress = false;
6045
e882efc9
YAP		 6046 priv->running_bsses = 0;
6047
99020471 6048 return rc;
3cc7772c 6049
be695fc4
LB		 6050err_stop_firmware:
6051 mwl8k_hw_reset(priv);
be695fc4
LB		 6052
6053err_iounmap:
a66098da
LB		 6054 if (priv->regs != NULL)
6055 pci_iounmap(pdev, priv->regs);
6056
5b9482dd
LB		 6057 if (priv->sram != NULL)
6058 pci_iounmap(pdev, priv->sram);
6059
a66098da
LB		 6060 pci_set_drvdata(pdev, NULL);
6061 ieee80211_free_hw(hw);
6062
6063err_free_reg:
6064 pci_release_regions(pdev);
3db95e50
LB		 6065
6066err_disable_device:
a66098da
LB		 6067 pci_disable_device(pdev);
6068
6069 return rc;
6070}
6071
8dee5eef 6072static void mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 6073{
6074 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
6075 struct mwl8k_priv *priv;
6076 int i;
6077
6078 if (hw == NULL)
6079 return;
6080 priv = hw->priv;
6081
99020471
BC		 6082 wait_for_completion(&priv->firmware_loading_complete);
6083
6084 if (priv->fw_state == FW_STATE_ERROR) {
6085 mwl8k_hw_reset(priv);
6086 goto unmap;
6087 }
6088
a66098da
LB		 6089 ieee80211_stop_queues(hw);
6090
60aa569f
LB		 6091 ieee80211_unregister_hw(hw);
6092
67e2eb27 6093 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 6094 tasklet_kill(&priv->poll_tx_task);
67e2eb27 6095 tasklet_kill(&priv->poll_rx_task);
a66098da 6096
a66098da
LB		 6097 /* Stop hardware */
6098 mwl8k_hw_reset(priv);
6099
6100 /* Return all skbs to mac80211 */
e600707b 6101 for (i = 0; i < mwl8k_tx_queues(priv); i++)
efb7c49a 6102 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 6103
e600707b 6104 for (i = 0; i < mwl8k_tx_queues(priv); i++)
a66098da
LB		 6105 mwl8k_txq_deinit(hw, i);
6106
6107 mwl8k_rxq_deinit(hw, 0);
6108
c2c357ce 6109 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da 6110
99020471 6111unmap:
a66098da 6112 pci_iounmap(pdev, priv->regs);
5b9482dd 6113 pci_iounmap(pdev, priv->sram);
a66098da
LB		 6114 pci_set_drvdata(pdev, NULL);
6115 ieee80211_free_hw(hw);
6116 pci_release_regions(pdev);
6117 pci_disable_device(pdev);
6118}
6119
6120static struct pci_driver mwl8k_driver = {
6121 .name = MWL8K_NAME,
45a390dd 6122 .id_table = mwl8k_pci_id_table,
a66098da 6123 .probe = mwl8k_probe,
8dee5eef 6124 .remove = mwl8k_remove,
a66098da
LB		 6125};
6126
5b0a3b7e 6127module_pci_driver(mwl8k_driver);
c2c357ce
LB		 6128
6129MODULE_DESCRIPTION(MWL8K_DESC);
6130MODULE_VERSION(MWL8K_VERSION);
6131MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
6132MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.851722 seconds and 5 git commands to generate.