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mwl8k: simplify sequence number assignment
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
6976b665 29#define MWL8K_VERSION "0.11"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d
LB		 87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
54bc3a0d
LB		 89};
90
45a390dd 91struct mwl8k_device_info {
a74b295e
LB		 92 char *part_name;
93 char *helper_image;
94 char *fw_image;
89a91f4f 95 struct rxd_ops *ap_rxd_ops;
45a390dd
LB		 96};
97
a66098da 98struct mwl8k_rx_queue {
45eb400d 99 int rxd_count;
a66098da
LB		 100
101 /* hw receives here */
45eb400d 102 int head;
a66098da
LB		 103
104 /* refill descs here */
45eb400d 105 int tail;
a66098da 106
54bc3a0d 107 void *rxd;
45eb400d 108 dma_addr_t rxd_dma;
788838eb
LB		 109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
a66098da
LB		 113};
114
a66098da
LB		 115struct mwl8k_tx_queue {
116 /* hw transmits here */
45eb400d 117 int head;
a66098da
LB		 118
119 /* sw appends here */
45eb400d 120 int tail;
a66098da 121
45eb400d
LB		 122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
124 dma_addr_t txd_dma;
125 struct sk_buff **skb;
a66098da
LB		 126};
127
a66098da 128struct mwl8k_priv {
a66098da 129 struct ieee80211_hw *hw;
a66098da 130 struct pci_dev *pdev;
a66098da 131
45a390dd
LB		 132 struct mwl8k_device_info *device_info;
133
be695fc4
LB		 134 void __iomem *sram;
135 void __iomem *regs;
136
137 /* firmware */
22be40d9
LB		 138 struct firmware *fw_helper;
139 struct firmware *fw_ucode;
a66098da 140
be695fc4
LB		 141 /* hardware/firmware parameters */
142 bool ap_fw;
143 struct rxd_ops *rxd_ops;
144
618952a7
LB		 145 /* firmware access */
146 struct mutex fw_mutex;
147 struct task_struct *fw_mutex_owner;
148 int fw_mutex_depth;
618952a7
LB		 149 struct completion *hostcmd_wait;
150
a66098da
LB		 151 /* lock held over TX and TX reap */
152 spinlock_t tx_lock;
a66098da 153
88de754a
LB		 154 /* TX quiesce completion, protected by fw_mutex and tx_lock */
155 struct completion *tx_wait;
156
a66098da 157 struct ieee80211_vif *vif;
a66098da 158
a66098da
LB		 159 /* power management status cookie from firmware */
160 u32 *cookie;
161 dma_addr_t cookie_dma;
162
163 u16 num_mcaddrs;
a66098da 164 u8 hw_rev;
2aa7b01f 165 u32 fw_rev;
a66098da
LB		 166
167 /*
168 * Running count of TX packets in flight, to avoid
169 * iterating over the transmit rings each time.
170 */
171 int pending_tx_pkts;
172
173 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
174 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
175
176 /* PHY parameters */
177 struct ieee80211_supported_band band;
178 struct ieee80211_channel channels[14];
140eb5e2 179 struct ieee80211_rate rates[14];
a66098da 180
c46563b7 181 bool radio_on;
68ce3884 182 bool radio_short_preamble;
a43c49a8 183 bool sniffer_enabled;
0439b1f5 184 bool wmm_enabled;
a66098da 185
bbfd9128
LB		 186 struct work_struct sta_notify_worker;
187 spinlock_t sta_notify_list_lock;
188 struct list_head sta_notify_list;
189
a66098da
LB		 190 /* XXX need to convert this to handle multiple interfaces */
191 bool capture_beacon;
d89173f2 192 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 193 struct sk_buff *beacon_skb;
194
195 /*
196 * This FJ worker has to be global as it is scheduled from the
197 * RX handler. At this point we don't know which interface it
198 * belongs to until the list of bssids waiting to complete join
199 * is checked.
200 */
201 struct work_struct finalize_join_worker;
202
1e9f9de3
LB		 203 /* Tasklet to perform TX reclaim. */
204 struct tasklet_struct poll_tx_task;
67e2eb27
LB		 205
206 /* Tasklet to perform RX. */
207 struct tasklet_struct poll_rx_task;
a66098da
LB		 208};
209
210/* Per interface specific private data */
211struct mwl8k_vif {
c2c2b12a 212 /* Non AMPDU sequence number assigned by driver. */
a680400e 213 u16 seqno;
a66098da 214};
a94cc97e 215#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da 216
a680400e
LB		 217struct mwl8k_sta {
218 /* Index into station database. Returned by UPDATE_STADB. */
219 u8 peer_id;
220};
221#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
222
a66098da
LB		 223static const struct ieee80211_channel mwl8k_channels[] = {
224 { .center_freq = 2412, .hw_value = 1, },
225 { .center_freq = 2417, .hw_value = 2, },
226 { .center_freq = 2422, .hw_value = 3, },
227 { .center_freq = 2427, .hw_value = 4, },
228 { .center_freq = 2432, .hw_value = 5, },
229 { .center_freq = 2437, .hw_value = 6, },
230 { .center_freq = 2442, .hw_value = 7, },
231 { .center_freq = 2447, .hw_value = 8, },
232 { .center_freq = 2452, .hw_value = 9, },
233 { .center_freq = 2457, .hw_value = 10, },
234 { .center_freq = 2462, .hw_value = 11, },
647ca6b0
LB		 235 { .center_freq = 2467, .hw_value = 12, },
236 { .center_freq = 2472, .hw_value = 13, },
237 { .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 238};
239
240static const struct ieee80211_rate mwl8k_rates[] = {
241 { .bitrate = 10, .hw_value = 2, },
242 { .bitrate = 20, .hw_value = 4, },
243 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 244 { .bitrate = 110, .hw_value = 22, },
245 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 246 { .bitrate = 60, .hw_value = 12, },
247 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 248 { .bitrate = 120, .hw_value = 24, },
249 { .bitrate = 180, .hw_value = 36, },
250 { .bitrate = 240, .hw_value = 48, },
251 { .bitrate = 360, .hw_value = 72, },
252 { .bitrate = 480, .hw_value = 96, },
253 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 254 { .bitrate = 720, .hw_value = 144, },
255};
256
a66098da
LB		 257/* Set or get info from Firmware */
258#define MWL8K_CMD_SET 0x0001
259#define MWL8K_CMD_GET 0x0000
260
261/* Firmware command codes */
262#define MWL8K_CMD_CODE_DNLD 0x0001
263#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 264#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 265#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
266#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 267#define MWL8K_CMD_RADIO_CONTROL 0x001c
268#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 269#define MWL8K_CMD_RF_ANTENNA 0x0020
b64fe619 270#define MWL8K_CMD_SET_BEACON 0x0100
a66098da
LB		 271#define MWL8K_CMD_SET_PRE_SCAN 0x0107
272#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 273#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
274#define MWL8K_CMD_SET_AID 0x010d
275#define MWL8K_CMD_SET_RATE 0x0110
276#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
277#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 278#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 279#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
280#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 281#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 282#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 283#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 284#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 285#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
b64fe619 286#define MWL8K_CMD_BSS_START 0x1100
3f5610ff 287#define MWL8K_CMD_SET_NEW_STN 0x1111
ff45fc60 288#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 289
290static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
291{
292#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
293 snprintf(buf, bufsize, "%s", #x);\
294 return buf;\
295 } while (0)
ce9e2e1b 296 switch (cmd & ~0x8000) {
a66098da
LB		 297 MWL8K_CMDNAME(CODE_DNLD);
298 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 299 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 300 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
301 MWL8K_CMDNAME(GET_STAT);
302 MWL8K_CMDNAME(RADIO_CONTROL);
303 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 304 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 305 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB		 306 MWL8K_CMDNAME(SET_PRE_SCAN);
307 MWL8K_CMDNAME(SET_POST_SCAN);
308 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 309 MWL8K_CMDNAME(SET_AID);
310 MWL8K_CMDNAME(SET_RATE);
311 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
312 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 313 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 314 MWL8K_CMDNAME(SET_EDCA_PARAMS);
315 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 316 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 317 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 318 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 319 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 320 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 321 MWL8K_CMDNAME(BSS_START);
3f5610ff 322 MWL8K_CMDNAME(SET_NEW_STN);
ff45fc60 323 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 324 default:
325 snprintf(buf, bufsize, "0x%x", cmd);
326 }
327#undef MWL8K_CMDNAME
328
329 return buf;
330}
331
332/* Hardware and firmware reset */
333static void mwl8k_hw_reset(struct mwl8k_priv *priv)
334{
335 iowrite32(MWL8K_H2A_INT_RESET,
336 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
337 iowrite32(MWL8K_H2A_INT_RESET,
338 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
339 msleep(20);
340}
341
342/* Release fw image */
343static void mwl8k_release_fw(struct firmware **fw)
344{
345 if (*fw == NULL)
346 return;
347 release_firmware(*fw);
348 *fw = NULL;
349}
350
351static void mwl8k_release_firmware(struct mwl8k_priv *priv)
352{
22be40d9
LB		 353 mwl8k_release_fw(&priv->fw_ucode);
354 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 355}
356
357/* Request fw image */
358static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 359 const char *fname, struct firmware **fw)
a66098da
LB		 360{
361 /* release current image */
362 if (*fw != NULL)
363 mwl8k_release_fw(fw);
364
365 return request_firmware((const struct firmware **)fw,
c2c357ce 366 fname, &priv->pdev->dev);
a66098da
LB		 367}
368
45a390dd 369static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 370{
a74b295e 371 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 372 int rc;
373
a74b295e 374 if (di->helper_image != NULL) {
22be40d9 375 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
a74b295e
LB		 376 if (rc) {
377 printk(KERN_ERR "%s: Error requesting helper "
378 "firmware file %s\n", pci_name(priv->pdev),
379 di->helper_image);
380 return rc;
381 }
a66098da
LB		 382 }
383
22be40d9 384 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
a66098da 385 if (rc) {
c2c357ce 386 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 387 pci_name(priv->pdev), di->fw_image);
22be40d9 388 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 389 return rc;
390 }
391
392 return 0;
393}
394
395struct mwl8k_cmd_pkt {
396 __le16 code;
397 __le16 length;
398 __le16 seq_num;
399 __le16 result;
400 char payload[0];
401} __attribute__((packed));
402
403/*
404 * Firmware loading.
405 */
406static int
407mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
408{
409 void __iomem *regs = priv->regs;
410 dma_addr_t dma_addr;
a66098da
LB		 411 int loops;
412
413 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
414 if (pci_dma_mapping_error(priv->pdev, dma_addr))
415 return -ENOMEM;
416
417 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
418 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
419 iowrite32(MWL8K_H2A_INT_DOORBELL,
420 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
421 iowrite32(MWL8K_H2A_INT_DUMMY,
422 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
423
a66098da
LB		 424 loops = 1000;
425 do {
426 u32 int_code;
427
428 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
429 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
430 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 431 break;
432 }
433
3d76e82c 434 cond_resched();
a66098da
LB		 435 udelay(1);
436 } while (--loops);
437
438 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
439
d4b70570 440 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 441}
442
443static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
444 const u8 *data, size_t length)
445{
446 struct mwl8k_cmd_pkt *cmd;
447 int done;
448 int rc = 0;
449
450 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
451 if (cmd == NULL)
452 return -ENOMEM;
453
454 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
455 cmd->seq_num = 0;
456 cmd->result = 0;
457
458 done = 0;
459 while (length) {
460 int block_size = length > 256 ? 256 : length;
461
462 memcpy(cmd->payload, data + done, block_size);
463 cmd->length = cpu_to_le16(block_size);
464
465 rc = mwl8k_send_fw_load_cmd(priv, cmd,
466 sizeof(*cmd) + block_size);
467 if (rc)
468 break;
469
470 done += block_size;
471 length -= block_size;
472 }
473
474 if (!rc) {
475 cmd->length = 0;
476 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
477 }
478
479 kfree(cmd);
480
481 return rc;
482}
483
484static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
485 const u8 *data, size_t length)
486{
487 unsigned char *buffer;
488 int may_continue, rc = 0;
489 u32 done, prev_block_size;
490
491 buffer = kmalloc(1024, GFP_KERNEL);
492 if (buffer == NULL)
493 return -ENOMEM;
494
495 done = 0;
496 prev_block_size = 0;
497 may_continue = 1000;
498 while (may_continue > 0) {
499 u32 block_size;
500
501 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
502 if (block_size & 1) {
503 block_size &= ~1;
504 may_continue--;
505 } else {
506 done += prev_block_size;
507 length -= prev_block_size;
508 }
509
510 if (block_size > 1024 || block_size > length) {
511 rc = -EOVERFLOW;
512 break;
513 }
514
515 if (length == 0) {
516 rc = 0;
517 break;
518 }
519
520 if (block_size == 0) {
521 rc = -EPROTO;
522 may_continue--;
523 udelay(1);
524 continue;
525 }
526
527 prev_block_size = block_size;
528 memcpy(buffer, data + done, block_size);
529
530 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
531 if (rc)
532 break;
533 }
534
535 if (!rc && length != 0)
536 rc = -EREMOTEIO;
537
538 kfree(buffer);
539
540 return rc;
541}
542
c2c357ce 543static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 544{
c2c357ce 545 struct mwl8k_priv *priv = hw->priv;
22be40d9 546 struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 547 int rc;
548 int loops;
549
550 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
22be40d9 551 struct firmware *helper = priv->fw_helper;
a66098da 552
c2c357ce
LB		 553 if (helper == NULL) {
554 printk(KERN_ERR "%s: helper image needed but none "
555 "given\n", pci_name(priv->pdev));
556 return -EINVAL;
557 }
a66098da 558
c2c357ce 559 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 560 if (rc) {
561 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 562 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 563 return rc;
564 }
89b872e2 565 msleep(5);
a66098da 566
c2c357ce 567 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 568 } else {
c2c357ce 569 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 570 }
571
572 if (rc) {
c2c357ce
LB		 573 printk(KERN_ERR "%s: unable to load firmware image\n",
574 pci_name(priv->pdev));
a66098da
LB		 575 return rc;
576 }
577
89a91f4f 578 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 579
89b872e2 580 loops = 500000;
a66098da 581 do {
eae74e65
LB		 582 u32 ready_code;
583
584 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
585 if (ready_code == MWL8K_FWAP_READY) {
586 priv->ap_fw = 1;
587 break;
588 } else if (ready_code == MWL8K_FWSTA_READY) {
589 priv->ap_fw = 0;
a66098da 590 break;
eae74e65
LB		 591 }
592
593 cond_resched();
a66098da
LB		 594 udelay(1);
595 } while (--loops);
596
597 return loops ? 0 : -ETIMEDOUT;
598}
599
600
a66098da
LB		 601/* DMA header used by firmware and hardware. */
602struct mwl8k_dma_data {
603 __le16 fwlen;
604 struct ieee80211_hdr wh;
20f09c3d 605 char data[0];
a66098da
LB		 606} __attribute__((packed));
607
608/* Routines to add/remove DMA header from skb. */
20f09c3d 609static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 610{
20f09c3d
LB		 611 struct mwl8k_dma_data *tr;
612 int hdrlen;
613
614 tr = (struct mwl8k_dma_data *)skb->data;
615 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
616
617 if (hdrlen != sizeof(tr->wh)) {
618 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
619 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
620 *((__le16 *)(tr->data - 2)) = qos;
621 } else {
622 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
623 }
a66098da 624 }
20f09c3d
LB		 625
626 if (hdrlen != sizeof(*tr))
627 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 628}
629
76266b2a 630static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 631{
632 struct ieee80211_hdr *wh;
ca009301 633 int hdrlen;
a66098da
LB		 634 struct mwl8k_dma_data *tr;
635
ca009301
LB		 636 /*
637 * Add a firmware DMA header; the firmware requires that we
638 * present a 2-byte payload length followed by a 4-address
639 * header (without QoS field), followed (optionally) by any
640 * WEP/ExtIV header (but only filled in for CCMP).
641 */
a66098da 642 wh = (struct ieee80211_hdr *)skb->data;
ca009301 643
a66098da 644 hdrlen = ieee80211_hdrlen(wh->frame_control);
ca009301
LB		 645 if (hdrlen != sizeof(*tr))
646 skb_push(skb, sizeof(*tr) - hdrlen);
a66098da 647
ca009301
LB		 648 if (ieee80211_is_data_qos(wh->frame_control))
649 hdrlen -= 2;
a66098da
LB		 650
651 tr = (struct mwl8k_dma_data *)skb->data;
652 if (wh != &tr->wh)
653 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 654 if (hdrlen != sizeof(tr->wh))
655 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 656
657 /*
658 * Firmware length is the length of the fully formed "802.11
659 * payload". That is, everything except for the 802.11 header.
660 * This includes all crypto material including the MIC.
661 */
ca009301 662 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
a66098da
LB		 663}
664
665
666/*
89a91f4f 667 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 668 */
89a91f4f 669struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB		 670 __le16 pkt_len;
671 __u8 sq2;
672 __u8 rate;
673 __le32 pkt_phys_addr;
674 __le32 next_rxd_phys_addr;
675 __le16 qos_control;
676 __le16 htsig2;
677 __le32 hw_rssi_info;
678 __le32 hw_noise_floor_info;
679 __u8 noise_floor;
680 __u8 pad0[3];
681 __u8 rssi;
682 __u8 rx_status;
683 __u8 channel;
684 __u8 rx_ctrl;
685} __attribute__((packed));
686
89a91f4f
LB		 687#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
688#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
689#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 690
89a91f4f 691#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 692
89a91f4f 693static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 694{
89a91f4f 695 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 696
697 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 698 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 699}
700
89a91f4f 701static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 702{
89a91f4f 703 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 704
705 rxd->pkt_len = cpu_to_le16(len);
706 rxd->pkt_phys_addr = cpu_to_le32(addr);
707 wmb();
708 rxd->rx_ctrl = 0;
709}
710
711static int
89a91f4f
LB		 712mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
713 __le16 *qos)
6f6d1e9a 714{
89a91f4f 715 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 716
89a91f4f 717 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 718 return -1;
719 rmb();
720
721 memset(status, 0, sizeof(*status));
722
723 status->signal = -rxd->rssi;
724 status->noise = -rxd->noise_floor;
725
89a91f4f 726 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 727 status->flag |= RX_FLAG_HT;
89a91f4f 728 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 729 status->flag |= RX_FLAG_40MHZ;
89a91f4f 730 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 731 } else {
732 int i;
733
734 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
735 if (mwl8k_rates[i].hw_value == rxd->rate) {
736 status->rate_idx = i;
737 break;
738 }
739 }
740 }
741
742 status->band = IEEE80211_BAND_2GHZ;
743 status->freq = ieee80211_channel_to_frequency(rxd->channel);
744
20f09c3d
LB		 745 *qos = rxd->qos_control;
746
6f6d1e9a
LB		 747 return le16_to_cpu(rxd->pkt_len);
748}
749
89a91f4f
LB		 750static struct rxd_ops rxd_8366_ap_ops = {
751 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
752 .rxd_init = mwl8k_rxd_8366_ap_init,
753 .rxd_refill = mwl8k_rxd_8366_ap_refill,
754 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB		 755};
756
757/*
89a91f4f 758 * Packet reception for STA firmware.
a66098da 759 */
89a91f4f 760struct mwl8k_rxd_sta {
a66098da
LB		 761 __le16 pkt_len;
762 __u8 link_quality;
763 __u8 noise_level;
764 __le32 pkt_phys_addr;
45eb400d 765 __le32 next_rxd_phys_addr;
a66098da
LB		 766 __le16 qos_control;
767 __le16 rate_info;
768 __le32 pad0[4];
769 __u8 rssi;
770 __u8 channel;
771 __le16 pad1;
772 __u8 rx_ctrl;
773 __u8 rx_status;
774 __u8 pad2[2];
775} __attribute__((packed));
776
89a91f4f
LB		 777#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
778#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
779#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
780#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
781#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
782#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 783
89a91f4f 784#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
54bc3a0d 785
89a91f4f 786static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 787{
89a91f4f 788 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 789
790 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 791 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 792}
793
89a91f4f 794static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 795{
89a91f4f 796 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 797
798 rxd->pkt_len = cpu_to_le16(len);
799 rxd->pkt_phys_addr = cpu_to_le32(addr);
800 wmb();
801 rxd->rx_ctrl = 0;
802}
803
804static int
89a91f4f 805mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
20f09c3d 806 __le16 *qos)
54bc3a0d 807{
89a91f4f 808 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 809 u16 rate_info;
810
89a91f4f 811 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 812 return -1;
813 rmb();
814
815 rate_info = le16_to_cpu(rxd->rate_info);
816
817 memset(status, 0, sizeof(*status));
818
819 status->signal = -rxd->rssi;
820 status->noise = -rxd->noise_level;
89a91f4f
LB		 821 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
822 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 823
89a91f4f 824 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 825 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 826 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 827 status->flag |= RX_FLAG_40MHZ;
89a91f4f 828 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 829 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 830 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 831 status->flag |= RX_FLAG_HT;
832
833 status->band = IEEE80211_BAND_2GHZ;
834 status->freq = ieee80211_channel_to_frequency(rxd->channel);
835
20f09c3d
LB		 836 *qos = rxd->qos_control;
837
54bc3a0d
LB		 838 return le16_to_cpu(rxd->pkt_len);
839}
840
89a91f4f
LB		 841static struct rxd_ops rxd_sta_ops = {
842 .rxd_size = sizeof(struct mwl8k_rxd_sta),
843 .rxd_init = mwl8k_rxd_sta_init,
844 .rxd_refill = mwl8k_rxd_sta_refill,
845 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 846};
847
848
a66098da
LB		 849#define MWL8K_RX_DESCS 256
850#define MWL8K_RX_MAXSZ 3800
851
852static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
853{
854 struct mwl8k_priv *priv = hw->priv;
855 struct mwl8k_rx_queue *rxq = priv->rxq + index;
856 int size;
857 int i;
858
45eb400d
LB		 859 rxq->rxd_count = 0;
860 rxq->head = 0;
861 rxq->tail = 0;
a66098da 862
54bc3a0d 863 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 864
45eb400d
LB		 865 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
866 if (rxq->rxd == NULL) {
a66098da 867 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 868 wiphy_name(hw->wiphy));
a66098da
LB		 869 return -ENOMEM;
870 }
45eb400d 871 memset(rxq->rxd, 0, size);
a66098da 872
788838eb
LB		 873 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
874 if (rxq->buf == NULL) {
a66098da 875 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 876 wiphy_name(hw->wiphy));
45eb400d 877 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 878 return -ENOMEM;
879 }
788838eb 880 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 881
882 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 883 int desc_size;
884 void *rxd;
a66098da 885 int nexti;
54bc3a0d
LB		 886 dma_addr_t next_dma_addr;
887
888 desc_size = priv->rxd_ops->rxd_size;
889 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 890
54bc3a0d
LB		 891 nexti = i + 1;
892 if (nexti == MWL8K_RX_DESCS)
893 nexti = 0;
894 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 895
54bc3a0d 896 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 897 }
898
899 return 0;
900}
901
902static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
903{
904 struct mwl8k_priv *priv = hw->priv;
905 struct mwl8k_rx_queue *rxq = priv->rxq + index;
906 int refilled;
907
908 refilled = 0;
45eb400d 909 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 910 struct sk_buff *skb;
788838eb 911 dma_addr_t addr;
a66098da 912 int rx;
54bc3a0d 913 void *rxd;
a66098da
LB		 914
915 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
916 if (skb == NULL)
917 break;
918
788838eb
LB		 919 addr = pci_map_single(priv->pdev, skb->data,
920 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 921
54bc3a0d
LB		 922 rxq->rxd_count++;
923 rx = rxq->tail++;
924 if (rxq->tail == MWL8K_RX_DESCS)
925 rxq->tail = 0;
788838eb
LB		 926 rxq->buf[rx].skb = skb;
927 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 928
929 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
930 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 931
932 refilled++;
933 }
934
935 return refilled;
936}
937
938/* Must be called only when the card's reception is completely halted */
939static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
940{
941 struct mwl8k_priv *priv = hw->priv;
942 struct mwl8k_rx_queue *rxq = priv->rxq + index;
943 int i;
944
945 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 946 if (rxq->buf[i].skb != NULL) {
947 pci_unmap_single(priv->pdev,
948 pci_unmap_addr(&rxq->buf[i], dma),
949 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
950 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
951
952 kfree_skb(rxq->buf[i].skb);
953 rxq->buf[i].skb = NULL;
a66098da
LB		 954 }
955 }
956
788838eb
LB		 957 kfree(rxq->buf);
958 rxq->buf = NULL;
a66098da
LB		 959
960 pci_free_consistent(priv->pdev,
54bc3a0d 961 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 962 rxq->rxd, rxq->rxd_dma);
963 rxq->rxd = NULL;
a66098da
LB		 964}
965
966
967/*
968 * Scan a list of BSSIDs to process for finalize join.
969 * Allows for extension to process multiple BSSIDs.
970 */
971static inline int
972mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
973{
974 return priv->capture_beacon &&
975 ieee80211_is_beacon(wh->frame_control) &&
976 !compare_ether_addr(wh->addr3, priv->capture_bssid);
977}
978
3779752d
LB		 979static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
980 struct sk_buff *skb)
a66098da 981{
3779752d
LB		 982 struct mwl8k_priv *priv = hw->priv;
983
a66098da 984 priv->capture_beacon = false;
d89173f2 985 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 986
987 /*
988 * Use GFP_ATOMIC as rxq_process is called from
989 * the primary interrupt handler, memory allocation call
990 * must not sleep.
991 */
992 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
993 if (priv->beacon_skb != NULL)
3779752d 994 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 995}
996
997static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
998{
999 struct mwl8k_priv *priv = hw->priv;
1000 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1001 int processed;
1002
1003 processed = 0;
45eb400d 1004 while (rxq->rxd_count && limit--) {
a66098da 1005 struct sk_buff *skb;
54bc3a0d
LB		 1006 void *rxd;
1007 int pkt_len;
a66098da 1008 struct ieee80211_rx_status status;
20f09c3d 1009 __le16 qos;
a66098da 1010
788838eb 1011 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1012 if (skb == NULL)
1013 break;
54bc3a0d
LB		 1014
1015 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1016
20f09c3d 1017 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
54bc3a0d
LB		 1018 if (pkt_len < 0)
1019 break;
1020
788838eb
LB		 1021 rxq->buf[rxq->head].skb = NULL;
1022
1023 pci_unmap_single(priv->pdev,
1024 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1025 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1026 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1027
54bc3a0d
LB		 1028 rxq->head++;
1029 if (rxq->head == MWL8K_RX_DESCS)
1030 rxq->head = 0;
1031
45eb400d 1032 rxq->rxd_count--;
a66098da 1033
54bc3a0d 1034 skb_put(skb, pkt_len);
20f09c3d 1035 mwl8k_remove_dma_header(skb, qos);
a66098da 1036
a66098da 1037 /*
c2c357ce
LB		 1038 * Check for a pending join operation. Save a
1039 * copy of the beacon and schedule a tasklet to
1040 * send a FINALIZE_JOIN command to the firmware.
a66098da 1041 */
54bc3a0d 1042 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1043 mwl8k_save_beacon(hw, skb);
a66098da 1044
f1d58c25
JB		 1045 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1046 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1047
1048 processed++;
1049 }
1050
1051 return processed;
1052}
1053
1054
1055/*
1056 * Packet transmission.
1057 */
1058
a66098da
LB		 1059#define MWL8K_TXD_STATUS_OK 0x00000001
1060#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1061#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1062#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1063#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1064
e0493a8d
LB		 1065#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1066#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1067#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1068#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1069#define MWL8K_QOS_EOSP 0x0010
1070
a66098da
LB		 1071struct mwl8k_tx_desc {
1072 __le32 status;
1073 __u8 data_rate;
1074 __u8 tx_priority;
1075 __le16 qos_control;
1076 __le32 pkt_phys_addr;
1077 __le16 pkt_len;
d89173f2 1078 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1079 __le32 next_txd_phys_addr;
a66098da
LB		 1080 __le32 reserved;
1081 __le16 rate_info;
1082 __u8 peer_id;
1083 __u8 tx_frag_cnt;
1084} __attribute__((packed));
1085
1086#define MWL8K_TX_DESCS 128
1087
1088static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1089{
1090 struct mwl8k_priv *priv = hw->priv;
1091 struct mwl8k_tx_queue *txq = priv->txq + index;
1092 int size;
1093 int i;
1094
45eb400d
LB		 1095 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1096 txq->stats.limit = MWL8K_TX_DESCS;
1097 txq->head = 0;
1098 txq->tail = 0;
a66098da
LB		 1099
1100 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1101
45eb400d
LB		 1102 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1103 if (txq->txd == NULL) {
a66098da 1104 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1105 wiphy_name(hw->wiphy));
a66098da
LB		 1106 return -ENOMEM;
1107 }
45eb400d 1108 memset(txq->txd, 0, size);
a66098da 1109
45eb400d
LB		 1110 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1111 if (txq->skb == NULL) {
a66098da 1112 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1113 wiphy_name(hw->wiphy));
45eb400d 1114 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1115 return -ENOMEM;
1116 }
45eb400d 1117 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1118
1119 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1120 struct mwl8k_tx_desc *tx_desc;
1121 int nexti;
1122
45eb400d 1123 tx_desc = txq->txd + i;
a66098da
LB		 1124 nexti = (i + 1) % MWL8K_TX_DESCS;
1125
1126 tx_desc->status = 0;
45eb400d
LB		 1127 tx_desc->next_txd_phys_addr =
1128 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1129 }
1130
1131 return 0;
1132}
1133
1134static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1135{
1136 iowrite32(MWL8K_H2A_INT_PPA_READY,
1137 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1138 iowrite32(MWL8K_H2A_INT_DUMMY,
1139 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1140 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1141}
1142
7e1112d3 1143static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1144{
7e1112d3
LB		 1145 struct mwl8k_priv *priv = hw->priv;
1146 int i;
1147
1148 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1149 struct mwl8k_tx_queue *txq = priv->txq + i;
1150 int fw_owned = 0;
1151 int drv_owned = 0;
1152 int unused = 0;
1153 int desc;
1154
a66098da 1155 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1156 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1157 u32 status;
a66098da 1158
7e1112d3 1159 status = le32_to_cpu(tx_desc->status);
a66098da 1160 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1161 fw_owned++;
a66098da 1162 else
7e1112d3 1163 drv_owned++;
a66098da
LB		 1164
1165 if (tx_desc->pkt_len == 0)
7e1112d3 1166 unused++;
a66098da 1167 }
a66098da 1168
7e1112d3
LB		 1169 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1170 "fw_owned=%d drv_owned=%d unused=%d\n",
1171 wiphy_name(hw->wiphy), i,
1172 txq->stats.len, txq->head, txq->tail,
1173 fw_owned, drv_owned, unused);
1174 }
a66098da
LB		 1175}
1176
618952a7 1177/*
88de754a 1178 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1179 */
62abd3cf 1180#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1181
950d5b01 1182static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1183{
a66098da 1184 struct mwl8k_priv *priv = hw->priv;
88de754a 1185 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1186 int retry;
1187 int rc;
a66098da
LB		 1188
1189 might_sleep();
1190
7e1112d3
LB		 1191 /*
1192 * The TX queues are stopped at this point, so this test
1193 * doesn't need to take ->tx_lock.
1194 */
1195 if (!priv->pending_tx_pkts)
1196 return 0;
1197
1198 retry = 0;
1199 rc = 0;
1200
a66098da 1201 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1202 priv->tx_wait = &tx_wait;
1203 while (!rc) {
1204 int oldcount;
1205 unsigned long timeout;
a66098da 1206
7e1112d3 1207 oldcount = priv->pending_tx_pkts;
a66098da 1208
7e1112d3 1209 spin_unlock_bh(&priv->tx_lock);
88de754a 1210 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1211 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1212 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1213
1214 if (timeout) {
1215 WARN_ON(priv->pending_tx_pkts);
1216 if (retry) {
1217 printk(KERN_NOTICE "%s: tx rings drained\n",
1218 wiphy_name(hw->wiphy));
1219 }
1220 break;
1221 }
1222
1223 if (priv->pending_tx_pkts < oldcount) {
9a2303b9
LB		 1224 printk(KERN_NOTICE "%s: waiting for tx rings "
1225 "to drain (%d -> %d pkts)\n",
7e1112d3
LB		 1226 wiphy_name(hw->wiphy), oldcount,
1227 priv->pending_tx_pkts);
1228 retry = 1;
1229 continue;
1230 }
1231
a66098da 1232 priv->tx_wait = NULL;
a66098da 1233
7e1112d3
LB		 1234 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1235 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1236 mwl8k_dump_tx_rings(hw);
1237
1238 rc = -ETIMEDOUT;
a66098da 1239 }
7e1112d3 1240 spin_unlock_bh(&priv->tx_lock);
a66098da 1241
7e1112d3 1242 return rc;
a66098da
LB		 1243}
1244
c23b5a69
LB		 1245#define MWL8K_TXD_SUCCESS(status) \
1246 ((status) & (MWL8K_TXD_STATUS_OK | \
1247 MWL8K_TXD_STATUS_OK_RETRY | \
1248 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1249
efb7c49a
LB		 1250static int
1251mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB		 1252{
1253 struct mwl8k_priv *priv = hw->priv;
1254 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1255 int processed;
a66098da 1256
efb7c49a
LB		 1257 processed = 0;
1258 while (txq->stats.len > 0 && limit--) {
a66098da 1259 int tx;
a66098da
LB		 1260 struct mwl8k_tx_desc *tx_desc;
1261 unsigned long addr;
ce9e2e1b 1262 int size;
a66098da
LB		 1263 struct sk_buff *skb;
1264 struct ieee80211_tx_info *info;
1265 u32 status;
1266
45eb400d
LB		 1267 tx = txq->head;
1268 tx_desc = txq->txd + tx;
a66098da
LB		 1269
1270 status = le32_to_cpu(tx_desc->status);
1271
1272 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1273 if (!force)
1274 break;
1275 tx_desc->status &=
1276 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1277 }
1278
45eb400d
LB		 1279 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1280 BUG_ON(txq->stats.len == 0);
1281 txq->stats.len--;
a66098da
LB		 1282 priv->pending_tx_pkts--;
1283
1284 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1285 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1286 skb = txq->skb[tx];
1287 txq->skb[tx] = NULL;
a66098da
LB		 1288
1289 BUG_ON(skb == NULL);
1290 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1291
20f09c3d 1292 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1293
1294 /* Mark descriptor as unused */
1295 tx_desc->pkt_phys_addr = 0;
1296 tx_desc->pkt_len = 0;
1297
a66098da
LB		 1298 info = IEEE80211_SKB_CB(skb);
1299 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1300 if (MWL8K_TXD_SUCCESS(status))
a66098da 1301 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1302
1303 ieee80211_tx_status_irqsafe(hw, skb);
1304
efb7c49a 1305 processed++;
a66098da
LB		 1306 }
1307
efb7c49a 1308 if (processed && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da 1309 ieee80211_wake_queue(hw, index);
efb7c49a
LB		 1310
1311 return processed;
a66098da
LB		 1312}
1313
1314/* must be called only when the card's transmit is completely halted */
1315static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1316{
1317 struct mwl8k_priv *priv = hw->priv;
1318 struct mwl8k_tx_queue *txq = priv->txq + index;
1319
efb7c49a 1320 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1321
45eb400d
LB		 1322 kfree(txq->skb);
1323 txq->skb = NULL;
a66098da
LB		 1324
1325 pci_free_consistent(priv->pdev,
1326 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1327 txq->txd, txq->txd_dma);
1328 txq->txd = NULL;
a66098da
LB		 1329}
1330
1331static int
1332mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1333{
1334 struct mwl8k_priv *priv = hw->priv;
1335 struct ieee80211_tx_info *tx_info;
23b33906 1336 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1337 struct ieee80211_hdr *wh;
1338 struct mwl8k_tx_queue *txq;
1339 struct mwl8k_tx_desc *tx;
a66098da 1340 dma_addr_t dma;
23b33906
LB		 1341 u32 txstatus;
1342 u8 txdatarate;
1343 u16 qos;
a66098da 1344
23b33906
LB		 1345 wh = (struct ieee80211_hdr *)skb->data;
1346 if (ieee80211_is_data_qos(wh->frame_control))
1347 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1348 else
1349 qos = 0;
a66098da 1350
76266b2a 1351 mwl8k_add_dma_header(skb);
23b33906 1352 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1353
1354 tx_info = IEEE80211_SKB_CB(skb);
1355 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1356
1357 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
a66098da 1358 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
657232b6
LB		 1359 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1360 mwl8k_vif->seqno += 0x10;
a66098da
LB		 1361 }
1362
23b33906
LB		 1363 /* Setup firmware control bit fields for each frame type. */
1364 txstatus = 0;
1365 txdatarate = 0;
1366 if (ieee80211_is_mgmt(wh->frame_control) ||
1367 ieee80211_is_ctl(wh->frame_control)) {
1368 txdatarate = 0;
e0493a8d 1369 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1370 } else if (ieee80211_is_data(wh->frame_control)) {
1371 txdatarate = 1;
1372 if (is_multicast_ether_addr(wh->addr1))
1373 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1374
e0493a8d 1375 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1376 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1377 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1378 else
e0493a8d 1379 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1380 }
a66098da
LB		 1381
1382 dma = pci_map_single(priv->pdev, skb->data,
1383 skb->len, PCI_DMA_TODEVICE);
1384
1385 if (pci_dma_mapping_error(priv->pdev, dma)) {
1386 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1387 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1388 dev_kfree_skb(skb);
a66098da
LB		 1389 return NETDEV_TX_OK;
1390 }
1391
23b33906 1392 spin_lock_bh(&priv->tx_lock);
a66098da 1393
23b33906 1394 txq = priv->txq + index;
a66098da 1395
45eb400d
LB		 1396 BUG_ON(txq->skb[txq->tail] != NULL);
1397 txq->skb[txq->tail] = skb;
a66098da 1398
45eb400d 1399 tx = txq->txd + txq->tail;
23b33906
LB		 1400 tx->data_rate = txdatarate;
1401 tx->tx_priority = index;
a66098da 1402 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1403 tx->pkt_phys_addr = cpu_to_le32(dma);
1404 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1405 tx->rate_info = 0;
a680400e
LB		 1406 if (!priv->ap_fw && tx_info->control.sta != NULL)
1407 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1408 else
1409 tx->peer_id = 0;
a66098da 1410 wmb();
23b33906
LB		 1411 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1412
45eb400d
LB		 1413 txq->stats.count++;
1414 txq->stats.len++;
a66098da 1415 priv->pending_tx_pkts++;
a66098da 1416
45eb400d
LB		 1417 txq->tail++;
1418 if (txq->tail == MWL8K_TX_DESCS)
1419 txq->tail = 0;
23b33906 1420
45eb400d 1421 if (txq->head == txq->tail)
a66098da
LB		 1422 ieee80211_stop_queue(hw, index);
1423
23b33906 1424 mwl8k_tx_start(priv);
a66098da
LB		 1425
1426 spin_unlock_bh(&priv->tx_lock);
1427
1428 return NETDEV_TX_OK;
1429}
1430
1431
618952a7
LB		 1432/*
1433 * Firmware access.
1434 *
1435 * We have the following requirements for issuing firmware commands:
1436 * - Some commands require that the packet transmit path is idle when
1437 * the command is issued. (For simplicity, we'll just quiesce the
1438 * transmit path for every command.)
1439 * - There are certain sequences of commands that need to be issued to
1440 * the hardware sequentially, with no other intervening commands.
1441 *
1442 * This leads to an implementation of a "firmware lock" as a mutex that
1443 * can be taken recursively, and which is taken by both the low-level
1444 * command submission function (mwl8k_post_cmd) as well as any users of
1445 * that function that require issuing of an atomic sequence of commands,
1446 * and quiesces the transmit path whenever it's taken.
1447 */
1448static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1449{
1450 struct mwl8k_priv *priv = hw->priv;
1451
1452 if (priv->fw_mutex_owner != current) {
1453 int rc;
1454
1455 mutex_lock(&priv->fw_mutex);
1456 ieee80211_stop_queues(hw);
1457
1458 rc = mwl8k_tx_wait_empty(hw);
1459 if (rc) {
1460 ieee80211_wake_queues(hw);
1461 mutex_unlock(&priv->fw_mutex);
1462
1463 return rc;
1464 }
1465
1466 priv->fw_mutex_owner = current;
1467 }
1468
1469 priv->fw_mutex_depth++;
1470
1471 return 0;
1472}
1473
1474static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1475{
1476 struct mwl8k_priv *priv = hw->priv;
1477
1478 if (!--priv->fw_mutex_depth) {
1479 ieee80211_wake_queues(hw);
1480 priv->fw_mutex_owner = NULL;
1481 mutex_unlock(&priv->fw_mutex);
1482 }
1483}
1484
1485
a66098da
LB		 1486/*
1487 * Command processing.
1488 */
1489
0c9cc640
LB		 1490/* Timeout firmware commands after 10s */
1491#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 1492
1493static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1494{
1495 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1496 struct mwl8k_priv *priv = hw->priv;
1497 void __iomem *regs = priv->regs;
1498 dma_addr_t dma_addr;
1499 unsigned int dma_size;
1500 int rc;
a66098da
LB		 1501 unsigned long timeout = 0;
1502 u8 buf[32];
1503
c2c357ce 1504 cmd->result = 0xffff;
a66098da
LB		 1505 dma_size = le16_to_cpu(cmd->length);
1506 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1507 PCI_DMA_BIDIRECTIONAL);
1508 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1509 return -ENOMEM;
1510
618952a7 1511 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1512 if (rc) {
1513 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1514 PCI_DMA_BIDIRECTIONAL);
618952a7 1515 return rc;
39a1e42e 1516 }
a66098da 1517
a66098da
LB		 1518 priv->hostcmd_wait = &cmd_wait;
1519 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1520 iowrite32(MWL8K_H2A_INT_DOORBELL,
1521 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1522 iowrite32(MWL8K_H2A_INT_DUMMY,
1523 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1524
1525 timeout = wait_for_completion_timeout(&cmd_wait,
1526 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1527
618952a7
LB		 1528 priv->hostcmd_wait = NULL;
1529
1530 mwl8k_fw_unlock(hw);
1531
37055bd4
LB		 1532 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1533 PCI_DMA_BIDIRECTIONAL);
1534
a66098da 1535 if (!timeout) {
a66098da 1536 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1537 wiphy_name(hw->wiphy),
a66098da
LB		 1538 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1539 MWL8K_CMD_TIMEOUT_MS);
1540 rc = -ETIMEDOUT;
1541 } else {
0c9cc640
LB		 1542 int ms;
1543
1544 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1545
ce9e2e1b 1546 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1547 if (rc)
1548 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1549 wiphy_name(hw->wiphy),
a66098da 1550 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1551 le16_to_cpu(cmd->result));
0c9cc640
LB		 1552 else if (ms > 2000)
1553 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1554 wiphy_name(hw->wiphy),
1555 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1556 ms);
a66098da
LB		 1557 }
1558
a66098da
LB		 1559 return rc;
1560}
1561
1562/*
04b147b1 1563 * CMD_GET_HW_SPEC (STA version).
a66098da 1564 */
04b147b1 1565struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1566 struct mwl8k_cmd_pkt header;
1567 __u8 hw_rev;
1568 __u8 host_interface;
1569 __le16 num_mcaddrs;
d89173f2 1570 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1571 __le16 region_code;
1572 __le32 fw_rev;
1573 __le32 ps_cookie;
1574 __le32 caps;
1575 __u8 mcs_bitmap[16];
1576 __le32 rx_queue_ptr;
1577 __le32 num_tx_queues;
1578 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1579 __le32 caps2;
1580 __le32 num_tx_desc_per_queue;
45eb400d 1581 __le32 total_rxd;
a66098da
LB		 1582} __attribute__((packed));
1583
341c9791
LB		 1584#define MWL8K_CAP_MAX_AMSDU 0x20000000
1585#define MWL8K_CAP_GREENFIELD 0x08000000
1586#define MWL8K_CAP_AMPDU 0x04000000
1587#define MWL8K_CAP_RX_STBC 0x01000000
1588#define MWL8K_CAP_TX_STBC 0x00800000
1589#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
1590#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
1591#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
1592#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
1593#define MWL8K_CAP_DELAY_BA 0x00003000
1594#define MWL8K_CAP_MIMO 0x00000200
1595#define MWL8K_CAP_40MHZ 0x00000100
1596
1597static void mwl8k_set_ht_caps(struct ieee80211_hw *hw, u32 cap)
1598{
1599 struct mwl8k_priv *priv = hw->priv;
1600 int rx_streams;
1601 int tx_streams;
1602
1603 priv->band.ht_cap.ht_supported = 1;
1604
1605 if (cap & MWL8K_CAP_MAX_AMSDU)
1606 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
1607 if (cap & MWL8K_CAP_GREENFIELD)
1608 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
1609 if (cap & MWL8K_CAP_AMPDU) {
1610 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
1611 priv->band.ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1612 priv->band.ht_cap.ampdu_density =
1613 IEEE80211_HT_MPDU_DENSITY_NONE;
1614 }
1615 if (cap & MWL8K_CAP_RX_STBC)
1616 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
1617 if (cap & MWL8K_CAP_TX_STBC)
1618 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
1619 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
1620 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
1621 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
1622 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
1623 if (cap & MWL8K_CAP_DELAY_BA)
1624 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
1625 if (cap & MWL8K_CAP_40MHZ)
1626 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
1627
1628 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
1629 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
1630
1631 priv->band.ht_cap.mcs.rx_mask[0] = 0xff;
1632 if (rx_streams >= 2)
1633 priv->band.ht_cap.mcs.rx_mask[1] = 0xff;
1634 if (rx_streams >= 3)
1635 priv->band.ht_cap.mcs.rx_mask[2] = 0xff;
1636 priv->band.ht_cap.mcs.rx_mask[4] = 0x01;
1637 priv->band.ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
1638
1639 if (rx_streams != tx_streams) {
1640 priv->band.ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
1641 priv->band.ht_cap.mcs.tx_params |= (tx_streams - 1) <<
1642 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
1643 }
1644}
1645
04b147b1 1646static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1647{
1648 struct mwl8k_priv *priv = hw->priv;
04b147b1 1649 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1650 int rc;
1651 int i;
1652
1653 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1654 if (cmd == NULL)
1655 return -ENOMEM;
1656
1657 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1658 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1659
1660 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1661 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1662 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1663 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1664 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1665 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1666 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1667 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1668
1669 rc = mwl8k_post_cmd(hw, &cmd->header);
1670
1671 if (!rc) {
1672 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1673 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1674 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1675 priv->hw_rev = cmd->hw_rev;
341c9791
LB		 1676 if (cmd->caps & cpu_to_le32(MWL8K_CAP_MIMO))
1677 mwl8k_set_ht_caps(hw, le32_to_cpu(cmd->caps));
a66098da
LB		 1678 }
1679
1680 kfree(cmd);
1681 return rc;
1682}
1683
42fba21d
LB		 1684/*
1685 * CMD_GET_HW_SPEC (AP version).
1686 */
1687struct mwl8k_cmd_get_hw_spec_ap {
1688 struct mwl8k_cmd_pkt header;
1689 __u8 hw_rev;
1690 __u8 host_interface;
1691 __le16 num_wcb;
1692 __le16 num_mcaddrs;
1693 __u8 perm_addr[ETH_ALEN];
1694 __le16 region_code;
1695 __le16 num_antenna;
1696 __le32 fw_rev;
1697 __le32 wcbbase0;
1698 __le32 rxwrptr;
1699 __le32 rxrdptr;
1700 __le32 ps_cookie;
1701 __le32 wcbbase1;
1702 __le32 wcbbase2;
1703 __le32 wcbbase3;
1704} __attribute__((packed));
1705
1706static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1707{
1708 struct mwl8k_priv *priv = hw->priv;
1709 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1710 int rc;
1711
1712 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1713 if (cmd == NULL)
1714 return -ENOMEM;
1715
1716 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1717 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1718
1719 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1720 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1721
1722 rc = mwl8k_post_cmd(hw, &cmd->header);
1723
1724 if (!rc) {
1725 int off;
1726
1727 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1728 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1729 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1730 priv->hw_rev = cmd->hw_rev;
1731
1732 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1733 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1734
1735 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1736 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1737
1738 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1739 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1740
1741 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1742 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1743
1744 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1745 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1746
1747 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1748 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1749 }
1750
1751 kfree(cmd);
1752 return rc;
1753}
1754
1755/*
1756 * CMD_SET_HW_SPEC.
1757 */
1758struct mwl8k_cmd_set_hw_spec {
1759 struct mwl8k_cmd_pkt header;
1760 __u8 hw_rev;
1761 __u8 host_interface;
1762 __le16 num_mcaddrs;
1763 __u8 perm_addr[ETH_ALEN];
1764 __le16 region_code;
1765 __le32 fw_rev;
1766 __le32 ps_cookie;
1767 __le32 caps;
1768 __le32 rx_queue_ptr;
1769 __le32 num_tx_queues;
1770 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1771 __le32 flags;
1772 __le32 num_tx_desc_per_queue;
1773 __le32 total_rxd;
1774} __attribute__((packed));
1775
b64fe619
LB		 1776#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1777#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
1778#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB		 1779
1780static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1781{
1782 struct mwl8k_priv *priv = hw->priv;
1783 struct mwl8k_cmd_set_hw_spec *cmd;
1784 int rc;
1785 int i;
1786
1787 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1788 if (cmd == NULL)
1789 return -ENOMEM;
1790
1791 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1792 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1793
1794 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1795 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1796 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1797 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1798 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
b64fe619
LB		 1799 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
1800 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
1801 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
42fba21d
LB		 1802 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1803 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1804
1805 rc = mwl8k_post_cmd(hw, &cmd->header);
1806 kfree(cmd);
1807
1808 return rc;
1809}
1810
a66098da
LB		 1811/*
1812 * CMD_MAC_MULTICAST_ADR.
1813 */
1814struct mwl8k_cmd_mac_multicast_adr {
1815 struct mwl8k_cmd_pkt header;
1816 __le16 action;
1817 __le16 numaddr;
ce9e2e1b 1818 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1819};
1820
d5e30845
LB		 1821#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1822#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1823#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1824#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1825
e81cd2d6 1826static struct mwl8k_cmd_pkt *
447ced07 1827__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1828 int mc_count, struct dev_addr_list *mclist)
a66098da 1829{
e81cd2d6 1830 struct mwl8k_priv *priv = hw->priv;
a66098da 1831 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1832 int size;
e81cd2d6 1833
447ced07 1834 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1835 allmulti = 1;
1836 mc_count = 0;
1837 }
e81cd2d6
LB		 1838
1839 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1840
e81cd2d6 1841 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1842 if (cmd == NULL)
e81cd2d6 1843 return NULL;
a66098da
LB		 1844
1845 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1846 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1847 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1848 MWL8K_ENABLE_RX_BROADCAST);
1849
1850 if (allmulti) {
1851 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1852 } else if (mc_count) {
1853 int i;
1854
1855 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1856 cmd->numaddr = cpu_to_le16(mc_count);
1857 for (i = 0; i < mc_count && mclist; i++) {
1858 if (mclist->da_addrlen != ETH_ALEN) {
1859 kfree(cmd);
1860 return NULL;
1861 }
1862 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1863 mclist = mclist->next;
a66098da 1864 }
a66098da
LB		 1865 }
1866
e81cd2d6 1867 return &cmd->header;
a66098da
LB		 1868}
1869
1870/*
55489b6e 1871 * CMD_GET_STAT.
a66098da 1872 */
55489b6e 1873struct mwl8k_cmd_get_stat {
a66098da 1874 struct mwl8k_cmd_pkt header;
a66098da
LB		 1875 __le32 stats[64];
1876} __attribute__((packed));
1877
1878#define MWL8K_STAT_ACK_FAILURE 9
1879#define MWL8K_STAT_RTS_FAILURE 12
1880#define MWL8K_STAT_FCS_ERROR 24
1881#define MWL8K_STAT_RTS_SUCCESS 11
1882
55489b6e
LB		 1883static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
1884 struct ieee80211_low_level_stats *stats)
a66098da 1885{
55489b6e 1886 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 1887 int rc;
1888
1889 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1890 if (cmd == NULL)
1891 return -ENOMEM;
1892
1893 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1894 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1895
1896 rc = mwl8k_post_cmd(hw, &cmd->header);
1897 if (!rc) {
1898 stats->dot11ACKFailureCount =
1899 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1900 stats->dot11RTSFailureCount =
1901 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1902 stats->dot11FCSErrorCount =
1903 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1904 stats->dot11RTSSuccessCount =
1905 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1906 }
1907 kfree(cmd);
1908
1909 return rc;
1910}
1911
1912/*
55489b6e 1913 * CMD_RADIO_CONTROL.
a66098da 1914 */
55489b6e 1915struct mwl8k_cmd_radio_control {
a66098da
LB		 1916 struct mwl8k_cmd_pkt header;
1917 __le16 action;
1918 __le16 control;
1919 __le16 radio_on;
1920} __attribute__((packed));
1921
c46563b7 1922static int
55489b6e 1923mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1924{
1925 struct mwl8k_priv *priv = hw->priv;
55489b6e 1926 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 1927 int rc;
1928
c46563b7 1929 if (enable == priv->radio_on && !force)
a66098da
LB		 1930 return 0;
1931
a66098da
LB		 1932 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1933 if (cmd == NULL)
1934 return -ENOMEM;
1935
1936 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1937 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1938 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1939 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1940 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1941
1942 rc = mwl8k_post_cmd(hw, &cmd->header);
1943 kfree(cmd);
1944
1945 if (!rc)
c46563b7 1946 priv->radio_on = enable;
a66098da
LB		 1947
1948 return rc;
1949}
1950
55489b6e 1951static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 1952{
55489b6e 1953 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 1954}
1955
55489b6e 1956static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 1957{
55489b6e 1958 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 1959}
1960
a66098da
LB		 1961static int
1962mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1963{
99200a99 1964 struct mwl8k_priv *priv = hw->priv;
a66098da 1965
68ce3884 1966 priv->radio_short_preamble = short_preamble;
a66098da 1967
55489b6e 1968 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 1969}
1970
1971/*
55489b6e 1972 * CMD_RF_TX_POWER.
a66098da
LB		 1973 */
1974#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1975
55489b6e 1976struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 1977 struct mwl8k_cmd_pkt header;
1978 __le16 action;
1979 __le16 support_level;
1980 __le16 current_level;
1981 __le16 reserved;
1982 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1983} __attribute__((packed));
1984
55489b6e 1985static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 1986{
55489b6e 1987 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 1988 int rc;
1989
1990 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1991 if (cmd == NULL)
1992 return -ENOMEM;
1993
1994 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1995 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1996 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1997 cmd->support_level = cpu_to_le16(dBm);
1998
1999 rc = mwl8k_post_cmd(hw, &cmd->header);
2000 kfree(cmd);
2001
2002 return rc;
2003}
2004
08b06347
LB		 2005/*
2006 * CMD_RF_ANTENNA.
2007 */
2008struct mwl8k_cmd_rf_antenna {
2009 struct mwl8k_cmd_pkt header;
2010 __le16 antenna;
2011 __le16 mode;
2012} __attribute__((packed));
2013
2014#define MWL8K_RF_ANTENNA_RX 1
2015#define MWL8K_RF_ANTENNA_TX 2
2016
2017static int
2018mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2019{
2020 struct mwl8k_cmd_rf_antenna *cmd;
2021 int rc;
2022
2023 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2024 if (cmd == NULL)
2025 return -ENOMEM;
2026
2027 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2028 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2029 cmd->antenna = cpu_to_le16(antenna);
2030 cmd->mode = cpu_to_le16(mask);
2031
2032 rc = mwl8k_post_cmd(hw, &cmd->header);
2033 kfree(cmd);
2034
2035 return rc;
2036}
2037
b64fe619
LB		 2038/*
2039 * CMD_SET_BEACON.
2040 */
2041struct mwl8k_cmd_set_beacon {
2042 struct mwl8k_cmd_pkt header;
2043 __le16 beacon_len;
2044 __u8 beacon[0];
2045};
2046
2047static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw, u8 *beacon, int len)
2048{
2049 struct mwl8k_cmd_set_beacon *cmd;
2050 int rc;
2051
2052 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2053 if (cmd == NULL)
2054 return -ENOMEM;
2055
2056 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2057 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2058 cmd->beacon_len = cpu_to_le16(len);
2059 memcpy(cmd->beacon, beacon, len);
2060
2061 rc = mwl8k_post_cmd(hw, &cmd->header);
2062 kfree(cmd);
2063
2064 return rc;
2065}
2066
a66098da
LB		 2067/*
2068 * CMD_SET_PRE_SCAN.
2069 */
2070struct mwl8k_cmd_set_pre_scan {
2071 struct mwl8k_cmd_pkt header;
2072} __attribute__((packed));
2073
2074static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2075{
2076 struct mwl8k_cmd_set_pre_scan *cmd;
2077 int rc;
2078
2079 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2080 if (cmd == NULL)
2081 return -ENOMEM;
2082
2083 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2084 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2085
2086 rc = mwl8k_post_cmd(hw, &cmd->header);
2087 kfree(cmd);
2088
2089 return rc;
2090}
2091
2092/*
2093 * CMD_SET_POST_SCAN.
2094 */
2095struct mwl8k_cmd_set_post_scan {
2096 struct mwl8k_cmd_pkt header;
2097 __le32 isibss;
d89173f2 2098 __u8 bssid[ETH_ALEN];
a66098da
LB		 2099} __attribute__((packed));
2100
2101static int
0a11dfc3 2102mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 2103{
2104 struct mwl8k_cmd_set_post_scan *cmd;
2105 int rc;
2106
2107 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2108 if (cmd == NULL)
2109 return -ENOMEM;
2110
2111 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2112 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2113 cmd->isibss = 0;
d89173f2 2114 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2115
2116 rc = mwl8k_post_cmd(hw, &cmd->header);
2117 kfree(cmd);
2118
2119 return rc;
2120}
2121
2122/*
2123 * CMD_SET_RF_CHANNEL.
2124 */
2125struct mwl8k_cmd_set_rf_channel {
2126 struct mwl8k_cmd_pkt header;
2127 __le16 action;
2128 __u8 current_channel;
2129 __le32 channel_flags;
2130} __attribute__((packed));
2131
2132static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 2133 struct ieee80211_conf *conf)
a66098da 2134{
610677d2 2135 struct ieee80211_channel *channel = conf->channel;
a66098da
LB		 2136 struct mwl8k_cmd_set_rf_channel *cmd;
2137 int rc;
2138
2139 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2140 if (cmd == NULL)
2141 return -ENOMEM;
2142
2143 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2144 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2145 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2146 cmd->current_channel = channel->hw_value;
610677d2 2147
a66098da 2148 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2
LB		 2149 cmd->channel_flags |= cpu_to_le32(0x00000001);
2150
2151 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2152 conf->channel_type == NL80211_CHAN_HT20)
2153 cmd->channel_flags |= cpu_to_le32(0x00000080);
2154 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2155 cmd->channel_flags |= cpu_to_le32(0x000001900);
2156 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2157 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB		 2158
2159 rc = mwl8k_post_cmd(hw, &cmd->header);
2160 kfree(cmd);
2161
2162 return rc;
2163}
2164
2165/*
55489b6e 2166 * CMD_SET_AID.
a66098da 2167 */
55489b6e
LB		 2168#define MWL8K_FRAME_PROT_DISABLED 0x00
2169#define MWL8K_FRAME_PROT_11G 0x07
2170#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2171#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2172
55489b6e
LB		 2173struct mwl8k_cmd_update_set_aid {
2174 struct mwl8k_cmd_pkt header;
2175 __le16 aid;
a66098da 2176
55489b6e
LB		 2177 /* AP's MAC address (BSSID) */
2178 __u8 bssid[ETH_ALEN];
2179 __le16 protection_mode;
2180 __u8 supp_rates[14];
a66098da
LB		 2181} __attribute__((packed));
2182
c6e96010
LB		 2183static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
2184{
2185 int i;
2186 int j;
2187
2188 /*
2189 * Clear nonstandard rates 4 and 13.
2190 */
2191 mask &= 0x1fef;
2192
2193 for (i = 0, j = 0; i < 14; i++) {
2194 if (mask & (1 << i))
2195 rates[j++] = mwl8k_rates[i].hw_value;
2196 }
2197}
2198
55489b6e 2199static int
c6e96010
LB		 2200mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2201 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 2202{
55489b6e
LB		 2203 struct mwl8k_cmd_update_set_aid *cmd;
2204 u16 prot_mode;
a66098da
LB		 2205 int rc;
2206
2207 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2208 if (cmd == NULL)
2209 return -ENOMEM;
2210
55489b6e 2211 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2212 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2213 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 2214 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2215
7dc6a7a7 2216 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 2217 prot_mode = MWL8K_FRAME_PROT_11G;
2218 } else {
7dc6a7a7 2219 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 2220 IEEE80211_HT_OP_MODE_PROTECTION) {
2221 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2222 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2223 break;
2224 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2225 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2226 break;
2227 default:
2228 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2229 break;
2230 }
2231 }
2232 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2233
c6e96010 2234 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 2235
2236 rc = mwl8k_post_cmd(hw, &cmd->header);
2237 kfree(cmd);
2238
2239 return rc;
2240}
2241
32060e1b 2242/*
55489b6e 2243 * CMD_SET_RATE.
32060e1b 2244 */
55489b6e
LB		 2245struct mwl8k_cmd_set_rate {
2246 struct mwl8k_cmd_pkt header;
2247 __u8 legacy_rates[14];
2248
2249 /* Bitmap for supported MCS codes. */
2250 __u8 mcs_set[16];
2251 __u8 reserved[16];
32060e1b
LB		 2252} __attribute__((packed));
2253
55489b6e 2254static int
c6e96010 2255mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 2256 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 2257{
55489b6e 2258 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 2259 int rc;
2260
2261 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2262 if (cmd == NULL)
2263 return -ENOMEM;
2264
55489b6e 2265 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 2266 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 2267 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 2268 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB		 2269
2270 rc = mwl8k_post_cmd(hw, &cmd->header);
2271 kfree(cmd);
2272
2273 return rc;
2274}
2275
a66098da 2276/*
55489b6e 2277 * CMD_FINALIZE_JOIN.
a66098da 2278 */
55489b6e
LB		 2279#define MWL8K_FJ_BEACON_MAXLEN 128
2280
2281struct mwl8k_cmd_finalize_join {
a66098da 2282 struct mwl8k_cmd_pkt header;
55489b6e
LB		 2283 __le32 sleep_interval; /* Number of beacon periods to sleep */
2284 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
a66098da
LB		 2285} __attribute__((packed));
2286
55489b6e
LB		 2287static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2288 int framelen, int dtim)
a66098da 2289{
55489b6e
LB		 2290 struct mwl8k_cmd_finalize_join *cmd;
2291 struct ieee80211_mgmt *payload = frame;
2292 int payload_len;
a66098da
LB		 2293 int rc;
2294
2295 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2296 if (cmd == NULL)
2297 return -ENOMEM;
2298
55489b6e 2299 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 2300 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2301 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2302
2303 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2304 if (payload_len < 0)
2305 payload_len = 0;
2306 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2307 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2308
2309 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 2310
2311 rc = mwl8k_post_cmd(hw, &cmd->header);
2312 kfree(cmd);
2313
2314 return rc;
2315}
2316
2317/*
55489b6e 2318 * CMD_SET_RTS_THRESHOLD.
a66098da 2319 */
55489b6e 2320struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 2321 struct mwl8k_cmd_pkt header;
2322 __le16 action;
55489b6e 2323 __le16 threshold;
a66098da
LB		 2324} __attribute__((packed));
2325
c2c2b12a
LB		 2326static int
2327mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 2328{
55489b6e 2329 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 2330 int rc;
2331
2332 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2333 if (cmd == NULL)
2334 return -ENOMEM;
2335
55489b6e 2336 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 2337 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB		 2338 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2339 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB		 2340
2341 rc = mwl8k_post_cmd(hw, &cmd->header);
2342 kfree(cmd);
2343
a66098da
LB		 2344 return rc;
2345}
2346
2347/*
55489b6e 2348 * CMD_SET_SLOT.
a66098da 2349 */
55489b6e 2350struct mwl8k_cmd_set_slot {
a66098da
LB		 2351 struct mwl8k_cmd_pkt header;
2352 __le16 action;
55489b6e 2353 __u8 short_slot;
a66098da
LB		 2354} __attribute__((packed));
2355
55489b6e 2356static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 2357{
55489b6e 2358 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 2359 int rc;
2360
2361 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2362 if (cmd == NULL)
2363 return -ENOMEM;
2364
55489b6e 2365 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 2366 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2367 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2368 cmd->short_slot = short_slot_time;
a66098da
LB		 2369
2370 rc = mwl8k_post_cmd(hw, &cmd->header);
2371 kfree(cmd);
2372
2373 return rc;
2374}
2375
2376/*
2377 * CMD_SET_EDCA_PARAMS.
2378 */
2379struct mwl8k_cmd_set_edca_params {
2380 struct mwl8k_cmd_pkt header;
2381
2382 /* See MWL8K_SET_EDCA_XXX below */
2383 __le16 action;
2384
2385 /* TX opportunity in units of 32 us */
2386 __le16 txop;
2387
2e484c89
LB		 2388 union {
2389 struct {
2390 /* Log exponent of max contention period: 0...15 */
2391 __le32 log_cw_max;
2392
2393 /* Log exponent of min contention period: 0...15 */
2394 __le32 log_cw_min;
2395
2396 /* Adaptive interframe spacing in units of 32us */
2397 __u8 aifs;
2398
2399 /* TX queue to configure */
2400 __u8 txq;
2401 } ap;
2402 struct {
2403 /* Log exponent of max contention period: 0...15 */
2404 __u8 log_cw_max;
a66098da 2405
2e484c89
LB		 2406 /* Log exponent of min contention period: 0...15 */
2407 __u8 log_cw_min;
a66098da 2408
2e484c89
LB		 2409 /* Adaptive interframe spacing in units of 32us */
2410 __u8 aifs;
a66098da 2411
2e484c89
LB		 2412 /* TX queue to configure */
2413 __u8 txq;
2414 } sta;
2415 };
a66098da
LB		 2416} __attribute__((packed));
2417
a66098da
LB		 2418#define MWL8K_SET_EDCA_CW 0x01
2419#define MWL8K_SET_EDCA_TXOP 0x02
2420#define MWL8K_SET_EDCA_AIFS 0x04
2421
2422#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2423 MWL8K_SET_EDCA_TXOP | \
2424 MWL8K_SET_EDCA_AIFS)
2425
2426static int
55489b6e
LB		 2427mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2428 __u16 cw_min, __u16 cw_max,
2429 __u8 aifs, __u16 txop)
a66098da 2430{
2e484c89 2431 struct mwl8k_priv *priv = hw->priv;
a66098da 2432 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2433 int rc;
2434
2435 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2436 if (cmd == NULL)
2437 return -ENOMEM;
2438
a66098da
LB		 2439 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2440 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2441 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2442 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2443 if (priv->ap_fw) {
2444 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2445 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2446 cmd->ap.aifs = aifs;
2447 cmd->ap.txq = qnum;
2448 } else {
2449 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2450 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2451 cmd->sta.aifs = aifs;
2452 cmd->sta.txq = qnum;
2453 }
a66098da
LB		 2454
2455 rc = mwl8k_post_cmd(hw, &cmd->header);
2456 kfree(cmd);
2457
2458 return rc;
2459}
2460
2461/*
55489b6e 2462 * CMD_SET_WMM_MODE.
a66098da 2463 */
55489b6e 2464struct mwl8k_cmd_set_wmm_mode {
a66098da 2465 struct mwl8k_cmd_pkt header;
55489b6e 2466 __le16 action;
a66098da
LB		 2467} __attribute__((packed));
2468
55489b6e 2469static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 2470{
55489b6e
LB		 2471 struct mwl8k_priv *priv = hw->priv;
2472 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 2473 int rc;
2474
a66098da
LB		 2475 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2476 if (cmd == NULL)
2477 return -ENOMEM;
2478
55489b6e 2479 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 2480 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 2481 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2482
2483 rc = mwl8k_post_cmd(hw, &cmd->header);
2484 kfree(cmd);
16cec43d 2485
55489b6e
LB		 2486 if (!rc)
2487 priv->wmm_enabled = enable;
a66098da
LB		 2488
2489 return rc;
2490}
2491
2492/*
55489b6e 2493 * CMD_MIMO_CONFIG.
a66098da 2494 */
55489b6e
LB		 2495struct mwl8k_cmd_mimo_config {
2496 struct mwl8k_cmd_pkt header;
2497 __le32 action;
2498 __u8 rx_antenna_map;
2499 __u8 tx_antenna_map;
a66098da
LB		 2500} __attribute__((packed));
2501
55489b6e 2502static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 2503{
55489b6e 2504 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 2505 int rc;
2506
2507 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2508 if (cmd == NULL)
2509 return -ENOMEM;
2510
55489b6e 2511 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 2512 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2513 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2514 cmd->rx_antenna_map = rx;
2515 cmd->tx_antenna_map = tx;
a66098da
LB		 2516
2517 rc = mwl8k_post_cmd(hw, &cmd->header);
2518 kfree(cmd);
2519
2520 return rc;
2521}
2522
2523/*
b71ed2c6 2524 * CMD_USE_FIXED_RATE (STA version).
a66098da 2525 */
b71ed2c6
LB		 2526struct mwl8k_cmd_use_fixed_rate_sta {
2527 struct mwl8k_cmd_pkt header;
2528 __le32 action;
2529 __le32 allow_rate_drop;
2530 __le32 num_rates;
2531 struct {
2532 __le32 is_ht_rate;
2533 __le32 enable_retry;
2534 __le32 rate;
2535 __le32 retry_count;
2536 } rate_entry[8];
2537 __le32 rate_type;
2538 __le32 reserved1;
2539 __le32 reserved2;
a66098da
LB		 2540} __attribute__((packed));
2541
b71ed2c6
LB		 2542#define MWL8K_USE_AUTO_RATE 0x0002
2543#define MWL8K_UCAST_RATE 0
a66098da 2544
b71ed2c6 2545static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 2546{
b71ed2c6 2547 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB		 2548 int rc;
2549
2550 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2551 if (cmd == NULL)
2552 return -ENOMEM;
2553
2554 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2555 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB		 2556 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2557 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB		 2558
2559 rc = mwl8k_post_cmd(hw, &cmd->header);
2560 kfree(cmd);
2561
2562 return rc;
2563}
2564
088aab8b
LB		 2565/*
2566 * CMD_USE_FIXED_RATE (AP version).
2567 */
2568struct mwl8k_cmd_use_fixed_rate_ap {
2569 struct mwl8k_cmd_pkt header;
2570 __le32 action;
2571 __le32 allow_rate_drop;
2572 __le32 num_rates;
2573 struct mwl8k_rate_entry_ap {
2574 __le32 is_ht_rate;
2575 __le32 enable_retry;
2576 __le32 rate;
2577 __le32 retry_count;
2578 } rate_entry[4];
2579 u8 multicast_rate;
2580 u8 multicast_rate_type;
2581 u8 management_rate;
2582} __attribute__((packed));
2583
2584static int
2585mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
2586{
2587 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
2588 int rc;
2589
2590 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2591 if (cmd == NULL)
2592 return -ENOMEM;
2593
2594 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2595 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2596 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2597 cmd->multicast_rate = mcast;
2598 cmd->management_rate = mgmt;
2599
2600 rc = mwl8k_post_cmd(hw, &cmd->header);
2601 kfree(cmd);
2602
2603 return rc;
2604}
2605
55489b6e
LB		 2606/*
2607 * CMD_ENABLE_SNIFFER.
2608 */
2609struct mwl8k_cmd_enable_sniffer {
2610 struct mwl8k_cmd_pkt header;
2611 __le32 action;
2612} __attribute__((packed));
2613
2614static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2615{
2616 struct mwl8k_cmd_enable_sniffer *cmd;
2617 int rc;
2618
2619 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2620 if (cmd == NULL)
2621 return -ENOMEM;
2622
2623 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2624 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2625 cmd->action = cpu_to_le32(!!enable);
2626
2627 rc = mwl8k_post_cmd(hw, &cmd->header);
2628 kfree(cmd);
2629
2630 return rc;
2631}
2632
2633/*
2634 * CMD_SET_MAC_ADDR.
2635 */
2636struct mwl8k_cmd_set_mac_addr {
2637 struct mwl8k_cmd_pkt header;
2638 union {
2639 struct {
2640 __le16 mac_type;
2641 __u8 mac_addr[ETH_ALEN];
2642 } mbss;
2643 __u8 mac_addr[ETH_ALEN];
2644 };
2645} __attribute__((packed));
2646
a9e00b15
LB		 2647#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
2648#define MWL8K_MAC_TYPE_PRIMARY_AP 2
2649
55489b6e
LB		 2650static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2651{
2652 struct mwl8k_priv *priv = hw->priv;
2653 struct mwl8k_cmd_set_mac_addr *cmd;
2654 int rc;
2655
2656 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2657 if (cmd == NULL)
2658 return -ENOMEM;
2659
2660 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2661 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2662 if (priv->ap_fw) {
a9e00b15 2663 cmd->mbss.mac_type = cpu_to_le16(MWL8K_MAC_TYPE_PRIMARY_AP);
55489b6e
LB		 2664 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2665 } else {
2666 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2667 }
2668
2669 rc = mwl8k_post_cmd(hw, &cmd->header);
2670 kfree(cmd);
2671
2672 return rc;
2673}
2674
2675/*
2676 * CMD_SET_RATEADAPT_MODE.
2677 */
2678struct mwl8k_cmd_set_rate_adapt_mode {
2679 struct mwl8k_cmd_pkt header;
2680 __le16 action;
2681 __le16 mode;
2682} __attribute__((packed));
2683
2684static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2685{
2686 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2687 int rc;
2688
2689 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2690 if (cmd == NULL)
2691 return -ENOMEM;
2692
2693 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2694 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2695 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2696 cmd->mode = cpu_to_le16(mode);
2697
2698 rc = mwl8k_post_cmd(hw, &cmd->header);
2699 kfree(cmd);
2700
2701 return rc;
2702}
2703
b64fe619
LB		 2704/*
2705 * CMD_BSS_START.
2706 */
2707struct mwl8k_cmd_bss_start {
2708 struct mwl8k_cmd_pkt header;
2709 __le32 enable;
2710} __attribute__((packed));
2711
2712static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw, int enable)
2713{
2714 struct mwl8k_cmd_bss_start *cmd;
2715 int rc;
2716
2717 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2718 if (cmd == NULL)
2719 return -ENOMEM;
2720
2721 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
2722 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2723 cmd->enable = cpu_to_le32(enable);
2724
2725 rc = mwl8k_post_cmd(hw, &cmd->header);
2726 kfree(cmd);
2727
2728 return rc;
2729}
2730
3f5610ff
LB		 2731/*
2732 * CMD_SET_NEW_STN.
2733 */
2734struct mwl8k_cmd_set_new_stn {
2735 struct mwl8k_cmd_pkt header;
2736 __le16 aid;
2737 __u8 mac_addr[6];
2738 __le16 stn_id;
2739 __le16 action;
2740 __le16 rsvd;
2741 __le32 legacy_rates;
2742 __u8 ht_rates[4];
2743 __le16 cap_info;
2744 __le16 ht_capabilities_info;
2745 __u8 mac_ht_param_info;
2746 __u8 rev;
2747 __u8 control_channel;
2748 __u8 add_channel;
2749 __le16 op_mode;
2750 __le16 stbc;
2751 __u8 add_qos_info;
2752 __u8 is_qos_sta;
2753 __le32 fw_sta_ptr;
2754} __attribute__((packed));
2755
2756#define MWL8K_STA_ACTION_ADD 0
2757#define MWL8K_STA_ACTION_REMOVE 2
2758
2759static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
2760 struct ieee80211_vif *vif,
2761 struct ieee80211_sta *sta)
2762{
2763 struct mwl8k_cmd_set_new_stn *cmd;
2764 int rc;
2765
2766 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2767 if (cmd == NULL)
2768 return -ENOMEM;
2769
2770 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2771 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2772 cmd->aid = cpu_to_le16(sta->aid);
2773 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
2774 cmd->stn_id = cpu_to_le16(sta->aid);
2775 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
2776 cmd->legacy_rates = cpu_to_le32(sta->supp_rates[IEEE80211_BAND_2GHZ]);
2777 if (sta->ht_cap.ht_supported) {
2778 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
2779 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
2780 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
2781 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
2782 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
2783 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
2784 ((sta->ht_cap.ampdu_density & 7) << 2);
2785 cmd->is_qos_sta = 1;
2786 }
2787
2788 rc = mwl8k_post_cmd(hw, &cmd->header);
2789 kfree(cmd);
2790
2791 return rc;
2792}
2793
b64fe619
LB		 2794static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
2795 struct ieee80211_vif *vif)
2796{
2797 struct mwl8k_cmd_set_new_stn *cmd;
2798 int rc;
2799
2800 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2801 if (cmd == NULL)
2802 return -ENOMEM;
2803
2804 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2805 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2806 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
2807
2808 rc = mwl8k_post_cmd(hw, &cmd->header);
2809 kfree(cmd);
2810
2811 return rc;
2812}
2813
3f5610ff
LB		 2814static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
2815 struct ieee80211_vif *vif, u8 *addr)
2816{
2817 struct mwl8k_cmd_set_new_stn *cmd;
2818 int rc;
2819
2820 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2821 if (cmd == NULL)
2822 return -ENOMEM;
2823
2824 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2825 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2826 memcpy(cmd->mac_addr, addr, ETH_ALEN);
2827 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
2828
2829 rc = mwl8k_post_cmd(hw, &cmd->header);
2830 kfree(cmd);
2831
2832 return rc;
2833}
2834
55489b6e
LB		 2835/*
2836 * CMD_UPDATE_STADB.
2837 */
25d81b1e
LB		 2838struct ewc_ht_info {
2839 __le16 control1;
2840 __le16 control2;
2841 __le16 control3;
2842} __attribute__((packed));
2843
2844struct peer_capability_info {
2845 /* Peer type - AP vs. STA. */
2846 __u8 peer_type;
2847
2848 /* Basic 802.11 capabilities from assoc resp. */
2849 __le16 basic_caps;
2850
2851 /* Set if peer supports 802.11n high throughput (HT). */
2852 __u8 ht_support;
2853
2854 /* Valid if HT is supported. */
2855 __le16 ht_caps;
2856 __u8 extended_ht_caps;
2857 struct ewc_ht_info ewc_info;
2858
2859 /* Legacy rate table. Intersection of our rates and peer rates. */
2860 __u8 legacy_rates[12];
2861
2862 /* HT rate table. Intersection of our rates and peer rates. */
2863 __u8 ht_rates[16];
2864 __u8 pad[16];
2865
2866 /* If set, interoperability mode, no proprietary extensions. */
2867 __u8 interop;
2868 __u8 pad2;
2869 __u8 station_id;
2870 __le16 amsdu_enabled;
2871} __attribute__((packed));
2872
55489b6e
LB		 2873struct mwl8k_cmd_update_stadb {
2874 struct mwl8k_cmd_pkt header;
2875
2876 /* See STADB_ACTION_TYPE */
2877 __le32 action;
2878
2879 /* Peer MAC address */
2880 __u8 peer_addr[ETH_ALEN];
2881
2882 __le32 reserved;
2883
2884 /* Peer info - valid during add/update. */
2885 struct peer_capability_info peer_info;
2886} __attribute__((packed));
2887
a680400e
LB		 2888#define MWL8K_STA_DB_MODIFY_ENTRY 1
2889#define MWL8K_STA_DB_DEL_ENTRY 2
2890
2891/* Peer Entry flags - used to define the type of the peer node */
2892#define MWL8K_PEER_TYPE_ACCESSPOINT 2
2893
2894static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 2895 struct ieee80211_vif *vif,
13935e2c 2896 struct ieee80211_sta *sta)
55489b6e 2897{
55489b6e 2898 struct mwl8k_cmd_update_stadb *cmd;
a680400e 2899 struct peer_capability_info *p;
55489b6e
LB		 2900 int rc;
2901
2902 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2903 if (cmd == NULL)
2904 return -ENOMEM;
2905
2906 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2907 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 2908 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 2909 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 2910
a680400e
LB		 2911 p = &cmd->peer_info;
2912 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2913 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c
LB		 2914 p->ht_support = sta->ht_cap.ht_supported;
2915 p->ht_caps = sta->ht_cap.cap;
2916 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
2917 ((sta->ht_cap.ampdu_density & 7) << 2);
2918 legacy_rate_mask_to_array(p->legacy_rates,
2919 sta->supp_rates[IEEE80211_BAND_2GHZ]);
2920 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB		 2921 p->interop = 1;
2922 p->amsdu_enabled = 0;
2923
2924 rc = mwl8k_post_cmd(hw, &cmd->header);
2925 kfree(cmd);
2926
2927 return rc ? rc : p->station_id;
2928}
2929
2930static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
2931 struct ieee80211_vif *vif, u8 *addr)
2932{
2933 struct mwl8k_cmd_update_stadb *cmd;
2934 int rc;
2935
2936 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2937 if (cmd == NULL)
2938 return -ENOMEM;
2939
2940 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2941 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2942 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 2943 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 2944
a680400e 2945 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 2946 kfree(cmd);
2947
2948 return rc;
2949}
2950
a66098da
LB		 2951
2952/*
2953 * Interrupt handling.
2954 */
2955static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2956{
2957 struct ieee80211_hw *hw = dev_id;
2958 struct mwl8k_priv *priv = hw->priv;
2959 u32 status;
2960
2961 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB		 2962 if (!status)
2963 return IRQ_NONE;
2964
1e9f9de3
LB		 2965 if (status & MWL8K_A2H_INT_TX_DONE) {
2966 status &= ~MWL8K_A2H_INT_TX_DONE;
2967 tasklet_schedule(&priv->poll_tx_task);
2968 }
2969
a66098da 2970 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB		 2971 status &= ~MWL8K_A2H_INT_RX_READY;
2972 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB		 2973 }
2974
67e2eb27
LB		 2975 if (status)
2976 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2977
a66098da 2978 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2979 if (priv->hostcmd_wait != NULL)
a66098da 2980 complete(priv->hostcmd_wait);
a66098da
LB		 2981 }
2982
2983 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2984 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2985 priv->radio_on && priv->pending_tx_pkts)
618952a7 2986 mwl8k_tx_start(priv);
a66098da
LB		 2987 }
2988
2989 return IRQ_HANDLED;
2990}
2991
1e9f9de3
LB		 2992static void mwl8k_tx_poll(unsigned long data)
2993{
2994 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
2995 struct mwl8k_priv *priv = hw->priv;
2996 int limit;
2997 int i;
2998
2999 limit = 32;
3000
3001 spin_lock_bh(&priv->tx_lock);
3002
3003 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3004 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
3005
3006 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
3007 complete(priv->tx_wait);
3008 priv->tx_wait = NULL;
3009 }
3010
3011 spin_unlock_bh(&priv->tx_lock);
3012
3013 if (limit) {
3014 writel(~MWL8K_A2H_INT_TX_DONE,
3015 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3016 } else {
3017 tasklet_schedule(&priv->poll_tx_task);
3018 }
3019}
3020
67e2eb27
LB		 3021static void mwl8k_rx_poll(unsigned long data)
3022{
3023 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3024 struct mwl8k_priv *priv = hw->priv;
3025 int limit;
3026
3027 limit = 32;
3028 limit -= rxq_process(hw, 0, limit);
3029 limit -= rxq_refill(hw, 0, limit);
3030
3031 if (limit) {
3032 writel(~MWL8K_A2H_INT_RX_READY,
3033 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3034 } else {
3035 tasklet_schedule(&priv->poll_rx_task);
3036 }
3037}
3038
a66098da
LB		 3039
3040/*
3041 * Core driver operations.
3042 */
3043static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3044{
3045 struct mwl8k_priv *priv = hw->priv;
3046 int index = skb_get_queue_mapping(skb);
3047 int rc;
3048
9189c100 3049 if (!priv->radio_on) {
a66098da 3050 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 3051 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 3052 dev_kfree_skb(skb);
3053 return NETDEV_TX_OK;
3054 }
3055
3056 rc = mwl8k_txq_xmit(hw, index, skb);
3057
3058 return rc;
3059}
3060
a66098da
LB		 3061static int mwl8k_start(struct ieee80211_hw *hw)
3062{
a66098da
LB		 3063 struct mwl8k_priv *priv = hw->priv;
3064 int rc;
3065
a0607fd3 3066 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3067 IRQF_SHARED, MWL8K_NAME, hw);
3068 if (rc) {
3069 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3070 wiphy_name(hw->wiphy));
2ec610cb 3071 return -EIO;
a66098da
LB		 3072 }
3073
67e2eb27 3074 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 3075 tasklet_enable(&priv->poll_tx_task);
67e2eb27 3076 tasklet_enable(&priv->poll_rx_task);
2ec610cb 3077
a66098da 3078 /* Enable interrupts */
c23b5a69 3079 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 3080
2ec610cb
LB		 3081 rc = mwl8k_fw_lock(hw);
3082 if (!rc) {
55489b6e 3083 rc = mwl8k_cmd_radio_enable(hw);
a66098da 3084
5e4cf166
LB		 3085 if (!priv->ap_fw) {
3086 if (!rc)
55489b6e 3087 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 3088
5e4cf166
LB		 3089 if (!rc)
3090 rc = mwl8k_cmd_set_pre_scan(hw);
3091
3092 if (!rc)
3093 rc = mwl8k_cmd_set_post_scan(hw,
3094 "\x00\x00\x00\x00\x00\x00");
3095 }
2ec610cb
LB		 3096
3097 if (!rc)
55489b6e 3098 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 3099
2ec610cb 3100 if (!rc)
55489b6e 3101 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 3102
2ec610cb
LB		 3103 mwl8k_fw_unlock(hw);
3104 }
3105
3106 if (rc) {
3107 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3108 free_irq(priv->pdev->irq, hw);
1e9f9de3 3109 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3110 tasklet_disable(&priv->poll_rx_task);
2ec610cb 3111 }
a66098da
LB		 3112
3113 return rc;
3114}
3115
a66098da
LB		 3116static void mwl8k_stop(struct ieee80211_hw *hw)
3117{
a66098da
LB		 3118 struct mwl8k_priv *priv = hw->priv;
3119 int i;
3120
55489b6e 3121 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 3122
3123 ieee80211_stop_queues(hw);
3124
a66098da 3125 /* Disable interrupts */
a66098da 3126 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3127 free_irq(priv->pdev->irq, hw);
3128
3129 /* Stop finalize join worker */
3130 cancel_work_sync(&priv->finalize_join_worker);
3131 if (priv->beacon_skb != NULL)
3132 dev_kfree_skb(priv->beacon_skb);
3133
67e2eb27 3134 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 3135 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3136 tasklet_disable(&priv->poll_rx_task);
a66098da 3137
a66098da
LB		 3138 /* Return all skbs to mac80211 */
3139 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 3140 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB		 3141}
3142
3143static int mwl8k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 3144 struct ieee80211_vif *vif)
a66098da
LB		 3145{
3146 struct mwl8k_priv *priv = hw->priv;
3147 struct mwl8k_vif *mwl8k_vif;
3148
3149 /*
3150 * We only support one active interface at a time.
3151 */
3152 if (priv->vif != NULL)
3153 return -EBUSY;
3154
a43c49a8
LB		 3155 /*
3156 * Reject interface creation if sniffer mode is active, as
3157 * STA operation is mutually exclusive with hardware sniffer
b64fe619 3158 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB		 3159 */
3160 if (priv->sniffer_enabled) {
3161 printk(KERN_INFO "%s: unable to create STA "
3162 "interface due to sniffer mode being enabled\n",
3163 wiphy_name(hw->wiphy));
3164 return -EINVAL;
3165 }
3166
c2c2b12a
LB		 3167 /* Set the mac address. */
3168 mwl8k_cmd_set_mac_addr(hw, vif->addr);
3169
b64fe619
LB		 3170 if (priv->ap_fw)
3171 mwl8k_cmd_set_new_stn_add_self(hw, vif);
3172
a66098da 3173 /* Clean out driver private area */
1ed32e4f 3174 mwl8k_vif = MWL8K_VIF(vif);
a66098da
LB		 3175 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
3176
a66098da
LB		 3177 /* Set Initial sequence number to zero */
3178 mwl8k_vif->seqno = 0;
3179
1ed32e4f 3180 priv->vif = vif;
a66098da
LB		 3181
3182 return 0;
3183}
3184
3185static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3186 struct ieee80211_vif *vif)
a66098da
LB		 3187{
3188 struct mwl8k_priv *priv = hw->priv;
3189
b64fe619
LB		 3190 if (priv->ap_fw)
3191 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
3192
55489b6e 3193 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b 3194
a66098da
LB		 3195 priv->vif = NULL;
3196}
3197
ee03a932 3198static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 3199{
a66098da
LB		 3200 struct ieee80211_conf *conf = &hw->conf;
3201 struct mwl8k_priv *priv = hw->priv;
ee03a932 3202 int rc;
a66098da 3203
7595d67a 3204 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 3205 mwl8k_cmd_radio_disable(hw);
ee03a932 3206 return 0;
7595d67a
LB		 3207 }
3208
ee03a932
LB		 3209 rc = mwl8k_fw_lock(hw);
3210 if (rc)
3211 return rc;
a66098da 3212
55489b6e 3213 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 3214 if (rc)
3215 goto out;
a66098da 3216
610677d2 3217 rc = mwl8k_cmd_set_rf_channel(hw, conf);
ee03a932
LB		 3218 if (rc)
3219 goto out;
3220
a66098da
LB		 3221 if (conf->power_level > 18)
3222 conf->power_level = 18;
55489b6e 3223 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
ee03a932
LB		 3224 if (rc)
3225 goto out;
a66098da 3226
08b06347
LB		 3227 if (priv->ap_fw) {
3228 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
3229 if (!rc)
3230 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
3231 } else {
3232 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
3233 }
a66098da 3234
ee03a932
LB		 3235out:
3236 mwl8k_fw_unlock(hw);
a66098da 3237
ee03a932 3238 return rc;
a66098da
LB		 3239}
3240
b64fe619
LB		 3241static void
3242mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3243 struct ieee80211_bss_conf *info, u32 changed)
a66098da 3244{
a66098da 3245 struct mwl8k_priv *priv = hw->priv;
c3cbbe8a 3246 u32 ap_legacy_rates;
13935e2c 3247 u8 ap_mcs_rates[16];
3a980d0a
LB		 3248 int rc;
3249
c3cbbe8a 3250 if (mwl8k_fw_lock(hw))
3a980d0a 3251 return;
a66098da 3252
c3cbbe8a
LB		 3253 /*
3254 * No need to capture a beacon if we're no longer associated.
3255 */
3256 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
3257 priv->capture_beacon = false;
3a980d0a 3258
c3cbbe8a 3259 /*
13935e2c 3260 * Get the AP's legacy and MCS rates.
c3cbbe8a 3261 */
7dc6a7a7 3262 if (vif->bss_conf.assoc) {
c6e96010 3263 struct ieee80211_sta *ap;
c97470dd 3264
c6e96010 3265 rcu_read_lock();
c6e96010 3266
c3cbbe8a
LB		 3267 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
3268 if (ap == NULL) {
3269 rcu_read_unlock();
c6e96010 3270 goto out;
c3cbbe8a
LB		 3271 }
3272
3273 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
13935e2c 3274 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB		 3275
3276 rcu_read_unlock();
3277 }
c6e96010 3278
c3cbbe8a 3279 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
13935e2c 3280 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB		 3281 if (rc)
3282 goto out;
a66098da 3283
b71ed2c6 3284 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB		 3285 if (rc)
3286 goto out;
c3cbbe8a 3287 }
a66098da 3288
c3cbbe8a 3289 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB		 3290 rc = mwl8k_set_radio_preamble(hw,
3291 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 3292 if (rc)
3293 goto out;
c3cbbe8a 3294 }
a66098da 3295
c3cbbe8a 3296 if (changed & BSS_CHANGED_ERP_SLOT) {
7dc6a7a7 3297 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 3298 if (rc)
3299 goto out;
c3cbbe8a 3300 }
a66098da 3301
c97470dd
LB		 3302 if (vif->bss_conf.assoc &&
3303 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
3304 BSS_CHANGED_HT))) {
c3cbbe8a 3305 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB		 3306 if (rc)
3307 goto out;
c3cbbe8a 3308 }
a66098da 3309
c3cbbe8a
LB		 3310 if (vif->bss_conf.assoc &&
3311 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB		 3312 /*
3313 * Finalize the join. Tell rx handler to process
3314 * next beacon from our BSSID.
3315 */
0a11dfc3 3316 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 3317 priv->capture_beacon = true;
a66098da
LB		 3318 }
3319
3a980d0a
LB		 3320out:
3321 mwl8k_fw_unlock(hw);
a66098da
LB		 3322}
3323
b64fe619
LB		 3324static void
3325mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3326 struct ieee80211_bss_conf *info, u32 changed)
3327{
3328 int rc;
3329
3330 if (mwl8k_fw_lock(hw))
3331 return;
3332
3333 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3334 rc = mwl8k_set_radio_preamble(hw,
3335 vif->bss_conf.use_short_preamble);
3336 if (rc)
3337 goto out;
3338 }
3339
3340 if (changed & BSS_CHANGED_BASIC_RATES) {
3341 int idx;
3342 int rate;
3343
3344 /*
3345 * Use lowest supported basic rate for multicasts
3346 * and management frames (such as probe responses --
3347 * beacons will always go out at 1 Mb/s).
3348 */
3349 idx = ffs(vif->bss_conf.basic_rates);
3350 rate = idx ? mwl8k_rates[idx - 1].hw_value : 2;
3351
3352 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
3353 }
3354
3355 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
3356 struct sk_buff *skb;
3357
3358 skb = ieee80211_beacon_get(hw, vif);
3359 if (skb != NULL) {
3360 mwl8k_cmd_set_beacon(hw, skb->data, skb->len);
3361 kfree_skb(skb);
3362 }
3363 }
3364
3365 if (changed & BSS_CHANGED_BEACON_ENABLED)
3366 mwl8k_cmd_bss_start(hw, info->enable_beacon);
3367
3368out:
3369 mwl8k_fw_unlock(hw);
3370}
3371
3372static void
3373mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3374 struct ieee80211_bss_conf *info, u32 changed)
3375{
3376 struct mwl8k_priv *priv = hw->priv;
3377
3378 if (!priv->ap_fw)
3379 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
3380 else
3381 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
3382}
3383
e81cd2d6
LB		 3384static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3385 int mc_count, struct dev_addr_list *mclist)
3386{
3387 struct mwl8k_cmd_pkt *cmd;
3388
447ced07
LB		 3389 /*
3390 * Synthesize and return a command packet that programs the
3391 * hardware multicast address filter. At this point we don't
3392 * know whether FIF_ALLMULTI is being requested, but if it is,
3393 * we'll end up throwing this packet away and creating a new
3394 * one in mwl8k_configure_filter().
3395 */
3396 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 3397
3398 return (unsigned long)cmd;
3399}
3400
a43c49a8
LB		 3401static int
3402mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3403 unsigned int changed_flags,
3404 unsigned int *total_flags)
3405{
3406 struct mwl8k_priv *priv = hw->priv;
3407
3408 /*
3409 * Hardware sniffer mode is mutually exclusive with STA
3410 * operation, so refuse to enable sniffer mode if a STA
3411 * interface is active.
3412 */
3413 if (priv->vif != NULL) {
3414 if (net_ratelimit())
3415 printk(KERN_INFO "%s: not enabling sniffer "
3416 "mode because STA interface is active\n",
3417 wiphy_name(hw->wiphy));
3418 return 0;
3419 }
3420
3421 if (!priv->sniffer_enabled) {
55489b6e 3422 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 3423 return 0;
3424 priv->sniffer_enabled = true;
3425 }
3426
3427 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3428 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3429 FIF_OTHER_BSS;
3430
3431 return 1;
3432}
3433
e6935ea1
LB		 3434static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3435 unsigned int changed_flags,
3436 unsigned int *total_flags,
3437 u64 multicast)
3438{
3439 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3440 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3441
c0adae2c
LB		 3442 /*
3443 * AP firmware doesn't allow fine-grained control over
3444 * the receive filter.
3445 */
3446 if (priv->ap_fw) {
3447 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3448 kfree(cmd);
3449 return;
3450 }
3451
a43c49a8
LB		 3452 /*
3453 * Enable hardware sniffer mode if FIF_CONTROL or
3454 * FIF_OTHER_BSS is requested.
3455 */
3456 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3457 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3458 kfree(cmd);
3459 return;
3460 }
a66098da 3461
e6935ea1 3462 /* Clear unsupported feature flags */
447ced07 3463 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3464
90852f7a
LB		 3465 if (mwl8k_fw_lock(hw)) {
3466 kfree(cmd);
e6935ea1 3467 return;
90852f7a 3468 }
a66098da 3469
a43c49a8 3470 if (priv->sniffer_enabled) {
55489b6e 3471 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 3472 priv->sniffer_enabled = false;
3473 }
3474
e6935ea1 3475 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3476 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3477 /*
3478 * Disable the BSS filter.
3479 */
e6935ea1 3480 mwl8k_cmd_set_pre_scan(hw);
77165d88 3481 } else {
0a11dfc3 3482 const u8 *bssid;
a94cc97e 3483
77165d88
LB		 3484 /*
3485 * Enable the BSS filter.
3486 *
3487 * If there is an active STA interface, use that
3488 * interface's BSSID, otherwise use a dummy one
3489 * (where the OUI part needs to be nonzero for
3490 * the BSSID to be accepted by POST_SCAN).
3491 */
3492 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 3493 if (priv->vif != NULL)
0a11dfc3 3494 bssid = priv->vif->bss_conf.bssid;
a94cc97e 3495
e6935ea1 3496 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3497 }
3498 }
3499
447ced07
LB		 3500 /*
3501 * If FIF_ALLMULTI is being requested, throw away the command
3502 * packet that ->prepare_multicast() built and replace it with
3503 * a command packet that enables reception of all multicast
3504 * packets.
3505 */
3506 if (*total_flags & FIF_ALLMULTI) {
3507 kfree(cmd);
3508 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3509 }
3510
3511 if (cmd != NULL) {
3512 mwl8k_post_cmd(hw, cmd);
3513 kfree(cmd);
e6935ea1 3514 }
a66098da 3515
e6935ea1 3516 mwl8k_fw_unlock(hw);
a66098da
LB		 3517}
3518
a66098da
LB		 3519static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3520{
c2c2b12a 3521 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB		 3522}
3523
bbfd9128
LB		 3524struct mwl8k_sta_notify_item
3525{
3526 struct list_head list;
3527 struct ieee80211_vif *vif;
3528 enum sta_notify_cmd cmd;
13935e2c 3529 struct ieee80211_sta sta;
bbfd9128
LB		 3530};
3531
3f5610ff
LB		 3532static void
3533mwl8k_do_sta_notify(struct ieee80211_hw *hw, struct mwl8k_sta_notify_item *s)
3534{
3535 struct mwl8k_priv *priv = hw->priv;
3536
3537 /*
3538 * STA firmware uses UPDATE_STADB, AP firmware uses SET_NEW_STN.
3539 */
3540 if (!priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
3541 int rc;
3542
3543 rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta);
3544 if (rc >= 0) {
3545 struct ieee80211_sta *sta;
3546
3547 rcu_read_lock();
3548 sta = ieee80211_find_sta(s->vif, s->sta.addr);
3549 if (sta != NULL)
3550 MWL8K_STA(sta)->peer_id = rc;
3551 rcu_read_unlock();
3552 }
3553 } else if (!priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
3554 mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr);
3555 } else if (priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
3556 mwl8k_cmd_set_new_stn_add(hw, s->vif, &s->sta);
3557 } else if (priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
3558 mwl8k_cmd_set_new_stn_del(hw, s->vif, s->sta.addr);
3559 }
3560}
3561
bbfd9128
LB		 3562static void mwl8k_sta_notify_worker(struct work_struct *work)
3563{
3564 struct mwl8k_priv *priv =
3565 container_of(work, struct mwl8k_priv, sta_notify_worker);
a680400e 3566 struct ieee80211_hw *hw = priv->hw;
bbfd9128
LB		 3567
3568 spin_lock_bh(&priv->sta_notify_list_lock);
3569 while (!list_empty(&priv->sta_notify_list)) {
3570 struct mwl8k_sta_notify_item *s;
bbfd9128
LB		 3571
3572 s = list_entry(priv->sta_notify_list.next,
3573 struct mwl8k_sta_notify_item, list);
3574 list_del(&s->list);
3575
3576 spin_unlock_bh(&priv->sta_notify_list_lock);
3577
3f5610ff 3578 mwl8k_do_sta_notify(hw, s);
bbfd9128
LB		 3579 kfree(s);
3580
3581 spin_lock_bh(&priv->sta_notify_list_lock);
3582 }
3583 spin_unlock_bh(&priv->sta_notify_list_lock);
3584}
3585
3586static void
3587mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3588 enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
3589{
3590 struct mwl8k_priv *priv = hw->priv;
3591 struct mwl8k_sta_notify_item *s;
3592
3593 if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
3594 return;
3595
3596 s = kmalloc(sizeof(*s), GFP_ATOMIC);
3597 if (s != NULL) {
3598 s->vif = vif;
3599 s->cmd = cmd;
13935e2c 3600 s->sta = *sta;
bbfd9128
LB		 3601
3602 spin_lock(&priv->sta_notify_list_lock);
3603 list_add_tail(&s->list, &priv->sta_notify_list);
3604 spin_unlock(&priv->sta_notify_list_lock);
3605
3606 ieee80211_queue_work(hw, &priv->sta_notify_worker);
3607 }
3608}
3609
a66098da
LB		 3610static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3611 const struct ieee80211_tx_queue_params *params)
3612{
3e4f542c 3613 struct mwl8k_priv *priv = hw->priv;
a66098da 3614 int rc;
a66098da 3615
3e4f542c
LB		 3616 rc = mwl8k_fw_lock(hw);
3617 if (!rc) {
3618 if (!priv->wmm_enabled)
55489b6e 3619 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 3620
3e4f542c 3621 if (!rc)
55489b6e
LB		 3622 rc = mwl8k_cmd_set_edca_params(hw, queue,
3623 params->cw_min,
3624 params->cw_max,
3625 params->aifs,
3626 params->txop);
3e4f542c
LB		 3627
3628 mwl8k_fw_unlock(hw);
a66098da 3629 }
3e4f542c 3630
a66098da
LB		 3631 return rc;
3632}
3633
3634static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3635 struct ieee80211_tx_queue_stats *stats)
3636{
3637 struct mwl8k_priv *priv = hw->priv;
3638 struct mwl8k_tx_queue *txq;
3639 int index;
3640
3641 spin_lock_bh(&priv->tx_lock);
3642 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3643 txq = priv->txq + index;
45eb400d 3644 memcpy(&stats[index], &txq->stats,
a66098da
LB		 3645 sizeof(struct ieee80211_tx_queue_stats));
3646 }
3647 spin_unlock_bh(&priv->tx_lock);
a66098da 3648
954ef509 3649 return 0;
a66098da
LB		 3650}
3651
3652static int mwl8k_get_stats(struct ieee80211_hw *hw,
3653 struct ieee80211_low_level_stats *stats)
3654{
55489b6e 3655 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 3656}
3657
a2292d83
LB		 3658static int
3659mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3660 enum ieee80211_ampdu_mlme_action action,
3661 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3662{
3663 switch (action) {
3664 case IEEE80211_AMPDU_RX_START:
3665 case IEEE80211_AMPDU_RX_STOP:
3666 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
3667 return -ENOTSUPP;
3668 return 0;
3669 default:
3670 return -ENOTSUPP;
3671 }
3672}
3673
a66098da
LB		 3674static const struct ieee80211_ops mwl8k_ops = {
3675 .tx = mwl8k_tx,
3676 .start = mwl8k_start,
3677 .stop = mwl8k_stop,
3678 .add_interface = mwl8k_add_interface,
3679 .remove_interface = mwl8k_remove_interface,
3680 .config = mwl8k_config,
a66098da 3681 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3682 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3683 .configure_filter = mwl8k_configure_filter,
3684 .set_rts_threshold = mwl8k_set_rts_threshold,
bbfd9128 3685 .sta_notify = mwl8k_sta_notify,
a66098da
LB		 3686 .conf_tx = mwl8k_conf_tx,
3687 .get_tx_stats = mwl8k_get_tx_stats,
3688 .get_stats = mwl8k_get_stats,
a2292d83 3689 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB		 3690};
3691
a66098da
LB		 3692static void mwl8k_finalize_join_worker(struct work_struct *work)
3693{
3694 struct mwl8k_priv *priv =
3695 container_of(work, struct mwl8k_priv, finalize_join_worker);
3696 struct sk_buff *skb = priv->beacon_skb;
a66098da 3697
7dc6a7a7
LB		 3698 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
3699 priv->vif->bss_conf.dtim_period);
a66098da
LB		 3700 dev_kfree_skb(skb);
3701
3702 priv->beacon_skb = NULL;
3703}
3704
bcb628d5 3705enum {
9e1b17ea
LB		 3706 MWL8363 = 0,
3707 MWL8687,
bcb628d5 3708 MWL8366,
6f6d1e9a
LB		 3709};
3710
bcb628d5 3711static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
9e1b17ea
LB		 3712 [MWL8363] = {
3713 .part_name = "88w8363",
3714 .helper_image = "mwl8k/helper_8363.fw",
3715 .fw_image = "mwl8k/fmimage_8363.fw",
3716 },
49eb691c 3717 [MWL8687] = {
bcb628d5
JL		 3718 .part_name = "88w8687",
3719 .helper_image = "mwl8k/helper_8687.fw",
3720 .fw_image = "mwl8k/fmimage_8687.fw",
bcb628d5 3721 },
49eb691c 3722 [MWL8366] = {
bcb628d5
JL		 3723 .part_name = "88w8366",
3724 .helper_image = "mwl8k/helper_8366.fw",
3725 .fw_image = "mwl8k/fmimage_8366.fw",
89a91f4f 3726 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 3727 },
45a390dd
LB		 3728};
3729
c92d4ede
LB		 3730MODULE_FIRMWARE("mwl8k/helper_8363.fw");
3731MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
3732MODULE_FIRMWARE("mwl8k/helper_8687.fw");
3733MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
3734MODULE_FIRMWARE("mwl8k/helper_8366.fw");
3735MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
3736
45a390dd 3737static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
9e1b17ea
LB		 3738 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
3739 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL		 3740 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3741 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3742 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3743 { },
45a390dd
LB		 3744};
3745MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3746
a66098da
LB		 3747static int __devinit mwl8k_probe(struct pci_dev *pdev,
3748 const struct pci_device_id *id)
3749{
2aa7b01f 3750 static int printed_version = 0;
a66098da
LB		 3751 struct ieee80211_hw *hw;
3752 struct mwl8k_priv *priv;
a66098da
LB		 3753 int rc;
3754 int i;
2aa7b01f
LB		 3755
3756 if (!printed_version) {
3757 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3758 printed_version = 1;
3759 }
a66098da 3760
be695fc4 3761
a66098da
LB		 3762 rc = pci_enable_device(pdev);
3763 if (rc) {
3764 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3765 MWL8K_NAME);
3766 return rc;
3767 }
3768
3769 rc = pci_request_regions(pdev, MWL8K_NAME);
3770 if (rc) {
3771 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3772 MWL8K_NAME);
3db95e50 3773 goto err_disable_device;
a66098da
LB		 3774 }
3775
3776 pci_set_master(pdev);
3777
be695fc4 3778
a66098da
LB		 3779 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3780 if (hw == NULL) {
3781 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3782 rc = -ENOMEM;
3783 goto err_free_reg;
3784 }
3785
be695fc4
LB		 3786 SET_IEEE80211_DEV(hw, &pdev->dev);
3787 pci_set_drvdata(pdev, hw);
3788
a66098da
LB		 3789 priv = hw->priv;
3790 priv->hw = hw;
3791 priv->pdev = pdev;
bcb628d5 3792 priv->device_info = &mwl8k_info_tbl[id->driver_data];
a66098da 3793
a66098da 3794
5b9482dd
LB		 3795 priv->sram = pci_iomap(pdev, 0, 0x10000);
3796 if (priv->sram == NULL) {
3797 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3798 wiphy_name(hw->wiphy));
a66098da
LB		 3799 goto err_iounmap;
3800 }
3801
5b9482dd
LB		 3802 /*
3803 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3804 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3805 */
3806 priv->regs = pci_iomap(pdev, 1, 0x10000);
3807 if (priv->regs == NULL) {
3808 priv->regs = pci_iomap(pdev, 2, 0x10000);
3809 if (priv->regs == NULL) {
3810 printk(KERN_ERR "%s: Cannot map device registers\n",
3811 wiphy_name(hw->wiphy));
3812 goto err_iounmap;
3813 }
3814 }
3815
be695fc4
LB		 3816
3817 /* Reset firmware and hardware */
3818 mwl8k_hw_reset(priv);
3819
3820 /* Ask userland hotplug daemon for the device firmware */
3821 rc = mwl8k_request_firmware(priv);
3822 if (rc) {
3823 printk(KERN_ERR "%s: Firmware files not found\n",
3824 wiphy_name(hw->wiphy));
3825 goto err_stop_firmware;
3826 }
3827
3828 /* Load firmware into hardware */
3829 rc = mwl8k_load_firmware(hw);
3830 if (rc) {
3831 printk(KERN_ERR "%s: Cannot start firmware\n",
3832 wiphy_name(hw->wiphy));
3833 goto err_stop_firmware;
3834 }
3835
3836 /* Reclaim memory once firmware is successfully loaded */
3837 mwl8k_release_firmware(priv);
3838
3839
91942230 3840 if (priv->ap_fw) {
89a91f4f 3841 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230
LB		 3842 if (priv->rxd_ops == NULL) {
3843 printk(KERN_ERR "%s: Driver does not have AP "
3844 "firmware image support for this hardware\n",
3845 wiphy_name(hw->wiphy));
3846 goto err_stop_firmware;
3847 }
3848 } else {
89a91f4f 3849 priv->rxd_ops = &rxd_sta_ops;
91942230 3850 }
be695fc4
LB		 3851
3852 priv->sniffer_enabled = false;
3853 priv->wmm_enabled = false;
3854 priv->pending_tx_pkts = 0;
3855
3856
a66098da
LB		 3857 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3858 priv->band.band = IEEE80211_BAND_2GHZ;
3859 priv->band.channels = priv->channels;
3860 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3861 priv->band.bitrates = priv->rates;
3862 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3863 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3864
3865 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3866 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3867
3868 /*
3869 * Extra headroom is the size of the required DMA header
3870 * minus the size of the smallest 802.11 frame (CTS frame).
3871 */
3872 hw->extra_tx_headroom =
3873 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3874
3875 hw->channel_change_time = 10;
3876
3877 hw->queues = MWL8K_TX_QUEUES;
3878
a66098da 3879 /* Set rssi and noise values to dBm */
ce9e2e1b 3880 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da 3881 hw->vif_data_size = sizeof(struct mwl8k_vif);
a680400e 3882 hw->sta_data_size = sizeof(struct mwl8k_sta);
a66098da
LB		 3883 priv->vif = NULL;
3884
3885 /* Set default radio state and preamble */
c46563b7 3886 priv->radio_on = 0;
68ce3884 3887 priv->radio_short_preamble = 0;
a66098da 3888
bbfd9128
LB		 3889 /* Station database handling */
3890 INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
3891 spin_lock_init(&priv->sta_notify_list_lock);
3892 INIT_LIST_HEAD(&priv->sta_notify_list);
3893
a66098da
LB		 3894 /* Finalize join worker */
3895 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3896
67e2eb27 3897 /* TX reclaim and RX tasklets. */
1e9f9de3
LB		 3898 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
3899 tasklet_disable(&priv->poll_tx_task);
67e2eb27
LB		 3900 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
3901 tasklet_disable(&priv->poll_rx_task);
a66098da 3902
a66098da
LB		 3903 /* Power management cookie */
3904 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3905 if (priv->cookie == NULL)
be695fc4 3906 goto err_stop_firmware;
a66098da
LB		 3907
3908 rc = mwl8k_rxq_init(hw, 0);
3909 if (rc)
be695fc4 3910 goto err_free_cookie;
a66098da
LB		 3911 rxq_refill(hw, 0, INT_MAX);
3912
618952a7
LB		 3913 mutex_init(&priv->fw_mutex);
3914 priv->fw_mutex_owner = NULL;
3915 priv->fw_mutex_depth = 0;
618952a7
LB		 3916 priv->hostcmd_wait = NULL;
3917
a66098da
LB		 3918 spin_lock_init(&priv->tx_lock);
3919
88de754a
LB		 3920 priv->tx_wait = NULL;
3921
a66098da
LB		 3922 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3923 rc = mwl8k_txq_init(hw, i);
3924 if (rc)
3925 goto err_free_queues;
3926 }
3927
3928 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3929 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
67e2eb27 3930 iowrite32(MWL8K_A2H_INT_TX_DONE | MWL8K_A2H_INT_RX_READY,
1e9f9de3 3931 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
a66098da
LB		 3932 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3933
a0607fd3 3934 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3935 IRQF_SHARED, MWL8K_NAME, hw);
3936 if (rc) {
3937 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3938 wiphy_name(hw->wiphy));
a66098da
LB		 3939 goto err_free_queues;
3940 }
3941
a66098da
LB		 3942 /*
3943 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 3944 * commands use interrupts and avoid polling. Disable
a66098da
LB		 3945 * interrupts when done.
3946 */
c23b5a69 3947 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3948
3949 /* Get config data, mac addrs etc */
42fba21d
LB		 3950 if (priv->ap_fw) {
3951 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3952 if (!rc)
3953 rc = mwl8k_cmd_set_hw_spec(hw);
b64fe619
LB		 3954
3955 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_AP);
42fba21d
LB		 3956 } else {
3957 rc = mwl8k_cmd_get_hw_spec_sta(hw);
89a91f4f
LB		 3958
3959 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
42fba21d 3960 }
a66098da 3961 if (rc) {
c2c357ce
LB		 3962 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3963 wiphy_name(hw->wiphy));
be695fc4 3964 goto err_free_irq;
a66098da
LB		 3965 }
3966
3967 /* Turn radio off */
55489b6e 3968 rc = mwl8k_cmd_radio_disable(hw);
a66098da 3969 if (rc) {
c2c357ce 3970 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
be695fc4 3971 goto err_free_irq;
a66098da
LB		 3972 }
3973
32060e1b 3974 /* Clear MAC address */
55489b6e 3975 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b
LB		 3976 if (rc) {
3977 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3978 wiphy_name(hw->wiphy));
be695fc4 3979 goto err_free_irq;
32060e1b
LB		 3980 }
3981
a66098da 3982 /* Disable interrupts */
a66098da 3983 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3984 free_irq(priv->pdev->irq, hw);
3985
3986 rc = ieee80211_register_hw(hw);
3987 if (rc) {
c2c357ce
LB		 3988 printk(KERN_ERR "%s: Cannot register device\n",
3989 wiphy_name(hw->wiphy));
153458ff 3990 goto err_free_queues;
a66098da
LB		 3991 }
3992
eae74e65 3993 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3994 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3995 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3996 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 3997 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3998 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3999
4000 return 0;
4001
a66098da 4002err_free_irq:
a66098da 4003 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4004 free_irq(priv->pdev->irq, hw);
4005
4006err_free_queues:
4007 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4008 mwl8k_txq_deinit(hw, i);
4009 mwl8k_rxq_deinit(hw, 0);
4010
be695fc4 4011err_free_cookie:
a66098da
LB		 4012 if (priv->cookie != NULL)
4013 pci_free_consistent(priv->pdev, 4,
4014 priv->cookie, priv->cookie_dma);
4015
be695fc4
LB		 4016err_stop_firmware:
4017 mwl8k_hw_reset(priv);
4018 mwl8k_release_firmware(priv);
4019
4020err_iounmap:
a66098da
LB		 4021 if (priv->regs != NULL)
4022 pci_iounmap(pdev, priv->regs);
4023
5b9482dd
LB		 4024 if (priv->sram != NULL)
4025 pci_iounmap(pdev, priv->sram);
4026
a66098da
LB		 4027 pci_set_drvdata(pdev, NULL);
4028 ieee80211_free_hw(hw);
4029
4030err_free_reg:
4031 pci_release_regions(pdev);
3db95e50
LB		 4032
4033err_disable_device:
a66098da
LB		 4034 pci_disable_device(pdev);
4035
4036 return rc;
4037}
4038
230f7af0 4039static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 4040{
4041 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
4042}
4043
230f7af0 4044static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 4045{
4046 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
4047 struct mwl8k_priv *priv;
4048 int i;
4049
4050 if (hw == NULL)
4051 return;
4052 priv = hw->priv;
4053
4054 ieee80211_stop_queues(hw);
4055
60aa569f
LB		 4056 ieee80211_unregister_hw(hw);
4057
67e2eb27 4058 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 4059 tasklet_kill(&priv->poll_tx_task);
67e2eb27 4060 tasklet_kill(&priv->poll_rx_task);
a66098da 4061
a66098da
LB		 4062 /* Stop hardware */
4063 mwl8k_hw_reset(priv);
4064
4065 /* Return all skbs to mac80211 */
4066 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 4067 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 4068
a66098da
LB		 4069 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4070 mwl8k_txq_deinit(hw, i);
4071
4072 mwl8k_rxq_deinit(hw, 0);
4073
c2c357ce 4074 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 4075
4076 pci_iounmap(pdev, priv->regs);
5b9482dd 4077 pci_iounmap(pdev, priv->sram);
a66098da
LB		 4078 pci_set_drvdata(pdev, NULL);
4079 ieee80211_free_hw(hw);
4080 pci_release_regions(pdev);
4081 pci_disable_device(pdev);
4082}
4083
4084static struct pci_driver mwl8k_driver = {
4085 .name = MWL8K_NAME,
45a390dd 4086 .id_table = mwl8k_pci_id_table,
a66098da
LB		 4087 .probe = mwl8k_probe,
4088 .remove = __devexit_p(mwl8k_remove),
4089 .shutdown = __devexit_p(mwl8k_shutdown),
4090};
4091
4092static int __init mwl8k_init(void)
4093{
4094 return pci_register_driver(&mwl8k_driver);
4095}
4096
4097static void __exit mwl8k_exit(void)
4098{
4099 pci_unregister_driver(&mwl8k_driver);
4100}
4101
4102module_init(mwl8k_init);
4103module_exit(mwl8k_exit);
c2c357ce
LB		 4104
4105MODULE_DESCRIPTION(MWL8K_DESC);
4106MODULE_VERSION(MWL8K_VERSION);
4107MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
4108MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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