mwl8k: rename 2.4 GHz band/channels/rates related variables from FOO to FOO_24
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
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2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
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6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
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16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
6976b665 29#define MWL8K_VERSION "0.11"
a66098da 30
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31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
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33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
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36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
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39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
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47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
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51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
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58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
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68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
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80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
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83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
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87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
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89};
90
45a390dd 91struct mwl8k_device_info {
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92 char *part_name;
93 char *helper_image;
94 char *fw_image;
89a91f4f 95 struct rxd_ops *ap_rxd_ops;
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96};
97
a66098da 98struct mwl8k_rx_queue {
45eb400d 99 int rxd_count;
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100
101 /* hw receives here */
45eb400d 102 int head;
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103
104 /* refill descs here */
45eb400d 105 int tail;
a66098da 106
54bc3a0d 107 void *rxd;
45eb400d 108 dma_addr_t rxd_dma;
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109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
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113};
114
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115struct mwl8k_tx_queue {
116 /* hw transmits here */
45eb400d 117 int head;
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118
119 /* sw appends here */
45eb400d 120 int tail;
a66098da 121
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122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
124 dma_addr_t txd_dma;
125 struct sk_buff **skb;
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126};
127
a66098da 128struct mwl8k_priv {
a66098da 129 struct ieee80211_hw *hw;
a66098da 130 struct pci_dev *pdev;
a66098da 131
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132 struct mwl8k_device_info *device_info;
133
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134 void __iomem *sram;
135 void __iomem *regs;
136
137 /* firmware */
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138 struct firmware *fw_helper;
139 struct firmware *fw_ucode;
a66098da 140
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141 /* hardware/firmware parameters */
142 bool ap_fw;
143 struct rxd_ops *rxd_ops;
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144 struct ieee80211_supported_band band_24;
145 struct ieee80211_channel channels_24[14];
146 struct ieee80211_rate rates_24[14];
be695fc4 147
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148 /* firmware access */
149 struct mutex fw_mutex;
150 struct task_struct *fw_mutex_owner;
151 int fw_mutex_depth;
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152 struct completion *hostcmd_wait;
153
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154 /* lock held over TX and TX reap */
155 spinlock_t tx_lock;
a66098da 156
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157 /* TX quiesce completion, protected by fw_mutex and tx_lock */
158 struct completion *tx_wait;
159
a66098da 160 struct ieee80211_vif *vif;
a66098da 161
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162 /* power management status cookie from firmware */
163 u32 *cookie;
164 dma_addr_t cookie_dma;
165
166 u16 num_mcaddrs;
a66098da 167 u8 hw_rev;
2aa7b01f 168 u32 fw_rev;
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169
170 /*
171 * Running count of TX packets in flight, to avoid
172 * iterating over the transmit rings each time.
173 */
174 int pending_tx_pkts;
175
176 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
177 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
178
c46563b7 179 bool radio_on;
68ce3884 180 bool radio_short_preamble;
a43c49a8 181 bool sniffer_enabled;
0439b1f5 182 bool wmm_enabled;
a66098da 183
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184 struct work_struct sta_notify_worker;
185 spinlock_t sta_notify_list_lock;
186 struct list_head sta_notify_list;
187
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188 /* XXX need to convert this to handle multiple interfaces */
189 bool capture_beacon;
d89173f2 190 u8 capture_bssid[ETH_ALEN];
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191 struct sk_buff *beacon_skb;
192
193 /*
194 * This FJ worker has to be global as it is scheduled from the
195 * RX handler. At this point we don't know which interface it
196 * belongs to until the list of bssids waiting to complete join
197 * is checked.
198 */
199 struct work_struct finalize_join_worker;
200
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201 /* Tasklet to perform TX reclaim. */
202 struct tasklet_struct poll_tx_task;
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203
204 /* Tasklet to perform RX. */
205 struct tasklet_struct poll_rx_task;
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206};
207
208/* Per interface specific private data */
209struct mwl8k_vif {
c2c2b12a 210 /* Non AMPDU sequence number assigned by driver. */
a680400e 211 u16 seqno;
a66098da 212};
a94cc97e 213#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da 214
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215struct mwl8k_sta {
216 /* Index into station database. Returned by UPDATE_STADB. */
217 u8 peer_id;
218};
219#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
220
777ad375 221static const struct ieee80211_channel mwl8k_channels_24[] = {
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222 { .center_freq = 2412, .hw_value = 1, },
223 { .center_freq = 2417, .hw_value = 2, },
224 { .center_freq = 2422, .hw_value = 3, },
225 { .center_freq = 2427, .hw_value = 4, },
226 { .center_freq = 2432, .hw_value = 5, },
227 { .center_freq = 2437, .hw_value = 6, },
228 { .center_freq = 2442, .hw_value = 7, },
229 { .center_freq = 2447, .hw_value = 8, },
230 { .center_freq = 2452, .hw_value = 9, },
231 { .center_freq = 2457, .hw_value = 10, },
232 { .center_freq = 2462, .hw_value = 11, },
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233 { .center_freq = 2467, .hw_value = 12, },
234 { .center_freq = 2472, .hw_value = 13, },
235 { .center_freq = 2484, .hw_value = 14, },
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236};
237
777ad375 238static const struct ieee80211_rate mwl8k_rates_24[] = {
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239 { .bitrate = 10, .hw_value = 2, },
240 { .bitrate = 20, .hw_value = 4, },
241 { .bitrate = 55, .hw_value = 11, },
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242 { .bitrate = 110, .hw_value = 22, },
243 { .bitrate = 220, .hw_value = 44, },
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244 { .bitrate = 60, .hw_value = 12, },
245 { .bitrate = 90, .hw_value = 18, },
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246 { .bitrate = 120, .hw_value = 24, },
247 { .bitrate = 180, .hw_value = 36, },
248 { .bitrate = 240, .hw_value = 48, },
249 { .bitrate = 360, .hw_value = 72, },
250 { .bitrate = 480, .hw_value = 96, },
251 { .bitrate = 540, .hw_value = 108, },
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252 { .bitrate = 720, .hw_value = 144, },
253};
254
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255/* Set or get info from Firmware */
256#define MWL8K_CMD_SET 0x0001
257#define MWL8K_CMD_GET 0x0000
258
259/* Firmware command codes */
260#define MWL8K_CMD_CODE_DNLD 0x0001
261#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 262#define MWL8K_CMD_SET_HW_SPEC 0x0004
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263#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
264#define MWL8K_CMD_GET_STAT 0x0014
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265#define MWL8K_CMD_RADIO_CONTROL 0x001c
266#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 267#define MWL8K_CMD_RF_ANTENNA 0x0020
b64fe619 268#define MWL8K_CMD_SET_BEACON 0x0100
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269#define MWL8K_CMD_SET_PRE_SCAN 0x0107
270#define MWL8K_CMD_SET_POST_SCAN 0x0108
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271#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
272#define MWL8K_CMD_SET_AID 0x010d
273#define MWL8K_CMD_SET_RATE 0x0110
274#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
275#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 276#define MWL8K_CMD_SET_SLOT 0x0114
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277#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
278#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 279#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 280#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 281#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 282#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 283#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
b64fe619 284#define MWL8K_CMD_BSS_START 0x1100
3f5610ff 285#define MWL8K_CMD_SET_NEW_STN 0x1111
ff45fc60 286#define MWL8K_CMD_UPDATE_STADB 0x1123
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287
288static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
289{
290#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
291 snprintf(buf, bufsize, "%s", #x);\
292 return buf;\
293 } while (0)
ce9e2e1b 294 switch (cmd & ~0x8000) {
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295 MWL8K_CMDNAME(CODE_DNLD);
296 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 297 MWL8K_CMDNAME(SET_HW_SPEC);
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298 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
299 MWL8K_CMDNAME(GET_STAT);
300 MWL8K_CMDNAME(RADIO_CONTROL);
301 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 302 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 303 MWL8K_CMDNAME(SET_BEACON);
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304 MWL8K_CMDNAME(SET_PRE_SCAN);
305 MWL8K_CMDNAME(SET_POST_SCAN);
306 MWL8K_CMDNAME(SET_RF_CHANNEL);
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LB
307 MWL8K_CMDNAME(SET_AID);
308 MWL8K_CMDNAME(SET_RATE);
309 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
310 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 311 MWL8K_CMDNAME(SET_SLOT);
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312 MWL8K_CMDNAME(SET_EDCA_PARAMS);
313 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 314 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 315 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 316 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 317 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 318 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 319 MWL8K_CMDNAME(BSS_START);
3f5610ff 320 MWL8K_CMDNAME(SET_NEW_STN);
ff45fc60 321 MWL8K_CMDNAME(UPDATE_STADB);
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322 default:
323 snprintf(buf, bufsize, "0x%x", cmd);
324 }
325#undef MWL8K_CMDNAME
326
327 return buf;
328}
329
330/* Hardware and firmware reset */
331static void mwl8k_hw_reset(struct mwl8k_priv *priv)
332{
333 iowrite32(MWL8K_H2A_INT_RESET,
334 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
335 iowrite32(MWL8K_H2A_INT_RESET,
336 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
337 msleep(20);
338}
339
340/* Release fw image */
341static void mwl8k_release_fw(struct firmware **fw)
342{
343 if (*fw == NULL)
344 return;
345 release_firmware(*fw);
346 *fw = NULL;
347}
348
349static void mwl8k_release_firmware(struct mwl8k_priv *priv)
350{
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351 mwl8k_release_fw(&priv->fw_ucode);
352 mwl8k_release_fw(&priv->fw_helper);
a66098da
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353}
354
355/* Request fw image */
356static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 357 const char *fname, struct firmware **fw)
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LB
358{
359 /* release current image */
360 if (*fw != NULL)
361 mwl8k_release_fw(fw);
362
363 return request_firmware((const struct firmware **)fw,
c2c357ce 364 fname, &priv->pdev->dev);
a66098da
LB
365}
366
45a390dd 367static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 368{
a74b295e 369 struct mwl8k_device_info *di = priv->device_info;
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370 int rc;
371
a74b295e 372 if (di->helper_image != NULL) {
22be40d9 373 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
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374 if (rc) {
375 printk(KERN_ERR "%s: Error requesting helper "
376 "firmware file %s\n", pci_name(priv->pdev),
377 di->helper_image);
378 return rc;
379 }
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380 }
381
22be40d9 382 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
a66098da 383 if (rc) {
c2c357ce 384 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 385 pci_name(priv->pdev), di->fw_image);
22be40d9 386 mwl8k_release_fw(&priv->fw_helper);
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387 return rc;
388 }
389
390 return 0;
391}
392
393struct mwl8k_cmd_pkt {
394 __le16 code;
395 __le16 length;
396 __le16 seq_num;
397 __le16 result;
398 char payload[0];
399} __attribute__((packed));
400
401/*
402 * Firmware loading.
403 */
404static int
405mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
406{
407 void __iomem *regs = priv->regs;
408 dma_addr_t dma_addr;
a66098da
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409 int loops;
410
411 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
412 if (pci_dma_mapping_error(priv->pdev, dma_addr))
413 return -ENOMEM;
414
415 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
416 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
417 iowrite32(MWL8K_H2A_INT_DOORBELL,
418 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
419 iowrite32(MWL8K_H2A_INT_DUMMY,
420 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
421
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422 loops = 1000;
423 do {
424 u32 int_code;
425
426 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
427 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
428 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
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429 break;
430 }
431
3d76e82c 432 cond_resched();
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433 udelay(1);
434 } while (--loops);
435
436 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
437
d4b70570 438 return loops ? 0 : -ETIMEDOUT;
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439}
440
441static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
442 const u8 *data, size_t length)
443{
444 struct mwl8k_cmd_pkt *cmd;
445 int done;
446 int rc = 0;
447
448 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
449 if (cmd == NULL)
450 return -ENOMEM;
451
452 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
453 cmd->seq_num = 0;
454 cmd->result = 0;
455
456 done = 0;
457 while (length) {
458 int block_size = length > 256 ? 256 : length;
459
460 memcpy(cmd->payload, data + done, block_size);
461 cmd->length = cpu_to_le16(block_size);
462
463 rc = mwl8k_send_fw_load_cmd(priv, cmd,
464 sizeof(*cmd) + block_size);
465 if (rc)
466 break;
467
468 done += block_size;
469 length -= block_size;
470 }
471
472 if (!rc) {
473 cmd->length = 0;
474 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
475 }
476
477 kfree(cmd);
478
479 return rc;
480}
481
482static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
483 const u8 *data, size_t length)
484{
485 unsigned char *buffer;
486 int may_continue, rc = 0;
487 u32 done, prev_block_size;
488
489 buffer = kmalloc(1024, GFP_KERNEL);
490 if (buffer == NULL)
491 return -ENOMEM;
492
493 done = 0;
494 prev_block_size = 0;
495 may_continue = 1000;
496 while (may_continue > 0) {
497 u32 block_size;
498
499 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
500 if (block_size & 1) {
501 block_size &= ~1;
502 may_continue--;
503 } else {
504 done += prev_block_size;
505 length -= prev_block_size;
506 }
507
508 if (block_size > 1024 || block_size > length) {
509 rc = -EOVERFLOW;
510 break;
511 }
512
513 if (length == 0) {
514 rc = 0;
515 break;
516 }
517
518 if (block_size == 0) {
519 rc = -EPROTO;
520 may_continue--;
521 udelay(1);
522 continue;
523 }
524
525 prev_block_size = block_size;
526 memcpy(buffer, data + done, block_size);
527
528 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
529 if (rc)
530 break;
531 }
532
533 if (!rc && length != 0)
534 rc = -EREMOTEIO;
535
536 kfree(buffer);
537
538 return rc;
539}
540
c2c357ce 541static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 542{
c2c357ce 543 struct mwl8k_priv *priv = hw->priv;
22be40d9 544 struct firmware *fw = priv->fw_ucode;
c2c357ce
LB
545 int rc;
546 int loops;
547
548 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
22be40d9 549 struct firmware *helper = priv->fw_helper;
a66098da 550
c2c357ce
LB
551 if (helper == NULL) {
552 printk(KERN_ERR "%s: helper image needed but none "
553 "given\n", pci_name(priv->pdev));
554 return -EINVAL;
555 }
a66098da 556
c2c357ce 557 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB
558 if (rc) {
559 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 560 "helper image\n", pci_name(priv->pdev));
a66098da
LB
561 return rc;
562 }
89b872e2 563 msleep(5);
a66098da 564
c2c357ce 565 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 566 } else {
c2c357ce 567 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB
568 }
569
570 if (rc) {
c2c357ce
LB
571 printk(KERN_ERR "%s: unable to load firmware image\n",
572 pci_name(priv->pdev));
a66098da
LB
573 return rc;
574 }
575
89a91f4f 576 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 577
89b872e2 578 loops = 500000;
a66098da 579 do {
eae74e65
LB
580 u32 ready_code;
581
582 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
583 if (ready_code == MWL8K_FWAP_READY) {
584 priv->ap_fw = 1;
585 break;
586 } else if (ready_code == MWL8K_FWSTA_READY) {
587 priv->ap_fw = 0;
a66098da 588 break;
eae74e65
LB
589 }
590
591 cond_resched();
a66098da
LB
592 udelay(1);
593 } while (--loops);
594
595 return loops ? 0 : -ETIMEDOUT;
596}
597
598
a66098da
LB
599/* DMA header used by firmware and hardware. */
600struct mwl8k_dma_data {
601 __le16 fwlen;
602 struct ieee80211_hdr wh;
20f09c3d 603 char data[0];
a66098da
LB
604} __attribute__((packed));
605
606/* Routines to add/remove DMA header from skb. */
20f09c3d 607static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 608{
20f09c3d
LB
609 struct mwl8k_dma_data *tr;
610 int hdrlen;
611
612 tr = (struct mwl8k_dma_data *)skb->data;
613 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
614
615 if (hdrlen != sizeof(tr->wh)) {
616 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
617 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
618 *((__le16 *)(tr->data - 2)) = qos;
619 } else {
620 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
621 }
a66098da 622 }
20f09c3d
LB
623
624 if (hdrlen != sizeof(*tr))
625 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB
626}
627
76266b2a 628static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB
629{
630 struct ieee80211_hdr *wh;
ca009301 631 int hdrlen;
a66098da
LB
632 struct mwl8k_dma_data *tr;
633
ca009301
LB
634 /*
635 * Add a firmware DMA header; the firmware requires that we
636 * present a 2-byte payload length followed by a 4-address
637 * header (without QoS field), followed (optionally) by any
638 * WEP/ExtIV header (but only filled in for CCMP).
639 */
a66098da 640 wh = (struct ieee80211_hdr *)skb->data;
ca009301 641
a66098da 642 hdrlen = ieee80211_hdrlen(wh->frame_control);
ca009301
LB
643 if (hdrlen != sizeof(*tr))
644 skb_push(skb, sizeof(*tr) - hdrlen);
a66098da 645
ca009301
LB
646 if (ieee80211_is_data_qos(wh->frame_control))
647 hdrlen -= 2;
a66098da
LB
648
649 tr = (struct mwl8k_dma_data *)skb->data;
650 if (wh != &tr->wh)
651 memmove(&tr->wh, wh, hdrlen);
ca009301
LB
652 if (hdrlen != sizeof(tr->wh))
653 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB
654
655 /*
656 * Firmware length is the length of the fully formed "802.11
657 * payload". That is, everything except for the 802.11 header.
658 * This includes all crypto material including the MIC.
659 */
ca009301 660 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
a66098da
LB
661}
662
663
664/*
89a91f4f 665 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 666 */
89a91f4f 667struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB
668 __le16 pkt_len;
669 __u8 sq2;
670 __u8 rate;
671 __le32 pkt_phys_addr;
672 __le32 next_rxd_phys_addr;
673 __le16 qos_control;
674 __le16 htsig2;
675 __le32 hw_rssi_info;
676 __le32 hw_noise_floor_info;
677 __u8 noise_floor;
678 __u8 pad0[3];
679 __u8 rssi;
680 __u8 rx_status;
681 __u8 channel;
682 __u8 rx_ctrl;
683} __attribute__((packed));
684
89a91f4f
LB
685#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
686#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
687#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 688
89a91f4f 689#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 690
89a91f4f 691static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 692{
89a91f4f 693 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB
694
695 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 696 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB
697}
698
89a91f4f 699static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 700{
89a91f4f 701 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB
702
703 rxd->pkt_len = cpu_to_le16(len);
704 rxd->pkt_phys_addr = cpu_to_le32(addr);
705 wmb();
706 rxd->rx_ctrl = 0;
707}
708
709static int
89a91f4f
LB
710mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
711 __le16 *qos)
6f6d1e9a 712{
89a91f4f 713 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 714
89a91f4f 715 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB
716 return -1;
717 rmb();
718
719 memset(status, 0, sizeof(*status));
720
721 status->signal = -rxd->rssi;
722 status->noise = -rxd->noise_floor;
723
89a91f4f 724 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 725 status->flag |= RX_FLAG_HT;
89a91f4f 726 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 727 status->flag |= RX_FLAG_40MHZ;
89a91f4f 728 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB
729 } else {
730 int i;
731
777ad375
LB
732 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
733 if (mwl8k_rates_24[i].hw_value == rxd->rate) {
6f6d1e9a
LB
734 status->rate_idx = i;
735 break;
736 }
737 }
738 }
739
740 status->band = IEEE80211_BAND_2GHZ;
741 status->freq = ieee80211_channel_to_frequency(rxd->channel);
742
20f09c3d
LB
743 *qos = rxd->qos_control;
744
6f6d1e9a
LB
745 return le16_to_cpu(rxd->pkt_len);
746}
747
89a91f4f
LB
748static struct rxd_ops rxd_8366_ap_ops = {
749 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
750 .rxd_init = mwl8k_rxd_8366_ap_init,
751 .rxd_refill = mwl8k_rxd_8366_ap_refill,
752 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB
753};
754
755/*
89a91f4f 756 * Packet reception for STA firmware.
a66098da 757 */
89a91f4f 758struct mwl8k_rxd_sta {
a66098da
LB
759 __le16 pkt_len;
760 __u8 link_quality;
761 __u8 noise_level;
762 __le32 pkt_phys_addr;
45eb400d 763 __le32 next_rxd_phys_addr;
a66098da
LB
764 __le16 qos_control;
765 __le16 rate_info;
766 __le32 pad0[4];
767 __u8 rssi;
768 __u8 channel;
769 __le16 pad1;
770 __u8 rx_ctrl;
771 __u8 rx_status;
772 __u8 pad2[2];
773} __attribute__((packed));
774
89a91f4f
LB
775#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
776#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
777#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
778#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
779#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
780#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 781
89a91f4f 782#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
54bc3a0d 783
89a91f4f 784static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 785{
89a91f4f 786 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB
787
788 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 789 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB
790}
791
89a91f4f 792static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 793{
89a91f4f 794 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB
795
796 rxd->pkt_len = cpu_to_le16(len);
797 rxd->pkt_phys_addr = cpu_to_le32(addr);
798 wmb();
799 rxd->rx_ctrl = 0;
800}
801
802static int
89a91f4f 803mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
20f09c3d 804 __le16 *qos)
54bc3a0d 805{
89a91f4f 806 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB
807 u16 rate_info;
808
89a91f4f 809 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB
810 return -1;
811 rmb();
812
813 rate_info = le16_to_cpu(rxd->rate_info);
814
815 memset(status, 0, sizeof(*status));
816
817 status->signal = -rxd->rssi;
818 status->noise = -rxd->noise_level;
89a91f4f
LB
819 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
820 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 821
89a91f4f 822 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 823 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 824 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 825 status->flag |= RX_FLAG_40MHZ;
89a91f4f 826 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 827 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 828 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB
829 status->flag |= RX_FLAG_HT;
830
831 status->band = IEEE80211_BAND_2GHZ;
832 status->freq = ieee80211_channel_to_frequency(rxd->channel);
833
20f09c3d
LB
834 *qos = rxd->qos_control;
835
54bc3a0d
LB
836 return le16_to_cpu(rxd->pkt_len);
837}
838
89a91f4f
LB
839static struct rxd_ops rxd_sta_ops = {
840 .rxd_size = sizeof(struct mwl8k_rxd_sta),
841 .rxd_init = mwl8k_rxd_sta_init,
842 .rxd_refill = mwl8k_rxd_sta_refill,
843 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB
844};
845
846
a66098da
LB
847#define MWL8K_RX_DESCS 256
848#define MWL8K_RX_MAXSZ 3800
849
850static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
851{
852 struct mwl8k_priv *priv = hw->priv;
853 struct mwl8k_rx_queue *rxq = priv->rxq + index;
854 int size;
855 int i;
856
45eb400d
LB
857 rxq->rxd_count = 0;
858 rxq->head = 0;
859 rxq->tail = 0;
a66098da 860
54bc3a0d 861 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 862
45eb400d
LB
863 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
864 if (rxq->rxd == NULL) {
a66098da 865 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 866 wiphy_name(hw->wiphy));
a66098da
LB
867 return -ENOMEM;
868 }
45eb400d 869 memset(rxq->rxd, 0, size);
a66098da 870
788838eb
LB
871 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
872 if (rxq->buf == NULL) {
a66098da 873 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 874 wiphy_name(hw->wiphy));
45eb400d 875 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB
876 return -ENOMEM;
877 }
788838eb 878 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB
879
880 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB
881 int desc_size;
882 void *rxd;
a66098da 883 int nexti;
54bc3a0d
LB
884 dma_addr_t next_dma_addr;
885
886 desc_size = priv->rxd_ops->rxd_size;
887 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 888
54bc3a0d
LB
889 nexti = i + 1;
890 if (nexti == MWL8K_RX_DESCS)
891 nexti = 0;
892 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 893
54bc3a0d 894 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB
895 }
896
897 return 0;
898}
899
900static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
901{
902 struct mwl8k_priv *priv = hw->priv;
903 struct mwl8k_rx_queue *rxq = priv->rxq + index;
904 int refilled;
905
906 refilled = 0;
45eb400d 907 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 908 struct sk_buff *skb;
788838eb 909 dma_addr_t addr;
a66098da 910 int rx;
54bc3a0d 911 void *rxd;
a66098da
LB
912
913 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
914 if (skb == NULL)
915 break;
916
788838eb
LB
917 addr = pci_map_single(priv->pdev, skb->data,
918 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 919
54bc3a0d
LB
920 rxq->rxd_count++;
921 rx = rxq->tail++;
922 if (rxq->tail == MWL8K_RX_DESCS)
923 rxq->tail = 0;
788838eb
LB
924 rxq->buf[rx].skb = skb;
925 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB
926
927 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
928 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB
929
930 refilled++;
931 }
932
933 return refilled;
934}
935
936/* Must be called only when the card's reception is completely halted */
937static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
938{
939 struct mwl8k_priv *priv = hw->priv;
940 struct mwl8k_rx_queue *rxq = priv->rxq + index;
941 int i;
942
943 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB
944 if (rxq->buf[i].skb != NULL) {
945 pci_unmap_single(priv->pdev,
946 pci_unmap_addr(&rxq->buf[i], dma),
947 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
948 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
949
950 kfree_skb(rxq->buf[i].skb);
951 rxq->buf[i].skb = NULL;
a66098da
LB
952 }
953 }
954
788838eb
LB
955 kfree(rxq->buf);
956 rxq->buf = NULL;
a66098da
LB
957
958 pci_free_consistent(priv->pdev,
54bc3a0d 959 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB
960 rxq->rxd, rxq->rxd_dma);
961 rxq->rxd = NULL;
a66098da
LB
962}
963
964
965/*
966 * Scan a list of BSSIDs to process for finalize join.
967 * Allows for extension to process multiple BSSIDs.
968 */
969static inline int
970mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
971{
972 return priv->capture_beacon &&
973 ieee80211_is_beacon(wh->frame_control) &&
974 !compare_ether_addr(wh->addr3, priv->capture_bssid);
975}
976
3779752d
LB
977static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
978 struct sk_buff *skb)
a66098da 979{
3779752d
LB
980 struct mwl8k_priv *priv = hw->priv;
981
a66098da 982 priv->capture_beacon = false;
d89173f2 983 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB
984
985 /*
986 * Use GFP_ATOMIC as rxq_process is called from
987 * the primary interrupt handler, memory allocation call
988 * must not sleep.
989 */
990 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
991 if (priv->beacon_skb != NULL)
3779752d 992 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB
993}
994
995static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
996{
997 struct mwl8k_priv *priv = hw->priv;
998 struct mwl8k_rx_queue *rxq = priv->rxq + index;
999 int processed;
1000
1001 processed = 0;
45eb400d 1002 while (rxq->rxd_count && limit--) {
a66098da 1003 struct sk_buff *skb;
54bc3a0d
LB
1004 void *rxd;
1005 int pkt_len;
a66098da 1006 struct ieee80211_rx_status status;
20f09c3d 1007 __le16 qos;
a66098da 1008
788838eb 1009 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB
1010 if (skb == NULL)
1011 break;
54bc3a0d
LB
1012
1013 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1014
20f09c3d 1015 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
54bc3a0d
LB
1016 if (pkt_len < 0)
1017 break;
1018
788838eb
LB
1019 rxq->buf[rxq->head].skb = NULL;
1020
1021 pci_unmap_single(priv->pdev,
1022 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1023 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1024 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1025
54bc3a0d
LB
1026 rxq->head++;
1027 if (rxq->head == MWL8K_RX_DESCS)
1028 rxq->head = 0;
1029
45eb400d 1030 rxq->rxd_count--;
a66098da 1031
54bc3a0d 1032 skb_put(skb, pkt_len);
20f09c3d 1033 mwl8k_remove_dma_header(skb, qos);
a66098da 1034
a66098da 1035 /*
c2c357ce
LB
1036 * Check for a pending join operation. Save a
1037 * copy of the beacon and schedule a tasklet to
1038 * send a FINALIZE_JOIN command to the firmware.
a66098da 1039 */
54bc3a0d 1040 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1041 mwl8k_save_beacon(hw, skb);
a66098da 1042
f1d58c25
JB
1043 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1044 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB
1045
1046 processed++;
1047 }
1048
1049 return processed;
1050}
1051
1052
1053/*
1054 * Packet transmission.
1055 */
1056
a66098da
LB
1057#define MWL8K_TXD_STATUS_OK 0x00000001
1058#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1059#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1060#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1061#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1062
e0493a8d
LB
1063#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1064#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1065#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1066#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1067#define MWL8K_QOS_EOSP 0x0010
1068
a66098da
LB
1069struct mwl8k_tx_desc {
1070 __le32 status;
1071 __u8 data_rate;
1072 __u8 tx_priority;
1073 __le16 qos_control;
1074 __le32 pkt_phys_addr;
1075 __le16 pkt_len;
d89173f2 1076 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1077 __le32 next_txd_phys_addr;
a66098da
LB
1078 __le32 reserved;
1079 __le16 rate_info;
1080 __u8 peer_id;
1081 __u8 tx_frag_cnt;
1082} __attribute__((packed));
1083
1084#define MWL8K_TX_DESCS 128
1085
1086static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1087{
1088 struct mwl8k_priv *priv = hw->priv;
1089 struct mwl8k_tx_queue *txq = priv->txq + index;
1090 int size;
1091 int i;
1092
45eb400d
LB
1093 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1094 txq->stats.limit = MWL8K_TX_DESCS;
1095 txq->head = 0;
1096 txq->tail = 0;
a66098da
LB
1097
1098 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1099
45eb400d
LB
1100 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1101 if (txq->txd == NULL) {
a66098da 1102 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1103 wiphy_name(hw->wiphy));
a66098da
LB
1104 return -ENOMEM;
1105 }
45eb400d 1106 memset(txq->txd, 0, size);
a66098da 1107
45eb400d
LB
1108 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1109 if (txq->skb == NULL) {
a66098da 1110 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1111 wiphy_name(hw->wiphy));
45eb400d 1112 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB
1113 return -ENOMEM;
1114 }
45eb400d 1115 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB
1116
1117 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1118 struct mwl8k_tx_desc *tx_desc;
1119 int nexti;
1120
45eb400d 1121 tx_desc = txq->txd + i;
a66098da
LB
1122 nexti = (i + 1) % MWL8K_TX_DESCS;
1123
1124 tx_desc->status = 0;
45eb400d
LB
1125 tx_desc->next_txd_phys_addr =
1126 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB
1127 }
1128
1129 return 0;
1130}
1131
1132static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1133{
1134 iowrite32(MWL8K_H2A_INT_PPA_READY,
1135 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1136 iowrite32(MWL8K_H2A_INT_DUMMY,
1137 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1138 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1139}
1140
7e1112d3 1141static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1142{
7e1112d3
LB
1143 struct mwl8k_priv *priv = hw->priv;
1144 int i;
1145
1146 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1147 struct mwl8k_tx_queue *txq = priv->txq + i;
1148 int fw_owned = 0;
1149 int drv_owned = 0;
1150 int unused = 0;
1151 int desc;
1152
a66098da 1153 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB
1154 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1155 u32 status;
a66098da 1156
7e1112d3 1157 status = le32_to_cpu(tx_desc->status);
a66098da 1158 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1159 fw_owned++;
a66098da 1160 else
7e1112d3 1161 drv_owned++;
a66098da
LB
1162
1163 if (tx_desc->pkt_len == 0)
7e1112d3 1164 unused++;
a66098da 1165 }
a66098da 1166
7e1112d3
LB
1167 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1168 "fw_owned=%d drv_owned=%d unused=%d\n",
1169 wiphy_name(hw->wiphy), i,
1170 txq->stats.len, txq->head, txq->tail,
1171 fw_owned, drv_owned, unused);
1172 }
a66098da
LB
1173}
1174
618952a7 1175/*
88de754a 1176 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1177 */
62abd3cf 1178#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1179
950d5b01 1180static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1181{
a66098da 1182 struct mwl8k_priv *priv = hw->priv;
88de754a 1183 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB
1184 int retry;
1185 int rc;
a66098da
LB
1186
1187 might_sleep();
1188
7e1112d3
LB
1189 /*
1190 * The TX queues are stopped at this point, so this test
1191 * doesn't need to take ->tx_lock.
1192 */
1193 if (!priv->pending_tx_pkts)
1194 return 0;
1195
1196 retry = 0;
1197 rc = 0;
1198
a66098da 1199 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB
1200 priv->tx_wait = &tx_wait;
1201 while (!rc) {
1202 int oldcount;
1203 unsigned long timeout;
a66098da 1204
7e1112d3 1205 oldcount = priv->pending_tx_pkts;
a66098da 1206
7e1112d3 1207 spin_unlock_bh(&priv->tx_lock);
88de754a 1208 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1209 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1210 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB
1211
1212 if (timeout) {
1213 WARN_ON(priv->pending_tx_pkts);
1214 if (retry) {
1215 printk(KERN_NOTICE "%s: tx rings drained\n",
1216 wiphy_name(hw->wiphy));
1217 }
1218 break;
1219 }
1220
1221 if (priv->pending_tx_pkts < oldcount) {
9a2303b9
LB
1222 printk(KERN_NOTICE "%s: waiting for tx rings "
1223 "to drain (%d -> %d pkts)\n",
7e1112d3
LB
1224 wiphy_name(hw->wiphy), oldcount,
1225 priv->pending_tx_pkts);
1226 retry = 1;
1227 continue;
1228 }
1229
a66098da 1230 priv->tx_wait = NULL;
a66098da 1231
7e1112d3
LB
1232 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1233 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1234 mwl8k_dump_tx_rings(hw);
1235
1236 rc = -ETIMEDOUT;
a66098da 1237 }
7e1112d3 1238 spin_unlock_bh(&priv->tx_lock);
a66098da 1239
7e1112d3 1240 return rc;
a66098da
LB
1241}
1242
c23b5a69
LB
1243#define MWL8K_TXD_SUCCESS(status) \
1244 ((status) & (MWL8K_TXD_STATUS_OK | \
1245 MWL8K_TXD_STATUS_OK_RETRY | \
1246 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1247
efb7c49a
LB
1248static int
1249mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB
1250{
1251 struct mwl8k_priv *priv = hw->priv;
1252 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1253 int processed;
a66098da 1254
efb7c49a
LB
1255 processed = 0;
1256 while (txq->stats.len > 0 && limit--) {
a66098da 1257 int tx;
a66098da
LB
1258 struct mwl8k_tx_desc *tx_desc;
1259 unsigned long addr;
ce9e2e1b 1260 int size;
a66098da
LB
1261 struct sk_buff *skb;
1262 struct ieee80211_tx_info *info;
1263 u32 status;
1264
45eb400d
LB
1265 tx = txq->head;
1266 tx_desc = txq->txd + tx;
a66098da
LB
1267
1268 status = le32_to_cpu(tx_desc->status);
1269
1270 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1271 if (!force)
1272 break;
1273 tx_desc->status &=
1274 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1275 }
1276
45eb400d
LB
1277 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1278 BUG_ON(txq->stats.len == 0);
1279 txq->stats.len--;
a66098da
LB
1280 priv->pending_tx_pkts--;
1281
1282 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1283 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB
1284 skb = txq->skb[tx];
1285 txq->skb[tx] = NULL;
a66098da
LB
1286
1287 BUG_ON(skb == NULL);
1288 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1289
20f09c3d 1290 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB
1291
1292 /* Mark descriptor as unused */
1293 tx_desc->pkt_phys_addr = 0;
1294 tx_desc->pkt_len = 0;
1295
a66098da
LB
1296 info = IEEE80211_SKB_CB(skb);
1297 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1298 if (MWL8K_TXD_SUCCESS(status))
a66098da 1299 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB
1300
1301 ieee80211_tx_status_irqsafe(hw, skb);
1302
efb7c49a 1303 processed++;
a66098da
LB
1304 }
1305
efb7c49a 1306 if (processed && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da 1307 ieee80211_wake_queue(hw, index);
efb7c49a
LB
1308
1309 return processed;
a66098da
LB
1310}
1311
1312/* must be called only when the card's transmit is completely halted */
1313static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1314{
1315 struct mwl8k_priv *priv = hw->priv;
1316 struct mwl8k_tx_queue *txq = priv->txq + index;
1317
efb7c49a 1318 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1319
45eb400d
LB
1320 kfree(txq->skb);
1321 txq->skb = NULL;
a66098da
LB
1322
1323 pci_free_consistent(priv->pdev,
1324 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB
1325 txq->txd, txq->txd_dma);
1326 txq->txd = NULL;
a66098da
LB
1327}
1328
1329static int
1330mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1331{
1332 struct mwl8k_priv *priv = hw->priv;
1333 struct ieee80211_tx_info *tx_info;
23b33906 1334 struct mwl8k_vif *mwl8k_vif;
a66098da
LB
1335 struct ieee80211_hdr *wh;
1336 struct mwl8k_tx_queue *txq;
1337 struct mwl8k_tx_desc *tx;
a66098da 1338 dma_addr_t dma;
23b33906
LB
1339 u32 txstatus;
1340 u8 txdatarate;
1341 u16 qos;
a66098da 1342
23b33906
LB
1343 wh = (struct ieee80211_hdr *)skb->data;
1344 if (ieee80211_is_data_qos(wh->frame_control))
1345 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1346 else
1347 qos = 0;
a66098da 1348
76266b2a 1349 mwl8k_add_dma_header(skb);
23b33906 1350 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB
1351
1352 tx_info = IEEE80211_SKB_CB(skb);
1353 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB
1354
1355 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
a66098da 1356 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
657232b6
LB
1357 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1358 mwl8k_vif->seqno += 0x10;
a66098da
LB
1359 }
1360
23b33906
LB
1361 /* Setup firmware control bit fields for each frame type. */
1362 txstatus = 0;
1363 txdatarate = 0;
1364 if (ieee80211_is_mgmt(wh->frame_control) ||
1365 ieee80211_is_ctl(wh->frame_control)) {
1366 txdatarate = 0;
e0493a8d 1367 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB
1368 } else if (ieee80211_is_data(wh->frame_control)) {
1369 txdatarate = 1;
1370 if (is_multicast_ether_addr(wh->addr1))
1371 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1372
e0493a8d 1373 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1374 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1375 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1376 else
e0493a8d 1377 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1378 }
a66098da
LB
1379
1380 dma = pci_map_single(priv->pdev, skb->data,
1381 skb->len, PCI_DMA_TODEVICE);
1382
1383 if (pci_dma_mapping_error(priv->pdev, dma)) {
1384 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1385 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1386 dev_kfree_skb(skb);
a66098da
LB
1387 return NETDEV_TX_OK;
1388 }
1389
23b33906 1390 spin_lock_bh(&priv->tx_lock);
a66098da 1391
23b33906 1392 txq = priv->txq + index;
a66098da 1393
45eb400d
LB
1394 BUG_ON(txq->skb[txq->tail] != NULL);
1395 txq->skb[txq->tail] = skb;
a66098da 1396
45eb400d 1397 tx = txq->txd + txq->tail;
23b33906
LB
1398 tx->data_rate = txdatarate;
1399 tx->tx_priority = index;
a66098da 1400 tx->qos_control = cpu_to_le16(qos);
a66098da
LB
1401 tx->pkt_phys_addr = cpu_to_le32(dma);
1402 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1403 tx->rate_info = 0;
a680400e
LB
1404 if (!priv->ap_fw && tx_info->control.sta != NULL)
1405 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1406 else
1407 tx->peer_id = 0;
a66098da 1408 wmb();
23b33906
LB
1409 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1410
45eb400d
LB
1411 txq->stats.count++;
1412 txq->stats.len++;
a66098da 1413 priv->pending_tx_pkts++;
a66098da 1414
45eb400d
LB
1415 txq->tail++;
1416 if (txq->tail == MWL8K_TX_DESCS)
1417 txq->tail = 0;
23b33906 1418
45eb400d 1419 if (txq->head == txq->tail)
a66098da
LB
1420 ieee80211_stop_queue(hw, index);
1421
23b33906 1422 mwl8k_tx_start(priv);
a66098da
LB
1423
1424 spin_unlock_bh(&priv->tx_lock);
1425
1426 return NETDEV_TX_OK;
1427}
1428
1429
618952a7
LB
1430/*
1431 * Firmware access.
1432 *
1433 * We have the following requirements for issuing firmware commands:
1434 * - Some commands require that the packet transmit path is idle when
1435 * the command is issued. (For simplicity, we'll just quiesce the
1436 * transmit path for every command.)
1437 * - There are certain sequences of commands that need to be issued to
1438 * the hardware sequentially, with no other intervening commands.
1439 *
1440 * This leads to an implementation of a "firmware lock" as a mutex that
1441 * can be taken recursively, and which is taken by both the low-level
1442 * command submission function (mwl8k_post_cmd) as well as any users of
1443 * that function that require issuing of an atomic sequence of commands,
1444 * and quiesces the transmit path whenever it's taken.
1445 */
1446static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1447{
1448 struct mwl8k_priv *priv = hw->priv;
1449
1450 if (priv->fw_mutex_owner != current) {
1451 int rc;
1452
1453 mutex_lock(&priv->fw_mutex);
1454 ieee80211_stop_queues(hw);
1455
1456 rc = mwl8k_tx_wait_empty(hw);
1457 if (rc) {
1458 ieee80211_wake_queues(hw);
1459 mutex_unlock(&priv->fw_mutex);
1460
1461 return rc;
1462 }
1463
1464 priv->fw_mutex_owner = current;
1465 }
1466
1467 priv->fw_mutex_depth++;
1468
1469 return 0;
1470}
1471
1472static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1473{
1474 struct mwl8k_priv *priv = hw->priv;
1475
1476 if (!--priv->fw_mutex_depth) {
1477 ieee80211_wake_queues(hw);
1478 priv->fw_mutex_owner = NULL;
1479 mutex_unlock(&priv->fw_mutex);
1480 }
1481}
1482
1483
a66098da
LB
1484/*
1485 * Command processing.
1486 */
1487
0c9cc640
LB
1488/* Timeout firmware commands after 10s */
1489#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB
1490
1491static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1492{
1493 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1494 struct mwl8k_priv *priv = hw->priv;
1495 void __iomem *regs = priv->regs;
1496 dma_addr_t dma_addr;
1497 unsigned int dma_size;
1498 int rc;
a66098da
LB
1499 unsigned long timeout = 0;
1500 u8 buf[32];
1501
c2c357ce 1502 cmd->result = 0xffff;
a66098da
LB
1503 dma_size = le16_to_cpu(cmd->length);
1504 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1505 PCI_DMA_BIDIRECTIONAL);
1506 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1507 return -ENOMEM;
1508
618952a7 1509 rc = mwl8k_fw_lock(hw);
39a1e42e
LB
1510 if (rc) {
1511 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1512 PCI_DMA_BIDIRECTIONAL);
618952a7 1513 return rc;
39a1e42e 1514 }
a66098da 1515
a66098da
LB
1516 priv->hostcmd_wait = &cmd_wait;
1517 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1518 iowrite32(MWL8K_H2A_INT_DOORBELL,
1519 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1520 iowrite32(MWL8K_H2A_INT_DUMMY,
1521 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB
1522
1523 timeout = wait_for_completion_timeout(&cmd_wait,
1524 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1525
618952a7
LB
1526 priv->hostcmd_wait = NULL;
1527
1528 mwl8k_fw_unlock(hw);
1529
37055bd4
LB
1530 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1531 PCI_DMA_BIDIRECTIONAL);
1532
a66098da 1533 if (!timeout) {
a66098da 1534 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1535 wiphy_name(hw->wiphy),
a66098da
LB
1536 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1537 MWL8K_CMD_TIMEOUT_MS);
1538 rc = -ETIMEDOUT;
1539 } else {
0c9cc640
LB
1540 int ms;
1541
1542 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1543
ce9e2e1b 1544 rc = cmd->result ? -EINVAL : 0;
a66098da
LB
1545 if (rc)
1546 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1547 wiphy_name(hw->wiphy),
a66098da 1548 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1549 le16_to_cpu(cmd->result));
0c9cc640
LB
1550 else if (ms > 2000)
1551 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1552 wiphy_name(hw->wiphy),
1553 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1554 ms);
a66098da
LB
1555 }
1556
a66098da
LB
1557 return rc;
1558}
1559
1560/*
04b147b1 1561 * CMD_GET_HW_SPEC (STA version).
a66098da 1562 */
04b147b1 1563struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB
1564 struct mwl8k_cmd_pkt header;
1565 __u8 hw_rev;
1566 __u8 host_interface;
1567 __le16 num_mcaddrs;
d89173f2 1568 __u8 perm_addr[ETH_ALEN];
a66098da
LB
1569 __le16 region_code;
1570 __le32 fw_rev;
1571 __le32 ps_cookie;
1572 __le32 caps;
1573 __u8 mcs_bitmap[16];
1574 __le32 rx_queue_ptr;
1575 __le32 num_tx_queues;
1576 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1577 __le32 caps2;
1578 __le32 num_tx_desc_per_queue;
45eb400d 1579 __le32 total_rxd;
a66098da
LB
1580} __attribute__((packed));
1581
341c9791
LB
1582#define MWL8K_CAP_MAX_AMSDU 0x20000000
1583#define MWL8K_CAP_GREENFIELD 0x08000000
1584#define MWL8K_CAP_AMPDU 0x04000000
1585#define MWL8K_CAP_RX_STBC 0x01000000
1586#define MWL8K_CAP_TX_STBC 0x00800000
1587#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
1588#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
1589#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
1590#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
1591#define MWL8K_CAP_DELAY_BA 0x00003000
1592#define MWL8K_CAP_MIMO 0x00000200
1593#define MWL8K_CAP_40MHZ 0x00000100
1594
1595static void mwl8k_set_ht_caps(struct ieee80211_hw *hw, u32 cap)
1596{
1597 struct mwl8k_priv *priv = hw->priv;
777ad375 1598 struct ieee80211_supported_band *band = &priv->band_24;
341c9791
LB
1599 int rx_streams;
1600 int tx_streams;
1601
777ad375 1602 band->ht_cap.ht_supported = 1;
341c9791
LB
1603
1604 if (cap & MWL8K_CAP_MAX_AMSDU)
777ad375 1605 band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
341c9791 1606 if (cap & MWL8K_CAP_GREENFIELD)
777ad375 1607 band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
341c9791
LB
1608 if (cap & MWL8K_CAP_AMPDU) {
1609 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
777ad375
LB
1610 band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1611 band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
341c9791
LB
1612 }
1613 if (cap & MWL8K_CAP_RX_STBC)
777ad375 1614 band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
341c9791 1615 if (cap & MWL8K_CAP_TX_STBC)
777ad375 1616 band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
341c9791 1617 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
777ad375 1618 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
341c9791 1619 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
777ad375 1620 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
341c9791 1621 if (cap & MWL8K_CAP_DELAY_BA)
777ad375 1622 band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
341c9791 1623 if (cap & MWL8K_CAP_40MHZ)
777ad375 1624 band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
341c9791
LB
1625
1626 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
1627 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
1628
777ad375 1629 band->ht_cap.mcs.rx_mask[0] = 0xff;
341c9791 1630 if (rx_streams >= 2)
777ad375 1631 band->ht_cap.mcs.rx_mask[1] = 0xff;
341c9791 1632 if (rx_streams >= 3)
777ad375
LB
1633 band->ht_cap.mcs.rx_mask[2] = 0xff;
1634 band->ht_cap.mcs.rx_mask[4] = 0x01;
1635 band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
341c9791
LB
1636
1637 if (rx_streams != tx_streams) {
777ad375
LB
1638 band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
1639 band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
341c9791
LB
1640 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
1641 }
1642}
1643
04b147b1 1644static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB
1645{
1646 struct mwl8k_priv *priv = hw->priv;
04b147b1 1647 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB
1648 int rc;
1649 int i;
1650
1651 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1652 if (cmd == NULL)
1653 return -ENOMEM;
1654
1655 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1656 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1657
1658 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1659 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1660 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1661 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1662 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1663 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1664 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1665 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB
1666
1667 rc = mwl8k_post_cmd(hw, &cmd->header);
1668
1669 if (!rc) {
1670 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1671 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1672 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1673 priv->hw_rev = cmd->hw_rev;
341c9791
LB
1674 if (cmd->caps & cpu_to_le32(MWL8K_CAP_MIMO))
1675 mwl8k_set_ht_caps(hw, le32_to_cpu(cmd->caps));
a66098da
LB
1676 }
1677
1678 kfree(cmd);
1679 return rc;
1680}
1681
42fba21d
LB
1682/*
1683 * CMD_GET_HW_SPEC (AP version).
1684 */
1685struct mwl8k_cmd_get_hw_spec_ap {
1686 struct mwl8k_cmd_pkt header;
1687 __u8 hw_rev;
1688 __u8 host_interface;
1689 __le16 num_wcb;
1690 __le16 num_mcaddrs;
1691 __u8 perm_addr[ETH_ALEN];
1692 __le16 region_code;
1693 __le16 num_antenna;
1694 __le32 fw_rev;
1695 __le32 wcbbase0;
1696 __le32 rxwrptr;
1697 __le32 rxrdptr;
1698 __le32 ps_cookie;
1699 __le32 wcbbase1;
1700 __le32 wcbbase2;
1701 __le32 wcbbase3;
1702} __attribute__((packed));
1703
1704static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1705{
1706 struct mwl8k_priv *priv = hw->priv;
1707 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1708 int rc;
1709
1710 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1711 if (cmd == NULL)
1712 return -ENOMEM;
1713
1714 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1715 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1716
1717 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1718 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1719
1720 rc = mwl8k_post_cmd(hw, &cmd->header);
1721
1722 if (!rc) {
1723 int off;
1724
1725 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1726 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1727 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1728 priv->hw_rev = cmd->hw_rev;
1729
1730 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1731 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1732
1733 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1734 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1735
1736 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1737 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1738
1739 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1740 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1741
1742 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1743 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1744
1745 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1746 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1747 }
1748
1749 kfree(cmd);
1750 return rc;
1751}
1752
1753/*
1754 * CMD_SET_HW_SPEC.
1755 */
1756struct mwl8k_cmd_set_hw_spec {
1757 struct mwl8k_cmd_pkt header;
1758 __u8 hw_rev;
1759 __u8 host_interface;
1760 __le16 num_mcaddrs;
1761 __u8 perm_addr[ETH_ALEN];
1762 __le16 region_code;
1763 __le32 fw_rev;
1764 __le32 ps_cookie;
1765 __le32 caps;
1766 __le32 rx_queue_ptr;
1767 __le32 num_tx_queues;
1768 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1769 __le32 flags;
1770 __le32 num_tx_desc_per_queue;
1771 __le32 total_rxd;
1772} __attribute__((packed));
1773
b64fe619
LB
1774#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1775#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
1776#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB
1777
1778static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1779{
1780 struct mwl8k_priv *priv = hw->priv;
1781 struct mwl8k_cmd_set_hw_spec *cmd;
1782 int rc;
1783 int i;
1784
1785 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1786 if (cmd == NULL)
1787 return -ENOMEM;
1788
1789 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1790 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1791
1792 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1793 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1794 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1795 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1796 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
b64fe619
LB
1797 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
1798 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
1799 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
42fba21d
LB
1800 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1801 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1802
1803 rc = mwl8k_post_cmd(hw, &cmd->header);
1804 kfree(cmd);
1805
1806 return rc;
1807}
1808
a66098da
LB
1809/*
1810 * CMD_MAC_MULTICAST_ADR.
1811 */
1812struct mwl8k_cmd_mac_multicast_adr {
1813 struct mwl8k_cmd_pkt header;
1814 __le16 action;
1815 __le16 numaddr;
ce9e2e1b 1816 __u8 addr[0][ETH_ALEN];
a66098da
LB
1817};
1818
d5e30845
LB
1819#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1820#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1821#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1822#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1823
e81cd2d6 1824static struct mwl8k_cmd_pkt *
447ced07 1825__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1826 int mc_count, struct dev_addr_list *mclist)
a66098da 1827{
e81cd2d6 1828 struct mwl8k_priv *priv = hw->priv;
a66098da 1829 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1830 int size;
e81cd2d6 1831
447ced07 1832 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB
1833 allmulti = 1;
1834 mc_count = 0;
1835 }
e81cd2d6
LB
1836
1837 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1838
e81cd2d6 1839 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1840 if (cmd == NULL)
e81cd2d6 1841 return NULL;
a66098da
LB
1842
1843 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1844 cmd->header.length = cpu_to_le16(size);
d5e30845
LB
1845 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1846 MWL8K_ENABLE_RX_BROADCAST);
1847
1848 if (allmulti) {
1849 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1850 } else if (mc_count) {
1851 int i;
1852
1853 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1854 cmd->numaddr = cpu_to_le16(mc_count);
1855 for (i = 0; i < mc_count && mclist; i++) {
1856 if (mclist->da_addrlen != ETH_ALEN) {
1857 kfree(cmd);
1858 return NULL;
1859 }
1860 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1861 mclist = mclist->next;
a66098da 1862 }
a66098da
LB
1863 }
1864
e81cd2d6 1865 return &cmd->header;
a66098da
LB
1866}
1867
1868/*
55489b6e 1869 * CMD_GET_STAT.
a66098da 1870 */
55489b6e 1871struct mwl8k_cmd_get_stat {
a66098da 1872 struct mwl8k_cmd_pkt header;
a66098da
LB
1873 __le32 stats[64];
1874} __attribute__((packed));
1875
1876#define MWL8K_STAT_ACK_FAILURE 9
1877#define MWL8K_STAT_RTS_FAILURE 12
1878#define MWL8K_STAT_FCS_ERROR 24
1879#define MWL8K_STAT_RTS_SUCCESS 11
1880
55489b6e
LB
1881static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
1882 struct ieee80211_low_level_stats *stats)
a66098da 1883{
55489b6e 1884 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB
1885 int rc;
1886
1887 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1888 if (cmd == NULL)
1889 return -ENOMEM;
1890
1891 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1892 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB
1893
1894 rc = mwl8k_post_cmd(hw, &cmd->header);
1895 if (!rc) {
1896 stats->dot11ACKFailureCount =
1897 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1898 stats->dot11RTSFailureCount =
1899 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1900 stats->dot11FCSErrorCount =
1901 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1902 stats->dot11RTSSuccessCount =
1903 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1904 }
1905 kfree(cmd);
1906
1907 return rc;
1908}
1909
1910/*
55489b6e 1911 * CMD_RADIO_CONTROL.
a66098da 1912 */
55489b6e 1913struct mwl8k_cmd_radio_control {
a66098da
LB
1914 struct mwl8k_cmd_pkt header;
1915 __le16 action;
1916 __le16 control;
1917 __le16 radio_on;
1918} __attribute__((packed));
1919
c46563b7 1920static int
55489b6e 1921mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB
1922{
1923 struct mwl8k_priv *priv = hw->priv;
55489b6e 1924 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB
1925 int rc;
1926
c46563b7 1927 if (enable == priv->radio_on && !force)
a66098da
LB
1928 return 0;
1929
a66098da
LB
1930 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1931 if (cmd == NULL)
1932 return -ENOMEM;
1933
1934 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1935 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1936 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1937 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB
1938 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1939
1940 rc = mwl8k_post_cmd(hw, &cmd->header);
1941 kfree(cmd);
1942
1943 if (!rc)
c46563b7 1944 priv->radio_on = enable;
a66098da
LB
1945
1946 return rc;
1947}
1948
55489b6e 1949static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 1950{
55489b6e 1951 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB
1952}
1953
55489b6e 1954static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 1955{
55489b6e 1956 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB
1957}
1958
a66098da
LB
1959static int
1960mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1961{
99200a99 1962 struct mwl8k_priv *priv = hw->priv;
a66098da 1963
68ce3884 1964 priv->radio_short_preamble = short_preamble;
a66098da 1965
55489b6e 1966 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB
1967}
1968
1969/*
55489b6e 1970 * CMD_RF_TX_POWER.
a66098da
LB
1971 */
1972#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1973
55489b6e 1974struct mwl8k_cmd_rf_tx_power {
a66098da
LB
1975 struct mwl8k_cmd_pkt header;
1976 __le16 action;
1977 __le16 support_level;
1978 __le16 current_level;
1979 __le16 reserved;
1980 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1981} __attribute__((packed));
1982
55489b6e 1983static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 1984{
55489b6e 1985 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB
1986 int rc;
1987
1988 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1989 if (cmd == NULL)
1990 return -ENOMEM;
1991
1992 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1993 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1994 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1995 cmd->support_level = cpu_to_le16(dBm);
1996
1997 rc = mwl8k_post_cmd(hw, &cmd->header);
1998 kfree(cmd);
1999
2000 return rc;
2001}
2002
08b06347
LB
2003/*
2004 * CMD_RF_ANTENNA.
2005 */
2006struct mwl8k_cmd_rf_antenna {
2007 struct mwl8k_cmd_pkt header;
2008 __le16 antenna;
2009 __le16 mode;
2010} __attribute__((packed));
2011
2012#define MWL8K_RF_ANTENNA_RX 1
2013#define MWL8K_RF_ANTENNA_TX 2
2014
2015static int
2016mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2017{
2018 struct mwl8k_cmd_rf_antenna *cmd;
2019 int rc;
2020
2021 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2022 if (cmd == NULL)
2023 return -ENOMEM;
2024
2025 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2026 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2027 cmd->antenna = cpu_to_le16(antenna);
2028 cmd->mode = cpu_to_le16(mask);
2029
2030 rc = mwl8k_post_cmd(hw, &cmd->header);
2031 kfree(cmd);
2032
2033 return rc;
2034}
2035
b64fe619
LB
2036/*
2037 * CMD_SET_BEACON.
2038 */
2039struct mwl8k_cmd_set_beacon {
2040 struct mwl8k_cmd_pkt header;
2041 __le16 beacon_len;
2042 __u8 beacon[0];
2043};
2044
2045static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw, u8 *beacon, int len)
2046{
2047 struct mwl8k_cmd_set_beacon *cmd;
2048 int rc;
2049
2050 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2051 if (cmd == NULL)
2052 return -ENOMEM;
2053
2054 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2055 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2056 cmd->beacon_len = cpu_to_le16(len);
2057 memcpy(cmd->beacon, beacon, len);
2058
2059 rc = mwl8k_post_cmd(hw, &cmd->header);
2060 kfree(cmd);
2061
2062 return rc;
2063}
2064
a66098da
LB
2065/*
2066 * CMD_SET_PRE_SCAN.
2067 */
2068struct mwl8k_cmd_set_pre_scan {
2069 struct mwl8k_cmd_pkt header;
2070} __attribute__((packed));
2071
2072static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2073{
2074 struct mwl8k_cmd_set_pre_scan *cmd;
2075 int rc;
2076
2077 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2078 if (cmd == NULL)
2079 return -ENOMEM;
2080
2081 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2082 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2083
2084 rc = mwl8k_post_cmd(hw, &cmd->header);
2085 kfree(cmd);
2086
2087 return rc;
2088}
2089
2090/*
2091 * CMD_SET_POST_SCAN.
2092 */
2093struct mwl8k_cmd_set_post_scan {
2094 struct mwl8k_cmd_pkt header;
2095 __le32 isibss;
d89173f2 2096 __u8 bssid[ETH_ALEN];
a66098da
LB
2097} __attribute__((packed));
2098
2099static int
0a11dfc3 2100mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB
2101{
2102 struct mwl8k_cmd_set_post_scan *cmd;
2103 int rc;
2104
2105 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2106 if (cmd == NULL)
2107 return -ENOMEM;
2108
2109 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2110 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2111 cmd->isibss = 0;
d89173f2 2112 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB
2113
2114 rc = mwl8k_post_cmd(hw, &cmd->header);
2115 kfree(cmd);
2116
2117 return rc;
2118}
2119
2120/*
2121 * CMD_SET_RF_CHANNEL.
2122 */
2123struct mwl8k_cmd_set_rf_channel {
2124 struct mwl8k_cmd_pkt header;
2125 __le16 action;
2126 __u8 current_channel;
2127 __le32 channel_flags;
2128} __attribute__((packed));
2129
2130static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 2131 struct ieee80211_conf *conf)
a66098da 2132{
610677d2 2133 struct ieee80211_channel *channel = conf->channel;
a66098da
LB
2134 struct mwl8k_cmd_set_rf_channel *cmd;
2135 int rc;
2136
2137 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2138 if (cmd == NULL)
2139 return -ENOMEM;
2140
2141 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2142 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2143 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2144 cmd->current_channel = channel->hw_value;
610677d2 2145
a66098da 2146 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2
LB
2147 cmd->channel_flags |= cpu_to_le32(0x00000001);
2148
2149 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2150 conf->channel_type == NL80211_CHAN_HT20)
2151 cmd->channel_flags |= cpu_to_le32(0x00000080);
2152 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2153 cmd->channel_flags |= cpu_to_le32(0x000001900);
2154 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2155 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB
2156
2157 rc = mwl8k_post_cmd(hw, &cmd->header);
2158 kfree(cmd);
2159
2160 return rc;
2161}
2162
2163/*
55489b6e 2164 * CMD_SET_AID.
a66098da 2165 */
55489b6e
LB
2166#define MWL8K_FRAME_PROT_DISABLED 0x00
2167#define MWL8K_FRAME_PROT_11G 0x07
2168#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2169#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2170
55489b6e
LB
2171struct mwl8k_cmd_update_set_aid {
2172 struct mwl8k_cmd_pkt header;
2173 __le16 aid;
a66098da 2174
55489b6e
LB
2175 /* AP's MAC address (BSSID) */
2176 __u8 bssid[ETH_ALEN];
2177 __le16 protection_mode;
2178 __u8 supp_rates[14];
a66098da
LB
2179} __attribute__((packed));
2180
c6e96010
LB
2181static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
2182{
2183 int i;
2184 int j;
2185
2186 /*
2187 * Clear nonstandard rates 4 and 13.
2188 */
2189 mask &= 0x1fef;
2190
2191 for (i = 0, j = 0; i < 14; i++) {
2192 if (mask & (1 << i))
777ad375 2193 rates[j++] = mwl8k_rates_24[i].hw_value;
c6e96010
LB
2194 }
2195}
2196
55489b6e 2197static int
c6e96010
LB
2198mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2199 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 2200{
55489b6e
LB
2201 struct mwl8k_cmd_update_set_aid *cmd;
2202 u16 prot_mode;
a66098da
LB
2203 int rc;
2204
2205 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2206 if (cmd == NULL)
2207 return -ENOMEM;
2208
55489b6e 2209 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2210 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2211 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 2212 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2213
7dc6a7a7 2214 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB
2215 prot_mode = MWL8K_FRAME_PROT_11G;
2216 } else {
7dc6a7a7 2217 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB
2218 IEEE80211_HT_OP_MODE_PROTECTION) {
2219 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2220 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2221 break;
2222 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2223 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2224 break;
2225 default:
2226 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2227 break;
2228 }
2229 }
2230 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2231
c6e96010 2232 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB
2233
2234 rc = mwl8k_post_cmd(hw, &cmd->header);
2235 kfree(cmd);
2236
2237 return rc;
2238}
2239
32060e1b 2240/*
55489b6e 2241 * CMD_SET_RATE.
32060e1b 2242 */
55489b6e
LB
2243struct mwl8k_cmd_set_rate {
2244 struct mwl8k_cmd_pkt header;
2245 __u8 legacy_rates[14];
2246
2247 /* Bitmap for supported MCS codes. */
2248 __u8 mcs_set[16];
2249 __u8 reserved[16];
32060e1b
LB
2250} __attribute__((packed));
2251
55489b6e 2252static int
c6e96010 2253mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 2254 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 2255{
55489b6e 2256 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB
2257 int rc;
2258
2259 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2260 if (cmd == NULL)
2261 return -ENOMEM;
2262
55489b6e 2263 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 2264 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 2265 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 2266 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB
2267
2268 rc = mwl8k_post_cmd(hw, &cmd->header);
2269 kfree(cmd);
2270
2271 return rc;
2272}
2273
a66098da 2274/*
55489b6e 2275 * CMD_FINALIZE_JOIN.
a66098da 2276 */
55489b6e
LB
2277#define MWL8K_FJ_BEACON_MAXLEN 128
2278
2279struct mwl8k_cmd_finalize_join {
a66098da 2280 struct mwl8k_cmd_pkt header;
55489b6e
LB
2281 __le32 sleep_interval; /* Number of beacon periods to sleep */
2282 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
a66098da
LB
2283} __attribute__((packed));
2284
55489b6e
LB
2285static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2286 int framelen, int dtim)
a66098da 2287{
55489b6e
LB
2288 struct mwl8k_cmd_finalize_join *cmd;
2289 struct ieee80211_mgmt *payload = frame;
2290 int payload_len;
a66098da
LB
2291 int rc;
2292
2293 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2294 if (cmd == NULL)
2295 return -ENOMEM;
2296
55489b6e 2297 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 2298 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB
2299 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2300
2301 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2302 if (payload_len < 0)
2303 payload_len = 0;
2304 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2305 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2306
2307 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB
2308
2309 rc = mwl8k_post_cmd(hw, &cmd->header);
2310 kfree(cmd);
2311
2312 return rc;
2313}
2314
2315/*
55489b6e 2316 * CMD_SET_RTS_THRESHOLD.
a66098da 2317 */
55489b6e 2318struct mwl8k_cmd_set_rts_threshold {
a66098da
LB
2319 struct mwl8k_cmd_pkt header;
2320 __le16 action;
55489b6e 2321 __le16 threshold;
a66098da
LB
2322} __attribute__((packed));
2323
c2c2b12a
LB
2324static int
2325mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 2326{
55489b6e 2327 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB
2328 int rc;
2329
2330 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2331 if (cmd == NULL)
2332 return -ENOMEM;
2333
55489b6e 2334 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 2335 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB
2336 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2337 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB
2338
2339 rc = mwl8k_post_cmd(hw, &cmd->header);
2340 kfree(cmd);
2341
a66098da
LB
2342 return rc;
2343}
2344
2345/*
55489b6e 2346 * CMD_SET_SLOT.
a66098da 2347 */
55489b6e 2348struct mwl8k_cmd_set_slot {
a66098da
LB
2349 struct mwl8k_cmd_pkt header;
2350 __le16 action;
55489b6e 2351 __u8 short_slot;
a66098da
LB
2352} __attribute__((packed));
2353
55489b6e 2354static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 2355{
55489b6e 2356 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB
2357 int rc;
2358
2359 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2360 if (cmd == NULL)
2361 return -ENOMEM;
2362
55489b6e 2363 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 2364 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB
2365 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2366 cmd->short_slot = short_slot_time;
a66098da
LB
2367
2368 rc = mwl8k_post_cmd(hw, &cmd->header);
2369 kfree(cmd);
2370
2371 return rc;
2372}
2373
2374/*
2375 * CMD_SET_EDCA_PARAMS.
2376 */
2377struct mwl8k_cmd_set_edca_params {
2378 struct mwl8k_cmd_pkt header;
2379
2380 /* See MWL8K_SET_EDCA_XXX below */
2381 __le16 action;
2382
2383 /* TX opportunity in units of 32 us */
2384 __le16 txop;
2385
2e484c89
LB
2386 union {
2387 struct {
2388 /* Log exponent of max contention period: 0...15 */
2389 __le32 log_cw_max;
2390
2391 /* Log exponent of min contention period: 0...15 */
2392 __le32 log_cw_min;
2393
2394 /* Adaptive interframe spacing in units of 32us */
2395 __u8 aifs;
2396
2397 /* TX queue to configure */
2398 __u8 txq;
2399 } ap;
2400 struct {
2401 /* Log exponent of max contention period: 0...15 */
2402 __u8 log_cw_max;
a66098da 2403
2e484c89
LB
2404 /* Log exponent of min contention period: 0...15 */
2405 __u8 log_cw_min;
a66098da 2406
2e484c89
LB
2407 /* Adaptive interframe spacing in units of 32us */
2408 __u8 aifs;
a66098da 2409
2e484c89
LB
2410 /* TX queue to configure */
2411 __u8 txq;
2412 } sta;
2413 };
a66098da
LB
2414} __attribute__((packed));
2415
a66098da
LB
2416#define MWL8K_SET_EDCA_CW 0x01
2417#define MWL8K_SET_EDCA_TXOP 0x02
2418#define MWL8K_SET_EDCA_AIFS 0x04
2419
2420#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2421 MWL8K_SET_EDCA_TXOP | \
2422 MWL8K_SET_EDCA_AIFS)
2423
2424static int
55489b6e
LB
2425mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2426 __u16 cw_min, __u16 cw_max,
2427 __u8 aifs, __u16 txop)
a66098da 2428{
2e484c89 2429 struct mwl8k_priv *priv = hw->priv;
a66098da 2430 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB
2431 int rc;
2432
2433 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2434 if (cmd == NULL)
2435 return -ENOMEM;
2436
a66098da
LB
2437 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2438 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB
2439 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2440 cmd->txop = cpu_to_le16(txop);
2e484c89
LB
2441 if (priv->ap_fw) {
2442 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2443 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2444 cmd->ap.aifs = aifs;
2445 cmd->ap.txq = qnum;
2446 } else {
2447 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2448 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2449 cmd->sta.aifs = aifs;
2450 cmd->sta.txq = qnum;
2451 }
a66098da
LB
2452
2453 rc = mwl8k_post_cmd(hw, &cmd->header);
2454 kfree(cmd);
2455
2456 return rc;
2457}
2458
2459/*
55489b6e 2460 * CMD_SET_WMM_MODE.
a66098da 2461 */
55489b6e 2462struct mwl8k_cmd_set_wmm_mode {
a66098da 2463 struct mwl8k_cmd_pkt header;
55489b6e 2464 __le16 action;
a66098da
LB
2465} __attribute__((packed));
2466
55489b6e 2467static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 2468{
55489b6e
LB
2469 struct mwl8k_priv *priv = hw->priv;
2470 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB
2471 int rc;
2472
a66098da
LB
2473 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2474 if (cmd == NULL)
2475 return -ENOMEM;
2476
55489b6e 2477 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 2478 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 2479 cmd->action = cpu_to_le16(!!enable);
a66098da
LB
2480
2481 rc = mwl8k_post_cmd(hw, &cmd->header);
2482 kfree(cmd);
16cec43d 2483
55489b6e
LB
2484 if (!rc)
2485 priv->wmm_enabled = enable;
a66098da
LB
2486
2487 return rc;
2488}
2489
2490/*
55489b6e 2491 * CMD_MIMO_CONFIG.
a66098da 2492 */
55489b6e
LB
2493struct mwl8k_cmd_mimo_config {
2494 struct mwl8k_cmd_pkt header;
2495 __le32 action;
2496 __u8 rx_antenna_map;
2497 __u8 tx_antenna_map;
a66098da
LB
2498} __attribute__((packed));
2499
55489b6e 2500static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 2501{
55489b6e 2502 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB
2503 int rc;
2504
2505 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2506 if (cmd == NULL)
2507 return -ENOMEM;
2508
55489b6e 2509 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 2510 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB
2511 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2512 cmd->rx_antenna_map = rx;
2513 cmd->tx_antenna_map = tx;
a66098da
LB
2514
2515 rc = mwl8k_post_cmd(hw, &cmd->header);
2516 kfree(cmd);
2517
2518 return rc;
2519}
2520
2521/*
b71ed2c6 2522 * CMD_USE_FIXED_RATE (STA version).
a66098da 2523 */
b71ed2c6
LB
2524struct mwl8k_cmd_use_fixed_rate_sta {
2525 struct mwl8k_cmd_pkt header;
2526 __le32 action;
2527 __le32 allow_rate_drop;
2528 __le32 num_rates;
2529 struct {
2530 __le32 is_ht_rate;
2531 __le32 enable_retry;
2532 __le32 rate;
2533 __le32 retry_count;
2534 } rate_entry[8];
2535 __le32 rate_type;
2536 __le32 reserved1;
2537 __le32 reserved2;
a66098da
LB
2538} __attribute__((packed));
2539
b71ed2c6
LB
2540#define MWL8K_USE_AUTO_RATE 0x0002
2541#define MWL8K_UCAST_RATE 0
a66098da 2542
b71ed2c6 2543static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 2544{
b71ed2c6 2545 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB
2546 int rc;
2547
2548 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2549 if (cmd == NULL)
2550 return -ENOMEM;
2551
2552 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2553 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB
2554 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2555 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB
2556
2557 rc = mwl8k_post_cmd(hw, &cmd->header);
2558 kfree(cmd);
2559
2560 return rc;
2561}
2562
088aab8b
LB
2563/*
2564 * CMD_USE_FIXED_RATE (AP version).
2565 */
2566struct mwl8k_cmd_use_fixed_rate_ap {
2567 struct mwl8k_cmd_pkt header;
2568 __le32 action;
2569 __le32 allow_rate_drop;
2570 __le32 num_rates;
2571 struct mwl8k_rate_entry_ap {
2572 __le32 is_ht_rate;
2573 __le32 enable_retry;
2574 __le32 rate;
2575 __le32 retry_count;
2576 } rate_entry[4];
2577 u8 multicast_rate;
2578 u8 multicast_rate_type;
2579 u8 management_rate;
2580} __attribute__((packed));
2581
2582static int
2583mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
2584{
2585 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
2586 int rc;
2587
2588 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2589 if (cmd == NULL)
2590 return -ENOMEM;
2591
2592 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2593 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2594 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2595 cmd->multicast_rate = mcast;
2596 cmd->management_rate = mgmt;
2597
2598 rc = mwl8k_post_cmd(hw, &cmd->header);
2599 kfree(cmd);
2600
2601 return rc;
2602}
2603
55489b6e
LB
2604/*
2605 * CMD_ENABLE_SNIFFER.
2606 */
2607struct mwl8k_cmd_enable_sniffer {
2608 struct mwl8k_cmd_pkt header;
2609 __le32 action;
2610} __attribute__((packed));
2611
2612static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2613{
2614 struct mwl8k_cmd_enable_sniffer *cmd;
2615 int rc;
2616
2617 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2618 if (cmd == NULL)
2619 return -ENOMEM;
2620
2621 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2622 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2623 cmd->action = cpu_to_le32(!!enable);
2624
2625 rc = mwl8k_post_cmd(hw, &cmd->header);
2626 kfree(cmd);
2627
2628 return rc;
2629}
2630
2631/*
2632 * CMD_SET_MAC_ADDR.
2633 */
2634struct mwl8k_cmd_set_mac_addr {
2635 struct mwl8k_cmd_pkt header;
2636 union {
2637 struct {
2638 __le16 mac_type;
2639 __u8 mac_addr[ETH_ALEN];
2640 } mbss;
2641 __u8 mac_addr[ETH_ALEN];
2642 };
2643} __attribute__((packed));
2644
a9e00b15
LB
2645#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
2646#define MWL8K_MAC_TYPE_PRIMARY_AP 2
2647
55489b6e
LB
2648static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2649{
2650 struct mwl8k_priv *priv = hw->priv;
2651 struct mwl8k_cmd_set_mac_addr *cmd;
2652 int rc;
2653
2654 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2655 if (cmd == NULL)
2656 return -ENOMEM;
2657
2658 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2659 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2660 if (priv->ap_fw) {
a9e00b15 2661 cmd->mbss.mac_type = cpu_to_le16(MWL8K_MAC_TYPE_PRIMARY_AP);
55489b6e
LB
2662 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2663 } else {
2664 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2665 }
2666
2667 rc = mwl8k_post_cmd(hw, &cmd->header);
2668 kfree(cmd);
2669
2670 return rc;
2671}
2672
2673/*
2674 * CMD_SET_RATEADAPT_MODE.
2675 */
2676struct mwl8k_cmd_set_rate_adapt_mode {
2677 struct mwl8k_cmd_pkt header;
2678 __le16 action;
2679 __le16 mode;
2680} __attribute__((packed));
2681
2682static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2683{
2684 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2685 int rc;
2686
2687 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2688 if (cmd == NULL)
2689 return -ENOMEM;
2690
2691 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2692 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2693 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2694 cmd->mode = cpu_to_le16(mode);
2695
2696 rc = mwl8k_post_cmd(hw, &cmd->header);
2697 kfree(cmd);
2698
2699 return rc;
2700}
2701
b64fe619
LB
2702/*
2703 * CMD_BSS_START.
2704 */
2705struct mwl8k_cmd_bss_start {
2706 struct mwl8k_cmd_pkt header;
2707 __le32 enable;
2708} __attribute__((packed));
2709
2710static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw, int enable)
2711{
2712 struct mwl8k_cmd_bss_start *cmd;
2713 int rc;
2714
2715 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2716 if (cmd == NULL)
2717 return -ENOMEM;
2718
2719 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
2720 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2721 cmd->enable = cpu_to_le32(enable);
2722
2723 rc = mwl8k_post_cmd(hw, &cmd->header);
2724 kfree(cmd);
2725
2726 return rc;
2727}
2728
3f5610ff
LB
2729/*
2730 * CMD_SET_NEW_STN.
2731 */
2732struct mwl8k_cmd_set_new_stn {
2733 struct mwl8k_cmd_pkt header;
2734 __le16 aid;
2735 __u8 mac_addr[6];
2736 __le16 stn_id;
2737 __le16 action;
2738 __le16 rsvd;
2739 __le32 legacy_rates;
2740 __u8 ht_rates[4];
2741 __le16 cap_info;
2742 __le16 ht_capabilities_info;
2743 __u8 mac_ht_param_info;
2744 __u8 rev;
2745 __u8 control_channel;
2746 __u8 add_channel;
2747 __le16 op_mode;
2748 __le16 stbc;
2749 __u8 add_qos_info;
2750 __u8 is_qos_sta;
2751 __le32 fw_sta_ptr;
2752} __attribute__((packed));
2753
2754#define MWL8K_STA_ACTION_ADD 0
2755#define MWL8K_STA_ACTION_REMOVE 2
2756
2757static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
2758 struct ieee80211_vif *vif,
2759 struct ieee80211_sta *sta)
2760{
2761 struct mwl8k_cmd_set_new_stn *cmd;
2762 int rc;
2763
2764 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2765 if (cmd == NULL)
2766 return -ENOMEM;
2767
2768 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2769 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2770 cmd->aid = cpu_to_le16(sta->aid);
2771 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
2772 cmd->stn_id = cpu_to_le16(sta->aid);
2773 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
2774 cmd->legacy_rates = cpu_to_le32(sta->supp_rates[IEEE80211_BAND_2GHZ]);
2775 if (sta->ht_cap.ht_supported) {
2776 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
2777 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
2778 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
2779 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
2780 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
2781 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
2782 ((sta->ht_cap.ampdu_density & 7) << 2);
2783 cmd->is_qos_sta = 1;
2784 }
2785
2786 rc = mwl8k_post_cmd(hw, &cmd->header);
2787 kfree(cmd);
2788
2789 return rc;
2790}
2791
b64fe619
LB
2792static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
2793 struct ieee80211_vif *vif)
2794{
2795 struct mwl8k_cmd_set_new_stn *cmd;
2796 int rc;
2797
2798 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2799 if (cmd == NULL)
2800 return -ENOMEM;
2801
2802 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2803 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2804 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
2805
2806 rc = mwl8k_post_cmd(hw, &cmd->header);
2807 kfree(cmd);
2808
2809 return rc;
2810}
2811
3f5610ff
LB
2812static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
2813 struct ieee80211_vif *vif, u8 *addr)
2814{
2815 struct mwl8k_cmd_set_new_stn *cmd;
2816 int rc;
2817
2818 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2819 if (cmd == NULL)
2820 return -ENOMEM;
2821
2822 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2823 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2824 memcpy(cmd->mac_addr, addr, ETH_ALEN);
2825 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
2826
2827 rc = mwl8k_post_cmd(hw, &cmd->header);
2828 kfree(cmd);
2829
2830 return rc;
2831}
2832
55489b6e
LB
2833/*
2834 * CMD_UPDATE_STADB.
2835 */
25d81b1e
LB
2836struct ewc_ht_info {
2837 __le16 control1;
2838 __le16 control2;
2839 __le16 control3;
2840} __attribute__((packed));
2841
2842struct peer_capability_info {
2843 /* Peer type - AP vs. STA. */
2844 __u8 peer_type;
2845
2846 /* Basic 802.11 capabilities from assoc resp. */
2847 __le16 basic_caps;
2848
2849 /* Set if peer supports 802.11n high throughput (HT). */
2850 __u8 ht_support;
2851
2852 /* Valid if HT is supported. */
2853 __le16 ht_caps;
2854 __u8 extended_ht_caps;
2855 struct ewc_ht_info ewc_info;
2856
2857 /* Legacy rate table. Intersection of our rates and peer rates. */
2858 __u8 legacy_rates[12];
2859
2860 /* HT rate table. Intersection of our rates and peer rates. */
2861 __u8 ht_rates[16];
2862 __u8 pad[16];
2863
2864 /* If set, interoperability mode, no proprietary extensions. */
2865 __u8 interop;
2866 __u8 pad2;
2867 __u8 station_id;
2868 __le16 amsdu_enabled;
2869} __attribute__((packed));
2870
55489b6e
LB
2871struct mwl8k_cmd_update_stadb {
2872 struct mwl8k_cmd_pkt header;
2873
2874 /* See STADB_ACTION_TYPE */
2875 __le32 action;
2876
2877 /* Peer MAC address */
2878 __u8 peer_addr[ETH_ALEN];
2879
2880 __le32 reserved;
2881
2882 /* Peer info - valid during add/update. */
2883 struct peer_capability_info peer_info;
2884} __attribute__((packed));
2885
a680400e
LB
2886#define MWL8K_STA_DB_MODIFY_ENTRY 1
2887#define MWL8K_STA_DB_DEL_ENTRY 2
2888
2889/* Peer Entry flags - used to define the type of the peer node */
2890#define MWL8K_PEER_TYPE_ACCESSPOINT 2
2891
2892static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 2893 struct ieee80211_vif *vif,
13935e2c 2894 struct ieee80211_sta *sta)
55489b6e 2895{
55489b6e 2896 struct mwl8k_cmd_update_stadb *cmd;
a680400e 2897 struct peer_capability_info *p;
55489b6e
LB
2898 int rc;
2899
2900 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2901 if (cmd == NULL)
2902 return -ENOMEM;
2903
2904 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2905 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 2906 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 2907 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 2908
a680400e
LB
2909 p = &cmd->peer_info;
2910 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2911 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c
LB
2912 p->ht_support = sta->ht_cap.ht_supported;
2913 p->ht_caps = sta->ht_cap.cap;
2914 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
2915 ((sta->ht_cap.ampdu_density & 7) << 2);
2916 legacy_rate_mask_to_array(p->legacy_rates,
2917 sta->supp_rates[IEEE80211_BAND_2GHZ]);
2918 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB
2919 p->interop = 1;
2920 p->amsdu_enabled = 0;
2921
2922 rc = mwl8k_post_cmd(hw, &cmd->header);
2923 kfree(cmd);
2924
2925 return rc ? rc : p->station_id;
2926}
2927
2928static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
2929 struct ieee80211_vif *vif, u8 *addr)
2930{
2931 struct mwl8k_cmd_update_stadb *cmd;
2932 int rc;
2933
2934 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2935 if (cmd == NULL)
2936 return -ENOMEM;
2937
2938 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2939 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2940 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 2941 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 2942
a680400e 2943 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB
2944 kfree(cmd);
2945
2946 return rc;
2947}
2948
a66098da
LB
2949
2950/*
2951 * Interrupt handling.
2952 */
2953static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2954{
2955 struct ieee80211_hw *hw = dev_id;
2956 struct mwl8k_priv *priv = hw->priv;
2957 u32 status;
2958
2959 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB
2960 if (!status)
2961 return IRQ_NONE;
2962
1e9f9de3
LB
2963 if (status & MWL8K_A2H_INT_TX_DONE) {
2964 status &= ~MWL8K_A2H_INT_TX_DONE;
2965 tasklet_schedule(&priv->poll_tx_task);
2966 }
2967
a66098da 2968 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB
2969 status &= ~MWL8K_A2H_INT_RX_READY;
2970 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB
2971 }
2972
67e2eb27
LB
2973 if (status)
2974 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2975
a66098da 2976 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2977 if (priv->hostcmd_wait != NULL)
a66098da 2978 complete(priv->hostcmd_wait);
a66098da
LB
2979 }
2980
2981 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2982 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2983 priv->radio_on && priv->pending_tx_pkts)
618952a7 2984 mwl8k_tx_start(priv);
a66098da
LB
2985 }
2986
2987 return IRQ_HANDLED;
2988}
2989
1e9f9de3
LB
2990static void mwl8k_tx_poll(unsigned long data)
2991{
2992 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
2993 struct mwl8k_priv *priv = hw->priv;
2994 int limit;
2995 int i;
2996
2997 limit = 32;
2998
2999 spin_lock_bh(&priv->tx_lock);
3000
3001 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3002 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
3003
3004 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
3005 complete(priv->tx_wait);
3006 priv->tx_wait = NULL;
3007 }
3008
3009 spin_unlock_bh(&priv->tx_lock);
3010
3011 if (limit) {
3012 writel(~MWL8K_A2H_INT_TX_DONE,
3013 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3014 } else {
3015 tasklet_schedule(&priv->poll_tx_task);
3016 }
3017}
3018
67e2eb27
LB
3019static void mwl8k_rx_poll(unsigned long data)
3020{
3021 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3022 struct mwl8k_priv *priv = hw->priv;
3023 int limit;
3024
3025 limit = 32;
3026 limit -= rxq_process(hw, 0, limit);
3027 limit -= rxq_refill(hw, 0, limit);
3028
3029 if (limit) {
3030 writel(~MWL8K_A2H_INT_RX_READY,
3031 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3032 } else {
3033 tasklet_schedule(&priv->poll_rx_task);
3034 }
3035}
3036
a66098da
LB
3037
3038/*
3039 * Core driver operations.
3040 */
3041static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3042{
3043 struct mwl8k_priv *priv = hw->priv;
3044 int index = skb_get_queue_mapping(skb);
3045 int rc;
3046
9189c100 3047 if (!priv->radio_on) {
a66098da 3048 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 3049 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB
3050 dev_kfree_skb(skb);
3051 return NETDEV_TX_OK;
3052 }
3053
3054 rc = mwl8k_txq_xmit(hw, index, skb);
3055
3056 return rc;
3057}
3058
a66098da
LB
3059static int mwl8k_start(struct ieee80211_hw *hw)
3060{
a66098da
LB
3061 struct mwl8k_priv *priv = hw->priv;
3062 int rc;
3063
a0607fd3 3064 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB
3065 IRQF_SHARED, MWL8K_NAME, hw);
3066 if (rc) {
3067 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3068 wiphy_name(hw->wiphy));
2ec610cb 3069 return -EIO;
a66098da
LB
3070 }
3071
67e2eb27 3072 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 3073 tasklet_enable(&priv->poll_tx_task);
67e2eb27 3074 tasklet_enable(&priv->poll_rx_task);
2ec610cb 3075
a66098da 3076 /* Enable interrupts */
c23b5a69 3077 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 3078
2ec610cb
LB
3079 rc = mwl8k_fw_lock(hw);
3080 if (!rc) {
55489b6e 3081 rc = mwl8k_cmd_radio_enable(hw);
a66098da 3082
5e4cf166
LB
3083 if (!priv->ap_fw) {
3084 if (!rc)
55489b6e 3085 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 3086
5e4cf166
LB
3087 if (!rc)
3088 rc = mwl8k_cmd_set_pre_scan(hw);
3089
3090 if (!rc)
3091 rc = mwl8k_cmd_set_post_scan(hw,
3092 "\x00\x00\x00\x00\x00\x00");
3093 }
2ec610cb
LB
3094
3095 if (!rc)
55489b6e 3096 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 3097
2ec610cb 3098 if (!rc)
55489b6e 3099 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 3100
2ec610cb
LB
3101 mwl8k_fw_unlock(hw);
3102 }
3103
3104 if (rc) {
3105 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3106 free_irq(priv->pdev->irq, hw);
1e9f9de3 3107 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3108 tasklet_disable(&priv->poll_rx_task);
2ec610cb 3109 }
a66098da
LB
3110
3111 return rc;
3112}
3113
a66098da
LB
3114static void mwl8k_stop(struct ieee80211_hw *hw)
3115{
a66098da
LB
3116 struct mwl8k_priv *priv = hw->priv;
3117 int i;
3118
55489b6e 3119 mwl8k_cmd_radio_disable(hw);
a66098da
LB
3120
3121 ieee80211_stop_queues(hw);
3122
a66098da 3123 /* Disable interrupts */
a66098da 3124 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB
3125 free_irq(priv->pdev->irq, hw);
3126
3127 /* Stop finalize join worker */
3128 cancel_work_sync(&priv->finalize_join_worker);
3129 if (priv->beacon_skb != NULL)
3130 dev_kfree_skb(priv->beacon_skb);
3131
67e2eb27 3132 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 3133 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3134 tasklet_disable(&priv->poll_rx_task);
a66098da 3135
a66098da
LB
3136 /* Return all skbs to mac80211 */
3137 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 3138 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB
3139}
3140
3141static int mwl8k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 3142 struct ieee80211_vif *vif)
a66098da
LB
3143{
3144 struct mwl8k_priv *priv = hw->priv;
3145 struct mwl8k_vif *mwl8k_vif;
3146
3147 /*
3148 * We only support one active interface at a time.
3149 */
3150 if (priv->vif != NULL)
3151 return -EBUSY;
3152
a43c49a8
LB
3153 /*
3154 * Reject interface creation if sniffer mode is active, as
3155 * STA operation is mutually exclusive with hardware sniffer
b64fe619 3156 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB
3157 */
3158 if (priv->sniffer_enabled) {
3159 printk(KERN_INFO "%s: unable to create STA "
3160 "interface due to sniffer mode being enabled\n",
3161 wiphy_name(hw->wiphy));
3162 return -EINVAL;
3163 }
3164
c2c2b12a
LB
3165 /* Set the mac address. */
3166 mwl8k_cmd_set_mac_addr(hw, vif->addr);
3167
b64fe619
LB
3168 if (priv->ap_fw)
3169 mwl8k_cmd_set_new_stn_add_self(hw, vif);
3170
a66098da 3171 /* Clean out driver private area */
1ed32e4f 3172 mwl8k_vif = MWL8K_VIF(vif);
a66098da
LB
3173 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
3174
a66098da
LB
3175 /* Set Initial sequence number to zero */
3176 mwl8k_vif->seqno = 0;
3177
1ed32e4f 3178 priv->vif = vif;
a66098da
LB
3179
3180 return 0;
3181}
3182
3183static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3184 struct ieee80211_vif *vif)
a66098da
LB
3185{
3186 struct mwl8k_priv *priv = hw->priv;
3187
b64fe619
LB
3188 if (priv->ap_fw)
3189 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
3190
55489b6e 3191 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b 3192
a66098da
LB
3193 priv->vif = NULL;
3194}
3195
ee03a932 3196static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 3197{
a66098da
LB
3198 struct ieee80211_conf *conf = &hw->conf;
3199 struct mwl8k_priv *priv = hw->priv;
ee03a932 3200 int rc;
a66098da 3201
7595d67a 3202 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 3203 mwl8k_cmd_radio_disable(hw);
ee03a932 3204 return 0;
7595d67a
LB
3205 }
3206
ee03a932
LB
3207 rc = mwl8k_fw_lock(hw);
3208 if (rc)
3209 return rc;
a66098da 3210
55489b6e 3211 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB
3212 if (rc)
3213 goto out;
a66098da 3214
610677d2 3215 rc = mwl8k_cmd_set_rf_channel(hw, conf);
ee03a932
LB
3216 if (rc)
3217 goto out;
3218
a66098da
LB
3219 if (conf->power_level > 18)
3220 conf->power_level = 18;
55489b6e 3221 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
ee03a932
LB
3222 if (rc)
3223 goto out;
a66098da 3224
08b06347
LB
3225 if (priv->ap_fw) {
3226 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
3227 if (!rc)
3228 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
3229 } else {
3230 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
3231 }
a66098da 3232
ee03a932
LB
3233out:
3234 mwl8k_fw_unlock(hw);
a66098da 3235
ee03a932 3236 return rc;
a66098da
LB
3237}
3238
b64fe619
LB
3239static void
3240mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3241 struct ieee80211_bss_conf *info, u32 changed)
a66098da 3242{
a66098da 3243 struct mwl8k_priv *priv = hw->priv;
c3cbbe8a 3244 u32 ap_legacy_rates;
13935e2c 3245 u8 ap_mcs_rates[16];
3a980d0a
LB
3246 int rc;
3247
c3cbbe8a 3248 if (mwl8k_fw_lock(hw))
3a980d0a 3249 return;
a66098da 3250
c3cbbe8a
LB
3251 /*
3252 * No need to capture a beacon if we're no longer associated.
3253 */
3254 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
3255 priv->capture_beacon = false;
3a980d0a 3256
c3cbbe8a 3257 /*
13935e2c 3258 * Get the AP's legacy and MCS rates.
c3cbbe8a 3259 */
7dc6a7a7 3260 if (vif->bss_conf.assoc) {
c6e96010 3261 struct ieee80211_sta *ap;
c97470dd 3262
c6e96010 3263 rcu_read_lock();
c6e96010 3264
c3cbbe8a
LB
3265 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
3266 if (ap == NULL) {
3267 rcu_read_unlock();
c6e96010 3268 goto out;
c3cbbe8a
LB
3269 }
3270
3271 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
13935e2c 3272 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB
3273
3274 rcu_read_unlock();
3275 }
c6e96010 3276
c3cbbe8a 3277 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
13935e2c 3278 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB
3279 if (rc)
3280 goto out;
a66098da 3281
b71ed2c6 3282 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB
3283 if (rc)
3284 goto out;
c3cbbe8a 3285 }
a66098da 3286
c3cbbe8a 3287 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB
3288 rc = mwl8k_set_radio_preamble(hw,
3289 vif->bss_conf.use_short_preamble);
3a980d0a
LB
3290 if (rc)
3291 goto out;
c3cbbe8a 3292 }
a66098da 3293
c3cbbe8a 3294 if (changed & BSS_CHANGED_ERP_SLOT) {
7dc6a7a7 3295 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB
3296 if (rc)
3297 goto out;
c3cbbe8a 3298 }
a66098da 3299
c97470dd
LB
3300 if (vif->bss_conf.assoc &&
3301 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
3302 BSS_CHANGED_HT))) {
c3cbbe8a 3303 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB
3304 if (rc)
3305 goto out;
c3cbbe8a 3306 }
a66098da 3307
c3cbbe8a
LB
3308 if (vif->bss_conf.assoc &&
3309 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB
3310 /*
3311 * Finalize the join. Tell rx handler to process
3312 * next beacon from our BSSID.
3313 */
0a11dfc3 3314 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 3315 priv->capture_beacon = true;
a66098da
LB
3316 }
3317
3a980d0a
LB
3318out:
3319 mwl8k_fw_unlock(hw);
a66098da
LB
3320}
3321
b64fe619
LB
3322static void
3323mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3324 struct ieee80211_bss_conf *info, u32 changed)
3325{
3326 int rc;
3327
3328 if (mwl8k_fw_lock(hw))
3329 return;
3330
3331 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3332 rc = mwl8k_set_radio_preamble(hw,
3333 vif->bss_conf.use_short_preamble);
3334 if (rc)
3335 goto out;
3336 }
3337
3338 if (changed & BSS_CHANGED_BASIC_RATES) {
3339 int idx;
3340 int rate;
3341
3342 /*
3343 * Use lowest supported basic rate for multicasts
3344 * and management frames (such as probe responses --
3345 * beacons will always go out at 1 Mb/s).
3346 */
3347 idx = ffs(vif->bss_conf.basic_rates);
777ad375 3348 rate = idx ? mwl8k_rates_24[idx - 1].hw_value : 2;
b64fe619
LB
3349
3350 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
3351 }
3352
3353 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
3354 struct sk_buff *skb;
3355
3356 skb = ieee80211_beacon_get(hw, vif);
3357 if (skb != NULL) {
3358 mwl8k_cmd_set_beacon(hw, skb->data, skb->len);
3359 kfree_skb(skb);
3360 }
3361 }
3362
3363 if (changed & BSS_CHANGED_BEACON_ENABLED)
3364 mwl8k_cmd_bss_start(hw, info->enable_beacon);
3365
3366out:
3367 mwl8k_fw_unlock(hw);
3368}
3369
3370static void
3371mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3372 struct ieee80211_bss_conf *info, u32 changed)
3373{
3374 struct mwl8k_priv *priv = hw->priv;
3375
3376 if (!priv->ap_fw)
3377 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
3378 else
3379 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
3380}
3381
e81cd2d6
LB
3382static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3383 int mc_count, struct dev_addr_list *mclist)
3384{
3385 struct mwl8k_cmd_pkt *cmd;
3386
447ced07
LB
3387 /*
3388 * Synthesize and return a command packet that programs the
3389 * hardware multicast address filter. At this point we don't
3390 * know whether FIF_ALLMULTI is being requested, but if it is,
3391 * we'll end up throwing this packet away and creating a new
3392 * one in mwl8k_configure_filter().
3393 */
3394 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB
3395
3396 return (unsigned long)cmd;
3397}
3398
a43c49a8
LB
3399static int
3400mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3401 unsigned int changed_flags,
3402 unsigned int *total_flags)
3403{
3404 struct mwl8k_priv *priv = hw->priv;
3405
3406 /*
3407 * Hardware sniffer mode is mutually exclusive with STA
3408 * operation, so refuse to enable sniffer mode if a STA
3409 * interface is active.
3410 */
3411 if (priv->vif != NULL) {
3412 if (net_ratelimit())
3413 printk(KERN_INFO "%s: not enabling sniffer "
3414 "mode because STA interface is active\n",
3415 wiphy_name(hw->wiphy));
3416 return 0;
3417 }
3418
3419 if (!priv->sniffer_enabled) {
55489b6e 3420 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB
3421 return 0;
3422 priv->sniffer_enabled = true;
3423 }
3424
3425 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3426 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3427 FIF_OTHER_BSS;
3428
3429 return 1;
3430}
3431
e6935ea1
LB
3432static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3433 unsigned int changed_flags,
3434 unsigned int *total_flags,
3435 u64 multicast)
3436{
3437 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB
3438 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3439
c0adae2c
LB
3440 /*
3441 * AP firmware doesn't allow fine-grained control over
3442 * the receive filter.
3443 */
3444 if (priv->ap_fw) {
3445 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3446 kfree(cmd);
3447 return;
3448 }
3449
a43c49a8
LB
3450 /*
3451 * Enable hardware sniffer mode if FIF_CONTROL or
3452 * FIF_OTHER_BSS is requested.
3453 */
3454 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3455 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3456 kfree(cmd);
3457 return;
3458 }
a66098da 3459
e6935ea1 3460 /* Clear unsupported feature flags */
447ced07 3461 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3462
90852f7a
LB
3463 if (mwl8k_fw_lock(hw)) {
3464 kfree(cmd);
e6935ea1 3465 return;
90852f7a 3466 }
a66098da 3467
a43c49a8 3468 if (priv->sniffer_enabled) {
55489b6e 3469 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB
3470 priv->sniffer_enabled = false;
3471 }
3472
e6935ea1 3473 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB
3474 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3475 /*
3476 * Disable the BSS filter.
3477 */
e6935ea1 3478 mwl8k_cmd_set_pre_scan(hw);
77165d88 3479 } else {
0a11dfc3 3480 const u8 *bssid;
a94cc97e 3481
77165d88
LB
3482 /*
3483 * Enable the BSS filter.
3484 *
3485 * If there is an active STA interface, use that
3486 * interface's BSSID, otherwise use a dummy one
3487 * (where the OUI part needs to be nonzero for
3488 * the BSSID to be accepted by POST_SCAN).
3489 */
3490 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 3491 if (priv->vif != NULL)
0a11dfc3 3492 bssid = priv->vif->bss_conf.bssid;
a94cc97e 3493
e6935ea1 3494 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB
3495 }
3496 }
3497
447ced07
LB
3498 /*
3499 * If FIF_ALLMULTI is being requested, throw away the command
3500 * packet that ->prepare_multicast() built and replace it with
3501 * a command packet that enables reception of all multicast
3502 * packets.
3503 */
3504 if (*total_flags & FIF_ALLMULTI) {
3505 kfree(cmd);
3506 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3507 }
3508
3509 if (cmd != NULL) {
3510 mwl8k_post_cmd(hw, cmd);
3511 kfree(cmd);
e6935ea1 3512 }
a66098da 3513
e6935ea1 3514 mwl8k_fw_unlock(hw);
a66098da
LB
3515}
3516
a66098da
LB
3517static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3518{
c2c2b12a 3519 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB
3520}
3521
bbfd9128
LB
3522struct mwl8k_sta_notify_item
3523{
3524 struct list_head list;
3525 struct ieee80211_vif *vif;
3526 enum sta_notify_cmd cmd;
13935e2c 3527 struct ieee80211_sta sta;
bbfd9128
LB
3528};
3529
3f5610ff
LB
3530static void
3531mwl8k_do_sta_notify(struct ieee80211_hw *hw, struct mwl8k_sta_notify_item *s)
3532{
3533 struct mwl8k_priv *priv = hw->priv;
3534
3535 /*
3536 * STA firmware uses UPDATE_STADB, AP firmware uses SET_NEW_STN.
3537 */
3538 if (!priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
3539 int rc;
3540
3541 rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta);
3542 if (rc >= 0) {
3543 struct ieee80211_sta *sta;
3544
3545 rcu_read_lock();
3546 sta = ieee80211_find_sta(s->vif, s->sta.addr);
3547 if (sta != NULL)
3548 MWL8K_STA(sta)->peer_id = rc;
3549 rcu_read_unlock();
3550 }
3551 } else if (!priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
3552 mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr);
3553 } else if (priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
3554 mwl8k_cmd_set_new_stn_add(hw, s->vif, &s->sta);
3555 } else if (priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
3556 mwl8k_cmd_set_new_stn_del(hw, s->vif, s->sta.addr);
3557 }
3558}
3559
bbfd9128
LB
3560static void mwl8k_sta_notify_worker(struct work_struct *work)
3561{
3562 struct mwl8k_priv *priv =
3563 container_of(work, struct mwl8k_priv, sta_notify_worker);
a680400e 3564 struct ieee80211_hw *hw = priv->hw;
bbfd9128
LB
3565
3566 spin_lock_bh(&priv->sta_notify_list_lock);
3567 while (!list_empty(&priv->sta_notify_list)) {
3568 struct mwl8k_sta_notify_item *s;
bbfd9128
LB
3569
3570 s = list_entry(priv->sta_notify_list.next,
3571 struct mwl8k_sta_notify_item, list);
3572 list_del(&s->list);
3573
3574 spin_unlock_bh(&priv->sta_notify_list_lock);
3575
3f5610ff 3576 mwl8k_do_sta_notify(hw, s);
bbfd9128
LB
3577 kfree(s);
3578
3579 spin_lock_bh(&priv->sta_notify_list_lock);
3580 }
3581 spin_unlock_bh(&priv->sta_notify_list_lock);
3582}
3583
3584static void
3585mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3586 enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
3587{
3588 struct mwl8k_priv *priv = hw->priv;
3589 struct mwl8k_sta_notify_item *s;
3590
3591 if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
3592 return;
3593
3594 s = kmalloc(sizeof(*s), GFP_ATOMIC);
3595 if (s != NULL) {
3596 s->vif = vif;
3597 s->cmd = cmd;
13935e2c 3598 s->sta = *sta;
bbfd9128
LB
3599
3600 spin_lock(&priv->sta_notify_list_lock);
3601 list_add_tail(&s->list, &priv->sta_notify_list);
3602 spin_unlock(&priv->sta_notify_list_lock);
3603
3604 ieee80211_queue_work(hw, &priv->sta_notify_worker);
3605 }
3606}
3607
a66098da
LB
3608static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3609 const struct ieee80211_tx_queue_params *params)
3610{
3e4f542c 3611 struct mwl8k_priv *priv = hw->priv;
a66098da 3612 int rc;
a66098da 3613
3e4f542c
LB
3614 rc = mwl8k_fw_lock(hw);
3615 if (!rc) {
3616 if (!priv->wmm_enabled)
55489b6e 3617 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 3618
3e4f542c 3619 if (!rc)
55489b6e
LB
3620 rc = mwl8k_cmd_set_edca_params(hw, queue,
3621 params->cw_min,
3622 params->cw_max,
3623 params->aifs,
3624 params->txop);
3e4f542c
LB
3625
3626 mwl8k_fw_unlock(hw);
a66098da 3627 }
3e4f542c 3628
a66098da
LB
3629 return rc;
3630}
3631
3632static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3633 struct ieee80211_tx_queue_stats *stats)
3634{
3635 struct mwl8k_priv *priv = hw->priv;
3636 struct mwl8k_tx_queue *txq;
3637 int index;
3638
3639 spin_lock_bh(&priv->tx_lock);
3640 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3641 txq = priv->txq + index;
45eb400d 3642 memcpy(&stats[index], &txq->stats,
a66098da
LB
3643 sizeof(struct ieee80211_tx_queue_stats));
3644 }
3645 spin_unlock_bh(&priv->tx_lock);
a66098da 3646
954ef509 3647 return 0;
a66098da
LB
3648}
3649
3650static int mwl8k_get_stats(struct ieee80211_hw *hw,
3651 struct ieee80211_low_level_stats *stats)
3652{
55489b6e 3653 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB
3654}
3655
a2292d83
LB
3656static int
3657mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3658 enum ieee80211_ampdu_mlme_action action,
3659 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3660{
3661 switch (action) {
3662 case IEEE80211_AMPDU_RX_START:
3663 case IEEE80211_AMPDU_RX_STOP:
3664 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
3665 return -ENOTSUPP;
3666 return 0;
3667 default:
3668 return -ENOTSUPP;
3669 }
3670}
3671
a66098da
LB
3672static const struct ieee80211_ops mwl8k_ops = {
3673 .tx = mwl8k_tx,
3674 .start = mwl8k_start,
3675 .stop = mwl8k_stop,
3676 .add_interface = mwl8k_add_interface,
3677 .remove_interface = mwl8k_remove_interface,
3678 .config = mwl8k_config,
a66098da 3679 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3680 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB
3681 .configure_filter = mwl8k_configure_filter,
3682 .set_rts_threshold = mwl8k_set_rts_threshold,
bbfd9128 3683 .sta_notify = mwl8k_sta_notify,
a66098da
LB
3684 .conf_tx = mwl8k_conf_tx,
3685 .get_tx_stats = mwl8k_get_tx_stats,
3686 .get_stats = mwl8k_get_stats,
a2292d83 3687 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB
3688};
3689
a66098da
LB
3690static void mwl8k_finalize_join_worker(struct work_struct *work)
3691{
3692 struct mwl8k_priv *priv =
3693 container_of(work, struct mwl8k_priv, finalize_join_worker);
3694 struct sk_buff *skb = priv->beacon_skb;
a66098da 3695
7dc6a7a7
LB
3696 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
3697 priv->vif->bss_conf.dtim_period);
a66098da
LB
3698 dev_kfree_skb(skb);
3699
3700 priv->beacon_skb = NULL;
3701}
3702
bcb628d5 3703enum {
9e1b17ea
LB
3704 MWL8363 = 0,
3705 MWL8687,
bcb628d5 3706 MWL8366,
6f6d1e9a
LB
3707};
3708
bcb628d5 3709static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
9e1b17ea
LB
3710 [MWL8363] = {
3711 .part_name = "88w8363",
3712 .helper_image = "mwl8k/helper_8363.fw",
3713 .fw_image = "mwl8k/fmimage_8363.fw",
3714 },
49eb691c 3715 [MWL8687] = {
bcb628d5
JL
3716 .part_name = "88w8687",
3717 .helper_image = "mwl8k/helper_8687.fw",
3718 .fw_image = "mwl8k/fmimage_8687.fw",
bcb628d5 3719 },
49eb691c 3720 [MWL8366] = {
bcb628d5
JL
3721 .part_name = "88w8366",
3722 .helper_image = "mwl8k/helper_8366.fw",
3723 .fw_image = "mwl8k/fmimage_8366.fw",
89a91f4f 3724 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 3725 },
45a390dd
LB
3726};
3727
c92d4ede
LB
3728MODULE_FIRMWARE("mwl8k/helper_8363.fw");
3729MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
3730MODULE_FIRMWARE("mwl8k/helper_8687.fw");
3731MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
3732MODULE_FIRMWARE("mwl8k/helper_8366.fw");
3733MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
3734
45a390dd 3735static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
9e1b17ea
LB
3736 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
3737 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL
3738 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3739 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3740 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
ca66527c 3741 { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
bcb628d5 3742 { },
45a390dd
LB
3743};
3744MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3745
a66098da
LB
3746static int __devinit mwl8k_probe(struct pci_dev *pdev,
3747 const struct pci_device_id *id)
3748{
2aa7b01f 3749 static int printed_version = 0;
a66098da
LB
3750 struct ieee80211_hw *hw;
3751 struct mwl8k_priv *priv;
a66098da
LB
3752 int rc;
3753 int i;
2aa7b01f
LB
3754
3755 if (!printed_version) {
3756 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3757 printed_version = 1;
3758 }
a66098da 3759
be695fc4 3760
a66098da
LB
3761 rc = pci_enable_device(pdev);
3762 if (rc) {
3763 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3764 MWL8K_NAME);
3765 return rc;
3766 }
3767
3768 rc = pci_request_regions(pdev, MWL8K_NAME);
3769 if (rc) {
3770 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3771 MWL8K_NAME);
3db95e50 3772 goto err_disable_device;
a66098da
LB
3773 }
3774
3775 pci_set_master(pdev);
3776
be695fc4 3777
a66098da
LB
3778 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3779 if (hw == NULL) {
3780 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3781 rc = -ENOMEM;
3782 goto err_free_reg;
3783 }
3784
be695fc4
LB
3785 SET_IEEE80211_DEV(hw, &pdev->dev);
3786 pci_set_drvdata(pdev, hw);
3787
a66098da
LB
3788 priv = hw->priv;
3789 priv->hw = hw;
3790 priv->pdev = pdev;
bcb628d5 3791 priv->device_info = &mwl8k_info_tbl[id->driver_data];
a66098da 3792
a66098da 3793
5b9482dd
LB
3794 priv->sram = pci_iomap(pdev, 0, 0x10000);
3795 if (priv->sram == NULL) {
3796 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3797 wiphy_name(hw->wiphy));
a66098da
LB
3798 goto err_iounmap;
3799 }
3800
5b9482dd
LB
3801 /*
3802 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3803 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3804 */
3805 priv->regs = pci_iomap(pdev, 1, 0x10000);
3806 if (priv->regs == NULL) {
3807 priv->regs = pci_iomap(pdev, 2, 0x10000);
3808 if (priv->regs == NULL) {
3809 printk(KERN_ERR "%s: Cannot map device registers\n",
3810 wiphy_name(hw->wiphy));
3811 goto err_iounmap;
3812 }
3813 }
3814
be695fc4
LB
3815
3816 /* Reset firmware and hardware */
3817 mwl8k_hw_reset(priv);
3818
3819 /* Ask userland hotplug daemon for the device firmware */
3820 rc = mwl8k_request_firmware(priv);
3821 if (rc) {
3822 printk(KERN_ERR "%s: Firmware files not found\n",
3823 wiphy_name(hw->wiphy));
3824 goto err_stop_firmware;
3825 }
3826
3827 /* Load firmware into hardware */
3828 rc = mwl8k_load_firmware(hw);
3829 if (rc) {
3830 printk(KERN_ERR "%s: Cannot start firmware\n",
3831 wiphy_name(hw->wiphy));
3832 goto err_stop_firmware;
3833 }
3834
3835 /* Reclaim memory once firmware is successfully loaded */
3836 mwl8k_release_firmware(priv);
3837
3838
91942230 3839 if (priv->ap_fw) {
89a91f4f 3840 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230
LB
3841 if (priv->rxd_ops == NULL) {
3842 printk(KERN_ERR "%s: Driver does not have AP "
3843 "firmware image support for this hardware\n",
3844 wiphy_name(hw->wiphy));
3845 goto err_stop_firmware;
3846 }
3847 } else {
89a91f4f 3848 priv->rxd_ops = &rxd_sta_ops;
91942230 3849 }
be695fc4
LB
3850
3851 priv->sniffer_enabled = false;
3852 priv->wmm_enabled = false;
3853 priv->pending_tx_pkts = 0;
3854
3855
777ad375
LB
3856 memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
3857 priv->band_24.band = IEEE80211_BAND_2GHZ;
3858 priv->band_24.channels = priv->channels_24;
3859 priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
3860 priv->band_24.bitrates = priv->rates_24;
3861 priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
3862 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24;
a66098da 3863
777ad375
LB
3864 BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
3865 memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
a66098da
LB
3866
3867 /*
3868 * Extra headroom is the size of the required DMA header
3869 * minus the size of the smallest 802.11 frame (CTS frame).
3870 */
3871 hw->extra_tx_headroom =
3872 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3873
3874 hw->channel_change_time = 10;
3875
3876 hw->queues = MWL8K_TX_QUEUES;
3877
a66098da 3878 /* Set rssi and noise values to dBm */
ce9e2e1b 3879 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da 3880 hw->vif_data_size = sizeof(struct mwl8k_vif);
a680400e 3881 hw->sta_data_size = sizeof(struct mwl8k_sta);
a66098da
LB
3882 priv->vif = NULL;
3883
3884 /* Set default radio state and preamble */
c46563b7 3885 priv->radio_on = 0;
68ce3884 3886 priv->radio_short_preamble = 0;
a66098da 3887
bbfd9128
LB
3888 /* Station database handling */
3889 INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
3890 spin_lock_init(&priv->sta_notify_list_lock);
3891 INIT_LIST_HEAD(&priv->sta_notify_list);
3892
a66098da
LB
3893 /* Finalize join worker */
3894 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3895
67e2eb27 3896 /* TX reclaim and RX tasklets. */
1e9f9de3
LB
3897 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
3898 tasklet_disable(&priv->poll_tx_task);
67e2eb27
LB
3899 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
3900 tasklet_disable(&priv->poll_rx_task);
a66098da 3901
a66098da
LB
3902 /* Power management cookie */
3903 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3904 if (priv->cookie == NULL)
be695fc4 3905 goto err_stop_firmware;
a66098da
LB
3906
3907 rc = mwl8k_rxq_init(hw, 0);
3908 if (rc)
be695fc4 3909 goto err_free_cookie;
a66098da
LB
3910 rxq_refill(hw, 0, INT_MAX);
3911
618952a7
LB
3912 mutex_init(&priv->fw_mutex);
3913 priv->fw_mutex_owner = NULL;
3914 priv->fw_mutex_depth = 0;
618952a7
LB
3915 priv->hostcmd_wait = NULL;
3916
a66098da
LB
3917 spin_lock_init(&priv->tx_lock);
3918
88de754a
LB
3919 priv->tx_wait = NULL;
3920
a66098da
LB
3921 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3922 rc = mwl8k_txq_init(hw, i);
3923 if (rc)
3924 goto err_free_queues;
3925 }
3926
3927 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3928 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
67e2eb27 3929 iowrite32(MWL8K_A2H_INT_TX_DONE | MWL8K_A2H_INT_RX_READY,
1e9f9de3 3930 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
a66098da
LB
3931 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3932
a0607fd3 3933 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB
3934 IRQF_SHARED, MWL8K_NAME, hw);
3935 if (rc) {
3936 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3937 wiphy_name(hw->wiphy));
a66098da
LB
3938 goto err_free_queues;
3939 }
3940
a66098da
LB
3941 /*
3942 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 3943 * commands use interrupts and avoid polling. Disable
a66098da
LB
3944 * interrupts when done.
3945 */
c23b5a69 3946 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB
3947
3948 /* Get config data, mac addrs etc */
42fba21d
LB
3949 if (priv->ap_fw) {
3950 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3951 if (!rc)
3952 rc = mwl8k_cmd_set_hw_spec(hw);
b64fe619
LB
3953
3954 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_AP);
42fba21d
LB
3955 } else {
3956 rc = mwl8k_cmd_get_hw_spec_sta(hw);
89a91f4f
LB
3957
3958 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
42fba21d 3959 }
a66098da 3960 if (rc) {
c2c357ce
LB
3961 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3962 wiphy_name(hw->wiphy));
be695fc4 3963 goto err_free_irq;
a66098da
LB
3964 }
3965
3966 /* Turn radio off */
55489b6e 3967 rc = mwl8k_cmd_radio_disable(hw);
a66098da 3968 if (rc) {
c2c357ce 3969 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
be695fc4 3970 goto err_free_irq;
a66098da
LB
3971 }
3972
32060e1b 3973 /* Clear MAC address */
55489b6e 3974 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b
LB
3975 if (rc) {
3976 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3977 wiphy_name(hw->wiphy));
be695fc4 3978 goto err_free_irq;
32060e1b
LB
3979 }
3980
a66098da 3981 /* Disable interrupts */
a66098da 3982 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB
3983 free_irq(priv->pdev->irq, hw);
3984
3985 rc = ieee80211_register_hw(hw);
3986 if (rc) {
c2c357ce
LB
3987 printk(KERN_ERR "%s: Cannot register device\n",
3988 wiphy_name(hw->wiphy));
153458ff 3989 goto err_free_queues;
a66098da
LB
3990 }
3991
eae74e65 3992 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3993 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3994 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3995 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB
3996 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3997 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB
3998
3999 return 0;
4000
a66098da 4001err_free_irq:
a66098da 4002 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB
4003 free_irq(priv->pdev->irq, hw);
4004
4005err_free_queues:
4006 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4007 mwl8k_txq_deinit(hw, i);
4008 mwl8k_rxq_deinit(hw, 0);
4009
be695fc4 4010err_free_cookie:
a66098da
LB
4011 if (priv->cookie != NULL)
4012 pci_free_consistent(priv->pdev, 4,
4013 priv->cookie, priv->cookie_dma);
4014
be695fc4
LB
4015err_stop_firmware:
4016 mwl8k_hw_reset(priv);
4017 mwl8k_release_firmware(priv);
4018
4019err_iounmap:
a66098da
LB
4020 if (priv->regs != NULL)
4021 pci_iounmap(pdev, priv->regs);
4022
5b9482dd
LB
4023 if (priv->sram != NULL)
4024 pci_iounmap(pdev, priv->sram);
4025
a66098da
LB
4026 pci_set_drvdata(pdev, NULL);
4027 ieee80211_free_hw(hw);
4028
4029err_free_reg:
4030 pci_release_regions(pdev);
3db95e50
LB
4031
4032err_disable_device:
a66098da
LB
4033 pci_disable_device(pdev);
4034
4035 return rc;
4036}
4037
230f7af0 4038static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB
4039{
4040 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
4041}
4042
230f7af0 4043static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB
4044{
4045 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
4046 struct mwl8k_priv *priv;
4047 int i;
4048
4049 if (hw == NULL)
4050 return;
4051 priv = hw->priv;
4052
4053 ieee80211_stop_queues(hw);
4054
60aa569f
LB
4055 ieee80211_unregister_hw(hw);
4056
67e2eb27 4057 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 4058 tasklet_kill(&priv->poll_tx_task);
67e2eb27 4059 tasklet_kill(&priv->poll_rx_task);
a66098da 4060
a66098da
LB
4061 /* Stop hardware */
4062 mwl8k_hw_reset(priv);
4063
4064 /* Return all skbs to mac80211 */
4065 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 4066 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 4067
a66098da
LB
4068 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4069 mwl8k_txq_deinit(hw, i);
4070
4071 mwl8k_rxq_deinit(hw, 0);
4072
c2c357ce 4073 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB
4074
4075 pci_iounmap(pdev, priv->regs);
5b9482dd 4076 pci_iounmap(pdev, priv->sram);
a66098da
LB
4077 pci_set_drvdata(pdev, NULL);
4078 ieee80211_free_hw(hw);
4079 pci_release_regions(pdev);
4080 pci_disable_device(pdev);
4081}
4082
4083static struct pci_driver mwl8k_driver = {
4084 .name = MWL8K_NAME,
45a390dd 4085 .id_table = mwl8k_pci_id_table,
a66098da
LB
4086 .probe = mwl8k_probe,
4087 .remove = __devexit_p(mwl8k_remove),
4088 .shutdown = __devexit_p(mwl8k_shutdown),
4089};
4090
4091static int __init mwl8k_init(void)
4092{
4093 return pci_register_driver(&mwl8k_driver);
4094}
4095
4096static void __exit mwl8k_exit(void)
4097{
4098 pci_unregister_driver(&mwl8k_driver);
4099}
4100
4101module_init(mwl8k_init);
4102module_exit(mwl8k_exit);
c2c357ce
LB
4103
4104MODULE_DESCRIPTION(MWL8K_DESC);
4105MODULE_VERSION(MWL8K_VERSION);
4106MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
4107MODULE_LICENSE("GPL");
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