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ath5k: improve comments for optimized tx descriptor setup
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a5fb297d 5 * Copyright (C) 2008, 2009, 2010 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
5a0e3ad6 22#include <linux/slab.h>
a66098da
LB		 23#include <net/mac80211.h>
24#include <linux/moduleparam.h>
25#include <linux/firmware.h>
26#include <linux/workqueue.h>
27
28#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
29#define MWL8K_NAME KBUILD_MODNAME
a5fb297d 30#define MWL8K_VERSION "0.12"
a66098da 31
0863ade8
BC		 32/* Module parameters */
33static unsigned ap_mode_default;
34module_param(ap_mode_default, bool, 0);
35MODULE_PARM_DESC(ap_mode_default,
36 "Set to 1 to make ap mode the default instead of sta mode");
37
a66098da
LB		 38/* Register definitions */
39#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 40#define MWL8K_MODE_STA 0x0000005a
41#define MWL8K_MODE_AP 0x000000a5
a66098da 42#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 43#define MWL8K_FWSTA_READY 0xf0f1f2f4
44#define MWL8K_FWAP_READY 0xf1f2f4a5
45#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 46#define MWL8K_HIU_SCRATCH 0x00000c40
47
48/* Host->device communications */
49#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
50#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
51#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
52#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
53#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 54#define MWL8K_H2A_INT_DUMMY (1 << 20)
55#define MWL8K_H2A_INT_RESET (1 << 15)
56#define MWL8K_H2A_INT_DOORBELL (1 << 1)
57#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 58
59/* Device->host communications */
60#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
61#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
62#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
63#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
64#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b 65#define MWL8K_A2H_INT_DUMMY (1 << 20)
3aefc37e 66#define MWL8K_A2H_INT_BA_WATCHDOG (1 << 14)
ce9e2e1b
LB		 67#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
68#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
69#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
70#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
71#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
72#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
73#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
74#define MWL8K_A2H_INT_RX_READY (1 << 1)
75#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 76
77#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
78 MWL8K_A2H_INT_CHNL_SWITCHED | \
79 MWL8K_A2H_INT_QUEUE_EMPTY | \
80 MWL8K_A2H_INT_RADAR_DETECT | \
81 MWL8K_A2H_INT_RADIO_ON | \
82 MWL8K_A2H_INT_RADIO_OFF | \
83 MWL8K_A2H_INT_MAC_EVENT | \
84 MWL8K_A2H_INT_OPC_DONE | \
85 MWL8K_A2H_INT_RX_READY | \
3aefc37e
NS		 86 MWL8K_A2H_INT_TX_DONE | \
87 MWL8K_A2H_INT_BA_WATCHDOG)
a66098da 88
a66098da 89#define MWL8K_RX_QUEUES 1
e600707b 90#define MWL8K_TX_WMM_QUEUES 4
8a7a578c 91#define MWL8K_MAX_AMPDU_QUEUES 8
e600707b
BC		 92#define MWL8K_MAX_TX_QUEUES (MWL8K_TX_WMM_QUEUES + MWL8K_MAX_AMPDU_QUEUES)
93#define mwl8k_tx_queues(priv) (MWL8K_TX_WMM_QUEUES + (priv)->num_ampdu_queues)
a66098da 94
54bc3a0d
LB		 95struct rxd_ops {
96 int rxd_size;
97 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
98 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d 99 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
0d462bbb 100 __le16 *qos, s8 *noise);
54bc3a0d
LB		 101};
102
45a390dd 103struct mwl8k_device_info {
a74b295e
LB		 104 char *part_name;
105 char *helper_image;
0863ade8
BC		 106 char *fw_image_sta;
107 char *fw_image_ap;
89a91f4f 108 struct rxd_ops *ap_rxd_ops;
952a0e96 109 u32 fw_api_ap;
45a390dd
LB		 110};
111
a66098da 112struct mwl8k_rx_queue {
45eb400d 113 int rxd_count;
a66098da
LB		 114
115 /* hw receives here */
45eb400d 116 int head;
a66098da
LB		 117
118 /* refill descs here */
45eb400d 119 int tail;
a66098da 120
54bc3a0d 121 void *rxd;
45eb400d 122 dma_addr_t rxd_dma;
788838eb
LB		 123 struct {
124 struct sk_buff *skb;
53b1b3e1 125 DEFINE_DMA_UNMAP_ADDR(dma);
788838eb 126 } *buf;
a66098da
LB		 127};
128
a66098da
LB		 129struct mwl8k_tx_queue {
130 /* hw transmits here */
45eb400d 131 int head;
a66098da
LB		 132
133 /* sw appends here */
45eb400d 134 int tail;
a66098da 135
8ccbc3b8 136 unsigned int len;
45eb400d
LB		 137 struct mwl8k_tx_desc *txd;
138 dma_addr_t txd_dma;
139 struct sk_buff **skb;
a66098da
LB		 140};
141
ac109fd0
BC		 142enum {
143 AMPDU_NO_STREAM,
144 AMPDU_STREAM_NEW,
145 AMPDU_STREAM_IN_PROGRESS,
146 AMPDU_STREAM_ACTIVE,
147};
148
5faa1aff
NS		 149struct mwl8k_ampdu_stream {
150 struct ieee80211_sta *sta;
151 u8 tid;
152 u8 state;
153 u8 idx;
154 u8 txq_idx; /* index of this stream in priv->txq */
155};
156
a66098da 157struct mwl8k_priv {
a66098da 158 struct ieee80211_hw *hw;
a66098da 159 struct pci_dev *pdev;
bf3ca7f7 160 int irq;
a66098da 161
45a390dd
LB		 162 struct mwl8k_device_info *device_info;
163
be695fc4
LB		 164 void __iomem *sram;
165 void __iomem *regs;
166
167 /* firmware */
d1f9e41d
BC		 168 const struct firmware *fw_helper;
169 const struct firmware *fw_ucode;
a66098da 170
be695fc4
LB		 171 /* hardware/firmware parameters */
172 bool ap_fw;
173 struct rxd_ops *rxd_ops;
777ad375
LB		 174 struct ieee80211_supported_band band_24;
175 struct ieee80211_channel channels_24[14];
176 struct ieee80211_rate rates_24[14];
4eae9edd
LB		 177 struct ieee80211_supported_band band_50;
178 struct ieee80211_channel channels_50[4];
179 struct ieee80211_rate rates_50[9];
ee0ddf18
LB		 180 u32 ap_macids_supported;
181 u32 sta_macids_supported;
be695fc4 182
8a7a578c
BC		 183 /* Ampdu stream information */
184 u8 num_ampdu_queues;
ac109fd0
BC		 185 spinlock_t stream_lock;
186 struct mwl8k_ampdu_stream ampdu[MWL8K_MAX_AMPDU_QUEUES];
3aefc37e 187 struct work_struct watchdog_ba_handle;
8a7a578c 188
618952a7
LB		 189 /* firmware access */
190 struct mutex fw_mutex;
191 struct task_struct *fw_mutex_owner;
192 int fw_mutex_depth;
618952a7
LB		 193 struct completion *hostcmd_wait;
194
a66098da
LB		 195 /* lock held over TX and TX reap */
196 spinlock_t tx_lock;
a66098da 197
88de754a
LB		 198 /* TX quiesce completion, protected by fw_mutex and tx_lock */
199 struct completion *tx_wait;
200
f5bb87cf 201 /* List of interfaces. */
ee0ddf18 202 u32 macids_used;
f5bb87cf 203 struct list_head vif_list;
a66098da 204
a66098da
LB		 205 /* power management status cookie from firmware */
206 u32 *cookie;
207 dma_addr_t cookie_dma;
208
209 u16 num_mcaddrs;
a66098da 210 u8 hw_rev;
2aa7b01f 211 u32 fw_rev;
a66098da
LB		 212
213 /*
214 * Running count of TX packets in flight, to avoid
215 * iterating over the transmit rings each time.
216 */
217 int pending_tx_pkts;
218
219 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
e600707b
BC		 220 struct mwl8k_tx_queue txq[MWL8K_MAX_TX_QUEUES];
221 u32 txq_offset[MWL8K_MAX_TX_QUEUES];
a66098da 222
c46563b7 223 bool radio_on;
68ce3884 224 bool radio_short_preamble;
a43c49a8 225 bool sniffer_enabled;
0439b1f5 226 bool wmm_enabled;
a66098da 227
a66098da
LB		 228 /* XXX need to convert this to handle multiple interfaces */
229 bool capture_beacon;
d89173f2 230 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 231 struct sk_buff *beacon_skb;
232
233 /*
234 * This FJ worker has to be global as it is scheduled from the
235 * RX handler. At this point we don't know which interface it
236 * belongs to until the list of bssids waiting to complete join
237 * is checked.
238 */
239 struct work_struct finalize_join_worker;
240
1e9f9de3
LB		 241 /* Tasklet to perform TX reclaim. */
242 struct tasklet_struct poll_tx_task;
67e2eb27
LB		 243
244 /* Tasklet to perform RX. */
245 struct tasklet_struct poll_rx_task;
0d462bbb
JL		 246
247 /* Most recently reported noise in dBm */
248 s8 noise;
0863ade8
BC		 249
250 /*
251 * preserve the queue configurations so they can be restored if/when
252 * the firmware image is swapped.
253 */
e600707b 254 struct ieee80211_tx_queue_params wmm_params[MWL8K_TX_WMM_QUEUES];
99020471
BC		 255
256 /* async firmware loading state */
257 unsigned fw_state;
258 char *fw_pref;
259 char *fw_alt;
260 struct completion firmware_loading_complete;
a66098da
LB		 261};
262
e53d9b96
NS		 263#define MAX_WEP_KEY_LEN 13
264#define NUM_WEP_KEYS 4
265
a66098da
LB		 266/* Per interface specific private data */
267struct mwl8k_vif {
f5bb87cf
LB		 268 struct list_head list;
269 struct ieee80211_vif *vif;
270
f57ca9c1
LB		 271 /* Firmware macid for this vif. */
272 int macid;
273
c2c2b12a 274 /* Non AMPDU sequence number assigned by driver. */
a680400e 275 u16 seqno;
e53d9b96
NS		 276
277 /* Saved WEP keys */
278 struct {
279 u8 enabled;
280 u8 key[sizeof(struct ieee80211_key_conf) + MAX_WEP_KEY_LEN];
281 } wep_key_conf[NUM_WEP_KEYS];
d9a07d49
NS		 282
283 /* BSSID */
284 u8 bssid[ETH_ALEN];
285
286 /* A flag to indicate is HW crypto is enabled for this bssid */
287 bool is_hw_crypto_enabled;
a66098da 288};
a94cc97e 289#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
fcdc403c 290#define IEEE80211_KEY_CONF(_u8) ((struct ieee80211_key_conf *)(_u8))
a66098da 291
a680400e
LB		 292struct mwl8k_sta {
293 /* Index into station database. Returned by UPDATE_STADB. */
294 u8 peer_id;
17033543 295 u8 is_ampdu_allowed;
a680400e
LB		 296};
297#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
298
777ad375 299static const struct ieee80211_channel mwl8k_channels_24[] = {
a66098da
LB		 300 { .center_freq = 2412, .hw_value = 1, },
301 { .center_freq = 2417, .hw_value = 2, },
302 { .center_freq = 2422, .hw_value = 3, },
303 { .center_freq = 2427, .hw_value = 4, },
304 { .center_freq = 2432, .hw_value = 5, },
305 { .center_freq = 2437, .hw_value = 6, },
306 { .center_freq = 2442, .hw_value = 7, },
307 { .center_freq = 2447, .hw_value = 8, },
308 { .center_freq = 2452, .hw_value = 9, },
309 { .center_freq = 2457, .hw_value = 10, },
310 { .center_freq = 2462, .hw_value = 11, },
647ca6b0
LB		 311 { .center_freq = 2467, .hw_value = 12, },
312 { .center_freq = 2472, .hw_value = 13, },
313 { .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 314};
315
777ad375 316static const struct ieee80211_rate mwl8k_rates_24[] = {
a66098da
LB		 317 { .bitrate = 10, .hw_value = 2, },
318 { .bitrate = 20, .hw_value = 4, },
319 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 320 { .bitrate = 110, .hw_value = 22, },
321 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 322 { .bitrate = 60, .hw_value = 12, },
323 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 324 { .bitrate = 120, .hw_value = 24, },
325 { .bitrate = 180, .hw_value = 36, },
326 { .bitrate = 240, .hw_value = 48, },
327 { .bitrate = 360, .hw_value = 72, },
328 { .bitrate = 480, .hw_value = 96, },
329 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 330 { .bitrate = 720, .hw_value = 144, },
331};
332
4eae9edd
LB		 333static const struct ieee80211_channel mwl8k_channels_50[] = {
334 { .center_freq = 5180, .hw_value = 36, },
335 { .center_freq = 5200, .hw_value = 40, },
336 { .center_freq = 5220, .hw_value = 44, },
337 { .center_freq = 5240, .hw_value = 48, },
338};
339
340static const struct ieee80211_rate mwl8k_rates_50[] = {
341 { .bitrate = 60, .hw_value = 12, },
342 { .bitrate = 90, .hw_value = 18, },
343 { .bitrate = 120, .hw_value = 24, },
344 { .bitrate = 180, .hw_value = 36, },
345 { .bitrate = 240, .hw_value = 48, },
346 { .bitrate = 360, .hw_value = 72, },
347 { .bitrate = 480, .hw_value = 96, },
348 { .bitrate = 540, .hw_value = 108, },
349 { .bitrate = 720, .hw_value = 144, },
350};
351
a66098da 352/* Set or get info from Firmware */
a66098da 353#define MWL8K_CMD_GET 0x0000
41fdf097
NS		 354#define MWL8K_CMD_SET 0x0001
355#define MWL8K_CMD_SET_LIST 0x0002
a66098da
LB		 356
357/* Firmware command codes */
358#define MWL8K_CMD_CODE_DNLD 0x0001
359#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 360#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 361#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
362#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 363#define MWL8K_CMD_RADIO_CONTROL 0x001c
364#define MWL8K_CMD_RF_TX_POWER 0x001e
41fdf097 365#define MWL8K_CMD_TX_POWER 0x001f
08b06347 366#define MWL8K_CMD_RF_ANTENNA 0x0020
aa21d0f6 367#define MWL8K_CMD_SET_BEACON 0x0100 /* per-vif */
a66098da
LB		 368#define MWL8K_CMD_SET_PRE_SCAN 0x0107
369#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 370#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
371#define MWL8K_CMD_SET_AID 0x010d
372#define MWL8K_CMD_SET_RATE 0x0110
373#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
374#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 375#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 376#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
377#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 378#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 379#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 380#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
aa21d0f6 381#define MWL8K_CMD_SET_MAC_ADDR 0x0202 /* per-vif */
a66098da 382#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
3aefc37e 383#define MWL8K_CMD_GET_WATCHDOG_BITMAP 0x0205
aa21d0f6
LB		 384#define MWL8K_CMD_BSS_START 0x1100 /* per-vif */
385#define MWL8K_CMD_SET_NEW_STN 0x1111 /* per-vif */
fcdc403c 386#define MWL8K_CMD_UPDATE_ENCRYPTION 0x1122 /* per-vif */
ff45fc60 387#define MWL8K_CMD_UPDATE_STADB 0x1123
5faa1aff 388#define MWL8K_CMD_BASTREAM 0x1125
a66098da 389
b603742f 390static const char *mwl8k_cmd_name(__le16 cmd, char *buf, int bufsize)
a66098da 391{
b603742f
JL		 392 u16 command = le16_to_cpu(cmd);
393
a66098da
LB		 394#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
395 snprintf(buf, bufsize, "%s", #x);\
396 return buf;\
397 } while (0)
b603742f 398 switch (command & ~0x8000) {
a66098da
LB		 399 MWL8K_CMDNAME(CODE_DNLD);
400 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 401 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 402 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
403 MWL8K_CMDNAME(GET_STAT);
404 MWL8K_CMDNAME(RADIO_CONTROL);
405 MWL8K_CMDNAME(RF_TX_POWER);
41fdf097 406 MWL8K_CMDNAME(TX_POWER);
08b06347 407 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 408 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB		 409 MWL8K_CMDNAME(SET_PRE_SCAN);
410 MWL8K_CMDNAME(SET_POST_SCAN);
411 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 412 MWL8K_CMDNAME(SET_AID);
413 MWL8K_CMDNAME(SET_RATE);
414 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
415 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 416 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 417 MWL8K_CMDNAME(SET_EDCA_PARAMS);
418 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 419 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 420 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 421 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 422 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 423 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 424 MWL8K_CMDNAME(BSS_START);
3f5610ff 425 MWL8K_CMDNAME(SET_NEW_STN);
fcdc403c 426 MWL8K_CMDNAME(UPDATE_ENCRYPTION);
ff45fc60 427 MWL8K_CMDNAME(UPDATE_STADB);
5faa1aff 428 MWL8K_CMDNAME(BASTREAM);
3aefc37e 429 MWL8K_CMDNAME(GET_WATCHDOG_BITMAP);
a66098da
LB		 430 default:
431 snprintf(buf, bufsize, "0x%x", cmd);
432 }
433#undef MWL8K_CMDNAME
434
435 return buf;
436}
437
438/* Hardware and firmware reset */
439static void mwl8k_hw_reset(struct mwl8k_priv *priv)
440{
441 iowrite32(MWL8K_H2A_INT_RESET,
442 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
443 iowrite32(MWL8K_H2A_INT_RESET,
444 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
445 msleep(20);
446}
447
448/* Release fw image */
d1f9e41d 449static void mwl8k_release_fw(const struct firmware **fw)
a66098da
LB		 450{
451 if (*fw == NULL)
452 return;
453 release_firmware(*fw);
454 *fw = NULL;
455}
456
457static void mwl8k_release_firmware(struct mwl8k_priv *priv)
458{
22be40d9
LB		 459 mwl8k_release_fw(&priv->fw_ucode);
460 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 461}
462
99020471
BC		 463/* states for asynchronous f/w loading */
464static void mwl8k_fw_state_machine(const struct firmware *fw, void *context);
465enum {
466 FW_STATE_INIT = 0,
467 FW_STATE_LOADING_PREF,
468 FW_STATE_LOADING_ALT,
469 FW_STATE_ERROR,
470};
471
a66098da
LB		 472/* Request fw image */
473static int mwl8k_request_fw(struct mwl8k_priv *priv,
d1f9e41d 474 const char *fname, const struct firmware **fw,
99020471 475 bool nowait)
a66098da
LB		 476{
477 /* release current image */
478 if (*fw != NULL)
479 mwl8k_release_fw(fw);
480
99020471
BC		 481 if (nowait)
482 return request_firmware_nowait(THIS_MODULE, 1, fname,
483 &priv->pdev->dev, GFP_KERNEL,
484 priv, mwl8k_fw_state_machine);
485 else
d1f9e41d 486 return request_firmware(fw, fname, &priv->pdev->dev);
a66098da
LB		 487}
488
99020471
BC		 489static int mwl8k_request_firmware(struct mwl8k_priv *priv, char *fw_image,
490 bool nowait)
a66098da 491{
a74b295e 492 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 493 int rc;
494
a74b295e 495 if (di->helper_image != NULL) {
99020471
BC		 496 if (nowait)
497 rc = mwl8k_request_fw(priv, di->helper_image,
498 &priv->fw_helper, true);
499 else
500 rc = mwl8k_request_fw(priv, di->helper_image,
501 &priv->fw_helper, false);
502 if (rc)
503 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
504 pci_name(priv->pdev), di->helper_image);
505
506 if (rc || nowait)
a74b295e 507 return rc;
a66098da
LB		 508 }
509
99020471
BC		 510 if (nowait) {
511 /*
512 * if we get here, no helper image is needed. Skip the
513 * FW_STATE_INIT state.
514 */
515 priv->fw_state = FW_STATE_LOADING_PREF;
516 rc = mwl8k_request_fw(priv, fw_image,
517 &priv->fw_ucode,
518 true);
519 } else
520 rc = mwl8k_request_fw(priv, fw_image,
521 &priv->fw_ucode, false);
a66098da 522 if (rc) {
c2c357ce 523 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
0863ade8 524 pci_name(priv->pdev), fw_image);
22be40d9 525 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 526 return rc;
527 }
528
529 return 0;
530}
531
532struct mwl8k_cmd_pkt {
533 __le16 code;
534 __le16 length;
f57ca9c1
LB		 535 __u8 seq_num;
536 __u8 macid;
a66098da
LB		 537 __le16 result;
538 char payload[0];
ba2d3587 539} __packed;
a66098da
LB		 540
541/*
542 * Firmware loading.
543 */
544static int
545mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
546{
547 void __iomem *regs = priv->regs;
548 dma_addr_t dma_addr;
a66098da
LB		 549 int loops;
550
551 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
552 if (pci_dma_mapping_error(priv->pdev, dma_addr))
553 return -ENOMEM;
554
555 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
556 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
557 iowrite32(MWL8K_H2A_INT_DOORBELL,
558 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
559 iowrite32(MWL8K_H2A_INT_DUMMY,
560 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
561
a66098da
LB		 562 loops = 1000;
563 do {
564 u32 int_code;
565
566 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
567 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
568 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 569 break;
570 }
571
3d76e82c 572 cond_resched();
a66098da
LB		 573 udelay(1);
574 } while (--loops);
575
576 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
577
d4b70570 578 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 579}
580
581static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
582 const u8 *data, size_t length)
583{
584 struct mwl8k_cmd_pkt *cmd;
585 int done;
586 int rc = 0;
587
588 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
589 if (cmd == NULL)
590 return -ENOMEM;
591
592 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
593 cmd->seq_num = 0;
f57ca9c1 594 cmd->macid = 0;
a66098da
LB		 595 cmd->result = 0;
596
597 done = 0;
598 while (length) {
599 int block_size = length > 256 ? 256 : length;
600
601 memcpy(cmd->payload, data + done, block_size);
602 cmd->length = cpu_to_le16(block_size);
603
604 rc = mwl8k_send_fw_load_cmd(priv, cmd,
605 sizeof(*cmd) + block_size);
606 if (rc)
607 break;
608
609 done += block_size;
610 length -= block_size;
611 }
612
613 if (!rc) {
614 cmd->length = 0;
615 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
616 }
617
618 kfree(cmd);
619
620 return rc;
621}
622
623static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
624 const u8 *data, size_t length)
625{
626 unsigned char *buffer;
627 int may_continue, rc = 0;
628 u32 done, prev_block_size;
629
630 buffer = kmalloc(1024, GFP_KERNEL);
631 if (buffer == NULL)
632 return -ENOMEM;
633
634 done = 0;
635 prev_block_size = 0;
636 may_continue = 1000;
637 while (may_continue > 0) {
638 u32 block_size;
639
640 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
641 if (block_size & 1) {
642 block_size &= ~1;
643 may_continue--;
644 } else {
645 done += prev_block_size;
646 length -= prev_block_size;
647 }
648
649 if (block_size > 1024 || block_size > length) {
650 rc = -EOVERFLOW;
651 break;
652 }
653
654 if (length == 0) {
655 rc = 0;
656 break;
657 }
658
659 if (block_size == 0) {
660 rc = -EPROTO;
661 may_continue--;
662 udelay(1);
663 continue;
664 }
665
666 prev_block_size = block_size;
667 memcpy(buffer, data + done, block_size);
668
669 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
670 if (rc)
671 break;
672 }
673
674 if (!rc && length != 0)
675 rc = -EREMOTEIO;
676
677 kfree(buffer);
678
679 return rc;
680}
681
c2c357ce 682static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 683{
c2c357ce 684 struct mwl8k_priv *priv = hw->priv;
d1f9e41d 685 const struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 686 int rc;
687 int loops;
688
689 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
d1f9e41d 690 const struct firmware *helper = priv->fw_helper;
a66098da 691
c2c357ce
LB		 692 if (helper == NULL) {
693 printk(KERN_ERR "%s: helper image needed but none "
694 "given\n", pci_name(priv->pdev));
695 return -EINVAL;
696 }
a66098da 697
c2c357ce 698 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 699 if (rc) {
700 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 701 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 702 return rc;
703 }
ba30c4a5 704 msleep(20);
a66098da 705
c2c357ce 706 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 707 } else {
c2c357ce 708 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 709 }
710
711 if (rc) {
c2c357ce
LB		 712 printk(KERN_ERR "%s: unable to load firmware image\n",
713 pci_name(priv->pdev));
a66098da
LB		 714 return rc;
715 }
716
89a91f4f 717 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 718
89b872e2 719 loops = 500000;
a66098da 720 do {
eae74e65
LB		 721 u32 ready_code;
722
723 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
724 if (ready_code == MWL8K_FWAP_READY) {
725 priv->ap_fw = 1;
726 break;
727 } else if (ready_code == MWL8K_FWSTA_READY) {
728 priv->ap_fw = 0;
a66098da 729 break;
eae74e65
LB		 730 }
731
732 cond_resched();
a66098da
LB		 733 udelay(1);
734 } while (--loops);
735
736 return loops ? 0 : -ETIMEDOUT;
737}
738
739
a66098da
LB		 740/* DMA header used by firmware and hardware. */
741struct mwl8k_dma_data {
742 __le16 fwlen;
743 struct ieee80211_hdr wh;
20f09c3d 744 char data[0];
ba2d3587 745} __packed;
a66098da
LB		 746
747/* Routines to add/remove DMA header from skb. */
20f09c3d 748static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 749{
20f09c3d
LB		 750 struct mwl8k_dma_data *tr;
751 int hdrlen;
752
753 tr = (struct mwl8k_dma_data *)skb->data;
754 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
755
756 if (hdrlen != sizeof(tr->wh)) {
757 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
758 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
759 *((__le16 *)(tr->data - 2)) = qos;
760 } else {
761 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
762 }
a66098da 763 }
20f09c3d
LB		 764
765 if (hdrlen != sizeof(*tr))
766 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 767}
768
252486a1
NS		 769static void
770mwl8k_add_dma_header(struct sk_buff *skb, int tail_pad)
a66098da
LB		 771{
772 struct ieee80211_hdr *wh;
ca009301 773 int hdrlen;
252486a1 774 int reqd_hdrlen;
a66098da
LB		 775 struct mwl8k_dma_data *tr;
776
ca009301
LB		 777 /*
778 * Add a firmware DMA header; the firmware requires that we
779 * present a 2-byte payload length followed by a 4-address
780 * header (without QoS field), followed (optionally) by any
781 * WEP/ExtIV header (but only filled in for CCMP).
782 */
a66098da 783 wh = (struct ieee80211_hdr *)skb->data;
ca009301 784
a66098da 785 hdrlen = ieee80211_hdrlen(wh->frame_control);
252486a1
NS		 786 reqd_hdrlen = sizeof(*tr);
787
788 if (hdrlen != reqd_hdrlen)
789 skb_push(skb, reqd_hdrlen - hdrlen);
a66098da 790
ca009301 791 if (ieee80211_is_data_qos(wh->frame_control))
252486a1 792 hdrlen -= IEEE80211_QOS_CTL_LEN;
a66098da
LB		 793
794 tr = (struct mwl8k_dma_data *)skb->data;
795 if (wh != &tr->wh)
796 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 797 if (hdrlen != sizeof(tr->wh))
798 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 799
800 /*
801 * Firmware length is the length of the fully formed "802.11
802 * payload". That is, everything except for the 802.11 header.
803 * This includes all crypto material including the MIC.
804 */
252486a1 805 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr) + tail_pad);
a66098da
LB		 806}
807
e53d9b96
NS		 808static void mwl8k_encapsulate_tx_frame(struct sk_buff *skb)
809{
810 struct ieee80211_hdr *wh;
811 struct ieee80211_tx_info *tx_info;
812 struct ieee80211_key_conf *key_conf;
813 int data_pad;
814
815 wh = (struct ieee80211_hdr *)skb->data;
816
817 tx_info = IEEE80211_SKB_CB(skb);
818
819 key_conf = NULL;
820 if (ieee80211_is_data(wh->frame_control))
821 key_conf = tx_info->control.hw_key;
822
823 /*
824 * Make sure the packet header is in the DMA header format (4-address
825 * without QoS), the necessary crypto padding between the header and the
ba30c4a5
YAP		 826 * payload has already been provided by mac80211, but it doesn't add
827 * tail padding when HW crypto is enabled.
e53d9b96
NS		 828 *
829 * We have the following trailer padding requirements:
830 * - WEP: 4 trailer bytes (ICV)
831 * - TKIP: 12 trailer bytes (8 MIC + 4 ICV)
832 * - CCMP: 8 trailer bytes (MIC)
833 */
834 data_pad = 0;
835 if (key_conf != NULL) {
836 switch (key_conf->cipher) {
837 case WLAN_CIPHER_SUITE_WEP40:
838 case WLAN_CIPHER_SUITE_WEP104:
839 data_pad = 4;
840 break;
841 case WLAN_CIPHER_SUITE_TKIP:
842 data_pad = 12;
843 break;
844 case WLAN_CIPHER_SUITE_CCMP:
845 data_pad = 8;
846 break;
847 }
848 }
849 mwl8k_add_dma_header(skb, data_pad);
850}
a66098da
LB		 851
852/*
89a91f4f 853 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 854 */
89a91f4f 855struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB		 856 __le16 pkt_len;
857 __u8 sq2;
858 __u8 rate;
859 __le32 pkt_phys_addr;
860 __le32 next_rxd_phys_addr;
861 __le16 qos_control;
862 __le16 htsig2;
863 __le32 hw_rssi_info;
864 __le32 hw_noise_floor_info;
865 __u8 noise_floor;
866 __u8 pad0[3];
867 __u8 rssi;
868 __u8 rx_status;
869 __u8 channel;
870 __u8 rx_ctrl;
ba2d3587 871} __packed;
6f6d1e9a 872
89a91f4f
LB		 873#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
874#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
875#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 876
89a91f4f 877#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 878
d9a07d49
NS		 879/* 8366 AP rx_status bits */
880#define MWL8K_8366_AP_RXSTAT_DECRYPT_ERR_MASK 0x80
881#define MWL8K_8366_AP_RXSTAT_GENERAL_DECRYPT_ERR 0xFF
882#define MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR 0x02
883#define MWL8K_8366_AP_RXSTAT_WEP_DECRYPT_ICV_ERR 0x04
884#define MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_ICV_ERR 0x08
885
89a91f4f 886static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 887{
89a91f4f 888 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 889
890 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 891 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 892}
893
89a91f4f 894static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 895{
89a91f4f 896 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 897
898 rxd->pkt_len = cpu_to_le16(len);
899 rxd->pkt_phys_addr = cpu_to_le32(addr);
900 wmb();
901 rxd->rx_ctrl = 0;
902}
903
904static int
89a91f4f 905mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 906 __le16 *qos, s8 *noise)
6f6d1e9a 907{
89a91f4f 908 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 909
89a91f4f 910 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 911 return -1;
912 rmb();
913
914 memset(status, 0, sizeof(*status));
915
916 status->signal = -rxd->rssi;
0d462bbb 917 *noise = -rxd->noise_floor;
6f6d1e9a 918
89a91f4f 919 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 920 status->flag |= RX_FLAG_HT;
89a91f4f 921 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 922 status->flag |= RX_FLAG_40MHZ;
89a91f4f 923 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 924 } else {
925 int i;
926
777ad375
LB		 927 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
928 if (mwl8k_rates_24[i].hw_value == rxd->rate) {
6f6d1e9a
LB		 929 status->rate_idx = i;
930 break;
931 }
932 }
933 }
934
85478344
LB		 935 if (rxd->channel > 14) {
936 status->band = IEEE80211_BAND_5GHZ;
937 if (!(status->flag & RX_FLAG_HT))
938 status->rate_idx -= 5;
939 } else {
940 status->band = IEEE80211_BAND_2GHZ;
941 }
59eb21a6
BR		 942 status->freq = ieee80211_channel_to_frequency(rxd->channel,
943 status->band);
6f6d1e9a 944
20f09c3d
LB		 945 *qos = rxd->qos_control;
946
d9a07d49
NS		 947 if ((rxd->rx_status != MWL8K_8366_AP_RXSTAT_GENERAL_DECRYPT_ERR) &&
948 (rxd->rx_status & MWL8K_8366_AP_RXSTAT_DECRYPT_ERR_MASK) &&
949 (rxd->rx_status & MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR))
950 status->flag |= RX_FLAG_MMIC_ERROR;
951
6f6d1e9a
LB		 952 return le16_to_cpu(rxd->pkt_len);
953}
954
89a91f4f
LB		 955static struct rxd_ops rxd_8366_ap_ops = {
956 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
957 .rxd_init = mwl8k_rxd_8366_ap_init,
958 .rxd_refill = mwl8k_rxd_8366_ap_refill,
959 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB		 960};
961
962/*
89a91f4f 963 * Packet reception for STA firmware.
a66098da 964 */
89a91f4f 965struct mwl8k_rxd_sta {
a66098da
LB		 966 __le16 pkt_len;
967 __u8 link_quality;
968 __u8 noise_level;
969 __le32 pkt_phys_addr;
45eb400d 970 __le32 next_rxd_phys_addr;
a66098da
LB		 971 __le16 qos_control;
972 __le16 rate_info;
973 __le32 pad0[4];
974 __u8 rssi;
975 __u8 channel;
976 __le16 pad1;
977 __u8 rx_ctrl;
978 __u8 rx_status;
979 __u8 pad2[2];
ba2d3587 980} __packed;
a66098da 981
89a91f4f
LB		 982#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
983#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
984#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
985#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
986#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
987#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 988
89a91f4f 989#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
d9a07d49
NS		 990#define MWL8K_STA_RX_CTRL_DECRYPT_ERROR 0x04
991/* ICV=0 or MIC=1 */
992#define MWL8K_STA_RX_CTRL_DEC_ERR_TYPE 0x08
993/* Key is uploaded only in failure case */
994#define MWL8K_STA_RX_CTRL_KEY_INDEX 0x30
54bc3a0d 995
89a91f4f 996static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 997{
89a91f4f 998 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 999
1000 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 1001 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 1002}
1003
89a91f4f 1004static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 1005{
89a91f4f 1006 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1007
1008 rxd->pkt_len = cpu_to_le16(len);
1009 rxd->pkt_phys_addr = cpu_to_le32(addr);
1010 wmb();
1011 rxd->rx_ctrl = 0;
1012}
1013
1014static int
89a91f4f 1015mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 1016 __le16 *qos, s8 *noise)
54bc3a0d 1017{
89a91f4f 1018 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1019 u16 rate_info;
1020
89a91f4f 1021 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 1022 return -1;
1023 rmb();
1024
1025 rate_info = le16_to_cpu(rxd->rate_info);
1026
1027 memset(status, 0, sizeof(*status));
1028
1029 status->signal = -rxd->rssi;
0d462bbb 1030 *noise = -rxd->noise_level;
89a91f4f
LB		 1031 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
1032 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 1033
89a91f4f 1034 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 1035 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 1036 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 1037 status->flag |= RX_FLAG_40MHZ;
89a91f4f 1038 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 1039 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 1040 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 1041 status->flag |= RX_FLAG_HT;
1042
85478344
LB		 1043 if (rxd->channel > 14) {
1044 status->band = IEEE80211_BAND_5GHZ;
1045 if (!(status->flag & RX_FLAG_HT))
1046 status->rate_idx -= 5;
1047 } else {
1048 status->band = IEEE80211_BAND_2GHZ;
1049 }
59eb21a6
BR		 1050 status->freq = ieee80211_channel_to_frequency(rxd->channel,
1051 status->band);
54bc3a0d 1052
20f09c3d 1053 *qos = rxd->qos_control;
d9a07d49
NS		 1054 if ((rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DECRYPT_ERROR) &&
1055 (rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DEC_ERR_TYPE))
1056 status->flag |= RX_FLAG_MMIC_ERROR;
20f09c3d 1057
54bc3a0d
LB		 1058 return le16_to_cpu(rxd->pkt_len);
1059}
1060
89a91f4f
LB		 1061static struct rxd_ops rxd_sta_ops = {
1062 .rxd_size = sizeof(struct mwl8k_rxd_sta),
1063 .rxd_init = mwl8k_rxd_sta_init,
1064 .rxd_refill = mwl8k_rxd_sta_refill,
1065 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 1066};
1067
1068
a66098da
LB		 1069#define MWL8K_RX_DESCS 256
1070#define MWL8K_RX_MAXSZ 3800
1071
1072static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
1073{
1074 struct mwl8k_priv *priv = hw->priv;
1075 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1076 int size;
1077 int i;
1078
45eb400d
LB		 1079 rxq->rxd_count = 0;
1080 rxq->head = 0;
1081 rxq->tail = 0;
a66098da 1082
54bc3a0d 1083 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 1084
45eb400d
LB		 1085 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
1086 if (rxq->rxd == NULL) {
5db55844 1087 wiphy_err(hw->wiphy, "failed to alloc RX descriptors\n");
a66098da
LB		 1088 return -ENOMEM;
1089 }
45eb400d 1090 memset(rxq->rxd, 0, size);
a66098da 1091
b9ede5f1 1092 rxq->buf = kcalloc(MWL8K_RX_DESCS, sizeof(*rxq->buf), GFP_KERNEL);
788838eb 1093 if (rxq->buf == NULL) {
5db55844 1094 wiphy_err(hw->wiphy, "failed to alloc RX skbuff list\n");
45eb400d 1095 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 1096 return -ENOMEM;
1097 }
a66098da
LB		 1098
1099 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 1100 int desc_size;
1101 void *rxd;
a66098da 1102 int nexti;
54bc3a0d
LB		 1103 dma_addr_t next_dma_addr;
1104
1105 desc_size = priv->rxd_ops->rxd_size;
1106 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 1107
54bc3a0d
LB		 1108 nexti = i + 1;
1109 if (nexti == MWL8K_RX_DESCS)
1110 nexti = 0;
1111 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 1112
54bc3a0d 1113 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 1114 }
1115
1116 return 0;
1117}
1118
1119static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1120{
1121 struct mwl8k_priv *priv = hw->priv;
1122 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1123 int refilled;
1124
1125 refilled = 0;
45eb400d 1126 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 1127 struct sk_buff *skb;
788838eb 1128 dma_addr_t addr;
a66098da 1129 int rx;
54bc3a0d 1130 void *rxd;
a66098da
LB		 1131
1132 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1133 if (skb == NULL)
1134 break;
1135
788838eb
LB		 1136 addr = pci_map_single(priv->pdev, skb->data,
1137 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1138
54bc3a0d
LB		 1139 rxq->rxd_count++;
1140 rx = rxq->tail++;
1141 if (rxq->tail == MWL8K_RX_DESCS)
1142 rxq->tail = 0;
788838eb 1143 rxq->buf[rx].skb = skb;
53b1b3e1 1144 dma_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 1145
1146 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1147 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 1148
1149 refilled++;
1150 }
1151
1152 return refilled;
1153}
1154
1155/* Must be called only when the card's reception is completely halted */
1156static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1157{
1158 struct mwl8k_priv *priv = hw->priv;
1159 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1160 int i;
1161
73b46320
BC		 1162 if (rxq->rxd == NULL)
1163 return;
1164
a66098da 1165 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 1166 if (rxq->buf[i].skb != NULL) {
1167 pci_unmap_single(priv->pdev,
53b1b3e1 1168 dma_unmap_addr(&rxq->buf[i], dma),
788838eb 1169 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1170 dma_unmap_addr_set(&rxq->buf[i], dma, 0);
788838eb
LB		 1171
1172 kfree_skb(rxq->buf[i].skb);
1173 rxq->buf[i].skb = NULL;
a66098da
LB		 1174 }
1175 }
1176
788838eb
LB		 1177 kfree(rxq->buf);
1178 rxq->buf = NULL;
a66098da
LB		 1179
1180 pci_free_consistent(priv->pdev,
54bc3a0d 1181 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1182 rxq->rxd, rxq->rxd_dma);
1183 rxq->rxd = NULL;
a66098da
LB		 1184}
1185
1186
1187/*
1188 * Scan a list of BSSIDs to process for finalize join.
1189 * Allows for extension to process multiple BSSIDs.
1190 */
1191static inline int
1192mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1193{
1194 return priv->capture_beacon &&
1195 ieee80211_is_beacon(wh->frame_control) &&
1196 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1197}
1198
3779752d
LB		 1199static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1200 struct sk_buff *skb)
a66098da 1201{
3779752d
LB		 1202 struct mwl8k_priv *priv = hw->priv;
1203
a66098da 1204 priv->capture_beacon = false;
d89173f2 1205 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1206
1207 /*
1208 * Use GFP_ATOMIC as rxq_process is called from
1209 * the primary interrupt handler, memory allocation call
1210 * must not sleep.
1211 */
1212 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1213 if (priv->beacon_skb != NULL)
3779752d 1214 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1215}
1216
d9a07d49
NS		 1217static inline struct mwl8k_vif *mwl8k_find_vif_bss(struct list_head *vif_list,
1218 u8 *bssid)
1219{
1220 struct mwl8k_vif *mwl8k_vif;
1221
1222 list_for_each_entry(mwl8k_vif,
1223 vif_list, list) {
1224 if (memcmp(bssid, mwl8k_vif->bssid,
1225 ETH_ALEN) == 0)
1226 return mwl8k_vif;
1227 }
1228
1229 return NULL;
1230}
1231
a66098da
LB		 1232static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1233{
1234 struct mwl8k_priv *priv = hw->priv;
d9a07d49 1235 struct mwl8k_vif *mwl8k_vif = NULL;
a66098da
LB		 1236 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1237 int processed;
1238
1239 processed = 0;
45eb400d 1240 while (rxq->rxd_count && limit--) {
a66098da 1241 struct sk_buff *skb;
54bc3a0d
LB		 1242 void *rxd;
1243 int pkt_len;
a66098da 1244 struct ieee80211_rx_status status;
d9a07d49 1245 struct ieee80211_hdr *wh;
20f09c3d 1246 __le16 qos;
a66098da 1247
788838eb 1248 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1249 if (skb == NULL)
1250 break;
54bc3a0d
LB		 1251
1252 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1253
0d462bbb
JL		 1254 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos,
1255 &priv->noise);
54bc3a0d
LB		 1256 if (pkt_len < 0)
1257 break;
1258
788838eb
LB		 1259 rxq->buf[rxq->head].skb = NULL;
1260
1261 pci_unmap_single(priv->pdev,
53b1b3e1 1262 dma_unmap_addr(&rxq->buf[rxq->head], dma),
788838eb 1263 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1264 dma_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1265
54bc3a0d
LB		 1266 rxq->head++;
1267 if (rxq->head == MWL8K_RX_DESCS)
1268 rxq->head = 0;
1269
45eb400d 1270 rxq->rxd_count--;
a66098da 1271
d9a07d49 1272 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da 1273
a66098da 1274 /*
c2c357ce
LB		 1275 * Check for a pending join operation. Save a
1276 * copy of the beacon and schedule a tasklet to
1277 * send a FINALIZE_JOIN command to the firmware.
a66098da 1278 */
54bc3a0d 1279 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1280 mwl8k_save_beacon(hw, skb);
a66098da 1281
d9a07d49
NS		 1282 if (ieee80211_has_protected(wh->frame_control)) {
1283
1284 /* Check if hw crypto has been enabled for
1285 * this bss. If yes, set the status flags
1286 * accordingly
1287 */
1288 mwl8k_vif = mwl8k_find_vif_bss(&priv->vif_list,
1289 wh->addr1);
1290
1291 if (mwl8k_vif != NULL &&
1292 mwl8k_vif->is_hw_crypto_enabled == true) {
1293 /*
1294 * When MMIC ERROR is encountered
1295 * by the firmware, payload is
1296 * dropped and only 32 bytes of
1297 * mwl8k Firmware header is sent
1298 * to the host.
1299 *
1300 * We need to add four bytes of
1301 * key information. In it
1302 * MAC80211 expects keyidx set to
1303 * 0 for triggering Counter
1304 * Measure of MMIC failure.
1305 */
1306 if (status.flag & RX_FLAG_MMIC_ERROR) {
1307 struct mwl8k_dma_data *tr;
1308 tr = (struct mwl8k_dma_data *)skb->data;
1309 memset((void *)&(tr->data), 0, 4);
1310 pkt_len += 4;
1311 }
1312
1313 if (!ieee80211_is_auth(wh->frame_control))
1314 status.flag |= RX_FLAG_IV_STRIPPED |
1315 RX_FLAG_DECRYPTED |
1316 RX_FLAG_MMIC_STRIPPED;
1317 }
1318 }
1319
1320 skb_put(skb, pkt_len);
1321 mwl8k_remove_dma_header(skb, qos);
f1d58c25
JB		 1322 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1323 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1324
1325 processed++;
1326 }
1327
1328 return processed;
1329}
1330
1331
1332/*
1333 * Packet transmission.
1334 */
1335
a66098da
LB		 1336#define MWL8K_TXD_STATUS_OK 0x00000001
1337#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1338#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1339#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1340#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1341
e0493a8d
LB		 1342#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1343#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1344#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1345#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1346#define MWL8K_QOS_EOSP 0x0010
1347
a66098da
LB		 1348struct mwl8k_tx_desc {
1349 __le32 status;
1350 __u8 data_rate;
1351 __u8 tx_priority;
1352 __le16 qos_control;
1353 __le32 pkt_phys_addr;
1354 __le16 pkt_len;
d89173f2 1355 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1356 __le32 next_txd_phys_addr;
8a7a578c 1357 __le32 timestamp;
a66098da
LB		 1358 __le16 rate_info;
1359 __u8 peer_id;
a1fe24b0 1360 __u8 tx_frag_cnt;
ba2d3587 1361} __packed;
a66098da
LB		 1362
1363#define MWL8K_TX_DESCS 128
1364
1365static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1366{
1367 struct mwl8k_priv *priv = hw->priv;
1368 struct mwl8k_tx_queue *txq = priv->txq + index;
1369 int size;
1370 int i;
1371
8ccbc3b8 1372 txq->len = 0;
45eb400d
LB		 1373 txq->head = 0;
1374 txq->tail = 0;
a66098da
LB		 1375
1376 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1377
45eb400d
LB		 1378 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1379 if (txq->txd == NULL) {
5db55844 1380 wiphy_err(hw->wiphy, "failed to alloc TX descriptors\n");
a66098da
LB		 1381 return -ENOMEM;
1382 }
45eb400d 1383 memset(txq->txd, 0, size);
a66098da 1384
b9ede5f1 1385 txq->skb = kcalloc(MWL8K_TX_DESCS, sizeof(*txq->skb), GFP_KERNEL);
45eb400d 1386 if (txq->skb == NULL) {
5db55844 1387 wiphy_err(hw->wiphy, "failed to alloc TX skbuff list\n");
45eb400d 1388 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1389 return -ENOMEM;
1390 }
a66098da
LB		 1391
1392 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1393 struct mwl8k_tx_desc *tx_desc;
1394 int nexti;
1395
45eb400d 1396 tx_desc = txq->txd + i;
a66098da
LB		 1397 nexti = (i + 1) % MWL8K_TX_DESCS;
1398
1399 tx_desc->status = 0;
45eb400d
LB		 1400 tx_desc->next_txd_phys_addr =
1401 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1402 }
1403
1404 return 0;
1405}
1406
1407static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1408{
1409 iowrite32(MWL8K_H2A_INT_PPA_READY,
1410 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1411 iowrite32(MWL8K_H2A_INT_DUMMY,
1412 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1413 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1414}
1415
7e1112d3 1416static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1417{
7e1112d3
LB		 1418 struct mwl8k_priv *priv = hw->priv;
1419 int i;
1420
e600707b 1421 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
7e1112d3
LB		 1422 struct mwl8k_tx_queue *txq = priv->txq + i;
1423 int fw_owned = 0;
1424 int drv_owned = 0;
1425 int unused = 0;
1426 int desc;
1427
a66098da 1428 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1429 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1430 u32 status;
a66098da 1431
7e1112d3 1432 status = le32_to_cpu(tx_desc->status);
a66098da 1433 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1434 fw_owned++;
a66098da 1435 else
7e1112d3 1436 drv_owned++;
a66098da
LB		 1437
1438 if (tx_desc->pkt_len == 0)
7e1112d3 1439 unused++;
a66098da 1440 }
a66098da 1441
c96c31e4
JP		 1442 wiphy_err(hw->wiphy,
1443 "txq[%d] len=%d head=%d tail=%d "
1444 "fw_owned=%d drv_owned=%d unused=%d\n",
1445 i,
1446 txq->len, txq->head, txq->tail,
1447 fw_owned, drv_owned, unused);
7e1112d3 1448 }
a66098da
LB		 1449}
1450
618952a7 1451/*
88de754a 1452 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1453 */
62abd3cf 1454#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1455
950d5b01 1456static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1457{
a66098da 1458 struct mwl8k_priv *priv = hw->priv;
88de754a 1459 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1460 int retry;
1461 int rc;
a66098da
LB		 1462
1463 might_sleep();
1464
7e1112d3
LB		 1465 /*
1466 * The TX queues are stopped at this point, so this test
1467 * doesn't need to take ->tx_lock.
1468 */
1469 if (!priv->pending_tx_pkts)
1470 return 0;
1471
1472 retry = 0;
1473 rc = 0;
1474
a66098da 1475 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1476 priv->tx_wait = &tx_wait;
1477 while (!rc) {
1478 int oldcount;
1479 unsigned long timeout;
a66098da 1480
7e1112d3 1481 oldcount = priv->pending_tx_pkts;
a66098da 1482
7e1112d3 1483 spin_unlock_bh(&priv->tx_lock);
88de754a 1484 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1485 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1486 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1487
1488 if (timeout) {
1489 WARN_ON(priv->pending_tx_pkts);
ba30c4a5 1490 if (retry)
c96c31e4 1491 wiphy_notice(hw->wiphy, "tx rings drained\n");
7e1112d3
LB		 1492 break;
1493 }
1494
1495 if (priv->pending_tx_pkts < oldcount) {
c96c31e4
JP		 1496 wiphy_notice(hw->wiphy,
1497 "waiting for tx rings to drain (%d -> %d pkts)\n",
1498 oldcount, priv->pending_tx_pkts);
7e1112d3
LB		 1499 retry = 1;
1500 continue;
1501 }
1502
a66098da 1503 priv->tx_wait = NULL;
a66098da 1504
c96c31e4
JP		 1505 wiphy_err(hw->wiphy, "tx rings stuck for %d ms\n",
1506 MWL8K_TX_WAIT_TIMEOUT_MS);
7e1112d3
LB		 1507 mwl8k_dump_tx_rings(hw);
1508
1509 rc = -ETIMEDOUT;
a66098da 1510 }
7e1112d3 1511 spin_unlock_bh(&priv->tx_lock);
a66098da 1512
7e1112d3 1513 return rc;
a66098da
LB		 1514}
1515
c23b5a69
LB		 1516#define MWL8K_TXD_SUCCESS(status) \
1517 ((status) & (MWL8K_TXD_STATUS_OK | \
1518 MWL8K_TXD_STATUS_OK_RETRY | \
1519 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1520
a0e7c6cf
NS		 1521static int mwl8k_tid_queue_mapping(u8 tid)
1522{
1523 BUG_ON(tid > 7);
1524
1525 switch (tid) {
1526 case 0:
1527 case 3:
1528 return IEEE80211_AC_BE;
1529 break;
1530 case 1:
1531 case 2:
1532 return IEEE80211_AC_BK;
1533 break;
1534 case 4:
1535 case 5:
1536 return IEEE80211_AC_VI;
1537 break;
1538 case 6:
1539 case 7:
1540 return IEEE80211_AC_VO;
1541 break;
1542 default:
1543 return -1;
1544 break;
1545 }
1546}
1547
17033543
NS		 1548/* The firmware will fill in the rate information
1549 * for each packet that gets queued in the hardware
1550 * in this structure
1551 */
1552
1553struct rateinfo {
1554 __le16 format:1;
1555 __le16 short_gi:1;
1556 __le16 band_width:1;
1557 __le16 rate_id_mcs:6;
1558 __le16 adv_coding:2;
1559 __le16 antenna:2;
1560 __le16 act_sub_chan:2;
1561 __le16 preamble_type:1;
1562 __le16 power_id:4;
1563 __le16 antenna2:1;
1564 __le16 reserved:1;
1565 __le16 tx_bf_frame:1;
1566 __le16 green_field:1;
1567} __packed;
1568
efb7c49a
LB		 1569static int
1570mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB		 1571{
1572 struct mwl8k_priv *priv = hw->priv;
1573 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1574 int processed;
a66098da 1575
efb7c49a 1576 processed = 0;
8ccbc3b8 1577 while (txq->len > 0 && limit--) {
a66098da 1578 int tx;
a66098da
LB		 1579 struct mwl8k_tx_desc *tx_desc;
1580 unsigned long addr;
ce9e2e1b 1581 int size;
a66098da
LB		 1582 struct sk_buff *skb;
1583 struct ieee80211_tx_info *info;
1584 u32 status;
17033543
NS		 1585 struct ieee80211_sta *sta;
1586 struct mwl8k_sta *sta_info = NULL;
1587 u16 rate_info;
1588 struct rateinfo *rate;
1589 struct ieee80211_hdr *wh;
a66098da 1590
45eb400d
LB		 1591 tx = txq->head;
1592 tx_desc = txq->txd + tx;
a66098da
LB		 1593
1594 status = le32_to_cpu(tx_desc->status);
1595
1596 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1597 if (!force)
1598 break;
1599 tx_desc->status &=
1600 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1601 }
1602
45eb400d 1603 txq->head = (tx + 1) % MWL8K_TX_DESCS;
8ccbc3b8
KV		 1604 BUG_ON(txq->len == 0);
1605 txq->len--;
a66098da
LB		 1606 priv->pending_tx_pkts--;
1607
1608 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1609 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1610 skb = txq->skb[tx];
1611 txq->skb[tx] = NULL;
a66098da
LB		 1612
1613 BUG_ON(skb == NULL);
1614 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1615
20f09c3d 1616 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da 1617
17033543
NS		 1618 wh = (struct ieee80211_hdr *) skb->data;
1619
a66098da
LB		 1620 /* Mark descriptor as unused */
1621 tx_desc->pkt_phys_addr = 0;
1622 tx_desc->pkt_len = 0;
1623
a66098da 1624 info = IEEE80211_SKB_CB(skb);
17033543
NS		 1625 if (ieee80211_is_data(wh->frame_control)) {
1626 sta = info->control.sta;
1627 if (sta) {
1628 sta_info = MWL8K_STA(sta);
1629 BUG_ON(sta_info == NULL);
1630 rate_info = le16_to_cpu(tx_desc->rate_info);
1631 rate = (struct rateinfo *)&rate_info;
1632 /* If rate is < 6.5 Mpbs for an ht station
1633 * do not form an ampdu. If the station is a
1634 * legacy station (format = 0), do not form an
1635 * ampdu
1636 */
1637 if (rate->rate_id_mcs < 1 ||
1638 rate->format == 0) {
1639 sta_info->is_ampdu_allowed = false;
1640 } else {
1641 sta_info->is_ampdu_allowed = true;
1642 }
1643 }
1644 }
1645
a66098da 1646 ieee80211_tx_info_clear_status(info);
0bf22c37
NS		 1647
1648 /* Rate control is happening in the firmware.
1649 * Ensure no tx rate is being reported.
1650 */
ba30c4a5
YAP		 1651 info->status.rates[0].idx = -1;
1652 info->status.rates[0].count = 1;
0bf22c37 1653
ce9e2e1b 1654 if (MWL8K_TXD_SUCCESS(status))
a66098da 1655 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1656
1657 ieee80211_tx_status_irqsafe(hw, skb);
1658
efb7c49a 1659 processed++;
a66098da
LB		 1660 }
1661
65f3ddcd
NS		 1662 if (index < MWL8K_TX_WMM_QUEUES && processed && priv->radio_on &&
1663 !mutex_is_locked(&priv->fw_mutex))
a66098da 1664 ieee80211_wake_queue(hw, index);
efb7c49a
LB		 1665
1666 return processed;
a66098da
LB		 1667}
1668
1669/* must be called only when the card's transmit is completely halted */
1670static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1671{
1672 struct mwl8k_priv *priv = hw->priv;
1673 struct mwl8k_tx_queue *txq = priv->txq + index;
1674
73b46320
BC		 1675 if (txq->txd == NULL)
1676 return;
1677
efb7c49a 1678 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1679
45eb400d
LB		 1680 kfree(txq->skb);
1681 txq->skb = NULL;
a66098da
LB		 1682
1683 pci_free_consistent(priv->pdev,
1684 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1685 txq->txd, txq->txd_dma);
1686 txq->txd = NULL;
a66098da
LB		 1687}
1688
ac109fd0 1689/* caller must hold priv->stream_lock when calling the stream functions */
ba30c4a5 1690static struct mwl8k_ampdu_stream *
ac109fd0
BC		 1691mwl8k_add_stream(struct ieee80211_hw *hw, struct ieee80211_sta *sta, u8 tid)
1692{
1693 struct mwl8k_ampdu_stream *stream;
1694 struct mwl8k_priv *priv = hw->priv;
1695 int i;
1696
1697 for (i = 0; i < priv->num_ampdu_queues; i++) {
1698 stream = &priv->ampdu[i];
1699 if (stream->state == AMPDU_NO_STREAM) {
1700 stream->sta = sta;
1701 stream->state = AMPDU_STREAM_NEW;
1702 stream->tid = tid;
1703 stream->idx = i;
1704 stream->txq_idx = MWL8K_TX_WMM_QUEUES + i;
1705 wiphy_debug(hw->wiphy, "Added a new stream for %pM %d",
1706 sta->addr, tid);
1707 return stream;
1708 }
1709 }
1710 return NULL;
1711}
1712
1713static int
1714mwl8k_start_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1715{
1716 int ret;
1717
1718 /* if the stream has already been started, don't start it again */
1719 if (stream->state != AMPDU_STREAM_NEW)
1720 return 0;
1721 ret = ieee80211_start_tx_ba_session(stream->sta, stream->tid, 0);
1722 if (ret)
1723 wiphy_debug(hw->wiphy, "Failed to start stream for %pM %d: "
1724 "%d\n", stream->sta->addr, stream->tid, ret);
1725 else
1726 wiphy_debug(hw->wiphy, "Started stream for %pM %d\n",
1727 stream->sta->addr, stream->tid);
1728 return ret;
1729}
1730
1731static void
1732mwl8k_remove_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1733{
1734 wiphy_debug(hw->wiphy, "Remove stream for %pM %d\n", stream->sta->addr,
1735 stream->tid);
1736 memset(stream, 0, sizeof(*stream));
1737}
1738
1739static struct mwl8k_ampdu_stream *
1740mwl8k_lookup_stream(struct ieee80211_hw *hw, u8 *addr, u8 tid)
1741{
1742 struct mwl8k_priv *priv = hw->priv;
1743 int i;
1744
1745 for (i = 0 ; i < priv->num_ampdu_queues; i++) {
1746 struct mwl8k_ampdu_stream *stream;
1747 stream = &priv->ampdu[i];
1748 if (stream->state == AMPDU_NO_STREAM)
1749 continue;
1750 if (!memcmp(stream->sta->addr, addr, ETH_ALEN) &&
1751 stream->tid == tid)
1752 return stream;
1753 }
1754 return NULL;
1755}
1756
7bb45683 1757static void
a66098da
LB		 1758mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1759{
1760 struct mwl8k_priv *priv = hw->priv;
1761 struct ieee80211_tx_info *tx_info;
23b33906 1762 struct mwl8k_vif *mwl8k_vif;
65f3ddcd 1763 struct ieee80211_sta *sta;
a66098da
LB		 1764 struct ieee80211_hdr *wh;
1765 struct mwl8k_tx_queue *txq;
1766 struct mwl8k_tx_desc *tx;
a66098da 1767 dma_addr_t dma;
23b33906
LB		 1768 u32 txstatus;
1769 u8 txdatarate;
1770 u16 qos;
65f3ddcd
NS		 1771 int txpriority;
1772 u8 tid = 0;
1773 struct mwl8k_ampdu_stream *stream = NULL;
1774 bool start_ba_session = false;
a0e7c6cf 1775 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
a66098da 1776
23b33906
LB		 1777 wh = (struct ieee80211_hdr *)skb->data;
1778 if (ieee80211_is_data_qos(wh->frame_control))
1779 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1780 else
1781 qos = 0;
a66098da 1782
d9a07d49
NS		 1783 if (priv->ap_fw)
1784 mwl8k_encapsulate_tx_frame(skb);
1785 else
1786 mwl8k_add_dma_header(skb, 0);
1787
23b33906 1788 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1789
1790 tx_info = IEEE80211_SKB_CB(skb);
65f3ddcd 1791 sta = tx_info->control.sta;
a66098da 1792 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1793
1794 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
a66098da 1795 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
657232b6
LB		 1796 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1797 mwl8k_vif->seqno += 0x10;
a66098da
LB		 1798 }
1799
23b33906
LB		 1800 /* Setup firmware control bit fields for each frame type. */
1801 txstatus = 0;
1802 txdatarate = 0;
1803 if (ieee80211_is_mgmt(wh->frame_control) ||
1804 ieee80211_is_ctl(wh->frame_control)) {
1805 txdatarate = 0;
e0493a8d 1806 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1807 } else if (ieee80211_is_data(wh->frame_control)) {
1808 txdatarate = 1;
1809 if (is_multicast_ether_addr(wh->addr1))
1810 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1811
e0493a8d 1812 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1813 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1814 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1815 else
e0493a8d 1816 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1817 }
a66098da 1818
a0e7c6cf
NS		 1819 /* Queue ADDBA request in the respective data queue. While setting up
1820 * the ampdu stream, mac80211 queues further packets for that
1821 * particular ra/tid pair. However, packets piled up in the hardware
1822 * for that ra/tid pair will still go out. ADDBA request and the
1823 * related data packets going out from different queues asynchronously
1824 * will cause a shift in the receiver window which might result in
1825 * ampdu packets getting dropped at the receiver after the stream has
1826 * been setup.
1827 */
1828 if (unlikely(ieee80211_is_action(wh->frame_control) &&
1829 mgmt->u.action.category == WLAN_CATEGORY_BACK &&
1830 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ &&
1831 priv->ap_fw)) {
1832 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
1833 tid = (capab & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2;
1834 index = mwl8k_tid_queue_mapping(tid);
1835 }
1836
65f3ddcd
NS		 1837 txpriority = index;
1838
1839 if (ieee80211_is_data_qos(wh->frame_control) &&
1840 skb->protocol != cpu_to_be16(ETH_P_PAE) &&
1841 sta->ht_cap.ht_supported && priv->ap_fw) {
1842 tid = qos & 0xf;
1843 spin_lock(&priv->stream_lock);
1844 stream = mwl8k_lookup_stream(hw, sta->addr, tid);
1845 if (stream != NULL) {
1846 if (stream->state == AMPDU_STREAM_ACTIVE) {
1847 txpriority = stream->txq_idx;
1848 index = stream->txq_idx;
1849 } else if (stream->state == AMPDU_STREAM_NEW) {
1850 /* We get here if the driver sends us packets
1851 * after we've initiated a stream, but before
1852 * our ampdu_action routine has been called
1853 * with IEEE80211_AMPDU_TX_START to get the SSN
1854 * for the ADDBA request. So this packet can
1855 * go out with no risk of sequence number
1856 * mismatch. No special handling is required.
1857 */
1858 } else {
1859 /* Drop packets that would go out after the
1860 * ADDBA request was sent but before the ADDBA
1861 * response is received. If we don't do this,
1862 * the recipient would probably receive it
1863 * after the ADDBA request with SSN 0. This
1864 * will cause the recipient's BA receive window
1865 * to shift, which would cause the subsequent
1866 * packets in the BA stream to be discarded.
1867 * mac80211 queues our packets for us in this
1868 * case, so this is really just a safety check.
1869 */
1870 wiphy_warn(hw->wiphy,
1871 "Cannot send packet while ADDBA "
1872 "dialog is underway.\n");
1873 spin_unlock(&priv->stream_lock);
1874 dev_kfree_skb(skb);
1875 return;
1876 }
1877 } else {
1878 /* Defer calling mwl8k_start_stream so that the current
1879 * skb can go out before the ADDBA request. This
1880 * prevents sequence number mismatch at the recepient
1881 * as described above.
1882 */
17033543
NS		 1883 if (MWL8K_STA(sta)->is_ampdu_allowed) {
1884 stream = mwl8k_add_stream(hw, sta, tid);
1885 if (stream != NULL)
1886 start_ba_session = true;
1887 }
65f3ddcd
NS		 1888 }
1889 spin_unlock(&priv->stream_lock);
1890 }
1891
a66098da
LB		 1892 dma = pci_map_single(priv->pdev, skb->data,
1893 skb->len, PCI_DMA_TODEVICE);
1894
1895 if (pci_dma_mapping_error(priv->pdev, dma)) {
c96c31e4
JP		 1896 wiphy_debug(hw->wiphy,
1897 "failed to dma map skb, dropping TX frame.\n");
65f3ddcd
NS		 1898 if (start_ba_session) {
1899 spin_lock(&priv->stream_lock);
1900 mwl8k_remove_stream(hw, stream);
1901 spin_unlock(&priv->stream_lock);
1902 }
23b33906 1903 dev_kfree_skb(skb);
7bb45683 1904 return;
a66098da
LB		 1905 }
1906
23b33906 1907 spin_lock_bh(&priv->tx_lock);
a66098da 1908
23b33906 1909 txq = priv->txq + index;
a66098da 1910
65f3ddcd
NS		 1911 if (index >= MWL8K_TX_WMM_QUEUES && txq->len >= MWL8K_TX_DESCS) {
1912 /* This is the case in which the tx packet is destined for an
1913 * AMPDU queue and that AMPDU queue is full. Because we don't
1914 * start and stop the AMPDU queues, we must drop these packets.
1915 */
1916 dev_kfree_skb(skb);
1917 spin_unlock_bh(&priv->tx_lock);
1918 return;
1919 }
1920
45eb400d
LB		 1921 BUG_ON(txq->skb[txq->tail] != NULL);
1922 txq->skb[txq->tail] = skb;
a66098da 1923
45eb400d 1924 tx = txq->txd + txq->tail;
23b33906 1925 tx->data_rate = txdatarate;
65f3ddcd 1926 tx->tx_priority = txpriority;
a66098da 1927 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1928 tx->pkt_phys_addr = cpu_to_le32(dma);
1929 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1930 tx->rate_info = 0;
a680400e
LB		 1931 if (!priv->ap_fw && tx_info->control.sta != NULL)
1932 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1933 else
1934 tx->peer_id = 0;
a66098da 1935 wmb();
23b33906
LB		 1936 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1937
8ccbc3b8 1938 txq->len++;
a66098da 1939 priv->pending_tx_pkts++;
a66098da 1940
45eb400d
LB		 1941 txq->tail++;
1942 if (txq->tail == MWL8K_TX_DESCS)
1943 txq->tail = 0;
23b33906 1944
65f3ddcd 1945 if (txq->head == txq->tail && index < MWL8K_TX_WMM_QUEUES)
a66098da
LB		 1946 ieee80211_stop_queue(hw, index);
1947
23b33906 1948 mwl8k_tx_start(priv);
a66098da
LB		 1949
1950 spin_unlock_bh(&priv->tx_lock);
65f3ddcd
NS		 1951
1952 /* Initiate the ampdu session here */
1953 if (start_ba_session) {
1954 spin_lock(&priv->stream_lock);
1955 if (mwl8k_start_stream(hw, stream))
1956 mwl8k_remove_stream(hw, stream);
1957 spin_unlock(&priv->stream_lock);
1958 }
a66098da
LB		 1959}
1960
1961
618952a7
LB		 1962/*
1963 * Firmware access.
1964 *
1965 * We have the following requirements for issuing firmware commands:
1966 * - Some commands require that the packet transmit path is idle when
1967 * the command is issued. (For simplicity, we'll just quiesce the
1968 * transmit path for every command.)
1969 * - There are certain sequences of commands that need to be issued to
1970 * the hardware sequentially, with no other intervening commands.
1971 *
1972 * This leads to an implementation of a "firmware lock" as a mutex that
1973 * can be taken recursively, and which is taken by both the low-level
1974 * command submission function (mwl8k_post_cmd) as well as any users of
1975 * that function that require issuing of an atomic sequence of commands,
1976 * and quiesces the transmit path whenever it's taken.
1977 */
1978static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1979{
1980 struct mwl8k_priv *priv = hw->priv;
1981
1982 if (priv->fw_mutex_owner != current) {
1983 int rc;
1984
1985 mutex_lock(&priv->fw_mutex);
1986 ieee80211_stop_queues(hw);
1987
1988 rc = mwl8k_tx_wait_empty(hw);
1989 if (rc) {
1990 ieee80211_wake_queues(hw);
1991 mutex_unlock(&priv->fw_mutex);
1992
1993 return rc;
1994 }
1995
1996 priv->fw_mutex_owner = current;
1997 }
1998
1999 priv->fw_mutex_depth++;
2000
2001 return 0;
2002}
2003
2004static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
2005{
2006 struct mwl8k_priv *priv = hw->priv;
2007
2008 if (!--priv->fw_mutex_depth) {
2009 ieee80211_wake_queues(hw);
2010 priv->fw_mutex_owner = NULL;
2011 mutex_unlock(&priv->fw_mutex);
2012 }
2013}
2014
2015
a66098da
LB		 2016/*
2017 * Command processing.
2018 */
2019
0c9cc640
LB		 2020/* Timeout firmware commands after 10s */
2021#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 2022
2023static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
2024{
2025 DECLARE_COMPLETION_ONSTACK(cmd_wait);
2026 struct mwl8k_priv *priv = hw->priv;
2027 void __iomem *regs = priv->regs;
2028 dma_addr_t dma_addr;
2029 unsigned int dma_size;
2030 int rc;
a66098da
LB		 2031 unsigned long timeout = 0;
2032 u8 buf[32];
2033
b603742f 2034 cmd->result = (__force __le16) 0xffff;
a66098da
LB		 2035 dma_size = le16_to_cpu(cmd->length);
2036 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
2037 PCI_DMA_BIDIRECTIONAL);
2038 if (pci_dma_mapping_error(priv->pdev, dma_addr))
2039 return -ENOMEM;
2040
618952a7 2041 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 2042 if (rc) {
2043 pci_unmap_single(priv->pdev, dma_addr, dma_size,
2044 PCI_DMA_BIDIRECTIONAL);
618952a7 2045 return rc;
39a1e42e 2046 }
a66098da 2047
a66098da
LB		 2048 priv->hostcmd_wait = &cmd_wait;
2049 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
2050 iowrite32(MWL8K_H2A_INT_DOORBELL,
2051 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
2052 iowrite32(MWL8K_H2A_INT_DUMMY,
2053 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 2054
2055 timeout = wait_for_completion_timeout(&cmd_wait,
2056 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
2057
618952a7
LB		 2058 priv->hostcmd_wait = NULL;
2059
2060 mwl8k_fw_unlock(hw);
2061
37055bd4
LB		 2062 pci_unmap_single(priv->pdev, dma_addr, dma_size,
2063 PCI_DMA_BIDIRECTIONAL);
2064
a66098da 2065 if (!timeout) {
5db55844 2066 wiphy_err(hw->wiphy, "Command %s timeout after %u ms\n",
c96c31e4
JP		 2067 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2068 MWL8K_CMD_TIMEOUT_MS);
a66098da
LB		 2069 rc = -ETIMEDOUT;
2070 } else {
0c9cc640
LB		 2071 int ms;
2072
2073 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
2074
ce9e2e1b 2075 rc = cmd->result ? -EINVAL : 0;
a66098da 2076 if (rc)
5db55844 2077 wiphy_err(hw->wiphy, "Command %s error 0x%x\n",
c96c31e4
JP		 2078 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2079 le16_to_cpu(cmd->result));
0c9cc640 2080 else if (ms > 2000)
5db55844 2081 wiphy_notice(hw->wiphy, "Command %s took %d ms\n",
c96c31e4
JP		 2082 mwl8k_cmd_name(cmd->code,
2083 buf, sizeof(buf)),
2084 ms);
a66098da
LB		 2085 }
2086
a66098da
LB		 2087 return rc;
2088}
2089
f57ca9c1
LB		 2090static int mwl8k_post_pervif_cmd(struct ieee80211_hw *hw,
2091 struct ieee80211_vif *vif,
2092 struct mwl8k_cmd_pkt *cmd)
2093{
2094 if (vif != NULL)
2095 cmd->macid = MWL8K_VIF(vif)->macid;
2096 return mwl8k_post_cmd(hw, cmd);
2097}
2098
1349ad2f
LB		 2099/*
2100 * Setup code shared between STA and AP firmware images.
2101 */
2102static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw)
2103{
2104 struct mwl8k_priv *priv = hw->priv;
2105
2106 BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24));
2107 memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
2108
2109 BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
2110 memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
2111
2112 priv->band_24.band = IEEE80211_BAND_2GHZ;
2113 priv->band_24.channels = priv->channels_24;
2114 priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
2115 priv->band_24.bitrates = priv->rates_24;
2116 priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
2117
2118 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24;
2119}
2120
4eae9edd
LB		 2121static void mwl8k_setup_5ghz_band(struct ieee80211_hw *hw)
2122{
2123 struct mwl8k_priv *priv = hw->priv;
2124
2125 BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl8k_channels_50));
2126 memcpy(priv->channels_50, mwl8k_channels_50, sizeof(mwl8k_channels_50));
2127
2128 BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl8k_rates_50));
2129 memcpy(priv->rates_50, mwl8k_rates_50, sizeof(mwl8k_rates_50));
2130
2131 priv->band_50.band = IEEE80211_BAND_5GHZ;
2132 priv->band_50.channels = priv->channels_50;
2133 priv->band_50.n_channels = ARRAY_SIZE(mwl8k_channels_50);
2134 priv->band_50.bitrates = priv->rates_50;
2135 priv->band_50.n_bitrates = ARRAY_SIZE(mwl8k_rates_50);
2136
2137 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->band_50;
2138}
2139
a66098da 2140/*
04b147b1 2141 * CMD_GET_HW_SPEC (STA version).
a66098da 2142 */
04b147b1 2143struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 2144 struct mwl8k_cmd_pkt header;
2145 __u8 hw_rev;
2146 __u8 host_interface;
2147 __le16 num_mcaddrs;
d89173f2 2148 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 2149 __le16 region_code;
2150 __le32 fw_rev;
2151 __le32 ps_cookie;
2152 __le32 caps;
2153 __u8 mcs_bitmap[16];
2154 __le32 rx_queue_ptr;
2155 __le32 num_tx_queues;
e600707b 2156 __le32 tx_queue_ptrs[MWL8K_TX_WMM_QUEUES];
a66098da
LB		 2157 __le32 caps2;
2158 __le32 num_tx_desc_per_queue;
45eb400d 2159 __le32 total_rxd;
ba2d3587 2160} __packed;
a66098da 2161
341c9791
LB		 2162#define MWL8K_CAP_MAX_AMSDU 0x20000000
2163#define MWL8K_CAP_GREENFIELD 0x08000000
2164#define MWL8K_CAP_AMPDU 0x04000000
2165#define MWL8K_CAP_RX_STBC 0x01000000
2166#define MWL8K_CAP_TX_STBC 0x00800000
2167#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
2168#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
2169#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
2170#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
2171#define MWL8K_CAP_DELAY_BA 0x00003000
2172#define MWL8K_CAP_MIMO 0x00000200
2173#define MWL8K_CAP_40MHZ 0x00000100
06953235
LB		 2174#define MWL8K_CAP_BAND_MASK 0x00000007
2175#define MWL8K_CAP_5GHZ 0x00000004
2176#define MWL8K_CAP_2GHZ4 0x00000001
341c9791 2177
06953235
LB		 2178static void
2179mwl8k_set_ht_caps(struct ieee80211_hw *hw,
2180 struct ieee80211_supported_band *band, u32 cap)
341c9791 2181{
341c9791
LB		 2182 int rx_streams;
2183 int tx_streams;
2184
777ad375 2185 band->ht_cap.ht_supported = 1;
341c9791
LB		 2186
2187 if (cap & MWL8K_CAP_MAX_AMSDU)
777ad375 2188 band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
341c9791 2189 if (cap & MWL8K_CAP_GREENFIELD)
777ad375 2190 band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
341c9791
LB		 2191 if (cap & MWL8K_CAP_AMPDU) {
2192 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
777ad375
LB		 2193 band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
2194 band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
341c9791
LB		 2195 }
2196 if (cap & MWL8K_CAP_RX_STBC)
777ad375 2197 band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
341c9791 2198 if (cap & MWL8K_CAP_TX_STBC)
777ad375 2199 band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
341c9791 2200 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
777ad375 2201 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
341c9791 2202 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
777ad375 2203 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
341c9791 2204 if (cap & MWL8K_CAP_DELAY_BA)
777ad375 2205 band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
341c9791 2206 if (cap & MWL8K_CAP_40MHZ)
777ad375 2207 band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
341c9791
LB		 2208
2209 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
2210 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
2211
777ad375 2212 band->ht_cap.mcs.rx_mask[0] = 0xff;
341c9791 2213 if (rx_streams >= 2)
777ad375 2214 band->ht_cap.mcs.rx_mask[1] = 0xff;
341c9791 2215 if (rx_streams >= 3)
777ad375
LB		 2216 band->ht_cap.mcs.rx_mask[2] = 0xff;
2217 band->ht_cap.mcs.rx_mask[4] = 0x01;
2218 band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
341c9791
LB		 2219
2220 if (rx_streams != tx_streams) {
777ad375
LB		 2221 band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
2222 band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
341c9791
LB		 2223 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2224 }
2225}
2226
06953235
LB		 2227static void
2228mwl8k_set_caps(struct ieee80211_hw *hw, u32 caps)
2229{
2230 struct mwl8k_priv *priv = hw->priv;
2231
2232 if ((caps & MWL8K_CAP_2GHZ4) || !(caps & MWL8K_CAP_BAND_MASK)) {
2233 mwl8k_setup_2ghz_band(hw);
2234 if (caps & MWL8K_CAP_MIMO)
2235 mwl8k_set_ht_caps(hw, &priv->band_24, caps);
2236 }
2237
2238 if (caps & MWL8K_CAP_5GHZ) {
2239 mwl8k_setup_5ghz_band(hw);
2240 if (caps & MWL8K_CAP_MIMO)
2241 mwl8k_set_ht_caps(hw, &priv->band_50, caps);
2242 }
2243}
2244
04b147b1 2245static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 2246{
2247 struct mwl8k_priv *priv = hw->priv;
04b147b1 2248 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 2249 int rc;
2250 int i;
2251
2252 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2253 if (cmd == NULL)
2254 return -ENOMEM;
2255
2256 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2257 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2258
2259 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2260 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 2261 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
e600707b
BC		 2262 cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
2263 for (i = 0; i < mwl8k_tx_queues(priv); i++)
45eb400d 2264 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 2265 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 2266 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 2267
2268 rc = mwl8k_post_cmd(hw, &cmd->header);
2269
2270 if (!rc) {
2271 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2272 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 2273 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 2274 priv->hw_rev = cmd->hw_rev;
06953235 2275 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18
LB		 2276 priv->ap_macids_supported = 0x00000000;
2277 priv->sta_macids_supported = 0x00000001;
a66098da
LB		 2278 }
2279
2280 kfree(cmd);
2281 return rc;
2282}
2283
42fba21d
LB		 2284/*
2285 * CMD_GET_HW_SPEC (AP version).
2286 */
2287struct mwl8k_cmd_get_hw_spec_ap {
2288 struct mwl8k_cmd_pkt header;
2289 __u8 hw_rev;
2290 __u8 host_interface;
2291 __le16 num_wcb;
2292 __le16 num_mcaddrs;
2293 __u8 perm_addr[ETH_ALEN];
2294 __le16 region_code;
2295 __le16 num_antenna;
2296 __le32 fw_rev;
2297 __le32 wcbbase0;
2298 __le32 rxwrptr;
2299 __le32 rxrdptr;
2300 __le32 ps_cookie;
2301 __le32 wcbbase1;
2302 __le32 wcbbase2;
2303 __le32 wcbbase3;
952a0e96 2304 __le32 fw_api_version;
8a7a578c
BC		 2305 __le32 caps;
2306 __le32 num_of_ampdu_queues;
2307 __le32 wcbbase_ampdu[MWL8K_MAX_AMPDU_QUEUES];
ba2d3587 2308} __packed;
42fba21d
LB		 2309
2310static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
2311{
2312 struct mwl8k_priv *priv = hw->priv;
2313 struct mwl8k_cmd_get_hw_spec_ap *cmd;
8a7a578c 2314 int rc, i;
952a0e96 2315 u32 api_version;
42fba21d
LB		 2316
2317 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2318 if (cmd == NULL)
2319 return -ENOMEM;
2320
2321 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2322 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2323
2324 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2325 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2326
2327 rc = mwl8k_post_cmd(hw, &cmd->header);
2328
2329 if (!rc) {
2330 int off;
2331
952a0e96
BC		 2332 api_version = le32_to_cpu(cmd->fw_api_version);
2333 if (priv->device_info->fw_api_ap != api_version) {
2334 printk(KERN_ERR "%s: Unsupported fw API version for %s."
2335 " Expected %d got %d.\n", MWL8K_NAME,
2336 priv->device_info->part_name,
2337 priv->device_info->fw_api_ap,
2338 api_version);
2339 rc = -EINVAL;
2340 goto done;
2341 }
42fba21d
LB		 2342 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2343 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
2344 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
2345 priv->hw_rev = cmd->hw_rev;
8a7a578c 2346 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18
LB		 2347 priv->ap_macids_supported = 0x000000ff;
2348 priv->sta_macids_supported = 0x00000000;
8a7a578c
BC		 2349 priv->num_ampdu_queues = le32_to_cpu(cmd->num_of_ampdu_queues);
2350 if (priv->num_ampdu_queues > MWL8K_MAX_AMPDU_QUEUES) {
2351 wiphy_warn(hw->wiphy, "fw reported %d ampdu queues"
2352 " but we only support %d.\n",
2353 priv->num_ampdu_queues,
2354 MWL8K_MAX_AMPDU_QUEUES);
2355 priv->num_ampdu_queues = MWL8K_MAX_AMPDU_QUEUES;
2356 }
42fba21d 2357 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
b603742f 2358 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d
LB		 2359
2360 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
b603742f 2361 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d 2362
73b46320
BC		 2363 priv->txq_offset[0] = le32_to_cpu(cmd->wcbbase0) & 0xffff;
2364 priv->txq_offset[1] = le32_to_cpu(cmd->wcbbase1) & 0xffff;
2365 priv->txq_offset[2] = le32_to_cpu(cmd->wcbbase2) & 0xffff;
2366 priv->txq_offset[3] = le32_to_cpu(cmd->wcbbase3) & 0xffff;
8a7a578c
BC		 2367
2368 for (i = 0; i < priv->num_ampdu_queues; i++)
e600707b 2369 priv->txq_offset[i + MWL8K_TX_WMM_QUEUES] =
8a7a578c 2370 le32_to_cpu(cmd->wcbbase_ampdu[i]) & 0xffff;
42fba21d
LB		 2371 }
2372
952a0e96 2373done:
42fba21d
LB		 2374 kfree(cmd);
2375 return rc;
2376}
2377
2378/*
2379 * CMD_SET_HW_SPEC.
2380 */
2381struct mwl8k_cmd_set_hw_spec {
2382 struct mwl8k_cmd_pkt header;
2383 __u8 hw_rev;
2384 __u8 host_interface;
2385 __le16 num_mcaddrs;
2386 __u8 perm_addr[ETH_ALEN];
2387 __le16 region_code;
2388 __le32 fw_rev;
2389 __le32 ps_cookie;
2390 __le32 caps;
2391 __le32 rx_queue_ptr;
2392 __le32 num_tx_queues;
e600707b 2393 __le32 tx_queue_ptrs[MWL8K_MAX_TX_QUEUES];
42fba21d
LB		 2394 __le32 flags;
2395 __le32 num_tx_desc_per_queue;
2396 __le32 total_rxd;
ba2d3587 2397} __packed;
42fba21d 2398
8a7a578c
BC		 2399/* If enabled, MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY will cause
2400 * packets to expire 500 ms after the timestamp in the tx descriptor. That is,
2401 * the packets that are queued for more than 500ms, will be dropped in the
2402 * hardware. This helps minimizing the issues caused due to head-of-line
2403 * blocking where a slow client can hog the bandwidth and affect traffic to a
2404 * faster client.
2405 */
2406#define MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY 0x00000400
b64fe619
LB		 2407#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
2408#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
2409#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB		 2410
2411static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
2412{
2413 struct mwl8k_priv *priv = hw->priv;
2414 struct mwl8k_cmd_set_hw_spec *cmd;
2415 int rc;
2416 int i;
2417
2418 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2419 if (cmd == NULL)
2420 return -ENOMEM;
2421
2422 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
2423 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2424
2425 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2426 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
e600707b 2427 cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
85c9205c
NS		 2428
2429 /*
2430 * Mac80211 stack has Q0 as highest priority and Q3 as lowest in
2431 * that order. Firmware has Q3 as highest priority and Q0 as lowest
2432 * in that order. Map Q3 of mac80211 to Q0 of firmware so that the
2433 * priority is interpreted the right way in firmware.
2434 */
e600707b
BC		 2435 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
2436 int j = mwl8k_tx_queues(priv) - 1 - i;
85c9205c
NS		 2437 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[j].txd_dma);
2438 }
2439
b64fe619
LB		 2440 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
2441 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
2442 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
42fba21d
LB		 2443 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
2444 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
2445
2446 rc = mwl8k_post_cmd(hw, &cmd->header);
2447 kfree(cmd);
2448
2449 return rc;
2450}
2451
a66098da
LB		 2452/*
2453 * CMD_MAC_MULTICAST_ADR.
2454 */
2455struct mwl8k_cmd_mac_multicast_adr {
2456 struct mwl8k_cmd_pkt header;
2457 __le16 action;
2458 __le16 numaddr;
ce9e2e1b 2459 __u8 addr[0][ETH_ALEN];
a66098da
LB		 2460};
2461
d5e30845
LB		 2462#define MWL8K_ENABLE_RX_DIRECTED 0x0001
2463#define MWL8K_ENABLE_RX_MULTICAST 0x0002
2464#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
2465#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 2466
e81cd2d6 2467static struct mwl8k_cmd_pkt *
447ced07 2468__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
22bedad3 2469 struct netdev_hw_addr_list *mc_list)
a66098da 2470{
e81cd2d6 2471 struct mwl8k_priv *priv = hw->priv;
a66098da 2472 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 2473 int size;
22bedad3
JP		 2474 int mc_count = 0;
2475
2476 if (mc_list)
2477 mc_count = netdev_hw_addr_list_count(mc_list);
e81cd2d6 2478
447ced07 2479 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 2480 allmulti = 1;
2481 mc_count = 0;
2482 }
e81cd2d6
LB		 2483
2484 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 2485
e81cd2d6 2486 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 2487 if (cmd == NULL)
e81cd2d6 2488 return NULL;
a66098da
LB		 2489
2490 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
2491 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 2492 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
2493 MWL8K_ENABLE_RX_BROADCAST);
2494
2495 if (allmulti) {
2496 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
2497 } else if (mc_count) {
22bedad3
JP		 2498 struct netdev_hw_addr *ha;
2499 int i = 0;
d5e30845
LB		 2500
2501 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
2502 cmd->numaddr = cpu_to_le16(mc_count);
22bedad3
JP		 2503 netdev_hw_addr_list_for_each(ha, mc_list) {
2504 memcpy(cmd->addr[i], ha->addr, ETH_ALEN);
a66098da 2505 }
a66098da
LB		 2506 }
2507
e81cd2d6 2508 return &cmd->header;
a66098da
LB		 2509}
2510
2511/*
55489b6e 2512 * CMD_GET_STAT.
a66098da 2513 */
55489b6e 2514struct mwl8k_cmd_get_stat {
a66098da 2515 struct mwl8k_cmd_pkt header;
a66098da 2516 __le32 stats[64];
ba2d3587 2517} __packed;
a66098da
LB		 2518
2519#define MWL8K_STAT_ACK_FAILURE 9
2520#define MWL8K_STAT_RTS_FAILURE 12
2521#define MWL8K_STAT_FCS_ERROR 24
2522#define MWL8K_STAT_RTS_SUCCESS 11
2523
55489b6e
LB		 2524static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
2525 struct ieee80211_low_level_stats *stats)
a66098da 2526{
55489b6e 2527 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 2528 int rc;
2529
2530 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2531 if (cmd == NULL)
2532 return -ENOMEM;
2533
2534 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
2535 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2536
2537 rc = mwl8k_post_cmd(hw, &cmd->header);
2538 if (!rc) {
2539 stats->dot11ACKFailureCount =
2540 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
2541 stats->dot11RTSFailureCount =
2542 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
2543 stats->dot11FCSErrorCount =
2544 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
2545 stats->dot11RTSSuccessCount =
2546 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
2547 }
2548 kfree(cmd);
2549
2550 return rc;
2551}
2552
2553/*
55489b6e 2554 * CMD_RADIO_CONTROL.
a66098da 2555 */
55489b6e 2556struct mwl8k_cmd_radio_control {
a66098da
LB		 2557 struct mwl8k_cmd_pkt header;
2558 __le16 action;
2559 __le16 control;
2560 __le16 radio_on;
ba2d3587 2561} __packed;
a66098da 2562
c46563b7 2563static int
55489b6e 2564mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 2565{
2566 struct mwl8k_priv *priv = hw->priv;
55489b6e 2567 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 2568 int rc;
2569
c46563b7 2570 if (enable == priv->radio_on && !force)
a66098da
LB		 2571 return 0;
2572
a66098da
LB		 2573 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2574 if (cmd == NULL)
2575 return -ENOMEM;
2576
2577 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
2578 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2579 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 2580 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 2581 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
2582
2583 rc = mwl8k_post_cmd(hw, &cmd->header);
2584 kfree(cmd);
2585
2586 if (!rc)
c46563b7 2587 priv->radio_on = enable;
a66098da
LB		 2588
2589 return rc;
2590}
2591
55489b6e 2592static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 2593{
55489b6e 2594 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 2595}
2596
55489b6e 2597static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 2598{
55489b6e 2599 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 2600}
2601
a66098da
LB		 2602static int
2603mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
2604{
99200a99 2605 struct mwl8k_priv *priv = hw->priv;
a66098da 2606
68ce3884 2607 priv->radio_short_preamble = short_preamble;
a66098da 2608
55489b6e 2609 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 2610}
2611
2612/*
55489b6e 2613 * CMD_RF_TX_POWER.
a66098da 2614 */
41fdf097 2615#define MWL8K_RF_TX_POWER_LEVEL_TOTAL 8
a66098da 2616
55489b6e 2617struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 2618 struct mwl8k_cmd_pkt header;
2619 __le16 action;
2620 __le16 support_level;
2621 __le16 current_level;
2622 __le16 reserved;
41fdf097 2623 __le16 power_level_list[MWL8K_RF_TX_POWER_LEVEL_TOTAL];
ba2d3587 2624} __packed;
a66098da 2625
55489b6e 2626static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 2627{
55489b6e 2628 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 2629 int rc;
2630
2631 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2632 if (cmd == NULL)
2633 return -ENOMEM;
2634
2635 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2636 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2637 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2638 cmd->support_level = cpu_to_le16(dBm);
2639
2640 rc = mwl8k_post_cmd(hw, &cmd->header);
2641 kfree(cmd);
2642
2643 return rc;
2644}
2645
41fdf097
NS		 2646/*
2647 * CMD_TX_POWER.
2648 */
2649#define MWL8K_TX_POWER_LEVEL_TOTAL 12
2650
2651struct mwl8k_cmd_tx_power {
2652 struct mwl8k_cmd_pkt header;
2653 __le16 action;
2654 __le16 band;
2655 __le16 channel;
2656 __le16 bw;
2657 __le16 sub_ch;
2658 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
ba30c4a5 2659} __packed;
41fdf097
NS		 2660
2661static int mwl8k_cmd_tx_power(struct ieee80211_hw *hw,
2662 struct ieee80211_conf *conf,
2663 unsigned short pwr)
2664{
2665 struct ieee80211_channel *channel = conf->channel;
2666 struct mwl8k_cmd_tx_power *cmd;
2667 int rc;
2668 int i;
2669
2670 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2671 if (cmd == NULL)
2672 return -ENOMEM;
2673
2674 cmd->header.code = cpu_to_le16(MWL8K_CMD_TX_POWER);
2675 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2676 cmd->action = cpu_to_le16(MWL8K_CMD_SET_LIST);
2677
2678 if (channel->band == IEEE80211_BAND_2GHZ)
2679 cmd->band = cpu_to_le16(0x1);
2680 else if (channel->band == IEEE80211_BAND_5GHZ)
2681 cmd->band = cpu_to_le16(0x4);
2682
2683 cmd->channel = channel->hw_value;
2684
2685 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2686 conf->channel_type == NL80211_CHAN_HT20) {
2687 cmd->bw = cpu_to_le16(0x2);
2688 } else {
2689 cmd->bw = cpu_to_le16(0x4);
2690 if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2691 cmd->sub_ch = cpu_to_le16(0x3);
2692 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2693 cmd->sub_ch = cpu_to_le16(0x1);
2694 }
2695
2696 for (i = 0; i < MWL8K_TX_POWER_LEVEL_TOTAL; i++)
2697 cmd->power_level_list[i] = cpu_to_le16(pwr);
2698
2699 rc = mwl8k_post_cmd(hw, &cmd->header);
2700 kfree(cmd);
2701
2702 return rc;
2703}
2704
08b06347
LB		 2705/*
2706 * CMD_RF_ANTENNA.
2707 */
2708struct mwl8k_cmd_rf_antenna {
2709 struct mwl8k_cmd_pkt header;
2710 __le16 antenna;
2711 __le16 mode;
ba2d3587 2712} __packed;
08b06347
LB		 2713
2714#define MWL8K_RF_ANTENNA_RX 1
2715#define MWL8K_RF_ANTENNA_TX 2
2716
2717static int
2718mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2719{
2720 struct mwl8k_cmd_rf_antenna *cmd;
2721 int rc;
2722
2723 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2724 if (cmd == NULL)
2725 return -ENOMEM;
2726
2727 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2728 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2729 cmd->antenna = cpu_to_le16(antenna);
2730 cmd->mode = cpu_to_le16(mask);
2731
2732 rc = mwl8k_post_cmd(hw, &cmd->header);
2733 kfree(cmd);
2734
2735 return rc;
2736}
2737
b64fe619
LB		 2738/*
2739 * CMD_SET_BEACON.
2740 */
2741struct mwl8k_cmd_set_beacon {
2742 struct mwl8k_cmd_pkt header;
2743 __le16 beacon_len;
2744 __u8 beacon[0];
2745};
2746
aa21d0f6
LB		 2747static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw,
2748 struct ieee80211_vif *vif, u8 *beacon, int len)
b64fe619
LB		 2749{
2750 struct mwl8k_cmd_set_beacon *cmd;
2751 int rc;
2752
2753 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2754 if (cmd == NULL)
2755 return -ENOMEM;
2756
2757 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2758 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2759 cmd->beacon_len = cpu_to_le16(len);
2760 memcpy(cmd->beacon, beacon, len);
2761
aa21d0f6 2762 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 2763 kfree(cmd);
2764
2765 return rc;
2766}
2767
a66098da
LB		 2768/*
2769 * CMD_SET_PRE_SCAN.
2770 */
2771struct mwl8k_cmd_set_pre_scan {
2772 struct mwl8k_cmd_pkt header;
ba2d3587 2773} __packed;
a66098da
LB		 2774
2775static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2776{
2777 struct mwl8k_cmd_set_pre_scan *cmd;
2778 int rc;
2779
2780 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2781 if (cmd == NULL)
2782 return -ENOMEM;
2783
2784 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2785 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2786
2787 rc = mwl8k_post_cmd(hw, &cmd->header);
2788 kfree(cmd);
2789
2790 return rc;
2791}
2792
2793/*
2794 * CMD_SET_POST_SCAN.
2795 */
2796struct mwl8k_cmd_set_post_scan {
2797 struct mwl8k_cmd_pkt header;
2798 __le32 isibss;
d89173f2 2799 __u8 bssid[ETH_ALEN];
ba2d3587 2800} __packed;
a66098da
LB		 2801
2802static int
0a11dfc3 2803mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 2804{
2805 struct mwl8k_cmd_set_post_scan *cmd;
2806 int rc;
2807
2808 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2809 if (cmd == NULL)
2810 return -ENOMEM;
2811
2812 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2813 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2814 cmd->isibss = 0;
d89173f2 2815 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2816
2817 rc = mwl8k_post_cmd(hw, &cmd->header);
2818 kfree(cmd);
2819
2820 return rc;
2821}
2822
2823/*
2824 * CMD_SET_RF_CHANNEL.
2825 */
2826struct mwl8k_cmd_set_rf_channel {
2827 struct mwl8k_cmd_pkt header;
2828 __le16 action;
2829 __u8 current_channel;
2830 __le32 channel_flags;
ba2d3587 2831} __packed;
a66098da
LB		 2832
2833static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 2834 struct ieee80211_conf *conf)
a66098da 2835{
610677d2 2836 struct ieee80211_channel *channel = conf->channel;
a66098da
LB		 2837 struct mwl8k_cmd_set_rf_channel *cmd;
2838 int rc;
2839
2840 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2841 if (cmd == NULL)
2842 return -ENOMEM;
2843
2844 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2845 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2846 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2847 cmd->current_channel = channel->hw_value;
610677d2 2848
a66098da 2849 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2 2850 cmd->channel_flags |= cpu_to_le32(0x00000001);
42574ea2
LB		 2851 else if (channel->band == IEEE80211_BAND_5GHZ)
2852 cmd->channel_flags |= cpu_to_le32(0x00000004);
610677d2
LB		 2853
2854 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2855 conf->channel_type == NL80211_CHAN_HT20)
2856 cmd->channel_flags |= cpu_to_le32(0x00000080);
2857 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2858 cmd->channel_flags |= cpu_to_le32(0x000001900);
2859 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2860 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB		 2861
2862 rc = mwl8k_post_cmd(hw, &cmd->header);
2863 kfree(cmd);
2864
2865 return rc;
2866}
2867
2868/*
55489b6e 2869 * CMD_SET_AID.
a66098da 2870 */
55489b6e
LB		 2871#define MWL8K_FRAME_PROT_DISABLED 0x00
2872#define MWL8K_FRAME_PROT_11G 0x07
2873#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2874#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2875
55489b6e
LB		 2876struct mwl8k_cmd_update_set_aid {
2877 struct mwl8k_cmd_pkt header;
2878 __le16 aid;
a66098da 2879
55489b6e
LB		 2880 /* AP's MAC address (BSSID) */
2881 __u8 bssid[ETH_ALEN];
2882 __le16 protection_mode;
2883 __u8 supp_rates[14];
ba2d3587 2884} __packed;
a66098da 2885
c6e96010
LB		 2886static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
2887{
2888 int i;
2889 int j;
2890
2891 /*
2892 * Clear nonstandard rates 4 and 13.
2893 */
2894 mask &= 0x1fef;
2895
2896 for (i = 0, j = 0; i < 14; i++) {
2897 if (mask & (1 << i))
777ad375 2898 rates[j++] = mwl8k_rates_24[i].hw_value;
c6e96010
LB		 2899 }
2900}
2901
55489b6e 2902static int
c6e96010
LB		 2903mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2904 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 2905{
55489b6e
LB		 2906 struct mwl8k_cmd_update_set_aid *cmd;
2907 u16 prot_mode;
a66098da
LB		 2908 int rc;
2909
2910 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2911 if (cmd == NULL)
2912 return -ENOMEM;
2913
55489b6e 2914 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2915 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2916 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 2917 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2918
7dc6a7a7 2919 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 2920 prot_mode = MWL8K_FRAME_PROT_11G;
2921 } else {
7dc6a7a7 2922 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 2923 IEEE80211_HT_OP_MODE_PROTECTION) {
2924 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2925 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2926 break;
2927 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2928 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2929 break;
2930 default:
2931 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2932 break;
2933 }
2934 }
2935 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2936
c6e96010 2937 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 2938
2939 rc = mwl8k_post_cmd(hw, &cmd->header);
2940 kfree(cmd);
2941
2942 return rc;
2943}
2944
32060e1b 2945/*
55489b6e 2946 * CMD_SET_RATE.
32060e1b 2947 */
55489b6e
LB		 2948struct mwl8k_cmd_set_rate {
2949 struct mwl8k_cmd_pkt header;
2950 __u8 legacy_rates[14];
2951
2952 /* Bitmap for supported MCS codes. */
2953 __u8 mcs_set[16];
2954 __u8 reserved[16];
ba2d3587 2955} __packed;
32060e1b 2956
55489b6e 2957static int
c6e96010 2958mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 2959 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 2960{
55489b6e 2961 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 2962 int rc;
2963
2964 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2965 if (cmd == NULL)
2966 return -ENOMEM;
2967
55489b6e 2968 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 2969 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 2970 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 2971 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB		 2972
2973 rc = mwl8k_post_cmd(hw, &cmd->header);
2974 kfree(cmd);
2975
2976 return rc;
2977}
2978
a66098da 2979/*
55489b6e 2980 * CMD_FINALIZE_JOIN.
a66098da 2981 */
55489b6e
LB		 2982#define MWL8K_FJ_BEACON_MAXLEN 128
2983
2984struct mwl8k_cmd_finalize_join {
a66098da 2985 struct mwl8k_cmd_pkt header;
55489b6e
LB		 2986 __le32 sleep_interval; /* Number of beacon periods to sleep */
2987 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
ba2d3587 2988} __packed;
a66098da 2989
55489b6e
LB		 2990static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2991 int framelen, int dtim)
a66098da 2992{
55489b6e
LB		 2993 struct mwl8k_cmd_finalize_join *cmd;
2994 struct ieee80211_mgmt *payload = frame;
2995 int payload_len;
a66098da
LB		 2996 int rc;
2997
2998 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2999 if (cmd == NULL)
3000 return -ENOMEM;
3001
55489b6e 3002 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 3003 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3004 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
3005
3006 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
3007 if (payload_len < 0)
3008 payload_len = 0;
3009 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
3010 payload_len = MWL8K_FJ_BEACON_MAXLEN;
3011
3012 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 3013
3014 rc = mwl8k_post_cmd(hw, &cmd->header);
3015 kfree(cmd);
3016
3017 return rc;
3018}
3019
3020/*
55489b6e 3021 * CMD_SET_RTS_THRESHOLD.
a66098da 3022 */
55489b6e 3023struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 3024 struct mwl8k_cmd_pkt header;
3025 __le16 action;
55489b6e 3026 __le16 threshold;
ba2d3587 3027} __packed;
a66098da 3028
c2c2b12a
LB		 3029static int
3030mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 3031{
55489b6e 3032 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 3033 int rc;
3034
3035 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3036 if (cmd == NULL)
3037 return -ENOMEM;
3038
55489b6e 3039 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 3040 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB		 3041 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3042 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB		 3043
3044 rc = mwl8k_post_cmd(hw, &cmd->header);
3045 kfree(cmd);
3046
a66098da
LB		 3047 return rc;
3048}
3049
3050/*
55489b6e 3051 * CMD_SET_SLOT.
a66098da 3052 */
55489b6e 3053struct mwl8k_cmd_set_slot {
a66098da
LB		 3054 struct mwl8k_cmd_pkt header;
3055 __le16 action;
55489b6e 3056 __u8 short_slot;
ba2d3587 3057} __packed;
a66098da 3058
55489b6e 3059static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 3060{
55489b6e 3061 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 3062 int rc;
3063
3064 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3065 if (cmd == NULL)
3066 return -ENOMEM;
3067
55489b6e 3068 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 3069 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3070 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3071 cmd->short_slot = short_slot_time;
a66098da
LB		 3072
3073 rc = mwl8k_post_cmd(hw, &cmd->header);
3074 kfree(cmd);
3075
3076 return rc;
3077}
3078
3079/*
3080 * CMD_SET_EDCA_PARAMS.
3081 */
3082struct mwl8k_cmd_set_edca_params {
3083 struct mwl8k_cmd_pkt header;
3084
3085 /* See MWL8K_SET_EDCA_XXX below */
3086 __le16 action;
3087
3088 /* TX opportunity in units of 32 us */
3089 __le16 txop;
3090
2e484c89
LB		 3091 union {
3092 struct {
3093 /* Log exponent of max contention period: 0...15 */
3094 __le32 log_cw_max;
3095
3096 /* Log exponent of min contention period: 0...15 */
3097 __le32 log_cw_min;
3098
3099 /* Adaptive interframe spacing in units of 32us */
3100 __u8 aifs;
3101
3102 /* TX queue to configure */
3103 __u8 txq;
3104 } ap;
3105 struct {
3106 /* Log exponent of max contention period: 0...15 */
3107 __u8 log_cw_max;
a66098da 3108
2e484c89
LB		 3109 /* Log exponent of min contention period: 0...15 */
3110 __u8 log_cw_min;
a66098da 3111
2e484c89
LB		 3112 /* Adaptive interframe spacing in units of 32us */
3113 __u8 aifs;
a66098da 3114
2e484c89
LB		 3115 /* TX queue to configure */
3116 __u8 txq;
3117 } sta;
3118 };
ba2d3587 3119} __packed;
a66098da 3120
a66098da
LB		 3121#define MWL8K_SET_EDCA_CW 0x01
3122#define MWL8K_SET_EDCA_TXOP 0x02
3123#define MWL8K_SET_EDCA_AIFS 0x04
3124
3125#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
3126 MWL8K_SET_EDCA_TXOP | \
3127 MWL8K_SET_EDCA_AIFS)
3128
3129static int
55489b6e
LB		 3130mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
3131 __u16 cw_min, __u16 cw_max,
3132 __u8 aifs, __u16 txop)
a66098da 3133{
2e484c89 3134 struct mwl8k_priv *priv = hw->priv;
a66098da 3135 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 3136 int rc;
3137
3138 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3139 if (cmd == NULL)
3140 return -ENOMEM;
3141
a66098da
LB		 3142 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
3143 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 3144 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
3145 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 3146 if (priv->ap_fw) {
3147 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
3148 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
3149 cmd->ap.aifs = aifs;
3150 cmd->ap.txq = qnum;
3151 } else {
3152 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
3153 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
3154 cmd->sta.aifs = aifs;
3155 cmd->sta.txq = qnum;
3156 }
a66098da
LB		 3157
3158 rc = mwl8k_post_cmd(hw, &cmd->header);
3159 kfree(cmd);
3160
3161 return rc;
3162}
3163
3164/*
55489b6e 3165 * CMD_SET_WMM_MODE.
a66098da 3166 */
55489b6e 3167struct mwl8k_cmd_set_wmm_mode {
a66098da 3168 struct mwl8k_cmd_pkt header;
55489b6e 3169 __le16 action;
ba2d3587 3170} __packed;
a66098da 3171
55489b6e 3172static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 3173{
55489b6e
LB		 3174 struct mwl8k_priv *priv = hw->priv;
3175 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 3176 int rc;
3177
a66098da
LB		 3178 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3179 if (cmd == NULL)
3180 return -ENOMEM;
3181
55489b6e 3182 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 3183 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 3184 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 3185
3186 rc = mwl8k_post_cmd(hw, &cmd->header);
3187 kfree(cmd);
16cec43d 3188
55489b6e
LB		 3189 if (!rc)
3190 priv->wmm_enabled = enable;
a66098da
LB		 3191
3192 return rc;
3193}
3194
3195/*
55489b6e 3196 * CMD_MIMO_CONFIG.
a66098da 3197 */
55489b6e
LB		 3198struct mwl8k_cmd_mimo_config {
3199 struct mwl8k_cmd_pkt header;
3200 __le32 action;
3201 __u8 rx_antenna_map;
3202 __u8 tx_antenna_map;
ba2d3587 3203} __packed;
a66098da 3204
55489b6e 3205static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 3206{
55489b6e 3207 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 3208 int rc;
3209
3210 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3211 if (cmd == NULL)
3212 return -ENOMEM;
3213
55489b6e 3214 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 3215 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3216 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
3217 cmd->rx_antenna_map = rx;
3218 cmd->tx_antenna_map = tx;
a66098da
LB		 3219
3220 rc = mwl8k_post_cmd(hw, &cmd->header);
3221 kfree(cmd);
3222
3223 return rc;
3224}
3225
3226/*
b71ed2c6 3227 * CMD_USE_FIXED_RATE (STA version).
a66098da 3228 */
b71ed2c6
LB		 3229struct mwl8k_cmd_use_fixed_rate_sta {
3230 struct mwl8k_cmd_pkt header;
3231 __le32 action;
3232 __le32 allow_rate_drop;
3233 __le32 num_rates;
3234 struct {
3235 __le32 is_ht_rate;
3236 __le32 enable_retry;
3237 __le32 rate;
3238 __le32 retry_count;
3239 } rate_entry[8];
3240 __le32 rate_type;
3241 __le32 reserved1;
3242 __le32 reserved2;
ba2d3587 3243} __packed;
a66098da 3244
b71ed2c6
LB		 3245#define MWL8K_USE_AUTO_RATE 0x0002
3246#define MWL8K_UCAST_RATE 0
a66098da 3247
b71ed2c6 3248static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 3249{
b71ed2c6 3250 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB		 3251 int rc;
3252
3253 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3254 if (cmd == NULL)
3255 return -ENOMEM;
3256
3257 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3258 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB		 3259 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3260 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB		 3261
3262 rc = mwl8k_post_cmd(hw, &cmd->header);
3263 kfree(cmd);
3264
3265 return rc;
3266}
3267
088aab8b
LB		 3268/*
3269 * CMD_USE_FIXED_RATE (AP version).
3270 */
3271struct mwl8k_cmd_use_fixed_rate_ap {
3272 struct mwl8k_cmd_pkt header;
3273 __le32 action;
3274 __le32 allow_rate_drop;
3275 __le32 num_rates;
3276 struct mwl8k_rate_entry_ap {
3277 __le32 is_ht_rate;
3278 __le32 enable_retry;
3279 __le32 rate;
3280 __le32 retry_count;
3281 } rate_entry[4];
3282 u8 multicast_rate;
3283 u8 multicast_rate_type;
3284 u8 management_rate;
ba2d3587 3285} __packed;
088aab8b
LB		 3286
3287static int
3288mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
3289{
3290 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
3291 int rc;
3292
3293 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3294 if (cmd == NULL)
3295 return -ENOMEM;
3296
3297 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3298 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3299 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3300 cmd->multicast_rate = mcast;
3301 cmd->management_rate = mgmt;
3302
3303 rc = mwl8k_post_cmd(hw, &cmd->header);
3304 kfree(cmd);
3305
3306 return rc;
3307}
3308
55489b6e
LB		 3309/*
3310 * CMD_ENABLE_SNIFFER.
3311 */
3312struct mwl8k_cmd_enable_sniffer {
3313 struct mwl8k_cmd_pkt header;
3314 __le32 action;
ba2d3587 3315} __packed;
55489b6e
LB		 3316
3317static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
3318{
3319 struct mwl8k_cmd_enable_sniffer *cmd;
3320 int rc;
3321
3322 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3323 if (cmd == NULL)
3324 return -ENOMEM;
3325
3326 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
3327 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3328 cmd->action = cpu_to_le32(!!enable);
3329
3330 rc = mwl8k_post_cmd(hw, &cmd->header);
3331 kfree(cmd);
3332
3333 return rc;
3334}
3335
3336/*
3337 * CMD_SET_MAC_ADDR.
3338 */
3339struct mwl8k_cmd_set_mac_addr {
3340 struct mwl8k_cmd_pkt header;
3341 union {
3342 struct {
3343 __le16 mac_type;
3344 __u8 mac_addr[ETH_ALEN];
3345 } mbss;
3346 __u8 mac_addr[ETH_ALEN];
3347 };
ba2d3587 3348} __packed;
55489b6e 3349
ee0ddf18
LB		 3350#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
3351#define MWL8K_MAC_TYPE_SECONDARY_CLIENT 1
3352#define MWL8K_MAC_TYPE_PRIMARY_AP 2
3353#define MWL8K_MAC_TYPE_SECONDARY_AP 3
a9e00b15 3354
aa21d0f6
LB		 3355static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw,
3356 struct ieee80211_vif *vif, u8 *mac)
55489b6e
LB		 3357{
3358 struct mwl8k_priv *priv = hw->priv;
ee0ddf18 3359 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
55489b6e 3360 struct mwl8k_cmd_set_mac_addr *cmd;
ee0ddf18 3361 int mac_type;
55489b6e
LB		 3362 int rc;
3363
ee0ddf18
LB		 3364 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3365 if (vif != NULL && vif->type == NL80211_IFTYPE_STATION) {
3366 if (mwl8k_vif->macid + 1 == ffs(priv->sta_macids_supported))
3367 mac_type = MWL8K_MAC_TYPE_PRIMARY_CLIENT;
3368 else
3369 mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3370 } else if (vif != NULL && vif->type == NL80211_IFTYPE_AP) {
3371 if (mwl8k_vif->macid + 1 == ffs(priv->ap_macids_supported))
3372 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3373 else
3374 mac_type = MWL8K_MAC_TYPE_SECONDARY_AP;
3375 }
3376
55489b6e
LB		 3377 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3378 if (cmd == NULL)
3379 return -ENOMEM;
3380
3381 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
3382 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3383 if (priv->ap_fw) {
ee0ddf18 3384 cmd->mbss.mac_type = cpu_to_le16(mac_type);
55489b6e
LB		 3385 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
3386 } else {
3387 memcpy(cmd->mac_addr, mac, ETH_ALEN);
3388 }
3389
aa21d0f6 3390 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
55489b6e
LB		 3391 kfree(cmd);
3392
3393 return rc;
3394}
3395
3396/*
3397 * CMD_SET_RATEADAPT_MODE.
3398 */
3399struct mwl8k_cmd_set_rate_adapt_mode {
3400 struct mwl8k_cmd_pkt header;
3401 __le16 action;
3402 __le16 mode;
ba2d3587 3403} __packed;
55489b6e
LB		 3404
3405static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
3406{
3407 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
3408 int rc;
3409
3410 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3411 if (cmd == NULL)
3412 return -ENOMEM;
3413
3414 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
3415 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3416 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3417 cmd->mode = cpu_to_le16(mode);
3418
3419 rc = mwl8k_post_cmd(hw, &cmd->header);
3420 kfree(cmd);
3421
3422 return rc;
3423}
3424
3aefc37e
NS		 3425/*
3426 * CMD_GET_WATCHDOG_BITMAP.
3427 */
3428struct mwl8k_cmd_get_watchdog_bitmap {
3429 struct mwl8k_cmd_pkt header;
3430 u8 bitmap;
3431} __packed;
3432
3433static int mwl8k_cmd_get_watchdog_bitmap(struct ieee80211_hw *hw, u8 *bitmap)
3434{
3435 struct mwl8k_cmd_get_watchdog_bitmap *cmd;
3436 int rc;
3437
3438 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3439 if (cmd == NULL)
3440 return -ENOMEM;
3441
3442 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_WATCHDOG_BITMAP);
3443 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3444
3445 rc = mwl8k_post_cmd(hw, &cmd->header);
3446 if (!rc)
3447 *bitmap = cmd->bitmap;
3448
3449 kfree(cmd);
3450
3451 return rc;
3452}
3453
3454#define INVALID_BA 0xAA
3455static void mwl8k_watchdog_ba_events(struct work_struct *work)
3456{
3457 int rc;
3458 u8 bitmap = 0, stream_index;
3459 struct mwl8k_ampdu_stream *streams;
3460 struct mwl8k_priv *priv =
3461 container_of(work, struct mwl8k_priv, watchdog_ba_handle);
3462
3463 rc = mwl8k_cmd_get_watchdog_bitmap(priv->hw, &bitmap);
3464 if (rc)
3465 return;
3466
3467 if (bitmap == INVALID_BA)
3468 return;
3469
3470 /* the bitmap is the hw queue number. Map it to the ampdu queue. */
3471 stream_index = bitmap - MWL8K_TX_WMM_QUEUES;
3472
3473 BUG_ON(stream_index >= priv->num_ampdu_queues);
3474
3475 streams = &priv->ampdu[stream_index];
3476
3477 if (streams->state == AMPDU_STREAM_ACTIVE)
3478 ieee80211_stop_tx_ba_session(streams->sta, streams->tid);
3479
3480 return;
3481}
3482
3483
b64fe619
LB		 3484/*
3485 * CMD_BSS_START.
3486 */
3487struct mwl8k_cmd_bss_start {
3488 struct mwl8k_cmd_pkt header;
3489 __le32 enable;
ba2d3587 3490} __packed;
b64fe619 3491
aa21d0f6
LB		 3492static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw,
3493 struct ieee80211_vif *vif, int enable)
b64fe619
LB		 3494{
3495 struct mwl8k_cmd_bss_start *cmd;
3496 int rc;
3497
3498 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3499 if (cmd == NULL)
3500 return -ENOMEM;
3501
3502 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
3503 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3504 cmd->enable = cpu_to_le32(enable);
3505
aa21d0f6 3506 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 3507 kfree(cmd);
3508
3509 return rc;
3510}
3511
5faa1aff
NS		 3512/*
3513 * CMD_BASTREAM.
3514 */
3515
3516/*
3517 * UPSTREAM is tx direction
3518 */
3519#define BASTREAM_FLAG_DIRECTION_UPSTREAM 0x00
3520#define BASTREAM_FLAG_IMMEDIATE_TYPE 0x01
3521
ba30c4a5 3522enum ba_stream_action_type {
5faa1aff
NS		 3523 MWL8K_BA_CREATE,
3524 MWL8K_BA_UPDATE,
3525 MWL8K_BA_DESTROY,
3526 MWL8K_BA_FLUSH,
3527 MWL8K_BA_CHECK,
ba30c4a5 3528};
5faa1aff
NS		 3529
3530
3531struct mwl8k_create_ba_stream {
3532 __le32 flags;
3533 __le32 idle_thrs;
3534 __le32 bar_thrs;
3535 __le32 window_size;
3536 u8 peer_mac_addr[6];
3537 u8 dialog_token;
3538 u8 tid;
3539 u8 queue_id;
3540 u8 param_info;
3541 __le32 ba_context;
3542 u8 reset_seq_no_flag;
3543 __le16 curr_seq_no;
3544 u8 sta_src_mac_addr[6];
3545} __packed;
3546
3547struct mwl8k_destroy_ba_stream {
3548 __le32 flags;
3549 __le32 ba_context;
3550} __packed;
3551
3552struct mwl8k_cmd_bastream {
3553 struct mwl8k_cmd_pkt header;
3554 __le32 action;
3555 union {
3556 struct mwl8k_create_ba_stream create_params;
3557 struct mwl8k_destroy_ba_stream destroy_params;
3558 };
3559} __packed;
3560
3561static int
3562mwl8k_check_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
3563{
3564 struct mwl8k_cmd_bastream *cmd;
3565 int rc;
3566
3567 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3568 if (cmd == NULL)
3569 return -ENOMEM;
3570
3571 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3572 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3573
3574 cmd->action = cpu_to_le32(MWL8K_BA_CHECK);
3575
3576 cmd->create_params.queue_id = stream->idx;
3577 memcpy(&cmd->create_params.peer_mac_addr[0], stream->sta->addr,
3578 ETH_ALEN);
3579 cmd->create_params.tid = stream->tid;
3580
3581 cmd->create_params.flags =
3582 cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE) |
3583 cpu_to_le32(BASTREAM_FLAG_DIRECTION_UPSTREAM);
3584
3585 rc = mwl8k_post_cmd(hw, &cmd->header);
3586
3587 kfree(cmd);
3588
3589 return rc;
3590}
3591
3592static int
3593mwl8k_create_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream,
3594 u8 buf_size)
3595{
3596 struct mwl8k_cmd_bastream *cmd;
3597 int rc;
3598
3599 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3600 if (cmd == NULL)
3601 return -ENOMEM;
3602
3603
3604 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3605 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3606
3607 cmd->action = cpu_to_le32(MWL8K_BA_CREATE);
3608
3609 cmd->create_params.bar_thrs = cpu_to_le32((u32)buf_size);
3610 cmd->create_params.window_size = cpu_to_le32((u32)buf_size);
3611 cmd->create_params.queue_id = stream->idx;
3612
3613 memcpy(cmd->create_params.peer_mac_addr, stream->sta->addr, ETH_ALEN);
3614 cmd->create_params.tid = stream->tid;
3615 cmd->create_params.curr_seq_no = cpu_to_le16(0);
3616 cmd->create_params.reset_seq_no_flag = 1;
3617
3618 cmd->create_params.param_info =
3619 (stream->sta->ht_cap.ampdu_factor &
3620 IEEE80211_HT_AMPDU_PARM_FACTOR) |
3621 ((stream->sta->ht_cap.ampdu_density << 2) &
3622 IEEE80211_HT_AMPDU_PARM_DENSITY);
3623
3624 cmd->create_params.flags =
3625 cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE |
3626 BASTREAM_FLAG_DIRECTION_UPSTREAM);
3627
3628 rc = mwl8k_post_cmd(hw, &cmd->header);
3629
3630 wiphy_debug(hw->wiphy, "Created a BA stream for %pM : tid %d\n",
3631 stream->sta->addr, stream->tid);
3632 kfree(cmd);
3633
3634 return rc;
3635}
3636
3637static void mwl8k_destroy_ba(struct ieee80211_hw *hw,
3638 struct mwl8k_ampdu_stream *stream)
3639{
3640 struct mwl8k_cmd_bastream *cmd;
3641
3642 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3643 if (cmd == NULL)
3644 return;
3645
3646 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3647 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3648 cmd->action = cpu_to_le32(MWL8K_BA_DESTROY);
3649
3650 cmd->destroy_params.ba_context = cpu_to_le32(stream->idx);
3651 mwl8k_post_cmd(hw, &cmd->header);
3652
3653 wiphy_debug(hw->wiphy, "Deleted BA stream index %d\n", stream->idx);
3654
3655 kfree(cmd);
3656}
3657
3f5610ff
LB		 3658/*
3659 * CMD_SET_NEW_STN.
3660 */
3661struct mwl8k_cmd_set_new_stn {
3662 struct mwl8k_cmd_pkt header;
3663 __le16 aid;
3664 __u8 mac_addr[6];
3665 __le16 stn_id;
3666 __le16 action;
3667 __le16 rsvd;
3668 __le32 legacy_rates;
3669 __u8 ht_rates[4];
3670 __le16 cap_info;
3671 __le16 ht_capabilities_info;
3672 __u8 mac_ht_param_info;
3673 __u8 rev;
3674 __u8 control_channel;
3675 __u8 add_channel;
3676 __le16 op_mode;
3677 __le16 stbc;
3678 __u8 add_qos_info;
3679 __u8 is_qos_sta;
3680 __le32 fw_sta_ptr;
ba2d3587 3681} __packed;
3f5610ff
LB		 3682
3683#define MWL8K_STA_ACTION_ADD 0
3684#define MWL8K_STA_ACTION_REMOVE 2
3685
3686static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
3687 struct ieee80211_vif *vif,
3688 struct ieee80211_sta *sta)
3689{
3690 struct mwl8k_cmd_set_new_stn *cmd;
8707d026 3691 u32 rates;
3f5610ff
LB		 3692 int rc;
3693
3694 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3695 if (cmd == NULL)
3696 return -ENOMEM;
3697
3698 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3699 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3700 cmd->aid = cpu_to_le16(sta->aid);
3701 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
3702 cmd->stn_id = cpu_to_le16(sta->aid);
3703 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
8707d026
LB		 3704 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3705 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
3706 else
3707 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3708 cmd->legacy_rates = cpu_to_le32(rates);
3f5610ff
LB		 3709 if (sta->ht_cap.ht_supported) {
3710 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
3711 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
3712 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
3713 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
3714 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
3715 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
3716 ((sta->ht_cap.ampdu_density & 7) << 2);
3717 cmd->is_qos_sta = 1;
3718 }
3719
aa21d0f6 3720 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 3721 kfree(cmd);
3722
3723 return rc;
3724}
3725
b64fe619
LB		 3726static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
3727 struct ieee80211_vif *vif)
3728{
3729 struct mwl8k_cmd_set_new_stn *cmd;
3730 int rc;
3731
3732 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3733 if (cmd == NULL)
3734 return -ENOMEM;
3735
3736 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3737 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3738 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
3739
aa21d0f6 3740 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 3741 kfree(cmd);
3742
3743 return rc;
3744}
3745
3f5610ff
LB		 3746static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
3747 struct ieee80211_vif *vif, u8 *addr)
3748{
3749 struct mwl8k_cmd_set_new_stn *cmd;
3750 int rc;
3751
3752 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3753 if (cmd == NULL)
3754 return -ENOMEM;
3755
3756 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3757 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3758 memcpy(cmd->mac_addr, addr, ETH_ALEN);
3759 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
3760
aa21d0f6 3761 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 3762 kfree(cmd);
3763
3764 return rc;
3765}
3766
fcdc403c
NS		 3767/*
3768 * CMD_UPDATE_ENCRYPTION.
3769 */
3770
3771#define MAX_ENCR_KEY_LENGTH 16
3772#define MIC_KEY_LENGTH 8
3773
3774struct mwl8k_cmd_update_encryption {
3775 struct mwl8k_cmd_pkt header;
3776
3777 __le32 action;
3778 __le32 reserved;
3779 __u8 mac_addr[6];
3780 __u8 encr_type;
3781
ba30c4a5 3782} __packed;
fcdc403c
NS		 3783
3784struct mwl8k_cmd_set_key {
3785 struct mwl8k_cmd_pkt header;
3786
3787 __le32 action;
3788 __le32 reserved;
3789 __le16 length;
3790 __le16 key_type_id;
3791 __le32 key_info;
3792 __le32 key_id;
3793 __le16 key_len;
3794 __u8 key_material[MAX_ENCR_KEY_LENGTH];
3795 __u8 tkip_tx_mic_key[MIC_KEY_LENGTH];
3796 __u8 tkip_rx_mic_key[MIC_KEY_LENGTH];
3797 __le16 tkip_rsc_low;
3798 __le32 tkip_rsc_high;
3799 __le16 tkip_tsc_low;
3800 __le32 tkip_tsc_high;
3801 __u8 mac_addr[6];
ba30c4a5 3802} __packed;
fcdc403c
NS		 3803
3804enum {
3805 MWL8K_ENCR_ENABLE,
3806 MWL8K_ENCR_SET_KEY,
3807 MWL8K_ENCR_REMOVE_KEY,
3808 MWL8K_ENCR_SET_GROUP_KEY,
3809};
3810
3811#define MWL8K_UPDATE_ENCRYPTION_TYPE_WEP 0
3812#define MWL8K_UPDATE_ENCRYPTION_TYPE_DISABLE 1
3813#define MWL8K_UPDATE_ENCRYPTION_TYPE_TKIP 4
3814#define MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED 7
3815#define MWL8K_UPDATE_ENCRYPTION_TYPE_AES 8
3816
3817enum {
3818 MWL8K_ALG_WEP,
3819 MWL8K_ALG_TKIP,
3820 MWL8K_ALG_CCMP,
3821};
3822
3823#define MWL8K_KEY_FLAG_TXGROUPKEY 0x00000004
3824#define MWL8K_KEY_FLAG_PAIRWISE 0x00000008
3825#define MWL8K_KEY_FLAG_TSC_VALID 0x00000040
3826#define MWL8K_KEY_FLAG_WEP_TXKEY 0x01000000
3827#define MWL8K_KEY_FLAG_MICKEY_VALID 0x02000000
3828
3829static int mwl8k_cmd_update_encryption_enable(struct ieee80211_hw *hw,
3830 struct ieee80211_vif *vif,
3831 u8 *addr,
3832 u8 encr_type)
3833{
3834 struct mwl8k_cmd_update_encryption *cmd;
3835 int rc;
3836
3837 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3838 if (cmd == NULL)
3839 return -ENOMEM;
3840
3841 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
3842 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3843 cmd->action = cpu_to_le32(MWL8K_ENCR_ENABLE);
3844 memcpy(cmd->mac_addr, addr, ETH_ALEN);
3845 cmd->encr_type = encr_type;
3846
3847 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3848 kfree(cmd);
3849
3850 return rc;
3851}
3852
3853static int mwl8k_encryption_set_cmd_info(struct mwl8k_cmd_set_key *cmd,
3854 u8 *addr,
3855 struct ieee80211_key_conf *key)
3856{
3857 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
3858 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3859 cmd->length = cpu_to_le16(sizeof(*cmd) -
3860 offsetof(struct mwl8k_cmd_set_key, length));
3861 cmd->key_id = cpu_to_le32(key->keyidx);
3862 cmd->key_len = cpu_to_le16(key->keylen);
3863 memcpy(cmd->mac_addr, addr, ETH_ALEN);
3864
3865 switch (key->cipher) {
3866 case WLAN_CIPHER_SUITE_WEP40:
3867 case WLAN_CIPHER_SUITE_WEP104:
3868 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_WEP);
3869 if (key->keyidx == 0)
3870 cmd->key_info = cpu_to_le32(MWL8K_KEY_FLAG_WEP_TXKEY);
3871
3872 break;
3873 case WLAN_CIPHER_SUITE_TKIP:
3874 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_TKIP);
3875 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
3876 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
3877 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
3878 cmd->key_info |= cpu_to_le32(MWL8K_KEY_FLAG_MICKEY_VALID
3879 | MWL8K_KEY_FLAG_TSC_VALID);
3880 break;
3881 case WLAN_CIPHER_SUITE_CCMP:
3882 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_CCMP);
3883 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
3884 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
3885 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
3886 break;
3887 default:
3888 return -ENOTSUPP;
3889 }
3890
3891 return 0;
3892}
3893
3894static int mwl8k_cmd_encryption_set_key(struct ieee80211_hw *hw,
3895 struct ieee80211_vif *vif,
3896 u8 *addr,
3897 struct ieee80211_key_conf *key)
3898{
3899 struct mwl8k_cmd_set_key *cmd;
3900 int rc;
3901 int keymlen;
3902 u32 action;
3903 u8 idx;
3904 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3905
3906 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3907 if (cmd == NULL)
3908 return -ENOMEM;
3909
3910 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
3911 if (rc < 0)
3912 goto done;
3913
3914 idx = key->keyidx;
3915
3916 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
3917 action = MWL8K_ENCR_SET_KEY;
3918 else
3919 action = MWL8K_ENCR_SET_GROUP_KEY;
3920
3921 switch (key->cipher) {
3922 case WLAN_CIPHER_SUITE_WEP40:
3923 case WLAN_CIPHER_SUITE_WEP104:
3924 if (!mwl8k_vif->wep_key_conf[idx].enabled) {
3925 memcpy(mwl8k_vif->wep_key_conf[idx].key, key,
3926 sizeof(*key) + key->keylen);
3927 mwl8k_vif->wep_key_conf[idx].enabled = 1;
3928 }
3929
3930 keymlen = 0;
3931 action = MWL8K_ENCR_SET_KEY;
3932 break;
3933 case WLAN_CIPHER_SUITE_TKIP:
3934 keymlen = MAX_ENCR_KEY_LENGTH + 2 * MIC_KEY_LENGTH;
3935 break;
3936 case WLAN_CIPHER_SUITE_CCMP:
3937 keymlen = key->keylen;
3938 break;
3939 default:
3940 rc = -ENOTSUPP;
3941 goto done;
3942 }
3943
3944 memcpy(cmd->key_material, key->key, keymlen);
3945 cmd->action = cpu_to_le32(action);
3946
3947 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3948done:
3949 kfree(cmd);
3950
3951 return rc;
3952}
3953
3954static int mwl8k_cmd_encryption_remove_key(struct ieee80211_hw *hw,
3955 struct ieee80211_vif *vif,
3956 u8 *addr,
3957 struct ieee80211_key_conf *key)
3958{
3959 struct mwl8k_cmd_set_key *cmd;
3960 int rc;
3961 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3962
3963 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3964 if (cmd == NULL)
3965 return -ENOMEM;
3966
3967 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
3968 if (rc < 0)
3969 goto done;
3970
3971 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3972 WLAN_CIPHER_SUITE_WEP104)
3973 mwl8k_vif->wep_key_conf[key->keyidx].enabled = 0;
3974
3975 cmd->action = cpu_to_le32(MWL8K_ENCR_REMOVE_KEY);
3976
3977 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3978done:
3979 kfree(cmd);
3980
3981 return rc;
3982}
3983
3984static int mwl8k_set_key(struct ieee80211_hw *hw,
3985 enum set_key_cmd cmd_param,
3986 struct ieee80211_vif *vif,
3987 struct ieee80211_sta *sta,
3988 struct ieee80211_key_conf *key)
3989{
3990 int rc = 0;
3991 u8 encr_type;
3992 u8 *addr;
3993 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3994
3995 if (vif->type == NL80211_IFTYPE_STATION)
3996 return -EOPNOTSUPP;
3997
3998 if (sta == NULL)
3999 addr = hw->wiphy->perm_addr;
4000 else
4001 addr = sta->addr;
4002
4003 if (cmd_param == SET_KEY) {
4004 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4005 rc = mwl8k_cmd_encryption_set_key(hw, vif, addr, key);
4006 if (rc)
4007 goto out;
4008
4009 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40)
4010 || (key->cipher == WLAN_CIPHER_SUITE_WEP104))
4011 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_WEP;
4012 else
4013 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED;
4014
4015 rc = mwl8k_cmd_update_encryption_enable(hw, vif, addr,
4016 encr_type);
4017 if (rc)
4018 goto out;
4019
4020 mwl8k_vif->is_hw_crypto_enabled = true;
4021
4022 } else {
4023 rc = mwl8k_cmd_encryption_remove_key(hw, vif, addr, key);
4024
4025 if (rc)
4026 goto out;
4027
4028 mwl8k_vif->is_hw_crypto_enabled = false;
4029
4030 }
4031out:
4032 return rc;
4033}
4034
55489b6e
LB		 4035/*
4036 * CMD_UPDATE_STADB.
4037 */
25d81b1e
LB		 4038struct ewc_ht_info {
4039 __le16 control1;
4040 __le16 control2;
4041 __le16 control3;
ba2d3587 4042} __packed;
25d81b1e
LB		 4043
4044struct peer_capability_info {
4045 /* Peer type - AP vs. STA. */
4046 __u8 peer_type;
4047
4048 /* Basic 802.11 capabilities from assoc resp. */
4049 __le16 basic_caps;
4050
4051 /* Set if peer supports 802.11n high throughput (HT). */
4052 __u8 ht_support;
4053
4054 /* Valid if HT is supported. */
4055 __le16 ht_caps;
4056 __u8 extended_ht_caps;
4057 struct ewc_ht_info ewc_info;
4058
4059 /* Legacy rate table. Intersection of our rates and peer rates. */
4060 __u8 legacy_rates[12];
4061
4062 /* HT rate table. Intersection of our rates and peer rates. */
4063 __u8 ht_rates[16];
4064 __u8 pad[16];
4065
4066 /* If set, interoperability mode, no proprietary extensions. */
4067 __u8 interop;
4068 __u8 pad2;
4069 __u8 station_id;
4070 __le16 amsdu_enabled;
ba2d3587 4071} __packed;
25d81b1e 4072
55489b6e
LB		 4073struct mwl8k_cmd_update_stadb {
4074 struct mwl8k_cmd_pkt header;
4075
4076 /* See STADB_ACTION_TYPE */
4077 __le32 action;
4078
4079 /* Peer MAC address */
4080 __u8 peer_addr[ETH_ALEN];
4081
4082 __le32 reserved;
4083
4084 /* Peer info - valid during add/update. */
4085 struct peer_capability_info peer_info;
ba2d3587 4086} __packed;
55489b6e 4087
a680400e
LB		 4088#define MWL8K_STA_DB_MODIFY_ENTRY 1
4089#define MWL8K_STA_DB_DEL_ENTRY 2
4090
4091/* Peer Entry flags - used to define the type of the peer node */
4092#define MWL8K_PEER_TYPE_ACCESSPOINT 2
4093
4094static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 4095 struct ieee80211_vif *vif,
13935e2c 4096 struct ieee80211_sta *sta)
55489b6e 4097{
55489b6e 4098 struct mwl8k_cmd_update_stadb *cmd;
a680400e 4099 struct peer_capability_info *p;
8707d026 4100 u32 rates;
55489b6e
LB		 4101 int rc;
4102
4103 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4104 if (cmd == NULL)
4105 return -ENOMEM;
4106
4107 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4108 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 4109 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 4110 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 4111
a680400e
LB		 4112 p = &cmd->peer_info;
4113 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
4114 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c 4115 p->ht_support = sta->ht_cap.ht_supported;
b603742f 4116 p->ht_caps = cpu_to_le16(sta->ht_cap.cap);
13935e2c
LB		 4117 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
4118 ((sta->ht_cap.ampdu_density & 7) << 2);
8707d026
LB		 4119 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
4120 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
4121 else
4122 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
4123 legacy_rate_mask_to_array(p->legacy_rates, rates);
13935e2c 4124 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB		 4125 p->interop = 1;
4126 p->amsdu_enabled = 0;
4127
4128 rc = mwl8k_post_cmd(hw, &cmd->header);
4129 kfree(cmd);
4130
4131 return rc ? rc : p->station_id;
4132}
4133
4134static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
4135 struct ieee80211_vif *vif, u8 *addr)
4136{
4137 struct mwl8k_cmd_update_stadb *cmd;
4138 int rc;
4139
4140 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4141 if (cmd == NULL)
4142 return -ENOMEM;
4143
4144 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4145 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4146 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 4147 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 4148
a680400e 4149 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 4150 kfree(cmd);
4151
4152 return rc;
4153}
4154
a66098da
LB		 4155
4156/*
4157 * Interrupt handling.
4158 */
4159static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
4160{
4161 struct ieee80211_hw *hw = dev_id;
4162 struct mwl8k_priv *priv = hw->priv;
4163 u32 status;
4164
4165 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB		 4166 if (!status)
4167 return IRQ_NONE;
4168
1e9f9de3
LB		 4169 if (status & MWL8K_A2H_INT_TX_DONE) {
4170 status &= ~MWL8K_A2H_INT_TX_DONE;
4171 tasklet_schedule(&priv->poll_tx_task);
4172 }
4173
a66098da 4174 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB		 4175 status &= ~MWL8K_A2H_INT_RX_READY;
4176 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB		 4177 }
4178
3aefc37e
NS		 4179 if (status & MWL8K_A2H_INT_BA_WATCHDOG) {
4180 status &= ~MWL8K_A2H_INT_BA_WATCHDOG;
4181 ieee80211_queue_work(hw, &priv->watchdog_ba_handle);
4182 }
4183
67e2eb27
LB		 4184 if (status)
4185 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4186
a66098da 4187 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 4188 if (priv->hostcmd_wait != NULL)
a66098da 4189 complete(priv->hostcmd_wait);
a66098da
LB		 4190 }
4191
4192 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 4193 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 4194 priv->radio_on && priv->pending_tx_pkts)
618952a7 4195 mwl8k_tx_start(priv);
a66098da
LB		 4196 }
4197
4198 return IRQ_HANDLED;
4199}
4200
1e9f9de3
LB		 4201static void mwl8k_tx_poll(unsigned long data)
4202{
4203 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
4204 struct mwl8k_priv *priv = hw->priv;
4205 int limit;
4206 int i;
4207
4208 limit = 32;
4209
4210 spin_lock_bh(&priv->tx_lock);
4211
e600707b 4212 for (i = 0; i < mwl8k_tx_queues(priv); i++)
1e9f9de3
LB		 4213 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
4214
4215 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
4216 complete(priv->tx_wait);
4217 priv->tx_wait = NULL;
4218 }
4219
4220 spin_unlock_bh(&priv->tx_lock);
4221
4222 if (limit) {
4223 writel(~MWL8K_A2H_INT_TX_DONE,
4224 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4225 } else {
4226 tasklet_schedule(&priv->poll_tx_task);
4227 }
4228}
4229
67e2eb27
LB		 4230static void mwl8k_rx_poll(unsigned long data)
4231{
4232 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
4233 struct mwl8k_priv *priv = hw->priv;
4234 int limit;
4235
4236 limit = 32;
4237 limit -= rxq_process(hw, 0, limit);
4238 limit -= rxq_refill(hw, 0, limit);
4239
4240 if (limit) {
4241 writel(~MWL8K_A2H_INT_RX_READY,
4242 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4243 } else {
4244 tasklet_schedule(&priv->poll_rx_task);
4245 }
4246}
4247
a66098da
LB		 4248
4249/*
4250 * Core driver operations.
4251 */
7bb45683 4252static void mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
a66098da
LB		 4253{
4254 struct mwl8k_priv *priv = hw->priv;
4255 int index = skb_get_queue_mapping(skb);
a66098da 4256
9189c100 4257 if (!priv->radio_on) {
c96c31e4
JP		 4258 wiphy_debug(hw->wiphy,
4259 "dropped TX frame since radio disabled\n");
a66098da 4260 dev_kfree_skb(skb);
7bb45683 4261 return;
a66098da
LB		 4262 }
4263
7bb45683 4264 mwl8k_txq_xmit(hw, index, skb);
a66098da
LB		 4265}
4266
a66098da
LB		 4267static int mwl8k_start(struct ieee80211_hw *hw)
4268{
a66098da
LB		 4269 struct mwl8k_priv *priv = hw->priv;
4270 int rc;
4271
a0607fd3 4272 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 4273 IRQF_SHARED, MWL8K_NAME, hw);
4274 if (rc) {
bf3ca7f7 4275 priv->irq = -1;
5db55844 4276 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
2ec610cb 4277 return -EIO;
a66098da 4278 }
bf3ca7f7 4279 priv->irq = priv->pdev->irq;
a66098da 4280
67e2eb27 4281 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 4282 tasklet_enable(&priv->poll_tx_task);
67e2eb27 4283 tasklet_enable(&priv->poll_rx_task);
2ec610cb 4284
a66098da 4285 /* Enable interrupts */
c23b5a69 4286 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 4287
2ec610cb
LB		 4288 rc = mwl8k_fw_lock(hw);
4289 if (!rc) {
55489b6e 4290 rc = mwl8k_cmd_radio_enable(hw);
a66098da 4291
5e4cf166
LB		 4292 if (!priv->ap_fw) {
4293 if (!rc)
55489b6e 4294 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 4295
5e4cf166
LB		 4296 if (!rc)
4297 rc = mwl8k_cmd_set_pre_scan(hw);
4298
4299 if (!rc)
4300 rc = mwl8k_cmd_set_post_scan(hw,
4301 "\x00\x00\x00\x00\x00\x00");
4302 }
2ec610cb
LB		 4303
4304 if (!rc)
55489b6e 4305 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 4306
2ec610cb 4307 if (!rc)
55489b6e 4308 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 4309
2ec610cb
LB		 4310 mwl8k_fw_unlock(hw);
4311 }
4312
4313 if (rc) {
4314 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
4315 free_irq(priv->pdev->irq, hw);
bf3ca7f7 4316 priv->irq = -1;
1e9f9de3 4317 tasklet_disable(&priv->poll_tx_task);
67e2eb27 4318 tasklet_disable(&priv->poll_rx_task);
2ec610cb 4319 }
a66098da
LB		 4320
4321 return rc;
4322}
4323
a66098da
LB		 4324static void mwl8k_stop(struct ieee80211_hw *hw)
4325{
a66098da
LB		 4326 struct mwl8k_priv *priv = hw->priv;
4327 int i;
4328
55489b6e 4329 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 4330
4331 ieee80211_stop_queues(hw);
4332
a66098da 4333 /* Disable interrupts */
a66098da 4334 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
bf3ca7f7
BC		 4335 if (priv->irq != -1) {
4336 free_irq(priv->pdev->irq, hw);
4337 priv->irq = -1;
4338 }
a66098da
LB		 4339
4340 /* Stop finalize join worker */
4341 cancel_work_sync(&priv->finalize_join_worker);
3aefc37e 4342 cancel_work_sync(&priv->watchdog_ba_handle);
a66098da
LB		 4343 if (priv->beacon_skb != NULL)
4344 dev_kfree_skb(priv->beacon_skb);
4345
67e2eb27 4346 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 4347 tasklet_disable(&priv->poll_tx_task);
67e2eb27 4348 tasklet_disable(&priv->poll_rx_task);
a66098da 4349
a66098da 4350 /* Return all skbs to mac80211 */
e600707b 4351 for (i = 0; i < mwl8k_tx_queues(priv); i++)
efb7c49a 4352 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB		 4353}
4354
0863ade8
BC		 4355static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image);
4356
a66098da 4357static int mwl8k_add_interface(struct ieee80211_hw *hw,
f5bb87cf 4358 struct ieee80211_vif *vif)
a66098da
LB		 4359{
4360 struct mwl8k_priv *priv = hw->priv;
4361 struct mwl8k_vif *mwl8k_vif;
ee0ddf18 4362 u32 macids_supported;
0863ade8
BC		 4363 int macid, rc;
4364 struct mwl8k_device_info *di;
a66098da 4365
a43c49a8
LB		 4366 /*
4367 * Reject interface creation if sniffer mode is active, as
4368 * STA operation is mutually exclusive with hardware sniffer
b64fe619 4369 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB		 4370 */
4371 if (priv->sniffer_enabled) {
c96c31e4
JP		 4372 wiphy_info(hw->wiphy,
4373 "unable to create STA interface because sniffer mode is enabled\n");
a43c49a8
LB		 4374 return -EINVAL;
4375 }
4376
0863ade8 4377 di = priv->device_info;
ee0ddf18
LB		 4378 switch (vif->type) {
4379 case NL80211_IFTYPE_AP:
0863ade8
BC		 4380 if (!priv->ap_fw && di->fw_image_ap) {
4381 /* we must load the ap fw to meet this request */
4382 if (!list_empty(&priv->vif_list))
4383 return -EBUSY;
4384 rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
4385 if (rc)
4386 return rc;
4387 }
ee0ddf18
LB		 4388 macids_supported = priv->ap_macids_supported;
4389 break;
4390 case NL80211_IFTYPE_STATION:
0863ade8
BC		 4391 if (priv->ap_fw && di->fw_image_sta) {
4392 /* we must load the sta fw to meet this request */
4393 if (!list_empty(&priv->vif_list))
4394 return -EBUSY;
4395 rc = mwl8k_reload_firmware(hw, di->fw_image_sta);
4396 if (rc)
4397 return rc;
4398 }
ee0ddf18
LB		 4399 macids_supported = priv->sta_macids_supported;
4400 break;
4401 default:
4402 return -EINVAL;
4403 }
4404
4405 macid = ffs(macids_supported & ~priv->macids_used);
4406 if (!macid--)
4407 return -EBUSY;
4408
f5bb87cf 4409 /* Setup driver private area. */
1ed32e4f 4410 mwl8k_vif = MWL8K_VIF(vif);
a66098da 4411 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
f5bb87cf 4412 mwl8k_vif->vif = vif;
ee0ddf18 4413 mwl8k_vif->macid = macid;
a66098da 4414 mwl8k_vif->seqno = 0;
d9a07d49
NS		 4415 memcpy(mwl8k_vif->bssid, vif->addr, ETH_ALEN);
4416 mwl8k_vif->is_hw_crypto_enabled = false;
a66098da 4417
aa21d0f6
LB		 4418 /* Set the mac address. */
4419 mwl8k_cmd_set_mac_addr(hw, vif, vif->addr);
4420
4421 if (priv->ap_fw)
4422 mwl8k_cmd_set_new_stn_add_self(hw, vif);
4423
ee0ddf18 4424 priv->macids_used |= 1 << mwl8k_vif->macid;
f5bb87cf 4425 list_add_tail(&mwl8k_vif->list, &priv->vif_list);
a66098da
LB		 4426
4427 return 0;
4428}
4429
4430static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4431 struct ieee80211_vif *vif)
a66098da
LB		 4432{
4433 struct mwl8k_priv *priv = hw->priv;
f5bb87cf 4434 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
a66098da 4435
b64fe619
LB		 4436 if (priv->ap_fw)
4437 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
4438
aa21d0f6 4439 mwl8k_cmd_set_mac_addr(hw, vif, "\x00\x00\x00\x00\x00\x00");
32060e1b 4440
ee0ddf18 4441 priv->macids_used &= ~(1 << mwl8k_vif->macid);
f5bb87cf 4442 list_del(&mwl8k_vif->list);
a66098da
LB		 4443}
4444
ee03a932 4445static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 4446{
a66098da
LB		 4447 struct ieee80211_conf *conf = &hw->conf;
4448 struct mwl8k_priv *priv = hw->priv;
ee03a932 4449 int rc;
a66098da 4450
7595d67a 4451 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 4452 mwl8k_cmd_radio_disable(hw);
ee03a932 4453 return 0;
7595d67a
LB		 4454 }
4455
ee03a932
LB		 4456 rc = mwl8k_fw_lock(hw);
4457 if (rc)
4458 return rc;
a66098da 4459
55489b6e 4460 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 4461 if (rc)
4462 goto out;
a66098da 4463
610677d2 4464 rc = mwl8k_cmd_set_rf_channel(hw, conf);
ee03a932
LB		 4465 if (rc)
4466 goto out;
4467
a66098da
LB		 4468 if (conf->power_level > 18)
4469 conf->power_level = 18;
a66098da 4470
08b06347 4471 if (priv->ap_fw) {
03217087
NS		 4472
4473 if (conf->flags & IEEE80211_CONF_CHANGE_POWER) {
4474 rc = mwl8k_cmd_tx_power(hw, conf, conf->power_level);
4475 if (rc)
4476 goto out;
4477 }
41fdf097 4478
da62b761
NS		 4479 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x3);
4480 if (rc)
4481 wiphy_warn(hw->wiphy, "failed to set # of RX antennas");
4482 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
4483 if (rc)
4484 wiphy_warn(hw->wiphy, "failed to set # of TX antennas");
4485
08b06347 4486 } else {
41fdf097
NS		 4487 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
4488 if (rc)
4489 goto out;
08b06347
LB		 4490 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
4491 }
a66098da 4492
ee03a932
LB		 4493out:
4494 mwl8k_fw_unlock(hw);
a66098da 4495
ee03a932 4496 return rc;
a66098da
LB		 4497}
4498
b64fe619
LB		 4499static void
4500mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4501 struct ieee80211_bss_conf *info, u32 changed)
a66098da 4502{
a66098da 4503 struct mwl8k_priv *priv = hw->priv;
ba30c4a5 4504 u32 ap_legacy_rates = 0;
13935e2c 4505 u8 ap_mcs_rates[16];
3a980d0a
LB		 4506 int rc;
4507
c3cbbe8a 4508 if (mwl8k_fw_lock(hw))
3a980d0a 4509 return;
a66098da 4510
c3cbbe8a
LB		 4511 /*
4512 * No need to capture a beacon if we're no longer associated.
4513 */
4514 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
4515 priv->capture_beacon = false;
3a980d0a 4516
c3cbbe8a 4517 /*
13935e2c 4518 * Get the AP's legacy and MCS rates.
c3cbbe8a 4519 */
7dc6a7a7 4520 if (vif->bss_conf.assoc) {
c6e96010 4521 struct ieee80211_sta *ap;
c97470dd 4522
c6e96010 4523 rcu_read_lock();
c6e96010 4524
c3cbbe8a
LB		 4525 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
4526 if (ap == NULL) {
4527 rcu_read_unlock();
c6e96010 4528 goto out;
c3cbbe8a
LB		 4529 }
4530
8707d026
LB		 4531 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
4532 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
4533 } else {
4534 ap_legacy_rates =
4535 ap->supp_rates[IEEE80211_BAND_5GHZ] << 5;
4536 }
13935e2c 4537 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB		 4538
4539 rcu_read_unlock();
4540 }
c6e96010 4541
c3cbbe8a 4542 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
13935e2c 4543 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB		 4544 if (rc)
4545 goto out;
a66098da 4546
b71ed2c6 4547 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB		 4548 if (rc)
4549 goto out;
c3cbbe8a 4550 }
a66098da 4551
c3cbbe8a 4552 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB		 4553 rc = mwl8k_set_radio_preamble(hw,
4554 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 4555 if (rc)
4556 goto out;
c3cbbe8a 4557 }
a66098da 4558
c3cbbe8a 4559 if (changed & BSS_CHANGED_ERP_SLOT) {
7dc6a7a7 4560 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 4561 if (rc)
4562 goto out;
c3cbbe8a 4563 }
a66098da 4564
c97470dd
LB		 4565 if (vif->bss_conf.assoc &&
4566 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
4567 BSS_CHANGED_HT))) {
c3cbbe8a 4568 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB		 4569 if (rc)
4570 goto out;
c3cbbe8a 4571 }
a66098da 4572
c3cbbe8a
LB		 4573 if (vif->bss_conf.assoc &&
4574 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB		 4575 /*
4576 * Finalize the join. Tell rx handler to process
4577 * next beacon from our BSSID.
4578 */
0a11dfc3 4579 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 4580 priv->capture_beacon = true;
a66098da
LB		 4581 }
4582
3a980d0a
LB		 4583out:
4584 mwl8k_fw_unlock(hw);
a66098da
LB		 4585}
4586
b64fe619
LB		 4587static void
4588mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4589 struct ieee80211_bss_conf *info, u32 changed)
4590{
4591 int rc;
4592
4593 if (mwl8k_fw_lock(hw))
4594 return;
4595
4596 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4597 rc = mwl8k_set_radio_preamble(hw,
4598 vif->bss_conf.use_short_preamble);
4599 if (rc)
4600 goto out;
4601 }
4602
4603 if (changed & BSS_CHANGED_BASIC_RATES) {
4604 int idx;
4605 int rate;
4606
4607 /*
4608 * Use lowest supported basic rate for multicasts
4609 * and management frames (such as probe responses --
4610 * beacons will always go out at 1 Mb/s).
4611 */
4612 idx = ffs(vif->bss_conf.basic_rates);
8707d026
LB		 4613 if (idx)
4614 idx--;
4615
4616 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
4617 rate = mwl8k_rates_24[idx].hw_value;
4618 else
4619 rate = mwl8k_rates_50[idx].hw_value;
b64fe619
LB		 4620
4621 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
4622 }
4623
4624 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
4625 struct sk_buff *skb;
4626
4627 skb = ieee80211_beacon_get(hw, vif);
4628 if (skb != NULL) {
aa21d0f6 4629 mwl8k_cmd_set_beacon(hw, vif, skb->data, skb->len);
b64fe619
LB		 4630 kfree_skb(skb);
4631 }
4632 }
4633
4634 if (changed & BSS_CHANGED_BEACON_ENABLED)
aa21d0f6 4635 mwl8k_cmd_bss_start(hw, vif, info->enable_beacon);
b64fe619
LB		 4636
4637out:
4638 mwl8k_fw_unlock(hw);
4639}
4640
4641static void
4642mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4643 struct ieee80211_bss_conf *info, u32 changed)
4644{
4645 struct mwl8k_priv *priv = hw->priv;
4646
4647 if (!priv->ap_fw)
4648 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
4649 else
4650 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
4651}
4652
e81cd2d6 4653static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 4654 struct netdev_hw_addr_list *mc_list)
e81cd2d6
LB		 4655{
4656 struct mwl8k_cmd_pkt *cmd;
4657
447ced07
LB		 4658 /*
4659 * Synthesize and return a command packet that programs the
4660 * hardware multicast address filter. At this point we don't
4661 * know whether FIF_ALLMULTI is being requested, but if it is,
4662 * we'll end up throwing this packet away and creating a new
4663 * one in mwl8k_configure_filter().
4664 */
22bedad3 4665 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_list);
e81cd2d6
LB		 4666
4667 return (unsigned long)cmd;
4668}
4669
a43c49a8
LB		 4670static int
4671mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
4672 unsigned int changed_flags,
4673 unsigned int *total_flags)
4674{
4675 struct mwl8k_priv *priv = hw->priv;
4676
4677 /*
4678 * Hardware sniffer mode is mutually exclusive with STA
4679 * operation, so refuse to enable sniffer mode if a STA
4680 * interface is active.
4681 */
f5bb87cf 4682 if (!list_empty(&priv->vif_list)) {
a43c49a8 4683 if (net_ratelimit())
c96c31e4
JP		 4684 wiphy_info(hw->wiphy,
4685 "not enabling sniffer mode because STA interface is active\n");
a43c49a8
LB		 4686 return 0;
4687 }
4688
4689 if (!priv->sniffer_enabled) {
55489b6e 4690 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 4691 return 0;
4692 priv->sniffer_enabled = true;
4693 }
4694
4695 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
4696 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
4697 FIF_OTHER_BSS;
4698
4699 return 1;
4700}
4701
f5bb87cf
LB		 4702static struct mwl8k_vif *mwl8k_first_vif(struct mwl8k_priv *priv)
4703{
4704 if (!list_empty(&priv->vif_list))
4705 return list_entry(priv->vif_list.next, struct mwl8k_vif, list);
4706
4707 return NULL;
4708}
4709
e6935ea1
LB		 4710static void mwl8k_configure_filter(struct ieee80211_hw *hw,
4711 unsigned int changed_flags,
4712 unsigned int *total_flags,
4713 u64 multicast)
4714{
4715 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 4716 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
4717
c0adae2c
LB		 4718 /*
4719 * AP firmware doesn't allow fine-grained control over
4720 * the receive filter.
4721 */
4722 if (priv->ap_fw) {
4723 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
4724 kfree(cmd);
4725 return;
4726 }
4727
a43c49a8
LB		 4728 /*
4729 * Enable hardware sniffer mode if FIF_CONTROL or
4730 * FIF_OTHER_BSS is requested.
4731 */
4732 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
4733 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
4734 kfree(cmd);
4735 return;
4736 }
a66098da 4737
e6935ea1 4738 /* Clear unsupported feature flags */
447ced07 4739 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 4740
90852f7a
LB		 4741 if (mwl8k_fw_lock(hw)) {
4742 kfree(cmd);
e6935ea1 4743 return;
90852f7a 4744 }
a66098da 4745
a43c49a8 4746 if (priv->sniffer_enabled) {
55489b6e 4747 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 4748 priv->sniffer_enabled = false;
4749 }
4750
e6935ea1 4751 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 4752 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
4753 /*
4754 * Disable the BSS filter.
4755 */
e6935ea1 4756 mwl8k_cmd_set_pre_scan(hw);
77165d88 4757 } else {
f5bb87cf 4758 struct mwl8k_vif *mwl8k_vif;
0a11dfc3 4759 const u8 *bssid;
a94cc97e 4760
77165d88
LB		 4761 /*
4762 * Enable the BSS filter.
4763 *
4764 * If there is an active STA interface, use that
4765 * interface's BSSID, otherwise use a dummy one
4766 * (where the OUI part needs to be nonzero for
4767 * the BSSID to be accepted by POST_SCAN).
4768 */
f5bb87cf
LB		 4769 mwl8k_vif = mwl8k_first_vif(priv);
4770 if (mwl8k_vif != NULL)
4771 bssid = mwl8k_vif->vif->bss_conf.bssid;
4772 else
4773 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 4774
e6935ea1 4775 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 4776 }
4777 }
4778
447ced07
LB		 4779 /*
4780 * If FIF_ALLMULTI is being requested, throw away the command
4781 * packet that ->prepare_multicast() built and replace it with
4782 * a command packet that enables reception of all multicast
4783 * packets.
4784 */
4785 if (*total_flags & FIF_ALLMULTI) {
4786 kfree(cmd);
22bedad3 4787 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, NULL);
447ced07
LB		 4788 }
4789
4790 if (cmd != NULL) {
4791 mwl8k_post_cmd(hw, cmd);
4792 kfree(cmd);
e6935ea1 4793 }
a66098da 4794
e6935ea1 4795 mwl8k_fw_unlock(hw);
a66098da
LB		 4796}
4797
a66098da
LB		 4798static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4799{
c2c2b12a 4800 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB		 4801}
4802
4a6967b8
JB		 4803static int mwl8k_sta_remove(struct ieee80211_hw *hw,
4804 struct ieee80211_vif *vif,
4805 struct ieee80211_sta *sta)
3f5610ff
LB		 4806{
4807 struct mwl8k_priv *priv = hw->priv;
4808
4a6967b8
JB		 4809 if (priv->ap_fw)
4810 return mwl8k_cmd_set_new_stn_del(hw, vif, sta->addr);
4811 else
4812 return mwl8k_cmd_update_stadb_del(hw, vif, sta->addr);
bbfd9128
LB		 4813}
4814
4a6967b8
JB		 4815static int mwl8k_sta_add(struct ieee80211_hw *hw,
4816 struct ieee80211_vif *vif,
4817 struct ieee80211_sta *sta)
bbfd9128
LB		 4818{
4819 struct mwl8k_priv *priv = hw->priv;
4a6967b8 4820 int ret;
fcdc403c
NS		 4821 int i;
4822 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4823 struct ieee80211_key_conf *key;
bbfd9128 4824
4a6967b8
JB		 4825 if (!priv->ap_fw) {
4826 ret = mwl8k_cmd_update_stadb_add(hw, vif, sta);
4827 if (ret >= 0) {
4828 MWL8K_STA(sta)->peer_id = ret;
17033543
NS		 4829 if (sta->ht_cap.ht_supported)
4830 MWL8K_STA(sta)->is_ampdu_allowed = true;
fcdc403c 4831 ret = 0;
4a6967b8 4832 }
bbfd9128 4833
d9a07d49
NS		 4834 } else {
4835 ret = mwl8k_cmd_set_new_stn_add(hw, vif, sta);
bbfd9128 4836 }
4a6967b8 4837
d9a07d49
NS		 4838 for (i = 0; i < NUM_WEP_KEYS; i++) {
4839 key = IEEE80211_KEY_CONF(mwl8k_vif->wep_key_conf[i].key);
4840 if (mwl8k_vif->wep_key_conf[i].enabled)
4841 mwl8k_set_key(hw, SET_KEY, vif, sta, key);
4842 }
fcdc403c 4843 return ret;
bbfd9128
LB		 4844}
4845
a66098da
LB		 4846static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
4847 const struct ieee80211_tx_queue_params *params)
4848{
3e4f542c 4849 struct mwl8k_priv *priv = hw->priv;
a66098da 4850 int rc;
a66098da 4851
3e4f542c
LB		 4852 rc = mwl8k_fw_lock(hw);
4853 if (!rc) {
e600707b 4854 BUG_ON(queue > MWL8K_TX_WMM_QUEUES - 1);
0863ade8
BC		 4855 memcpy(&priv->wmm_params[queue], params, sizeof(*params));
4856
3e4f542c 4857 if (!priv->wmm_enabled)
55489b6e 4858 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 4859
85c9205c 4860 if (!rc) {
e600707b 4861 int q = MWL8K_TX_WMM_QUEUES - 1 - queue;
85c9205c 4862 rc = mwl8k_cmd_set_edca_params(hw, q,
55489b6e
LB		 4863 params->cw_min,
4864 params->cw_max,
4865 params->aifs,
4866 params->txop);
85c9205c 4867 }
3e4f542c
LB		 4868
4869 mwl8k_fw_unlock(hw);
a66098da 4870 }
3e4f542c 4871
a66098da
LB		 4872 return rc;
4873}
4874
a66098da
LB		 4875static int mwl8k_get_stats(struct ieee80211_hw *hw,
4876 struct ieee80211_low_level_stats *stats)
4877{
55489b6e 4878 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 4879}
4880
0d462bbb
JL		 4881static int mwl8k_get_survey(struct ieee80211_hw *hw, int idx,
4882 struct survey_info *survey)
4883{
4884 struct mwl8k_priv *priv = hw->priv;
4885 struct ieee80211_conf *conf = &hw->conf;
4886
4887 if (idx != 0)
4888 return -ENOENT;
4889
4890 survey->channel = conf->channel;
4891 survey->filled = SURVEY_INFO_NOISE_DBM;
4892 survey->noise = priv->noise;
4893
4894 return 0;
4895}
4896
65f3ddcd
NS		 4897#define MAX_AMPDU_ATTEMPTS 5
4898
a2292d83
LB		 4899static int
4900mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4901 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 4902 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4903 u8 buf_size)
a2292d83 4904{
65f3ddcd
NS		 4905
4906 int i, rc = 0;
4907 struct mwl8k_priv *priv = hw->priv;
4908 struct mwl8k_ampdu_stream *stream;
4909 u8 *addr = sta->addr;
4910
4911 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
4912 return -ENOTSUPP;
4913
4914 spin_lock(&priv->stream_lock);
4915 stream = mwl8k_lookup_stream(hw, addr, tid);
4916
a2292d83
LB		 4917 switch (action) {
4918 case IEEE80211_AMPDU_RX_START:
4919 case IEEE80211_AMPDU_RX_STOP:
65f3ddcd
NS		 4920 break;
4921 case IEEE80211_AMPDU_TX_START:
4922 /* By the time we get here the hw queues may contain outgoing
4923 * packets for this RA/TID that are not part of this BA
4924 * session. The hw will assign sequence numbers to these
4925 * packets as they go out. So if we query the hw for its next
4926 * sequence number and use that for the SSN here, it may end up
4927 * being wrong, which will lead to sequence number mismatch at
4928 * the recipient. To avoid this, we reset the sequence number
4929 * to O for the first MPDU in this BA stream.
4930 */
4931 *ssn = 0;
4932 if (stream == NULL) {
4933 /* This means that somebody outside this driver called
4934 * ieee80211_start_tx_ba_session. This is unexpected
4935 * because we do our own rate control. Just warn and
4936 * move on.
4937 */
4938 wiphy_warn(hw->wiphy, "Unexpected call to %s. "
4939 "Proceeding anyway.\n", __func__);
4940 stream = mwl8k_add_stream(hw, sta, tid);
4941 }
4942 if (stream == NULL) {
4943 wiphy_debug(hw->wiphy, "no free AMPDU streams\n");
4944 rc = -EBUSY;
4945 break;
4946 }
4947 stream->state = AMPDU_STREAM_IN_PROGRESS;
4948
4949 /* Release the lock before we do the time consuming stuff */
4950 spin_unlock(&priv->stream_lock);
4951 for (i = 0; i < MAX_AMPDU_ATTEMPTS; i++) {
4952 rc = mwl8k_check_ba(hw, stream);
4953
4954 if (!rc)
4955 break;
4956 /*
4957 * HW queues take time to be flushed, give them
4958 * sufficient time
4959 */
4960
4961 msleep(1000);
4962 }
4963 spin_lock(&priv->stream_lock);
4964 if (rc) {
4965 wiphy_err(hw->wiphy, "Stream for tid %d busy after %d"
4966 " attempts\n", tid, MAX_AMPDU_ATTEMPTS);
4967 mwl8k_remove_stream(hw, stream);
4968 rc = -EBUSY;
4969 break;
4970 }
4971 ieee80211_start_tx_ba_cb_irqsafe(vif, addr, tid);
4972 break;
4973 case IEEE80211_AMPDU_TX_STOP:
4974 if (stream == NULL)
4975 break;
4976 if (stream->state == AMPDU_STREAM_ACTIVE) {
4977 spin_unlock(&priv->stream_lock);
4978 mwl8k_destroy_ba(hw, stream);
4979 spin_lock(&priv->stream_lock);
4980 }
4981 mwl8k_remove_stream(hw, stream);
4982 ieee80211_stop_tx_ba_cb_irqsafe(vif, addr, tid);
4983 break;
4984 case IEEE80211_AMPDU_TX_OPERATIONAL:
4985 BUG_ON(stream == NULL);
4986 BUG_ON(stream->state != AMPDU_STREAM_IN_PROGRESS);
4987 spin_unlock(&priv->stream_lock);
4988 rc = mwl8k_create_ba(hw, stream, buf_size);
4989 spin_lock(&priv->stream_lock);
4990 if (!rc)
4991 stream->state = AMPDU_STREAM_ACTIVE;
4992 else {
4993 spin_unlock(&priv->stream_lock);
4994 mwl8k_destroy_ba(hw, stream);
4995 spin_lock(&priv->stream_lock);
4996 wiphy_debug(hw->wiphy,
4997 "Failed adding stream for sta %pM tid %d\n",
4998 addr, tid);
4999 mwl8k_remove_stream(hw, stream);
5000 }
5001 break;
5002
a2292d83 5003 default:
65f3ddcd 5004 rc = -ENOTSUPP;
a2292d83 5005 }
65f3ddcd
NS		 5006
5007 spin_unlock(&priv->stream_lock);
5008 return rc;
a2292d83
LB		 5009}
5010
a66098da
LB		 5011static const struct ieee80211_ops mwl8k_ops = {
5012 .tx = mwl8k_tx,
5013 .start = mwl8k_start,
5014 .stop = mwl8k_stop,
5015 .add_interface = mwl8k_add_interface,
5016 .remove_interface = mwl8k_remove_interface,
5017 .config = mwl8k_config,
a66098da 5018 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 5019 .prepare_multicast = mwl8k_prepare_multicast,
a66098da 5020 .configure_filter = mwl8k_configure_filter,
fcdc403c 5021 .set_key = mwl8k_set_key,
a66098da 5022 .set_rts_threshold = mwl8k_set_rts_threshold,
4a6967b8
JB		 5023 .sta_add = mwl8k_sta_add,
5024 .sta_remove = mwl8k_sta_remove,
a66098da 5025 .conf_tx = mwl8k_conf_tx,
a66098da 5026 .get_stats = mwl8k_get_stats,
0d462bbb 5027 .get_survey = mwl8k_get_survey,
a2292d83 5028 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB		 5029};
5030
a66098da
LB		 5031static void mwl8k_finalize_join_worker(struct work_struct *work)
5032{
5033 struct mwl8k_priv *priv =
5034 container_of(work, struct mwl8k_priv, finalize_join_worker);
5035 struct sk_buff *skb = priv->beacon_skb;
56007a02
JB		 5036 struct ieee80211_mgmt *mgmt = (void *)skb->data;
5037 int len = skb->len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
5038 const u8 *tim = cfg80211_find_ie(WLAN_EID_TIM,
5039 mgmt->u.beacon.variable, len);
5040 int dtim_period = 1;
5041
5042 if (tim && tim[1] >= 2)
5043 dtim_period = tim[3];
a66098da 5044
56007a02 5045 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, dtim_period);
a66098da 5046
f5bb87cf 5047 dev_kfree_skb(skb);
a66098da
LB		 5048 priv->beacon_skb = NULL;
5049}
5050
bcb628d5 5051enum {
9e1b17ea
LB		 5052 MWL8363 = 0,
5053 MWL8687,
bcb628d5 5054 MWL8366,
6f6d1e9a
LB		 5055};
5056
8a7a578c 5057#define MWL8K_8366_AP_FW_API 2
952a0e96
BC		 5058#define _MWL8K_8366_AP_FW(api) "mwl8k/fmimage_8366_ap-" #api ".fw"
5059#define MWL8K_8366_AP_FW(api) _MWL8K_8366_AP_FW(api)
5060
bcb628d5 5061static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
9e1b17ea
LB		 5062 [MWL8363] = {
5063 .part_name = "88w8363",
5064 .helper_image = "mwl8k/helper_8363.fw",
0863ade8 5065 .fw_image_sta = "mwl8k/fmimage_8363.fw",
9e1b17ea 5066 },
49eb691c 5067 [MWL8687] = {
bcb628d5
JL		 5068 .part_name = "88w8687",
5069 .helper_image = "mwl8k/helper_8687.fw",
0863ade8 5070 .fw_image_sta = "mwl8k/fmimage_8687.fw",
bcb628d5 5071 },
49eb691c 5072 [MWL8366] = {
bcb628d5
JL		 5073 .part_name = "88w8366",
5074 .helper_image = "mwl8k/helper_8366.fw",
0863ade8 5075 .fw_image_sta = "mwl8k/fmimage_8366.fw",
952a0e96
BC		 5076 .fw_image_ap = MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API),
5077 .fw_api_ap = MWL8K_8366_AP_FW_API,
89a91f4f 5078 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 5079 },
45a390dd
LB		 5080};
5081
c92d4ede
LB		 5082MODULE_FIRMWARE("mwl8k/helper_8363.fw");
5083MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
5084MODULE_FIRMWARE("mwl8k/helper_8687.fw");
5085MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
5086MODULE_FIRMWARE("mwl8k/helper_8366.fw");
5087MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
952a0e96 5088MODULE_FIRMWARE(MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API));
c92d4ede 5089
45a390dd 5090static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
e5868ba1 5091 { PCI_VDEVICE(MARVELL, 0x2a0a), .driver_data = MWL8363, },
9e1b17ea
LB		 5092 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
5093 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL		 5094 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
5095 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
5096 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
ca66527c 5097 { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
bcb628d5 5098 { },
45a390dd
LB		 5099};
5100MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
5101
99020471
BC		 5102static int mwl8k_request_alt_fw(struct mwl8k_priv *priv)
5103{
5104 int rc;
5105 printk(KERN_ERR "%s: Error requesting preferred fw %s.\n"
5106 "Trying alternative firmware %s\n", pci_name(priv->pdev),
5107 priv->fw_pref, priv->fw_alt);
5108 rc = mwl8k_request_fw(priv, priv->fw_alt, &priv->fw_ucode, true);
5109 if (rc) {
5110 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5111 pci_name(priv->pdev), priv->fw_alt);
5112 return rc;
5113 }
5114 return 0;
5115}
5116
5117static int mwl8k_firmware_load_success(struct mwl8k_priv *priv);
5118static void mwl8k_fw_state_machine(const struct firmware *fw, void *context)
5119{
5120 struct mwl8k_priv *priv = context;
5121 struct mwl8k_device_info *di = priv->device_info;
5122 int rc;
5123
5124 switch (priv->fw_state) {
5125 case FW_STATE_INIT:
5126 if (!fw) {
5127 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
5128 pci_name(priv->pdev), di->helper_image);
5129 goto fail;
5130 }
5131 priv->fw_helper = fw;
5132 rc = mwl8k_request_fw(priv, priv->fw_pref, &priv->fw_ucode,
5133 true);
5134 if (rc && priv->fw_alt) {
5135 rc = mwl8k_request_alt_fw(priv);
5136 if (rc)
5137 goto fail;
5138 priv->fw_state = FW_STATE_LOADING_ALT;
5139 } else if (rc)
5140 goto fail;
5141 else
5142 priv->fw_state = FW_STATE_LOADING_PREF;
5143 break;
5144
5145 case FW_STATE_LOADING_PREF:
5146 if (!fw) {
5147 if (priv->fw_alt) {
5148 rc = mwl8k_request_alt_fw(priv);
5149 if (rc)
5150 goto fail;
5151 priv->fw_state = FW_STATE_LOADING_ALT;
5152 } else
5153 goto fail;
5154 } else {
5155 priv->fw_ucode = fw;
5156 rc = mwl8k_firmware_load_success(priv);
5157 if (rc)
5158 goto fail;
5159 else
5160 complete(&priv->firmware_loading_complete);
5161 }
5162 break;
5163
5164 case FW_STATE_LOADING_ALT:
5165 if (!fw) {
5166 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5167 pci_name(priv->pdev), di->helper_image);
5168 goto fail;
5169 }
5170 priv->fw_ucode = fw;
5171 rc = mwl8k_firmware_load_success(priv);
5172 if (rc)
5173 goto fail;
5174 else
5175 complete(&priv->firmware_loading_complete);
5176 break;
5177
5178 default:
5179 printk(KERN_ERR "%s: Unexpected firmware loading state: %d\n",
5180 MWL8K_NAME, priv->fw_state);
5181 BUG_ON(1);
5182 }
5183
5184 return;
5185
5186fail:
5187 priv->fw_state = FW_STATE_ERROR;
5188 complete(&priv->firmware_loading_complete);
5189 device_release_driver(&priv->pdev->dev);
5190 mwl8k_release_firmware(priv);
5191}
5192
5193static int mwl8k_init_firmware(struct ieee80211_hw *hw, char *fw_image,
5194 bool nowait)
a66098da 5195{
3cc7772c 5196 struct mwl8k_priv *priv = hw->priv;
a66098da 5197 int rc;
be695fc4
LB		 5198
5199 /* Reset firmware and hardware */
5200 mwl8k_hw_reset(priv);
5201
5202 /* Ask userland hotplug daemon for the device firmware */
99020471 5203 rc = mwl8k_request_firmware(priv, fw_image, nowait);
be695fc4 5204 if (rc) {
5db55844 5205 wiphy_err(hw->wiphy, "Firmware files not found\n");
3cc7772c 5206 return rc;
be695fc4
LB		 5207 }
5208
99020471
BC		 5209 if (nowait)
5210 return rc;
5211
be695fc4
LB		 5212 /* Load firmware into hardware */
5213 rc = mwl8k_load_firmware(hw);
3cc7772c 5214 if (rc)
5db55844 5215 wiphy_err(hw->wiphy, "Cannot start firmware\n");
be695fc4
LB		 5216
5217 /* Reclaim memory once firmware is successfully loaded */
5218 mwl8k_release_firmware(priv);
5219
3cc7772c
BC		 5220 return rc;
5221}
5222
73b46320
BC		 5223static int mwl8k_init_txqs(struct ieee80211_hw *hw)
5224{
5225 struct mwl8k_priv *priv = hw->priv;
5226 int rc = 0;
5227 int i;
5228
e600707b 5229 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
73b46320
BC		 5230 rc = mwl8k_txq_init(hw, i);
5231 if (rc)
5232 break;
5233 if (priv->ap_fw)
5234 iowrite32(priv->txq[i].txd_dma,
5235 priv->sram + priv->txq_offset[i]);
5236 }
5237 return rc;
5238}
5239
3cc7772c
BC		 5240/* initialize hw after successfully loading a firmware image */
5241static int mwl8k_probe_hw(struct ieee80211_hw *hw)
5242{
5243 struct mwl8k_priv *priv = hw->priv;
5244 int rc = 0;
5245 int i;
be695fc4 5246
91942230 5247 if (priv->ap_fw) {
89a91f4f 5248 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230 5249 if (priv->rxd_ops == NULL) {
c96c31e4
JP		 5250 wiphy_err(hw->wiphy,
5251 "Driver does not have AP firmware image support for this hardware\n");
91942230
LB		 5252 goto err_stop_firmware;
5253 }
5254 } else {
89a91f4f 5255 priv->rxd_ops = &rxd_sta_ops;
91942230 5256 }
be695fc4
LB		 5257
5258 priv->sniffer_enabled = false;
5259 priv->wmm_enabled = false;
5260 priv->pending_tx_pkts = 0;
5261
a66098da
LB		 5262 rc = mwl8k_rxq_init(hw, 0);
5263 if (rc)
3cc7772c 5264 goto err_stop_firmware;
a66098da
LB		 5265 rxq_refill(hw, 0, INT_MAX);
5266
73b46320
BC		 5267 /* For the sta firmware, we need to know the dma addresses of tx queues
5268 * before sending MWL8K_CMD_GET_HW_SPEC. So we must initialize them
5269 * prior to issuing this command. But for the AP case, we learn the
5270 * total number of queues from the result CMD_GET_HW_SPEC, so for this
5271 * case we must initialize the tx queues after.
5272 */
8a7a578c 5273 priv->num_ampdu_queues = 0;
73b46320
BC		 5274 if (!priv->ap_fw) {
5275 rc = mwl8k_init_txqs(hw);
a66098da
LB		 5276 if (rc)
5277 goto err_free_queues;
5278 }
5279
5280 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 5281 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3aefc37e
NS		 5282 iowrite32(MWL8K_A2H_INT_TX_DONE|MWL8K_A2H_INT_RX_READY|
5283 MWL8K_A2H_INT_BA_WATCHDOG,
1e9f9de3 5284 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
a66098da
LB		 5285 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
5286
a0607fd3 5287 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 5288 IRQF_SHARED, MWL8K_NAME, hw);
5289 if (rc) {
5db55844 5290 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
a66098da
LB		 5291 goto err_free_queues;
5292 }
5293
ac109fd0
BC		 5294 memset(priv->ampdu, 0, sizeof(priv->ampdu));
5295
a66098da
LB		 5296 /*
5297 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 5298 * commands use interrupts and avoid polling. Disable
a66098da
LB		 5299 * interrupts when done.
5300 */
c23b5a69 5301 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5302
5303 /* Get config data, mac addrs etc */
42fba21d
LB		 5304 if (priv->ap_fw) {
5305 rc = mwl8k_cmd_get_hw_spec_ap(hw);
73b46320
BC		 5306 if (!rc)
5307 rc = mwl8k_init_txqs(hw);
42fba21d
LB		 5308 if (!rc)
5309 rc = mwl8k_cmd_set_hw_spec(hw);
5310 } else {
5311 rc = mwl8k_cmd_get_hw_spec_sta(hw);
5312 }
a66098da 5313 if (rc) {
5db55844 5314 wiphy_err(hw->wiphy, "Cannot initialise firmware\n");
be695fc4 5315 goto err_free_irq;
a66098da
LB		 5316 }
5317
5318 /* Turn radio off */
55489b6e 5319 rc = mwl8k_cmd_radio_disable(hw);
a66098da 5320 if (rc) {
5db55844 5321 wiphy_err(hw->wiphy, "Cannot disable\n");
be695fc4 5322 goto err_free_irq;
a66098da
LB		 5323 }
5324
32060e1b 5325 /* Clear MAC address */
aa21d0f6 5326 rc = mwl8k_cmd_set_mac_addr(hw, NULL, "\x00\x00\x00\x00\x00\x00");
32060e1b 5327 if (rc) {
5db55844 5328 wiphy_err(hw->wiphy, "Cannot clear MAC address\n");
be695fc4 5329 goto err_free_irq;
32060e1b
LB		 5330 }
5331
a66098da 5332 /* Disable interrupts */
a66098da 5333 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5334 free_irq(priv->pdev->irq, hw);
5335
c96c31e4
JP		 5336 wiphy_info(hw->wiphy, "%s v%d, %pm, %s firmware %u.%u.%u.%u\n",
5337 priv->device_info->part_name,
5338 priv->hw_rev, hw->wiphy->perm_addr,
5339 priv->ap_fw ? "AP" : "STA",
5340 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
5341 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 5342
5343 return 0;
5344
a66098da 5345err_free_irq:
a66098da 5346 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5347 free_irq(priv->pdev->irq, hw);
5348
5349err_free_queues:
e600707b 5350 for (i = 0; i < mwl8k_tx_queues(priv); i++)
a66098da
LB		 5351 mwl8k_txq_deinit(hw, i);
5352 mwl8k_rxq_deinit(hw, 0);
5353
3cc7772c
BC		 5354err_stop_firmware:
5355 mwl8k_hw_reset(priv);
5356
5357 return rc;
5358}
5359
5360/*
5361 * invoke mwl8k_reload_firmware to change the firmware image after the device
5362 * has already been registered
5363 */
5364static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image)
5365{
5366 int i, rc = 0;
5367 struct mwl8k_priv *priv = hw->priv;
5368
5369 mwl8k_stop(hw);
5370 mwl8k_rxq_deinit(hw, 0);
5371
e600707b 5372 for (i = 0; i < mwl8k_tx_queues(priv); i++)
3cc7772c
BC		 5373 mwl8k_txq_deinit(hw, i);
5374
99020471 5375 rc = mwl8k_init_firmware(hw, fw_image, false);
3cc7772c
BC		 5376 if (rc)
5377 goto fail;
5378
5379 rc = mwl8k_probe_hw(hw);
5380 if (rc)
5381 goto fail;
5382
5383 rc = mwl8k_start(hw);
5384 if (rc)
5385 goto fail;
5386
5387 rc = mwl8k_config(hw, ~0);
5388 if (rc)
5389 goto fail;
5390
e600707b 5391 for (i = 0; i < MWL8K_TX_WMM_QUEUES; i++) {
3cc7772c
BC		 5392 rc = mwl8k_conf_tx(hw, i, &priv->wmm_params[i]);
5393 if (rc)
5394 goto fail;
5395 }
5396
5397 return rc;
5398
5399fail:
5400 printk(KERN_WARNING "mwl8k: Failed to reload firmware image.\n");
5401 return rc;
5402}
5403
5404static int mwl8k_firmware_load_success(struct mwl8k_priv *priv)
5405{
5406 struct ieee80211_hw *hw = priv->hw;
5407 int i, rc;
5408
99020471
BC		 5409 rc = mwl8k_load_firmware(hw);
5410 mwl8k_release_firmware(priv);
5411 if (rc) {
5412 wiphy_err(hw->wiphy, "Cannot start firmware\n");
5413 return rc;
5414 }
5415
3cc7772c
BC		 5416 /*
5417 * Extra headroom is the size of the required DMA header
5418 * minus the size of the smallest 802.11 frame (CTS frame).
5419 */
5420 hw->extra_tx_headroom =
5421 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
5422
5423 hw->channel_change_time = 10;
5424
e600707b 5425 hw->queues = MWL8K_TX_WMM_QUEUES;
3cc7772c
BC		 5426
5427 /* Set rssi values to dBm */
0bf22c37 5428 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_HAS_RATE_CONTROL;
3cc7772c
BC		 5429 hw->vif_data_size = sizeof(struct mwl8k_vif);
5430 hw->sta_data_size = sizeof(struct mwl8k_sta);
5431
5432 priv->macids_used = 0;
5433 INIT_LIST_HEAD(&priv->vif_list);
5434
5435 /* Set default radio state and preamble */
5436 priv->radio_on = 0;
5437 priv->radio_short_preamble = 0;
5438
5439 /* Finalize join worker */
5440 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3aefc37e
NS		 5441 /* Handle watchdog ba events */
5442 INIT_WORK(&priv->watchdog_ba_handle, mwl8k_watchdog_ba_events);
3cc7772c
BC		 5443
5444 /* TX reclaim and RX tasklets. */
5445 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
5446 tasklet_disable(&priv->poll_tx_task);
5447 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
5448 tasklet_disable(&priv->poll_rx_task);
5449
5450 /* Power management cookie */
5451 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
5452 if (priv->cookie == NULL)
5453 return -ENOMEM;
5454
5455 mutex_init(&priv->fw_mutex);
5456 priv->fw_mutex_owner = NULL;
5457 priv->fw_mutex_depth = 0;
5458 priv->hostcmd_wait = NULL;
5459
5460 spin_lock_init(&priv->tx_lock);
5461
ac109fd0
BC		 5462 spin_lock_init(&priv->stream_lock);
5463
3cc7772c
BC		 5464 priv->tx_wait = NULL;
5465
5466 rc = mwl8k_probe_hw(hw);
5467 if (rc)
5468 goto err_free_cookie;
5469
5470 hw->wiphy->interface_modes = 0;
5471 if (priv->ap_macids_supported || priv->device_info->fw_image_ap)
5472 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
5473 if (priv->sta_macids_supported || priv->device_info->fw_image_sta)
5474 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
5475
5476 rc = ieee80211_register_hw(hw);
5477 if (rc) {
5478 wiphy_err(hw->wiphy, "Cannot register device\n");
5479 goto err_unprobe_hw;
5480 }
5481
5482 return 0;
5483
5484err_unprobe_hw:
e600707b 5485 for (i = 0; i < mwl8k_tx_queues(priv); i++)
3cc7772c
BC		 5486 mwl8k_txq_deinit(hw, i);
5487 mwl8k_rxq_deinit(hw, 0);
5488
be695fc4 5489err_free_cookie:
a66098da
LB		 5490 if (priv->cookie != NULL)
5491 pci_free_consistent(priv->pdev, 4,
5492 priv->cookie, priv->cookie_dma);
5493
3cc7772c
BC		 5494 return rc;
5495}
5496static int __devinit mwl8k_probe(struct pci_dev *pdev,
5497 const struct pci_device_id *id)
5498{
5499 static int printed_version;
5500 struct ieee80211_hw *hw;
5501 struct mwl8k_priv *priv;
0863ade8 5502 struct mwl8k_device_info *di;
3cc7772c
BC		 5503 int rc;
5504
5505 if (!printed_version) {
5506 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
5507 printed_version = 1;
5508 }
5509
5510
5511 rc = pci_enable_device(pdev);
5512 if (rc) {
5513 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
5514 MWL8K_NAME);
5515 return rc;
5516 }
5517
5518 rc = pci_request_regions(pdev, MWL8K_NAME);
5519 if (rc) {
5520 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
5521 MWL8K_NAME);
5522 goto err_disable_device;
5523 }
5524
5525 pci_set_master(pdev);
5526
5527
5528 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
5529 if (hw == NULL) {
5530 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
5531 rc = -ENOMEM;
5532 goto err_free_reg;
5533 }
5534
5535 SET_IEEE80211_DEV(hw, &pdev->dev);
5536 pci_set_drvdata(pdev, hw);
5537
5538 priv = hw->priv;
5539 priv->hw = hw;
5540 priv->pdev = pdev;
5541 priv->device_info = &mwl8k_info_tbl[id->driver_data];
5542
5543
5544 priv->sram = pci_iomap(pdev, 0, 0x10000);
5545 if (priv->sram == NULL) {
5546 wiphy_err(hw->wiphy, "Cannot map device SRAM\n");
5547 goto err_iounmap;
5548 }
5549
5550 /*
5551 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
5552 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
5553 */
5554 priv->regs = pci_iomap(pdev, 1, 0x10000);
5555 if (priv->regs == NULL) {
5556 priv->regs = pci_iomap(pdev, 2, 0x10000);
5557 if (priv->regs == NULL) {
5558 wiphy_err(hw->wiphy, "Cannot map device registers\n");
5559 goto err_iounmap;
5560 }
5561 }
5562
0863ade8 5563 /*
99020471
BC		 5564 * Choose the initial fw image depending on user input. If a second
5565 * image is available, make it the alternative image that will be
5566 * loaded if the first one fails.
0863ade8 5567 */
99020471 5568 init_completion(&priv->firmware_loading_complete);
0863ade8 5569 di = priv->device_info;
99020471
BC		 5570 if (ap_mode_default && di->fw_image_ap) {
5571 priv->fw_pref = di->fw_image_ap;
5572 priv->fw_alt = di->fw_image_sta;
5573 } else if (!ap_mode_default && di->fw_image_sta) {
5574 priv->fw_pref = di->fw_image_sta;
5575 priv->fw_alt = di->fw_image_ap;
5576 } else if (ap_mode_default && !di->fw_image_ap && di->fw_image_sta) {
0863ade8 5577 printk(KERN_WARNING "AP fw is unavailable. Using STA fw.");
99020471 5578 priv->fw_pref = di->fw_image_sta;
0863ade8
BC		 5579 } else if (!ap_mode_default && !di->fw_image_sta && di->fw_image_ap) {
5580 printk(KERN_WARNING "STA fw is unavailable. Using AP fw.");
99020471
BC		 5581 priv->fw_pref = di->fw_image_ap;
5582 }
5583 rc = mwl8k_init_firmware(hw, priv->fw_pref, true);
3cc7772c
BC		 5584 if (rc)
5585 goto err_stop_firmware;
99020471 5586 return rc;
3cc7772c 5587
be695fc4
LB		 5588err_stop_firmware:
5589 mwl8k_hw_reset(priv);
be695fc4
LB		 5590
5591err_iounmap:
a66098da
LB		 5592 if (priv->regs != NULL)
5593 pci_iounmap(pdev, priv->regs);
5594
5b9482dd
LB		 5595 if (priv->sram != NULL)
5596 pci_iounmap(pdev, priv->sram);
5597
a66098da
LB		 5598 pci_set_drvdata(pdev, NULL);
5599 ieee80211_free_hw(hw);
5600
5601err_free_reg:
5602 pci_release_regions(pdev);
3db95e50
LB		 5603
5604err_disable_device:
a66098da
LB		 5605 pci_disable_device(pdev);
5606
5607 return rc;
5608}
5609
230f7af0 5610static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 5611{
5612 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
5613}
5614
230f7af0 5615static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 5616{
5617 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
5618 struct mwl8k_priv *priv;
5619 int i;
5620
5621 if (hw == NULL)
5622 return;
5623 priv = hw->priv;
5624
99020471
BC		 5625 wait_for_completion(&priv->firmware_loading_complete);
5626
5627 if (priv->fw_state == FW_STATE_ERROR) {
5628 mwl8k_hw_reset(priv);
5629 goto unmap;
5630 }
5631
a66098da
LB		 5632 ieee80211_stop_queues(hw);
5633
60aa569f
LB		 5634 ieee80211_unregister_hw(hw);
5635
67e2eb27 5636 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 5637 tasklet_kill(&priv->poll_tx_task);
67e2eb27 5638 tasklet_kill(&priv->poll_rx_task);
a66098da 5639
a66098da
LB		 5640 /* Stop hardware */
5641 mwl8k_hw_reset(priv);
5642
5643 /* Return all skbs to mac80211 */
e600707b 5644 for (i = 0; i < mwl8k_tx_queues(priv); i++)
efb7c49a 5645 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 5646
e600707b 5647 for (i = 0; i < mwl8k_tx_queues(priv); i++)
a66098da
LB		 5648 mwl8k_txq_deinit(hw, i);
5649
5650 mwl8k_rxq_deinit(hw, 0);
5651
c2c357ce 5652 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da 5653
99020471 5654unmap:
a66098da 5655 pci_iounmap(pdev, priv->regs);
5b9482dd 5656 pci_iounmap(pdev, priv->sram);
a66098da
LB		 5657 pci_set_drvdata(pdev, NULL);
5658 ieee80211_free_hw(hw);
5659 pci_release_regions(pdev);
5660 pci_disable_device(pdev);
5661}
5662
5663static struct pci_driver mwl8k_driver = {
5664 .name = MWL8K_NAME,
45a390dd 5665 .id_table = mwl8k_pci_id_table,
a66098da
LB		 5666 .probe = mwl8k_probe,
5667 .remove = __devexit_p(mwl8k_remove),
5668 .shutdown = __devexit_p(mwl8k_shutdown),
5669};
5670
5671static int __init mwl8k_init(void)
5672{
5673 return pci_register_driver(&mwl8k_driver);
5674}
5675
5676static void __exit mwl8k_exit(void)
5677{
5678 pci_unregister_driver(&mwl8k_driver);
5679}
5680
5681module_init(mwl8k_init);
5682module_exit(mwl8k_exit);
c2c357ce
LB		 5683
5684MODULE_DESCRIPTION(MWL8K_DESC);
5685MODULE_VERSION(MWL8K_VERSION);
5686MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
5687MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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