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mwl8k: increase firmware loading timeouts
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
a145d575 29#define MWL8K_VERSION "0.10"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d
LB		 87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
54bc3a0d
LB		 89};
90
45a390dd 91struct mwl8k_device_info {
a74b295e
LB		 92 char *part_name;
93 char *helper_image;
94 char *fw_image;
54bc3a0d 95 struct rxd_ops *rxd_ops;
547810e3 96 u16 modes;
45a390dd
LB		 97};
98
a66098da 99struct mwl8k_rx_queue {
45eb400d 100 int rxd_count;
a66098da
LB		 101
102 /* hw receives here */
45eb400d 103 int head;
a66098da
LB		 104
105 /* refill descs here */
45eb400d 106 int tail;
a66098da 107
54bc3a0d 108 void *rxd;
45eb400d 109 dma_addr_t rxd_dma;
788838eb
LB		 110 struct {
111 struct sk_buff *skb;
112 DECLARE_PCI_UNMAP_ADDR(dma)
113 } *buf;
a66098da
LB		 114};
115
a66098da
LB		 116struct mwl8k_tx_queue {
117 /* hw transmits here */
45eb400d 118 int head;
a66098da
LB		 119
120 /* sw appends here */
45eb400d 121 int tail;
a66098da 122
45eb400d
LB		 123 struct ieee80211_tx_queue_stats stats;
124 struct mwl8k_tx_desc *txd;
125 dma_addr_t txd_dma;
126 struct sk_buff **skb;
a66098da
LB		 127};
128
129/* Pointers to the firmware data and meta information about it. */
130struct mwl8k_firmware {
a66098da
LB		 131 /* Boot helper code */
132 struct firmware *helper;
a74b295e
LB		 133
134 /* Microcode */
135 struct firmware *ucode;
a66098da
LB		 136};
137
138struct mwl8k_priv {
5b9482dd 139 void __iomem *sram;
a66098da
LB		 140 void __iomem *regs;
141 struct ieee80211_hw *hw;
142
143 struct pci_dev *pdev;
a66098da 144
45a390dd 145 struct mwl8k_device_info *device_info;
eae74e65 146 bool ap_fw;
54bc3a0d 147 struct rxd_ops *rxd_ops;
45a390dd 148
a66098da
LB		 149 /* firmware files and meta data */
150 struct mwl8k_firmware fw;
a66098da 151
618952a7
LB		 152 /* firmware access */
153 struct mutex fw_mutex;
154 struct task_struct *fw_mutex_owner;
155 int fw_mutex_depth;
618952a7
LB		 156 struct completion *hostcmd_wait;
157
a66098da
LB		 158 /* lock held over TX and TX reap */
159 spinlock_t tx_lock;
a66098da 160
88de754a
LB		 161 /* TX quiesce completion, protected by fw_mutex and tx_lock */
162 struct completion *tx_wait;
163
a66098da 164 struct ieee80211_vif *vif;
a66098da
LB		 165
166 struct ieee80211_channel *current_channel;
167
168 /* power management status cookie from firmware */
169 u32 *cookie;
170 dma_addr_t cookie_dma;
171
172 u16 num_mcaddrs;
a66098da 173 u8 hw_rev;
2aa7b01f 174 u32 fw_rev;
a66098da
LB		 175
176 /*
177 * Running count of TX packets in flight, to avoid
178 * iterating over the transmit rings each time.
179 */
180 int pending_tx_pkts;
181
182 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
183 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
184
185 /* PHY parameters */
186 struct ieee80211_supported_band band;
187 struct ieee80211_channel channels[14];
140eb5e2 188 struct ieee80211_rate rates[14];
a66098da 189
c46563b7 190 bool radio_on;
68ce3884 191 bool radio_short_preamble;
a43c49a8 192 bool sniffer_enabled;
0439b1f5 193 bool wmm_enabled;
a66098da 194
a66098da
LB		 195 /* XXX need to convert this to handle multiple interfaces */
196 bool capture_beacon;
d89173f2 197 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 198 struct sk_buff *beacon_skb;
199
200 /*
201 * This FJ worker has to be global as it is scheduled from the
202 * RX handler. At this point we don't know which interface it
203 * belongs to until the list of bssids waiting to complete join
204 * is checked.
205 */
206 struct work_struct finalize_join_worker;
207
208 /* Tasklet to reclaim TX descriptors and buffers after tx */
209 struct tasklet_struct tx_reclaim_task;
a66098da
LB		 210};
211
212/* Per interface specific private data */
213struct mwl8k_vif {
a66098da
LB		 214 /* backpointer to parent config block */
215 struct mwl8k_priv *priv;
216
217 /* BSS config of AP or IBSS from mac80211*/
218 struct ieee80211_bss_conf bss_info;
219
220 /* BSSID of AP or IBSS */
d89173f2
LB		 221 u8 bssid[ETH_ALEN];
222 u8 mac_addr[ETH_ALEN];
a66098da 223
a66098da
LB		 224 /* Index into station database.Returned by update_sta_db call */
225 u8 peer_id;
226
227 /* Non AMPDU sequence number assigned by driver */
228 u16 seqno;
a66098da
LB		 229};
230
a94cc97e 231#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 232
233static const struct ieee80211_channel mwl8k_channels[] = {
234 { .center_freq = 2412, .hw_value = 1, },
235 { .center_freq = 2417, .hw_value = 2, },
236 { .center_freq = 2422, .hw_value = 3, },
237 { .center_freq = 2427, .hw_value = 4, },
238 { .center_freq = 2432, .hw_value = 5, },
239 { .center_freq = 2437, .hw_value = 6, },
240 { .center_freq = 2442, .hw_value = 7, },
241 { .center_freq = 2447, .hw_value = 8, },
242 { .center_freq = 2452, .hw_value = 9, },
243 { .center_freq = 2457, .hw_value = 10, },
244 { .center_freq = 2462, .hw_value = 11, },
245};
246
247static const struct ieee80211_rate mwl8k_rates[] = {
248 { .bitrate = 10, .hw_value = 2, },
249 { .bitrate = 20, .hw_value = 4, },
250 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 251 { .bitrate = 110, .hw_value = 22, },
252 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 253 { .bitrate = 60, .hw_value = 12, },
254 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 255 { .bitrate = 120, .hw_value = 24, },
256 { .bitrate = 180, .hw_value = 36, },
257 { .bitrate = 240, .hw_value = 48, },
258 { .bitrate = 360, .hw_value = 72, },
259 { .bitrate = 480, .hw_value = 96, },
260 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 261 { .bitrate = 720, .hw_value = 144, },
262};
263
264static const u8 mwl8k_rateids[12] = {
265 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
a66098da
LB		 266};
267
a66098da
LB		 268/* Set or get info from Firmware */
269#define MWL8K_CMD_SET 0x0001
270#define MWL8K_CMD_GET 0x0000
271
272/* Firmware command codes */
273#define MWL8K_CMD_CODE_DNLD 0x0001
274#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 275#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 276#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
277#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 278#define MWL8K_CMD_RADIO_CONTROL 0x001c
279#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 280#define MWL8K_CMD_RF_ANTENNA 0x0020
a66098da
LB		 281#define MWL8K_CMD_SET_PRE_SCAN 0x0107
282#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 283#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
284#define MWL8K_CMD_SET_AID 0x010d
285#define MWL8K_CMD_SET_RATE 0x0110
286#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
287#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 288#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 289#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
290#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 291#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 292#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 293#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 294#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 295#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 296#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 297
298static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
299{
300#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
301 snprintf(buf, bufsize, "%s", #x);\
302 return buf;\
303 } while (0)
ce9e2e1b 304 switch (cmd & ~0x8000) {
a66098da
LB		 305 MWL8K_CMDNAME(CODE_DNLD);
306 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 307 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 308 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
309 MWL8K_CMDNAME(GET_STAT);
310 MWL8K_CMDNAME(RADIO_CONTROL);
311 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 312 MWL8K_CMDNAME(RF_ANTENNA);
a66098da
LB		 313 MWL8K_CMDNAME(SET_PRE_SCAN);
314 MWL8K_CMDNAME(SET_POST_SCAN);
315 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 316 MWL8K_CMDNAME(SET_AID);
317 MWL8K_CMDNAME(SET_RATE);
318 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
319 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 320 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 321 MWL8K_CMDNAME(SET_EDCA_PARAMS);
322 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 323 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 324 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 325 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 326 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 327 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 328 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 329 default:
330 snprintf(buf, bufsize, "0x%x", cmd);
331 }
332#undef MWL8K_CMDNAME
333
334 return buf;
335}
336
337/* Hardware and firmware reset */
338static void mwl8k_hw_reset(struct mwl8k_priv *priv)
339{
340 iowrite32(MWL8K_H2A_INT_RESET,
341 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
342 iowrite32(MWL8K_H2A_INT_RESET,
343 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
344 msleep(20);
345}
346
347/* Release fw image */
348static void mwl8k_release_fw(struct firmware **fw)
349{
350 if (*fw == NULL)
351 return;
352 release_firmware(*fw);
353 *fw = NULL;
354}
355
356static void mwl8k_release_firmware(struct mwl8k_priv *priv)
357{
358 mwl8k_release_fw(&priv->fw.ucode);
359 mwl8k_release_fw(&priv->fw.helper);
360}
361
362/* Request fw image */
363static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 364 const char *fname, struct firmware **fw)
a66098da
LB		 365{
366 /* release current image */
367 if (*fw != NULL)
368 mwl8k_release_fw(fw);
369
370 return request_firmware((const struct firmware **)fw,
c2c357ce 371 fname, &priv->pdev->dev);
a66098da
LB		 372}
373
45a390dd 374static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 375{
a74b295e 376 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 377 int rc;
378
a74b295e
LB		 379 if (di->helper_image != NULL) {
380 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
381 if (rc) {
382 printk(KERN_ERR "%s: Error requesting helper "
383 "firmware file %s\n", pci_name(priv->pdev),
384 di->helper_image);
385 return rc;
386 }
a66098da
LB		 387 }
388
a74b295e 389 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
a66098da 390 if (rc) {
c2c357ce 391 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 392 pci_name(priv->pdev), di->fw_image);
a66098da
LB		 393 mwl8k_release_fw(&priv->fw.helper);
394 return rc;
395 }
396
397 return 0;
398}
399
7e75b942
BH		 400MODULE_FIRMWARE("mwl8k/helper_8687.fw");
401MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
402
a66098da
LB		 403struct mwl8k_cmd_pkt {
404 __le16 code;
405 __le16 length;
406 __le16 seq_num;
407 __le16 result;
408 char payload[0];
409} __attribute__((packed));
410
411/*
412 * Firmware loading.
413 */
414static int
415mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
416{
417 void __iomem *regs = priv->regs;
418 dma_addr_t dma_addr;
a66098da
LB		 419 int loops;
420
421 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
422 if (pci_dma_mapping_error(priv->pdev, dma_addr))
423 return -ENOMEM;
424
425 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
426 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
427 iowrite32(MWL8K_H2A_INT_DOORBELL,
428 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
429 iowrite32(MWL8K_H2A_INT_DUMMY,
430 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
431
a66098da
LB		 432 loops = 1000;
433 do {
434 u32 int_code;
435
436 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
437 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
438 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 439 break;
440 }
441
3d76e82c 442 cond_resched();
a66098da
LB		 443 udelay(1);
444 } while (--loops);
445
446 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
447
d4b70570 448 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 449}
450
451static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
452 const u8 *data, size_t length)
453{
454 struct mwl8k_cmd_pkt *cmd;
455 int done;
456 int rc = 0;
457
458 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
459 if (cmd == NULL)
460 return -ENOMEM;
461
462 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
463 cmd->seq_num = 0;
464 cmd->result = 0;
465
466 done = 0;
467 while (length) {
468 int block_size = length > 256 ? 256 : length;
469
470 memcpy(cmd->payload, data + done, block_size);
471 cmd->length = cpu_to_le16(block_size);
472
473 rc = mwl8k_send_fw_load_cmd(priv, cmd,
474 sizeof(*cmd) + block_size);
475 if (rc)
476 break;
477
478 done += block_size;
479 length -= block_size;
480 }
481
482 if (!rc) {
483 cmd->length = 0;
484 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
485 }
486
487 kfree(cmd);
488
489 return rc;
490}
491
492static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
493 const u8 *data, size_t length)
494{
495 unsigned char *buffer;
496 int may_continue, rc = 0;
497 u32 done, prev_block_size;
498
499 buffer = kmalloc(1024, GFP_KERNEL);
500 if (buffer == NULL)
501 return -ENOMEM;
502
503 done = 0;
504 prev_block_size = 0;
505 may_continue = 1000;
506 while (may_continue > 0) {
507 u32 block_size;
508
509 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
510 if (block_size & 1) {
511 block_size &= ~1;
512 may_continue--;
513 } else {
514 done += prev_block_size;
515 length -= prev_block_size;
516 }
517
518 if (block_size > 1024 || block_size > length) {
519 rc = -EOVERFLOW;
520 break;
521 }
522
523 if (length == 0) {
524 rc = 0;
525 break;
526 }
527
528 if (block_size == 0) {
529 rc = -EPROTO;
530 may_continue--;
531 udelay(1);
532 continue;
533 }
534
535 prev_block_size = block_size;
536 memcpy(buffer, data + done, block_size);
537
538 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
539 if (rc)
540 break;
541 }
542
543 if (!rc && length != 0)
544 rc = -EREMOTEIO;
545
546 kfree(buffer);
547
548 return rc;
549}
550
c2c357ce 551static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 552{
c2c357ce
LB		 553 struct mwl8k_priv *priv = hw->priv;
554 struct firmware *fw = priv->fw.ucode;
eae74e65 555 struct mwl8k_device_info *di = priv->device_info;
c2c357ce
LB		 556 int rc;
557 int loops;
558
559 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
560 struct firmware *helper = priv->fw.helper;
a66098da 561
c2c357ce
LB		 562 if (helper == NULL) {
563 printk(KERN_ERR "%s: helper image needed but none "
564 "given\n", pci_name(priv->pdev));
565 return -EINVAL;
566 }
a66098da 567
c2c357ce 568 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 569 if (rc) {
570 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 571 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 572 return rc;
573 }
89b872e2 574 msleep(5);
a66098da 575
c2c357ce 576 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 577 } else {
c2c357ce 578 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 579 }
580
581 if (rc) {
c2c357ce
LB		 582 printk(KERN_ERR "%s: unable to load firmware image\n",
583 pci_name(priv->pdev));
a66098da
LB		 584 return rc;
585 }
586
eae74e65
LB		 587 if (di->modes & BIT(NL80211_IFTYPE_AP))
588 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
589 else
590 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 591
89b872e2 592 loops = 500000;
a66098da 593 do {
eae74e65
LB		 594 u32 ready_code;
595
596 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
597 if (ready_code == MWL8K_FWAP_READY) {
598 priv->ap_fw = 1;
599 break;
600 } else if (ready_code == MWL8K_FWSTA_READY) {
601 priv->ap_fw = 0;
a66098da 602 break;
eae74e65
LB		 603 }
604
605 cond_resched();
a66098da
LB		 606 udelay(1);
607 } while (--loops);
608
609 return loops ? 0 : -ETIMEDOUT;
610}
611
612
613/*
614 * Defines shared between transmission and reception.
615 */
616/* HT control fields for firmware */
617struct ewc_ht_info {
618 __le16 control1;
619 __le16 control2;
620 __le16 control3;
621} __attribute__((packed));
622
623/* Firmware Station database operations */
624#define MWL8K_STA_DB_ADD_ENTRY 0
625#define MWL8K_STA_DB_MODIFY_ENTRY 1
626#define MWL8K_STA_DB_DEL_ENTRY 2
627#define MWL8K_STA_DB_FLUSH 3
628
629/* Peer Entry flags - used to define the type of the peer node */
630#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da 631
a66098da
LB		 632struct peer_capability_info {
633 /* Peer type - AP vs. STA. */
634 __u8 peer_type;
635
636 /* Basic 802.11 capabilities from assoc resp. */
637 __le16 basic_caps;
638
639 /* Set if peer supports 802.11n high throughput (HT). */
640 __u8 ht_support;
641
642 /* Valid if HT is supported. */
643 __le16 ht_caps;
644 __u8 extended_ht_caps;
645 struct ewc_ht_info ewc_info;
646
647 /* Legacy rate table. Intersection of our rates and peer rates. */
140eb5e2 648 __u8 legacy_rates[12];
a66098da
LB		 649
650 /* HT rate table. Intersection of our rates and peer rates. */
0b5351a8 651 __u8 ht_rates[16];
c23b5a69 652 __u8 pad[16];
a66098da
LB		 653
654 /* If set, interoperability mode, no proprietary extensions. */
655 __u8 interop;
656 __u8 pad2;
657 __u8 station_id;
658 __le16 amsdu_enabled;
659} __attribute__((packed));
660
661/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 662static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
663{
664 u16 val_mask = 1 << 4;
665
666 /* End of Service Period Bit 4 */
667 return qos | val_mask;
668}
669
670static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
671{
672 u16 val_mask = 0x3;
673 u8 shift = 5;
674 u16 qos_mask = ~(val_mask << shift);
675
676 /* Ack Policy Bit 5-6 */
677 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
678}
679
680static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
681{
682 u16 val_mask = 1 << 7;
683
684 /* AMSDU present Bit 7 */
685 return qos | val_mask;
686}
687
688static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
689{
690 u16 val_mask = 0xff;
691 u8 shift = 8;
692 u16 qos_mask = ~(val_mask << shift);
693
694 /* Queue Length Bits 8-15 */
695 return (qos & qos_mask) | ((len & val_mask) << shift);
696}
697
698/* DMA header used by firmware and hardware. */
699struct mwl8k_dma_data {
700 __le16 fwlen;
701 struct ieee80211_hdr wh;
20f09c3d 702 char data[0];
a66098da
LB		 703} __attribute__((packed));
704
705/* Routines to add/remove DMA header from skb. */
20f09c3d 706static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 707{
20f09c3d
LB		 708 struct mwl8k_dma_data *tr;
709 int hdrlen;
710
711 tr = (struct mwl8k_dma_data *)skb->data;
712 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
713
714 if (hdrlen != sizeof(tr->wh)) {
715 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
716 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
717 *((__le16 *)(tr->data - 2)) = qos;
718 } else {
719 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
720 }
a66098da 721 }
20f09c3d
LB		 722
723 if (hdrlen != sizeof(*tr))
724 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 725}
726
76266b2a 727static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 728{
729 struct ieee80211_hdr *wh;
ca009301 730 int hdrlen;
a66098da
LB		 731 struct mwl8k_dma_data *tr;
732
ca009301
LB		 733 /*
734 * Add a firmware DMA header; the firmware requires that we
735 * present a 2-byte payload length followed by a 4-address
736 * header (without QoS field), followed (optionally) by any
737 * WEP/ExtIV header (but only filled in for CCMP).
738 */
a66098da 739 wh = (struct ieee80211_hdr *)skb->data;
ca009301 740
a66098da 741 hdrlen = ieee80211_hdrlen(wh->frame_control);
ca009301
LB		 742 if (hdrlen != sizeof(*tr))
743 skb_push(skb, sizeof(*tr) - hdrlen);
a66098da 744
ca009301
LB		 745 if (ieee80211_is_data_qos(wh->frame_control))
746 hdrlen -= 2;
a66098da
LB		 747
748 tr = (struct mwl8k_dma_data *)skb->data;
749 if (wh != &tr->wh)
750 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 751 if (hdrlen != sizeof(tr->wh))
752 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 753
754 /*
755 * Firmware length is the length of the fully formed "802.11
756 * payload". That is, everything except for the 802.11 header.
757 * This includes all crypto material including the MIC.
758 */
ca009301 759 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
a66098da
LB		 760}
761
762
763/*
6f6d1e9a
LB		 764 * Packet reception for 88w8366.
765 */
766struct mwl8k_rxd_8366 {
767 __le16 pkt_len;
768 __u8 sq2;
769 __u8 rate;
770 __le32 pkt_phys_addr;
771 __le32 next_rxd_phys_addr;
772 __le16 qos_control;
773 __le16 htsig2;
774 __le32 hw_rssi_info;
775 __le32 hw_noise_floor_info;
776 __u8 noise_floor;
777 __u8 pad0[3];
778 __u8 rssi;
779 __u8 rx_status;
780 __u8 channel;
781 __u8 rx_ctrl;
782} __attribute__((packed));
783
8e9f33f0
LB		 784#define MWL8K_8366_RATE_INFO_MCS_FORMAT 0x80
785#define MWL8K_8366_RATE_INFO_40MHZ 0x40
786#define MWL8K_8366_RATE_INFO_RATEID(x) ((x) & 0x3f)
787
6f6d1e9a
LB		 788#define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
789
790static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
791{
792 struct mwl8k_rxd_8366 *rxd = _rxd;
793
794 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
795 rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
796}
797
798static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
799{
800 struct mwl8k_rxd_8366 *rxd = _rxd;
801
802 rxd->pkt_len = cpu_to_le16(len);
803 rxd->pkt_phys_addr = cpu_to_le32(addr);
804 wmb();
805 rxd->rx_ctrl = 0;
806}
807
808static int
20f09c3d
LB		 809mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status,
810 __le16 *qos)
6f6d1e9a
LB		 811{
812 struct mwl8k_rxd_8366 *rxd = _rxd;
813
814 if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
815 return -1;
816 rmb();
817
818 memset(status, 0, sizeof(*status));
819
820 status->signal = -rxd->rssi;
821 status->noise = -rxd->noise_floor;
822
8e9f33f0 823 if (rxd->rate & MWL8K_8366_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 824 status->flag |= RX_FLAG_HT;
8e9f33f0
LB		 825 if (rxd->rate & MWL8K_8366_RATE_INFO_40MHZ)
826 status->flag |= RX_FLAG_40MHZ;
827 status->rate_idx = MWL8K_8366_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 828 } else {
829 int i;
830
831 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
832 if (mwl8k_rates[i].hw_value == rxd->rate) {
833 status->rate_idx = i;
834 break;
835 }
836 }
837 }
838
839 status->band = IEEE80211_BAND_2GHZ;
840 status->freq = ieee80211_channel_to_frequency(rxd->channel);
841
20f09c3d
LB		 842 *qos = rxd->qos_control;
843
6f6d1e9a
LB		 844 return le16_to_cpu(rxd->pkt_len);
845}
846
847static struct rxd_ops rxd_8366_ops = {
848 .rxd_size = sizeof(struct mwl8k_rxd_8366),
849 .rxd_init = mwl8k_rxd_8366_init,
850 .rxd_refill = mwl8k_rxd_8366_refill,
851 .rxd_process = mwl8k_rxd_8366_process,
852};
853
854/*
855 * Packet reception for 88w8687.
a66098da 856 */
54bc3a0d 857struct mwl8k_rxd_8687 {
a66098da
LB		 858 __le16 pkt_len;
859 __u8 link_quality;
860 __u8 noise_level;
861 __le32 pkt_phys_addr;
45eb400d 862 __le32 next_rxd_phys_addr;
a66098da
LB		 863 __le16 qos_control;
864 __le16 rate_info;
865 __le32 pad0[4];
866 __u8 rssi;
867 __u8 channel;
868 __le16 pad1;
869 __u8 rx_ctrl;
870 __u8 rx_status;
871 __u8 pad2[2];
872} __attribute__((packed));
873
54bc3a0d
LB		 874#define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
875#define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
876#define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
877#define MWL8K_8687_RATE_INFO_40MHZ 0x0004
878#define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
879#define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
880
881#define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
882
883static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
884{
885 struct mwl8k_rxd_8687 *rxd = _rxd;
886
887 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
888 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
889}
890
891static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
892{
893 struct mwl8k_rxd_8687 *rxd = _rxd;
894
895 rxd->pkt_len = cpu_to_le16(len);
896 rxd->pkt_phys_addr = cpu_to_le32(addr);
897 wmb();
898 rxd->rx_ctrl = 0;
899}
900
901static int
20f09c3d
LB		 902mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status,
903 __le16 *qos)
54bc3a0d
LB		 904{
905 struct mwl8k_rxd_8687 *rxd = _rxd;
906 u16 rate_info;
907
908 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
909 return -1;
910 rmb();
911
912 rate_info = le16_to_cpu(rxd->rate_info);
913
914 memset(status, 0, sizeof(*status));
915
916 status->signal = -rxd->rssi;
917 status->noise = -rxd->noise_level;
918 status->qual = rxd->link_quality;
919 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
920 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
921
922 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
923 status->flag |= RX_FLAG_SHORTPRE;
924 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
925 status->flag |= RX_FLAG_40MHZ;
926 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
927 status->flag |= RX_FLAG_SHORT_GI;
928 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
929 status->flag |= RX_FLAG_HT;
930
931 status->band = IEEE80211_BAND_2GHZ;
932 status->freq = ieee80211_channel_to_frequency(rxd->channel);
933
20f09c3d
LB		 934 *qos = rxd->qos_control;
935
54bc3a0d
LB		 936 return le16_to_cpu(rxd->pkt_len);
937}
938
939static struct rxd_ops rxd_8687_ops = {
940 .rxd_size = sizeof(struct mwl8k_rxd_8687),
941 .rxd_init = mwl8k_rxd_8687_init,
942 .rxd_refill = mwl8k_rxd_8687_refill,
943 .rxd_process = mwl8k_rxd_8687_process,
944};
945
946
a66098da
LB		 947#define MWL8K_RX_DESCS 256
948#define MWL8K_RX_MAXSZ 3800
949
950static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
951{
952 struct mwl8k_priv *priv = hw->priv;
953 struct mwl8k_rx_queue *rxq = priv->rxq + index;
954 int size;
955 int i;
956
45eb400d
LB		 957 rxq->rxd_count = 0;
958 rxq->head = 0;
959 rxq->tail = 0;
a66098da 960
54bc3a0d 961 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 962
45eb400d
LB		 963 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
964 if (rxq->rxd == NULL) {
a66098da 965 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 966 wiphy_name(hw->wiphy));
a66098da
LB		 967 return -ENOMEM;
968 }
45eb400d 969 memset(rxq->rxd, 0, size);
a66098da 970
788838eb
LB		 971 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
972 if (rxq->buf == NULL) {
a66098da 973 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 974 wiphy_name(hw->wiphy));
45eb400d 975 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 976 return -ENOMEM;
977 }
788838eb 978 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 979
980 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 981 int desc_size;
982 void *rxd;
a66098da 983 int nexti;
54bc3a0d
LB		 984 dma_addr_t next_dma_addr;
985
986 desc_size = priv->rxd_ops->rxd_size;
987 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 988
54bc3a0d
LB		 989 nexti = i + 1;
990 if (nexti == MWL8K_RX_DESCS)
991 nexti = 0;
992 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 993
54bc3a0d 994 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 995 }
996
997 return 0;
998}
999
1000static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1001{
1002 struct mwl8k_priv *priv = hw->priv;
1003 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1004 int refilled;
1005
1006 refilled = 0;
45eb400d 1007 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 1008 struct sk_buff *skb;
788838eb 1009 dma_addr_t addr;
a66098da 1010 int rx;
54bc3a0d 1011 void *rxd;
a66098da
LB		 1012
1013 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1014 if (skb == NULL)
1015 break;
1016
788838eb
LB		 1017 addr = pci_map_single(priv->pdev, skb->data,
1018 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1019
54bc3a0d
LB		 1020 rxq->rxd_count++;
1021 rx = rxq->tail++;
1022 if (rxq->tail == MWL8K_RX_DESCS)
1023 rxq->tail = 0;
788838eb
LB		 1024 rxq->buf[rx].skb = skb;
1025 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 1026
1027 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1028 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 1029
1030 refilled++;
1031 }
1032
1033 return refilled;
1034}
1035
1036/* Must be called only when the card's reception is completely halted */
1037static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1038{
1039 struct mwl8k_priv *priv = hw->priv;
1040 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1041 int i;
1042
1043 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 1044 if (rxq->buf[i].skb != NULL) {
1045 pci_unmap_single(priv->pdev,
1046 pci_unmap_addr(&rxq->buf[i], dma),
1047 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1048 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
1049
1050 kfree_skb(rxq->buf[i].skb);
1051 rxq->buf[i].skb = NULL;
a66098da
LB		 1052 }
1053 }
1054
788838eb
LB		 1055 kfree(rxq->buf);
1056 rxq->buf = NULL;
a66098da
LB		 1057
1058 pci_free_consistent(priv->pdev,
54bc3a0d 1059 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1060 rxq->rxd, rxq->rxd_dma);
1061 rxq->rxd = NULL;
a66098da
LB		 1062}
1063
1064
1065/*
1066 * Scan a list of BSSIDs to process for finalize join.
1067 * Allows for extension to process multiple BSSIDs.
1068 */
1069static inline int
1070mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1071{
1072 return priv->capture_beacon &&
1073 ieee80211_is_beacon(wh->frame_control) &&
1074 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1075}
1076
3779752d
LB		 1077static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1078 struct sk_buff *skb)
a66098da 1079{
3779752d
LB		 1080 struct mwl8k_priv *priv = hw->priv;
1081
a66098da 1082 priv->capture_beacon = false;
d89173f2 1083 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1084
1085 /*
1086 * Use GFP_ATOMIC as rxq_process is called from
1087 * the primary interrupt handler, memory allocation call
1088 * must not sleep.
1089 */
1090 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1091 if (priv->beacon_skb != NULL)
3779752d 1092 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1093}
1094
1095static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1096{
1097 struct mwl8k_priv *priv = hw->priv;
1098 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1099 int processed;
1100
1101 processed = 0;
45eb400d 1102 while (rxq->rxd_count && limit--) {
a66098da 1103 struct sk_buff *skb;
54bc3a0d
LB		 1104 void *rxd;
1105 int pkt_len;
a66098da 1106 struct ieee80211_rx_status status;
20f09c3d 1107 __le16 qos;
a66098da 1108
788838eb 1109 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1110 if (skb == NULL)
1111 break;
54bc3a0d
LB		 1112
1113 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1114
20f09c3d 1115 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
54bc3a0d
LB		 1116 if (pkt_len < 0)
1117 break;
1118
788838eb
LB		 1119 rxq->buf[rxq->head].skb = NULL;
1120
1121 pci_unmap_single(priv->pdev,
1122 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1123 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1124 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1125
54bc3a0d
LB		 1126 rxq->head++;
1127 if (rxq->head == MWL8K_RX_DESCS)
1128 rxq->head = 0;
1129
45eb400d 1130 rxq->rxd_count--;
a66098da 1131
54bc3a0d 1132 skb_put(skb, pkt_len);
20f09c3d 1133 mwl8k_remove_dma_header(skb, qos);
a66098da 1134
a66098da 1135 /*
c2c357ce
LB		 1136 * Check for a pending join operation. Save a
1137 * copy of the beacon and schedule a tasklet to
1138 * send a FINALIZE_JOIN command to the firmware.
a66098da 1139 */
54bc3a0d 1140 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1141 mwl8k_save_beacon(hw, skb);
a66098da 1142
f1d58c25
JB		 1143 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1144 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1145
1146 processed++;
1147 }
1148
1149 return processed;
1150}
1151
1152
1153/*
1154 * Packet transmission.
1155 */
1156
a66098da
LB		 1157/* Transmit packet ACK policy */
1158#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 1159#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1160
a66098da
LB		 1161#define MWL8K_TXD_STATUS_OK 0x00000001
1162#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1163#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1164#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1165#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 1166
1167struct mwl8k_tx_desc {
1168 __le32 status;
1169 __u8 data_rate;
1170 __u8 tx_priority;
1171 __le16 qos_control;
1172 __le32 pkt_phys_addr;
1173 __le16 pkt_len;
d89173f2 1174 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1175 __le32 next_txd_phys_addr;
a66098da
LB		 1176 __le32 reserved;
1177 __le16 rate_info;
1178 __u8 peer_id;
1179 __u8 tx_frag_cnt;
1180} __attribute__((packed));
1181
1182#define MWL8K_TX_DESCS 128
1183
1184static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1185{
1186 struct mwl8k_priv *priv = hw->priv;
1187 struct mwl8k_tx_queue *txq = priv->txq + index;
1188 int size;
1189 int i;
1190
45eb400d
LB		 1191 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1192 txq->stats.limit = MWL8K_TX_DESCS;
1193 txq->head = 0;
1194 txq->tail = 0;
a66098da
LB		 1195
1196 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1197
45eb400d
LB		 1198 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1199 if (txq->txd == NULL) {
a66098da 1200 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1201 wiphy_name(hw->wiphy));
a66098da
LB		 1202 return -ENOMEM;
1203 }
45eb400d 1204 memset(txq->txd, 0, size);
a66098da 1205
45eb400d
LB		 1206 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1207 if (txq->skb == NULL) {
a66098da 1208 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1209 wiphy_name(hw->wiphy));
45eb400d 1210 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1211 return -ENOMEM;
1212 }
45eb400d 1213 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1214
1215 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1216 struct mwl8k_tx_desc *tx_desc;
1217 int nexti;
1218
45eb400d 1219 tx_desc = txq->txd + i;
a66098da
LB		 1220 nexti = (i + 1) % MWL8K_TX_DESCS;
1221
1222 tx_desc->status = 0;
45eb400d
LB		 1223 tx_desc->next_txd_phys_addr =
1224 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1225 }
1226
1227 return 0;
1228}
1229
1230static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1231{
1232 iowrite32(MWL8K_H2A_INT_PPA_READY,
1233 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1234 iowrite32(MWL8K_H2A_INT_DUMMY,
1235 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1236 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1237}
1238
7e1112d3 1239static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1240{
7e1112d3
LB		 1241 struct mwl8k_priv *priv = hw->priv;
1242 int i;
1243
1244 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1245 struct mwl8k_tx_queue *txq = priv->txq + i;
1246 int fw_owned = 0;
1247 int drv_owned = 0;
1248 int unused = 0;
1249 int desc;
1250
a66098da 1251 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1252 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1253 u32 status;
a66098da 1254
7e1112d3 1255 status = le32_to_cpu(tx_desc->status);
a66098da 1256 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1257 fw_owned++;
a66098da 1258 else
7e1112d3 1259 drv_owned++;
a66098da
LB		 1260
1261 if (tx_desc->pkt_len == 0)
7e1112d3 1262 unused++;
a66098da 1263 }
a66098da 1264
7e1112d3
LB		 1265 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1266 "fw_owned=%d drv_owned=%d unused=%d\n",
1267 wiphy_name(hw->wiphy), i,
1268 txq->stats.len, txq->head, txq->tail,
1269 fw_owned, drv_owned, unused);
1270 }
a66098da
LB		 1271}
1272
618952a7 1273/*
88de754a 1274 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1275 */
7e1112d3
LB		 1276#define MWL8K_TX_WAIT_TIMEOUT_MS 1000
1277
950d5b01 1278static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1279{
a66098da 1280 struct mwl8k_priv *priv = hw->priv;
88de754a 1281 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1282 int retry;
1283 int rc;
a66098da
LB		 1284
1285 might_sleep();
1286
7e1112d3
LB		 1287 /*
1288 * The TX queues are stopped at this point, so this test
1289 * doesn't need to take ->tx_lock.
1290 */
1291 if (!priv->pending_tx_pkts)
1292 return 0;
1293
1294 retry = 0;
1295 rc = 0;
1296
a66098da 1297 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1298 priv->tx_wait = &tx_wait;
1299 while (!rc) {
1300 int oldcount;
1301 unsigned long timeout;
a66098da 1302
7e1112d3 1303 oldcount = priv->pending_tx_pkts;
a66098da 1304
7e1112d3 1305 spin_unlock_bh(&priv->tx_lock);
88de754a 1306 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1307 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1308 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1309
1310 if (timeout) {
1311 WARN_ON(priv->pending_tx_pkts);
1312 if (retry) {
1313 printk(KERN_NOTICE "%s: tx rings drained\n",
1314 wiphy_name(hw->wiphy));
1315 }
1316 break;
1317 }
1318
1319 if (priv->pending_tx_pkts < oldcount) {
1320 printk(KERN_NOTICE "%s: timeout waiting for tx "
1321 "rings to drain (%d -> %d pkts), retrying\n",
1322 wiphy_name(hw->wiphy), oldcount,
1323 priv->pending_tx_pkts);
1324 retry = 1;
1325 continue;
1326 }
1327
a66098da 1328 priv->tx_wait = NULL;
a66098da 1329
7e1112d3
LB		 1330 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1331 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1332 mwl8k_dump_tx_rings(hw);
1333
1334 rc = -ETIMEDOUT;
a66098da 1335 }
7e1112d3 1336 spin_unlock_bh(&priv->tx_lock);
a66098da 1337
7e1112d3 1338 return rc;
a66098da
LB		 1339}
1340
c23b5a69
LB		 1341#define MWL8K_TXD_SUCCESS(status) \
1342 ((status) & (MWL8K_TXD_STATUS_OK | \
1343 MWL8K_TXD_STATUS_OK_RETRY | \
1344 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1345
1346static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1347{
1348 struct mwl8k_priv *priv = hw->priv;
1349 struct mwl8k_tx_queue *txq = priv->txq + index;
1350 int wake = 0;
1351
45eb400d 1352 while (txq->stats.len > 0) {
a66098da 1353 int tx;
a66098da
LB		 1354 struct mwl8k_tx_desc *tx_desc;
1355 unsigned long addr;
ce9e2e1b 1356 int size;
a66098da
LB		 1357 struct sk_buff *skb;
1358 struct ieee80211_tx_info *info;
1359 u32 status;
1360
45eb400d
LB		 1361 tx = txq->head;
1362 tx_desc = txq->txd + tx;
a66098da
LB		 1363
1364 status = le32_to_cpu(tx_desc->status);
1365
1366 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1367 if (!force)
1368 break;
1369 tx_desc->status &=
1370 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1371 }
1372
45eb400d
LB		 1373 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1374 BUG_ON(txq->stats.len == 0);
1375 txq->stats.len--;
a66098da
LB		 1376 priv->pending_tx_pkts--;
1377
1378 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1379 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1380 skb = txq->skb[tx];
1381 txq->skb[tx] = NULL;
a66098da
LB		 1382
1383 BUG_ON(skb == NULL);
1384 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1385
20f09c3d 1386 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1387
1388 /* Mark descriptor as unused */
1389 tx_desc->pkt_phys_addr = 0;
1390 tx_desc->pkt_len = 0;
1391
a66098da
LB		 1392 info = IEEE80211_SKB_CB(skb);
1393 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1394 if (MWL8K_TXD_SUCCESS(status))
a66098da 1395 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1396
1397 ieee80211_tx_status_irqsafe(hw, skb);
1398
618952a7 1399 wake = 1;
a66098da
LB		 1400 }
1401
618952a7 1402 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da
LB		 1403 ieee80211_wake_queue(hw, index);
1404}
1405
1406/* must be called only when the card's transmit is completely halted */
1407static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1408{
1409 struct mwl8k_priv *priv = hw->priv;
1410 struct mwl8k_tx_queue *txq = priv->txq + index;
1411
1412 mwl8k_txq_reclaim(hw, index, 1);
1413
45eb400d
LB		 1414 kfree(txq->skb);
1415 txq->skb = NULL;
a66098da
LB		 1416
1417 pci_free_consistent(priv->pdev,
1418 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1419 txq->txd, txq->txd_dma);
1420 txq->txd = NULL;
a66098da
LB		 1421}
1422
1423static int
1424mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1425{
1426 struct mwl8k_priv *priv = hw->priv;
1427 struct ieee80211_tx_info *tx_info;
23b33906 1428 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1429 struct ieee80211_hdr *wh;
1430 struct mwl8k_tx_queue *txq;
1431 struct mwl8k_tx_desc *tx;
a66098da 1432 dma_addr_t dma;
23b33906
LB		 1433 u32 txstatus;
1434 u8 txdatarate;
1435 u16 qos;
a66098da 1436
23b33906
LB		 1437 wh = (struct ieee80211_hdr *)skb->data;
1438 if (ieee80211_is_data_qos(wh->frame_control))
1439 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1440 else
1441 qos = 0;
a66098da 1442
76266b2a 1443 mwl8k_add_dma_header(skb);
23b33906 1444 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1445
1446 tx_info = IEEE80211_SKB_CB(skb);
1447 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1448
1449 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1450 u16 seqno = mwl8k_vif->seqno;
23b33906 1451
a66098da
LB		 1452 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1453 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1454 mwl8k_vif->seqno = seqno++ % 4096;
1455 }
1456
23b33906
LB		 1457 /* Setup firmware control bit fields for each frame type. */
1458 txstatus = 0;
1459 txdatarate = 0;
1460 if (ieee80211_is_mgmt(wh->frame_control) ||
1461 ieee80211_is_ctl(wh->frame_control)) {
1462 txdatarate = 0;
1463 qos = mwl8k_qos_setbit_eosp(qos);
1464 /* Set Queue size to unspecified */
1465 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1466 } else if (ieee80211_is_data(wh->frame_control)) {
1467 txdatarate = 1;
1468 if (is_multicast_ether_addr(wh->addr1))
1469 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1470
1471 /* Send pkt in an aggregate if AMPDU frame. */
1472 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1473 qos = mwl8k_qos_setbit_ack(qos,
1474 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1475 else
1476 qos = mwl8k_qos_setbit_ack(qos,
1477 MWL8K_TXD_ACK_POLICY_NORMAL);
1478
1479 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1480 qos = mwl8k_qos_setbit_amsdu(qos);
1481 }
a66098da
LB		 1482
1483 dma = pci_map_single(priv->pdev, skb->data,
1484 skb->len, PCI_DMA_TODEVICE);
1485
1486 if (pci_dma_mapping_error(priv->pdev, dma)) {
1487 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1488 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1489 dev_kfree_skb(skb);
a66098da
LB		 1490 return NETDEV_TX_OK;
1491 }
1492
23b33906 1493 spin_lock_bh(&priv->tx_lock);
a66098da 1494
23b33906 1495 txq = priv->txq + index;
a66098da 1496
45eb400d
LB		 1497 BUG_ON(txq->skb[txq->tail] != NULL);
1498 txq->skb[txq->tail] = skb;
a66098da 1499
45eb400d 1500 tx = txq->txd + txq->tail;
23b33906
LB		 1501 tx->data_rate = txdatarate;
1502 tx->tx_priority = index;
a66098da 1503 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1504 tx->pkt_phys_addr = cpu_to_le32(dma);
1505 tx->pkt_len = cpu_to_le16(skb->len);
23b33906
LB		 1506 tx->rate_info = 0;
1507 tx->peer_id = mwl8k_vif->peer_id;
a66098da 1508 wmb();
23b33906
LB		 1509 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1510
45eb400d
LB		 1511 txq->stats.count++;
1512 txq->stats.len++;
a66098da 1513 priv->pending_tx_pkts++;
a66098da 1514
45eb400d
LB		 1515 txq->tail++;
1516 if (txq->tail == MWL8K_TX_DESCS)
1517 txq->tail = 0;
23b33906 1518
45eb400d 1519 if (txq->head == txq->tail)
a66098da
LB		 1520 ieee80211_stop_queue(hw, index);
1521
23b33906 1522 mwl8k_tx_start(priv);
a66098da
LB		 1523
1524 spin_unlock_bh(&priv->tx_lock);
1525
1526 return NETDEV_TX_OK;
1527}
1528
1529
618952a7
LB		 1530/*
1531 * Firmware access.
1532 *
1533 * We have the following requirements for issuing firmware commands:
1534 * - Some commands require that the packet transmit path is idle when
1535 * the command is issued. (For simplicity, we'll just quiesce the
1536 * transmit path for every command.)
1537 * - There are certain sequences of commands that need to be issued to
1538 * the hardware sequentially, with no other intervening commands.
1539 *
1540 * This leads to an implementation of a "firmware lock" as a mutex that
1541 * can be taken recursively, and which is taken by both the low-level
1542 * command submission function (mwl8k_post_cmd) as well as any users of
1543 * that function that require issuing of an atomic sequence of commands,
1544 * and quiesces the transmit path whenever it's taken.
1545 */
1546static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1547{
1548 struct mwl8k_priv *priv = hw->priv;
1549
1550 if (priv->fw_mutex_owner != current) {
1551 int rc;
1552
1553 mutex_lock(&priv->fw_mutex);
1554 ieee80211_stop_queues(hw);
1555
1556 rc = mwl8k_tx_wait_empty(hw);
1557 if (rc) {
1558 ieee80211_wake_queues(hw);
1559 mutex_unlock(&priv->fw_mutex);
1560
1561 return rc;
1562 }
1563
1564 priv->fw_mutex_owner = current;
1565 }
1566
1567 priv->fw_mutex_depth++;
1568
1569 return 0;
1570}
1571
1572static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1573{
1574 struct mwl8k_priv *priv = hw->priv;
1575
1576 if (!--priv->fw_mutex_depth) {
1577 ieee80211_wake_queues(hw);
1578 priv->fw_mutex_owner = NULL;
1579 mutex_unlock(&priv->fw_mutex);
1580 }
1581}
1582
1583
a66098da
LB		 1584/*
1585 * Command processing.
1586 */
1587
0c9cc640
LB		 1588/* Timeout firmware commands after 10s */
1589#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 1590
1591static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1592{
1593 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1594 struct mwl8k_priv *priv = hw->priv;
1595 void __iomem *regs = priv->regs;
1596 dma_addr_t dma_addr;
1597 unsigned int dma_size;
1598 int rc;
a66098da
LB		 1599 unsigned long timeout = 0;
1600 u8 buf[32];
1601
c2c357ce 1602 cmd->result = 0xffff;
a66098da
LB		 1603 dma_size = le16_to_cpu(cmd->length);
1604 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1605 PCI_DMA_BIDIRECTIONAL);
1606 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1607 return -ENOMEM;
1608
618952a7 1609 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1610 if (rc) {
1611 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1612 PCI_DMA_BIDIRECTIONAL);
618952a7 1613 return rc;
39a1e42e 1614 }
a66098da 1615
a66098da
LB		 1616 priv->hostcmd_wait = &cmd_wait;
1617 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1618 iowrite32(MWL8K_H2A_INT_DOORBELL,
1619 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1620 iowrite32(MWL8K_H2A_INT_DUMMY,
1621 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1622
1623 timeout = wait_for_completion_timeout(&cmd_wait,
1624 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1625
618952a7
LB		 1626 priv->hostcmd_wait = NULL;
1627
1628 mwl8k_fw_unlock(hw);
1629
37055bd4
LB		 1630 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1631 PCI_DMA_BIDIRECTIONAL);
1632
a66098da 1633 if (!timeout) {
a66098da 1634 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1635 wiphy_name(hw->wiphy),
a66098da
LB		 1636 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1637 MWL8K_CMD_TIMEOUT_MS);
1638 rc = -ETIMEDOUT;
1639 } else {
0c9cc640
LB		 1640 int ms;
1641
1642 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1643
ce9e2e1b 1644 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1645 if (rc)
1646 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1647 wiphy_name(hw->wiphy),
a66098da 1648 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1649 le16_to_cpu(cmd->result));
0c9cc640
LB		 1650 else if (ms > 2000)
1651 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1652 wiphy_name(hw->wiphy),
1653 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1654 ms);
a66098da
LB		 1655 }
1656
a66098da
LB		 1657 return rc;
1658}
1659
1660/*
04b147b1 1661 * CMD_GET_HW_SPEC (STA version).
a66098da 1662 */
04b147b1 1663struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1664 struct mwl8k_cmd_pkt header;
1665 __u8 hw_rev;
1666 __u8 host_interface;
1667 __le16 num_mcaddrs;
d89173f2 1668 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1669 __le16 region_code;
1670 __le32 fw_rev;
1671 __le32 ps_cookie;
1672 __le32 caps;
1673 __u8 mcs_bitmap[16];
1674 __le32 rx_queue_ptr;
1675 __le32 num_tx_queues;
1676 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1677 __le32 caps2;
1678 __le32 num_tx_desc_per_queue;
45eb400d 1679 __le32 total_rxd;
a66098da
LB		 1680} __attribute__((packed));
1681
04b147b1 1682static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1683{
1684 struct mwl8k_priv *priv = hw->priv;
04b147b1 1685 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1686 int rc;
1687 int i;
1688
1689 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1690 if (cmd == NULL)
1691 return -ENOMEM;
1692
1693 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1694 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1695
1696 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1697 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1698 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1699 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1700 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1701 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1702 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1703 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1704
1705 rc = mwl8k_post_cmd(hw, &cmd->header);
1706
1707 if (!rc) {
1708 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1709 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1710 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1711 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1712 }
1713
1714 kfree(cmd);
1715 return rc;
1716}
1717
42fba21d
LB		 1718/*
1719 * CMD_GET_HW_SPEC (AP version).
1720 */
1721struct mwl8k_cmd_get_hw_spec_ap {
1722 struct mwl8k_cmd_pkt header;
1723 __u8 hw_rev;
1724 __u8 host_interface;
1725 __le16 num_wcb;
1726 __le16 num_mcaddrs;
1727 __u8 perm_addr[ETH_ALEN];
1728 __le16 region_code;
1729 __le16 num_antenna;
1730 __le32 fw_rev;
1731 __le32 wcbbase0;
1732 __le32 rxwrptr;
1733 __le32 rxrdptr;
1734 __le32 ps_cookie;
1735 __le32 wcbbase1;
1736 __le32 wcbbase2;
1737 __le32 wcbbase3;
1738} __attribute__((packed));
1739
1740static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1741{
1742 struct mwl8k_priv *priv = hw->priv;
1743 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1744 int rc;
1745
1746 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1747 if (cmd == NULL)
1748 return -ENOMEM;
1749
1750 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1751 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1752
1753 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1754 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1755
1756 rc = mwl8k_post_cmd(hw, &cmd->header);
1757
1758 if (!rc) {
1759 int off;
1760
1761 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1762 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1763 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1764 priv->hw_rev = cmd->hw_rev;
1765
1766 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1767 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1768
1769 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1770 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1771
1772 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1773 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1774
1775 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1776 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1777
1778 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1779 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1780
1781 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1782 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1783 }
1784
1785 kfree(cmd);
1786 return rc;
1787}
1788
1789/*
1790 * CMD_SET_HW_SPEC.
1791 */
1792struct mwl8k_cmd_set_hw_spec {
1793 struct mwl8k_cmd_pkt header;
1794 __u8 hw_rev;
1795 __u8 host_interface;
1796 __le16 num_mcaddrs;
1797 __u8 perm_addr[ETH_ALEN];
1798 __le16 region_code;
1799 __le32 fw_rev;
1800 __le32 ps_cookie;
1801 __le32 caps;
1802 __le32 rx_queue_ptr;
1803 __le32 num_tx_queues;
1804 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1805 __le32 flags;
1806 __le32 num_tx_desc_per_queue;
1807 __le32 total_rxd;
1808} __attribute__((packed));
1809
1810#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1811
1812static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1813{
1814 struct mwl8k_priv *priv = hw->priv;
1815 struct mwl8k_cmd_set_hw_spec *cmd;
1816 int rc;
1817 int i;
1818
1819 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1820 if (cmd == NULL)
1821 return -ENOMEM;
1822
1823 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1824 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1825
1826 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1827 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1828 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1829 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1830 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1831 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1832 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1833 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1834
1835 rc = mwl8k_post_cmd(hw, &cmd->header);
1836 kfree(cmd);
1837
1838 return rc;
1839}
1840
a66098da
LB		 1841/*
1842 * CMD_MAC_MULTICAST_ADR.
1843 */
1844struct mwl8k_cmd_mac_multicast_adr {
1845 struct mwl8k_cmd_pkt header;
1846 __le16 action;
1847 __le16 numaddr;
ce9e2e1b 1848 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1849};
1850
d5e30845
LB		 1851#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1852#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1853#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1854#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1855
e81cd2d6 1856static struct mwl8k_cmd_pkt *
447ced07 1857__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1858 int mc_count, struct dev_addr_list *mclist)
a66098da 1859{
e81cd2d6 1860 struct mwl8k_priv *priv = hw->priv;
a66098da 1861 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1862 int size;
e81cd2d6 1863
447ced07 1864 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1865 allmulti = 1;
1866 mc_count = 0;
1867 }
e81cd2d6
LB		 1868
1869 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1870
e81cd2d6 1871 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1872 if (cmd == NULL)
e81cd2d6 1873 return NULL;
a66098da
LB		 1874
1875 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1876 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1877 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1878 MWL8K_ENABLE_RX_BROADCAST);
1879
1880 if (allmulti) {
1881 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1882 } else if (mc_count) {
1883 int i;
1884
1885 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1886 cmd->numaddr = cpu_to_le16(mc_count);
1887 for (i = 0; i < mc_count && mclist; i++) {
1888 if (mclist->da_addrlen != ETH_ALEN) {
1889 kfree(cmd);
1890 return NULL;
1891 }
1892 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1893 mclist = mclist->next;
a66098da 1894 }
a66098da
LB		 1895 }
1896
e81cd2d6 1897 return &cmd->header;
a66098da
LB		 1898}
1899
1900/*
1901 * CMD_802_11_GET_STAT.
1902 */
1903struct mwl8k_cmd_802_11_get_stat {
1904 struct mwl8k_cmd_pkt header;
a66098da
LB		 1905 __le32 stats[64];
1906} __attribute__((packed));
1907
1908#define MWL8K_STAT_ACK_FAILURE 9
1909#define MWL8K_STAT_RTS_FAILURE 12
1910#define MWL8K_STAT_FCS_ERROR 24
1911#define MWL8K_STAT_RTS_SUCCESS 11
1912
1913static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1914 struct ieee80211_low_level_stats *stats)
1915{
1916 struct mwl8k_cmd_802_11_get_stat *cmd;
1917 int rc;
1918
1919 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1920 if (cmd == NULL)
1921 return -ENOMEM;
1922
1923 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1924 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1925
1926 rc = mwl8k_post_cmd(hw, &cmd->header);
1927 if (!rc) {
1928 stats->dot11ACKFailureCount =
1929 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1930 stats->dot11RTSFailureCount =
1931 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1932 stats->dot11FCSErrorCount =
1933 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1934 stats->dot11RTSSuccessCount =
1935 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1936 }
1937 kfree(cmd);
1938
1939 return rc;
1940}
1941
1942/*
1943 * CMD_802_11_RADIO_CONTROL.
1944 */
1945struct mwl8k_cmd_802_11_radio_control {
1946 struct mwl8k_cmd_pkt header;
1947 __le16 action;
1948 __le16 control;
1949 __le16 radio_on;
1950} __attribute__((packed));
1951
c46563b7
LB		 1952static int
1953mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1954{
1955 struct mwl8k_priv *priv = hw->priv;
1956 struct mwl8k_cmd_802_11_radio_control *cmd;
1957 int rc;
1958
c46563b7 1959 if (enable == priv->radio_on && !force)
a66098da
LB		 1960 return 0;
1961
a66098da
LB		 1962 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1963 if (cmd == NULL)
1964 return -ENOMEM;
1965
1966 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1967 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1968 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1969 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1970 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1971
1972 rc = mwl8k_post_cmd(hw, &cmd->header);
1973 kfree(cmd);
1974
1975 if (!rc)
c46563b7 1976 priv->radio_on = enable;
a66098da
LB		 1977
1978 return rc;
1979}
1980
c46563b7
LB		 1981static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1982{
1983 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1984}
1985
1986static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1987{
1988 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1989}
1990
a66098da
LB		 1991static int
1992mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1993{
1994 struct mwl8k_priv *priv;
1995
1996 if (hw == NULL || hw->priv == NULL)
1997 return -EINVAL;
1998 priv = hw->priv;
1999
68ce3884 2000 priv->radio_short_preamble = short_preamble;
a66098da 2001
c46563b7 2002 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
a66098da
LB		 2003}
2004
2005/*
2006 * CMD_802_11_RF_TX_POWER.
2007 */
2008#define MWL8K_TX_POWER_LEVEL_TOTAL 8
2009
2010struct mwl8k_cmd_802_11_rf_tx_power {
2011 struct mwl8k_cmd_pkt header;
2012 __le16 action;
2013 __le16 support_level;
2014 __le16 current_level;
2015 __le16 reserved;
2016 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
2017} __attribute__((packed));
2018
2019static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
2020{
2021 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
2022 int rc;
2023
2024 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2025 if (cmd == NULL)
2026 return -ENOMEM;
2027
2028 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2029 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2030 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2031 cmd->support_level = cpu_to_le16(dBm);
2032
2033 rc = mwl8k_post_cmd(hw, &cmd->header);
2034 kfree(cmd);
2035
2036 return rc;
2037}
2038
08b06347
LB		 2039/*
2040 * CMD_RF_ANTENNA.
2041 */
2042struct mwl8k_cmd_rf_antenna {
2043 struct mwl8k_cmd_pkt header;
2044 __le16 antenna;
2045 __le16 mode;
2046} __attribute__((packed));
2047
2048#define MWL8K_RF_ANTENNA_RX 1
2049#define MWL8K_RF_ANTENNA_TX 2
2050
2051static int
2052mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2053{
2054 struct mwl8k_cmd_rf_antenna *cmd;
2055 int rc;
2056
2057 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2058 if (cmd == NULL)
2059 return -ENOMEM;
2060
2061 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2062 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2063 cmd->antenna = cpu_to_le16(antenna);
2064 cmd->mode = cpu_to_le16(mask);
2065
2066 rc = mwl8k_post_cmd(hw, &cmd->header);
2067 kfree(cmd);
2068
2069 return rc;
2070}
2071
a66098da
LB		 2072/*
2073 * CMD_SET_PRE_SCAN.
2074 */
2075struct mwl8k_cmd_set_pre_scan {
2076 struct mwl8k_cmd_pkt header;
2077} __attribute__((packed));
2078
2079static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2080{
2081 struct mwl8k_cmd_set_pre_scan *cmd;
2082 int rc;
2083
2084 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2085 if (cmd == NULL)
2086 return -ENOMEM;
2087
2088 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2089 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2090
2091 rc = mwl8k_post_cmd(hw, &cmd->header);
2092 kfree(cmd);
2093
2094 return rc;
2095}
2096
2097/*
2098 * CMD_SET_POST_SCAN.
2099 */
2100struct mwl8k_cmd_set_post_scan {
2101 struct mwl8k_cmd_pkt header;
2102 __le32 isibss;
d89173f2 2103 __u8 bssid[ETH_ALEN];
a66098da
LB		 2104} __attribute__((packed));
2105
2106static int
ce9e2e1b 2107mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
a66098da
LB		 2108{
2109 struct mwl8k_cmd_set_post_scan *cmd;
2110 int rc;
2111
2112 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2113 if (cmd == NULL)
2114 return -ENOMEM;
2115
2116 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2117 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2118 cmd->isibss = 0;
d89173f2 2119 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2120
2121 rc = mwl8k_post_cmd(hw, &cmd->header);
2122 kfree(cmd);
2123
2124 return rc;
2125}
2126
2127/*
2128 * CMD_SET_RF_CHANNEL.
2129 */
2130struct mwl8k_cmd_set_rf_channel {
2131 struct mwl8k_cmd_pkt header;
2132 __le16 action;
2133 __u8 current_channel;
2134 __le32 channel_flags;
2135} __attribute__((packed));
2136
2137static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2138 struct ieee80211_channel *channel)
2139{
2140 struct mwl8k_cmd_set_rf_channel *cmd;
2141 int rc;
2142
2143 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2144 if (cmd == NULL)
2145 return -ENOMEM;
2146
2147 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2148 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2149 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2150 cmd->current_channel = channel->hw_value;
2151 if (channel->band == IEEE80211_BAND_2GHZ)
2152 cmd->channel_flags = cpu_to_le32(0x00000081);
2153 else
2154 cmd->channel_flags = cpu_to_le32(0x00000000);
2155
2156 rc = mwl8k_post_cmd(hw, &cmd->header);
2157 kfree(cmd);
2158
2159 return rc;
2160}
2161
2162/*
2163 * CMD_SET_SLOT.
2164 */
2165struct mwl8k_cmd_set_slot {
2166 struct mwl8k_cmd_pkt header;
2167 __le16 action;
2168 __u8 short_slot;
2169} __attribute__((packed));
2170
5539bb51 2171static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da
LB		 2172{
2173 struct mwl8k_cmd_set_slot *cmd;
2174 int rc;
2175
2176 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2177 if (cmd == NULL)
2178 return -ENOMEM;
2179
2180 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2181 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2182 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
5539bb51 2183 cmd->short_slot = short_slot_time;
a66098da
LB		 2184
2185 rc = mwl8k_post_cmd(hw, &cmd->header);
2186 kfree(cmd);
2187
2188 return rc;
2189}
2190
2191/*
2192 * CMD_MIMO_CONFIG.
2193 */
2194struct mwl8k_cmd_mimo_config {
2195 struct mwl8k_cmd_pkt header;
2196 __le32 action;
2197 __u8 rx_antenna_map;
2198 __u8 tx_antenna_map;
2199} __attribute__((packed));
2200
2201static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2202{
2203 struct mwl8k_cmd_mimo_config *cmd;
2204 int rc;
2205
2206 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2207 if (cmd == NULL)
2208 return -ENOMEM;
2209
2210 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2211 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2212 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2213 cmd->rx_antenna_map = rx;
2214 cmd->tx_antenna_map = tx;
2215
2216 rc = mwl8k_post_cmd(hw, &cmd->header);
2217 kfree(cmd);
2218
2219 return rc;
2220}
2221
2222/*
2223 * CMD_ENABLE_SNIFFER.
2224 */
2225struct mwl8k_cmd_enable_sniffer {
2226 struct mwl8k_cmd_pkt header;
2227 __le32 action;
2228} __attribute__((packed));
2229
2230static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2231{
2232 struct mwl8k_cmd_enable_sniffer *cmd;
2233 int rc;
2234
2235 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2236 if (cmd == NULL)
2237 return -ENOMEM;
2238
2239 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2240 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2241 cmd->action = cpu_to_le32(!!enable);
a66098da
LB		 2242
2243 rc = mwl8k_post_cmd(hw, &cmd->header);
2244 kfree(cmd);
2245
2246 return rc;
2247}
2248
32060e1b
LB		 2249/*
2250 * CMD_SET_MAC_ADDR.
2251 */
2252struct mwl8k_cmd_set_mac_addr {
2253 struct mwl8k_cmd_pkt header;
259a8e7d
LB		 2254 union {
2255 struct {
2256 __le16 mac_type;
2257 __u8 mac_addr[ETH_ALEN];
2258 } mbss;
2259 __u8 mac_addr[ETH_ALEN];
2260 };
32060e1b
LB		 2261} __attribute__((packed));
2262
2263static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2264{
259a8e7d 2265 struct mwl8k_priv *priv = hw->priv;
32060e1b
LB		 2266 struct mwl8k_cmd_set_mac_addr *cmd;
2267 int rc;
2268
2269 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2270 if (cmd == NULL)
2271 return -ENOMEM;
2272
2273 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2274 cmd->header.length = cpu_to_le16(sizeof(*cmd));
259a8e7d
LB		 2275 if (priv->ap_fw) {
2276 cmd->mbss.mac_type = 0;
2277 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2278 } else {
2279 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2280 }
32060e1b
LB		 2281
2282 rc = mwl8k_post_cmd(hw, &cmd->header);
2283 kfree(cmd);
2284
2285 return rc;
2286}
2287
2288
a66098da 2289/*
ce9e2e1b 2290 * CMD_SET_RATEADAPT_MODE.
a66098da
LB		 2291 */
2292struct mwl8k_cmd_set_rate_adapt_mode {
2293 struct mwl8k_cmd_pkt header;
2294 __le16 action;
2295 __le16 mode;
2296} __attribute__((packed));
2297
2298static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2299{
2300 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2301 int rc;
2302
2303 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2304 if (cmd == NULL)
2305 return -ENOMEM;
2306
2307 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2308 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2309 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2310 cmd->mode = cpu_to_le16(mode);
2311
2312 rc = mwl8k_post_cmd(hw, &cmd->header);
2313 kfree(cmd);
2314
2315 return rc;
2316}
2317
2318/*
2319 * CMD_SET_WMM_MODE.
2320 */
2321struct mwl8k_cmd_set_wmm {
2322 struct mwl8k_cmd_pkt header;
2323 __le16 action;
2324} __attribute__((packed));
2325
2326static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2327{
2328 struct mwl8k_priv *priv = hw->priv;
2329 struct mwl8k_cmd_set_wmm *cmd;
2330 int rc;
2331
2332 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2333 if (cmd == NULL)
2334 return -ENOMEM;
2335
2336 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2337 cmd->header.length = cpu_to_le16(sizeof(*cmd));
0439b1f5 2338 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2339
2340 rc = mwl8k_post_cmd(hw, &cmd->header);
2341 kfree(cmd);
2342
2343 if (!rc)
0439b1f5 2344 priv->wmm_enabled = enable;
a66098da
LB		 2345
2346 return rc;
2347}
2348
2349/*
2350 * CMD_SET_RTS_THRESHOLD.
2351 */
2352struct mwl8k_cmd_rts_threshold {
2353 struct mwl8k_cmd_pkt header;
2354 __le16 action;
2355 __le16 threshold;
2356} __attribute__((packed));
2357
2358static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
733d3067 2359 u16 action, u16 threshold)
a66098da
LB		 2360{
2361 struct mwl8k_cmd_rts_threshold *cmd;
2362 int rc;
2363
2364 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2365 if (cmd == NULL)
2366 return -ENOMEM;
2367
2368 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2369 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2370 cmd->action = cpu_to_le16(action);
733d3067 2371 cmd->threshold = cpu_to_le16(threshold);
a66098da
LB		 2372
2373 rc = mwl8k_post_cmd(hw, &cmd->header);
2374 kfree(cmd);
2375
2376 return rc;
2377}
2378
2379/*
2380 * CMD_SET_EDCA_PARAMS.
2381 */
2382struct mwl8k_cmd_set_edca_params {
2383 struct mwl8k_cmd_pkt header;
2384
2385 /* See MWL8K_SET_EDCA_XXX below */
2386 __le16 action;
2387
2388 /* TX opportunity in units of 32 us */
2389 __le16 txop;
2390
2e484c89
LB		 2391 union {
2392 struct {
2393 /* Log exponent of max contention period: 0...15 */
2394 __le32 log_cw_max;
2395
2396 /* Log exponent of min contention period: 0...15 */
2397 __le32 log_cw_min;
2398
2399 /* Adaptive interframe spacing in units of 32us */
2400 __u8 aifs;
2401
2402 /* TX queue to configure */
2403 __u8 txq;
2404 } ap;
2405 struct {
2406 /* Log exponent of max contention period: 0...15 */
2407 __u8 log_cw_max;
a66098da 2408
2e484c89
LB		 2409 /* Log exponent of min contention period: 0...15 */
2410 __u8 log_cw_min;
a66098da 2411
2e484c89
LB		 2412 /* Adaptive interframe spacing in units of 32us */
2413 __u8 aifs;
a66098da 2414
2e484c89
LB		 2415 /* TX queue to configure */
2416 __u8 txq;
2417 } sta;
2418 };
a66098da
LB		 2419} __attribute__((packed));
2420
a66098da
LB		 2421#define MWL8K_SET_EDCA_CW 0x01
2422#define MWL8K_SET_EDCA_TXOP 0x02
2423#define MWL8K_SET_EDCA_AIFS 0x04
2424
2425#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2426 MWL8K_SET_EDCA_TXOP | \
2427 MWL8K_SET_EDCA_AIFS)
2428
2429static int
2430mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2431 __u16 cw_min, __u16 cw_max,
2432 __u8 aifs, __u16 txop)
2433{
2e484c89 2434 struct mwl8k_priv *priv = hw->priv;
a66098da 2435 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2436 int rc;
2437
2438 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2439 if (cmd == NULL)
2440 return -ENOMEM;
2441
22995b24
LB		 2442 /*
2443 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2444 * this call.
2445 */
2446 qnum ^= !(qnum >> 1);
2447
a66098da
LB		 2448 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2449 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2450 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2451 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2452 if (priv->ap_fw) {
2453 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2454 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2455 cmd->ap.aifs = aifs;
2456 cmd->ap.txq = qnum;
2457 } else {
2458 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2459 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2460 cmd->sta.aifs = aifs;
2461 cmd->sta.txq = qnum;
2462 }
a66098da
LB		 2463
2464 rc = mwl8k_post_cmd(hw, &cmd->header);
2465 kfree(cmd);
2466
2467 return rc;
2468}
2469
2470/*
2471 * CMD_FINALIZE_JOIN.
2472 */
2473
2474/* FJ beacon buffer size is compiled into the firmware. */
2475#define MWL8K_FJ_BEACON_MAXLEN 128
2476
2477struct mwl8k_cmd_finalize_join {
2478 struct mwl8k_cmd_pkt header;
2479 __le32 sleep_interval; /* Number of beacon periods to sleep */
2480 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2481} __attribute__((packed));
2482
2483static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2484 __u16 framelen, __u16 dtim)
2485{
2486 struct mwl8k_cmd_finalize_join *cmd;
2487 struct ieee80211_mgmt *payload = frame;
2488 u16 hdrlen;
2489 u32 payload_len;
2490 int rc;
2491
2492 if (frame == NULL)
2493 return -EINVAL;
2494
2495 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2496 if (cmd == NULL)
2497 return -ENOMEM;
2498
2499 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2500 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2501 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
a66098da
LB		 2502
2503 hdrlen = ieee80211_hdrlen(payload->frame_control);
2504
2505 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2506
2507 /* XXX TBD Might just have to abort and return an error */
2508 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2509 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
c2c357ce
LB		 2510 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2511 payload_len, MWL8K_FJ_BEACON_MAXLEN);
a66098da 2512
ce9e2e1b
LB		 2513 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2514 payload_len = MWL8K_FJ_BEACON_MAXLEN;
a66098da
LB		 2515
2516 if (payload && payload_len)
2517 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2518
2519 rc = mwl8k_post_cmd(hw, &cmd->header);
2520 kfree(cmd);
2521 return rc;
2522}
2523
2524/*
2525 * CMD_UPDATE_STADB.
2526 */
2527struct mwl8k_cmd_update_sta_db {
2528 struct mwl8k_cmd_pkt header;
2529
2530 /* See STADB_ACTION_TYPE */
2531 __le32 action;
2532
2533 /* Peer MAC address */
d89173f2 2534 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2535
2536 __le32 reserved;
2537
2538 /* Peer info - valid during add/update. */
2539 struct peer_capability_info peer_info;
2540} __attribute__((packed));
2541
2542static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2543 struct ieee80211_vif *vif, __u32 action)
2544{
2545 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2546 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2547 struct mwl8k_cmd_update_sta_db *cmd;
2548 struct peer_capability_info *peer_info;
a66098da 2549 int rc;
a66098da
LB		 2550
2551 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2552 if (cmd == NULL)
2553 return -ENOMEM;
2554
2555 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2556 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2557
2558 cmd->action = cpu_to_le32(action);
2559 peer_info = &cmd->peer_info;
d89173f2 2560 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2561
2562 switch (action) {
2563 case MWL8K_STA_DB_ADD_ENTRY:
2564 case MWL8K_STA_DB_MODIFY_ENTRY:
2565 /* Build peer_info block */
2566 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2567 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
140eb5e2
LB		 2568 memcpy(peer_info->legacy_rates, mwl8k_rateids,
2569 sizeof(mwl8k_rateids));
a66098da
LB		 2570 peer_info->interop = 1;
2571 peer_info->amsdu_enabled = 0;
2572
a66098da
LB		 2573 rc = mwl8k_post_cmd(hw, &cmd->header);
2574 if (rc == 0)
2575 mv_vif->peer_id = peer_info->station_id;
2576
2577 break;
2578
2579 case MWL8K_STA_DB_DEL_ENTRY:
2580 case MWL8K_STA_DB_FLUSH:
2581 default:
2582 rc = mwl8k_post_cmd(hw, &cmd->header);
2583 if (rc == 0)
2584 mv_vif->peer_id = 0;
2585 break;
2586 }
2587 kfree(cmd);
2588
2589 return rc;
2590}
2591
2592/*
2593 * CMD_SET_AID.
2594 */
a66098da
LB		 2595#define MWL8K_FRAME_PROT_DISABLED 0x00
2596#define MWL8K_FRAME_PROT_11G 0x07
2597#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2598#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2599
2600struct mwl8k_cmd_update_set_aid {
2601 struct mwl8k_cmd_pkt header;
2602 __le16 aid;
2603
2604 /* AP's MAC address (BSSID) */
d89173f2 2605 __u8 bssid[ETH_ALEN];
a66098da 2606 __le16 protection_mode;
140eb5e2 2607 __u8 supp_rates[14];
a66098da
LB		 2608} __attribute__((packed));
2609
2610static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2611 struct ieee80211_vif *vif)
2612{
2613 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2614 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2615 struct mwl8k_cmd_update_set_aid *cmd;
a66098da
LB		 2616 u16 prot_mode;
2617 int rc;
2618
2619 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2620 if (cmd == NULL)
2621 return -ENOMEM;
2622
2623 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2624 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2625 cmd->aid = cpu_to_le16(info->aid);
2626
d89173f2 2627 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da 2628
a66098da
LB		 2629 if (info->use_cts_prot) {
2630 prot_mode = MWL8K_FRAME_PROT_11G;
2631 } else {
9ed6bcce 2632 switch (info->ht_operation_mode &
a66098da
LB		 2633 IEEE80211_HT_OP_MODE_PROTECTION) {
2634 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2635 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2636 break;
2637 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2638 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2639 break;
2640 default:
2641 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2642 break;
2643 }
2644 }
a66098da
LB		 2645 cmd->protection_mode = cpu_to_le16(prot_mode);
2646
140eb5e2 2647 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
a66098da
LB		 2648
2649 rc = mwl8k_post_cmd(hw, &cmd->header);
2650 kfree(cmd);
2651
2652 return rc;
2653}
2654
2655/*
2656 * CMD_SET_RATE.
2657 */
2658struct mwl8k_cmd_update_rateset {
2659 struct mwl8k_cmd_pkt header;
140eb5e2 2660 __u8 legacy_rates[14];
a66098da
LB		 2661
2662 /* Bitmap for supported MCS codes. */
0b5351a8
LB		 2663 __u8 mcs_set[16];
2664 __u8 reserved[16];
a66098da
LB		 2665} __attribute__((packed));
2666
2667static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2668 struct ieee80211_vif *vif)
2669{
a66098da 2670 struct mwl8k_cmd_update_rateset *cmd;
a66098da
LB		 2671 int rc;
2672
2673 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2674 if (cmd == NULL)
2675 return -ENOMEM;
2676
2677 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2678 cmd->header.length = cpu_to_le16(sizeof(*cmd));
140eb5e2 2679 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
a66098da
LB		 2680
2681 rc = mwl8k_post_cmd(hw, &cmd->header);
2682 kfree(cmd);
2683
2684 return rc;
2685}
2686
2687/*
2688 * CMD_USE_FIXED_RATE.
2689 */
2690#define MWL8K_RATE_TABLE_SIZE 8
2691#define MWL8K_UCAST_RATE 0
a66098da
LB		 2692#define MWL8K_USE_AUTO_RATE 0x0002
2693
2694struct mwl8k_rate_entry {
2695 /* Set to 1 if HT rate, 0 if legacy. */
2696 __le32 is_ht_rate;
2697
2698 /* Set to 1 to use retry_count field. */
2699 __le32 enable_retry;
2700
2701 /* Specified legacy rate or MCS. */
2702 __le32 rate;
2703
2704 /* Number of allowed retries. */
2705 __le32 retry_count;
2706} __attribute__((packed));
2707
2708struct mwl8k_rate_table {
2709 /* 1 to allow specified rate and below */
2710 __le32 allow_rate_drop;
2711 __le32 num_rates;
2712 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2713} __attribute__((packed));
2714
2715struct mwl8k_cmd_use_fixed_rate {
2716 struct mwl8k_cmd_pkt header;
2717 __le32 action;
2718 struct mwl8k_rate_table rate_table;
2719
2720 /* Unicast, Broadcast or Multicast */
2721 __le32 rate_type;
2722 __le32 reserved1;
2723 __le32 reserved2;
2724} __attribute__((packed));
2725
2726static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2727 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2728{
2729 struct mwl8k_cmd_use_fixed_rate *cmd;
2730 int count;
2731 int rc;
2732
2733 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2734 if (cmd == NULL)
2735 return -ENOMEM;
2736
2737 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2738 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2739
2740 cmd->action = cpu_to_le32(action);
2741 cmd->rate_type = cpu_to_le32(rate_type);
2742
2743 if (rate_table != NULL) {
c2c357ce
LB		 2744 /*
2745 * Copy over each field manually so that endian
2746 * conversion can be done.
2747 */
a66098da
LB		 2748 cmd->rate_table.allow_rate_drop =
2749 cpu_to_le32(rate_table->allow_rate_drop);
2750 cmd->rate_table.num_rates =
2751 cpu_to_le32(rate_table->num_rates);
2752
2753 for (count = 0; count < rate_table->num_rates; count++) {
2754 struct mwl8k_rate_entry *dst =
2755 &cmd->rate_table.rate_entry[count];
2756 struct mwl8k_rate_entry *src =
2757 &rate_table->rate_entry[count];
2758
2759 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2760 dst->enable_retry = cpu_to_le32(src->enable_retry);
2761 dst->rate = cpu_to_le32(src->rate);
2762 dst->retry_count = cpu_to_le32(src->retry_count);
2763 }
2764 }
2765
2766 rc = mwl8k_post_cmd(hw, &cmd->header);
2767 kfree(cmd);
2768
2769 return rc;
2770}
2771
2772
2773/*
2774 * Interrupt handling.
2775 */
2776static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2777{
2778 struct ieee80211_hw *hw = dev_id;
2779 struct mwl8k_priv *priv = hw->priv;
2780 u32 status;
2781
2782 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2783 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2784
a66098da
LB		 2785 if (!status)
2786 return IRQ_NONE;
2787
2788 if (status & MWL8K_A2H_INT_TX_DONE)
2789 tasklet_schedule(&priv->tx_reclaim_task);
2790
2791 if (status & MWL8K_A2H_INT_RX_READY) {
2792 while (rxq_process(hw, 0, 1))
2793 rxq_refill(hw, 0, 1);
2794 }
2795
2796 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2797 if (priv->hostcmd_wait != NULL)
a66098da 2798 complete(priv->hostcmd_wait);
a66098da
LB		 2799 }
2800
2801 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2802 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2803 priv->radio_on && priv->pending_tx_pkts)
618952a7 2804 mwl8k_tx_start(priv);
a66098da
LB		 2805 }
2806
2807 return IRQ_HANDLED;
2808}
2809
2810
2811/*
2812 * Core driver operations.
2813 */
2814static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2815{
2816 struct mwl8k_priv *priv = hw->priv;
2817 int index = skb_get_queue_mapping(skb);
2818 int rc;
2819
2820 if (priv->current_channel == NULL) {
2821 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 2822 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 2823 dev_kfree_skb(skb);
2824 return NETDEV_TX_OK;
2825 }
2826
2827 rc = mwl8k_txq_xmit(hw, index, skb);
2828
2829 return rc;
2830}
2831
a66098da
LB		 2832static int mwl8k_start(struct ieee80211_hw *hw)
2833{
a66098da
LB		 2834 struct mwl8k_priv *priv = hw->priv;
2835 int rc;
2836
a0607fd3 2837 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 2838 IRQF_SHARED, MWL8K_NAME, hw);
2839 if (rc) {
2840 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2841 wiphy_name(hw->wiphy));
2ec610cb 2842 return -EIO;
a66098da
LB		 2843 }
2844
2ec610cb
LB		 2845 /* Enable tx reclaim tasklet */
2846 tasklet_enable(&priv->tx_reclaim_task);
2847
a66098da 2848 /* Enable interrupts */
c23b5a69 2849 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 2850
2ec610cb
LB		 2851 rc = mwl8k_fw_lock(hw);
2852 if (!rc) {
2853 rc = mwl8k_cmd_802_11_radio_enable(hw);
a66098da 2854
5e4cf166
LB		 2855 if (!priv->ap_fw) {
2856 if (!rc)
2857 rc = mwl8k_enable_sniffer(hw, 0);
a66098da 2858
5e4cf166
LB		 2859 if (!rc)
2860 rc = mwl8k_cmd_set_pre_scan(hw);
2861
2862 if (!rc)
2863 rc = mwl8k_cmd_set_post_scan(hw,
2864 "\x00\x00\x00\x00\x00\x00");
2865 }
2ec610cb
LB		 2866
2867 if (!rc)
2868 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
a66098da 2869
2ec610cb
LB		 2870 if (!rc)
2871 rc = mwl8k_set_wmm(hw, 0);
a66098da 2872
2ec610cb
LB		 2873 mwl8k_fw_unlock(hw);
2874 }
2875
2876 if (rc) {
2877 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2878 free_irq(priv->pdev->irq, hw);
2879 tasklet_disable(&priv->tx_reclaim_task);
2880 }
a66098da
LB		 2881
2882 return rc;
2883}
2884
a66098da
LB		 2885static void mwl8k_stop(struct ieee80211_hw *hw)
2886{
a66098da
LB		 2887 struct mwl8k_priv *priv = hw->priv;
2888 int i;
2889
d3cea0b8 2890 mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 2891
2892 ieee80211_stop_queues(hw);
2893
a66098da 2894 /* Disable interrupts */
a66098da 2895 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2896 free_irq(priv->pdev->irq, hw);
2897
2898 /* Stop finalize join worker */
2899 cancel_work_sync(&priv->finalize_join_worker);
2900 if (priv->beacon_skb != NULL)
2901 dev_kfree_skb(priv->beacon_skb);
2902
2903 /* Stop tx reclaim tasklet */
2904 tasklet_disable(&priv->tx_reclaim_task);
2905
a66098da
LB		 2906 /* Return all skbs to mac80211 */
2907 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2908 mwl8k_txq_reclaim(hw, i, 1);
2909}
2910
2911static int mwl8k_add_interface(struct ieee80211_hw *hw,
2912 struct ieee80211_if_init_conf *conf)
2913{
2914 struct mwl8k_priv *priv = hw->priv;
2915 struct mwl8k_vif *mwl8k_vif;
2916
2917 /*
2918 * We only support one active interface at a time.
2919 */
2920 if (priv->vif != NULL)
2921 return -EBUSY;
2922
2923 /*
2924 * We only support managed interfaces for now.
2925 */
240e86ef 2926 if (conf->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2927 return -EINVAL;
2928
a43c49a8
LB		 2929 /*
2930 * Reject interface creation if sniffer mode is active, as
2931 * STA operation is mutually exclusive with hardware sniffer
2932 * mode.
2933 */
2934 if (priv->sniffer_enabled) {
2935 printk(KERN_INFO "%s: unable to create STA "
2936 "interface due to sniffer mode being enabled\n",
2937 wiphy_name(hw->wiphy));
2938 return -EINVAL;
2939 }
2940
a66098da
LB		 2941 /* Clean out driver private area */
2942 mwl8k_vif = MWL8K_VIF(conf->vif);
2943 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2944
32060e1b
LB		 2945 /* Set and save the mac address */
2946 mwl8k_set_mac_addr(hw, conf->mac_addr);
d89173f2 2947 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2948
2949 /* Back pointer to parent config block */
2950 mwl8k_vif->priv = priv;
2951
a66098da
LB		 2952 /* Set Initial sequence number to zero */
2953 mwl8k_vif->seqno = 0;
2954
2955 priv->vif = conf->vif;
2956 priv->current_channel = NULL;
2957
2958 return 0;
2959}
2960
2961static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2962 struct ieee80211_if_init_conf *conf)
2963{
2964 struct mwl8k_priv *priv = hw->priv;
2965
2966 if (priv->vif == NULL)
2967 return;
2968
32060e1b
LB		 2969 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2970
a66098da
LB		 2971 priv->vif = NULL;
2972}
2973
ee03a932 2974static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 2975{
a66098da
LB		 2976 struct ieee80211_conf *conf = &hw->conf;
2977 struct mwl8k_priv *priv = hw->priv;
ee03a932 2978 int rc;
a66098da 2979
7595d67a
LB		 2980 if (conf->flags & IEEE80211_CONF_IDLE) {
2981 mwl8k_cmd_802_11_radio_disable(hw);
2982 priv->current_channel = NULL;
ee03a932 2983 return 0;
7595d67a
LB		 2984 }
2985
ee03a932
LB		 2986 rc = mwl8k_fw_lock(hw);
2987 if (rc)
2988 return rc;
a66098da 2989
ee03a932
LB		 2990 rc = mwl8k_cmd_802_11_radio_enable(hw);
2991 if (rc)
2992 goto out;
a66098da 2993
ee03a932
LB		 2994 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2995 if (rc)
2996 goto out;
2997
2998 priv->current_channel = conf->channel;
a66098da
LB		 2999
3000 if (conf->power_level > 18)
3001 conf->power_level = 18;
ee03a932
LB		 3002 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
3003 if (rc)
3004 goto out;
a66098da 3005
08b06347
LB		 3006 if (priv->ap_fw) {
3007 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
3008 if (!rc)
3009 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
3010 } else {
3011 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
3012 }
a66098da 3013
ee03a932
LB		 3014out:
3015 mwl8k_fw_unlock(hw);
a66098da 3016
ee03a932 3017 return rc;
a66098da
LB		 3018}
3019
3a980d0a
LB		 3020static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
3021 struct ieee80211_vif *vif,
3022 struct ieee80211_bss_conf *info,
3023 u32 changed)
a66098da 3024{
a66098da
LB		 3025 struct mwl8k_priv *priv = hw->priv;
3026 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3a980d0a
LB		 3027 int rc;
3028
3029 if (changed & BSS_CHANGED_BSSID)
3030 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
3031
3032 if ((changed & BSS_CHANGED_ASSOC) == 0)
3033 return;
a66098da 3034
a66098da
LB		 3035 priv->capture_beacon = false;
3036
3a980d0a 3037 rc = mwl8k_fw_lock(hw);
942457d6 3038 if (rc)
3a980d0a
LB		 3039 return;
3040
a66098da
LB		 3041 if (info->assoc) {
3042 memcpy(&mwl8k_vif->bss_info, info,
3043 sizeof(struct ieee80211_bss_conf));
3044
3045 /* Install rates */
3a980d0a
LB		 3046 rc = mwl8k_update_rateset(hw, vif);
3047 if (rc)
3048 goto out;
a66098da
LB		 3049
3050 /* Turn on rate adaptation */
3a980d0a
LB		 3051 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
3052 MWL8K_UCAST_RATE, NULL);
3053 if (rc)
3054 goto out;
a66098da
LB		 3055
3056 /* Set radio preamble */
3a980d0a
LB		 3057 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
3058 if (rc)
3059 goto out;
a66098da
LB		 3060
3061 /* Set slot time */
3a980d0a
LB		 3062 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
3063 if (rc)
3064 goto out;
a66098da
LB		 3065
3066 /* Update peer rate info */
3a980d0a
LB		 3067 rc = mwl8k_cmd_update_sta_db(hw, vif,
3068 MWL8K_STA_DB_MODIFY_ENTRY);
3069 if (rc)
3070 goto out;
a66098da
LB		 3071
3072 /* Set AID */
3a980d0a
LB		 3073 rc = mwl8k_cmd_set_aid(hw, vif);
3074 if (rc)
3075 goto out;
a66098da
LB		 3076
3077 /*
3078 * Finalize the join. Tell rx handler to process
3079 * next beacon from our BSSID.
3080 */
d89173f2 3081 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 3082 priv->capture_beacon = true;
3083 } else {
3a980d0a 3084 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
a66098da
LB		 3085 memset(&mwl8k_vif->bss_info, 0,
3086 sizeof(struct ieee80211_bss_conf));
d89173f2 3087 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 3088 }
3089
3a980d0a
LB		 3090out:
3091 mwl8k_fw_unlock(hw);
a66098da
LB		 3092}
3093
e81cd2d6
LB		 3094static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3095 int mc_count, struct dev_addr_list *mclist)
3096{
3097 struct mwl8k_cmd_pkt *cmd;
3098
447ced07
LB		 3099 /*
3100 * Synthesize and return a command packet that programs the
3101 * hardware multicast address filter. At this point we don't
3102 * know whether FIF_ALLMULTI is being requested, but if it is,
3103 * we'll end up throwing this packet away and creating a new
3104 * one in mwl8k_configure_filter().
3105 */
3106 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 3107
3108 return (unsigned long)cmd;
3109}
3110
a43c49a8
LB		 3111static int
3112mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3113 unsigned int changed_flags,
3114 unsigned int *total_flags)
3115{
3116 struct mwl8k_priv *priv = hw->priv;
3117
3118 /*
3119 * Hardware sniffer mode is mutually exclusive with STA
3120 * operation, so refuse to enable sniffer mode if a STA
3121 * interface is active.
3122 */
3123 if (priv->vif != NULL) {
3124 if (net_ratelimit())
3125 printk(KERN_INFO "%s: not enabling sniffer "
3126 "mode because STA interface is active\n",
3127 wiphy_name(hw->wiphy));
3128 return 0;
3129 }
3130
3131 if (!priv->sniffer_enabled) {
3132 if (mwl8k_enable_sniffer(hw, 1))
3133 return 0;
3134 priv->sniffer_enabled = true;
3135 }
3136
3137 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3138 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3139 FIF_OTHER_BSS;
3140
3141 return 1;
3142}
3143
e6935ea1
LB		 3144static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3145 unsigned int changed_flags,
3146 unsigned int *total_flags,
3147 u64 multicast)
3148{
3149 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3150 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3151
c0adae2c
LB		 3152 /*
3153 * AP firmware doesn't allow fine-grained control over
3154 * the receive filter.
3155 */
3156 if (priv->ap_fw) {
3157 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3158 kfree(cmd);
3159 return;
3160 }
3161
a43c49a8
LB		 3162 /*
3163 * Enable hardware sniffer mode if FIF_CONTROL or
3164 * FIF_OTHER_BSS is requested.
3165 */
3166 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3167 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3168 kfree(cmd);
3169 return;
3170 }
a66098da 3171
e6935ea1 3172 /* Clear unsupported feature flags */
447ced07 3173 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3174
e6935ea1
LB		 3175 if (mwl8k_fw_lock(hw))
3176 return;
a66098da 3177
a43c49a8
LB		 3178 if (priv->sniffer_enabled) {
3179 mwl8k_enable_sniffer(hw, 0);
3180 priv->sniffer_enabled = false;
3181 }
3182
e6935ea1 3183 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3184 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3185 /*
3186 * Disable the BSS filter.
3187 */
e6935ea1 3188 mwl8k_cmd_set_pre_scan(hw);
77165d88 3189 } else {
a94cc97e
LB		 3190 u8 *bssid;
3191
77165d88
LB		 3192 /*
3193 * Enable the BSS filter.
3194 *
3195 * If there is an active STA interface, use that
3196 * interface's BSSID, otherwise use a dummy one
3197 * (where the OUI part needs to be nonzero for
3198 * the BSSID to be accepted by POST_SCAN).
3199 */
3200 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e
LB		 3201 if (priv->vif != NULL)
3202 bssid = MWL8K_VIF(priv->vif)->bssid;
3203
e6935ea1 3204 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3205 }
3206 }
3207
447ced07
LB		 3208 /*
3209 * If FIF_ALLMULTI is being requested, throw away the command
3210 * packet that ->prepare_multicast() built and replace it with
3211 * a command packet that enables reception of all multicast
3212 * packets.
3213 */
3214 if (*total_flags & FIF_ALLMULTI) {
3215 kfree(cmd);
3216 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3217 }
3218
3219 if (cmd != NULL) {
3220 mwl8k_post_cmd(hw, cmd);
3221 kfree(cmd);
e6935ea1 3222 }
a66098da 3223
e6935ea1 3224 mwl8k_fw_unlock(hw);
a66098da
LB		 3225}
3226
a66098da
LB		 3227static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3228{
733d3067 3229 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
a66098da
LB		 3230}
3231
a66098da
LB		 3232static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3233 const struct ieee80211_tx_queue_params *params)
3234{
3e4f542c 3235 struct mwl8k_priv *priv = hw->priv;
a66098da 3236 int rc;
a66098da 3237
3e4f542c
LB		 3238 rc = mwl8k_fw_lock(hw);
3239 if (!rc) {
3240 if (!priv->wmm_enabled)
3241 rc = mwl8k_set_wmm(hw, 1);
a66098da 3242
3e4f542c
LB		 3243 if (!rc)
3244 rc = mwl8k_set_edca_params(hw, queue,
3245 params->cw_min,
3246 params->cw_max,
3247 params->aifs,
3248 params->txop);
3249
3250 mwl8k_fw_unlock(hw);
a66098da 3251 }
3e4f542c 3252
a66098da
LB		 3253 return rc;
3254}
3255
3256static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3257 struct ieee80211_tx_queue_stats *stats)
3258{
3259 struct mwl8k_priv *priv = hw->priv;
3260 struct mwl8k_tx_queue *txq;
3261 int index;
3262
3263 spin_lock_bh(&priv->tx_lock);
3264 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3265 txq = priv->txq + index;
45eb400d 3266 memcpy(&stats[index], &txq->stats,
a66098da
LB		 3267 sizeof(struct ieee80211_tx_queue_stats));
3268 }
3269 spin_unlock_bh(&priv->tx_lock);
a66098da 3270
954ef509 3271 return 0;
a66098da
LB		 3272}
3273
3274static int mwl8k_get_stats(struct ieee80211_hw *hw,
3275 struct ieee80211_low_level_stats *stats)
3276{
954ef509 3277 return mwl8k_cmd_802_11_get_stat(hw, stats);
a66098da
LB		 3278}
3279
3280static const struct ieee80211_ops mwl8k_ops = {
3281 .tx = mwl8k_tx,
3282 .start = mwl8k_start,
3283 .stop = mwl8k_stop,
3284 .add_interface = mwl8k_add_interface,
3285 .remove_interface = mwl8k_remove_interface,
3286 .config = mwl8k_config,
a66098da 3287 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3288 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3289 .configure_filter = mwl8k_configure_filter,
3290 .set_rts_threshold = mwl8k_set_rts_threshold,
3291 .conf_tx = mwl8k_conf_tx,
3292 .get_tx_stats = mwl8k_get_tx_stats,
3293 .get_stats = mwl8k_get_stats,
3294};
3295
3296static void mwl8k_tx_reclaim_handler(unsigned long data)
3297{
3298 int i;
3299 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3300 struct mwl8k_priv *priv = hw->priv;
3301
3302 spin_lock_bh(&priv->tx_lock);
3303 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3304 mwl8k_txq_reclaim(hw, i, 0);
3305
88de754a 3306 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
ce9e2e1b
LB		 3307 complete(priv->tx_wait);
3308 priv->tx_wait = NULL;
a66098da
LB		 3309 }
3310 spin_unlock_bh(&priv->tx_lock);
3311}
3312
3313static void mwl8k_finalize_join_worker(struct work_struct *work)
3314{
3315 struct mwl8k_priv *priv =
3316 container_of(work, struct mwl8k_priv, finalize_join_worker);
3317 struct sk_buff *skb = priv->beacon_skb;
ce9e2e1b 3318 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
a66098da
LB		 3319
3320 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3321 dev_kfree_skb(skb);
3322
3323 priv->beacon_skb = NULL;
3324}
3325
bcb628d5
JL		 3326enum {
3327 MWL8687 = 0,
3328 MWL8366,
6f6d1e9a
LB		 3329};
3330
bcb628d5
JL		 3331static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3332 {
3333 .part_name = "88w8687",
3334 .helper_image = "mwl8k/helper_8687.fw",
3335 .fw_image = "mwl8k/fmimage_8687.fw",
3336 .rxd_ops = &rxd_8687_ops,
3337 .modes = BIT(NL80211_IFTYPE_STATION),
3338 },
3339 {
3340 .part_name = "88w8366",
3341 .helper_image = "mwl8k/helper_8366.fw",
3342 .fw_image = "mwl8k/fmimage_8366.fw",
3343 .rxd_ops = &rxd_8366_ops,
3344 .modes = 0,
3345 },
45a390dd
LB		 3346};
3347
3348static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
bcb628d5
JL		 3349 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3350 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3351 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3352 { },
45a390dd
LB		 3353};
3354MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3355
a66098da
LB		 3356static int __devinit mwl8k_probe(struct pci_dev *pdev,
3357 const struct pci_device_id *id)
3358{
2aa7b01f 3359 static int printed_version = 0;
a66098da
LB		 3360 struct ieee80211_hw *hw;
3361 struct mwl8k_priv *priv;
a66098da
LB		 3362 int rc;
3363 int i;
2aa7b01f
LB		 3364
3365 if (!printed_version) {
3366 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3367 printed_version = 1;
3368 }
a66098da
LB		 3369
3370 rc = pci_enable_device(pdev);
3371 if (rc) {
3372 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3373 MWL8K_NAME);
3374 return rc;
3375 }
3376
3377 rc = pci_request_regions(pdev, MWL8K_NAME);
3378 if (rc) {
3379 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3380 MWL8K_NAME);
3381 return rc;
3382 }
3383
3384 pci_set_master(pdev);
3385
3386 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3387 if (hw == NULL) {
3388 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3389 rc = -ENOMEM;
3390 goto err_free_reg;
3391 }
3392
3393 priv = hw->priv;
3394 priv->hw = hw;
3395 priv->pdev = pdev;
bcb628d5 3396 priv->device_info = &mwl8k_info_tbl[id->driver_data];
54bc3a0d 3397 priv->rxd_ops = priv->device_info->rxd_ops;
a43c49a8 3398 priv->sniffer_enabled = false;
0439b1f5 3399 priv->wmm_enabled = false;
a66098da 3400 priv->pending_tx_pkts = 0;
a66098da 3401
a66098da
LB		 3402 SET_IEEE80211_DEV(hw, &pdev->dev);
3403 pci_set_drvdata(pdev, hw);
3404
5b9482dd
LB		 3405 priv->sram = pci_iomap(pdev, 0, 0x10000);
3406 if (priv->sram == NULL) {
3407 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3408 wiphy_name(hw->wiphy));
a66098da
LB		 3409 goto err_iounmap;
3410 }
3411
5b9482dd
LB		 3412 /*
3413 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3414 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3415 */
3416 priv->regs = pci_iomap(pdev, 1, 0x10000);
3417 if (priv->regs == NULL) {
3418 priv->regs = pci_iomap(pdev, 2, 0x10000);
3419 if (priv->regs == NULL) {
3420 printk(KERN_ERR "%s: Cannot map device registers\n",
3421 wiphy_name(hw->wiphy));
3422 goto err_iounmap;
3423 }
3424 }
3425
a66098da
LB		 3426 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3427 priv->band.band = IEEE80211_BAND_2GHZ;
3428 priv->band.channels = priv->channels;
3429 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3430 priv->band.bitrates = priv->rates;
3431 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3432 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3433
3434 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3435 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3436
3437 /*
3438 * Extra headroom is the size of the required DMA header
3439 * minus the size of the smallest 802.11 frame (CTS frame).
3440 */
3441 hw->extra_tx_headroom =
3442 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3443
3444 hw->channel_change_time = 10;
3445
3446 hw->queues = MWL8K_TX_QUEUES;
3447
547810e3 3448 hw->wiphy->interface_modes = priv->device_info->modes;
a66098da
LB		 3449
3450 /* Set rssi and noise values to dBm */
ce9e2e1b 3451 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da
LB		 3452 hw->vif_data_size = sizeof(struct mwl8k_vif);
3453 priv->vif = NULL;
3454
3455 /* Set default radio state and preamble */
c46563b7 3456 priv->radio_on = 0;
68ce3884 3457 priv->radio_short_preamble = 0;
a66098da
LB		 3458
3459 /* Finalize join worker */
3460 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3461
3462 /* TX reclaim tasklet */
3463 tasklet_init(&priv->tx_reclaim_task,
3464 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3465 tasklet_disable(&priv->tx_reclaim_task);
3466
a66098da
LB		 3467 /* Power management cookie */
3468 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3469 if (priv->cookie == NULL)
3470 goto err_iounmap;
3471
3472 rc = mwl8k_rxq_init(hw, 0);
3473 if (rc)
3474 goto err_iounmap;
3475 rxq_refill(hw, 0, INT_MAX);
3476
618952a7
LB		 3477 mutex_init(&priv->fw_mutex);
3478 priv->fw_mutex_owner = NULL;
3479 priv->fw_mutex_depth = 0;
618952a7
LB		 3480 priv->hostcmd_wait = NULL;
3481
a66098da
LB		 3482 spin_lock_init(&priv->tx_lock);
3483
88de754a
LB		 3484 priv->tx_wait = NULL;
3485
a66098da
LB		 3486 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3487 rc = mwl8k_txq_init(hw, i);
3488 if (rc)
3489 goto err_free_queues;
3490 }
3491
3492 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3493 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3494 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3495 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3496
a0607fd3 3497 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3498 IRQF_SHARED, MWL8K_NAME, hw);
3499 if (rc) {
3500 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3501 wiphy_name(hw->wiphy));
a66098da
LB		 3502 goto err_free_queues;
3503 }
3504
3505 /* Reset firmware and hardware */
3506 mwl8k_hw_reset(priv);
3507
3508 /* Ask userland hotplug daemon for the device firmware */
45a390dd 3509 rc = mwl8k_request_firmware(priv);
a66098da 3510 if (rc) {
c2c357ce
LB		 3511 printk(KERN_ERR "%s: Firmware files not found\n",
3512 wiphy_name(hw->wiphy));
a66098da
LB		 3513 goto err_free_irq;
3514 }
3515
3516 /* Load firmware into hardware */
c2c357ce 3517 rc = mwl8k_load_firmware(hw);
a66098da 3518 if (rc) {
c2c357ce
LB		 3519 printk(KERN_ERR "%s: Cannot start firmware\n",
3520 wiphy_name(hw->wiphy));
a66098da
LB		 3521 goto err_stop_firmware;
3522 }
3523
3524 /* Reclaim memory once firmware is successfully loaded */
3525 mwl8k_release_firmware(priv);
3526
3527 /*
3528 * Temporarily enable interrupts. Initial firmware host
3529 * commands use interrupts and avoids polling. Disable
3530 * interrupts when done.
3531 */
c23b5a69 3532 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3533
3534 /* Get config data, mac addrs etc */
42fba21d
LB		 3535 if (priv->ap_fw) {
3536 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3537 if (!rc)
3538 rc = mwl8k_cmd_set_hw_spec(hw);
3539 } else {
3540 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3541 }
a66098da 3542 if (rc) {
c2c357ce
LB		 3543 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3544 wiphy_name(hw->wiphy));
a66098da
LB		 3545 goto err_stop_firmware;
3546 }
3547
3548 /* Turn radio off */
c46563b7 3549 rc = mwl8k_cmd_802_11_radio_disable(hw);
a66098da 3550 if (rc) {
c2c357ce 3551 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
a66098da
LB		 3552 goto err_stop_firmware;
3553 }
3554
32060e1b
LB		 3555 /* Clear MAC address */
3556 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3557 if (rc) {
3558 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3559 wiphy_name(hw->wiphy));
3560 goto err_stop_firmware;
3561 }
3562
a66098da 3563 /* Disable interrupts */
a66098da 3564 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3565 free_irq(priv->pdev->irq, hw);
3566
3567 rc = ieee80211_register_hw(hw);
3568 if (rc) {
c2c357ce
LB		 3569 printk(KERN_ERR "%s: Cannot register device\n",
3570 wiphy_name(hw->wiphy));
a66098da
LB		 3571 goto err_stop_firmware;
3572 }
3573
eae74e65 3574 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3575 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3576 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3577 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 3578 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3579 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3580
3581 return 0;
3582
3583err_stop_firmware:
3584 mwl8k_hw_reset(priv);
3585 mwl8k_release_firmware(priv);
3586
3587err_free_irq:
a66098da 3588 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3589 free_irq(priv->pdev->irq, hw);
3590
3591err_free_queues:
3592 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3593 mwl8k_txq_deinit(hw, i);
3594 mwl8k_rxq_deinit(hw, 0);
3595
3596err_iounmap:
3597 if (priv->cookie != NULL)
3598 pci_free_consistent(priv->pdev, 4,
3599 priv->cookie, priv->cookie_dma);
3600
3601 if (priv->regs != NULL)
3602 pci_iounmap(pdev, priv->regs);
3603
5b9482dd
LB		 3604 if (priv->sram != NULL)
3605 pci_iounmap(pdev, priv->sram);
3606
a66098da
LB		 3607 pci_set_drvdata(pdev, NULL);
3608 ieee80211_free_hw(hw);
3609
3610err_free_reg:
3611 pci_release_regions(pdev);
3612 pci_disable_device(pdev);
3613
3614 return rc;
3615}
3616
230f7af0 3617static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3618{
3619 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3620}
3621
230f7af0 3622static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3623{
3624 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3625 struct mwl8k_priv *priv;
3626 int i;
3627
3628 if (hw == NULL)
3629 return;
3630 priv = hw->priv;
3631
3632 ieee80211_stop_queues(hw);
3633
60aa569f
LB		 3634 ieee80211_unregister_hw(hw);
3635
a66098da
LB		 3636 /* Remove tx reclaim tasklet */
3637 tasklet_kill(&priv->tx_reclaim_task);
3638
a66098da
LB		 3639 /* Stop hardware */
3640 mwl8k_hw_reset(priv);
3641
3642 /* Return all skbs to mac80211 */
3643 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3644 mwl8k_txq_reclaim(hw, i, 1);
3645
a66098da
LB		 3646 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3647 mwl8k_txq_deinit(hw, i);
3648
3649 mwl8k_rxq_deinit(hw, 0);
3650
c2c357ce 3651 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 3652
3653 pci_iounmap(pdev, priv->regs);
5b9482dd 3654 pci_iounmap(pdev, priv->sram);
a66098da
LB		 3655 pci_set_drvdata(pdev, NULL);
3656 ieee80211_free_hw(hw);
3657 pci_release_regions(pdev);
3658 pci_disable_device(pdev);
3659}
3660
3661static struct pci_driver mwl8k_driver = {
3662 .name = MWL8K_NAME,
45a390dd 3663 .id_table = mwl8k_pci_id_table,
a66098da
LB		 3664 .probe = mwl8k_probe,
3665 .remove = __devexit_p(mwl8k_remove),
3666 .shutdown = __devexit_p(mwl8k_shutdown),
3667};
3668
3669static int __init mwl8k_init(void)
3670{
3671 return pci_register_driver(&mwl8k_driver);
3672}
3673
3674static void __exit mwl8k_exit(void)
3675{
3676 pci_unregister_driver(&mwl8k_driver);
3677}
3678
3679module_init(mwl8k_init);
3680module_exit(mwl8k_exit);
c2c357ce
LB		 3681
3682MODULE_DESCRIPTION(MWL8K_DESC);
3683MODULE_VERSION(MWL8K_VERSION);
3684MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3685MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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